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00db8189 AF |
1 | /* |
2 | * drivers/net/phy/marvell.c | |
3 | * | |
4 | * Driver for Marvell PHYs | |
5 | * | |
6 | * Author: Andy Fleming | |
7 | * | |
8 | * Copyright (c) 2004 Freescale Semiconductor, Inc. | |
9 | * | |
3871c387 MS |
10 | * Copyright (c) 2013 Michael Stapelberg <michael@stapelberg.de> |
11 | * | |
00db8189 AF |
12 | * This program is free software; you can redistribute it and/or modify it |
13 | * under the terms of the GNU General Public License as published by the | |
14 | * Free Software Foundation; either version 2 of the License, or (at your | |
15 | * option) any later version. | |
16 | * | |
17 | */ | |
00db8189 | 18 | #include <linux/kernel.h> |
00db8189 AF |
19 | #include <linux/string.h> |
20 | #include <linux/errno.h> | |
21 | #include <linux/unistd.h> | |
00db8189 AF |
22 | #include <linux/interrupt.h> |
23 | #include <linux/init.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/netdevice.h> | |
26 | #include <linux/etherdevice.h> | |
27 | #include <linux/skbuff.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/mm.h> | |
30 | #include <linux/module.h> | |
00db8189 AF |
31 | #include <linux/mii.h> |
32 | #include <linux/ethtool.h> | |
33 | #include <linux/phy.h> | |
2f495c39 | 34 | #include <linux/marvell_phy.h> |
cf41a51d | 35 | #include <linux/of.h> |
00db8189 | 36 | |
eea3b201 | 37 | #include <linux/io.h> |
00db8189 | 38 | #include <asm/irq.h> |
eea3b201 | 39 | #include <linux/uaccess.h> |
00db8189 | 40 | |
27d916d6 DD |
41 | #define MII_MARVELL_PHY_PAGE 22 |
42 | ||
00db8189 AF |
43 | #define MII_M1011_IEVENT 0x13 |
44 | #define MII_M1011_IEVENT_CLEAR 0x0000 | |
45 | ||
46 | #define MII_M1011_IMASK 0x12 | |
47 | #define MII_M1011_IMASK_INIT 0x6400 | |
48 | #define MII_M1011_IMASK_CLEAR 0x0000 | |
49 | ||
76884679 AF |
50 | #define MII_M1011_PHY_SCR 0x10 |
51 | #define MII_M1011_PHY_SCR_AUTO_CROSS 0x0060 | |
52 | ||
53 | #define MII_M1145_PHY_EXT_CR 0x14 | |
54 | #define MII_M1145_RGMII_RX_DELAY 0x0080 | |
55 | #define MII_M1145_RGMII_TX_DELAY 0x0002 | |
56 | ||
76884679 AF |
57 | #define MII_M1111_PHY_LED_CONTROL 0x18 |
58 | #define MII_M1111_PHY_LED_DIRECT 0x4100 | |
59 | #define MII_M1111_PHY_LED_COMBINE 0x411c | |
895ee682 KP |
60 | #define MII_M1111_PHY_EXT_CR 0x14 |
61 | #define MII_M1111_RX_DELAY 0x80 | |
62 | #define MII_M1111_TX_DELAY 0x2 | |
63 | #define MII_M1111_PHY_EXT_SR 0x1b | |
be937f1f AS |
64 | |
65 | #define MII_M1111_HWCFG_MODE_MASK 0xf | |
66 | #define MII_M1111_HWCFG_MODE_COPPER_RGMII 0xb | |
67 | #define MII_M1111_HWCFG_MODE_FIBER_RGMII 0x3 | |
4117b5be | 68 | #define MII_M1111_HWCFG_MODE_SGMII_NO_CLK 0x4 |
5f8cbc13 | 69 | #define MII_M1111_HWCFG_MODE_COPPER_RTBI 0x9 |
be937f1f AS |
70 | #define MII_M1111_HWCFG_FIBER_COPPER_AUTO 0x8000 |
71 | #define MII_M1111_HWCFG_FIBER_COPPER_RES 0x2000 | |
72 | ||
73 | #define MII_M1111_COPPER 0 | |
74 | #define MII_M1111_FIBER 1 | |
75 | ||
c477d044 CC |
76 | #define MII_88E1121_PHY_MSCR_PAGE 2 |
77 | #define MII_88E1121_PHY_MSCR_REG 21 | |
78 | #define MII_88E1121_PHY_MSCR_RX_DELAY BIT(5) | |
79 | #define MII_88E1121_PHY_MSCR_TX_DELAY BIT(4) | |
80 | #define MII_88E1121_PHY_MSCR_DELAY_MASK (~(0x3 << 4)) | |
81 | ||
337ac9d5 CC |
82 | #define MII_88E1318S_PHY_MSCR1_REG 16 |
83 | #define MII_88E1318S_PHY_MSCR1_PAD_ODD BIT(6) | |
3ff1c259 | 84 | |
3871c387 MS |
85 | /* Copper Specific Interrupt Enable Register */ |
86 | #define MII_88E1318S_PHY_CSIER 0x12 | |
87 | /* WOL Event Interrupt Enable */ | |
88 | #define MII_88E1318S_PHY_CSIER_WOL_EIE BIT(7) | |
89 | ||
90 | /* LED Timer Control Register */ | |
91 | #define MII_88E1318S_PHY_LED_PAGE 0x03 | |
92 | #define MII_88E1318S_PHY_LED_TCR 0x12 | |
93 | #define MII_88E1318S_PHY_LED_TCR_FORCE_INT BIT(15) | |
94 | #define MII_88E1318S_PHY_LED_TCR_INTn_ENABLE BIT(7) | |
95 | #define MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW BIT(11) | |
96 | ||
97 | /* Magic Packet MAC address registers */ | |
98 | #define MII_88E1318S_PHY_MAGIC_PACKET_WORD2 0x17 | |
99 | #define MII_88E1318S_PHY_MAGIC_PACKET_WORD1 0x18 | |
100 | #define MII_88E1318S_PHY_MAGIC_PACKET_WORD0 0x19 | |
101 | ||
102 | #define MII_88E1318S_PHY_WOL_PAGE 0x11 | |
103 | #define MII_88E1318S_PHY_WOL_CTRL 0x10 | |
104 | #define MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS BIT(12) | |
105 | #define MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE BIT(14) | |
106 | ||
140bc929 SP |
107 | #define MII_88E1121_PHY_LED_CTRL 16 |
108 | #define MII_88E1121_PHY_LED_PAGE 3 | |
109 | #define MII_88E1121_PHY_LED_DEF 0x0030 | |
140bc929 | 110 | |
be937f1f AS |
111 | #define MII_M1011_PHY_STATUS 0x11 |
112 | #define MII_M1011_PHY_STATUS_1000 0x8000 | |
113 | #define MII_M1011_PHY_STATUS_100 0x4000 | |
114 | #define MII_M1011_PHY_STATUS_SPD_MASK 0xc000 | |
115 | #define MII_M1011_PHY_STATUS_FULLDUPLEX 0x2000 | |
116 | #define MII_M1011_PHY_STATUS_RESOLVED 0x0800 | |
117 | #define MII_M1011_PHY_STATUS_LINK 0x0400 | |
118 | ||
3da09a51 MS |
119 | #define MII_M1116R_CONTROL_REG_MAC 21 |
120 | ||
76884679 | 121 | |
00db8189 AF |
122 | MODULE_DESCRIPTION("Marvell PHY driver"); |
123 | MODULE_AUTHOR("Andy Fleming"); | |
124 | MODULE_LICENSE("GPL"); | |
125 | ||
126 | static int marvell_ack_interrupt(struct phy_device *phydev) | |
127 | { | |
128 | int err; | |
129 | ||
130 | /* Clear the interrupts by reading the reg */ | |
131 | err = phy_read(phydev, MII_M1011_IEVENT); | |
132 | ||
133 | if (err < 0) | |
134 | return err; | |
135 | ||
136 | return 0; | |
137 | } | |
138 | ||
139 | static int marvell_config_intr(struct phy_device *phydev) | |
140 | { | |
141 | int err; | |
142 | ||
76884679 | 143 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) |
00db8189 AF |
144 | err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_INIT); |
145 | else | |
146 | err = phy_write(phydev, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); | |
147 | ||
148 | return err; | |
149 | } | |
150 | ||
151 | static int marvell_config_aneg(struct phy_device *phydev) | |
152 | { | |
153 | int err; | |
154 | ||
155 | /* The Marvell PHY has an errata which requires | |
156 | * that certain registers get written in order | |
157 | * to restart autonegotiation */ | |
158 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); | |
159 | ||
160 | if (err < 0) | |
161 | return err; | |
162 | ||
163 | err = phy_write(phydev, 0x1d, 0x1f); | |
164 | if (err < 0) | |
165 | return err; | |
166 | ||
167 | err = phy_write(phydev, 0x1e, 0x200c); | |
168 | if (err < 0) | |
169 | return err; | |
170 | ||
171 | err = phy_write(phydev, 0x1d, 0x5); | |
172 | if (err < 0) | |
173 | return err; | |
174 | ||
175 | err = phy_write(phydev, 0x1e, 0); | |
176 | if (err < 0) | |
177 | return err; | |
178 | ||
179 | err = phy_write(phydev, 0x1e, 0x100); | |
180 | if (err < 0) | |
181 | return err; | |
182 | ||
76884679 AF |
183 | err = phy_write(phydev, MII_M1011_PHY_SCR, |
184 | MII_M1011_PHY_SCR_AUTO_CROSS); | |
185 | if (err < 0) | |
186 | return err; | |
187 | ||
188 | err = phy_write(phydev, MII_M1111_PHY_LED_CONTROL, | |
189 | MII_M1111_PHY_LED_DIRECT); | |
190 | if (err < 0) | |
191 | return err; | |
00db8189 AF |
192 | |
193 | err = genphy_config_aneg(phydev); | |
8ff44985 AV |
194 | if (err < 0) |
195 | return err; | |
00db8189 | 196 | |
8ff44985 AV |
197 | if (phydev->autoneg != AUTONEG_ENABLE) { |
198 | int bmcr; | |
199 | ||
200 | /* | |
201 | * A write to speed/duplex bits (that is performed by | |
202 | * genphy_config_aneg() call above) must be followed by | |
203 | * a software reset. Otherwise, the write has no effect. | |
204 | */ | |
205 | bmcr = phy_read(phydev, MII_BMCR); | |
206 | if (bmcr < 0) | |
207 | return bmcr; | |
208 | ||
209 | err = phy_write(phydev, MII_BMCR, bmcr | BMCR_RESET); | |
210 | if (err < 0) | |
211 | return err; | |
212 | } | |
213 | ||
214 | return 0; | |
00db8189 AF |
215 | } |
216 | ||
cf41a51d DD |
217 | #ifdef CONFIG_OF_MDIO |
218 | /* | |
219 | * Set and/or override some configuration registers based on the | |
220 | * marvell,reg-init property stored in the of_node for the phydev. | |
221 | * | |
222 | * marvell,reg-init = <reg-page reg mask value>,...; | |
223 | * | |
224 | * There may be one or more sets of <reg-page reg mask value>: | |
225 | * | |
226 | * reg-page: which register bank to use. | |
227 | * reg: the register. | |
228 | * mask: if non-zero, ANDed with existing register value. | |
229 | * value: ORed with the masked value and written to the regiser. | |
230 | * | |
231 | */ | |
232 | static int marvell_of_reg_init(struct phy_device *phydev) | |
233 | { | |
234 | const __be32 *paddr; | |
235 | int len, i, saved_page, current_page, page_changed, ret; | |
236 | ||
237 | if (!phydev->dev.of_node) | |
238 | return 0; | |
239 | ||
240 | paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len); | |
241 | if (!paddr || len < (4 * sizeof(*paddr))) | |
242 | return 0; | |
243 | ||
244 | saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE); | |
245 | if (saved_page < 0) | |
246 | return saved_page; | |
247 | page_changed = 0; | |
248 | current_page = saved_page; | |
249 | ||
250 | ret = 0; | |
251 | len /= sizeof(*paddr); | |
252 | for (i = 0; i < len - 3; i += 4) { | |
253 | u16 reg_page = be32_to_cpup(paddr + i); | |
254 | u16 reg = be32_to_cpup(paddr + i + 1); | |
255 | u16 mask = be32_to_cpup(paddr + i + 2); | |
256 | u16 val_bits = be32_to_cpup(paddr + i + 3); | |
257 | int val; | |
258 | ||
259 | if (reg_page != current_page) { | |
260 | current_page = reg_page; | |
261 | page_changed = 1; | |
262 | ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page); | |
263 | if (ret < 0) | |
264 | goto err; | |
265 | } | |
266 | ||
267 | val = 0; | |
268 | if (mask) { | |
269 | val = phy_read(phydev, reg); | |
270 | if (val < 0) { | |
271 | ret = val; | |
272 | goto err; | |
273 | } | |
274 | val &= mask; | |
275 | } | |
276 | val |= val_bits; | |
277 | ||
278 | ret = phy_write(phydev, reg, val); | |
279 | if (ret < 0) | |
280 | goto err; | |
281 | ||
282 | } | |
283 | err: | |
284 | if (page_changed) { | |
285 | i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page); | |
286 | if (ret == 0) | |
287 | ret = i; | |
288 | } | |
289 | return ret; | |
290 | } | |
291 | #else | |
292 | static int marvell_of_reg_init(struct phy_device *phydev) | |
293 | { | |
294 | return 0; | |
295 | } | |
296 | #endif /* CONFIG_OF_MDIO */ | |
297 | ||
140bc929 SP |
298 | static int m88e1121_config_aneg(struct phy_device *phydev) |
299 | { | |
c477d044 CC |
300 | int err, oldpage, mscr; |
301 | ||
27d916d6 | 302 | oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); |
c477d044 | 303 | |
27d916d6 | 304 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, |
c477d044 CC |
305 | MII_88E1121_PHY_MSCR_PAGE); |
306 | if (err < 0) | |
307 | return err; | |
be8c6480 AP |
308 | |
309 | if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || | |
310 | (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || | |
311 | (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || | |
312 | (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { | |
313 | ||
314 | mscr = phy_read(phydev, MII_88E1121_PHY_MSCR_REG) & | |
315 | MII_88E1121_PHY_MSCR_DELAY_MASK; | |
316 | ||
317 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) | |
318 | mscr |= (MII_88E1121_PHY_MSCR_RX_DELAY | | |
319 | MII_88E1121_PHY_MSCR_TX_DELAY); | |
320 | else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) | |
321 | mscr |= MII_88E1121_PHY_MSCR_RX_DELAY; | |
322 | else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) | |
323 | mscr |= MII_88E1121_PHY_MSCR_TX_DELAY; | |
324 | ||
325 | err = phy_write(phydev, MII_88E1121_PHY_MSCR_REG, mscr); | |
326 | if (err < 0) | |
327 | return err; | |
328 | } | |
c477d044 | 329 | |
27d916d6 | 330 | phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); |
140bc929 SP |
331 | |
332 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); | |
333 | if (err < 0) | |
334 | return err; | |
335 | ||
336 | err = phy_write(phydev, MII_M1011_PHY_SCR, | |
337 | MII_M1011_PHY_SCR_AUTO_CROSS); | |
338 | if (err < 0) | |
339 | return err; | |
340 | ||
27d916d6 | 341 | oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); |
140bc929 | 342 | |
27d916d6 | 343 | phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE); |
140bc929 | 344 | phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF); |
27d916d6 | 345 | phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); |
140bc929 SP |
346 | |
347 | err = genphy_config_aneg(phydev); | |
348 | ||
349 | return err; | |
350 | } | |
351 | ||
337ac9d5 | 352 | static int m88e1318_config_aneg(struct phy_device *phydev) |
3ff1c259 CC |
353 | { |
354 | int err, oldpage, mscr; | |
355 | ||
27d916d6 | 356 | oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); |
3ff1c259 | 357 | |
27d916d6 | 358 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, |
3ff1c259 CC |
359 | MII_88E1121_PHY_MSCR_PAGE); |
360 | if (err < 0) | |
361 | return err; | |
362 | ||
337ac9d5 CC |
363 | mscr = phy_read(phydev, MII_88E1318S_PHY_MSCR1_REG); |
364 | mscr |= MII_88E1318S_PHY_MSCR1_PAD_ODD; | |
3ff1c259 | 365 | |
337ac9d5 | 366 | err = phy_write(phydev, MII_88E1318S_PHY_MSCR1_REG, mscr); |
3ff1c259 CC |
367 | if (err < 0) |
368 | return err; | |
369 | ||
27d916d6 | 370 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); |
3ff1c259 CC |
371 | if (err < 0) |
372 | return err; | |
373 | ||
374 | return m88e1121_config_aneg(phydev); | |
375 | } | |
376 | ||
10e24caa MS |
377 | static int m88e1510_config_aneg(struct phy_device *phydev) |
378 | { | |
379 | int err; | |
380 | ||
381 | err = m88e1318_config_aneg(phydev); | |
382 | if (err < 0) | |
383 | return err; | |
384 | ||
385 | return marvell_of_reg_init(phydev); | |
386 | } | |
387 | ||
3da09a51 MS |
388 | static int m88e1116r_config_init(struct phy_device *phydev) |
389 | { | |
390 | int temp; | |
391 | int err; | |
392 | ||
393 | temp = phy_read(phydev, MII_BMCR); | |
394 | temp |= BMCR_RESET; | |
395 | err = phy_write(phydev, MII_BMCR, temp); | |
396 | if (err < 0) | |
397 | return err; | |
398 | ||
399 | mdelay(500); | |
400 | ||
401 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0); | |
402 | if (err < 0) | |
403 | return err; | |
404 | ||
405 | temp = phy_read(phydev, MII_M1011_PHY_SCR); | |
406 | temp |= (7 << 12); /* max number of gigabit attempts */ | |
407 | temp |= (1 << 11); /* enable downshift */ | |
408 | temp |= MII_M1011_PHY_SCR_AUTO_CROSS; | |
409 | err = phy_write(phydev, MII_M1011_PHY_SCR, temp); | |
410 | if (err < 0) | |
411 | return err; | |
412 | ||
413 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 2); | |
414 | if (err < 0) | |
415 | return err; | |
416 | temp = phy_read(phydev, MII_M1116R_CONTROL_REG_MAC); | |
417 | temp |= (1 << 5); | |
418 | temp |= (1 << 4); | |
419 | err = phy_write(phydev, MII_M1116R_CONTROL_REG_MAC, temp); | |
420 | if (err < 0) | |
421 | return err; | |
422 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0); | |
423 | if (err < 0) | |
424 | return err; | |
425 | ||
426 | temp = phy_read(phydev, MII_BMCR); | |
427 | temp |= BMCR_RESET; | |
428 | err = phy_write(phydev, MII_BMCR, temp); | |
429 | if (err < 0) | |
430 | return err; | |
431 | ||
432 | mdelay(500); | |
433 | ||
434 | return 0; | |
435 | } | |
436 | ||
895ee682 KP |
437 | static int m88e1111_config_init(struct phy_device *phydev) |
438 | { | |
439 | int err; | |
be937f1f | 440 | int temp; |
be937f1f | 441 | |
895ee682 | 442 | if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || |
9daf5a76 KP |
443 | (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || |
444 | (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || | |
445 | (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { | |
895ee682 | 446 | |
9daf5a76 KP |
447 | temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); |
448 | if (temp < 0) | |
449 | return temp; | |
895ee682 | 450 | |
9daf5a76 | 451 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { |
895ee682 | 452 | temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); |
9daf5a76 KP |
453 | } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { |
454 | temp &= ~MII_M1111_TX_DELAY; | |
455 | temp |= MII_M1111_RX_DELAY; | |
456 | } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) { | |
457 | temp &= ~MII_M1111_RX_DELAY; | |
458 | temp |= MII_M1111_TX_DELAY; | |
895ee682 KP |
459 | } |
460 | ||
9daf5a76 KP |
461 | err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); |
462 | if (err < 0) | |
463 | return err; | |
464 | ||
895ee682 KP |
465 | temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); |
466 | if (temp < 0) | |
467 | return temp; | |
468 | ||
469 | temp &= ~(MII_M1111_HWCFG_MODE_MASK); | |
be937f1f | 470 | |
7239016d | 471 | if (temp & MII_M1111_HWCFG_FIBER_COPPER_RES) |
be937f1f AS |
472 | temp |= MII_M1111_HWCFG_MODE_FIBER_RGMII; |
473 | else | |
474 | temp |= MII_M1111_HWCFG_MODE_COPPER_RGMII; | |
895ee682 KP |
475 | |
476 | err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); | |
477 | if (err < 0) | |
478 | return err; | |
479 | } | |
480 | ||
4117b5be | 481 | if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { |
4117b5be KJ |
482 | temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); |
483 | if (temp < 0) | |
484 | return temp; | |
485 | ||
486 | temp &= ~(MII_M1111_HWCFG_MODE_MASK); | |
487 | temp |= MII_M1111_HWCFG_MODE_SGMII_NO_CLK; | |
32d0c1e1 | 488 | temp |= MII_M1111_HWCFG_FIBER_COPPER_AUTO; |
4117b5be KJ |
489 | |
490 | err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); | |
491 | if (err < 0) | |
492 | return err; | |
493 | } | |
494 | ||
5f8cbc13 LYB |
495 | if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { |
496 | temp = phy_read(phydev, MII_M1111_PHY_EXT_CR); | |
497 | if (temp < 0) | |
498 | return temp; | |
499 | temp |= (MII_M1111_RX_DELAY | MII_M1111_TX_DELAY); | |
500 | err = phy_write(phydev, MII_M1111_PHY_EXT_CR, temp); | |
501 | if (err < 0) | |
502 | return err; | |
503 | ||
504 | temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); | |
505 | if (temp < 0) | |
506 | return temp; | |
507 | temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); | |
508 | temp |= 0x7 | MII_M1111_HWCFG_FIBER_COPPER_AUTO; | |
509 | err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); | |
510 | if (err < 0) | |
511 | return err; | |
512 | ||
513 | /* soft reset */ | |
514 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); | |
515 | if (err < 0) | |
516 | return err; | |
517 | do | |
518 | temp = phy_read(phydev, MII_BMCR); | |
519 | while (temp & BMCR_RESET); | |
520 | ||
521 | temp = phy_read(phydev, MII_M1111_PHY_EXT_SR); | |
522 | if (temp < 0) | |
523 | return temp; | |
524 | temp &= ~(MII_M1111_HWCFG_MODE_MASK | MII_M1111_HWCFG_FIBER_COPPER_RES); | |
525 | temp |= MII_M1111_HWCFG_MODE_COPPER_RTBI | MII_M1111_HWCFG_FIBER_COPPER_AUTO; | |
526 | err = phy_write(phydev, MII_M1111_PHY_EXT_SR, temp); | |
527 | if (err < 0) | |
528 | return err; | |
529 | } | |
530 | ||
cf41a51d DD |
531 | err = marvell_of_reg_init(phydev); |
532 | if (err < 0) | |
533 | return err; | |
5f8cbc13 | 534 | |
cc90cb3b | 535 | return phy_write(phydev, MII_BMCR, BMCR_RESET); |
895ee682 KP |
536 | } |
537 | ||
605f196e RM |
538 | static int m88e1118_config_aneg(struct phy_device *phydev) |
539 | { | |
540 | int err; | |
541 | ||
542 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); | |
543 | if (err < 0) | |
544 | return err; | |
545 | ||
546 | err = phy_write(phydev, MII_M1011_PHY_SCR, | |
547 | MII_M1011_PHY_SCR_AUTO_CROSS); | |
548 | if (err < 0) | |
549 | return err; | |
550 | ||
551 | err = genphy_config_aneg(phydev); | |
552 | return 0; | |
553 | } | |
554 | ||
555 | static int m88e1118_config_init(struct phy_device *phydev) | |
556 | { | |
557 | int err; | |
558 | ||
559 | /* Change address */ | |
27d916d6 | 560 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002); |
605f196e RM |
561 | if (err < 0) |
562 | return err; | |
563 | ||
564 | /* Enable 1000 Mbit */ | |
565 | err = phy_write(phydev, 0x15, 0x1070); | |
566 | if (err < 0) | |
567 | return err; | |
568 | ||
569 | /* Change address */ | |
27d916d6 | 570 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003); |
605f196e RM |
571 | if (err < 0) |
572 | return err; | |
573 | ||
574 | /* Adjust LED Control */ | |
2f495c39 BH |
575 | if (phydev->dev_flags & MARVELL_PHY_M1118_DNS323_LEDS) |
576 | err = phy_write(phydev, 0x10, 0x1100); | |
577 | else | |
578 | err = phy_write(phydev, 0x10, 0x021e); | |
605f196e RM |
579 | if (err < 0) |
580 | return err; | |
581 | ||
cf41a51d DD |
582 | err = marvell_of_reg_init(phydev); |
583 | if (err < 0) | |
584 | return err; | |
585 | ||
605f196e | 586 | /* Reset address */ |
27d916d6 | 587 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0); |
605f196e RM |
588 | if (err < 0) |
589 | return err; | |
590 | ||
cc90cb3b | 591 | return phy_write(phydev, MII_BMCR, BMCR_RESET); |
605f196e RM |
592 | } |
593 | ||
90600732 DD |
594 | static int m88e1149_config_init(struct phy_device *phydev) |
595 | { | |
596 | int err; | |
597 | ||
598 | /* Change address */ | |
599 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002); | |
600 | if (err < 0) | |
601 | return err; | |
602 | ||
603 | /* Enable 1000 Mbit */ | |
604 | err = phy_write(phydev, 0x15, 0x1048); | |
605 | if (err < 0) | |
606 | return err; | |
607 | ||
cf41a51d DD |
608 | err = marvell_of_reg_init(phydev); |
609 | if (err < 0) | |
610 | return err; | |
611 | ||
90600732 DD |
612 | /* Reset address */ |
613 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0); | |
614 | if (err < 0) | |
615 | return err; | |
616 | ||
cc90cb3b | 617 | return phy_write(phydev, MII_BMCR, BMCR_RESET); |
90600732 DD |
618 | } |
619 | ||
76884679 AF |
620 | static int m88e1145_config_init(struct phy_device *phydev) |
621 | { | |
622 | int err; | |
623 | ||
624 | /* Take care of errata E0 & E1 */ | |
625 | err = phy_write(phydev, 0x1d, 0x001b); | |
626 | if (err < 0) | |
627 | return err; | |
628 | ||
629 | err = phy_write(phydev, 0x1e, 0x418f); | |
630 | if (err < 0) | |
631 | return err; | |
632 | ||
633 | err = phy_write(phydev, 0x1d, 0x0016); | |
634 | if (err < 0) | |
635 | return err; | |
636 | ||
637 | err = phy_write(phydev, 0x1e, 0xa2da); | |
638 | if (err < 0) | |
639 | return err; | |
640 | ||
895ee682 | 641 | if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { |
76884679 AF |
642 | int temp = phy_read(phydev, MII_M1145_PHY_EXT_CR); |
643 | if (temp < 0) | |
644 | return temp; | |
645 | ||
646 | temp |= (MII_M1145_RGMII_RX_DELAY | MII_M1145_RGMII_TX_DELAY); | |
647 | ||
648 | err = phy_write(phydev, MII_M1145_PHY_EXT_CR, temp); | |
649 | if (err < 0) | |
650 | return err; | |
651 | ||
2f495c39 | 652 | if (phydev->dev_flags & MARVELL_PHY_M1145_FLAGS_RESISTANCE) { |
76884679 AF |
653 | err = phy_write(phydev, 0x1d, 0x0012); |
654 | if (err < 0) | |
655 | return err; | |
656 | ||
657 | temp = phy_read(phydev, 0x1e); | |
658 | if (temp < 0) | |
659 | return temp; | |
660 | ||
661 | temp &= 0xf03f; | |
662 | temp |= 2 << 9; /* 36 ohm */ | |
663 | temp |= 2 << 6; /* 39 ohm */ | |
664 | ||
665 | err = phy_write(phydev, 0x1e, temp); | |
666 | if (err < 0) | |
667 | return err; | |
668 | ||
669 | err = phy_write(phydev, 0x1d, 0x3); | |
670 | if (err < 0) | |
671 | return err; | |
672 | ||
673 | err = phy_write(phydev, 0x1e, 0x8000); | |
674 | if (err < 0) | |
675 | return err; | |
676 | } | |
677 | } | |
678 | ||
cf41a51d DD |
679 | err = marvell_of_reg_init(phydev); |
680 | if (err < 0) | |
681 | return err; | |
682 | ||
76884679 AF |
683 | return 0; |
684 | } | |
00db8189 | 685 | |
be937f1f AS |
686 | /* marvell_read_status |
687 | * | |
688 | * Generic status code does not detect Fiber correctly! | |
f0c88f9c | 689 | * Description: |
be937f1f AS |
690 | * Check the link, then figure out the current state |
691 | * by comparing what we advertise with what the link partner | |
692 | * advertises. Start by checking the gigabit possibilities, | |
693 | * then move on to 10/100. | |
694 | */ | |
695 | static int marvell_read_status(struct phy_device *phydev) | |
696 | { | |
697 | int adv; | |
698 | int err; | |
699 | int lpa; | |
700 | int status = 0; | |
701 | ||
702 | /* Update the link, but return if there | |
703 | * was an error */ | |
704 | err = genphy_update_link(phydev); | |
705 | if (err) | |
706 | return err; | |
707 | ||
708 | if (AUTONEG_ENABLE == phydev->autoneg) { | |
709 | status = phy_read(phydev, MII_M1011_PHY_STATUS); | |
710 | if (status < 0) | |
711 | return status; | |
712 | ||
713 | lpa = phy_read(phydev, MII_LPA); | |
714 | if (lpa < 0) | |
715 | return lpa; | |
716 | ||
717 | adv = phy_read(phydev, MII_ADVERTISE); | |
718 | if (adv < 0) | |
719 | return adv; | |
720 | ||
721 | lpa &= adv; | |
722 | ||
723 | if (status & MII_M1011_PHY_STATUS_FULLDUPLEX) | |
724 | phydev->duplex = DUPLEX_FULL; | |
725 | else | |
726 | phydev->duplex = DUPLEX_HALF; | |
727 | ||
728 | status = status & MII_M1011_PHY_STATUS_SPD_MASK; | |
729 | phydev->pause = phydev->asym_pause = 0; | |
730 | ||
731 | switch (status) { | |
732 | case MII_M1011_PHY_STATUS_1000: | |
733 | phydev->speed = SPEED_1000; | |
734 | break; | |
735 | ||
736 | case MII_M1011_PHY_STATUS_100: | |
737 | phydev->speed = SPEED_100; | |
738 | break; | |
739 | ||
740 | default: | |
741 | phydev->speed = SPEED_10; | |
742 | break; | |
743 | } | |
744 | ||
745 | if (phydev->duplex == DUPLEX_FULL) { | |
746 | phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0; | |
747 | phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0; | |
748 | } | |
749 | } else { | |
750 | int bmcr = phy_read(phydev, MII_BMCR); | |
751 | ||
752 | if (bmcr < 0) | |
753 | return bmcr; | |
754 | ||
755 | if (bmcr & BMCR_FULLDPLX) | |
756 | phydev->duplex = DUPLEX_FULL; | |
757 | else | |
758 | phydev->duplex = DUPLEX_HALF; | |
759 | ||
760 | if (bmcr & BMCR_SPEED1000) | |
761 | phydev->speed = SPEED_1000; | |
762 | else if (bmcr & BMCR_SPEED100) | |
763 | phydev->speed = SPEED_100; | |
764 | else | |
765 | phydev->speed = SPEED_10; | |
766 | ||
767 | phydev->pause = phydev->asym_pause = 0; | |
768 | } | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
dcd07be3 AG |
773 | static int m88e1121_did_interrupt(struct phy_device *phydev) |
774 | { | |
775 | int imask; | |
776 | ||
777 | imask = phy_read(phydev, MII_M1011_IEVENT); | |
778 | ||
779 | if (imask & MII_M1011_IMASK_INIT) | |
780 | return 1; | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
3871c387 MS |
785 | static void m88e1318_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) |
786 | { | |
787 | wol->supported = WAKE_MAGIC; | |
788 | wol->wolopts = 0; | |
789 | ||
790 | if (phy_write(phydev, MII_MARVELL_PHY_PAGE, | |
791 | MII_88E1318S_PHY_WOL_PAGE) < 0) | |
792 | return; | |
793 | ||
794 | if (phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL) & | |
795 | MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE) | |
796 | wol->wolopts |= WAKE_MAGIC; | |
797 | ||
798 | if (phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00) < 0) | |
799 | return; | |
800 | } | |
801 | ||
802 | static int m88e1318_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) | |
803 | { | |
804 | int err, oldpage, temp; | |
805 | ||
806 | oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); | |
807 | ||
808 | if (wol->wolopts & WAKE_MAGIC) { | |
809 | /* Explicitly switch to page 0x00, just to be sure */ | |
810 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x00); | |
811 | if (err < 0) | |
812 | return err; | |
813 | ||
814 | /* Enable the WOL interrupt */ | |
815 | temp = phy_read(phydev, MII_88E1318S_PHY_CSIER); | |
816 | temp |= MII_88E1318S_PHY_CSIER_WOL_EIE; | |
817 | err = phy_write(phydev, MII_88E1318S_PHY_CSIER, temp); | |
818 | if (err < 0) | |
819 | return err; | |
820 | ||
821 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, | |
822 | MII_88E1318S_PHY_LED_PAGE); | |
823 | if (err < 0) | |
824 | return err; | |
825 | ||
826 | /* Setup LED[2] as interrupt pin (active low) */ | |
827 | temp = phy_read(phydev, MII_88E1318S_PHY_LED_TCR); | |
828 | temp &= ~MII_88E1318S_PHY_LED_TCR_FORCE_INT; | |
829 | temp |= MII_88E1318S_PHY_LED_TCR_INTn_ENABLE; | |
830 | temp |= MII_88E1318S_PHY_LED_TCR_INT_ACTIVE_LOW; | |
831 | err = phy_write(phydev, MII_88E1318S_PHY_LED_TCR, temp); | |
832 | if (err < 0) | |
833 | return err; | |
834 | ||
835 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, | |
836 | MII_88E1318S_PHY_WOL_PAGE); | |
837 | if (err < 0) | |
838 | return err; | |
839 | ||
840 | /* Store the device address for the magic packet */ | |
841 | err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD2, | |
842 | ((phydev->attached_dev->dev_addr[5] << 8) | | |
843 | phydev->attached_dev->dev_addr[4])); | |
844 | if (err < 0) | |
845 | return err; | |
846 | err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD1, | |
847 | ((phydev->attached_dev->dev_addr[3] << 8) | | |
848 | phydev->attached_dev->dev_addr[2])); | |
849 | if (err < 0) | |
850 | return err; | |
851 | err = phy_write(phydev, MII_88E1318S_PHY_MAGIC_PACKET_WORD0, | |
852 | ((phydev->attached_dev->dev_addr[1] << 8) | | |
853 | phydev->attached_dev->dev_addr[0])); | |
854 | if (err < 0) | |
855 | return err; | |
856 | ||
857 | /* Clear WOL status and enable magic packet matching */ | |
858 | temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL); | |
859 | temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS; | |
860 | temp |= MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE; | |
861 | err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp); | |
862 | if (err < 0) | |
863 | return err; | |
864 | } else { | |
865 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, | |
866 | MII_88E1318S_PHY_WOL_PAGE); | |
867 | if (err < 0) | |
868 | return err; | |
869 | ||
870 | /* Clear WOL status and disable magic packet matching */ | |
871 | temp = phy_read(phydev, MII_88E1318S_PHY_WOL_CTRL); | |
872 | temp |= MII_88E1318S_PHY_WOL_CTRL_CLEAR_WOL_STATUS; | |
873 | temp &= ~MII_88E1318S_PHY_WOL_CTRL_MAGIC_PACKET_MATCH_ENABLE; | |
874 | err = phy_write(phydev, MII_88E1318S_PHY_WOL_CTRL, temp); | |
875 | if (err < 0) | |
876 | return err; | |
877 | } | |
878 | ||
879 | err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); | |
880 | if (err < 0) | |
881 | return err; | |
882 | ||
883 | return 0; | |
884 | } | |
885 | ||
e5479239 OJ |
886 | static struct phy_driver marvell_drivers[] = { |
887 | { | |
2f495c39 BH |
888 | .phy_id = MARVELL_PHY_ID_88E1101, |
889 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
e5479239 OJ |
890 | .name = "Marvell 88E1101", |
891 | .features = PHY_GBIT_FEATURES, | |
892 | .flags = PHY_HAS_INTERRUPT, | |
893 | .config_aneg = &marvell_config_aneg, | |
894 | .read_status = &genphy_read_status, | |
895 | .ack_interrupt = &marvell_ack_interrupt, | |
896 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
897 | .resume = &genphy_resume, |
898 | .suspend = &genphy_suspend, | |
ac8c635a | 899 | .driver = { .owner = THIS_MODULE }, |
e5479239 | 900 | }, |
85cfb534 | 901 | { |
2f495c39 BH |
902 | .phy_id = MARVELL_PHY_ID_88E1112, |
903 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
85cfb534 OJ |
904 | .name = "Marvell 88E1112", |
905 | .features = PHY_GBIT_FEATURES, | |
906 | .flags = PHY_HAS_INTERRUPT, | |
907 | .config_init = &m88e1111_config_init, | |
908 | .config_aneg = &marvell_config_aneg, | |
909 | .read_status = &genphy_read_status, | |
910 | .ack_interrupt = &marvell_ack_interrupt, | |
911 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
912 | .resume = &genphy_resume, |
913 | .suspend = &genphy_suspend, | |
ac8c635a | 914 | .driver = { .owner = THIS_MODULE }, |
85cfb534 | 915 | }, |
e5479239 | 916 | { |
2f495c39 BH |
917 | .phy_id = MARVELL_PHY_ID_88E1111, |
918 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
e5479239 OJ |
919 | .name = "Marvell 88E1111", |
920 | .features = PHY_GBIT_FEATURES, | |
921 | .flags = PHY_HAS_INTERRUPT, | |
922 | .config_init = &m88e1111_config_init, | |
923 | .config_aneg = &marvell_config_aneg, | |
be937f1f | 924 | .read_status = &marvell_read_status, |
e5479239 OJ |
925 | .ack_interrupt = &marvell_ack_interrupt, |
926 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
927 | .resume = &genphy_resume, |
928 | .suspend = &genphy_suspend, | |
ac8c635a | 929 | .driver = { .owner = THIS_MODULE }, |
e5479239 | 930 | }, |
605f196e | 931 | { |
2f495c39 BH |
932 | .phy_id = MARVELL_PHY_ID_88E1118, |
933 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
605f196e RM |
934 | .name = "Marvell 88E1118", |
935 | .features = PHY_GBIT_FEATURES, | |
936 | .flags = PHY_HAS_INTERRUPT, | |
937 | .config_init = &m88e1118_config_init, | |
938 | .config_aneg = &m88e1118_config_aneg, | |
939 | .read_status = &genphy_read_status, | |
940 | .ack_interrupt = &marvell_ack_interrupt, | |
941 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
942 | .resume = &genphy_resume, |
943 | .suspend = &genphy_suspend, | |
605f196e RM |
944 | .driver = {.owner = THIS_MODULE,}, |
945 | }, | |
140bc929 | 946 | { |
2f495c39 BH |
947 | .phy_id = MARVELL_PHY_ID_88E1121R, |
948 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
140bc929 SP |
949 | .name = "Marvell 88E1121R", |
950 | .features = PHY_GBIT_FEATURES, | |
951 | .flags = PHY_HAS_INTERRUPT, | |
952 | .config_aneg = &m88e1121_config_aneg, | |
953 | .read_status = &marvell_read_status, | |
954 | .ack_interrupt = &marvell_ack_interrupt, | |
955 | .config_intr = &marvell_config_intr, | |
dcd07be3 | 956 | .did_interrupt = &m88e1121_did_interrupt, |
0898b448 SH |
957 | .resume = &genphy_resume, |
958 | .suspend = &genphy_suspend, | |
140bc929 SP |
959 | .driver = { .owner = THIS_MODULE }, |
960 | }, | |
3ff1c259 | 961 | { |
337ac9d5 | 962 | .phy_id = MARVELL_PHY_ID_88E1318S, |
6ba74014 | 963 | .phy_id_mask = MARVELL_PHY_ID_MASK, |
337ac9d5 | 964 | .name = "Marvell 88E1318S", |
3ff1c259 CC |
965 | .features = PHY_GBIT_FEATURES, |
966 | .flags = PHY_HAS_INTERRUPT, | |
337ac9d5 | 967 | .config_aneg = &m88e1318_config_aneg, |
3ff1c259 CC |
968 | .read_status = &marvell_read_status, |
969 | .ack_interrupt = &marvell_ack_interrupt, | |
970 | .config_intr = &marvell_config_intr, | |
971 | .did_interrupt = &m88e1121_did_interrupt, | |
3871c387 MS |
972 | .get_wol = &m88e1318_get_wol, |
973 | .set_wol = &m88e1318_set_wol, | |
0898b448 SH |
974 | .resume = &genphy_resume, |
975 | .suspend = &genphy_suspend, | |
3ff1c259 CC |
976 | .driver = { .owner = THIS_MODULE }, |
977 | }, | |
e5479239 | 978 | { |
2f495c39 BH |
979 | .phy_id = MARVELL_PHY_ID_88E1145, |
980 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
e5479239 OJ |
981 | .name = "Marvell 88E1145", |
982 | .features = PHY_GBIT_FEATURES, | |
983 | .flags = PHY_HAS_INTERRUPT, | |
984 | .config_init = &m88e1145_config_init, | |
985 | .config_aneg = &marvell_config_aneg, | |
986 | .read_status = &genphy_read_status, | |
987 | .ack_interrupt = &marvell_ack_interrupt, | |
988 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
989 | .resume = &genphy_resume, |
990 | .suspend = &genphy_suspend, | |
ac8c635a OJ |
991 | .driver = { .owner = THIS_MODULE }, |
992 | }, | |
90600732 DD |
993 | { |
994 | .phy_id = MARVELL_PHY_ID_88E1149R, | |
995 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
996 | .name = "Marvell 88E1149R", | |
997 | .features = PHY_GBIT_FEATURES, | |
998 | .flags = PHY_HAS_INTERRUPT, | |
999 | .config_init = &m88e1149_config_init, | |
1000 | .config_aneg = &m88e1118_config_aneg, | |
1001 | .read_status = &genphy_read_status, | |
1002 | .ack_interrupt = &marvell_ack_interrupt, | |
1003 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
1004 | .resume = &genphy_resume, |
1005 | .suspend = &genphy_suspend, | |
90600732 DD |
1006 | .driver = { .owner = THIS_MODULE }, |
1007 | }, | |
ac8c635a | 1008 | { |
2f495c39 BH |
1009 | .phy_id = MARVELL_PHY_ID_88E1240, |
1010 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
ac8c635a OJ |
1011 | .name = "Marvell 88E1240", |
1012 | .features = PHY_GBIT_FEATURES, | |
1013 | .flags = PHY_HAS_INTERRUPT, | |
1014 | .config_init = &m88e1111_config_init, | |
1015 | .config_aneg = &marvell_config_aneg, | |
1016 | .read_status = &genphy_read_status, | |
1017 | .ack_interrupt = &marvell_ack_interrupt, | |
1018 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
1019 | .resume = &genphy_resume, |
1020 | .suspend = &genphy_suspend, | |
ac8c635a OJ |
1021 | .driver = { .owner = THIS_MODULE }, |
1022 | }, | |
3da09a51 MS |
1023 | { |
1024 | .phy_id = MARVELL_PHY_ID_88E1116R, | |
1025 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
1026 | .name = "Marvell 88E1116R", | |
1027 | .features = PHY_GBIT_FEATURES, | |
1028 | .flags = PHY_HAS_INTERRUPT, | |
1029 | .config_init = &m88e1116r_config_init, | |
1030 | .config_aneg = &genphy_config_aneg, | |
1031 | .read_status = &genphy_read_status, | |
1032 | .ack_interrupt = &marvell_ack_interrupt, | |
1033 | .config_intr = &marvell_config_intr, | |
0898b448 SH |
1034 | .resume = &genphy_resume, |
1035 | .suspend = &genphy_suspend, | |
3da09a51 MS |
1036 | .driver = { .owner = THIS_MODULE }, |
1037 | }, | |
10e24caa MS |
1038 | { |
1039 | .phy_id = MARVELL_PHY_ID_88E1510, | |
1040 | .phy_id_mask = MARVELL_PHY_ID_MASK, | |
1041 | .name = "Marvell 88E1510", | |
1042 | .features = PHY_GBIT_FEATURES, | |
1043 | .flags = PHY_HAS_INTERRUPT, | |
1044 | .config_aneg = &m88e1510_config_aneg, | |
1045 | .read_status = &marvell_read_status, | |
1046 | .ack_interrupt = &marvell_ack_interrupt, | |
1047 | .config_intr = &marvell_config_intr, | |
1048 | .did_interrupt = &m88e1121_did_interrupt, | |
0898b448 SH |
1049 | .resume = &genphy_resume, |
1050 | .suspend = &genphy_suspend, | |
10e24caa MS |
1051 | .driver = { .owner = THIS_MODULE }, |
1052 | }, | |
00db8189 AF |
1053 | }; |
1054 | ||
1055 | static int __init marvell_init(void) | |
1056 | { | |
d5bf9071 CH |
1057 | return phy_drivers_register(marvell_drivers, |
1058 | ARRAY_SIZE(marvell_drivers)); | |
00db8189 AF |
1059 | } |
1060 | ||
1061 | static void __exit marvell_exit(void) | |
1062 | { | |
d5bf9071 CH |
1063 | phy_drivers_unregister(marvell_drivers, |
1064 | ARRAY_SIZE(marvell_drivers)); | |
00db8189 AF |
1065 | } |
1066 | ||
1067 | module_init(marvell_init); | |
1068 | module_exit(marvell_exit); | |
4e4f10f6 | 1069 | |
cf93c945 | 1070 | static struct mdio_device_id __maybe_unused marvell_tbl[] = { |
f5e1cabf MS |
1071 | { MARVELL_PHY_ID_88E1101, MARVELL_PHY_ID_MASK }, |
1072 | { MARVELL_PHY_ID_88E1112, MARVELL_PHY_ID_MASK }, | |
1073 | { MARVELL_PHY_ID_88E1111, MARVELL_PHY_ID_MASK }, | |
1074 | { MARVELL_PHY_ID_88E1118, MARVELL_PHY_ID_MASK }, | |
1075 | { MARVELL_PHY_ID_88E1121R, MARVELL_PHY_ID_MASK }, | |
1076 | { MARVELL_PHY_ID_88E1145, MARVELL_PHY_ID_MASK }, | |
1077 | { MARVELL_PHY_ID_88E1149R, MARVELL_PHY_ID_MASK }, | |
1078 | { MARVELL_PHY_ID_88E1240, MARVELL_PHY_ID_MASK }, | |
1079 | { MARVELL_PHY_ID_88E1318S, MARVELL_PHY_ID_MASK }, | |
3da09a51 | 1080 | { MARVELL_PHY_ID_88E1116R, MARVELL_PHY_ID_MASK }, |
10e24caa | 1081 | { MARVELL_PHY_ID_88E1510, MARVELL_PHY_ID_MASK }, |
4e4f10f6 DW |
1082 | { } |
1083 | }; | |
1084 | ||
1085 | MODULE_DEVICE_TABLE(mdio, marvell_tbl); |