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d0507009 DC |
1 | /* |
2 | * drivers/net/phy/micrel.c | |
3 | * | |
4 | * Driver for Micrel PHYs | |
5 | * | |
6 | * Author: David J. Choi | |
7 | * | |
7ab59dc1 | 8 | * Copyright (c) 2010-2013 Micrel, Inc. |
ee0dc2fb | 9 | * Copyright (c) 2014 Johan Hovold <johan@kernel.org> |
d0507009 DC |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
7ab59dc1 DC |
16 | * Support : Micrel Phys: |
17 | * Giga phys: ksz9021, ksz9031 | |
18 | * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 | |
19 | * ksz8021, ksz8031, ksz8051, | |
20 | * ksz8081, ksz8091, | |
21 | * ksz8061, | |
22 | * Switch : ksz8873, ksz886x | |
fc3973a1 | 23 | * ksz9477 |
d0507009 DC |
24 | */ |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/phy.h> | |
d606ef3f | 29 | #include <linux/micrel_phy.h> |
954c3967 | 30 | #include <linux/of.h> |
1fadee0c | 31 | #include <linux/clk.h> |
d0507009 | 32 | |
212ea99a MV |
33 | /* Operation Mode Strap Override */ |
34 | #define MII_KSZPHY_OMSO 0x16 | |
00aee095 | 35 | #define KSZPHY_OMSO_B_CAST_OFF BIT(9) |
2b0ba96c | 36 | #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) |
00aee095 JH |
37 | #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) |
38 | #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) | |
212ea99a | 39 | |
51f932c4 CD |
40 | /* general Interrupt control/status reg in vendor specific block. */ |
41 | #define MII_KSZPHY_INTCS 0x1B | |
00aee095 JH |
42 | #define KSZPHY_INTCS_JABBER BIT(15) |
43 | #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) | |
44 | #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) | |
45 | #define KSZPHY_INTCS_PARELLEL BIT(12) | |
46 | #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) | |
47 | #define KSZPHY_INTCS_LINK_DOWN BIT(10) | |
48 | #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) | |
49 | #define KSZPHY_INTCS_LINK_UP BIT(8) | |
51f932c4 CD |
50 | #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ |
51 | KSZPHY_INTCS_LINK_DOWN) | |
52 | ||
5a16778e JH |
53 | /* PHY Control 1 */ |
54 | #define MII_KSZPHY_CTRL_1 0x1e | |
55 | ||
56 | /* PHY Control 2 / PHY Control (if no PHY Control 1) */ | |
57 | #define MII_KSZPHY_CTRL_2 0x1f | |
58 | #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 | |
51f932c4 | 59 | /* bitmap of PHY register to set interrupt mode */ |
00aee095 | 60 | #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) |
63f44b2b | 61 | #define KSZPHY_RMII_REF_CLK_SEL BIT(7) |
51f932c4 | 62 | |
954c3967 SC |
63 | /* Write/read to/from extended registers */ |
64 | #define MII_KSZPHY_EXTREG 0x0b | |
65 | #define KSZPHY_EXTREG_WRITE 0x8000 | |
66 | ||
67 | #define MII_KSZPHY_EXTREG_WRITE 0x0c | |
68 | #define MII_KSZPHY_EXTREG_READ 0x0d | |
69 | ||
70 | /* Extended registers */ | |
71 | #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 | |
72 | #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 | |
73 | #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 | |
74 | ||
75 | #define PS_TO_REG 200 | |
76 | ||
2b2427d0 AL |
77 | struct kszphy_hw_stat { |
78 | const char *string; | |
79 | u8 reg; | |
80 | u8 bits; | |
81 | }; | |
82 | ||
83 | static struct kszphy_hw_stat kszphy_hw_stats[] = { | |
84 | { "phy_receive_errors", 21, 16}, | |
85 | { "phy_idle_errors", 10, 8 }, | |
86 | }; | |
87 | ||
e6a423a8 JH |
88 | struct kszphy_type { |
89 | u32 led_mode_reg; | |
c6f9575c | 90 | u16 interrupt_level_mask; |
0f95903e | 91 | bool has_broadcast_disable; |
2b0ba96c | 92 | bool has_nand_tree_disable; |
63f44b2b | 93 | bool has_rmii_ref_clk_sel; |
e6a423a8 JH |
94 | }; |
95 | ||
96 | struct kszphy_priv { | |
97 | const struct kszphy_type *type; | |
e7a792e9 | 98 | int led_mode; |
63f44b2b JH |
99 | bool rmii_ref_clk_sel; |
100 | bool rmii_ref_clk_sel_val; | |
2b2427d0 | 101 | u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; |
e6a423a8 JH |
102 | }; |
103 | ||
104 | static const struct kszphy_type ksz8021_type = { | |
105 | .led_mode_reg = MII_KSZPHY_CTRL_2, | |
d0e1df9c | 106 | .has_broadcast_disable = true, |
2b0ba96c | 107 | .has_nand_tree_disable = true, |
63f44b2b | 108 | .has_rmii_ref_clk_sel = true, |
e6a423a8 JH |
109 | }; |
110 | ||
111 | static const struct kszphy_type ksz8041_type = { | |
112 | .led_mode_reg = MII_KSZPHY_CTRL_1, | |
113 | }; | |
114 | ||
115 | static const struct kszphy_type ksz8051_type = { | |
116 | .led_mode_reg = MII_KSZPHY_CTRL_2, | |
2b0ba96c | 117 | .has_nand_tree_disable = true, |
e6a423a8 JH |
118 | }; |
119 | ||
120 | static const struct kszphy_type ksz8081_type = { | |
121 | .led_mode_reg = MII_KSZPHY_CTRL_2, | |
0f95903e | 122 | .has_broadcast_disable = true, |
2b0ba96c | 123 | .has_nand_tree_disable = true, |
86dc1342 | 124 | .has_rmii_ref_clk_sel = true, |
e6a423a8 JH |
125 | }; |
126 | ||
c6f9575c JH |
127 | static const struct kszphy_type ks8737_type = { |
128 | .interrupt_level_mask = BIT(14), | |
129 | }; | |
130 | ||
131 | static const struct kszphy_type ksz9021_type = { | |
132 | .interrupt_level_mask = BIT(14), | |
133 | }; | |
134 | ||
954c3967 | 135 | static int kszphy_extended_write(struct phy_device *phydev, |
756b5089 | 136 | u32 regnum, u16 val) |
954c3967 SC |
137 | { |
138 | phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); | |
139 | return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); | |
140 | } | |
141 | ||
142 | static int kszphy_extended_read(struct phy_device *phydev, | |
756b5089 | 143 | u32 regnum) |
954c3967 SC |
144 | { |
145 | phy_write(phydev, MII_KSZPHY_EXTREG, regnum); | |
146 | return phy_read(phydev, MII_KSZPHY_EXTREG_READ); | |
147 | } | |
148 | ||
51f932c4 CD |
149 | static int kszphy_ack_interrupt(struct phy_device *phydev) |
150 | { | |
151 | /* bit[7..0] int status, which is a read and clear register. */ | |
152 | int rc; | |
153 | ||
154 | rc = phy_read(phydev, MII_KSZPHY_INTCS); | |
155 | ||
156 | return (rc < 0) ? rc : 0; | |
157 | } | |
158 | ||
51f932c4 CD |
159 | static int kszphy_config_intr(struct phy_device *phydev) |
160 | { | |
c6f9575c JH |
161 | const struct kszphy_type *type = phydev->drv->driver_data; |
162 | int temp; | |
163 | u16 mask; | |
51f932c4 | 164 | |
c6f9575c JH |
165 | if (type && type->interrupt_level_mask) |
166 | mask = type->interrupt_level_mask; | |
167 | else | |
168 | mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; | |
51f932c4 CD |
169 | |
170 | /* set the interrupt pin active low */ | |
171 | temp = phy_read(phydev, MII_KSZPHY_CTRL); | |
5bb8fc0d JH |
172 | if (temp < 0) |
173 | return temp; | |
c6f9575c | 174 | temp &= ~mask; |
51f932c4 | 175 | phy_write(phydev, MII_KSZPHY_CTRL, temp); |
51f932c4 | 176 | |
c6f9575c JH |
177 | /* enable / disable interrupts */ |
178 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) | |
179 | temp = KSZPHY_INTCS_ALL; | |
180 | else | |
181 | temp = 0; | |
51f932c4 | 182 | |
c6f9575c | 183 | return phy_write(phydev, MII_KSZPHY_INTCS, temp); |
51f932c4 | 184 | } |
d0507009 | 185 | |
63f44b2b JH |
186 | static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) |
187 | { | |
188 | int ctrl; | |
189 | ||
190 | ctrl = phy_read(phydev, MII_KSZPHY_CTRL); | |
191 | if (ctrl < 0) | |
192 | return ctrl; | |
193 | ||
194 | if (val) | |
195 | ctrl |= KSZPHY_RMII_REF_CLK_SEL; | |
196 | else | |
197 | ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; | |
198 | ||
199 | return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); | |
200 | } | |
201 | ||
e7a792e9 | 202 | static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) |
20d8435a | 203 | { |
5a16778e | 204 | int rc, temp, shift; |
8620546c | 205 | |
5a16778e JH |
206 | switch (reg) { |
207 | case MII_KSZPHY_CTRL_1: | |
208 | shift = 14; | |
209 | break; | |
210 | case MII_KSZPHY_CTRL_2: | |
211 | shift = 4; | |
212 | break; | |
213 | default: | |
214 | return -EINVAL; | |
215 | } | |
216 | ||
20d8435a | 217 | temp = phy_read(phydev, reg); |
b7035860 JH |
218 | if (temp < 0) { |
219 | rc = temp; | |
220 | goto out; | |
221 | } | |
20d8435a | 222 | |
28bdc499 | 223 | temp &= ~(3 << shift); |
20d8435a BD |
224 | temp |= val << shift; |
225 | rc = phy_write(phydev, reg, temp); | |
b7035860 JH |
226 | out: |
227 | if (rc < 0) | |
72ba48be | 228 | phydev_err(phydev, "failed to set led mode\n"); |
20d8435a | 229 | |
b7035860 | 230 | return rc; |
20d8435a BD |
231 | } |
232 | ||
bde15129 JH |
233 | /* Disable PHY address 0 as the broadcast address, so that it can be used as a |
234 | * unique (non-broadcast) address on a shared bus. | |
235 | */ | |
236 | static int kszphy_broadcast_disable(struct phy_device *phydev) | |
237 | { | |
238 | int ret; | |
239 | ||
240 | ret = phy_read(phydev, MII_KSZPHY_OMSO); | |
241 | if (ret < 0) | |
242 | goto out; | |
243 | ||
244 | ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); | |
245 | out: | |
246 | if (ret) | |
72ba48be | 247 | phydev_err(phydev, "failed to disable broadcast address\n"); |
bde15129 JH |
248 | |
249 | return ret; | |
250 | } | |
251 | ||
2b0ba96c SR |
252 | static int kszphy_nand_tree_disable(struct phy_device *phydev) |
253 | { | |
254 | int ret; | |
255 | ||
256 | ret = phy_read(phydev, MII_KSZPHY_OMSO); | |
257 | if (ret < 0) | |
258 | goto out; | |
259 | ||
260 | if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) | |
261 | return 0; | |
262 | ||
263 | ret = phy_write(phydev, MII_KSZPHY_OMSO, | |
264 | ret & ~KSZPHY_OMSO_NAND_TREE_ON); | |
265 | out: | |
266 | if (ret) | |
72ba48be | 267 | phydev_err(phydev, "failed to disable NAND tree mode\n"); |
2b0ba96c SR |
268 | |
269 | return ret; | |
270 | } | |
271 | ||
79e498a9 LC |
272 | /* Some config bits need to be set again on resume, handle them here. */ |
273 | static int kszphy_config_reset(struct phy_device *phydev) | |
d0507009 | 274 | { |
e6a423a8 | 275 | struct kszphy_priv *priv = phydev->priv; |
63f44b2b | 276 | int ret; |
d0507009 | 277 | |
63f44b2b JH |
278 | if (priv->rmii_ref_clk_sel) { |
279 | ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); | |
280 | if (ret) { | |
72ba48be AL |
281 | phydev_err(phydev, |
282 | "failed to set rmii reference clock\n"); | |
63f44b2b JH |
283 | return ret; |
284 | } | |
285 | } | |
286 | ||
e7a792e9 | 287 | if (priv->led_mode >= 0) |
79e498a9 | 288 | kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode); |
e6a423a8 JH |
289 | |
290 | return 0; | |
20d8435a BD |
291 | } |
292 | ||
79e498a9 LC |
293 | static int kszphy_config_init(struct phy_device *phydev) |
294 | { | |
295 | struct kszphy_priv *priv = phydev->priv; | |
296 | const struct kszphy_type *type; | |
297 | ||
298 | if (!priv) | |
299 | return 0; | |
300 | ||
301 | type = priv->type; | |
302 | ||
303 | if (type->has_broadcast_disable) | |
304 | kszphy_broadcast_disable(phydev); | |
305 | ||
306 | if (type->has_nand_tree_disable) | |
307 | kszphy_nand_tree_disable(phydev); | |
308 | ||
309 | return kszphy_config_reset(phydev); | |
310 | } | |
311 | ||
77501a79 PZ |
312 | static int ksz8041_config_init(struct phy_device *phydev) |
313 | { | |
314 | struct device_node *of_node = phydev->mdio.dev.of_node; | |
315 | ||
316 | /* Limit supported and advertised modes in fiber mode */ | |
317 | if (of_property_read_bool(of_node, "micrel,fiber-mode")) { | |
318 | phydev->dev_flags |= MICREL_PHY_FXEN; | |
ffa54a23 | 319 | phydev->supported &= SUPPORTED_100baseT_Full | |
77501a79 | 320 | SUPPORTED_100baseT_Half; |
ffa54a23 KE |
321 | phydev->supported |= SUPPORTED_FIBRE; |
322 | phydev->advertising &= ADVERTISED_100baseT_Full | | |
77501a79 | 323 | ADVERTISED_100baseT_Half; |
ffa54a23 | 324 | phydev->advertising |= ADVERTISED_FIBRE; |
77501a79 PZ |
325 | phydev->autoneg = AUTONEG_DISABLE; |
326 | } | |
327 | ||
328 | return kszphy_config_init(phydev); | |
329 | } | |
330 | ||
331 | static int ksz8041_config_aneg(struct phy_device *phydev) | |
332 | { | |
333 | /* Skip auto-negotiation in fiber mode */ | |
334 | if (phydev->dev_flags & MICREL_PHY_FXEN) { | |
335 | phydev->speed = SPEED_100; | |
336 | return 0; | |
337 | } | |
338 | ||
339 | return genphy_config_aneg(phydev); | |
340 | } | |
341 | ||
954c3967 | 342 | static int ksz9021_load_values_from_of(struct phy_device *phydev, |
3c9a9f7f JA |
343 | const struct device_node *of_node, |
344 | u16 reg, | |
345 | const char *field1, const char *field2, | |
346 | const char *field3, const char *field4) | |
954c3967 SC |
347 | { |
348 | int val1 = -1; | |
349 | int val2 = -2; | |
350 | int val3 = -3; | |
351 | int val4 = -4; | |
352 | int newval; | |
353 | int matches = 0; | |
354 | ||
355 | if (!of_property_read_u32(of_node, field1, &val1)) | |
356 | matches++; | |
357 | ||
358 | if (!of_property_read_u32(of_node, field2, &val2)) | |
359 | matches++; | |
360 | ||
361 | if (!of_property_read_u32(of_node, field3, &val3)) | |
362 | matches++; | |
363 | ||
364 | if (!of_property_read_u32(of_node, field4, &val4)) | |
365 | matches++; | |
366 | ||
367 | if (!matches) | |
368 | return 0; | |
369 | ||
370 | if (matches < 4) | |
371 | newval = kszphy_extended_read(phydev, reg); | |
372 | else | |
373 | newval = 0; | |
374 | ||
375 | if (val1 != -1) | |
376 | newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); | |
377 | ||
6a119745 | 378 | if (val2 != -2) |
954c3967 SC |
379 | newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); |
380 | ||
6a119745 | 381 | if (val3 != -3) |
954c3967 SC |
382 | newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); |
383 | ||
6a119745 | 384 | if (val4 != -4) |
954c3967 SC |
385 | newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); |
386 | ||
387 | return kszphy_extended_write(phydev, reg, newval); | |
388 | } | |
389 | ||
390 | static int ksz9021_config_init(struct phy_device *phydev) | |
391 | { | |
e5a03bfd | 392 | const struct device *dev = &phydev->mdio.dev; |
3c9a9f7f | 393 | const struct device_node *of_node = dev->of_node; |
651df218 AL |
394 | const struct device *dev_walker; |
395 | ||
396 | /* The Micrel driver has a deprecated option to place phy OF | |
397 | * properties in the MAC node. Walk up the tree of devices to | |
398 | * find a device with an OF node. | |
399 | */ | |
e5a03bfd | 400 | dev_walker = &phydev->mdio.dev; |
651df218 AL |
401 | do { |
402 | of_node = dev_walker->of_node; | |
403 | dev_walker = dev_walker->parent; | |
404 | ||
405 | } while (!of_node && dev_walker); | |
954c3967 SC |
406 | |
407 | if (of_node) { | |
408 | ksz9021_load_values_from_of(phydev, of_node, | |
409 | MII_KSZPHY_CLK_CONTROL_PAD_SKEW, | |
410 | "txen-skew-ps", "txc-skew-ps", | |
411 | "rxdv-skew-ps", "rxc-skew-ps"); | |
412 | ksz9021_load_values_from_of(phydev, of_node, | |
413 | MII_KSZPHY_RX_DATA_PAD_SKEW, | |
414 | "rxd0-skew-ps", "rxd1-skew-ps", | |
415 | "rxd2-skew-ps", "rxd3-skew-ps"); | |
416 | ksz9021_load_values_from_of(phydev, of_node, | |
417 | MII_KSZPHY_TX_DATA_PAD_SKEW, | |
418 | "txd0-skew-ps", "txd1-skew-ps", | |
419 | "txd2-skew-ps", "txd3-skew-ps"); | |
420 | } | |
421 | return 0; | |
422 | } | |
423 | ||
6e4b8273 HC |
424 | #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d |
425 | #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e | |
426 | #define OP_DATA 1 | |
427 | #define KSZ9031_PS_TO_REG 60 | |
428 | ||
429 | /* Extended registers */ | |
6270e1ae JA |
430 | /* MMD Address 0x0 */ |
431 | #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 | |
432 | #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 | |
433 | ||
ae6c97bb | 434 | /* MMD Address 0x2 */ |
6e4b8273 HC |
435 | #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 |
436 | #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 | |
437 | #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 | |
438 | #define MII_KSZ9031RN_CLK_PAD_SKEW 8 | |
439 | ||
af70c1f9 ML |
440 | /* MMD Address 0x1C */ |
441 | #define MII_KSZ9031RN_EDPD 0x23 | |
442 | #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) | |
443 | ||
6e4b8273 HC |
444 | static int ksz9031_extended_write(struct phy_device *phydev, |
445 | u8 mode, u32 dev_addr, u32 regnum, u16 val) | |
446 | { | |
447 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); | |
448 | phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); | |
449 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); | |
450 | return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val); | |
451 | } | |
452 | ||
453 | static int ksz9031_extended_read(struct phy_device *phydev, | |
454 | u8 mode, u32 dev_addr, u32 regnum) | |
455 | { | |
456 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); | |
457 | phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); | |
458 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); | |
459 | return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG); | |
460 | } | |
461 | ||
462 | static int ksz9031_of_load_skew_values(struct phy_device *phydev, | |
3c9a9f7f | 463 | const struct device_node *of_node, |
6e4b8273 | 464 | u16 reg, size_t field_sz, |
3c9a9f7f | 465 | const char *field[], u8 numfields) |
6e4b8273 HC |
466 | { |
467 | int val[4] = {-1, -2, -3, -4}; | |
468 | int matches = 0; | |
469 | u16 mask; | |
470 | u16 maxval; | |
471 | u16 newval; | |
472 | int i; | |
473 | ||
474 | for (i = 0; i < numfields; i++) | |
475 | if (!of_property_read_u32(of_node, field[i], val + i)) | |
476 | matches++; | |
477 | ||
478 | if (!matches) | |
479 | return 0; | |
480 | ||
481 | if (matches < numfields) | |
482 | newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg); | |
483 | else | |
484 | newval = 0; | |
485 | ||
486 | maxval = (field_sz == 4) ? 0xf : 0x1f; | |
487 | for (i = 0; i < numfields; i++) | |
488 | if (val[i] != -(i + 1)) { | |
489 | mask = 0xffff; | |
490 | mask ^= maxval << (field_sz * i); | |
491 | newval = (newval & mask) | | |
492 | (((val[i] / KSZ9031_PS_TO_REG) & maxval) | |
493 | << (field_sz * i)); | |
494 | } | |
495 | ||
496 | return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); | |
497 | } | |
498 | ||
a0da456b | 499 | /* Center KSZ9031RNX FLP timing at 16ms. */ |
6270e1ae JA |
500 | static int ksz9031_center_flp_timing(struct phy_device *phydev) |
501 | { | |
502 | int result; | |
503 | ||
6270e1ae JA |
504 | result = ksz9031_extended_write(phydev, OP_DATA, 0, |
505 | MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006); | |
a0da456b MU |
506 | if (result) |
507 | return result; | |
508 | ||
6270e1ae JA |
509 | result = ksz9031_extended_write(phydev, OP_DATA, 0, |
510 | MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80); | |
6270e1ae JA |
511 | if (result) |
512 | return result; | |
513 | ||
514 | return genphy_restart_aneg(phydev); | |
515 | } | |
516 | ||
af70c1f9 ML |
517 | /* Enable energy-detect power-down mode */ |
518 | static int ksz9031_enable_edpd(struct phy_device *phydev) | |
519 | { | |
520 | int reg; | |
521 | ||
522 | reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD); | |
523 | if (reg < 0) | |
524 | return reg; | |
525 | return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD, | |
526 | reg | MII_KSZ9031RN_EDPD_ENABLE); | |
527 | } | |
528 | ||
6e4b8273 HC |
529 | static int ksz9031_config_init(struct phy_device *phydev) |
530 | { | |
e5a03bfd | 531 | const struct device *dev = &phydev->mdio.dev; |
3c9a9f7f JA |
532 | const struct device_node *of_node = dev->of_node; |
533 | static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; | |
534 | static const char *rx_data_skews[4] = { | |
6e4b8273 HC |
535 | "rxd0-skew-ps", "rxd1-skew-ps", |
536 | "rxd2-skew-ps", "rxd3-skew-ps" | |
537 | }; | |
3c9a9f7f | 538 | static const char *tx_data_skews[4] = { |
6e4b8273 HC |
539 | "txd0-skew-ps", "txd1-skew-ps", |
540 | "txd2-skew-ps", "txd3-skew-ps" | |
541 | }; | |
3c9a9f7f | 542 | static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; |
b4c19f71 | 543 | const struct device *dev_walker; |
af70c1f9 ML |
544 | int result; |
545 | ||
546 | result = ksz9031_enable_edpd(phydev); | |
547 | if (result < 0) | |
548 | return result; | |
6e4b8273 | 549 | |
b4c19f71 RH |
550 | /* The Micrel driver has a deprecated option to place phy OF |
551 | * properties in the MAC node. Walk up the tree of devices to | |
552 | * find a device with an OF node. | |
553 | */ | |
9d367edd | 554 | dev_walker = &phydev->mdio.dev; |
b4c19f71 RH |
555 | do { |
556 | of_node = dev_walker->of_node; | |
557 | dev_walker = dev_walker->parent; | |
558 | } while (!of_node && dev_walker); | |
6e4b8273 HC |
559 | |
560 | if (of_node) { | |
561 | ksz9031_of_load_skew_values(phydev, of_node, | |
562 | MII_KSZ9031RN_CLK_PAD_SKEW, 5, | |
563 | clk_skews, 2); | |
564 | ||
565 | ksz9031_of_load_skew_values(phydev, of_node, | |
566 | MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, | |
567 | control_skews, 2); | |
568 | ||
569 | ksz9031_of_load_skew_values(phydev, of_node, | |
570 | MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, | |
571 | rx_data_skews, 4); | |
572 | ||
573 | ksz9031_of_load_skew_values(phydev, of_node, | |
574 | MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, | |
575 | tx_data_skews, 4); | |
576 | } | |
6270e1ae JA |
577 | |
578 | return ksz9031_center_flp_timing(phydev); | |
6e4b8273 HC |
579 | } |
580 | ||
93272e07 | 581 | #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 |
00aee095 JH |
582 | #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) |
583 | #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) | |
32d73b14 | 584 | static int ksz8873mll_read_status(struct phy_device *phydev) |
93272e07 JCPV |
585 | { |
586 | int regval; | |
587 | ||
588 | /* dummy read */ | |
589 | regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); | |
590 | ||
591 | regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); | |
592 | ||
593 | if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) | |
594 | phydev->duplex = DUPLEX_HALF; | |
595 | else | |
596 | phydev->duplex = DUPLEX_FULL; | |
597 | ||
598 | if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) | |
599 | phydev->speed = SPEED_10; | |
600 | else | |
601 | phydev->speed = SPEED_100; | |
602 | ||
603 | phydev->link = 1; | |
604 | phydev->pause = phydev->asym_pause = 0; | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
d2fd719b NS |
609 | static int ksz9031_read_status(struct phy_device *phydev) |
610 | { | |
611 | int err; | |
612 | int regval; | |
613 | ||
614 | err = genphy_read_status(phydev); | |
615 | if (err) | |
616 | return err; | |
617 | ||
618 | /* Make sure the PHY is not broken. Read idle error count, | |
619 | * and reset the PHY if it is maxed out. | |
620 | */ | |
621 | regval = phy_read(phydev, MII_STAT1000); | |
622 | if ((regval & 0xFF) == 0xFF) { | |
623 | phy_init_hw(phydev); | |
624 | phydev->link = 0; | |
b866203d ZB |
625 | if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev)) |
626 | phydev->drv->config_intr(phydev); | |
c1a8d0a3 | 627 | return genphy_config_aneg(phydev); |
d2fd719b NS |
628 | } |
629 | ||
630 | return 0; | |
631 | } | |
632 | ||
93272e07 JCPV |
633 | static int ksz8873mll_config_aneg(struct phy_device *phydev) |
634 | { | |
635 | return 0; | |
636 | } | |
637 | ||
19936942 VB |
638 | /* This routine returns -1 as an indication to the caller that the |
639 | * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE | |
640 | * MMD extended PHY registers. | |
641 | */ | |
642 | static int | |
d11437e0 | 643 | ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum) |
19936942 VB |
644 | { |
645 | return -1; | |
646 | } | |
647 | ||
648 | /* This routine does nothing since the Micrel ksz9021 does not support | |
649 | * standard IEEE MMD extended PHY registers. | |
650 | */ | |
d11437e0 RK |
651 | static int |
652 | ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int devad, u16 regnum, u16 val) | |
19936942 | 653 | { |
d11437e0 | 654 | return -1; |
19936942 VB |
655 | } |
656 | ||
2b2427d0 AL |
657 | static int kszphy_get_sset_count(struct phy_device *phydev) |
658 | { | |
659 | return ARRAY_SIZE(kszphy_hw_stats); | |
660 | } | |
661 | ||
662 | static void kszphy_get_strings(struct phy_device *phydev, u8 *data) | |
663 | { | |
664 | int i; | |
665 | ||
666 | for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { | |
667 | memcpy(data + i * ETH_GSTRING_LEN, | |
668 | kszphy_hw_stats[i].string, ETH_GSTRING_LEN); | |
669 | } | |
670 | } | |
671 | ||
672 | #ifndef UINT64_MAX | |
673 | #define UINT64_MAX (u64)(~((u64)0)) | |
674 | #endif | |
675 | static u64 kszphy_get_stat(struct phy_device *phydev, int i) | |
676 | { | |
677 | struct kszphy_hw_stat stat = kszphy_hw_stats[i]; | |
678 | struct kszphy_priv *priv = phydev->priv; | |
321b4d4b AL |
679 | int val; |
680 | u64 ret; | |
2b2427d0 AL |
681 | |
682 | val = phy_read(phydev, stat.reg); | |
683 | if (val < 0) { | |
321b4d4b | 684 | ret = UINT64_MAX; |
2b2427d0 AL |
685 | } else { |
686 | val = val & ((1 << stat.bits) - 1); | |
687 | priv->stats[i] += val; | |
321b4d4b | 688 | ret = priv->stats[i]; |
2b2427d0 AL |
689 | } |
690 | ||
321b4d4b | 691 | return ret; |
2b2427d0 AL |
692 | } |
693 | ||
694 | static void kszphy_get_stats(struct phy_device *phydev, | |
695 | struct ethtool_stats *stats, u64 *data) | |
696 | { | |
697 | int i; | |
698 | ||
699 | for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) | |
700 | data[i] = kszphy_get_stat(phydev, i); | |
701 | } | |
702 | ||
836384d2 | 703 | static int kszphy_suspend(struct phy_device *phydev) |
f5aba91d | 704 | { |
836384d2 WY |
705 | /* Disable PHY Interrupts */ |
706 | if (phy_interrupt_is_valid(phydev)) { | |
707 | phydev->interrupts = PHY_INTERRUPT_DISABLED; | |
708 | if (phydev->drv->config_intr) | |
709 | phydev->drv->config_intr(phydev); | |
710 | } | |
f5aba91d | 711 | |
836384d2 WY |
712 | return genphy_suspend(phydev); |
713 | } | |
f5aba91d | 714 | |
836384d2 WY |
715 | static int kszphy_resume(struct phy_device *phydev) |
716 | { | |
79e498a9 LC |
717 | int ret; |
718 | ||
836384d2 | 719 | genphy_resume(phydev); |
f5aba91d | 720 | |
79e498a9 LC |
721 | ret = kszphy_config_reset(phydev); |
722 | if (ret) | |
723 | return ret; | |
724 | ||
836384d2 WY |
725 | /* Enable PHY Interrupts */ |
726 | if (phy_interrupt_is_valid(phydev)) { | |
727 | phydev->interrupts = PHY_INTERRUPT_ENABLED; | |
728 | if (phydev->drv->config_intr) | |
729 | phydev->drv->config_intr(phydev); | |
730 | } | |
f5aba91d AB |
731 | |
732 | return 0; | |
733 | } | |
734 | ||
e6a423a8 JH |
735 | static int kszphy_probe(struct phy_device *phydev) |
736 | { | |
737 | const struct kszphy_type *type = phydev->drv->driver_data; | |
e5a03bfd | 738 | const struct device_node *np = phydev->mdio.dev.of_node; |
e6a423a8 | 739 | struct kszphy_priv *priv; |
63f44b2b | 740 | struct clk *clk; |
e7a792e9 | 741 | int ret; |
e6a423a8 | 742 | |
e5a03bfd | 743 | priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); |
e6a423a8 JH |
744 | if (!priv) |
745 | return -ENOMEM; | |
746 | ||
747 | phydev->priv = priv; | |
748 | ||
749 | priv->type = type; | |
750 | ||
e7a792e9 JH |
751 | if (type->led_mode_reg) { |
752 | ret = of_property_read_u32(np, "micrel,led-mode", | |
753 | &priv->led_mode); | |
754 | if (ret) | |
755 | priv->led_mode = -1; | |
756 | ||
757 | if (priv->led_mode > 3) { | |
72ba48be AL |
758 | phydev_err(phydev, "invalid led mode: 0x%02x\n", |
759 | priv->led_mode); | |
e7a792e9 JH |
760 | priv->led_mode = -1; |
761 | } | |
762 | } else { | |
763 | priv->led_mode = -1; | |
764 | } | |
765 | ||
e5a03bfd | 766 | clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); |
bced8701 NC |
767 | /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ |
768 | if (!IS_ERR_OR_NULL(clk)) { | |
1fadee0c | 769 | unsigned long rate = clk_get_rate(clk); |
86dc1342 | 770 | bool rmii_ref_clk_sel_25_mhz; |
1fadee0c | 771 | |
63f44b2b | 772 | priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; |
86dc1342 JH |
773 | rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, |
774 | "micrel,rmii-reference-clock-select-25-mhz"); | |
63f44b2b | 775 | |
1fadee0c | 776 | if (rate > 24500000 && rate < 25500000) { |
86dc1342 | 777 | priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; |
1fadee0c | 778 | } else if (rate > 49500000 && rate < 50500000) { |
86dc1342 | 779 | priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; |
1fadee0c | 780 | } else { |
72ba48be AL |
781 | phydev_err(phydev, "Clock rate out of range: %ld\n", |
782 | rate); | |
1fadee0c SH |
783 | return -EINVAL; |
784 | } | |
785 | } | |
786 | ||
63f44b2b JH |
787 | /* Support legacy board-file configuration */ |
788 | if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { | |
789 | priv->rmii_ref_clk_sel = true; | |
790 | priv->rmii_ref_clk_sel_val = true; | |
791 | } | |
792 | ||
793 | return 0; | |
1fadee0c SH |
794 | } |
795 | ||
d5bf9071 CH |
796 | static struct phy_driver ksphy_driver[] = { |
797 | { | |
51f932c4 | 798 | .phy_id = PHY_ID_KS8737, |
f893a99e | 799 | .phy_id_mask = MICREL_PHY_ID_MASK, |
51f932c4 | 800 | .name = "Micrel KS8737", |
529ed127 | 801 | .features = PHY_BASIC_FEATURES, |
1b86f702 | 802 | .flags = PHY_HAS_INTERRUPT, |
c6f9575c | 803 | .driver_data = &ks8737_type, |
51f932c4 CD |
804 | .config_init = kszphy_config_init, |
805 | .config_aneg = genphy_config_aneg, | |
806 | .read_status = genphy_read_status, | |
807 | .ack_interrupt = kszphy_ack_interrupt, | |
c6f9575c | 808 | .config_intr = kszphy_config_intr, |
1a5465f5 PV |
809 | .suspend = genphy_suspend, |
810 | .resume = genphy_resume, | |
212ea99a MV |
811 | }, { |
812 | .phy_id = PHY_ID_KSZ8021, | |
813 | .phy_id_mask = 0x00ffffff, | |
7ab59dc1 | 814 | .name = "Micrel KSZ8021 or KSZ8031", |
529ed127 | 815 | .features = PHY_BASIC_FEATURES, |
1b86f702 | 816 | .flags = PHY_HAS_INTERRUPT, |
e6a423a8 | 817 | .driver_data = &ksz8021_type, |
63f44b2b | 818 | .probe = kszphy_probe, |
d0e1df9c | 819 | .config_init = kszphy_config_init, |
212ea99a MV |
820 | .config_aneg = genphy_config_aneg, |
821 | .read_status = genphy_read_status, | |
822 | .ack_interrupt = kszphy_ack_interrupt, | |
823 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
824 | .get_sset_count = kszphy_get_sset_count, |
825 | .get_strings = kszphy_get_strings, | |
826 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
827 | .suspend = genphy_suspend, |
828 | .resume = genphy_resume, | |
b818d1a7 HP |
829 | }, { |
830 | .phy_id = PHY_ID_KSZ8031, | |
831 | .phy_id_mask = 0x00ffffff, | |
832 | .name = "Micrel KSZ8031", | |
529ed127 | 833 | .features = PHY_BASIC_FEATURES, |
1b86f702 | 834 | .flags = PHY_HAS_INTERRUPT, |
e6a423a8 | 835 | .driver_data = &ksz8021_type, |
63f44b2b | 836 | .probe = kszphy_probe, |
d0e1df9c | 837 | .config_init = kszphy_config_init, |
b818d1a7 HP |
838 | .config_aneg = genphy_config_aneg, |
839 | .read_status = genphy_read_status, | |
840 | .ack_interrupt = kszphy_ack_interrupt, | |
841 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
842 | .get_sset_count = kszphy_get_sset_count, |
843 | .get_strings = kszphy_get_strings, | |
844 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
845 | .suspend = genphy_suspend, |
846 | .resume = genphy_resume, | |
d5bf9071 | 847 | }, { |
510d573f | 848 | .phy_id = PHY_ID_KSZ8041, |
f893a99e | 849 | .phy_id_mask = MICREL_PHY_ID_MASK, |
510d573f | 850 | .name = "Micrel KSZ8041", |
529ed127 | 851 | .features = PHY_BASIC_FEATURES, |
1b86f702 | 852 | .flags = PHY_HAS_INTERRUPT, |
e6a423a8 JH |
853 | .driver_data = &ksz8041_type, |
854 | .probe = kszphy_probe, | |
77501a79 PZ |
855 | .config_init = ksz8041_config_init, |
856 | .config_aneg = ksz8041_config_aneg, | |
51f932c4 CD |
857 | .read_status = genphy_read_status, |
858 | .ack_interrupt = kszphy_ack_interrupt, | |
859 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
860 | .get_sset_count = kszphy_get_sset_count, |
861 | .get_strings = kszphy_get_strings, | |
862 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
863 | .suspend = genphy_suspend, |
864 | .resume = genphy_resume, | |
4bd7b512 SS |
865 | }, { |
866 | .phy_id = PHY_ID_KSZ8041RNLI, | |
f893a99e | 867 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4bd7b512 | 868 | .name = "Micrel KSZ8041RNLI", |
529ed127 | 869 | .features = PHY_BASIC_FEATURES, |
1b86f702 | 870 | .flags = PHY_HAS_INTERRUPT, |
e6a423a8 JH |
871 | .driver_data = &ksz8041_type, |
872 | .probe = kszphy_probe, | |
873 | .config_init = kszphy_config_init, | |
4bd7b512 SS |
874 | .config_aneg = genphy_config_aneg, |
875 | .read_status = genphy_read_status, | |
876 | .ack_interrupt = kszphy_ack_interrupt, | |
877 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
878 | .get_sset_count = kszphy_get_sset_count, |
879 | .get_strings = kszphy_get_strings, | |
880 | .get_stats = kszphy_get_stats, | |
4bd7b512 SS |
881 | .suspend = genphy_suspend, |
882 | .resume = genphy_resume, | |
d5bf9071 | 883 | }, { |
510d573f | 884 | .phy_id = PHY_ID_KSZ8051, |
f893a99e | 885 | .phy_id_mask = MICREL_PHY_ID_MASK, |
510d573f | 886 | .name = "Micrel KSZ8051", |
529ed127 | 887 | .features = PHY_BASIC_FEATURES, |
1b86f702 | 888 | .flags = PHY_HAS_INTERRUPT, |
e6a423a8 JH |
889 | .driver_data = &ksz8051_type, |
890 | .probe = kszphy_probe, | |
63f44b2b | 891 | .config_init = kszphy_config_init, |
d0507009 DC |
892 | .config_aneg = genphy_config_aneg, |
893 | .read_status = genphy_read_status, | |
51f932c4 CD |
894 | .ack_interrupt = kszphy_ack_interrupt, |
895 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
896 | .get_sset_count = kszphy_get_sset_count, |
897 | .get_strings = kszphy_get_strings, | |
898 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
899 | .suspend = genphy_suspend, |
900 | .resume = genphy_resume, | |
d5bf9071 | 901 | }, { |
510d573f MV |
902 | .phy_id = PHY_ID_KSZ8001, |
903 | .name = "Micrel KSZ8001 or KS8721", | |
ecd5a323 | 904 | .phy_id_mask = 0x00fffffc, |
529ed127 | 905 | .features = PHY_BASIC_FEATURES, |
1b86f702 | 906 | .flags = PHY_HAS_INTERRUPT, |
e6a423a8 JH |
907 | .driver_data = &ksz8041_type, |
908 | .probe = kszphy_probe, | |
909 | .config_init = kszphy_config_init, | |
d0507009 DC |
910 | .config_aneg = genphy_config_aneg, |
911 | .read_status = genphy_read_status, | |
51f932c4 CD |
912 | .ack_interrupt = kszphy_ack_interrupt, |
913 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
914 | .get_sset_count = kszphy_get_sset_count, |
915 | .get_strings = kszphy_get_strings, | |
916 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
917 | .suspend = genphy_suspend, |
918 | .resume = genphy_resume, | |
7ab59dc1 DC |
919 | }, { |
920 | .phy_id = PHY_ID_KSZ8081, | |
921 | .name = "Micrel KSZ8081 or KSZ8091", | |
f893a99e | 922 | .phy_id_mask = MICREL_PHY_ID_MASK, |
529ed127 | 923 | .features = PHY_BASIC_FEATURES, |
1b86f702 | 924 | .flags = PHY_HAS_INTERRUPT, |
e6a423a8 JH |
925 | .driver_data = &ksz8081_type, |
926 | .probe = kszphy_probe, | |
0f95903e | 927 | .config_init = kszphy_config_init, |
7ab59dc1 DC |
928 | .config_aneg = genphy_config_aneg, |
929 | .read_status = genphy_read_status, | |
930 | .ack_interrupt = kszphy_ack_interrupt, | |
931 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
932 | .get_sset_count = kszphy_get_sset_count, |
933 | .get_strings = kszphy_get_strings, | |
934 | .get_stats = kszphy_get_stats, | |
836384d2 | 935 | .suspend = kszphy_suspend, |
f5aba91d | 936 | .resume = kszphy_resume, |
7ab59dc1 DC |
937 | }, { |
938 | .phy_id = PHY_ID_KSZ8061, | |
939 | .name = "Micrel KSZ8061", | |
f893a99e | 940 | .phy_id_mask = MICREL_PHY_ID_MASK, |
529ed127 | 941 | .features = PHY_BASIC_FEATURES, |
1b86f702 | 942 | .flags = PHY_HAS_INTERRUPT, |
7ab59dc1 DC |
943 | .config_init = kszphy_config_init, |
944 | .config_aneg = genphy_config_aneg, | |
945 | .read_status = genphy_read_status, | |
946 | .ack_interrupt = kszphy_ack_interrupt, | |
947 | .config_intr = kszphy_config_intr, | |
1a5465f5 PV |
948 | .suspend = genphy_suspend, |
949 | .resume = genphy_resume, | |
d5bf9071 | 950 | }, { |
d0507009 | 951 | .phy_id = PHY_ID_KSZ9021, |
48d7d0ad | 952 | .phy_id_mask = 0x000ffffe, |
d0507009 | 953 | .name = "Micrel KSZ9021 Gigabit PHY", |
529ed127 | 954 | .features = PHY_GBIT_FEATURES, |
1b86f702 | 955 | .flags = PHY_HAS_INTERRUPT, |
c6f9575c | 956 | .driver_data = &ksz9021_type, |
bfe72442 | 957 | .probe = kszphy_probe, |
954c3967 | 958 | .config_init = ksz9021_config_init, |
d0507009 DC |
959 | .config_aneg = genphy_config_aneg, |
960 | .read_status = genphy_read_status, | |
51f932c4 | 961 | .ack_interrupt = kszphy_ack_interrupt, |
c6f9575c | 962 | .config_intr = kszphy_config_intr, |
2b2427d0 AL |
963 | .get_sset_count = kszphy_get_sset_count, |
964 | .get_strings = kszphy_get_strings, | |
965 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
966 | .suspend = genphy_suspend, |
967 | .resume = genphy_resume, | |
d11437e0 RK |
968 | .read_mmd = ksz9021_rd_mmd_phyreg, |
969 | .write_mmd = ksz9021_wr_mmd_phyreg, | |
7ab59dc1 DC |
970 | }, { |
971 | .phy_id = PHY_ID_KSZ9031, | |
f893a99e | 972 | .phy_id_mask = MICREL_PHY_ID_MASK, |
7ab59dc1 | 973 | .name = "Micrel KSZ9031 Gigabit PHY", |
529ed127 | 974 | .features = PHY_GBIT_FEATURES, |
1b86f702 | 975 | .flags = PHY_HAS_INTERRUPT, |
c6f9575c | 976 | .driver_data = &ksz9021_type, |
bfe72442 | 977 | .probe = kszphy_probe, |
6e4b8273 | 978 | .config_init = ksz9031_config_init, |
7ab59dc1 | 979 | .config_aneg = genphy_config_aneg, |
d2fd719b | 980 | .read_status = ksz9031_read_status, |
7ab59dc1 | 981 | .ack_interrupt = kszphy_ack_interrupt, |
c6f9575c | 982 | .config_intr = kszphy_config_intr, |
2b2427d0 AL |
983 | .get_sset_count = kszphy_get_sset_count, |
984 | .get_strings = kszphy_get_strings, | |
985 | .get_stats = kszphy_get_stats, | |
1a5465f5 | 986 | .suspend = genphy_suspend, |
f64f1482 | 987 | .resume = kszphy_resume, |
93272e07 JCPV |
988 | }, { |
989 | .phy_id = PHY_ID_KSZ8873MLL, | |
f893a99e | 990 | .phy_id_mask = MICREL_PHY_ID_MASK, |
93272e07 | 991 | .name = "Micrel KSZ8873MLL Switch", |
93272e07 JCPV |
992 | .config_init = kszphy_config_init, |
993 | .config_aneg = ksz8873mll_config_aneg, | |
994 | .read_status = ksz8873mll_read_status, | |
1a5465f5 PV |
995 | .suspend = genphy_suspend, |
996 | .resume = genphy_resume, | |
7ab59dc1 DC |
997 | }, { |
998 | .phy_id = PHY_ID_KSZ886X, | |
f893a99e | 999 | .phy_id_mask = MICREL_PHY_ID_MASK, |
7ab59dc1 | 1000 | .name = "Micrel KSZ886X Switch", |
529ed127 | 1001 | .features = PHY_BASIC_FEATURES, |
1b86f702 | 1002 | .flags = PHY_HAS_INTERRUPT, |
7ab59dc1 DC |
1003 | .config_init = kszphy_config_init, |
1004 | .config_aneg = genphy_config_aneg, | |
1005 | .read_status = genphy_read_status, | |
1a5465f5 PV |
1006 | .suspend = genphy_suspend, |
1007 | .resume = genphy_resume, | |
9d162ed6 SN |
1008 | }, { |
1009 | .phy_id = PHY_ID_KSZ8795, | |
1010 | .phy_id_mask = MICREL_PHY_ID_MASK, | |
1011 | .name = "Micrel KSZ8795", | |
cf626c3b | 1012 | .features = PHY_BASIC_FEATURES, |
1b86f702 | 1013 | .flags = PHY_HAS_INTERRUPT, |
9d162ed6 SN |
1014 | .config_init = kszphy_config_init, |
1015 | .config_aneg = ksz8873mll_config_aneg, | |
1016 | .read_status = ksz8873mll_read_status, | |
9d162ed6 SN |
1017 | .suspend = genphy_suspend, |
1018 | .resume = genphy_resume, | |
fc3973a1 WH |
1019 | }, { |
1020 | .phy_id = PHY_ID_KSZ9477, | |
1021 | .phy_id_mask = MICREL_PHY_ID_MASK, | |
1022 | .name = "Microchip KSZ9477", | |
1023 | .features = PHY_GBIT_FEATURES, | |
1024 | .config_init = kszphy_config_init, | |
1025 | .config_aneg = genphy_config_aneg, | |
1026 | .read_status = genphy_read_status, | |
1027 | .suspend = genphy_suspend, | |
1028 | .resume = genphy_resume, | |
d5bf9071 | 1029 | } }; |
d0507009 | 1030 | |
50fd7150 | 1031 | module_phy_driver(ksphy_driver); |
d0507009 DC |
1032 | |
1033 | MODULE_DESCRIPTION("Micrel PHY driver"); | |
1034 | MODULE_AUTHOR("David J. Choi"); | |
1035 | MODULE_LICENSE("GPL"); | |
52a60ed2 | 1036 | |
cf93c945 | 1037 | static struct mdio_device_id __maybe_unused micrel_tbl[] = { |
48d7d0ad | 1038 | { PHY_ID_KSZ9021, 0x000ffffe }, |
f893a99e | 1039 | { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, |
ecd5a323 | 1040 | { PHY_ID_KSZ8001, 0x00fffffc }, |
f893a99e | 1041 | { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, |
212ea99a | 1042 | { PHY_ID_KSZ8021, 0x00ffffff }, |
b818d1a7 | 1043 | { PHY_ID_KSZ8031, 0x00ffffff }, |
f893a99e FE |
1044 | { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, |
1045 | { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, | |
1046 | { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, | |
1047 | { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, | |
1048 | { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, | |
1049 | { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, | |
52a60ed2 DM |
1050 | { } |
1051 | }; | |
1052 | ||
1053 | MODULE_DEVICE_TABLE(mdio, micrel_tbl); |