]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/phy/micrel.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge tag 'regmap-v3.17-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie...
[mirror_ubuntu-artful-kernel.git] / drivers / net / phy / micrel.c
CommitLineData
d0507009
DC		 1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
7ab59dc1 8 * Copyright (c) 2010-2013 Micrel, Inc.
d0507009
DC		 9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
7ab59dc1
DC		 15 * Support : Micrel Phys:
16 * Giga phys: ksz9021, ksz9031
17 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
18 * ksz8021, ksz8031, ksz8051,
19 * ksz8081, ksz8091,
20 * ksz8061,
21 * Switch : ksz8873, ksz886x
d0507009
DC		 22 */
23
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/phy.h>
d606ef3f 27#include <linux/micrel_phy.h>
954c3967 28#include <linux/of.h>
d0507009 29
212ea99a
MV		 30/* Operation Mode Strap Override */
31#define MII_KSZPHY_OMSO 0x16
32#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
33#define KSZPHY_OMSO_RMII_OVERRIDE (1 << 1)
34#define KSZPHY_OMSO_MII_OVERRIDE (1 << 0)
35
51f932c4
CD		 36/* general Interrupt control/status reg in vendor specific block. */
37#define MII_KSZPHY_INTCS 0x1B
38#define KSZPHY_INTCS_JABBER (1 << 15)
39#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
40#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
41#define KSZPHY_INTCS_PARELLEL (1 << 12)
42#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
43#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
44#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
45#define KSZPHY_INTCS_LINK_UP (1 << 8)
46#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
47 KSZPHY_INTCS_LINK_DOWN)
48
49/* general PHY control reg in vendor specific block. */
50#define MII_KSZPHY_CTRL 0x1F
51/* bitmap of PHY register to set interrupt mode */
52#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
53#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
54#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
d606ef3f 55#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
51f932c4 56
954c3967
SC		 57/* Write/read to/from extended registers */
58#define MII_KSZPHY_EXTREG 0x0b
59#define KSZPHY_EXTREG_WRITE 0x8000
60
61#define MII_KSZPHY_EXTREG_WRITE 0x0c
62#define MII_KSZPHY_EXTREG_READ 0x0d
63
64/* Extended registers */
65#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
66#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
67#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
68
69#define PS_TO_REG 200
70
b6bb4dfc
HP		 71static int ksz_config_flags(struct phy_device *phydev)
72{
73 int regval;
74
75 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
76 regval = phy_read(phydev, MII_KSZPHY_CTRL);
77 regval |= KSZ8051_RMII_50MHZ_CLK;
78 return phy_write(phydev, MII_KSZPHY_CTRL, regval);
79 }
80 return 0;
81}
82
954c3967 83static int kszphy_extended_write(struct phy_device *phydev,
756b5089 84 u32 regnum, u16 val)
954c3967
SC		 85{
86 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
87 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
88}
89
90static int kszphy_extended_read(struct phy_device *phydev,
756b5089 91 u32 regnum)
954c3967
SC		 92{
93 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
94 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
95}
96
51f932c4
CD		 97static int kszphy_ack_interrupt(struct phy_device *phydev)
98{
99 /* bit[7..0] int status, which is a read and clear register. */
100 int rc;
101
102 rc = phy_read(phydev, MII_KSZPHY_INTCS);
103
104 return (rc < 0) ? rc : 0;
105}
106
107static int kszphy_set_interrupt(struct phy_device *phydev)
108{
109 int temp;
110 temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
111 KSZPHY_INTCS_ALL : 0;
112 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
113}
114
115static int kszphy_config_intr(struct phy_device *phydev)
116{
117 int temp, rc;
118
119 /* set the interrupt pin active low */
120 temp = phy_read(phydev, MII_KSZPHY_CTRL);
121 temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
122 phy_write(phydev, MII_KSZPHY_CTRL, temp);
123 rc = kszphy_set_interrupt(phydev);
124 return rc < 0 ? rc : 0;
125}
126
127static int ksz9021_config_intr(struct phy_device *phydev)
128{
129 int temp, rc;
130
131 /* set the interrupt pin active low */
132 temp = phy_read(phydev, MII_KSZPHY_CTRL);
133 temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
134 phy_write(phydev, MII_KSZPHY_CTRL, temp);
135 rc = kszphy_set_interrupt(phydev);
136 return rc < 0 ? rc : 0;
137}
138
139static int ks8737_config_intr(struct phy_device *phydev)
140{
141 int temp, rc;
142
143 /* set the interrupt pin active low */
144 temp = phy_read(phydev, MII_KSZPHY_CTRL);
145 temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
146 phy_write(phydev, MII_KSZPHY_CTRL, temp);
147 rc = kszphy_set_interrupt(phydev);
148 return rc < 0 ? rc : 0;
149}
d0507009 150
20d8435a
BD		 151static int kszphy_setup_led(struct phy_device *phydev,
152 unsigned int reg, unsigned int shift)
153{
154
155 struct device *dev = &phydev->dev;
156 struct device_node *of_node = dev->of_node;
157 int rc, temp;
158 u32 val;
159
160 if (!of_node && dev->parent->of_node)
161 of_node = dev->parent->of_node;
162
163 if (of_property_read_u32(of_node, "micrel,led-mode", &val))
164 return 0;
165
166 temp = phy_read(phydev, reg);
167 if (temp < 0)
168 return temp;
169
28bdc499 170 temp &= ~(3 << shift);
20d8435a
BD		 171 temp |= val << shift;
172 rc = phy_write(phydev, reg, temp);
173
174 return rc < 0 ? rc : 0;
175}
176
d0507009
DC		 177static int kszphy_config_init(struct phy_device *phydev)
178{
179 return 0;
180}
181
20d8435a
BD		 182static int kszphy_config_init_led8041(struct phy_device *phydev)
183{
184 /* single led control, register 0x1e bits 15..14 */
185 return kszphy_setup_led(phydev, 0x1e, 14);
186}
187
212ea99a
MV		 188static int ksz8021_config_init(struct phy_device *phydev)
189{
190 const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
20d8435a
BD		 191 int rc;
192
193 rc = kszphy_setup_led(phydev, 0x1f, 4);
194 if (rc)
195 dev_err(&phydev->dev, "failed to set led mode\n");
196
212ea99a 197 phy_write(phydev, MII_KSZPHY_OMSO, val);
b6bb4dfc
HP		 198 rc = ksz_config_flags(phydev);
199 return rc < 0 ? rc : 0;
212ea99a
MV		 200}
201
d606ef3f
BS		 202static int ks8051_config_init(struct phy_device *phydev)
203{
b6bb4dfc 204 int rc;
d606ef3f 205
20d8435a
BD		 206 rc = kszphy_setup_led(phydev, 0x1f, 4);
207 if (rc)
208 dev_err(&phydev->dev, "failed to set led mode\n");
209
b6bb4dfc
HP		 210 rc = ksz_config_flags(phydev);
211 return rc < 0 ? rc : 0;
d606ef3f
BS		 212}
213
954c3967
SC		 214static int ksz9021_load_values_from_of(struct phy_device *phydev,
215 struct device_node *of_node, u16 reg,
216 char *field1, char *field2,
217 char *field3, char *field4)
218{
219 int val1 = -1;
220 int val2 = -2;
221 int val3 = -3;
222 int val4 = -4;
223 int newval;
224 int matches = 0;
225
226 if (!of_property_read_u32(of_node, field1, &val1))
227 matches++;
228
229 if (!of_property_read_u32(of_node, field2, &val2))
230 matches++;
231
232 if (!of_property_read_u32(of_node, field3, &val3))
233 matches++;
234
235 if (!of_property_read_u32(of_node, field4, &val4))
236 matches++;
237
238 if (!matches)
239 return 0;
240
241 if (matches < 4)
242 newval = kszphy_extended_read(phydev, reg);
243 else
244 newval = 0;
245
246 if (val1 != -1)
247 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
248
6a119745 249 if (val2 != -2)
954c3967
SC		 250 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
251
6a119745 252 if (val3 != -3)
954c3967
SC		 253 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
254
6a119745 255 if (val4 != -4)
954c3967
SC		 256 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
257
258 return kszphy_extended_write(phydev, reg, newval);
259}
260
261static int ksz9021_config_init(struct phy_device *phydev)
262{
263 struct device *dev = &phydev->dev;
264 struct device_node *of_node = dev->of_node;
265
266 if (!of_node && dev->parent->of_node)
267 of_node = dev->parent->of_node;
268
269 if (of_node) {
270 ksz9021_load_values_from_of(phydev, of_node,
271 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
272 "txen-skew-ps", "txc-skew-ps",
273 "rxdv-skew-ps", "rxc-skew-ps");
274 ksz9021_load_values_from_of(phydev, of_node,
275 MII_KSZPHY_RX_DATA_PAD_SKEW,
276 "rxd0-skew-ps", "rxd1-skew-ps",
277 "rxd2-skew-ps", "rxd3-skew-ps");
278 ksz9021_load_values_from_of(phydev, of_node,
279 MII_KSZPHY_TX_DATA_PAD_SKEW,
280 "txd0-skew-ps", "txd1-skew-ps",
281 "txd2-skew-ps", "txd3-skew-ps");
282 }
283 return 0;
284}
285
6e4b8273
HC		 286#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
287#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
288#define OP_DATA 1
289#define KSZ9031_PS_TO_REG 60
290
291/* Extended registers */
292#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
293#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
294#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
295#define MII_KSZ9031RN_CLK_PAD_SKEW 8
296
297static int ksz9031_extended_write(struct phy_device *phydev,
298 u8 mode, u32 dev_addr, u32 regnum, u16 val)
299{
300 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
301 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
302 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
303 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
304}
305
306static int ksz9031_extended_read(struct phy_device *phydev,
307 u8 mode, u32 dev_addr, u32 regnum)
308{
309 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
310 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
311 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
312 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
313}
314
315static int ksz9031_of_load_skew_values(struct phy_device *phydev,
316 struct device_node *of_node,
317 u16 reg, size_t field_sz,
318 char *field[], u8 numfields)
319{
320 int val[4] = {-1, -2, -3, -4};
321 int matches = 0;
322 u16 mask;
323 u16 maxval;
324 u16 newval;
325 int i;
326
327 for (i = 0; i < numfields; i++)
328 if (!of_property_read_u32(of_node, field[i], val + i))
329 matches++;
330
331 if (!matches)
332 return 0;
333
334 if (matches < numfields)
335 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
336 else
337 newval = 0;
338
339 maxval = (field_sz == 4) ? 0xf : 0x1f;
340 for (i = 0; i < numfields; i++)
341 if (val[i] != -(i + 1)) {
342 mask = 0xffff;
343 mask ^= maxval << (field_sz * i);
344 newval = (newval & mask) |
345 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
346 << (field_sz * i));
347 }
348
349 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
350}
351
352static int ksz9031_config_init(struct phy_device *phydev)
353{
354 struct device *dev = &phydev->dev;
355 struct device_node *of_node = dev->of_node;
356 char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
357 char *rx_data_skews[4] = {
358 "rxd0-skew-ps", "rxd1-skew-ps",
359 "rxd2-skew-ps", "rxd3-skew-ps"
360 };
361 char *tx_data_skews[4] = {
362 "txd0-skew-ps", "txd1-skew-ps",
363 "txd2-skew-ps", "txd3-skew-ps"
364 };
365 char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
366
367 if (!of_node && dev->parent->of_node)
368 of_node = dev->parent->of_node;
369
370 if (of_node) {
371 ksz9031_of_load_skew_values(phydev, of_node,
372 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
373 clk_skews, 2);
374
375 ksz9031_of_load_skew_values(phydev, of_node,
376 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
377 control_skews, 2);
378
379 ksz9031_of_load_skew_values(phydev, of_node,
380 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
381 rx_data_skews, 4);
382
383 ksz9031_of_load_skew_values(phydev, of_node,
384 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
385 tx_data_skews, 4);
386 }
387 return 0;
388}
389
93272e07
JCPV		 390#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
391#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
392#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
32d73b14 393static int ksz8873mll_read_status(struct phy_device *phydev)
93272e07
JCPV		 394{
395 int regval;
396
397 /* dummy read */
398 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
399
400 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
401
402 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
403 phydev->duplex = DUPLEX_HALF;
404 else
405 phydev->duplex = DUPLEX_FULL;
406
407 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
408 phydev->speed = SPEED_10;
409 else
410 phydev->speed = SPEED_100;
411
412 phydev->link = 1;
413 phydev->pause = phydev->asym_pause = 0;
414
415 return 0;
416}
417
418static int ksz8873mll_config_aneg(struct phy_device *phydev)
419{
420 return 0;
421}
422
19936942
VB		 423/* This routine returns -1 as an indication to the caller that the
424 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
425 * MMD extended PHY registers.
426 */
427static int
428ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
429 int regnum)
430{
431 return -1;
432}
433
434/* This routine does nothing since the Micrel ksz9021 does not support
435 * standard IEEE MMD extended PHY registers.
436 */
437static void
438ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
439 int regnum, u32 val)
440{
441}
442
d5bf9071
CH		 443static struct phy_driver ksphy_driver[] = {
444{
51f932c4
CD		 445 .phy_id = PHY_ID_KS8737,
446 .phy_id_mask = 0x00fffff0,
447 .name = "Micrel KS8737",
448 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
449 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
450 .config_init = kszphy_config_init,
451 .config_aneg = genphy_config_aneg,
452 .read_status = genphy_read_status,
453 .ack_interrupt = kszphy_ack_interrupt,
454 .config_intr = ks8737_config_intr,
1a5465f5
PV		 455 .suspend = genphy_suspend,
456 .resume = genphy_resume,
51f932c4 457 .driver = { .owner = THIS_MODULE,},
212ea99a
MV		 458}, {
459 .phy_id = PHY_ID_KSZ8021,
460 .phy_id_mask = 0x00ffffff,
7ab59dc1 461 .name = "Micrel KSZ8021 or KSZ8031",
212ea99a
MV		 462 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
463 SUPPORTED_Asym_Pause),
464 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
465 .config_init = ksz8021_config_init,
466 .config_aneg = genphy_config_aneg,
467 .read_status = genphy_read_status,
468 .ack_interrupt = kszphy_ack_interrupt,
469 .config_intr = kszphy_config_intr,
1a5465f5
PV		 470 .suspend = genphy_suspend,
471 .resume = genphy_resume,
212ea99a 472 .driver = { .owner = THIS_MODULE,},
b818d1a7
HP		 473}, {
474 .phy_id = PHY_ID_KSZ8031,
475 .phy_id_mask = 0x00ffffff,
476 .name = "Micrel KSZ8031",
477 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
478 SUPPORTED_Asym_Pause),
479 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
480 .config_init = ksz8021_config_init,
481 .config_aneg = genphy_config_aneg,
482 .read_status = genphy_read_status,
483 .ack_interrupt = kszphy_ack_interrupt,
484 .config_intr = kszphy_config_intr,
1a5465f5
PV		 485 .suspend = genphy_suspend,
486 .resume = genphy_resume,
b818d1a7 487 .driver = { .owner = THIS_MODULE,},
d5bf9071 488}, {
510d573f 489 .phy_id = PHY_ID_KSZ8041,
51f932c4 490 .phy_id_mask = 0x00fffff0,
510d573f 491 .name = "Micrel KSZ8041",
51f932c4
CD		 492 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
493 | SUPPORTED_Asym_Pause),
494 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 495 .config_init = kszphy_config_init_led8041,
51f932c4
CD		 496 .config_aneg = genphy_config_aneg,
497 .read_status = genphy_read_status,
498 .ack_interrupt = kszphy_ack_interrupt,
499 .config_intr = kszphy_config_intr,
1a5465f5
PV		 500 .suspend = genphy_suspend,
501 .resume = genphy_resume,
51f932c4 502 .driver = { .owner = THIS_MODULE,},
4bd7b512
SS		 503}, {
504 .phy_id = PHY_ID_KSZ8041RNLI,
505 .phy_id_mask = 0x00fffff0,
506 .name = "Micrel KSZ8041RNLI",
507 .features = PHY_BASIC_FEATURES |
508 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
509 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 510 .config_init = kszphy_config_init_led8041,
4bd7b512
SS		 511 .config_aneg = genphy_config_aneg,
512 .read_status = genphy_read_status,
513 .ack_interrupt = kszphy_ack_interrupt,
514 .config_intr = kszphy_config_intr,
515 .suspend = genphy_suspend,
516 .resume = genphy_resume,
517 .driver = { .owner = THIS_MODULE,},
d5bf9071 518}, {
510d573f 519 .phy_id = PHY_ID_KSZ8051,
d0507009 520 .phy_id_mask = 0x00fffff0,
510d573f 521 .name = "Micrel KSZ8051",
51f932c4
CD		 522 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
523 | SUPPORTED_Asym_Pause),
524 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
d606ef3f 525 .config_init = ks8051_config_init,
d0507009
DC		 526 .config_aneg = genphy_config_aneg,
527 .read_status = genphy_read_status,
51f932c4
CD		 528 .ack_interrupt = kszphy_ack_interrupt,
529 .config_intr = kszphy_config_intr,
1a5465f5
PV		 530 .suspend = genphy_suspend,
531 .resume = genphy_resume,
d0507009 532 .driver = { .owner = THIS_MODULE,},
d5bf9071 533}, {
510d573f
MV		 534 .phy_id = PHY_ID_KSZ8001,
535 .name = "Micrel KSZ8001 or KS8721",
48d7d0ad 536 .phy_id_mask = 0x00ffffff,
51f932c4
CD		 537 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
538 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
20d8435a 539 .config_init = kszphy_config_init_led8041,
d0507009
DC		 540 .config_aneg = genphy_config_aneg,
541 .read_status = genphy_read_status,
51f932c4
CD		 542 .ack_interrupt = kszphy_ack_interrupt,
543 .config_intr = kszphy_config_intr,
1a5465f5
PV		 544 .suspend = genphy_suspend,
545 .resume = genphy_resume,
d0507009 546 .driver = { .owner = THIS_MODULE,},
7ab59dc1
DC		 547}, {
548 .phy_id = PHY_ID_KSZ8081,
549 .name = "Micrel KSZ8081 or KSZ8091",
550 .phy_id_mask = 0x00fffff0,
551 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
552 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
553 .config_init = kszphy_config_init,
554 .config_aneg = genphy_config_aneg,
555 .read_status = genphy_read_status,
556 .ack_interrupt = kszphy_ack_interrupt,
557 .config_intr = kszphy_config_intr,
1a5465f5
PV		 558 .suspend = genphy_suspend,
559 .resume = genphy_resume,
7ab59dc1
DC		 560 .driver = { .owner = THIS_MODULE,},
561}, {
562 .phy_id = PHY_ID_KSZ8061,
563 .name = "Micrel KSZ8061",
564 .phy_id_mask = 0x00fffff0,
565 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
566 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
567 .config_init = kszphy_config_init,
568 .config_aneg = genphy_config_aneg,
569 .read_status = genphy_read_status,
570 .ack_interrupt = kszphy_ack_interrupt,
571 .config_intr = kszphy_config_intr,
1a5465f5
PV		 572 .suspend = genphy_suspend,
573 .resume = genphy_resume,
7ab59dc1 574 .driver = { .owner = THIS_MODULE,},
d5bf9071 575}, {
d0507009 576 .phy_id = PHY_ID_KSZ9021,
48d7d0ad 577 .phy_id_mask = 0x000ffffe,
d0507009 578 .name = "Micrel KSZ9021 Gigabit PHY",
32fcafbc 579 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
51f932c4 580 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
954c3967 581 .config_init = ksz9021_config_init,
d0507009
DC		 582 .config_aneg = genphy_config_aneg,
583 .read_status = genphy_read_status,
51f932c4
CD		 584 .ack_interrupt = kszphy_ack_interrupt,
585 .config_intr = ksz9021_config_intr,
1a5465f5
PV		 586 .suspend = genphy_suspend,
587 .resume = genphy_resume,
19936942
VB		 588 .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
589 .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
d0507009 590 .driver = { .owner = THIS_MODULE, },
7ab59dc1
DC		 591}, {
592 .phy_id = PHY_ID_KSZ9031,
593 .phy_id_mask = 0x00fffff0,
594 .name = "Micrel KSZ9031 Gigabit PHY",
595 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause
596 | SUPPORTED_Asym_Pause),
597 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
6e4b8273 598 .config_init = ksz9031_config_init,
7ab59dc1
DC		 599 .config_aneg = genphy_config_aneg,
600 .read_status = genphy_read_status,
601 .ack_interrupt = kszphy_ack_interrupt,
602 .config_intr = ksz9021_config_intr,
1a5465f5
PV		 603 .suspend = genphy_suspend,
604 .resume = genphy_resume,
7ab59dc1 605 .driver = { .owner = THIS_MODULE, },
93272e07
JCPV		 606}, {
607 .phy_id = PHY_ID_KSZ8873MLL,
608 .phy_id_mask = 0x00fffff0,
609 .name = "Micrel KSZ8873MLL Switch",
610 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
611 .flags = PHY_HAS_MAGICANEG,
612 .config_init = kszphy_config_init,
613 .config_aneg = ksz8873mll_config_aneg,
614 .read_status = ksz8873mll_read_status,
1a5465f5
PV		 615 .suspend = genphy_suspend,
616 .resume = genphy_resume,
93272e07 617 .driver = { .owner = THIS_MODULE, },
7ab59dc1
DC		 618}, {
619 .phy_id = PHY_ID_KSZ886X,
620 .phy_id_mask = 0x00fffff0,
621 .name = "Micrel KSZ886X Switch",
622 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
623 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
624 .config_init = kszphy_config_init,
625 .config_aneg = genphy_config_aneg,
626 .read_status = genphy_read_status,
1a5465f5
PV		 627 .suspend = genphy_suspend,
628 .resume = genphy_resume,
7ab59dc1 629 .driver = { .owner = THIS_MODULE, },
d5bf9071 630} };
d0507009
DC		 631
632static int __init ksphy_init(void)
633{
d5bf9071
CH		 634 return phy_drivers_register(ksphy_driver,
635 ARRAY_SIZE(ksphy_driver));
d0507009
DC		 636}
637
638static void __exit ksphy_exit(void)
639{
d5bf9071
CH		 640 phy_drivers_unregister(ksphy_driver,
641 ARRAY_SIZE(ksphy_driver));
d0507009
DC		 642}
643
644module_init(ksphy_init);
645module_exit(ksphy_exit);
646
647MODULE_DESCRIPTION("Micrel PHY driver");
648MODULE_AUTHOR("David J. Choi");
649MODULE_LICENSE("GPL");
52a60ed2 650
cf93c945 651static struct mdio_device_id __maybe_unused micrel_tbl[] = {
48d7d0ad 652 { PHY_ID_KSZ9021, 0x000ffffe },
7ab59dc1 653 { PHY_ID_KSZ9031, 0x00fffff0 },
510d573f 654 { PHY_ID_KSZ8001, 0x00ffffff },
51f932c4 655 { PHY_ID_KS8737, 0x00fffff0 },
212ea99a 656 { PHY_ID_KSZ8021, 0x00ffffff },
b818d1a7 657 { PHY_ID_KSZ8031, 0x00ffffff },
510d573f
MV		 658 { PHY_ID_KSZ8041, 0x00fffff0 },
659 { PHY_ID_KSZ8051, 0x00fffff0 },
7ab59dc1
DC		 660 { PHY_ID_KSZ8061, 0x00fffff0 },
661 { PHY_ID_KSZ8081, 0x00fffff0 },
93272e07 662 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
7ab59dc1 663 { PHY_ID_KSZ886X, 0x00fffff0 },
52a60ed2
DM		 664 { }
665};
666
667MODULE_DEVICE_TABLE(mdio, micrel_tbl);
Ubuntu Artful kernel mirror