[mirror_ubuntu-hirsute-kernel.git] / drivers / net / phy / micrel.c

/*
 * drivers/net/phy/micrel.c
 *
 * Driver for Micrel PHYs
 *
 * Author: David J. Choi
 *
 * Copyright (c) 2010-2013 Micrel, Inc.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 *
 * Support : Micrel Phys:
 *		Giga phys: ksz9021, ksz9031
 *		100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
 *			   ksz8021, ksz8031, ksz8051,
 *			   ksz8081, ksz8091,
 *			   ksz8061,
 *		Switch : ksz8873, ksz886x
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/phy.h>
#include <linux/micrel_phy.h>
#include <linux/of.h>

/* Operation Mode Strap Override */
#define MII_KSZPHY_OMSO				0x16
#define KSZPHY_OMSO_B_CAST_OFF			(1 << 9)
#define KSZPHY_OMSO_RMII_OVERRIDE		(1 << 1)
#define KSZPHY_OMSO_MII_OVERRIDE		(1 << 0)

/* general Interrupt control/status reg in vendor specific block. */
#define MII_KSZPHY_INTCS			0x1B
#define	KSZPHY_INTCS_JABBER			(1 << 15)
#define	KSZPHY_INTCS_RECEIVE_ERR		(1 << 14)
#define	KSZPHY_INTCS_PAGE_RECEIVE		(1 << 13)
#define	KSZPHY_INTCS_PARELLEL			(1 << 12)
#define	KSZPHY_INTCS_LINK_PARTNER_ACK		(1 << 11)
#define	KSZPHY_INTCS_LINK_DOWN			(1 << 10)
#define	KSZPHY_INTCS_REMOTE_FAULT		(1 << 9)
#define	KSZPHY_INTCS_LINK_UP			(1 << 8)
#define	KSZPHY_INTCS_ALL			(KSZPHY_INTCS_LINK_UP |\
						KSZPHY_INTCS_LINK_DOWN)

/* general PHY control reg in vendor specific block. */
#define	MII_KSZPHY_CTRL			0x1F
/* bitmap of PHY register to set interrupt mode */
#define KSZPHY_CTRL_INT_ACTIVE_HIGH		(1 << 9)
#define KSZ9021_CTRL_INT_ACTIVE_HIGH		(1 << 14)
#define KS8737_CTRL_INT_ACTIVE_HIGH		(1 << 14)
#define KSZ8051_RMII_50MHZ_CLK			(1 << 7)

/* Write/read to/from extended registers */
#define MII_KSZPHY_EXTREG                       0x0b
#define KSZPHY_EXTREG_WRITE                     0x8000

#define MII_KSZPHY_EXTREG_WRITE                 0x0c
#define MII_KSZPHY_EXTREG_READ                  0x0d

/* Extended registers */
#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
#define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
#define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106

#define PS_TO_REG				200

static int ksz_config_flags(struct phy_device *phydev)
{
	int regval;

	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
		regval = phy_read(phydev, MII_KSZPHY_CTRL);
		regval |= KSZ8051_RMII_50MHZ_CLK;
		return phy_write(phydev, MII_KSZPHY_CTRL, regval);
	}
	return 0;
}

static int kszphy_extended_write(struct phy_device *phydev,
				u32 regnum, u16 val)
{
	phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
	return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
}

static int kszphy_extended_read(struct phy_device *phydev,
				u32 regnum)
{
	phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
	return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
}

static int kszphy_ack_interrupt(struct phy_device *phydev)
{
	/* bit[7..0] int status, which is a read and clear register. */
	int rc;

	rc = phy_read(phydev, MII_KSZPHY_INTCS);

	return (rc < 0) ? rc : 0;
}

static int kszphy_set_interrupt(struct phy_device *phydev)
{
	int temp;
	temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
		KSZPHY_INTCS_ALL : 0;
	return phy_write(phydev, MII_KSZPHY_INTCS, temp);
}

static int kszphy_config_intr(struct phy_device *phydev)
{
	int temp, rc;

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	rc = kszphy_set_interrupt(phydev);
	return rc < 0 ? rc : 0;
}

static int ksz9021_config_intr(struct phy_device *phydev)
{
	int temp, rc;

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	rc = kszphy_set_interrupt(phydev);
	return rc < 0 ? rc : 0;
}

static int ks8737_config_intr(struct phy_device *phydev)
{
	int temp, rc;

	/* set the interrupt pin active low */
	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	rc = kszphy_set_interrupt(phydev);
	return rc < 0 ? rc : 0;
}

static int kszphy_setup_led(struct phy_device *phydev,
			    unsigned int reg, unsigned int shift)
{

	struct device *dev = &phydev->dev;
	struct device_node *of_node = dev->of_node;
	int rc, temp;
	u32 val;

	if (!of_node && dev->parent->of_node)
		of_node = dev->parent->of_node;

	if (of_property_read_u32(of_node, "micrel,led-mode", &val))
		return 0;

	temp = phy_read(phydev, reg);
	if (temp < 0)
		return temp;

	temp &= ~(3 << shift);
	temp |= val << shift;
	rc = phy_write(phydev, reg, temp);

	return rc < 0 ? rc : 0;
}

static int kszphy_config_init(struct phy_device *phydev)
{
	return 0;
}

static int kszphy_config_init_led8041(struct phy_device *phydev)
{
	/* single led control, register 0x1e bits 15..14 */
	return kszphy_setup_led(phydev, 0x1e, 14);
}

static int ksz8021_config_init(struct phy_device *phydev)
{
	const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
	int rc;

	rc = kszphy_setup_led(phydev, 0x1f, 4);
	if (rc)
		dev_err(&phydev->dev, "failed to set led mode\n");

	phy_write(phydev, MII_KSZPHY_OMSO, val);
	rc = ksz_config_flags(phydev);
	return rc < 0 ? rc : 0;
}

static int ks8051_config_init(struct phy_device *phydev)
{
	int rc;

	rc = kszphy_setup_led(phydev, 0x1f, 4);
	if (rc)
		dev_err(&phydev->dev, "failed to set led mode\n");

	rc = ksz_config_flags(phydev);
	return rc < 0 ? rc : 0;
}

static int ksz9021_load_values_from_of(struct phy_device *phydev,
				       struct device_node *of_node, u16 reg,
				       char *field1, char *field2,
				       char *field3, char *field4)
{
	int val1 = -1;
	int val2 = -2;
	int val3 = -3;
	int val4 = -4;
	int newval;
	int matches = 0;

	if (!of_property_read_u32(of_node, field1, &val1))
		matches++;

	if (!of_property_read_u32(of_node, field2, &val2))
		matches++;

	if (!of_property_read_u32(of_node, field3, &val3))
		matches++;

	if (!of_property_read_u32(of_node, field4, &val4))
		matches++;

	if (!matches)
		return 0;

	if (matches < 4)
		newval = kszphy_extended_read(phydev, reg);
	else
		newval = 0;

	if (val1 != -1)
		newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);

	if (val2 != -2)
		newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);

	if (val3 != -3)
		newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);

	if (val4 != -4)
		newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);

	return kszphy_extended_write(phydev, reg, newval);
}

static int ksz9021_config_init(struct phy_device *phydev)
{
	struct device *dev = &phydev->dev;
	struct device_node *of_node = dev->of_node;

	if (!of_node && dev->parent->of_node)
		of_node = dev->parent->of_node;

	if (of_node) {
		ksz9021_load_values_from_of(phydev, of_node,
				    MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
				    "txen-skew-ps", "txc-skew-ps",
				    "rxdv-skew-ps", "rxc-skew-ps");
		ksz9021_load_values_from_of(phydev, of_node,
				    MII_KSZPHY_RX_DATA_PAD_SKEW,
				    "rxd0-skew-ps", "rxd1-skew-ps",
				    "rxd2-skew-ps", "rxd3-skew-ps");
		ksz9021_load_values_from_of(phydev, of_node,
				    MII_KSZPHY_TX_DATA_PAD_SKEW,
				    "txd0-skew-ps", "txd1-skew-ps",
				    "txd2-skew-ps", "txd3-skew-ps");
	}
	return 0;
}

#define KSZ8873MLL_GLOBAL_CONTROL_4	0x06
#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX	(1 << 6)
#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED	(1 << 4)
static int ksz8873mll_read_status(struct phy_device *phydev)
{
	int regval;

	/* dummy read */
	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);

	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);

	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
		phydev->duplex = DUPLEX_HALF;
	else
		phydev->duplex = DUPLEX_FULL;

	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
		phydev->speed = SPEED_10;
	else
		phydev->speed = SPEED_100;

	phydev->link = 1;
	phydev->pause = phydev->asym_pause = 0;

	return 0;
}

static int ksz8873mll_config_aneg(struct phy_device *phydev)
{
	return 0;
}

static struct phy_driver ksphy_driver[] = {
{
	.phy_id		= PHY_ID_KS8737,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KS8737",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= ks8737_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8021,
	.phy_id_mask	= 0x00ffffff,
	.name		= "Micrel KSZ8021 or KSZ8031",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ksz8021_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8031,
	.phy_id_mask	= 0x00ffffff,
	.name		= "Micrel KSZ8031",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
			   SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ksz8021_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8041,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8041",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause
				| SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init_led8041,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8041RNLI,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8041RNLI",
	.features	= PHY_BASIC_FEATURES |
			  SUPPORTED_Pause | SUPPORTED_Asym_Pause,
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init_led8041,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8051,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8051",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause
				| SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ks8051_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8001,
	.name		= "Micrel KSZ8001 or KS8721",
	.phy_id_mask	= 0x00ffffff,
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init_led8041,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8081,
	.name		= "Micrel KSZ8081 or KSZ8091",
	.phy_id_mask	= 0x00fffff0,
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ8061,
	.name		= "Micrel KSZ8061",
	.phy_id_mask	= 0x00fffff0,
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= kszphy_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE,},
}, {
	.phy_id		= PHY_ID_KSZ9021,
	.phy_id_mask	= 0x000ffffe,
	.name		= "Micrel KSZ9021 Gigabit PHY",
	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= ksz9021_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= ksz9021_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE, },
}, {
	.phy_id		= PHY_ID_KSZ9031,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ9031 Gigabit PHY",
	.features	= (PHY_GBIT_FEATURES | SUPPORTED_Pause
				| SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.ack_interrupt	= kszphy_ack_interrupt,
	.config_intr	= ksz9021_config_intr,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE, },
}, {
	.phy_id		= PHY_ID_KSZ8873MLL,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ8873MLL Switch",
	.features	= (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
	.flags		= PHY_HAS_MAGICANEG,
	.config_init	= kszphy_config_init,
	.config_aneg	= ksz8873mll_config_aneg,
	.read_status	= ksz8873mll_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE, },
}, {
	.phy_id		= PHY_ID_KSZ886X,
	.phy_id_mask	= 0x00fffff0,
	.name		= "Micrel KSZ886X Switch",
	.features	= (PHY_BASIC_FEATURES | SUPPORTED_Pause),
	.flags		= PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
	.config_init	= kszphy_config_init,
	.config_aneg	= genphy_config_aneg,
	.read_status	= genphy_read_status,
	.suspend	= genphy_suspend,
	.resume		= genphy_resume,
	.driver		= { .owner = THIS_MODULE, },
} };

static int __init ksphy_init(void)
{
	return phy_drivers_register(ksphy_driver,
		ARRAY_SIZE(ksphy_driver));
}

static void __exit ksphy_exit(void)
{
	phy_drivers_unregister(ksphy_driver,
		ARRAY_SIZE(ksphy_driver));
}

module_init(ksphy_init);
module_exit(ksphy_exit);

MODULE_DESCRIPTION("Micrel PHY driver");
MODULE_AUTHOR("David J. Choi");
MODULE_LICENSE("GPL");

static struct mdio_device_id __maybe_unused micrel_tbl[] = {
	{ PHY_ID_KSZ9021, 0x000ffffe },
	{ PHY_ID_KSZ9031, 0x00fffff0 },
	{ PHY_ID_KSZ8001, 0x00ffffff },
	{ PHY_ID_KS8737, 0x00fffff0 },
	{ PHY_ID_KSZ8021, 0x00ffffff },
	{ PHY_ID_KSZ8031, 0x00ffffff },
	{ PHY_ID_KSZ8041, 0x00fffff0 },
	{ PHY_ID_KSZ8051, 0x00fffff0 },
	{ PHY_ID_KSZ8061, 0x00fffff0 },
	{ PHY_ID_KSZ8081, 0x00fffff0 },
	{ PHY_ID_KSZ8873MLL, 0x00fffff0 },
	{ PHY_ID_KSZ886X, 0x00fffff0 },
	{ }
};

MODULE_DEVICE_TABLE(mdio, micrel_tbl);
Commit	Line	Data
d0507009 DC	1	/*
	2	* drivers/net/phy/micrel.c
	3	*
	4	* Driver for Micrel PHYs
	5	*
	6	* Author: David J. Choi
	7	*
7ab59dc1	8	* Copyright (c) 2010-2013 Micrel, Inc.
d0507009 DC	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*
7ab59dc1 DC	15	* Support : Micrel Phys:
	16	* Giga phys: ksz9021, ksz9031
	17	* 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
	18	* ksz8021, ksz8031, ksz8051,
	19	* ksz8081, ksz8091,
	20	* ksz8061,
	21	* Switch : ksz8873, ksz886x
d0507009 DC	22	*/
	23
	24	#include <linux/kernel.h>
	25	#include <linux/module.h>
	26	#include <linux/phy.h>
d606ef3f	27	#include <linux/micrel_phy.h>
954c3967	28	#include <linux/of.h>
d0507009	29
212ea99a MV	30	/* Operation Mode Strap Override */
	31	#define MII_KSZPHY_OMSO 0x16
	32	#define KSZPHY_OMSO_B_CAST_OFF (1 << 9)
	33	#define KSZPHY_OMSO_RMII_OVERRIDE (1 << 1)
	34	#define KSZPHY_OMSO_MII_OVERRIDE (1 << 0)
	35
51f932c4 CD	36	/* general Interrupt control/status reg in vendor specific block. */
	37	#define MII_KSZPHY_INTCS 0x1B
	38	#define KSZPHY_INTCS_JABBER (1 << 15)
	39	#define KSZPHY_INTCS_RECEIVE_ERR (1 << 14)
	40	#define KSZPHY_INTCS_PAGE_RECEIVE (1 << 13)
	41	#define KSZPHY_INTCS_PARELLEL (1 << 12)
	42	#define KSZPHY_INTCS_LINK_PARTNER_ACK (1 << 11)
	43	#define KSZPHY_INTCS_LINK_DOWN (1 << 10)
	44	#define KSZPHY_INTCS_REMOTE_FAULT (1 << 9)
	45	#define KSZPHY_INTCS_LINK_UP (1 << 8)
	46	#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP \|\
	47	KSZPHY_INTCS_LINK_DOWN)
	48
	49	/* general PHY control reg in vendor specific block. */
	50	#define MII_KSZPHY_CTRL 0x1F
	51	/* bitmap of PHY register to set interrupt mode */
	52	#define KSZPHY_CTRL_INT_ACTIVE_HIGH (1 << 9)
	53	#define KSZ9021_CTRL_INT_ACTIVE_HIGH (1 << 14)
	54	#define KS8737_CTRL_INT_ACTIVE_HIGH (1 << 14)
d606ef3f	55	#define KSZ8051_RMII_50MHZ_CLK (1 << 7)
51f932c4	56
954c3967 SC	57	/* Write/read to/from extended registers */
	58	#define MII_KSZPHY_EXTREG 0x0b
	59	#define KSZPHY_EXTREG_WRITE 0x8000
	60
	61	#define MII_KSZPHY_EXTREG_WRITE 0x0c
	62	#define MII_KSZPHY_EXTREG_READ 0x0d
	63
	64	/* Extended registers */
	65	#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
	66	#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
	67	#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
	68
	69	#define PS_TO_REG 200
	70
b6bb4dfc HP	71	static int ksz_config_flags(struct phy_device *phydev)
	72	{
	73	int regval;
	74
	75	if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
	76	regval = phy_read(phydev, MII_KSZPHY_CTRL);
	77	regval \|= KSZ8051_RMII_50MHZ_CLK;
	78	return phy_write(phydev, MII_KSZPHY_CTRL, regval);
	79	}
	80	return 0;
	81	}
	82
954c3967	83	static int kszphy_extended_write(struct phy_device *phydev,
756b5089	84	u32 regnum, u16 val)
954c3967 SC	85	{
	86	phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE \| regnum);
	87	return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
	88	}
	89
	90	static int kszphy_extended_read(struct phy_device *phydev,
756b5089	91	u32 regnum)
954c3967 SC	92	{
	93	phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
	94	return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
	95	}
	96
51f932c4 CD	97	static int kszphy_ack_interrupt(struct phy_device *phydev)
	98	{
	99	/* bit[7..0] int status, which is a read and clear register. */
	100	int rc;
	101
	102	rc = phy_read(phydev, MII_KSZPHY_INTCS);
	103
	104	return (rc < 0) ? rc : 0;
	105	}
	106
	107	static int kszphy_set_interrupt(struct phy_device *phydev)
	108	{
	109	int temp;
	110	temp = (PHY_INTERRUPT_ENABLED == phydev->interrupts) ?
	111	KSZPHY_INTCS_ALL : 0;
	112	return phy_write(phydev, MII_KSZPHY_INTCS, temp);
	113	}
	114
	115	static int kszphy_config_intr(struct phy_device *phydev)
	116	{
	117	int temp, rc;
	118
	119	/* set the interrupt pin active low */
	120	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	121	temp &= ~KSZPHY_CTRL_INT_ACTIVE_HIGH;
	122	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	123	rc = kszphy_set_interrupt(phydev);
	124	return rc < 0 ? rc : 0;
	125	}
	126
	127	static int ksz9021_config_intr(struct phy_device *phydev)
	128	{
	129	int temp, rc;
	130
	131	/* set the interrupt pin active low */
	132	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	133	temp &= ~KSZ9021_CTRL_INT_ACTIVE_HIGH;
	134	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	135	rc = kszphy_set_interrupt(phydev);
	136	return rc < 0 ? rc : 0;
	137	}
	138
	139	static int ks8737_config_intr(struct phy_device *phydev)
	140	{
	141	int temp, rc;
	142
	143	/* set the interrupt pin active low */
	144	temp = phy_read(phydev, MII_KSZPHY_CTRL);
	145	temp &= ~KS8737_CTRL_INT_ACTIVE_HIGH;
	146	phy_write(phydev, MII_KSZPHY_CTRL, temp);
	147	rc = kszphy_set_interrupt(phydev);
	148	return rc < 0 ? rc : 0;
	149	}
d0507009	150
20d8435a BD	151	static int kszphy_setup_led(struct phy_device *phydev,
	152	unsigned int reg, unsigned int shift)
	153	{
	154
	155	struct device *dev = &phydev->dev;
	156	struct device_node *of_node = dev->of_node;
	157	int rc, temp;
	158	u32 val;
	159
	160	if (!of_node && dev->parent->of_node)
	161	of_node = dev->parent->of_node;
	162
	163	if (of_property_read_u32(of_node, "micrel,led-mode", &val))
	164	return 0;
	165
	166	temp = phy_read(phydev, reg);
	167	if (temp < 0)
	168	return temp;
	169
28bdc499	170	temp &= ~(3 << shift);
20d8435a BD	171	temp \|= val << shift;
	172	rc = phy_write(phydev, reg, temp);
	173
	174	return rc < 0 ? rc : 0;
	175	}
	176
d0507009 DC	177	static int kszphy_config_init(struct phy_device *phydev)
	178	{
	179	return 0;
	180	}
	181
20d8435a BD	182	static int kszphy_config_init_led8041(struct phy_device *phydev)
	183	{
	184	/* single led control, register 0x1e bits 15..14 */
	185	return kszphy_setup_led(phydev, 0x1e, 14);
	186	}
	187
212ea99a MV	188	static int ksz8021_config_init(struct phy_device *phydev)
	189	{
	190	const u16 val = KSZPHY_OMSO_B_CAST_OFF \| KSZPHY_OMSO_RMII_OVERRIDE;
20d8435a BD	191	int rc;
	192
	193	rc = kszphy_setup_led(phydev, 0x1f, 4);
	194	if (rc)
	195	dev_err(&phydev->dev, "failed to set led mode\n");
	196
212ea99a	197	phy_write(phydev, MII_KSZPHY_OMSO, val);
b6bb4dfc HP	198	rc = ksz_config_flags(phydev);
b6bb4dfc HP	199	return rc < 0 ? rc : 0;
212ea99a MV	200	}
212ea99a MV	201
d606ef3f BS	202	static int ks8051_config_init(struct phy_device *phydev)
d606ef3f BS	203	{
b6bb4dfc	204	int rc;
d606ef3f	205
20d8435a BD	206	rc = kszphy_setup_led(phydev, 0x1f, 4);
	207	if (rc)
	208	dev_err(&phydev->dev, "failed to set led mode\n");
	209
b6bb4dfc HP	210	rc = ksz_config_flags(phydev);
b6bb4dfc HP	211	return rc < 0 ? rc : 0;
d606ef3f BS	212	}
d606ef3f BS	213
954c3967 SC	214	static int ksz9021_load_values_from_of(struct phy_device *phydev,
	215	struct device_node *of_node, u16 reg,
	216	char field1, char field2,
	217	char field3, char field4)
	218	{
	219	int val1 = -1;
	220	int val2 = -2;
	221	int val3 = -3;
	222	int val4 = -4;
	223	int newval;
	224	int matches = 0;
	225
	226	if (!of_property_read_u32(of_node, field1, &val1))
	227	matches++;
	228
	229	if (!of_property_read_u32(of_node, field2, &val2))
	230	matches++;
	231
	232	if (!of_property_read_u32(of_node, field3, &val3))
	233	matches++;
	234
	235	if (!of_property_read_u32(of_node, field4, &val4))
	236	matches++;
	237
	238	if (!matches)
	239	return 0;
	240
	241	if (matches < 4)
	242	newval = kszphy_extended_read(phydev, reg);
	243	else
	244	newval = 0;
	245
	246	if (val1 != -1)
	247	newval = ((newval & 0xfff0) \| ((val1 / PS_TO_REG) & 0xf) << 0);
	248
6a119745	249	if (val2 != -2)
954c3967 SC	250	newval = ((newval & 0xff0f) \| ((val2 / PS_TO_REG) & 0xf) << 4);
954c3967 SC	251
6a119745	252	if (val3 != -3)
954c3967 SC	253	newval = ((newval & 0xf0ff) \| ((val3 / PS_TO_REG) & 0xf) << 8);
954c3967 SC	254
6a119745	255	if (val4 != -4)
954c3967 SC	256	newval = ((newval & 0x0fff) \| ((val4 / PS_TO_REG) & 0xf) << 12);
	257
	258	return kszphy_extended_write(phydev, reg, newval);
	259	}
	260
	261	static int ksz9021_config_init(struct phy_device *phydev)
	262	{
	263	struct device *dev = &phydev->dev;
	264	struct device_node *of_node = dev->of_node;
	265
	266	if (!of_node && dev->parent->of_node)
	267	of_node = dev->parent->of_node;
	268
	269	if (of_node) {
	270	ksz9021_load_values_from_of(phydev, of_node,
	271	MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
	272	"txen-skew-ps", "txc-skew-ps",
	273	"rxdv-skew-ps", "rxc-skew-ps");
	274	ksz9021_load_values_from_of(phydev, of_node,
	275	MII_KSZPHY_RX_DATA_PAD_SKEW,
	276	"rxd0-skew-ps", "rxd1-skew-ps",
	277	"rxd2-skew-ps", "rxd3-skew-ps");
	278	ksz9021_load_values_from_of(phydev, of_node,
	279	MII_KSZPHY_TX_DATA_PAD_SKEW,
	280	"txd0-skew-ps", "txd1-skew-ps",
	281	"txd2-skew-ps", "txd3-skew-ps");
	282	}
	283	return 0;
	284	}
	285
93272e07 JCPV	286	#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
	287	#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX (1 << 6)
	288	#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED (1 << 4)
32d73b14	289	static int ksz8873mll_read_status(struct phy_device *phydev)
93272e07 JCPV	290	{
	291	int regval;
	292
	293	/* dummy read */
	294	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
	295
	296	regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
	297
	298	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
	299	phydev->duplex = DUPLEX_HALF;
	300	else
	301	phydev->duplex = DUPLEX_FULL;
	302
	303	if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
	304	phydev->speed = SPEED_10;
	305	else
	306	phydev->speed = SPEED_100;
	307
	308	phydev->link = 1;
	309	phydev->pause = phydev->asym_pause = 0;
	310
	311	return 0;
	312	}
	313
	314	static int ksz8873mll_config_aneg(struct phy_device *phydev)
	315	{
	316	return 0;
	317	}
	318
d5bf9071 CH	319	static struct phy_driver ksphy_driver[] = {
d5bf9071 CH	320	{
51f932c4 CD	321	.phy_id = PHY_ID_KS8737,
	322	.phy_id_mask = 0x00fffff0,
	323	.name = "Micrel KS8737",
	324	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	325	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	326	.config_init = kszphy_config_init,
	327	.config_aneg = genphy_config_aneg,
	328	.read_status = genphy_read_status,
	329	.ack_interrupt = kszphy_ack_interrupt,
	330	.config_intr = ks8737_config_intr,
1a5465f5 PV	331	.suspend = genphy_suspend,
1a5465f5 PV	332	.resume = genphy_resume,
51f932c4	333	.driver = { .owner = THIS_MODULE,},
212ea99a MV	334	}, {
	335	.phy_id = PHY_ID_KSZ8021,
	336	.phy_id_mask = 0x00ffffff,
7ab59dc1	337	.name = "Micrel KSZ8021 or KSZ8031",
212ea99a MV	338	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause \|
	339	SUPPORTED_Asym_Pause),
	340	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	341	.config_init = ksz8021_config_init,
	342	.config_aneg = genphy_config_aneg,
	343	.read_status = genphy_read_status,
	344	.ack_interrupt = kszphy_ack_interrupt,
	345	.config_intr = kszphy_config_intr,
1a5465f5 PV	346	.suspend = genphy_suspend,
1a5465f5 PV	347	.resume = genphy_resume,
212ea99a	348	.driver = { .owner = THIS_MODULE,},
b818d1a7 HP	349	}, {
	350	.phy_id = PHY_ID_KSZ8031,
	351	.phy_id_mask = 0x00ffffff,
	352	.name = "Micrel KSZ8031",
	353	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause \|
	354	SUPPORTED_Asym_Pause),
	355	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	356	.config_init = ksz8021_config_init,
	357	.config_aneg = genphy_config_aneg,
	358	.read_status = genphy_read_status,
	359	.ack_interrupt = kszphy_ack_interrupt,
	360	.config_intr = kszphy_config_intr,
1a5465f5 PV	361	.suspend = genphy_suspend,
1a5465f5 PV	362	.resume = genphy_resume,
b818d1a7	363	.driver = { .owner = THIS_MODULE,},
d5bf9071	364	}, {
510d573f	365	.phy_id = PHY_ID_KSZ8041,
51f932c4	366	.phy_id_mask = 0x00fffff0,
510d573f	367	.name = "Micrel KSZ8041",
51f932c4 CD	368	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause
	369	\| SUPPORTED_Asym_Pause),
	370	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
20d8435a	371	.config_init = kszphy_config_init_led8041,
51f932c4 CD	372	.config_aneg = genphy_config_aneg,
	373	.read_status = genphy_read_status,
	374	.ack_interrupt = kszphy_ack_interrupt,
	375	.config_intr = kszphy_config_intr,
1a5465f5 PV	376	.suspend = genphy_suspend,
1a5465f5 PV	377	.resume = genphy_resume,
51f932c4	378	.driver = { .owner = THIS_MODULE,},
4bd7b512 SS	379	}, {
	380	.phy_id = PHY_ID_KSZ8041RNLI,
	381	.phy_id_mask = 0x00fffff0,
	382	.name = "Micrel KSZ8041RNLI",
	383	.features = PHY_BASIC_FEATURES \|
	384	SUPPORTED_Pause \| SUPPORTED_Asym_Pause,
	385	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
20d8435a	386	.config_init = kszphy_config_init_led8041,
4bd7b512 SS	387	.config_aneg = genphy_config_aneg,
	388	.read_status = genphy_read_status,
	389	.ack_interrupt = kszphy_ack_interrupt,
	390	.config_intr = kszphy_config_intr,
	391	.suspend = genphy_suspend,
	392	.resume = genphy_resume,
	393	.driver = { .owner = THIS_MODULE,},
d5bf9071	394	}, {
510d573f	395	.phy_id = PHY_ID_KSZ8051,
d0507009	396	.phy_id_mask = 0x00fffff0,
510d573f	397	.name = "Micrel KSZ8051",
51f932c4 CD	398	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause
	399	\| SUPPORTED_Asym_Pause),
	400	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
d606ef3f	401	.config_init = ks8051_config_init,
d0507009 DC	402	.config_aneg = genphy_config_aneg,
d0507009 DC	403	.read_status = genphy_read_status,
51f932c4 CD	404	.ack_interrupt = kszphy_ack_interrupt,
51f932c4 CD	405	.config_intr = kszphy_config_intr,
1a5465f5 PV	406	.suspend = genphy_suspend,
1a5465f5 PV	407	.resume = genphy_resume,
d0507009	408	.driver = { .owner = THIS_MODULE,},
d5bf9071	409	}, {
510d573f MV	410	.phy_id = PHY_ID_KSZ8001,
510d573f MV	411	.name = "Micrel KSZ8001 or KS8721",
48d7d0ad	412	.phy_id_mask = 0x00ffffff,
51f932c4 CD	413	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
51f932c4 CD	414	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
20d8435a	415	.config_init = kszphy_config_init_led8041,
d0507009 DC	416	.config_aneg = genphy_config_aneg,
d0507009 DC	417	.read_status = genphy_read_status,
51f932c4 CD	418	.ack_interrupt = kszphy_ack_interrupt,
51f932c4 CD	419	.config_intr = kszphy_config_intr,
1a5465f5 PV	420	.suspend = genphy_suspend,
1a5465f5 PV	421	.resume = genphy_resume,
d0507009	422	.driver = { .owner = THIS_MODULE,},
7ab59dc1 DC	423	}, {
	424	.phy_id = PHY_ID_KSZ8081,
	425	.name = "Micrel KSZ8081 or KSZ8091",
	426	.phy_id_mask = 0x00fffff0,
	427	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	428	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	429	.config_init = kszphy_config_init,
	430	.config_aneg = genphy_config_aneg,
	431	.read_status = genphy_read_status,
	432	.ack_interrupt = kszphy_ack_interrupt,
	433	.config_intr = kszphy_config_intr,
1a5465f5 PV	434	.suspend = genphy_suspend,
1a5465f5 PV	435	.resume = genphy_resume,
7ab59dc1 DC	436	.driver = { .owner = THIS_MODULE,},
	437	}, {
	438	.phy_id = PHY_ID_KSZ8061,
	439	.name = "Micrel KSZ8061",
	440	.phy_id_mask = 0x00fffff0,
	441	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	442	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	443	.config_init = kszphy_config_init,
	444	.config_aneg = genphy_config_aneg,
	445	.read_status = genphy_read_status,
	446	.ack_interrupt = kszphy_ack_interrupt,
	447	.config_intr = kszphy_config_intr,
1a5465f5 PV	448	.suspend = genphy_suspend,
1a5465f5 PV	449	.resume = genphy_resume,
7ab59dc1	450	.driver = { .owner = THIS_MODULE,},
d5bf9071	451	}, {
d0507009	452	.phy_id = PHY_ID_KSZ9021,
48d7d0ad	453	.phy_id_mask = 0x000ffffe,
d0507009	454	.name = "Micrel KSZ9021 Gigabit PHY",
32fcafbc	455	.features = (PHY_GBIT_FEATURES \| SUPPORTED_Pause),
51f932c4	456	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
954c3967	457	.config_init = ksz9021_config_init,
d0507009 DC	458	.config_aneg = genphy_config_aneg,
d0507009 DC	459	.read_status = genphy_read_status,
51f932c4 CD	460	.ack_interrupt = kszphy_ack_interrupt,
51f932c4 CD	461	.config_intr = ksz9021_config_intr,
1a5465f5 PV	462	.suspend = genphy_suspend,
1a5465f5 PV	463	.resume = genphy_resume,
d0507009	464	.driver = { .owner = THIS_MODULE, },
7ab59dc1 DC	465	}, {
	466	.phy_id = PHY_ID_KSZ9031,
	467	.phy_id_mask = 0x00fffff0,
	468	.name = "Micrel KSZ9031 Gigabit PHY",
	469	.features = (PHY_GBIT_FEATURES \| SUPPORTED_Pause
	470	\| SUPPORTED_Asym_Pause),
	471	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	472	.config_init = kszphy_config_init,
	473	.config_aneg = genphy_config_aneg,
	474	.read_status = genphy_read_status,
	475	.ack_interrupt = kszphy_ack_interrupt,
	476	.config_intr = ksz9021_config_intr,
1a5465f5 PV	477	.suspend = genphy_suspend,
1a5465f5 PV	478	.resume = genphy_resume,
7ab59dc1	479	.driver = { .owner = THIS_MODULE, },
93272e07 JCPV	480	}, {
	481	.phy_id = PHY_ID_KSZ8873MLL,
	482	.phy_id_mask = 0x00fffff0,
	483	.name = "Micrel KSZ8873MLL Switch",
	484	.features = (SUPPORTED_Pause \| SUPPORTED_Asym_Pause),
	485	.flags = PHY_HAS_MAGICANEG,
	486	.config_init = kszphy_config_init,
	487	.config_aneg = ksz8873mll_config_aneg,
	488	.read_status = ksz8873mll_read_status,
1a5465f5 PV	489	.suspend = genphy_suspend,
1a5465f5 PV	490	.resume = genphy_resume,
93272e07	491	.driver = { .owner = THIS_MODULE, },
7ab59dc1 DC	492	}, {
	493	.phy_id = PHY_ID_KSZ886X,
	494	.phy_id_mask = 0x00fffff0,
	495	.name = "Micrel KSZ886X Switch",
	496	.features = (PHY_BASIC_FEATURES \| SUPPORTED_Pause),
	497	.flags = PHY_HAS_MAGICANEG \| PHY_HAS_INTERRUPT,
	498	.config_init = kszphy_config_init,
	499	.config_aneg = genphy_config_aneg,
	500	.read_status = genphy_read_status,
1a5465f5 PV	501	.suspend = genphy_suspend,
1a5465f5 PV	502	.resume = genphy_resume,
7ab59dc1	503	.driver = { .owner = THIS_MODULE, },
d5bf9071	504	} };
d0507009 DC	505
	506	static int __init ksphy_init(void)
	507	{
d5bf9071 CH	508	return phy_drivers_register(ksphy_driver,
d5bf9071 CH	509	ARRAY_SIZE(ksphy_driver));
d0507009 DC	510	}
	511
	512	static void __exit ksphy_exit(void)
	513	{
d5bf9071 CH	514	phy_drivers_unregister(ksphy_driver,
d5bf9071 CH	515	ARRAY_SIZE(ksphy_driver));
d0507009 DC	516	}
	517
	518	module_init(ksphy_init);
	519	module_exit(ksphy_exit);
	520
	521	MODULE_DESCRIPTION("Micrel PHY driver");
	522	MODULE_AUTHOR("David J. Choi");
	523	MODULE_LICENSE("GPL");
52a60ed2	524
cf93c945	525	static struct mdio_device_id __maybe_unused micrel_tbl[] = {
48d7d0ad	526	{ PHY_ID_KSZ9021, 0x000ffffe },
7ab59dc1	527	{ PHY_ID_KSZ9031, 0x00fffff0 },
510d573f	528	{ PHY_ID_KSZ8001, 0x00ffffff },
51f932c4	529	{ PHY_ID_KS8737, 0x00fffff0 },
212ea99a	530	{ PHY_ID_KSZ8021, 0x00ffffff },
b818d1a7	531	{ PHY_ID_KSZ8031, 0x00ffffff },
510d573f MV	532	{ PHY_ID_KSZ8041, 0x00fffff0 },
510d573f MV	533	{ PHY_ID_KSZ8051, 0x00fffff0 },
7ab59dc1 DC	534	{ PHY_ID_KSZ8061, 0x00fffff0 },
7ab59dc1 DC	535	{ PHY_ID_KSZ8081, 0x00fffff0 },
93272e07	536	{ PHY_ID_KSZ8873MLL, 0x00fffff0 },
7ab59dc1	537	{ PHY_ID_KSZ886X, 0x00fffff0 },
52a60ed2 DM	538	{ }
	539	};
	540
	541	MODULE_DEVICE_TABLE(mdio, micrel_tbl);