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d0507009 DC |
1 | /* |
2 | * drivers/net/phy/micrel.c | |
3 | * | |
4 | * Driver for Micrel PHYs | |
5 | * | |
6 | * Author: David J. Choi | |
7 | * | |
7ab59dc1 | 8 | * Copyright (c) 2010-2013 Micrel, Inc. |
ee0dc2fb | 9 | * Copyright (c) 2014 Johan Hovold <johan@kernel.org> |
d0507009 DC |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
7ab59dc1 DC |
16 | * Support : Micrel Phys: |
17 | * Giga phys: ksz9021, ksz9031 | |
18 | * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 | |
19 | * ksz8021, ksz8031, ksz8051, | |
20 | * ksz8081, ksz8091, | |
21 | * ksz8061, | |
22 | * Switch : ksz8873, ksz886x | |
d0507009 DC |
23 | */ |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/phy.h> | |
d606ef3f | 28 | #include <linux/micrel_phy.h> |
954c3967 | 29 | #include <linux/of.h> |
1fadee0c | 30 | #include <linux/clk.h> |
d0507009 | 31 | |
212ea99a MV |
32 | /* Operation Mode Strap Override */ |
33 | #define MII_KSZPHY_OMSO 0x16 | |
00aee095 | 34 | #define KSZPHY_OMSO_B_CAST_OFF BIT(9) |
2b0ba96c | 35 | #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) |
00aee095 JH |
36 | #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) |
37 | #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) | |
212ea99a | 38 | |
51f932c4 CD |
39 | /* general Interrupt control/status reg in vendor specific block. */ |
40 | #define MII_KSZPHY_INTCS 0x1B | |
00aee095 JH |
41 | #define KSZPHY_INTCS_JABBER BIT(15) |
42 | #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) | |
43 | #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) | |
44 | #define KSZPHY_INTCS_PARELLEL BIT(12) | |
45 | #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) | |
46 | #define KSZPHY_INTCS_LINK_DOWN BIT(10) | |
47 | #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) | |
48 | #define KSZPHY_INTCS_LINK_UP BIT(8) | |
51f932c4 CD |
49 | #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ |
50 | KSZPHY_INTCS_LINK_DOWN) | |
51 | ||
5a16778e JH |
52 | /* PHY Control 1 */ |
53 | #define MII_KSZPHY_CTRL_1 0x1e | |
54 | ||
55 | /* PHY Control 2 / PHY Control (if no PHY Control 1) */ | |
56 | #define MII_KSZPHY_CTRL_2 0x1f | |
57 | #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 | |
51f932c4 | 58 | /* bitmap of PHY register to set interrupt mode */ |
00aee095 | 59 | #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) |
63f44b2b | 60 | #define KSZPHY_RMII_REF_CLK_SEL BIT(7) |
51f932c4 | 61 | |
954c3967 SC |
62 | /* Write/read to/from extended registers */ |
63 | #define MII_KSZPHY_EXTREG 0x0b | |
64 | #define KSZPHY_EXTREG_WRITE 0x8000 | |
65 | ||
66 | #define MII_KSZPHY_EXTREG_WRITE 0x0c | |
67 | #define MII_KSZPHY_EXTREG_READ 0x0d | |
68 | ||
69 | /* Extended registers */ | |
70 | #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 | |
71 | #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 | |
72 | #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 | |
73 | ||
74 | #define PS_TO_REG 200 | |
75 | ||
2b2427d0 AL |
76 | struct kszphy_hw_stat { |
77 | const char *string; | |
78 | u8 reg; | |
79 | u8 bits; | |
80 | }; | |
81 | ||
82 | static struct kszphy_hw_stat kszphy_hw_stats[] = { | |
83 | { "phy_receive_errors", 21, 16}, | |
84 | { "phy_idle_errors", 10, 8 }, | |
85 | }; | |
86 | ||
e6a423a8 JH |
87 | struct kszphy_type { |
88 | u32 led_mode_reg; | |
c6f9575c | 89 | u16 interrupt_level_mask; |
0f95903e | 90 | bool has_broadcast_disable; |
2b0ba96c | 91 | bool has_nand_tree_disable; |
63f44b2b | 92 | bool has_rmii_ref_clk_sel; |
e6a423a8 JH |
93 | }; |
94 | ||
95 | struct kszphy_priv { | |
96 | const struct kszphy_type *type; | |
e7a792e9 | 97 | int led_mode; |
63f44b2b JH |
98 | bool rmii_ref_clk_sel; |
99 | bool rmii_ref_clk_sel_val; | |
2b2427d0 | 100 | u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; |
e6a423a8 JH |
101 | }; |
102 | ||
103 | static const struct kszphy_type ksz8021_type = { | |
104 | .led_mode_reg = MII_KSZPHY_CTRL_2, | |
d0e1df9c | 105 | .has_broadcast_disable = true, |
2b0ba96c | 106 | .has_nand_tree_disable = true, |
63f44b2b | 107 | .has_rmii_ref_clk_sel = true, |
e6a423a8 JH |
108 | }; |
109 | ||
110 | static const struct kszphy_type ksz8041_type = { | |
111 | .led_mode_reg = MII_KSZPHY_CTRL_1, | |
112 | }; | |
113 | ||
114 | static const struct kszphy_type ksz8051_type = { | |
115 | .led_mode_reg = MII_KSZPHY_CTRL_2, | |
2b0ba96c | 116 | .has_nand_tree_disable = true, |
e6a423a8 JH |
117 | }; |
118 | ||
119 | static const struct kszphy_type ksz8081_type = { | |
120 | .led_mode_reg = MII_KSZPHY_CTRL_2, | |
0f95903e | 121 | .has_broadcast_disable = true, |
2b0ba96c | 122 | .has_nand_tree_disable = true, |
86dc1342 | 123 | .has_rmii_ref_clk_sel = true, |
e6a423a8 JH |
124 | }; |
125 | ||
c6f9575c JH |
126 | static const struct kszphy_type ks8737_type = { |
127 | .interrupt_level_mask = BIT(14), | |
128 | }; | |
129 | ||
130 | static const struct kszphy_type ksz9021_type = { | |
131 | .interrupt_level_mask = BIT(14), | |
132 | }; | |
133 | ||
954c3967 | 134 | static int kszphy_extended_write(struct phy_device *phydev, |
756b5089 | 135 | u32 regnum, u16 val) |
954c3967 SC |
136 | { |
137 | phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); | |
138 | return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); | |
139 | } | |
140 | ||
141 | static int kszphy_extended_read(struct phy_device *phydev, | |
756b5089 | 142 | u32 regnum) |
954c3967 SC |
143 | { |
144 | phy_write(phydev, MII_KSZPHY_EXTREG, regnum); | |
145 | return phy_read(phydev, MII_KSZPHY_EXTREG_READ); | |
146 | } | |
147 | ||
51f932c4 CD |
148 | static int kszphy_ack_interrupt(struct phy_device *phydev) |
149 | { | |
150 | /* bit[7..0] int status, which is a read and clear register. */ | |
151 | int rc; | |
152 | ||
153 | rc = phy_read(phydev, MII_KSZPHY_INTCS); | |
154 | ||
155 | return (rc < 0) ? rc : 0; | |
156 | } | |
157 | ||
51f932c4 CD |
158 | static int kszphy_config_intr(struct phy_device *phydev) |
159 | { | |
c6f9575c JH |
160 | const struct kszphy_type *type = phydev->drv->driver_data; |
161 | int temp; | |
162 | u16 mask; | |
51f932c4 | 163 | |
c6f9575c JH |
164 | if (type && type->interrupt_level_mask) |
165 | mask = type->interrupt_level_mask; | |
166 | else | |
167 | mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; | |
51f932c4 CD |
168 | |
169 | /* set the interrupt pin active low */ | |
170 | temp = phy_read(phydev, MII_KSZPHY_CTRL); | |
5bb8fc0d JH |
171 | if (temp < 0) |
172 | return temp; | |
c6f9575c | 173 | temp &= ~mask; |
51f932c4 | 174 | phy_write(phydev, MII_KSZPHY_CTRL, temp); |
51f932c4 | 175 | |
c6f9575c JH |
176 | /* enable / disable interrupts */ |
177 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) | |
178 | temp = KSZPHY_INTCS_ALL; | |
179 | else | |
180 | temp = 0; | |
51f932c4 | 181 | |
c6f9575c | 182 | return phy_write(phydev, MII_KSZPHY_INTCS, temp); |
51f932c4 | 183 | } |
d0507009 | 184 | |
63f44b2b JH |
185 | static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) |
186 | { | |
187 | int ctrl; | |
188 | ||
189 | ctrl = phy_read(phydev, MII_KSZPHY_CTRL); | |
190 | if (ctrl < 0) | |
191 | return ctrl; | |
192 | ||
193 | if (val) | |
194 | ctrl |= KSZPHY_RMII_REF_CLK_SEL; | |
195 | else | |
196 | ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; | |
197 | ||
198 | return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); | |
199 | } | |
200 | ||
e7a792e9 | 201 | static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) |
20d8435a | 202 | { |
5a16778e | 203 | int rc, temp, shift; |
8620546c | 204 | |
5a16778e JH |
205 | switch (reg) { |
206 | case MII_KSZPHY_CTRL_1: | |
207 | shift = 14; | |
208 | break; | |
209 | case MII_KSZPHY_CTRL_2: | |
210 | shift = 4; | |
211 | break; | |
212 | default: | |
213 | return -EINVAL; | |
214 | } | |
215 | ||
20d8435a | 216 | temp = phy_read(phydev, reg); |
b7035860 JH |
217 | if (temp < 0) { |
218 | rc = temp; | |
219 | goto out; | |
220 | } | |
20d8435a | 221 | |
28bdc499 | 222 | temp &= ~(3 << shift); |
20d8435a BD |
223 | temp |= val << shift; |
224 | rc = phy_write(phydev, reg, temp); | |
b7035860 JH |
225 | out: |
226 | if (rc < 0) | |
227 | dev_err(&phydev->dev, "failed to set led mode\n"); | |
20d8435a | 228 | |
b7035860 | 229 | return rc; |
20d8435a BD |
230 | } |
231 | ||
bde15129 JH |
232 | /* Disable PHY address 0 as the broadcast address, so that it can be used as a |
233 | * unique (non-broadcast) address on a shared bus. | |
234 | */ | |
235 | static int kszphy_broadcast_disable(struct phy_device *phydev) | |
236 | { | |
237 | int ret; | |
238 | ||
239 | ret = phy_read(phydev, MII_KSZPHY_OMSO); | |
240 | if (ret < 0) | |
241 | goto out; | |
242 | ||
243 | ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); | |
244 | out: | |
245 | if (ret) | |
246 | dev_err(&phydev->dev, "failed to disable broadcast address\n"); | |
247 | ||
248 | return ret; | |
249 | } | |
250 | ||
2b0ba96c SR |
251 | static int kszphy_nand_tree_disable(struct phy_device *phydev) |
252 | { | |
253 | int ret; | |
254 | ||
255 | ret = phy_read(phydev, MII_KSZPHY_OMSO); | |
256 | if (ret < 0) | |
257 | goto out; | |
258 | ||
259 | if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) | |
260 | return 0; | |
261 | ||
262 | ret = phy_write(phydev, MII_KSZPHY_OMSO, | |
263 | ret & ~KSZPHY_OMSO_NAND_TREE_ON); | |
264 | out: | |
265 | if (ret) | |
266 | dev_err(&phydev->dev, "failed to disable NAND tree mode\n"); | |
267 | ||
268 | return ret; | |
269 | } | |
270 | ||
d0507009 DC |
271 | static int kszphy_config_init(struct phy_device *phydev) |
272 | { | |
e6a423a8 JH |
273 | struct kszphy_priv *priv = phydev->priv; |
274 | const struct kszphy_type *type; | |
63f44b2b | 275 | int ret; |
d0507009 | 276 | |
e6a423a8 JH |
277 | if (!priv) |
278 | return 0; | |
279 | ||
280 | type = priv->type; | |
281 | ||
0f95903e JH |
282 | if (type->has_broadcast_disable) |
283 | kszphy_broadcast_disable(phydev); | |
284 | ||
2b0ba96c SR |
285 | if (type->has_nand_tree_disable) |
286 | kszphy_nand_tree_disable(phydev); | |
287 | ||
63f44b2b JH |
288 | if (priv->rmii_ref_clk_sel) { |
289 | ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); | |
290 | if (ret) { | |
291 | dev_err(&phydev->dev, "failed to set rmii reference clock\n"); | |
292 | return ret; | |
293 | } | |
294 | } | |
295 | ||
e7a792e9 JH |
296 | if (priv->led_mode >= 0) |
297 | kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode); | |
e6a423a8 JH |
298 | |
299 | return 0; | |
20d8435a BD |
300 | } |
301 | ||
954c3967 | 302 | static int ksz9021_load_values_from_of(struct phy_device *phydev, |
3c9a9f7f JA |
303 | const struct device_node *of_node, |
304 | u16 reg, | |
305 | const char *field1, const char *field2, | |
306 | const char *field3, const char *field4) | |
954c3967 SC |
307 | { |
308 | int val1 = -1; | |
309 | int val2 = -2; | |
310 | int val3 = -3; | |
311 | int val4 = -4; | |
312 | int newval; | |
313 | int matches = 0; | |
314 | ||
315 | if (!of_property_read_u32(of_node, field1, &val1)) | |
316 | matches++; | |
317 | ||
318 | if (!of_property_read_u32(of_node, field2, &val2)) | |
319 | matches++; | |
320 | ||
321 | if (!of_property_read_u32(of_node, field3, &val3)) | |
322 | matches++; | |
323 | ||
324 | if (!of_property_read_u32(of_node, field4, &val4)) | |
325 | matches++; | |
326 | ||
327 | if (!matches) | |
328 | return 0; | |
329 | ||
330 | if (matches < 4) | |
331 | newval = kszphy_extended_read(phydev, reg); | |
332 | else | |
333 | newval = 0; | |
334 | ||
335 | if (val1 != -1) | |
336 | newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); | |
337 | ||
6a119745 | 338 | if (val2 != -2) |
954c3967 SC |
339 | newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); |
340 | ||
6a119745 | 341 | if (val3 != -3) |
954c3967 SC |
342 | newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); |
343 | ||
6a119745 | 344 | if (val4 != -4) |
954c3967 SC |
345 | newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); |
346 | ||
347 | return kszphy_extended_write(phydev, reg, newval); | |
348 | } | |
349 | ||
350 | static int ksz9021_config_init(struct phy_device *phydev) | |
351 | { | |
3c9a9f7f JA |
352 | const struct device *dev = &phydev->dev; |
353 | const struct device_node *of_node = dev->of_node; | |
651df218 AL |
354 | const struct device *dev_walker; |
355 | ||
356 | /* The Micrel driver has a deprecated option to place phy OF | |
357 | * properties in the MAC node. Walk up the tree of devices to | |
358 | * find a device with an OF node. | |
359 | */ | |
360 | dev_walker = &phydev->dev; | |
361 | do { | |
362 | of_node = dev_walker->of_node; | |
363 | dev_walker = dev_walker->parent; | |
364 | ||
365 | } while (!of_node && dev_walker); | |
954c3967 SC |
366 | |
367 | if (of_node) { | |
368 | ksz9021_load_values_from_of(phydev, of_node, | |
369 | MII_KSZPHY_CLK_CONTROL_PAD_SKEW, | |
370 | "txen-skew-ps", "txc-skew-ps", | |
371 | "rxdv-skew-ps", "rxc-skew-ps"); | |
372 | ksz9021_load_values_from_of(phydev, of_node, | |
373 | MII_KSZPHY_RX_DATA_PAD_SKEW, | |
374 | "rxd0-skew-ps", "rxd1-skew-ps", | |
375 | "rxd2-skew-ps", "rxd3-skew-ps"); | |
376 | ksz9021_load_values_from_of(phydev, of_node, | |
377 | MII_KSZPHY_TX_DATA_PAD_SKEW, | |
378 | "txd0-skew-ps", "txd1-skew-ps", | |
379 | "txd2-skew-ps", "txd3-skew-ps"); | |
380 | } | |
381 | return 0; | |
382 | } | |
383 | ||
6e4b8273 HC |
384 | #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d |
385 | #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e | |
386 | #define OP_DATA 1 | |
387 | #define KSZ9031_PS_TO_REG 60 | |
388 | ||
389 | /* Extended registers */ | |
6270e1ae JA |
390 | /* MMD Address 0x0 */ |
391 | #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 | |
392 | #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 | |
393 | ||
ae6c97bb | 394 | /* MMD Address 0x2 */ |
6e4b8273 HC |
395 | #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 |
396 | #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 | |
397 | #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 | |
398 | #define MII_KSZ9031RN_CLK_PAD_SKEW 8 | |
399 | ||
400 | static int ksz9031_extended_write(struct phy_device *phydev, | |
401 | u8 mode, u32 dev_addr, u32 regnum, u16 val) | |
402 | { | |
403 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); | |
404 | phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); | |
405 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); | |
406 | return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val); | |
407 | } | |
408 | ||
409 | static int ksz9031_extended_read(struct phy_device *phydev, | |
410 | u8 mode, u32 dev_addr, u32 regnum) | |
411 | { | |
412 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); | |
413 | phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); | |
414 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); | |
415 | return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG); | |
416 | } | |
417 | ||
418 | static int ksz9031_of_load_skew_values(struct phy_device *phydev, | |
3c9a9f7f | 419 | const struct device_node *of_node, |
6e4b8273 | 420 | u16 reg, size_t field_sz, |
3c9a9f7f | 421 | const char *field[], u8 numfields) |
6e4b8273 HC |
422 | { |
423 | int val[4] = {-1, -2, -3, -4}; | |
424 | int matches = 0; | |
425 | u16 mask; | |
426 | u16 maxval; | |
427 | u16 newval; | |
428 | int i; | |
429 | ||
430 | for (i = 0; i < numfields; i++) | |
431 | if (!of_property_read_u32(of_node, field[i], val + i)) | |
432 | matches++; | |
433 | ||
434 | if (!matches) | |
435 | return 0; | |
436 | ||
437 | if (matches < numfields) | |
438 | newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg); | |
439 | else | |
440 | newval = 0; | |
441 | ||
442 | maxval = (field_sz == 4) ? 0xf : 0x1f; | |
443 | for (i = 0; i < numfields; i++) | |
444 | if (val[i] != -(i + 1)) { | |
445 | mask = 0xffff; | |
446 | mask ^= maxval << (field_sz * i); | |
447 | newval = (newval & mask) | | |
448 | (((val[i] / KSZ9031_PS_TO_REG) & maxval) | |
449 | << (field_sz * i)); | |
450 | } | |
451 | ||
452 | return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); | |
453 | } | |
454 | ||
6270e1ae JA |
455 | static int ksz9031_center_flp_timing(struct phy_device *phydev) |
456 | { | |
457 | int result; | |
458 | ||
459 | /* Center KSZ9031RNX FLP timing at 16ms. */ | |
460 | result = ksz9031_extended_write(phydev, OP_DATA, 0, | |
461 | MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006); | |
462 | result = ksz9031_extended_write(phydev, OP_DATA, 0, | |
463 | MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80); | |
464 | ||
465 | if (result) | |
466 | return result; | |
467 | ||
468 | return genphy_restart_aneg(phydev); | |
469 | } | |
470 | ||
6e4b8273 HC |
471 | static int ksz9031_config_init(struct phy_device *phydev) |
472 | { | |
3c9a9f7f JA |
473 | const struct device *dev = &phydev->dev; |
474 | const struct device_node *of_node = dev->of_node; | |
475 | static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; | |
476 | static const char *rx_data_skews[4] = { | |
6e4b8273 HC |
477 | "rxd0-skew-ps", "rxd1-skew-ps", |
478 | "rxd2-skew-ps", "rxd3-skew-ps" | |
479 | }; | |
3c9a9f7f | 480 | static const char *tx_data_skews[4] = { |
6e4b8273 HC |
481 | "txd0-skew-ps", "txd1-skew-ps", |
482 | "txd2-skew-ps", "txd3-skew-ps" | |
483 | }; | |
3c9a9f7f | 484 | static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; |
6e4b8273 HC |
485 | |
486 | if (!of_node && dev->parent->of_node) | |
487 | of_node = dev->parent->of_node; | |
488 | ||
489 | if (of_node) { | |
490 | ksz9031_of_load_skew_values(phydev, of_node, | |
491 | MII_KSZ9031RN_CLK_PAD_SKEW, 5, | |
492 | clk_skews, 2); | |
493 | ||
494 | ksz9031_of_load_skew_values(phydev, of_node, | |
495 | MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, | |
496 | control_skews, 2); | |
497 | ||
498 | ksz9031_of_load_skew_values(phydev, of_node, | |
499 | MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, | |
500 | rx_data_skews, 4); | |
501 | ||
502 | ksz9031_of_load_skew_values(phydev, of_node, | |
503 | MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, | |
504 | tx_data_skews, 4); | |
505 | } | |
6270e1ae JA |
506 | |
507 | return ksz9031_center_flp_timing(phydev); | |
6e4b8273 HC |
508 | } |
509 | ||
93272e07 | 510 | #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 |
00aee095 JH |
511 | #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) |
512 | #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) | |
32d73b14 | 513 | static int ksz8873mll_read_status(struct phy_device *phydev) |
93272e07 JCPV |
514 | { |
515 | int regval; | |
516 | ||
517 | /* dummy read */ | |
518 | regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); | |
519 | ||
520 | regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); | |
521 | ||
522 | if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) | |
523 | phydev->duplex = DUPLEX_HALF; | |
524 | else | |
525 | phydev->duplex = DUPLEX_FULL; | |
526 | ||
527 | if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) | |
528 | phydev->speed = SPEED_10; | |
529 | else | |
530 | phydev->speed = SPEED_100; | |
531 | ||
532 | phydev->link = 1; | |
533 | phydev->pause = phydev->asym_pause = 0; | |
534 | ||
535 | return 0; | |
536 | } | |
537 | ||
d2fd719b NS |
538 | static int ksz9031_read_status(struct phy_device *phydev) |
539 | { | |
540 | int err; | |
541 | int regval; | |
542 | ||
543 | err = genphy_read_status(phydev); | |
544 | if (err) | |
545 | return err; | |
546 | ||
547 | /* Make sure the PHY is not broken. Read idle error count, | |
548 | * and reset the PHY if it is maxed out. | |
549 | */ | |
550 | regval = phy_read(phydev, MII_STAT1000); | |
551 | if ((regval & 0xFF) == 0xFF) { | |
552 | phy_init_hw(phydev); | |
553 | phydev->link = 0; | |
554 | } | |
555 | ||
556 | return 0; | |
557 | } | |
558 | ||
93272e07 JCPV |
559 | static int ksz8873mll_config_aneg(struct phy_device *phydev) |
560 | { | |
561 | return 0; | |
562 | } | |
563 | ||
19936942 VB |
564 | /* This routine returns -1 as an indication to the caller that the |
565 | * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE | |
566 | * MMD extended PHY registers. | |
567 | */ | |
568 | static int | |
569 | ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum, | |
570 | int regnum) | |
571 | { | |
572 | return -1; | |
573 | } | |
574 | ||
575 | /* This routine does nothing since the Micrel ksz9021 does not support | |
576 | * standard IEEE MMD extended PHY registers. | |
577 | */ | |
578 | static void | |
579 | ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum, | |
580 | int regnum, u32 val) | |
581 | { | |
582 | } | |
583 | ||
2b2427d0 AL |
584 | static int kszphy_get_sset_count(struct phy_device *phydev) |
585 | { | |
586 | return ARRAY_SIZE(kszphy_hw_stats); | |
587 | } | |
588 | ||
589 | static void kszphy_get_strings(struct phy_device *phydev, u8 *data) | |
590 | { | |
591 | int i; | |
592 | ||
593 | for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { | |
594 | memcpy(data + i * ETH_GSTRING_LEN, | |
595 | kszphy_hw_stats[i].string, ETH_GSTRING_LEN); | |
596 | } | |
597 | } | |
598 | ||
599 | #ifndef UINT64_MAX | |
600 | #define UINT64_MAX (u64)(~((u64)0)) | |
601 | #endif | |
602 | static u64 kszphy_get_stat(struct phy_device *phydev, int i) | |
603 | { | |
604 | struct kszphy_hw_stat stat = kszphy_hw_stats[i]; | |
605 | struct kszphy_priv *priv = phydev->priv; | |
606 | u64 val; | |
607 | ||
608 | val = phy_read(phydev, stat.reg); | |
609 | if (val < 0) { | |
610 | val = UINT64_MAX; | |
611 | } else { | |
612 | val = val & ((1 << stat.bits) - 1); | |
613 | priv->stats[i] += val; | |
614 | val = priv->stats[i]; | |
615 | } | |
616 | ||
617 | return val; | |
618 | } | |
619 | ||
620 | static void kszphy_get_stats(struct phy_device *phydev, | |
621 | struct ethtool_stats *stats, u64 *data) | |
622 | { | |
623 | int i; | |
624 | ||
625 | for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) | |
626 | data[i] = kszphy_get_stat(phydev, i); | |
627 | } | |
628 | ||
e6a423a8 JH |
629 | static int kszphy_probe(struct phy_device *phydev) |
630 | { | |
631 | const struct kszphy_type *type = phydev->drv->driver_data; | |
3c9a9f7f | 632 | const struct device_node *np = phydev->dev.of_node; |
e6a423a8 | 633 | struct kszphy_priv *priv; |
63f44b2b | 634 | struct clk *clk; |
e7a792e9 | 635 | int ret; |
e6a423a8 JH |
636 | |
637 | priv = devm_kzalloc(&phydev->dev, sizeof(*priv), GFP_KERNEL); | |
638 | if (!priv) | |
639 | return -ENOMEM; | |
640 | ||
641 | phydev->priv = priv; | |
642 | ||
643 | priv->type = type; | |
644 | ||
e7a792e9 JH |
645 | if (type->led_mode_reg) { |
646 | ret = of_property_read_u32(np, "micrel,led-mode", | |
647 | &priv->led_mode); | |
648 | if (ret) | |
649 | priv->led_mode = -1; | |
650 | ||
651 | if (priv->led_mode > 3) { | |
652 | dev_err(&phydev->dev, "invalid led mode: 0x%02x\n", | |
653 | priv->led_mode); | |
654 | priv->led_mode = -1; | |
655 | } | |
656 | } else { | |
657 | priv->led_mode = -1; | |
658 | } | |
659 | ||
1fadee0c | 660 | clk = devm_clk_get(&phydev->dev, "rmii-ref"); |
bced8701 NC |
661 | /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ |
662 | if (!IS_ERR_OR_NULL(clk)) { | |
1fadee0c | 663 | unsigned long rate = clk_get_rate(clk); |
86dc1342 | 664 | bool rmii_ref_clk_sel_25_mhz; |
1fadee0c | 665 | |
63f44b2b | 666 | priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; |
86dc1342 JH |
667 | rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, |
668 | "micrel,rmii-reference-clock-select-25-mhz"); | |
63f44b2b | 669 | |
1fadee0c | 670 | if (rate > 24500000 && rate < 25500000) { |
86dc1342 | 671 | priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; |
1fadee0c | 672 | } else if (rate > 49500000 && rate < 50500000) { |
86dc1342 | 673 | priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; |
1fadee0c SH |
674 | } else { |
675 | dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate); | |
676 | return -EINVAL; | |
677 | } | |
678 | } | |
679 | ||
63f44b2b JH |
680 | /* Support legacy board-file configuration */ |
681 | if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { | |
682 | priv->rmii_ref_clk_sel = true; | |
683 | priv->rmii_ref_clk_sel_val = true; | |
684 | } | |
685 | ||
686 | return 0; | |
1fadee0c SH |
687 | } |
688 | ||
d5bf9071 CH |
689 | static struct phy_driver ksphy_driver[] = { |
690 | { | |
51f932c4 CD |
691 | .phy_id = PHY_ID_KS8737, |
692 | .phy_id_mask = 0x00fffff0, | |
693 | .name = "Micrel KS8737", | |
694 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), | |
695 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
c6f9575c | 696 | .driver_data = &ks8737_type, |
51f932c4 CD |
697 | .config_init = kszphy_config_init, |
698 | .config_aneg = genphy_config_aneg, | |
699 | .read_status = genphy_read_status, | |
700 | .ack_interrupt = kszphy_ack_interrupt, | |
c6f9575c | 701 | .config_intr = kszphy_config_intr, |
2b2427d0 AL |
702 | .get_sset_count = kszphy_get_sset_count, |
703 | .get_strings = kszphy_get_strings, | |
704 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
705 | .suspend = genphy_suspend, |
706 | .resume = genphy_resume, | |
51f932c4 | 707 | .driver = { .owner = THIS_MODULE,}, |
212ea99a MV |
708 | }, { |
709 | .phy_id = PHY_ID_KSZ8021, | |
710 | .phy_id_mask = 0x00ffffff, | |
7ab59dc1 | 711 | .name = "Micrel KSZ8021 or KSZ8031", |
212ea99a MV |
712 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | |
713 | SUPPORTED_Asym_Pause), | |
714 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 | 715 | .driver_data = &ksz8021_type, |
63f44b2b | 716 | .probe = kszphy_probe, |
d0e1df9c | 717 | .config_init = kszphy_config_init, |
212ea99a MV |
718 | .config_aneg = genphy_config_aneg, |
719 | .read_status = genphy_read_status, | |
720 | .ack_interrupt = kszphy_ack_interrupt, | |
721 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
722 | .get_sset_count = kszphy_get_sset_count, |
723 | .get_strings = kszphy_get_strings, | |
724 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
725 | .suspend = genphy_suspend, |
726 | .resume = genphy_resume, | |
212ea99a | 727 | .driver = { .owner = THIS_MODULE,}, |
b818d1a7 HP |
728 | }, { |
729 | .phy_id = PHY_ID_KSZ8031, | |
730 | .phy_id_mask = 0x00ffffff, | |
731 | .name = "Micrel KSZ8031", | |
732 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | | |
733 | SUPPORTED_Asym_Pause), | |
734 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 | 735 | .driver_data = &ksz8021_type, |
63f44b2b | 736 | .probe = kszphy_probe, |
d0e1df9c | 737 | .config_init = kszphy_config_init, |
b818d1a7 HP |
738 | .config_aneg = genphy_config_aneg, |
739 | .read_status = genphy_read_status, | |
740 | .ack_interrupt = kszphy_ack_interrupt, | |
741 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
742 | .get_sset_count = kszphy_get_sset_count, |
743 | .get_strings = kszphy_get_strings, | |
744 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
745 | .suspend = genphy_suspend, |
746 | .resume = genphy_resume, | |
b818d1a7 | 747 | .driver = { .owner = THIS_MODULE,}, |
d5bf9071 | 748 | }, { |
510d573f | 749 | .phy_id = PHY_ID_KSZ8041, |
51f932c4 | 750 | .phy_id_mask = 0x00fffff0, |
510d573f | 751 | .name = "Micrel KSZ8041", |
51f932c4 CD |
752 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
753 | | SUPPORTED_Asym_Pause), | |
754 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 JH |
755 | .driver_data = &ksz8041_type, |
756 | .probe = kszphy_probe, | |
757 | .config_init = kszphy_config_init, | |
51f932c4 CD |
758 | .config_aneg = genphy_config_aneg, |
759 | .read_status = genphy_read_status, | |
760 | .ack_interrupt = kszphy_ack_interrupt, | |
761 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
762 | .get_sset_count = kszphy_get_sset_count, |
763 | .get_strings = kszphy_get_strings, | |
764 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
765 | .suspend = genphy_suspend, |
766 | .resume = genphy_resume, | |
51f932c4 | 767 | .driver = { .owner = THIS_MODULE,}, |
4bd7b512 SS |
768 | }, { |
769 | .phy_id = PHY_ID_KSZ8041RNLI, | |
770 | .phy_id_mask = 0x00fffff0, | |
771 | .name = "Micrel KSZ8041RNLI", | |
772 | .features = PHY_BASIC_FEATURES | | |
773 | SUPPORTED_Pause | SUPPORTED_Asym_Pause, | |
774 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 JH |
775 | .driver_data = &ksz8041_type, |
776 | .probe = kszphy_probe, | |
777 | .config_init = kszphy_config_init, | |
4bd7b512 SS |
778 | .config_aneg = genphy_config_aneg, |
779 | .read_status = genphy_read_status, | |
780 | .ack_interrupt = kszphy_ack_interrupt, | |
781 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
782 | .get_sset_count = kszphy_get_sset_count, |
783 | .get_strings = kszphy_get_strings, | |
784 | .get_stats = kszphy_get_stats, | |
4bd7b512 SS |
785 | .suspend = genphy_suspend, |
786 | .resume = genphy_resume, | |
787 | .driver = { .owner = THIS_MODULE,}, | |
d5bf9071 | 788 | }, { |
510d573f | 789 | .phy_id = PHY_ID_KSZ8051, |
d0507009 | 790 | .phy_id_mask = 0x00fffff0, |
510d573f | 791 | .name = "Micrel KSZ8051", |
51f932c4 CD |
792 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
793 | | SUPPORTED_Asym_Pause), | |
794 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 JH |
795 | .driver_data = &ksz8051_type, |
796 | .probe = kszphy_probe, | |
63f44b2b | 797 | .config_init = kszphy_config_init, |
d0507009 DC |
798 | .config_aneg = genphy_config_aneg, |
799 | .read_status = genphy_read_status, | |
51f932c4 CD |
800 | .ack_interrupt = kszphy_ack_interrupt, |
801 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
802 | .get_sset_count = kszphy_get_sset_count, |
803 | .get_strings = kszphy_get_strings, | |
804 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
805 | .suspend = genphy_suspend, |
806 | .resume = genphy_resume, | |
d0507009 | 807 | .driver = { .owner = THIS_MODULE,}, |
d5bf9071 | 808 | }, { |
510d573f MV |
809 | .phy_id = PHY_ID_KSZ8001, |
810 | .name = "Micrel KSZ8001 or KS8721", | |
48d7d0ad | 811 | .phy_id_mask = 0x00ffffff, |
51f932c4 CD |
812 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), |
813 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 JH |
814 | .driver_data = &ksz8041_type, |
815 | .probe = kszphy_probe, | |
816 | .config_init = kszphy_config_init, | |
d0507009 DC |
817 | .config_aneg = genphy_config_aneg, |
818 | .read_status = genphy_read_status, | |
51f932c4 CD |
819 | .ack_interrupt = kszphy_ack_interrupt, |
820 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
821 | .get_sset_count = kszphy_get_sset_count, |
822 | .get_strings = kszphy_get_strings, | |
823 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
824 | .suspend = genphy_suspend, |
825 | .resume = genphy_resume, | |
d0507009 | 826 | .driver = { .owner = THIS_MODULE,}, |
7ab59dc1 DC |
827 | }, { |
828 | .phy_id = PHY_ID_KSZ8081, | |
829 | .name = "Micrel KSZ8081 or KSZ8091", | |
830 | .phy_id_mask = 0x00fffff0, | |
831 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), | |
832 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 JH |
833 | .driver_data = &ksz8081_type, |
834 | .probe = kszphy_probe, | |
0f95903e | 835 | .config_init = kszphy_config_init, |
7ab59dc1 DC |
836 | .config_aneg = genphy_config_aneg, |
837 | .read_status = genphy_read_status, | |
838 | .ack_interrupt = kszphy_ack_interrupt, | |
839 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
840 | .get_sset_count = kszphy_get_sset_count, |
841 | .get_strings = kszphy_get_strings, | |
842 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
843 | .suspend = genphy_suspend, |
844 | .resume = genphy_resume, | |
7ab59dc1 DC |
845 | .driver = { .owner = THIS_MODULE,}, |
846 | }, { | |
847 | .phy_id = PHY_ID_KSZ8061, | |
848 | .name = "Micrel KSZ8061", | |
849 | .phy_id_mask = 0x00fffff0, | |
850 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), | |
851 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
852 | .config_init = kszphy_config_init, | |
853 | .config_aneg = genphy_config_aneg, | |
854 | .read_status = genphy_read_status, | |
855 | .ack_interrupt = kszphy_ack_interrupt, | |
856 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
857 | .get_sset_count = kszphy_get_sset_count, |
858 | .get_strings = kszphy_get_strings, | |
859 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
860 | .suspend = genphy_suspend, |
861 | .resume = genphy_resume, | |
7ab59dc1 | 862 | .driver = { .owner = THIS_MODULE,}, |
d5bf9071 | 863 | }, { |
d0507009 | 864 | .phy_id = PHY_ID_KSZ9021, |
48d7d0ad | 865 | .phy_id_mask = 0x000ffffe, |
d0507009 | 866 | .name = "Micrel KSZ9021 Gigabit PHY", |
32fcafbc | 867 | .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), |
51f932c4 | 868 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
c6f9575c | 869 | .driver_data = &ksz9021_type, |
954c3967 | 870 | .config_init = ksz9021_config_init, |
d0507009 DC |
871 | .config_aneg = genphy_config_aneg, |
872 | .read_status = genphy_read_status, | |
51f932c4 | 873 | .ack_interrupt = kszphy_ack_interrupt, |
c6f9575c | 874 | .config_intr = kszphy_config_intr, |
2b2427d0 AL |
875 | .get_sset_count = kszphy_get_sset_count, |
876 | .get_strings = kszphy_get_strings, | |
877 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
878 | .suspend = genphy_suspend, |
879 | .resume = genphy_resume, | |
19936942 VB |
880 | .read_mmd_indirect = ksz9021_rd_mmd_phyreg, |
881 | .write_mmd_indirect = ksz9021_wr_mmd_phyreg, | |
d0507009 | 882 | .driver = { .owner = THIS_MODULE, }, |
7ab59dc1 DC |
883 | }, { |
884 | .phy_id = PHY_ID_KSZ9031, | |
885 | .phy_id_mask = 0x00fffff0, | |
886 | .name = "Micrel KSZ9031 Gigabit PHY", | |
95e8b103 | 887 | .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), |
7ab59dc1 | 888 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
c6f9575c | 889 | .driver_data = &ksz9021_type, |
6e4b8273 | 890 | .config_init = ksz9031_config_init, |
7ab59dc1 | 891 | .config_aneg = genphy_config_aneg, |
d2fd719b | 892 | .read_status = ksz9031_read_status, |
7ab59dc1 | 893 | .ack_interrupt = kszphy_ack_interrupt, |
c6f9575c | 894 | .config_intr = kszphy_config_intr, |
2b2427d0 AL |
895 | .get_sset_count = kszphy_get_sset_count, |
896 | .get_strings = kszphy_get_strings, | |
897 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
898 | .suspend = genphy_suspend, |
899 | .resume = genphy_resume, | |
7ab59dc1 | 900 | .driver = { .owner = THIS_MODULE, }, |
93272e07 JCPV |
901 | }, { |
902 | .phy_id = PHY_ID_KSZ8873MLL, | |
903 | .phy_id_mask = 0x00fffff0, | |
904 | .name = "Micrel KSZ8873MLL Switch", | |
905 | .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause), | |
906 | .flags = PHY_HAS_MAGICANEG, | |
907 | .config_init = kszphy_config_init, | |
908 | .config_aneg = ksz8873mll_config_aneg, | |
909 | .read_status = ksz8873mll_read_status, | |
2b2427d0 AL |
910 | .get_sset_count = kszphy_get_sset_count, |
911 | .get_strings = kszphy_get_strings, | |
912 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
913 | .suspend = genphy_suspend, |
914 | .resume = genphy_resume, | |
93272e07 | 915 | .driver = { .owner = THIS_MODULE, }, |
7ab59dc1 DC |
916 | }, { |
917 | .phy_id = PHY_ID_KSZ886X, | |
918 | .phy_id_mask = 0x00fffff0, | |
919 | .name = "Micrel KSZ886X Switch", | |
920 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), | |
921 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
922 | .config_init = kszphy_config_init, | |
923 | .config_aneg = genphy_config_aneg, | |
924 | .read_status = genphy_read_status, | |
2b2427d0 AL |
925 | .get_sset_count = kszphy_get_sset_count, |
926 | .get_strings = kszphy_get_strings, | |
927 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
928 | .suspend = genphy_suspend, |
929 | .resume = genphy_resume, | |
7ab59dc1 | 930 | .driver = { .owner = THIS_MODULE, }, |
d5bf9071 | 931 | } }; |
d0507009 | 932 | |
50fd7150 | 933 | module_phy_driver(ksphy_driver); |
d0507009 DC |
934 | |
935 | MODULE_DESCRIPTION("Micrel PHY driver"); | |
936 | MODULE_AUTHOR("David J. Choi"); | |
937 | MODULE_LICENSE("GPL"); | |
52a60ed2 | 938 | |
cf93c945 | 939 | static struct mdio_device_id __maybe_unused micrel_tbl[] = { |
48d7d0ad | 940 | { PHY_ID_KSZ9021, 0x000ffffe }, |
7ab59dc1 | 941 | { PHY_ID_KSZ9031, 0x00fffff0 }, |
510d573f | 942 | { PHY_ID_KSZ8001, 0x00ffffff }, |
51f932c4 | 943 | { PHY_ID_KS8737, 0x00fffff0 }, |
212ea99a | 944 | { PHY_ID_KSZ8021, 0x00ffffff }, |
b818d1a7 | 945 | { PHY_ID_KSZ8031, 0x00ffffff }, |
510d573f MV |
946 | { PHY_ID_KSZ8041, 0x00fffff0 }, |
947 | { PHY_ID_KSZ8051, 0x00fffff0 }, | |
7ab59dc1 DC |
948 | { PHY_ID_KSZ8061, 0x00fffff0 }, |
949 | { PHY_ID_KSZ8081, 0x00fffff0 }, | |
93272e07 | 950 | { PHY_ID_KSZ8873MLL, 0x00fffff0 }, |
7ab59dc1 | 951 | { PHY_ID_KSZ886X, 0x00fffff0 }, |
52a60ed2 DM |
952 | { } |
953 | }; | |
954 | ||
955 | MODULE_DEVICE_TABLE(mdio, micrel_tbl); |