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d0507009 DC |
1 | /* |
2 | * drivers/net/phy/micrel.c | |
3 | * | |
4 | * Driver for Micrel PHYs | |
5 | * | |
6 | * Author: David J. Choi | |
7 | * | |
7ab59dc1 | 8 | * Copyright (c) 2010-2013 Micrel, Inc. |
ee0dc2fb | 9 | * Copyright (c) 2014 Johan Hovold <johan@kernel.org> |
d0507009 DC |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
7ab59dc1 DC |
16 | * Support : Micrel Phys: |
17 | * Giga phys: ksz9021, ksz9031 | |
18 | * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 | |
19 | * ksz8021, ksz8031, ksz8051, | |
20 | * ksz8081, ksz8091, | |
21 | * ksz8061, | |
22 | * Switch : ksz8873, ksz886x | |
d0507009 DC |
23 | */ |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/phy.h> | |
d606ef3f | 28 | #include <linux/micrel_phy.h> |
954c3967 | 29 | #include <linux/of.h> |
1fadee0c | 30 | #include <linux/clk.h> |
d0507009 | 31 | |
212ea99a MV |
32 | /* Operation Mode Strap Override */ |
33 | #define MII_KSZPHY_OMSO 0x16 | |
00aee095 | 34 | #define KSZPHY_OMSO_B_CAST_OFF BIT(9) |
2b0ba96c | 35 | #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) |
00aee095 JH |
36 | #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) |
37 | #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) | |
212ea99a | 38 | |
51f932c4 CD |
39 | /* general Interrupt control/status reg in vendor specific block. */ |
40 | #define MII_KSZPHY_INTCS 0x1B | |
00aee095 JH |
41 | #define KSZPHY_INTCS_JABBER BIT(15) |
42 | #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) | |
43 | #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) | |
44 | #define KSZPHY_INTCS_PARELLEL BIT(12) | |
45 | #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) | |
46 | #define KSZPHY_INTCS_LINK_DOWN BIT(10) | |
47 | #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) | |
48 | #define KSZPHY_INTCS_LINK_UP BIT(8) | |
51f932c4 CD |
49 | #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ |
50 | KSZPHY_INTCS_LINK_DOWN) | |
51 | ||
5a16778e JH |
52 | /* PHY Control 1 */ |
53 | #define MII_KSZPHY_CTRL_1 0x1e | |
54 | ||
55 | /* PHY Control 2 / PHY Control (if no PHY Control 1) */ | |
56 | #define MII_KSZPHY_CTRL_2 0x1f | |
57 | #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 | |
51f932c4 | 58 | /* bitmap of PHY register to set interrupt mode */ |
00aee095 | 59 | #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) |
63f44b2b | 60 | #define KSZPHY_RMII_REF_CLK_SEL BIT(7) |
51f932c4 | 61 | |
954c3967 SC |
62 | /* Write/read to/from extended registers */ |
63 | #define MII_KSZPHY_EXTREG 0x0b | |
64 | #define KSZPHY_EXTREG_WRITE 0x8000 | |
65 | ||
66 | #define MII_KSZPHY_EXTREG_WRITE 0x0c | |
67 | #define MII_KSZPHY_EXTREG_READ 0x0d | |
68 | ||
69 | /* Extended registers */ | |
70 | #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 | |
71 | #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 | |
72 | #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 | |
73 | ||
74 | #define PS_TO_REG 200 | |
75 | ||
e6a423a8 JH |
76 | struct kszphy_type { |
77 | u32 led_mode_reg; | |
c6f9575c | 78 | u16 interrupt_level_mask; |
0f95903e | 79 | bool has_broadcast_disable; |
2b0ba96c | 80 | bool has_nand_tree_disable; |
63f44b2b | 81 | bool has_rmii_ref_clk_sel; |
e6a423a8 JH |
82 | }; |
83 | ||
84 | struct kszphy_priv { | |
85 | const struct kszphy_type *type; | |
e7a792e9 | 86 | int led_mode; |
63f44b2b JH |
87 | bool rmii_ref_clk_sel; |
88 | bool rmii_ref_clk_sel_val; | |
e6a423a8 JH |
89 | }; |
90 | ||
91 | static const struct kszphy_type ksz8021_type = { | |
92 | .led_mode_reg = MII_KSZPHY_CTRL_2, | |
d0e1df9c | 93 | .has_broadcast_disable = true, |
2b0ba96c | 94 | .has_nand_tree_disable = true, |
63f44b2b | 95 | .has_rmii_ref_clk_sel = true, |
e6a423a8 JH |
96 | }; |
97 | ||
98 | static const struct kszphy_type ksz8041_type = { | |
99 | .led_mode_reg = MII_KSZPHY_CTRL_1, | |
100 | }; | |
101 | ||
102 | static const struct kszphy_type ksz8051_type = { | |
103 | .led_mode_reg = MII_KSZPHY_CTRL_2, | |
2b0ba96c | 104 | .has_nand_tree_disable = true, |
e6a423a8 JH |
105 | }; |
106 | ||
107 | static const struct kszphy_type ksz8081_type = { | |
108 | .led_mode_reg = MII_KSZPHY_CTRL_2, | |
0f95903e | 109 | .has_broadcast_disable = true, |
2b0ba96c | 110 | .has_nand_tree_disable = true, |
86dc1342 | 111 | .has_rmii_ref_clk_sel = true, |
e6a423a8 JH |
112 | }; |
113 | ||
c6f9575c JH |
114 | static const struct kszphy_type ks8737_type = { |
115 | .interrupt_level_mask = BIT(14), | |
116 | }; | |
117 | ||
118 | static const struct kszphy_type ksz9021_type = { | |
119 | .interrupt_level_mask = BIT(14), | |
120 | }; | |
121 | ||
954c3967 | 122 | static int kszphy_extended_write(struct phy_device *phydev, |
756b5089 | 123 | u32 regnum, u16 val) |
954c3967 SC |
124 | { |
125 | phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); | |
126 | return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); | |
127 | } | |
128 | ||
129 | static int kszphy_extended_read(struct phy_device *phydev, | |
756b5089 | 130 | u32 regnum) |
954c3967 SC |
131 | { |
132 | phy_write(phydev, MII_KSZPHY_EXTREG, regnum); | |
133 | return phy_read(phydev, MII_KSZPHY_EXTREG_READ); | |
134 | } | |
135 | ||
51f932c4 CD |
136 | static int kszphy_ack_interrupt(struct phy_device *phydev) |
137 | { | |
138 | /* bit[7..0] int status, which is a read and clear register. */ | |
139 | int rc; | |
140 | ||
141 | rc = phy_read(phydev, MII_KSZPHY_INTCS); | |
142 | ||
143 | return (rc < 0) ? rc : 0; | |
144 | } | |
145 | ||
51f932c4 CD |
146 | static int kszphy_config_intr(struct phy_device *phydev) |
147 | { | |
c6f9575c JH |
148 | const struct kszphy_type *type = phydev->drv->driver_data; |
149 | int temp; | |
150 | u16 mask; | |
51f932c4 | 151 | |
c6f9575c JH |
152 | if (type && type->interrupt_level_mask) |
153 | mask = type->interrupt_level_mask; | |
154 | else | |
155 | mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; | |
51f932c4 CD |
156 | |
157 | /* set the interrupt pin active low */ | |
158 | temp = phy_read(phydev, MII_KSZPHY_CTRL); | |
5bb8fc0d JH |
159 | if (temp < 0) |
160 | return temp; | |
c6f9575c | 161 | temp &= ~mask; |
51f932c4 | 162 | phy_write(phydev, MII_KSZPHY_CTRL, temp); |
51f932c4 | 163 | |
c6f9575c JH |
164 | /* enable / disable interrupts */ |
165 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) | |
166 | temp = KSZPHY_INTCS_ALL; | |
167 | else | |
168 | temp = 0; | |
51f932c4 | 169 | |
c6f9575c | 170 | return phy_write(phydev, MII_KSZPHY_INTCS, temp); |
51f932c4 | 171 | } |
d0507009 | 172 | |
63f44b2b JH |
173 | static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) |
174 | { | |
175 | int ctrl; | |
176 | ||
177 | ctrl = phy_read(phydev, MII_KSZPHY_CTRL); | |
178 | if (ctrl < 0) | |
179 | return ctrl; | |
180 | ||
181 | if (val) | |
182 | ctrl |= KSZPHY_RMII_REF_CLK_SEL; | |
183 | else | |
184 | ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; | |
185 | ||
186 | return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); | |
187 | } | |
188 | ||
e7a792e9 | 189 | static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) |
20d8435a | 190 | { |
5a16778e | 191 | int rc, temp, shift; |
8620546c | 192 | |
5a16778e JH |
193 | switch (reg) { |
194 | case MII_KSZPHY_CTRL_1: | |
195 | shift = 14; | |
196 | break; | |
197 | case MII_KSZPHY_CTRL_2: | |
198 | shift = 4; | |
199 | break; | |
200 | default: | |
201 | return -EINVAL; | |
202 | } | |
203 | ||
20d8435a | 204 | temp = phy_read(phydev, reg); |
b7035860 JH |
205 | if (temp < 0) { |
206 | rc = temp; | |
207 | goto out; | |
208 | } | |
20d8435a | 209 | |
28bdc499 | 210 | temp &= ~(3 << shift); |
20d8435a BD |
211 | temp |= val << shift; |
212 | rc = phy_write(phydev, reg, temp); | |
b7035860 JH |
213 | out: |
214 | if (rc < 0) | |
215 | dev_err(&phydev->dev, "failed to set led mode\n"); | |
20d8435a | 216 | |
b7035860 | 217 | return rc; |
20d8435a BD |
218 | } |
219 | ||
bde15129 JH |
220 | /* Disable PHY address 0 as the broadcast address, so that it can be used as a |
221 | * unique (non-broadcast) address on a shared bus. | |
222 | */ | |
223 | static int kszphy_broadcast_disable(struct phy_device *phydev) | |
224 | { | |
225 | int ret; | |
226 | ||
227 | ret = phy_read(phydev, MII_KSZPHY_OMSO); | |
228 | if (ret < 0) | |
229 | goto out; | |
230 | ||
231 | ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); | |
232 | out: | |
233 | if (ret) | |
234 | dev_err(&phydev->dev, "failed to disable broadcast address\n"); | |
235 | ||
236 | return ret; | |
237 | } | |
238 | ||
2b0ba96c SR |
239 | static int kszphy_nand_tree_disable(struct phy_device *phydev) |
240 | { | |
241 | int ret; | |
242 | ||
243 | ret = phy_read(phydev, MII_KSZPHY_OMSO); | |
244 | if (ret < 0) | |
245 | goto out; | |
246 | ||
247 | if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) | |
248 | return 0; | |
249 | ||
250 | ret = phy_write(phydev, MII_KSZPHY_OMSO, | |
251 | ret & ~KSZPHY_OMSO_NAND_TREE_ON); | |
252 | out: | |
253 | if (ret) | |
254 | dev_err(&phydev->dev, "failed to disable NAND tree mode\n"); | |
255 | ||
256 | return ret; | |
257 | } | |
258 | ||
d0507009 DC |
259 | static int kszphy_config_init(struct phy_device *phydev) |
260 | { | |
e6a423a8 JH |
261 | struct kszphy_priv *priv = phydev->priv; |
262 | const struct kszphy_type *type; | |
63f44b2b | 263 | int ret; |
d0507009 | 264 | |
e6a423a8 JH |
265 | if (!priv) |
266 | return 0; | |
267 | ||
268 | type = priv->type; | |
269 | ||
0f95903e JH |
270 | if (type->has_broadcast_disable) |
271 | kszphy_broadcast_disable(phydev); | |
272 | ||
2b0ba96c SR |
273 | if (type->has_nand_tree_disable) |
274 | kszphy_nand_tree_disable(phydev); | |
275 | ||
63f44b2b JH |
276 | if (priv->rmii_ref_clk_sel) { |
277 | ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); | |
278 | if (ret) { | |
279 | dev_err(&phydev->dev, "failed to set rmii reference clock\n"); | |
280 | return ret; | |
281 | } | |
282 | } | |
283 | ||
e7a792e9 JH |
284 | if (priv->led_mode >= 0) |
285 | kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode); | |
e6a423a8 JH |
286 | |
287 | return 0; | |
20d8435a BD |
288 | } |
289 | ||
954c3967 | 290 | static int ksz9021_load_values_from_of(struct phy_device *phydev, |
3c9a9f7f JA |
291 | const struct device_node *of_node, |
292 | u16 reg, | |
293 | const char *field1, const char *field2, | |
294 | const char *field3, const char *field4) | |
954c3967 SC |
295 | { |
296 | int val1 = -1; | |
297 | int val2 = -2; | |
298 | int val3 = -3; | |
299 | int val4 = -4; | |
300 | int newval; | |
301 | int matches = 0; | |
302 | ||
303 | if (!of_property_read_u32(of_node, field1, &val1)) | |
304 | matches++; | |
305 | ||
306 | if (!of_property_read_u32(of_node, field2, &val2)) | |
307 | matches++; | |
308 | ||
309 | if (!of_property_read_u32(of_node, field3, &val3)) | |
310 | matches++; | |
311 | ||
312 | if (!of_property_read_u32(of_node, field4, &val4)) | |
313 | matches++; | |
314 | ||
315 | if (!matches) | |
316 | return 0; | |
317 | ||
318 | if (matches < 4) | |
319 | newval = kszphy_extended_read(phydev, reg); | |
320 | else | |
321 | newval = 0; | |
322 | ||
323 | if (val1 != -1) | |
324 | newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); | |
325 | ||
6a119745 | 326 | if (val2 != -2) |
954c3967 SC |
327 | newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); |
328 | ||
6a119745 | 329 | if (val3 != -3) |
954c3967 SC |
330 | newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); |
331 | ||
6a119745 | 332 | if (val4 != -4) |
954c3967 SC |
333 | newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); |
334 | ||
335 | return kszphy_extended_write(phydev, reg, newval); | |
336 | } | |
337 | ||
338 | static int ksz9021_config_init(struct phy_device *phydev) | |
339 | { | |
3c9a9f7f JA |
340 | const struct device *dev = &phydev->dev; |
341 | const struct device_node *of_node = dev->of_node; | |
651df218 AL |
342 | const struct device *dev_walker; |
343 | ||
344 | /* The Micrel driver has a deprecated option to place phy OF | |
345 | * properties in the MAC node. Walk up the tree of devices to | |
346 | * find a device with an OF node. | |
347 | */ | |
348 | dev_walker = &phydev->dev; | |
349 | do { | |
350 | of_node = dev_walker->of_node; | |
351 | dev_walker = dev_walker->parent; | |
352 | ||
353 | } while (!of_node && dev_walker); | |
954c3967 SC |
354 | |
355 | if (of_node) { | |
356 | ksz9021_load_values_from_of(phydev, of_node, | |
357 | MII_KSZPHY_CLK_CONTROL_PAD_SKEW, | |
358 | "txen-skew-ps", "txc-skew-ps", | |
359 | "rxdv-skew-ps", "rxc-skew-ps"); | |
360 | ksz9021_load_values_from_of(phydev, of_node, | |
361 | MII_KSZPHY_RX_DATA_PAD_SKEW, | |
362 | "rxd0-skew-ps", "rxd1-skew-ps", | |
363 | "rxd2-skew-ps", "rxd3-skew-ps"); | |
364 | ksz9021_load_values_from_of(phydev, of_node, | |
365 | MII_KSZPHY_TX_DATA_PAD_SKEW, | |
366 | "txd0-skew-ps", "txd1-skew-ps", | |
367 | "txd2-skew-ps", "txd3-skew-ps"); | |
368 | } | |
369 | return 0; | |
370 | } | |
371 | ||
6e4b8273 HC |
372 | #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d |
373 | #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e | |
374 | #define OP_DATA 1 | |
375 | #define KSZ9031_PS_TO_REG 60 | |
376 | ||
377 | /* Extended registers */ | |
6270e1ae JA |
378 | /* MMD Address 0x0 */ |
379 | #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 | |
380 | #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 | |
381 | ||
ae6c97bb | 382 | /* MMD Address 0x2 */ |
6e4b8273 HC |
383 | #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 |
384 | #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 | |
385 | #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 | |
386 | #define MII_KSZ9031RN_CLK_PAD_SKEW 8 | |
387 | ||
388 | static int ksz9031_extended_write(struct phy_device *phydev, | |
389 | u8 mode, u32 dev_addr, u32 regnum, u16 val) | |
390 | { | |
391 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); | |
392 | phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); | |
393 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); | |
394 | return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val); | |
395 | } | |
396 | ||
397 | static int ksz9031_extended_read(struct phy_device *phydev, | |
398 | u8 mode, u32 dev_addr, u32 regnum) | |
399 | { | |
400 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); | |
401 | phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); | |
402 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); | |
403 | return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG); | |
404 | } | |
405 | ||
406 | static int ksz9031_of_load_skew_values(struct phy_device *phydev, | |
3c9a9f7f | 407 | const struct device_node *of_node, |
6e4b8273 | 408 | u16 reg, size_t field_sz, |
3c9a9f7f | 409 | const char *field[], u8 numfields) |
6e4b8273 HC |
410 | { |
411 | int val[4] = {-1, -2, -3, -4}; | |
412 | int matches = 0; | |
413 | u16 mask; | |
414 | u16 maxval; | |
415 | u16 newval; | |
416 | int i; | |
417 | ||
418 | for (i = 0; i < numfields; i++) | |
419 | if (!of_property_read_u32(of_node, field[i], val + i)) | |
420 | matches++; | |
421 | ||
422 | if (!matches) | |
423 | return 0; | |
424 | ||
425 | if (matches < numfields) | |
426 | newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg); | |
427 | else | |
428 | newval = 0; | |
429 | ||
430 | maxval = (field_sz == 4) ? 0xf : 0x1f; | |
431 | for (i = 0; i < numfields; i++) | |
432 | if (val[i] != -(i + 1)) { | |
433 | mask = 0xffff; | |
434 | mask ^= maxval << (field_sz * i); | |
435 | newval = (newval & mask) | | |
436 | (((val[i] / KSZ9031_PS_TO_REG) & maxval) | |
437 | << (field_sz * i)); | |
438 | } | |
439 | ||
440 | return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); | |
441 | } | |
442 | ||
6270e1ae JA |
443 | static int ksz9031_center_flp_timing(struct phy_device *phydev) |
444 | { | |
445 | int result; | |
446 | ||
447 | /* Center KSZ9031RNX FLP timing at 16ms. */ | |
448 | result = ksz9031_extended_write(phydev, OP_DATA, 0, | |
449 | MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006); | |
450 | result = ksz9031_extended_write(phydev, OP_DATA, 0, | |
451 | MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80); | |
452 | ||
453 | if (result) | |
454 | return result; | |
455 | ||
456 | return genphy_restart_aneg(phydev); | |
457 | } | |
458 | ||
6e4b8273 HC |
459 | static int ksz9031_config_init(struct phy_device *phydev) |
460 | { | |
3c9a9f7f JA |
461 | const struct device *dev = &phydev->dev; |
462 | const struct device_node *of_node = dev->of_node; | |
463 | static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; | |
464 | static const char *rx_data_skews[4] = { | |
6e4b8273 HC |
465 | "rxd0-skew-ps", "rxd1-skew-ps", |
466 | "rxd2-skew-ps", "rxd3-skew-ps" | |
467 | }; | |
3c9a9f7f | 468 | static const char *tx_data_skews[4] = { |
6e4b8273 HC |
469 | "txd0-skew-ps", "txd1-skew-ps", |
470 | "txd2-skew-ps", "txd3-skew-ps" | |
471 | }; | |
3c9a9f7f | 472 | static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; |
6e4b8273 HC |
473 | |
474 | if (!of_node && dev->parent->of_node) | |
475 | of_node = dev->parent->of_node; | |
476 | ||
477 | if (of_node) { | |
478 | ksz9031_of_load_skew_values(phydev, of_node, | |
479 | MII_KSZ9031RN_CLK_PAD_SKEW, 5, | |
480 | clk_skews, 2); | |
481 | ||
482 | ksz9031_of_load_skew_values(phydev, of_node, | |
483 | MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, | |
484 | control_skews, 2); | |
485 | ||
486 | ksz9031_of_load_skew_values(phydev, of_node, | |
487 | MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, | |
488 | rx_data_skews, 4); | |
489 | ||
490 | ksz9031_of_load_skew_values(phydev, of_node, | |
491 | MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, | |
492 | tx_data_skews, 4); | |
493 | } | |
6270e1ae JA |
494 | |
495 | return ksz9031_center_flp_timing(phydev); | |
6e4b8273 HC |
496 | } |
497 | ||
93272e07 | 498 | #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 |
00aee095 JH |
499 | #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) |
500 | #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) | |
32d73b14 | 501 | static int ksz8873mll_read_status(struct phy_device *phydev) |
93272e07 JCPV |
502 | { |
503 | int regval; | |
504 | ||
505 | /* dummy read */ | |
506 | regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); | |
507 | ||
508 | regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); | |
509 | ||
510 | if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) | |
511 | phydev->duplex = DUPLEX_HALF; | |
512 | else | |
513 | phydev->duplex = DUPLEX_FULL; | |
514 | ||
515 | if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) | |
516 | phydev->speed = SPEED_10; | |
517 | else | |
518 | phydev->speed = SPEED_100; | |
519 | ||
520 | phydev->link = 1; | |
521 | phydev->pause = phydev->asym_pause = 0; | |
522 | ||
523 | return 0; | |
524 | } | |
525 | ||
d2fd719b NS |
526 | static int ksz9031_read_status(struct phy_device *phydev) |
527 | { | |
528 | int err; | |
529 | int regval; | |
530 | ||
531 | err = genphy_read_status(phydev); | |
532 | if (err) | |
533 | return err; | |
534 | ||
535 | /* Make sure the PHY is not broken. Read idle error count, | |
536 | * and reset the PHY if it is maxed out. | |
537 | */ | |
538 | regval = phy_read(phydev, MII_STAT1000); | |
539 | if ((regval & 0xFF) == 0xFF) { | |
540 | phy_init_hw(phydev); | |
541 | phydev->link = 0; | |
542 | } | |
543 | ||
544 | return 0; | |
545 | } | |
546 | ||
93272e07 JCPV |
547 | static int ksz8873mll_config_aneg(struct phy_device *phydev) |
548 | { | |
549 | return 0; | |
550 | } | |
551 | ||
19936942 VB |
552 | /* This routine returns -1 as an indication to the caller that the |
553 | * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE | |
554 | * MMD extended PHY registers. | |
555 | */ | |
556 | static int | |
557 | ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum, | |
558 | int regnum) | |
559 | { | |
560 | return -1; | |
561 | } | |
562 | ||
563 | /* This routine does nothing since the Micrel ksz9021 does not support | |
564 | * standard IEEE MMD extended PHY registers. | |
565 | */ | |
566 | static void | |
567 | ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum, | |
568 | int regnum, u32 val) | |
569 | { | |
570 | } | |
571 | ||
e6a423a8 JH |
572 | static int kszphy_probe(struct phy_device *phydev) |
573 | { | |
574 | const struct kszphy_type *type = phydev->drv->driver_data; | |
3c9a9f7f | 575 | const struct device_node *np = phydev->dev.of_node; |
e6a423a8 | 576 | struct kszphy_priv *priv; |
63f44b2b | 577 | struct clk *clk; |
e7a792e9 | 578 | int ret; |
e6a423a8 JH |
579 | |
580 | priv = devm_kzalloc(&phydev->dev, sizeof(*priv), GFP_KERNEL); | |
581 | if (!priv) | |
582 | return -ENOMEM; | |
583 | ||
584 | phydev->priv = priv; | |
585 | ||
586 | priv->type = type; | |
587 | ||
e7a792e9 JH |
588 | if (type->led_mode_reg) { |
589 | ret = of_property_read_u32(np, "micrel,led-mode", | |
590 | &priv->led_mode); | |
591 | if (ret) | |
592 | priv->led_mode = -1; | |
593 | ||
594 | if (priv->led_mode > 3) { | |
595 | dev_err(&phydev->dev, "invalid led mode: 0x%02x\n", | |
596 | priv->led_mode); | |
597 | priv->led_mode = -1; | |
598 | } | |
599 | } else { | |
600 | priv->led_mode = -1; | |
601 | } | |
602 | ||
1fadee0c | 603 | clk = devm_clk_get(&phydev->dev, "rmii-ref"); |
bced8701 NC |
604 | /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ |
605 | if (!IS_ERR_OR_NULL(clk)) { | |
1fadee0c | 606 | unsigned long rate = clk_get_rate(clk); |
86dc1342 | 607 | bool rmii_ref_clk_sel_25_mhz; |
1fadee0c | 608 | |
63f44b2b | 609 | priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; |
86dc1342 JH |
610 | rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, |
611 | "micrel,rmii-reference-clock-select-25-mhz"); | |
63f44b2b | 612 | |
1fadee0c | 613 | if (rate > 24500000 && rate < 25500000) { |
86dc1342 | 614 | priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; |
1fadee0c | 615 | } else if (rate > 49500000 && rate < 50500000) { |
86dc1342 | 616 | priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; |
1fadee0c SH |
617 | } else { |
618 | dev_err(&phydev->dev, "Clock rate out of range: %ld\n", rate); | |
619 | return -EINVAL; | |
620 | } | |
621 | } | |
622 | ||
63f44b2b JH |
623 | /* Support legacy board-file configuration */ |
624 | if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { | |
625 | priv->rmii_ref_clk_sel = true; | |
626 | priv->rmii_ref_clk_sel_val = true; | |
627 | } | |
628 | ||
629 | return 0; | |
1fadee0c SH |
630 | } |
631 | ||
d5bf9071 CH |
632 | static struct phy_driver ksphy_driver[] = { |
633 | { | |
51f932c4 CD |
634 | .phy_id = PHY_ID_KS8737, |
635 | .phy_id_mask = 0x00fffff0, | |
636 | .name = "Micrel KS8737", | |
637 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), | |
638 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
c6f9575c | 639 | .driver_data = &ks8737_type, |
51f932c4 CD |
640 | .config_init = kszphy_config_init, |
641 | .config_aneg = genphy_config_aneg, | |
642 | .read_status = genphy_read_status, | |
643 | .ack_interrupt = kszphy_ack_interrupt, | |
c6f9575c | 644 | .config_intr = kszphy_config_intr, |
1a5465f5 PV |
645 | .suspend = genphy_suspend, |
646 | .resume = genphy_resume, | |
51f932c4 | 647 | .driver = { .owner = THIS_MODULE,}, |
212ea99a MV |
648 | }, { |
649 | .phy_id = PHY_ID_KSZ8021, | |
650 | .phy_id_mask = 0x00ffffff, | |
7ab59dc1 | 651 | .name = "Micrel KSZ8021 or KSZ8031", |
212ea99a MV |
652 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | |
653 | SUPPORTED_Asym_Pause), | |
654 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 | 655 | .driver_data = &ksz8021_type, |
63f44b2b | 656 | .probe = kszphy_probe, |
d0e1df9c | 657 | .config_init = kszphy_config_init, |
212ea99a MV |
658 | .config_aneg = genphy_config_aneg, |
659 | .read_status = genphy_read_status, | |
660 | .ack_interrupt = kszphy_ack_interrupt, | |
661 | .config_intr = kszphy_config_intr, | |
1a5465f5 PV |
662 | .suspend = genphy_suspend, |
663 | .resume = genphy_resume, | |
212ea99a | 664 | .driver = { .owner = THIS_MODULE,}, |
b818d1a7 HP |
665 | }, { |
666 | .phy_id = PHY_ID_KSZ8031, | |
667 | .phy_id_mask = 0x00ffffff, | |
668 | .name = "Micrel KSZ8031", | |
669 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause | | |
670 | SUPPORTED_Asym_Pause), | |
671 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 | 672 | .driver_data = &ksz8021_type, |
63f44b2b | 673 | .probe = kszphy_probe, |
d0e1df9c | 674 | .config_init = kszphy_config_init, |
b818d1a7 HP |
675 | .config_aneg = genphy_config_aneg, |
676 | .read_status = genphy_read_status, | |
677 | .ack_interrupt = kszphy_ack_interrupt, | |
678 | .config_intr = kszphy_config_intr, | |
1a5465f5 PV |
679 | .suspend = genphy_suspend, |
680 | .resume = genphy_resume, | |
b818d1a7 | 681 | .driver = { .owner = THIS_MODULE,}, |
d5bf9071 | 682 | }, { |
510d573f | 683 | .phy_id = PHY_ID_KSZ8041, |
51f932c4 | 684 | .phy_id_mask = 0x00fffff0, |
510d573f | 685 | .name = "Micrel KSZ8041", |
51f932c4 CD |
686 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
687 | | SUPPORTED_Asym_Pause), | |
688 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 JH |
689 | .driver_data = &ksz8041_type, |
690 | .probe = kszphy_probe, | |
691 | .config_init = kszphy_config_init, | |
51f932c4 CD |
692 | .config_aneg = genphy_config_aneg, |
693 | .read_status = genphy_read_status, | |
694 | .ack_interrupt = kszphy_ack_interrupt, | |
695 | .config_intr = kszphy_config_intr, | |
1a5465f5 PV |
696 | .suspend = genphy_suspend, |
697 | .resume = genphy_resume, | |
51f932c4 | 698 | .driver = { .owner = THIS_MODULE,}, |
4bd7b512 SS |
699 | }, { |
700 | .phy_id = PHY_ID_KSZ8041RNLI, | |
701 | .phy_id_mask = 0x00fffff0, | |
702 | .name = "Micrel KSZ8041RNLI", | |
703 | .features = PHY_BASIC_FEATURES | | |
704 | SUPPORTED_Pause | SUPPORTED_Asym_Pause, | |
705 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 JH |
706 | .driver_data = &ksz8041_type, |
707 | .probe = kszphy_probe, | |
708 | .config_init = kszphy_config_init, | |
4bd7b512 SS |
709 | .config_aneg = genphy_config_aneg, |
710 | .read_status = genphy_read_status, | |
711 | .ack_interrupt = kszphy_ack_interrupt, | |
712 | .config_intr = kszphy_config_intr, | |
713 | .suspend = genphy_suspend, | |
714 | .resume = genphy_resume, | |
715 | .driver = { .owner = THIS_MODULE,}, | |
d5bf9071 | 716 | }, { |
510d573f | 717 | .phy_id = PHY_ID_KSZ8051, |
d0507009 | 718 | .phy_id_mask = 0x00fffff0, |
510d573f | 719 | .name = "Micrel KSZ8051", |
51f932c4 CD |
720 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
721 | | SUPPORTED_Asym_Pause), | |
722 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 JH |
723 | .driver_data = &ksz8051_type, |
724 | .probe = kszphy_probe, | |
63f44b2b | 725 | .config_init = kszphy_config_init, |
d0507009 DC |
726 | .config_aneg = genphy_config_aneg, |
727 | .read_status = genphy_read_status, | |
51f932c4 CD |
728 | .ack_interrupt = kszphy_ack_interrupt, |
729 | .config_intr = kszphy_config_intr, | |
1a5465f5 PV |
730 | .suspend = genphy_suspend, |
731 | .resume = genphy_resume, | |
d0507009 | 732 | .driver = { .owner = THIS_MODULE,}, |
d5bf9071 | 733 | }, { |
510d573f MV |
734 | .phy_id = PHY_ID_KSZ8001, |
735 | .name = "Micrel KSZ8001 or KS8721", | |
48d7d0ad | 736 | .phy_id_mask = 0x00ffffff, |
51f932c4 CD |
737 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), |
738 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 JH |
739 | .driver_data = &ksz8041_type, |
740 | .probe = kszphy_probe, | |
741 | .config_init = kszphy_config_init, | |
d0507009 DC |
742 | .config_aneg = genphy_config_aneg, |
743 | .read_status = genphy_read_status, | |
51f932c4 CD |
744 | .ack_interrupt = kszphy_ack_interrupt, |
745 | .config_intr = kszphy_config_intr, | |
1a5465f5 PV |
746 | .suspend = genphy_suspend, |
747 | .resume = genphy_resume, | |
d0507009 | 748 | .driver = { .owner = THIS_MODULE,}, |
7ab59dc1 DC |
749 | }, { |
750 | .phy_id = PHY_ID_KSZ8081, | |
751 | .name = "Micrel KSZ8081 or KSZ8091", | |
752 | .phy_id_mask = 0x00fffff0, | |
753 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), | |
754 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
e6a423a8 JH |
755 | .driver_data = &ksz8081_type, |
756 | .probe = kszphy_probe, | |
0f95903e | 757 | .config_init = kszphy_config_init, |
7ab59dc1 DC |
758 | .config_aneg = genphy_config_aneg, |
759 | .read_status = genphy_read_status, | |
760 | .ack_interrupt = kszphy_ack_interrupt, | |
761 | .config_intr = kszphy_config_intr, | |
1a5465f5 PV |
762 | .suspend = genphy_suspend, |
763 | .resume = genphy_resume, | |
7ab59dc1 DC |
764 | .driver = { .owner = THIS_MODULE,}, |
765 | }, { | |
766 | .phy_id = PHY_ID_KSZ8061, | |
767 | .name = "Micrel KSZ8061", | |
768 | .phy_id_mask = 0x00fffff0, | |
769 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), | |
770 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
771 | .config_init = kszphy_config_init, | |
772 | .config_aneg = genphy_config_aneg, | |
773 | .read_status = genphy_read_status, | |
774 | .ack_interrupt = kszphy_ack_interrupt, | |
775 | .config_intr = kszphy_config_intr, | |
1a5465f5 PV |
776 | .suspend = genphy_suspend, |
777 | .resume = genphy_resume, | |
7ab59dc1 | 778 | .driver = { .owner = THIS_MODULE,}, |
d5bf9071 | 779 | }, { |
d0507009 | 780 | .phy_id = PHY_ID_KSZ9021, |
48d7d0ad | 781 | .phy_id_mask = 0x000ffffe, |
d0507009 | 782 | .name = "Micrel KSZ9021 Gigabit PHY", |
32fcafbc | 783 | .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), |
51f932c4 | 784 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
c6f9575c | 785 | .driver_data = &ksz9021_type, |
954c3967 | 786 | .config_init = ksz9021_config_init, |
d0507009 DC |
787 | .config_aneg = genphy_config_aneg, |
788 | .read_status = genphy_read_status, | |
51f932c4 | 789 | .ack_interrupt = kszphy_ack_interrupt, |
c6f9575c | 790 | .config_intr = kszphy_config_intr, |
1a5465f5 PV |
791 | .suspend = genphy_suspend, |
792 | .resume = genphy_resume, | |
19936942 VB |
793 | .read_mmd_indirect = ksz9021_rd_mmd_phyreg, |
794 | .write_mmd_indirect = ksz9021_wr_mmd_phyreg, | |
d0507009 | 795 | .driver = { .owner = THIS_MODULE, }, |
7ab59dc1 DC |
796 | }, { |
797 | .phy_id = PHY_ID_KSZ9031, | |
798 | .phy_id_mask = 0x00fffff0, | |
799 | .name = "Micrel KSZ9031 Gigabit PHY", | |
95e8b103 | 800 | .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause), |
7ab59dc1 | 801 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
c6f9575c | 802 | .driver_data = &ksz9021_type, |
6e4b8273 | 803 | .config_init = ksz9031_config_init, |
7ab59dc1 | 804 | .config_aneg = genphy_config_aneg, |
d2fd719b | 805 | .read_status = ksz9031_read_status, |
7ab59dc1 | 806 | .ack_interrupt = kszphy_ack_interrupt, |
c6f9575c | 807 | .config_intr = kszphy_config_intr, |
1a5465f5 PV |
808 | .suspend = genphy_suspend, |
809 | .resume = genphy_resume, | |
7ab59dc1 | 810 | .driver = { .owner = THIS_MODULE, }, |
93272e07 JCPV |
811 | }, { |
812 | .phy_id = PHY_ID_KSZ8873MLL, | |
813 | .phy_id_mask = 0x00fffff0, | |
814 | .name = "Micrel KSZ8873MLL Switch", | |
815 | .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause), | |
816 | .flags = PHY_HAS_MAGICANEG, | |
817 | .config_init = kszphy_config_init, | |
818 | .config_aneg = ksz8873mll_config_aneg, | |
819 | .read_status = ksz8873mll_read_status, | |
1a5465f5 PV |
820 | .suspend = genphy_suspend, |
821 | .resume = genphy_resume, | |
93272e07 | 822 | .driver = { .owner = THIS_MODULE, }, |
7ab59dc1 DC |
823 | }, { |
824 | .phy_id = PHY_ID_KSZ886X, | |
825 | .phy_id_mask = 0x00fffff0, | |
826 | .name = "Micrel KSZ886X Switch", | |
827 | .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), | |
828 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, | |
829 | .config_init = kszphy_config_init, | |
830 | .config_aneg = genphy_config_aneg, | |
831 | .read_status = genphy_read_status, | |
1a5465f5 PV |
832 | .suspend = genphy_suspend, |
833 | .resume = genphy_resume, | |
7ab59dc1 | 834 | .driver = { .owner = THIS_MODULE, }, |
d5bf9071 | 835 | } }; |
d0507009 | 836 | |
50fd7150 | 837 | module_phy_driver(ksphy_driver); |
d0507009 DC |
838 | |
839 | MODULE_DESCRIPTION("Micrel PHY driver"); | |
840 | MODULE_AUTHOR("David J. Choi"); | |
841 | MODULE_LICENSE("GPL"); | |
52a60ed2 | 842 | |
cf93c945 | 843 | static struct mdio_device_id __maybe_unused micrel_tbl[] = { |
48d7d0ad | 844 | { PHY_ID_KSZ9021, 0x000ffffe }, |
7ab59dc1 | 845 | { PHY_ID_KSZ9031, 0x00fffff0 }, |
510d573f | 846 | { PHY_ID_KSZ8001, 0x00ffffff }, |
51f932c4 | 847 | { PHY_ID_KS8737, 0x00fffff0 }, |
212ea99a | 848 | { PHY_ID_KSZ8021, 0x00ffffff }, |
b818d1a7 | 849 | { PHY_ID_KSZ8031, 0x00ffffff }, |
510d573f MV |
850 | { PHY_ID_KSZ8041, 0x00fffff0 }, |
851 | { PHY_ID_KSZ8051, 0x00fffff0 }, | |
7ab59dc1 DC |
852 | { PHY_ID_KSZ8061, 0x00fffff0 }, |
853 | { PHY_ID_KSZ8081, 0x00fffff0 }, | |
93272e07 | 854 | { PHY_ID_KSZ8873MLL, 0x00fffff0 }, |
7ab59dc1 | 855 | { PHY_ID_KSZ886X, 0x00fffff0 }, |
52a60ed2 DM |
856 | { } |
857 | }; | |
858 | ||
859 | MODULE_DEVICE_TABLE(mdio, micrel_tbl); |