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d0507009 DC |
1 | /* |
2 | * drivers/net/phy/micrel.c | |
3 | * | |
4 | * Driver for Micrel PHYs | |
5 | * | |
6 | * Author: David J. Choi | |
7 | * | |
7ab59dc1 | 8 | * Copyright (c) 2010-2013 Micrel, Inc. |
ee0dc2fb | 9 | * Copyright (c) 2014 Johan Hovold <johan@kernel.org> |
d0507009 DC |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify it | |
12 | * under the terms of the GNU General Public License as published by the | |
13 | * Free Software Foundation; either version 2 of the License, or (at your | |
14 | * option) any later version. | |
15 | * | |
7ab59dc1 DC |
16 | * Support : Micrel Phys: |
17 | * Giga phys: ksz9021, ksz9031 | |
18 | * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041 | |
19 | * ksz8021, ksz8031, ksz8051, | |
20 | * ksz8081, ksz8091, | |
21 | * ksz8061, | |
22 | * Switch : ksz8873, ksz886x | |
d0507009 DC |
23 | */ |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/phy.h> | |
d606ef3f | 28 | #include <linux/micrel_phy.h> |
954c3967 | 29 | #include <linux/of.h> |
1fadee0c | 30 | #include <linux/clk.h> |
d0507009 | 31 | |
212ea99a MV |
32 | /* Operation Mode Strap Override */ |
33 | #define MII_KSZPHY_OMSO 0x16 | |
00aee095 | 34 | #define KSZPHY_OMSO_B_CAST_OFF BIT(9) |
2b0ba96c | 35 | #define KSZPHY_OMSO_NAND_TREE_ON BIT(5) |
00aee095 JH |
36 | #define KSZPHY_OMSO_RMII_OVERRIDE BIT(1) |
37 | #define KSZPHY_OMSO_MII_OVERRIDE BIT(0) | |
212ea99a | 38 | |
51f932c4 CD |
39 | /* general Interrupt control/status reg in vendor specific block. */ |
40 | #define MII_KSZPHY_INTCS 0x1B | |
00aee095 JH |
41 | #define KSZPHY_INTCS_JABBER BIT(15) |
42 | #define KSZPHY_INTCS_RECEIVE_ERR BIT(14) | |
43 | #define KSZPHY_INTCS_PAGE_RECEIVE BIT(13) | |
44 | #define KSZPHY_INTCS_PARELLEL BIT(12) | |
45 | #define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11) | |
46 | #define KSZPHY_INTCS_LINK_DOWN BIT(10) | |
47 | #define KSZPHY_INTCS_REMOTE_FAULT BIT(9) | |
48 | #define KSZPHY_INTCS_LINK_UP BIT(8) | |
51f932c4 CD |
49 | #define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\ |
50 | KSZPHY_INTCS_LINK_DOWN) | |
51 | ||
5a16778e JH |
52 | /* PHY Control 1 */ |
53 | #define MII_KSZPHY_CTRL_1 0x1e | |
54 | ||
55 | /* PHY Control 2 / PHY Control (if no PHY Control 1) */ | |
56 | #define MII_KSZPHY_CTRL_2 0x1f | |
57 | #define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2 | |
51f932c4 | 58 | /* bitmap of PHY register to set interrupt mode */ |
00aee095 | 59 | #define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9) |
63f44b2b | 60 | #define KSZPHY_RMII_REF_CLK_SEL BIT(7) |
51f932c4 | 61 | |
954c3967 SC |
62 | /* Write/read to/from extended registers */ |
63 | #define MII_KSZPHY_EXTREG 0x0b | |
64 | #define KSZPHY_EXTREG_WRITE 0x8000 | |
65 | ||
66 | #define MII_KSZPHY_EXTREG_WRITE 0x0c | |
67 | #define MII_KSZPHY_EXTREG_READ 0x0d | |
68 | ||
69 | /* Extended registers */ | |
70 | #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104 | |
71 | #define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105 | |
72 | #define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106 | |
73 | ||
74 | #define PS_TO_REG 200 | |
75 | ||
2b2427d0 AL |
76 | struct kszphy_hw_stat { |
77 | const char *string; | |
78 | u8 reg; | |
79 | u8 bits; | |
80 | }; | |
81 | ||
82 | static struct kszphy_hw_stat kszphy_hw_stats[] = { | |
83 | { "phy_receive_errors", 21, 16}, | |
84 | { "phy_idle_errors", 10, 8 }, | |
85 | }; | |
86 | ||
e6a423a8 JH |
87 | struct kszphy_type { |
88 | u32 led_mode_reg; | |
c6f9575c | 89 | u16 interrupt_level_mask; |
0f95903e | 90 | bool has_broadcast_disable; |
2b0ba96c | 91 | bool has_nand_tree_disable; |
63f44b2b | 92 | bool has_rmii_ref_clk_sel; |
e6a423a8 JH |
93 | }; |
94 | ||
95 | struct kszphy_priv { | |
96 | const struct kszphy_type *type; | |
e7a792e9 | 97 | int led_mode; |
63f44b2b JH |
98 | bool rmii_ref_clk_sel; |
99 | bool rmii_ref_clk_sel_val; | |
2b2427d0 | 100 | u64 stats[ARRAY_SIZE(kszphy_hw_stats)]; |
e6a423a8 JH |
101 | }; |
102 | ||
103 | static const struct kszphy_type ksz8021_type = { | |
104 | .led_mode_reg = MII_KSZPHY_CTRL_2, | |
d0e1df9c | 105 | .has_broadcast_disable = true, |
2b0ba96c | 106 | .has_nand_tree_disable = true, |
63f44b2b | 107 | .has_rmii_ref_clk_sel = true, |
e6a423a8 JH |
108 | }; |
109 | ||
110 | static const struct kszphy_type ksz8041_type = { | |
111 | .led_mode_reg = MII_KSZPHY_CTRL_1, | |
112 | }; | |
113 | ||
114 | static const struct kszphy_type ksz8051_type = { | |
115 | .led_mode_reg = MII_KSZPHY_CTRL_2, | |
2b0ba96c | 116 | .has_nand_tree_disable = true, |
e6a423a8 JH |
117 | }; |
118 | ||
119 | static const struct kszphy_type ksz8081_type = { | |
120 | .led_mode_reg = MII_KSZPHY_CTRL_2, | |
0f95903e | 121 | .has_broadcast_disable = true, |
2b0ba96c | 122 | .has_nand_tree_disable = true, |
86dc1342 | 123 | .has_rmii_ref_clk_sel = true, |
e6a423a8 JH |
124 | }; |
125 | ||
c6f9575c JH |
126 | static const struct kszphy_type ks8737_type = { |
127 | .interrupt_level_mask = BIT(14), | |
128 | }; | |
129 | ||
130 | static const struct kszphy_type ksz9021_type = { | |
131 | .interrupt_level_mask = BIT(14), | |
132 | }; | |
133 | ||
954c3967 | 134 | static int kszphy_extended_write(struct phy_device *phydev, |
756b5089 | 135 | u32 regnum, u16 val) |
954c3967 SC |
136 | { |
137 | phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum); | |
138 | return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val); | |
139 | } | |
140 | ||
141 | static int kszphy_extended_read(struct phy_device *phydev, | |
756b5089 | 142 | u32 regnum) |
954c3967 SC |
143 | { |
144 | phy_write(phydev, MII_KSZPHY_EXTREG, regnum); | |
145 | return phy_read(phydev, MII_KSZPHY_EXTREG_READ); | |
146 | } | |
147 | ||
51f932c4 CD |
148 | static int kszphy_ack_interrupt(struct phy_device *phydev) |
149 | { | |
150 | /* bit[7..0] int status, which is a read and clear register. */ | |
151 | int rc; | |
152 | ||
153 | rc = phy_read(phydev, MII_KSZPHY_INTCS); | |
154 | ||
155 | return (rc < 0) ? rc : 0; | |
156 | } | |
157 | ||
51f932c4 CD |
158 | static int kszphy_config_intr(struct phy_device *phydev) |
159 | { | |
c6f9575c JH |
160 | const struct kszphy_type *type = phydev->drv->driver_data; |
161 | int temp; | |
162 | u16 mask; | |
51f932c4 | 163 | |
c6f9575c JH |
164 | if (type && type->interrupt_level_mask) |
165 | mask = type->interrupt_level_mask; | |
166 | else | |
167 | mask = KSZPHY_CTRL_INT_ACTIVE_HIGH; | |
51f932c4 CD |
168 | |
169 | /* set the interrupt pin active low */ | |
170 | temp = phy_read(phydev, MII_KSZPHY_CTRL); | |
5bb8fc0d JH |
171 | if (temp < 0) |
172 | return temp; | |
c6f9575c | 173 | temp &= ~mask; |
51f932c4 | 174 | phy_write(phydev, MII_KSZPHY_CTRL, temp); |
51f932c4 | 175 | |
c6f9575c JH |
176 | /* enable / disable interrupts */ |
177 | if (phydev->interrupts == PHY_INTERRUPT_ENABLED) | |
178 | temp = KSZPHY_INTCS_ALL; | |
179 | else | |
180 | temp = 0; | |
51f932c4 | 181 | |
c6f9575c | 182 | return phy_write(phydev, MII_KSZPHY_INTCS, temp); |
51f932c4 | 183 | } |
d0507009 | 184 | |
63f44b2b JH |
185 | static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val) |
186 | { | |
187 | int ctrl; | |
188 | ||
189 | ctrl = phy_read(phydev, MII_KSZPHY_CTRL); | |
190 | if (ctrl < 0) | |
191 | return ctrl; | |
192 | ||
193 | if (val) | |
194 | ctrl |= KSZPHY_RMII_REF_CLK_SEL; | |
195 | else | |
196 | ctrl &= ~KSZPHY_RMII_REF_CLK_SEL; | |
197 | ||
198 | return phy_write(phydev, MII_KSZPHY_CTRL, ctrl); | |
199 | } | |
200 | ||
e7a792e9 | 201 | static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val) |
20d8435a | 202 | { |
5a16778e | 203 | int rc, temp, shift; |
8620546c | 204 | |
5a16778e JH |
205 | switch (reg) { |
206 | case MII_KSZPHY_CTRL_1: | |
207 | shift = 14; | |
208 | break; | |
209 | case MII_KSZPHY_CTRL_2: | |
210 | shift = 4; | |
211 | break; | |
212 | default: | |
213 | return -EINVAL; | |
214 | } | |
215 | ||
20d8435a | 216 | temp = phy_read(phydev, reg); |
b7035860 JH |
217 | if (temp < 0) { |
218 | rc = temp; | |
219 | goto out; | |
220 | } | |
20d8435a | 221 | |
28bdc499 | 222 | temp &= ~(3 << shift); |
20d8435a BD |
223 | temp |= val << shift; |
224 | rc = phy_write(phydev, reg, temp); | |
b7035860 JH |
225 | out: |
226 | if (rc < 0) | |
72ba48be | 227 | phydev_err(phydev, "failed to set led mode\n"); |
20d8435a | 228 | |
b7035860 | 229 | return rc; |
20d8435a BD |
230 | } |
231 | ||
bde15129 JH |
232 | /* Disable PHY address 0 as the broadcast address, so that it can be used as a |
233 | * unique (non-broadcast) address on a shared bus. | |
234 | */ | |
235 | static int kszphy_broadcast_disable(struct phy_device *phydev) | |
236 | { | |
237 | int ret; | |
238 | ||
239 | ret = phy_read(phydev, MII_KSZPHY_OMSO); | |
240 | if (ret < 0) | |
241 | goto out; | |
242 | ||
243 | ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF); | |
244 | out: | |
245 | if (ret) | |
72ba48be | 246 | phydev_err(phydev, "failed to disable broadcast address\n"); |
bde15129 JH |
247 | |
248 | return ret; | |
249 | } | |
250 | ||
2b0ba96c SR |
251 | static int kszphy_nand_tree_disable(struct phy_device *phydev) |
252 | { | |
253 | int ret; | |
254 | ||
255 | ret = phy_read(phydev, MII_KSZPHY_OMSO); | |
256 | if (ret < 0) | |
257 | goto out; | |
258 | ||
259 | if (!(ret & KSZPHY_OMSO_NAND_TREE_ON)) | |
260 | return 0; | |
261 | ||
262 | ret = phy_write(phydev, MII_KSZPHY_OMSO, | |
263 | ret & ~KSZPHY_OMSO_NAND_TREE_ON); | |
264 | out: | |
265 | if (ret) | |
72ba48be | 266 | phydev_err(phydev, "failed to disable NAND tree mode\n"); |
2b0ba96c SR |
267 | |
268 | return ret; | |
269 | } | |
270 | ||
d0507009 DC |
271 | static int kszphy_config_init(struct phy_device *phydev) |
272 | { | |
e6a423a8 JH |
273 | struct kszphy_priv *priv = phydev->priv; |
274 | const struct kszphy_type *type; | |
63f44b2b | 275 | int ret; |
d0507009 | 276 | |
e6a423a8 JH |
277 | if (!priv) |
278 | return 0; | |
279 | ||
280 | type = priv->type; | |
281 | ||
0f95903e JH |
282 | if (type->has_broadcast_disable) |
283 | kszphy_broadcast_disable(phydev); | |
284 | ||
2b0ba96c SR |
285 | if (type->has_nand_tree_disable) |
286 | kszphy_nand_tree_disable(phydev); | |
287 | ||
63f44b2b JH |
288 | if (priv->rmii_ref_clk_sel) { |
289 | ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val); | |
290 | if (ret) { | |
72ba48be AL |
291 | phydev_err(phydev, |
292 | "failed to set rmii reference clock\n"); | |
63f44b2b JH |
293 | return ret; |
294 | } | |
295 | } | |
296 | ||
e7a792e9 JH |
297 | if (priv->led_mode >= 0) |
298 | kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode); | |
e6a423a8 | 299 | |
99f81afc AB |
300 | if (phy_interrupt_is_valid(phydev)) { |
301 | int ctl = phy_read(phydev, MII_BMCR); | |
302 | ||
303 | if (ctl < 0) | |
304 | return ctl; | |
305 | ||
306 | ret = phy_write(phydev, MII_BMCR, ctl & ~BMCR_ANENABLE); | |
307 | if (ret < 0) | |
308 | return ret; | |
309 | } | |
310 | ||
e6a423a8 | 311 | return 0; |
20d8435a BD |
312 | } |
313 | ||
77501a79 PZ |
314 | static int ksz8041_config_init(struct phy_device *phydev) |
315 | { | |
316 | struct device_node *of_node = phydev->mdio.dev.of_node; | |
317 | ||
318 | /* Limit supported and advertised modes in fiber mode */ | |
319 | if (of_property_read_bool(of_node, "micrel,fiber-mode")) { | |
320 | phydev->dev_flags |= MICREL_PHY_FXEN; | |
ffa54a23 | 321 | phydev->supported &= SUPPORTED_100baseT_Full | |
77501a79 | 322 | SUPPORTED_100baseT_Half; |
ffa54a23 KE |
323 | phydev->supported |= SUPPORTED_FIBRE; |
324 | phydev->advertising &= ADVERTISED_100baseT_Full | | |
77501a79 | 325 | ADVERTISED_100baseT_Half; |
ffa54a23 | 326 | phydev->advertising |= ADVERTISED_FIBRE; |
77501a79 PZ |
327 | phydev->autoneg = AUTONEG_DISABLE; |
328 | } | |
329 | ||
330 | return kszphy_config_init(phydev); | |
331 | } | |
332 | ||
333 | static int ksz8041_config_aneg(struct phy_device *phydev) | |
334 | { | |
335 | /* Skip auto-negotiation in fiber mode */ | |
336 | if (phydev->dev_flags & MICREL_PHY_FXEN) { | |
337 | phydev->speed = SPEED_100; | |
338 | return 0; | |
339 | } | |
340 | ||
341 | return genphy_config_aneg(phydev); | |
342 | } | |
343 | ||
954c3967 | 344 | static int ksz9021_load_values_from_of(struct phy_device *phydev, |
3c9a9f7f JA |
345 | const struct device_node *of_node, |
346 | u16 reg, | |
347 | const char *field1, const char *field2, | |
348 | const char *field3, const char *field4) | |
954c3967 SC |
349 | { |
350 | int val1 = -1; | |
351 | int val2 = -2; | |
352 | int val3 = -3; | |
353 | int val4 = -4; | |
354 | int newval; | |
355 | int matches = 0; | |
356 | ||
357 | if (!of_property_read_u32(of_node, field1, &val1)) | |
358 | matches++; | |
359 | ||
360 | if (!of_property_read_u32(of_node, field2, &val2)) | |
361 | matches++; | |
362 | ||
363 | if (!of_property_read_u32(of_node, field3, &val3)) | |
364 | matches++; | |
365 | ||
366 | if (!of_property_read_u32(of_node, field4, &val4)) | |
367 | matches++; | |
368 | ||
369 | if (!matches) | |
370 | return 0; | |
371 | ||
372 | if (matches < 4) | |
373 | newval = kszphy_extended_read(phydev, reg); | |
374 | else | |
375 | newval = 0; | |
376 | ||
377 | if (val1 != -1) | |
378 | newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0); | |
379 | ||
6a119745 | 380 | if (val2 != -2) |
954c3967 SC |
381 | newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4); |
382 | ||
6a119745 | 383 | if (val3 != -3) |
954c3967 SC |
384 | newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8); |
385 | ||
6a119745 | 386 | if (val4 != -4) |
954c3967 SC |
387 | newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12); |
388 | ||
389 | return kszphy_extended_write(phydev, reg, newval); | |
390 | } | |
391 | ||
392 | static int ksz9021_config_init(struct phy_device *phydev) | |
393 | { | |
e5a03bfd | 394 | const struct device *dev = &phydev->mdio.dev; |
3c9a9f7f | 395 | const struct device_node *of_node = dev->of_node; |
651df218 AL |
396 | const struct device *dev_walker; |
397 | ||
398 | /* The Micrel driver has a deprecated option to place phy OF | |
399 | * properties in the MAC node. Walk up the tree of devices to | |
400 | * find a device with an OF node. | |
401 | */ | |
e5a03bfd | 402 | dev_walker = &phydev->mdio.dev; |
651df218 AL |
403 | do { |
404 | of_node = dev_walker->of_node; | |
405 | dev_walker = dev_walker->parent; | |
406 | ||
407 | } while (!of_node && dev_walker); | |
954c3967 SC |
408 | |
409 | if (of_node) { | |
410 | ksz9021_load_values_from_of(phydev, of_node, | |
411 | MII_KSZPHY_CLK_CONTROL_PAD_SKEW, | |
412 | "txen-skew-ps", "txc-skew-ps", | |
413 | "rxdv-skew-ps", "rxc-skew-ps"); | |
414 | ksz9021_load_values_from_of(phydev, of_node, | |
415 | MII_KSZPHY_RX_DATA_PAD_SKEW, | |
416 | "rxd0-skew-ps", "rxd1-skew-ps", | |
417 | "rxd2-skew-ps", "rxd3-skew-ps"); | |
418 | ksz9021_load_values_from_of(phydev, of_node, | |
419 | MII_KSZPHY_TX_DATA_PAD_SKEW, | |
420 | "txd0-skew-ps", "txd1-skew-ps", | |
421 | "txd2-skew-ps", "txd3-skew-ps"); | |
422 | } | |
423 | return 0; | |
424 | } | |
425 | ||
6e4b8273 HC |
426 | #define MII_KSZ9031RN_MMD_CTRL_REG 0x0d |
427 | #define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e | |
428 | #define OP_DATA 1 | |
429 | #define KSZ9031_PS_TO_REG 60 | |
430 | ||
431 | /* Extended registers */ | |
6270e1ae JA |
432 | /* MMD Address 0x0 */ |
433 | #define MII_KSZ9031RN_FLP_BURST_TX_LO 3 | |
434 | #define MII_KSZ9031RN_FLP_BURST_TX_HI 4 | |
435 | ||
ae6c97bb | 436 | /* MMD Address 0x2 */ |
6e4b8273 HC |
437 | #define MII_KSZ9031RN_CONTROL_PAD_SKEW 4 |
438 | #define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5 | |
439 | #define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6 | |
440 | #define MII_KSZ9031RN_CLK_PAD_SKEW 8 | |
441 | ||
af70c1f9 ML |
442 | /* MMD Address 0x1C */ |
443 | #define MII_KSZ9031RN_EDPD 0x23 | |
444 | #define MII_KSZ9031RN_EDPD_ENABLE BIT(0) | |
445 | ||
6e4b8273 HC |
446 | static int ksz9031_extended_write(struct phy_device *phydev, |
447 | u8 mode, u32 dev_addr, u32 regnum, u16 val) | |
448 | { | |
449 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); | |
450 | phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); | |
451 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); | |
452 | return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val); | |
453 | } | |
454 | ||
455 | static int ksz9031_extended_read(struct phy_device *phydev, | |
456 | u8 mode, u32 dev_addr, u32 regnum) | |
457 | { | |
458 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr); | |
459 | phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum); | |
460 | phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr); | |
461 | return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG); | |
462 | } | |
463 | ||
464 | static int ksz9031_of_load_skew_values(struct phy_device *phydev, | |
3c9a9f7f | 465 | const struct device_node *of_node, |
6e4b8273 | 466 | u16 reg, size_t field_sz, |
3c9a9f7f | 467 | const char *field[], u8 numfields) |
6e4b8273 HC |
468 | { |
469 | int val[4] = {-1, -2, -3, -4}; | |
470 | int matches = 0; | |
471 | u16 mask; | |
472 | u16 maxval; | |
473 | u16 newval; | |
474 | int i; | |
475 | ||
476 | for (i = 0; i < numfields; i++) | |
477 | if (!of_property_read_u32(of_node, field[i], val + i)) | |
478 | matches++; | |
479 | ||
480 | if (!matches) | |
481 | return 0; | |
482 | ||
483 | if (matches < numfields) | |
484 | newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg); | |
485 | else | |
486 | newval = 0; | |
487 | ||
488 | maxval = (field_sz == 4) ? 0xf : 0x1f; | |
489 | for (i = 0; i < numfields; i++) | |
490 | if (val[i] != -(i + 1)) { | |
491 | mask = 0xffff; | |
492 | mask ^= maxval << (field_sz * i); | |
493 | newval = (newval & mask) | | |
494 | (((val[i] / KSZ9031_PS_TO_REG) & maxval) | |
495 | << (field_sz * i)); | |
496 | } | |
497 | ||
498 | return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval); | |
499 | } | |
500 | ||
6270e1ae JA |
501 | static int ksz9031_center_flp_timing(struct phy_device *phydev) |
502 | { | |
503 | int result; | |
504 | ||
505 | /* Center KSZ9031RNX FLP timing at 16ms. */ | |
506 | result = ksz9031_extended_write(phydev, OP_DATA, 0, | |
507 | MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006); | |
508 | result = ksz9031_extended_write(phydev, OP_DATA, 0, | |
509 | MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80); | |
510 | ||
511 | if (result) | |
512 | return result; | |
513 | ||
514 | return genphy_restart_aneg(phydev); | |
515 | } | |
516 | ||
af70c1f9 ML |
517 | /* Enable energy-detect power-down mode */ |
518 | static int ksz9031_enable_edpd(struct phy_device *phydev) | |
519 | { | |
520 | int reg; | |
521 | ||
522 | reg = ksz9031_extended_read(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD); | |
523 | if (reg < 0) | |
524 | return reg; | |
525 | return ksz9031_extended_write(phydev, OP_DATA, 0x1C, MII_KSZ9031RN_EDPD, | |
526 | reg | MII_KSZ9031RN_EDPD_ENABLE); | |
527 | } | |
528 | ||
6e4b8273 HC |
529 | static int ksz9031_config_init(struct phy_device *phydev) |
530 | { | |
e5a03bfd | 531 | const struct device *dev = &phydev->mdio.dev; |
3c9a9f7f JA |
532 | const struct device_node *of_node = dev->of_node; |
533 | static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"}; | |
534 | static const char *rx_data_skews[4] = { | |
6e4b8273 HC |
535 | "rxd0-skew-ps", "rxd1-skew-ps", |
536 | "rxd2-skew-ps", "rxd3-skew-ps" | |
537 | }; | |
3c9a9f7f | 538 | static const char *tx_data_skews[4] = { |
6e4b8273 HC |
539 | "txd0-skew-ps", "txd1-skew-ps", |
540 | "txd2-skew-ps", "txd3-skew-ps" | |
541 | }; | |
3c9a9f7f | 542 | static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"}; |
b4c19f71 | 543 | const struct device *dev_walker; |
af70c1f9 ML |
544 | int result; |
545 | ||
546 | result = ksz9031_enable_edpd(phydev); | |
547 | if (result < 0) | |
548 | return result; | |
6e4b8273 | 549 | |
b4c19f71 RH |
550 | /* The Micrel driver has a deprecated option to place phy OF |
551 | * properties in the MAC node. Walk up the tree of devices to | |
552 | * find a device with an OF node. | |
553 | */ | |
9d367edd | 554 | dev_walker = &phydev->mdio.dev; |
b4c19f71 RH |
555 | do { |
556 | of_node = dev_walker->of_node; | |
557 | dev_walker = dev_walker->parent; | |
558 | } while (!of_node && dev_walker); | |
6e4b8273 HC |
559 | |
560 | if (of_node) { | |
561 | ksz9031_of_load_skew_values(phydev, of_node, | |
562 | MII_KSZ9031RN_CLK_PAD_SKEW, 5, | |
563 | clk_skews, 2); | |
564 | ||
565 | ksz9031_of_load_skew_values(phydev, of_node, | |
566 | MII_KSZ9031RN_CONTROL_PAD_SKEW, 4, | |
567 | control_skews, 2); | |
568 | ||
569 | ksz9031_of_load_skew_values(phydev, of_node, | |
570 | MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4, | |
571 | rx_data_skews, 4); | |
572 | ||
573 | ksz9031_of_load_skew_values(phydev, of_node, | |
574 | MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4, | |
575 | tx_data_skews, 4); | |
576 | } | |
6270e1ae JA |
577 | |
578 | return ksz9031_center_flp_timing(phydev); | |
6e4b8273 HC |
579 | } |
580 | ||
93272e07 | 581 | #define KSZ8873MLL_GLOBAL_CONTROL_4 0x06 |
00aee095 JH |
582 | #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6) |
583 | #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4) | |
32d73b14 | 584 | static int ksz8873mll_read_status(struct phy_device *phydev) |
93272e07 JCPV |
585 | { |
586 | int regval; | |
587 | ||
588 | /* dummy read */ | |
589 | regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); | |
590 | ||
591 | regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4); | |
592 | ||
593 | if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX) | |
594 | phydev->duplex = DUPLEX_HALF; | |
595 | else | |
596 | phydev->duplex = DUPLEX_FULL; | |
597 | ||
598 | if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED) | |
599 | phydev->speed = SPEED_10; | |
600 | else | |
601 | phydev->speed = SPEED_100; | |
602 | ||
603 | phydev->link = 1; | |
604 | phydev->pause = phydev->asym_pause = 0; | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
d2fd719b NS |
609 | static int ksz9031_read_status(struct phy_device *phydev) |
610 | { | |
611 | int err; | |
612 | int regval; | |
613 | ||
614 | err = genphy_read_status(phydev); | |
615 | if (err) | |
616 | return err; | |
617 | ||
618 | /* Make sure the PHY is not broken. Read idle error count, | |
619 | * and reset the PHY if it is maxed out. | |
620 | */ | |
621 | regval = phy_read(phydev, MII_STAT1000); | |
622 | if ((regval & 0xFF) == 0xFF) { | |
623 | phy_init_hw(phydev); | |
624 | phydev->link = 0; | |
625 | } | |
626 | ||
627 | return 0; | |
628 | } | |
629 | ||
93272e07 JCPV |
630 | static int ksz8873mll_config_aneg(struct phy_device *phydev) |
631 | { | |
632 | return 0; | |
633 | } | |
634 | ||
19936942 VB |
635 | /* This routine returns -1 as an indication to the caller that the |
636 | * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE | |
637 | * MMD extended PHY registers. | |
638 | */ | |
639 | static int | |
640 | ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum, | |
641 | int regnum) | |
642 | { | |
643 | return -1; | |
644 | } | |
645 | ||
646 | /* This routine does nothing since the Micrel ksz9021 does not support | |
647 | * standard IEEE MMD extended PHY registers. | |
648 | */ | |
649 | static void | |
650 | ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum, | |
651 | int regnum, u32 val) | |
652 | { | |
653 | } | |
654 | ||
2b2427d0 AL |
655 | static int kszphy_get_sset_count(struct phy_device *phydev) |
656 | { | |
657 | return ARRAY_SIZE(kszphy_hw_stats); | |
658 | } | |
659 | ||
660 | static void kszphy_get_strings(struct phy_device *phydev, u8 *data) | |
661 | { | |
662 | int i; | |
663 | ||
664 | for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) { | |
665 | memcpy(data + i * ETH_GSTRING_LEN, | |
666 | kszphy_hw_stats[i].string, ETH_GSTRING_LEN); | |
667 | } | |
668 | } | |
669 | ||
670 | #ifndef UINT64_MAX | |
671 | #define UINT64_MAX (u64)(~((u64)0)) | |
672 | #endif | |
673 | static u64 kszphy_get_stat(struct phy_device *phydev, int i) | |
674 | { | |
675 | struct kszphy_hw_stat stat = kszphy_hw_stats[i]; | |
676 | struct kszphy_priv *priv = phydev->priv; | |
321b4d4b AL |
677 | int val; |
678 | u64 ret; | |
2b2427d0 AL |
679 | |
680 | val = phy_read(phydev, stat.reg); | |
681 | if (val < 0) { | |
321b4d4b | 682 | ret = UINT64_MAX; |
2b2427d0 AL |
683 | } else { |
684 | val = val & ((1 << stat.bits) - 1); | |
685 | priv->stats[i] += val; | |
321b4d4b | 686 | ret = priv->stats[i]; |
2b2427d0 AL |
687 | } |
688 | ||
321b4d4b | 689 | return ret; |
2b2427d0 AL |
690 | } |
691 | ||
692 | static void kszphy_get_stats(struct phy_device *phydev, | |
693 | struct ethtool_stats *stats, u64 *data) | |
694 | { | |
695 | int i; | |
696 | ||
697 | for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) | |
698 | data[i] = kszphy_get_stat(phydev, i); | |
699 | } | |
700 | ||
836384d2 | 701 | static int kszphy_suspend(struct phy_device *phydev) |
f5aba91d | 702 | { |
836384d2 WY |
703 | /* Disable PHY Interrupts */ |
704 | if (phy_interrupt_is_valid(phydev)) { | |
705 | phydev->interrupts = PHY_INTERRUPT_DISABLED; | |
706 | if (phydev->drv->config_intr) | |
707 | phydev->drv->config_intr(phydev); | |
708 | } | |
f5aba91d | 709 | |
836384d2 WY |
710 | return genphy_suspend(phydev); |
711 | } | |
f5aba91d | 712 | |
836384d2 WY |
713 | static int kszphy_resume(struct phy_device *phydev) |
714 | { | |
715 | genphy_resume(phydev); | |
f5aba91d | 716 | |
836384d2 WY |
717 | /* Enable PHY Interrupts */ |
718 | if (phy_interrupt_is_valid(phydev)) { | |
719 | phydev->interrupts = PHY_INTERRUPT_ENABLED; | |
720 | if (phydev->drv->config_intr) | |
721 | phydev->drv->config_intr(phydev); | |
722 | } | |
f5aba91d AB |
723 | |
724 | return 0; | |
725 | } | |
726 | ||
e6a423a8 JH |
727 | static int kszphy_probe(struct phy_device *phydev) |
728 | { | |
729 | const struct kszphy_type *type = phydev->drv->driver_data; | |
e5a03bfd | 730 | const struct device_node *np = phydev->mdio.dev.of_node; |
e6a423a8 | 731 | struct kszphy_priv *priv; |
63f44b2b | 732 | struct clk *clk; |
e7a792e9 | 733 | int ret; |
e6a423a8 | 734 | |
e5a03bfd | 735 | priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); |
e6a423a8 JH |
736 | if (!priv) |
737 | return -ENOMEM; | |
738 | ||
739 | phydev->priv = priv; | |
740 | ||
741 | priv->type = type; | |
742 | ||
e7a792e9 JH |
743 | if (type->led_mode_reg) { |
744 | ret = of_property_read_u32(np, "micrel,led-mode", | |
745 | &priv->led_mode); | |
746 | if (ret) | |
747 | priv->led_mode = -1; | |
748 | ||
749 | if (priv->led_mode > 3) { | |
72ba48be AL |
750 | phydev_err(phydev, "invalid led mode: 0x%02x\n", |
751 | priv->led_mode); | |
e7a792e9 JH |
752 | priv->led_mode = -1; |
753 | } | |
754 | } else { | |
755 | priv->led_mode = -1; | |
756 | } | |
757 | ||
e5a03bfd | 758 | clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref"); |
bced8701 NC |
759 | /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */ |
760 | if (!IS_ERR_OR_NULL(clk)) { | |
1fadee0c | 761 | unsigned long rate = clk_get_rate(clk); |
86dc1342 | 762 | bool rmii_ref_clk_sel_25_mhz; |
1fadee0c | 763 | |
63f44b2b | 764 | priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel; |
86dc1342 JH |
765 | rmii_ref_clk_sel_25_mhz = of_property_read_bool(np, |
766 | "micrel,rmii-reference-clock-select-25-mhz"); | |
63f44b2b | 767 | |
1fadee0c | 768 | if (rate > 24500000 && rate < 25500000) { |
86dc1342 | 769 | priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz; |
1fadee0c | 770 | } else if (rate > 49500000 && rate < 50500000) { |
86dc1342 | 771 | priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz; |
1fadee0c | 772 | } else { |
72ba48be AL |
773 | phydev_err(phydev, "Clock rate out of range: %ld\n", |
774 | rate); | |
1fadee0c SH |
775 | return -EINVAL; |
776 | } | |
777 | } | |
778 | ||
63f44b2b JH |
779 | /* Support legacy board-file configuration */ |
780 | if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) { | |
781 | priv->rmii_ref_clk_sel = true; | |
782 | priv->rmii_ref_clk_sel_val = true; | |
783 | } | |
784 | ||
785 | return 0; | |
1fadee0c SH |
786 | } |
787 | ||
d5bf9071 CH |
788 | static struct phy_driver ksphy_driver[] = { |
789 | { | |
51f932c4 | 790 | .phy_id = PHY_ID_KS8737, |
f893a99e | 791 | .phy_id_mask = MICREL_PHY_ID_MASK, |
51f932c4 | 792 | .name = "Micrel KS8737", |
529ed127 | 793 | .features = PHY_BASIC_FEATURES, |
51f932c4 | 794 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
c6f9575c | 795 | .driver_data = &ks8737_type, |
51f932c4 CD |
796 | .config_init = kszphy_config_init, |
797 | .config_aneg = genphy_config_aneg, | |
798 | .read_status = genphy_read_status, | |
799 | .ack_interrupt = kszphy_ack_interrupt, | |
c6f9575c | 800 | .config_intr = kszphy_config_intr, |
1a5465f5 PV |
801 | .suspend = genphy_suspend, |
802 | .resume = genphy_resume, | |
212ea99a MV |
803 | }, { |
804 | .phy_id = PHY_ID_KSZ8021, | |
805 | .phy_id_mask = 0x00ffffff, | |
7ab59dc1 | 806 | .name = "Micrel KSZ8021 or KSZ8031", |
529ed127 | 807 | .features = PHY_BASIC_FEATURES, |
212ea99a | 808 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
e6a423a8 | 809 | .driver_data = &ksz8021_type, |
63f44b2b | 810 | .probe = kszphy_probe, |
d0e1df9c | 811 | .config_init = kszphy_config_init, |
212ea99a MV |
812 | .config_aneg = genphy_config_aneg, |
813 | .read_status = genphy_read_status, | |
814 | .ack_interrupt = kszphy_ack_interrupt, | |
815 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
816 | .get_sset_count = kszphy_get_sset_count, |
817 | .get_strings = kszphy_get_strings, | |
818 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
819 | .suspend = genphy_suspend, |
820 | .resume = genphy_resume, | |
b818d1a7 HP |
821 | }, { |
822 | .phy_id = PHY_ID_KSZ8031, | |
823 | .phy_id_mask = 0x00ffffff, | |
824 | .name = "Micrel KSZ8031", | |
529ed127 | 825 | .features = PHY_BASIC_FEATURES, |
b818d1a7 | 826 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
e6a423a8 | 827 | .driver_data = &ksz8021_type, |
63f44b2b | 828 | .probe = kszphy_probe, |
d0e1df9c | 829 | .config_init = kszphy_config_init, |
b818d1a7 HP |
830 | .config_aneg = genphy_config_aneg, |
831 | .read_status = genphy_read_status, | |
832 | .ack_interrupt = kszphy_ack_interrupt, | |
833 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
834 | .get_sset_count = kszphy_get_sset_count, |
835 | .get_strings = kszphy_get_strings, | |
836 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
837 | .suspend = genphy_suspend, |
838 | .resume = genphy_resume, | |
d5bf9071 | 839 | }, { |
510d573f | 840 | .phy_id = PHY_ID_KSZ8041, |
f893a99e | 841 | .phy_id_mask = MICREL_PHY_ID_MASK, |
510d573f | 842 | .name = "Micrel KSZ8041", |
529ed127 | 843 | .features = PHY_BASIC_FEATURES, |
51f932c4 | 844 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
e6a423a8 JH |
845 | .driver_data = &ksz8041_type, |
846 | .probe = kszphy_probe, | |
77501a79 PZ |
847 | .config_init = ksz8041_config_init, |
848 | .config_aneg = ksz8041_config_aneg, | |
51f932c4 CD |
849 | .read_status = genphy_read_status, |
850 | .ack_interrupt = kszphy_ack_interrupt, | |
851 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
852 | .get_sset_count = kszphy_get_sset_count, |
853 | .get_strings = kszphy_get_strings, | |
854 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
855 | .suspend = genphy_suspend, |
856 | .resume = genphy_resume, | |
4bd7b512 SS |
857 | }, { |
858 | .phy_id = PHY_ID_KSZ8041RNLI, | |
f893a99e | 859 | .phy_id_mask = MICREL_PHY_ID_MASK, |
4bd7b512 | 860 | .name = "Micrel KSZ8041RNLI", |
529ed127 | 861 | .features = PHY_BASIC_FEATURES, |
4bd7b512 | 862 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
e6a423a8 JH |
863 | .driver_data = &ksz8041_type, |
864 | .probe = kszphy_probe, | |
865 | .config_init = kszphy_config_init, | |
4bd7b512 SS |
866 | .config_aneg = genphy_config_aneg, |
867 | .read_status = genphy_read_status, | |
868 | .ack_interrupt = kszphy_ack_interrupt, | |
869 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
870 | .get_sset_count = kszphy_get_sset_count, |
871 | .get_strings = kszphy_get_strings, | |
872 | .get_stats = kszphy_get_stats, | |
4bd7b512 SS |
873 | .suspend = genphy_suspend, |
874 | .resume = genphy_resume, | |
d5bf9071 | 875 | }, { |
510d573f | 876 | .phy_id = PHY_ID_KSZ8051, |
f893a99e | 877 | .phy_id_mask = MICREL_PHY_ID_MASK, |
510d573f | 878 | .name = "Micrel KSZ8051", |
529ed127 | 879 | .features = PHY_BASIC_FEATURES, |
51f932c4 | 880 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
e6a423a8 JH |
881 | .driver_data = &ksz8051_type, |
882 | .probe = kszphy_probe, | |
63f44b2b | 883 | .config_init = kszphy_config_init, |
d0507009 DC |
884 | .config_aneg = genphy_config_aneg, |
885 | .read_status = genphy_read_status, | |
51f932c4 CD |
886 | .ack_interrupt = kszphy_ack_interrupt, |
887 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
888 | .get_sset_count = kszphy_get_sset_count, |
889 | .get_strings = kszphy_get_strings, | |
890 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
891 | .suspend = genphy_suspend, |
892 | .resume = genphy_resume, | |
d5bf9071 | 893 | }, { |
510d573f MV |
894 | .phy_id = PHY_ID_KSZ8001, |
895 | .name = "Micrel KSZ8001 or KS8721", | |
ecd5a323 | 896 | .phy_id_mask = 0x00fffffc, |
529ed127 | 897 | .features = PHY_BASIC_FEATURES, |
51f932c4 | 898 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
e6a423a8 JH |
899 | .driver_data = &ksz8041_type, |
900 | .probe = kszphy_probe, | |
901 | .config_init = kszphy_config_init, | |
d0507009 DC |
902 | .config_aneg = genphy_config_aneg, |
903 | .read_status = genphy_read_status, | |
51f932c4 CD |
904 | .ack_interrupt = kszphy_ack_interrupt, |
905 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
906 | .get_sset_count = kszphy_get_sset_count, |
907 | .get_strings = kszphy_get_strings, | |
908 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
909 | .suspend = genphy_suspend, |
910 | .resume = genphy_resume, | |
7ab59dc1 DC |
911 | }, { |
912 | .phy_id = PHY_ID_KSZ8081, | |
913 | .name = "Micrel KSZ8081 or KSZ8091", | |
f893a99e | 914 | .phy_id_mask = MICREL_PHY_ID_MASK, |
529ed127 | 915 | .features = PHY_BASIC_FEATURES, |
7ab59dc1 | 916 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
e6a423a8 JH |
917 | .driver_data = &ksz8081_type, |
918 | .probe = kszphy_probe, | |
0f95903e | 919 | .config_init = kszphy_config_init, |
7ab59dc1 DC |
920 | .config_aneg = genphy_config_aneg, |
921 | .read_status = genphy_read_status, | |
922 | .ack_interrupt = kszphy_ack_interrupt, | |
923 | .config_intr = kszphy_config_intr, | |
2b2427d0 AL |
924 | .get_sset_count = kszphy_get_sset_count, |
925 | .get_strings = kszphy_get_strings, | |
926 | .get_stats = kszphy_get_stats, | |
836384d2 | 927 | .suspend = kszphy_suspend, |
f5aba91d | 928 | .resume = kszphy_resume, |
7ab59dc1 DC |
929 | }, { |
930 | .phy_id = PHY_ID_KSZ8061, | |
931 | .name = "Micrel KSZ8061", | |
f893a99e | 932 | .phy_id_mask = MICREL_PHY_ID_MASK, |
529ed127 | 933 | .features = PHY_BASIC_FEATURES, |
7ab59dc1 DC |
934 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
935 | .config_init = kszphy_config_init, | |
936 | .config_aneg = genphy_config_aneg, | |
937 | .read_status = genphy_read_status, | |
938 | .ack_interrupt = kszphy_ack_interrupt, | |
939 | .config_intr = kszphy_config_intr, | |
1a5465f5 PV |
940 | .suspend = genphy_suspend, |
941 | .resume = genphy_resume, | |
d5bf9071 | 942 | }, { |
d0507009 | 943 | .phy_id = PHY_ID_KSZ9021, |
48d7d0ad | 944 | .phy_id_mask = 0x000ffffe, |
d0507009 | 945 | .name = "Micrel KSZ9021 Gigabit PHY", |
529ed127 | 946 | .features = PHY_GBIT_FEATURES, |
51f932c4 | 947 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
c6f9575c | 948 | .driver_data = &ksz9021_type, |
bfe72442 | 949 | .probe = kszphy_probe, |
954c3967 | 950 | .config_init = ksz9021_config_init, |
d0507009 DC |
951 | .config_aneg = genphy_config_aneg, |
952 | .read_status = genphy_read_status, | |
51f932c4 | 953 | .ack_interrupt = kszphy_ack_interrupt, |
c6f9575c | 954 | .config_intr = kszphy_config_intr, |
2b2427d0 AL |
955 | .get_sset_count = kszphy_get_sset_count, |
956 | .get_strings = kszphy_get_strings, | |
957 | .get_stats = kszphy_get_stats, | |
1a5465f5 PV |
958 | .suspend = genphy_suspend, |
959 | .resume = genphy_resume, | |
19936942 VB |
960 | .read_mmd_indirect = ksz9021_rd_mmd_phyreg, |
961 | .write_mmd_indirect = ksz9021_wr_mmd_phyreg, | |
7ab59dc1 DC |
962 | }, { |
963 | .phy_id = PHY_ID_KSZ9031, | |
f893a99e | 964 | .phy_id_mask = MICREL_PHY_ID_MASK, |
7ab59dc1 | 965 | .name = "Micrel KSZ9031 Gigabit PHY", |
529ed127 | 966 | .features = PHY_GBIT_FEATURES, |
7ab59dc1 | 967 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
c6f9575c | 968 | .driver_data = &ksz9021_type, |
bfe72442 | 969 | .probe = kszphy_probe, |
6e4b8273 | 970 | .config_init = ksz9031_config_init, |
7ab59dc1 | 971 | .config_aneg = genphy_config_aneg, |
d2fd719b | 972 | .read_status = ksz9031_read_status, |
7ab59dc1 | 973 | .ack_interrupt = kszphy_ack_interrupt, |
c6f9575c | 974 | .config_intr = kszphy_config_intr, |
2b2427d0 AL |
975 | .get_sset_count = kszphy_get_sset_count, |
976 | .get_strings = kszphy_get_strings, | |
977 | .get_stats = kszphy_get_stats, | |
1a5465f5 | 978 | .suspend = genphy_suspend, |
f64f1482 | 979 | .resume = kszphy_resume, |
93272e07 JCPV |
980 | }, { |
981 | .phy_id = PHY_ID_KSZ8873MLL, | |
f893a99e | 982 | .phy_id_mask = MICREL_PHY_ID_MASK, |
93272e07 | 983 | .name = "Micrel KSZ8873MLL Switch", |
93272e07 JCPV |
984 | .flags = PHY_HAS_MAGICANEG, |
985 | .config_init = kszphy_config_init, | |
986 | .config_aneg = ksz8873mll_config_aneg, | |
987 | .read_status = ksz8873mll_read_status, | |
1a5465f5 PV |
988 | .suspend = genphy_suspend, |
989 | .resume = genphy_resume, | |
7ab59dc1 DC |
990 | }, { |
991 | .phy_id = PHY_ID_KSZ886X, | |
f893a99e | 992 | .phy_id_mask = MICREL_PHY_ID_MASK, |
7ab59dc1 | 993 | .name = "Micrel KSZ886X Switch", |
529ed127 | 994 | .features = PHY_BASIC_FEATURES, |
7ab59dc1 DC |
995 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
996 | .config_init = kszphy_config_init, | |
997 | .config_aneg = genphy_config_aneg, | |
998 | .read_status = genphy_read_status, | |
1a5465f5 PV |
999 | .suspend = genphy_suspend, |
1000 | .resume = genphy_resume, | |
9d162ed6 SN |
1001 | }, { |
1002 | .phy_id = PHY_ID_KSZ8795, | |
1003 | .phy_id_mask = MICREL_PHY_ID_MASK, | |
1004 | .name = "Micrel KSZ8795", | |
cf626c3b | 1005 | .features = PHY_BASIC_FEATURES, |
9d162ed6 SN |
1006 | .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT, |
1007 | .config_init = kszphy_config_init, | |
1008 | .config_aneg = ksz8873mll_config_aneg, | |
1009 | .read_status = ksz8873mll_read_status, | |
9d162ed6 SN |
1010 | .suspend = genphy_suspend, |
1011 | .resume = genphy_resume, | |
d5bf9071 | 1012 | } }; |
d0507009 | 1013 | |
50fd7150 | 1014 | module_phy_driver(ksphy_driver); |
d0507009 DC |
1015 | |
1016 | MODULE_DESCRIPTION("Micrel PHY driver"); | |
1017 | MODULE_AUTHOR("David J. Choi"); | |
1018 | MODULE_LICENSE("GPL"); | |
52a60ed2 | 1019 | |
cf93c945 | 1020 | static struct mdio_device_id __maybe_unused micrel_tbl[] = { |
48d7d0ad | 1021 | { PHY_ID_KSZ9021, 0x000ffffe }, |
f893a99e | 1022 | { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK }, |
ecd5a323 | 1023 | { PHY_ID_KSZ8001, 0x00fffffc }, |
f893a99e | 1024 | { PHY_ID_KS8737, MICREL_PHY_ID_MASK }, |
212ea99a | 1025 | { PHY_ID_KSZ8021, 0x00ffffff }, |
b818d1a7 | 1026 | { PHY_ID_KSZ8031, 0x00ffffff }, |
f893a99e FE |
1027 | { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK }, |
1028 | { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK }, | |
1029 | { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK }, | |
1030 | { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK }, | |
1031 | { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK }, | |
1032 | { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK }, | |
52a60ed2 DM |
1033 | { } |
1034 | }; | |
1035 | ||
1036 | MODULE_DEVICE_TABLE(mdio, micrel_tbl); |