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2f53e904 1/* Framework for configuring and reading PHY devices
00db8189
AF
2 * Based on code in sungem_phy.c and gianfar_phy.c
3 *
4 * Author: Andy Fleming
5 *
6 * Copyright (c) 2004 Freescale Semiconductor, Inc.
0ac49527 7 * Copyright (c) 2006, 2007 Maciej W. Rozycki
00db8189
AF
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
8d242488
JP
15
16#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
17
00db8189 18#include <linux/kernel.h>
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AF
19#include <linux/string.h>
20#include <linux/errno.h>
21#include <linux/unistd.h>
00db8189 22#include <linux/interrupt.h>
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AF
23#include <linux/delay.h>
24#include <linux/netdevice.h>
25#include <linux/etherdevice.h>
26#include <linux/skbuff.h>
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AF
27#include <linux/mm.h>
28#include <linux/module.h>
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AF
29#include <linux/mii.h>
30#include <linux/ethtool.h>
31#include <linux/phy.h>
3c3070d7
MR
32#include <linux/timer.h>
33#include <linux/workqueue.h>
a59a4d19 34#include <linux/mdio.h>
2f53e904
SS
35#include <linux/io.h>
36#include <linux/uaccess.h>
60063497 37#include <linux/atomic.h>
2f53e904 38
00db8189 39#include <asm/irq.h>
00db8189 40
766d1d38
FF
41static const char *phy_speed_to_str(int speed)
42{
43 switch (speed) {
44 case SPEED_10:
45 return "10Mbps";
46 case SPEED_100:
47 return "100Mbps";
48 case SPEED_1000:
49 return "1Gbps";
50 case SPEED_2500:
51 return "2.5Gbps";
52 case SPEED_10000:
53 return "10Gbps";
54 case SPEED_UNKNOWN:
55 return "Unknown";
56 default:
57 return "Unsupported (update phy.c)";
58 }
59}
60
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RD
61/**
62 * phy_print_status - Convenience function to print out the current phy status
63 * @phydev: the phy_device struct
e1393456
AF
64 */
65void phy_print_status(struct phy_device *phydev)
66{
2f53e904 67 if (phydev->link) {
df40cc88 68 netdev_info(phydev->attached_dev,
766d1d38
FF
69 "Link is Up - %s/%s - flow control %s\n",
70 phy_speed_to_str(phydev->speed),
df40cc88
FF
71 DUPLEX_FULL == phydev->duplex ? "Full" : "Half",
72 phydev->pause ? "rx/tx" : "off");
2f53e904 73 } else {
43b6329f 74 netdev_info(phydev->attached_dev, "Link is Down\n");
2f53e904 75 }
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AF
76}
77EXPORT_SYMBOL(phy_print_status);
00db8189 78
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RD
79/**
80 * phy_clear_interrupt - Ack the phy device's interrupt
81 * @phydev: the phy_device struct
82 *
83 * If the @phydev driver has an ack_interrupt function, call it to
84 * ack and clear the phy device's interrupt.
85 *
ad033506 86 * Returns 0 on success or < 0 on error.
b3df0da8 87 */
89ff05ec 88static int phy_clear_interrupt(struct phy_device *phydev)
00db8189 89{
00db8189 90 if (phydev->drv->ack_interrupt)
e62a768f 91 return phydev->drv->ack_interrupt(phydev);
00db8189 92
e62a768f 93 return 0;
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AF
94}
95
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RD
96/**
97 * phy_config_interrupt - configure the PHY device for the requested interrupts
98 * @phydev: the phy_device struct
99 * @interrupts: interrupt flags to configure for this @phydev
100 *
ad033506 101 * Returns 0 on success or < 0 on error.
b3df0da8 102 */
89ff05ec 103static int phy_config_interrupt(struct phy_device *phydev, u32 interrupts)
00db8189 104{
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AF
105 phydev->interrupts = interrupts;
106 if (phydev->drv->config_intr)
e62a768f 107 return phydev->drv->config_intr(phydev);
00db8189 108
e62a768f 109 return 0;
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AF
110}
111
112
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RD
113/**
114 * phy_aneg_done - return auto-negotiation status
115 * @phydev: target phy_device struct
00db8189 116 *
76a423a3
FF
117 * Description: Return the auto-negotiation status from this @phydev
118 * Returns > 0 on success or < 0 on error. 0 means that auto-negotiation
119 * is still pending.
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AF
120 */
121static inline int phy_aneg_done(struct phy_device *phydev)
122{
76a423a3
FF
123 if (phydev->drv->aneg_done)
124 return phydev->drv->aneg_done(phydev);
125
a9fa6e6a 126 return genphy_aneg_done(phydev);
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AF
127}
128
00db8189 129/* A structure for mapping a particular speed and duplex
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SS
130 * combination to a particular SUPPORTED and ADVERTISED value
131 */
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AF
132struct phy_setting {
133 int speed;
134 int duplex;
135 u32 setting;
136};
137
138/* A mapping of all SUPPORTED settings to speed/duplex */
f71e1309 139static const struct phy_setting settings[] = {
00db8189 140 {
3e707706
LT
141 .speed = SPEED_10000,
142 .duplex = DUPLEX_FULL,
143 .setting = SUPPORTED_10000baseKR_Full,
144 },
145 {
146 .speed = SPEED_10000,
147 .duplex = DUPLEX_FULL,
148 .setting = SUPPORTED_10000baseKX4_Full,
149 },
150 {
151 .speed = SPEED_10000,
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AF
152 .duplex = DUPLEX_FULL,
153 .setting = SUPPORTED_10000baseT_Full,
154 },
3e707706
LT
155 {
156 .speed = SPEED_2500,
157 .duplex = DUPLEX_FULL,
158 .setting = SUPPORTED_2500baseX_Full,
159 },
160 {
161 .speed = SPEED_1000,
162 .duplex = DUPLEX_FULL,
163 .setting = SUPPORTED_1000baseKX_Full,
164 },
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AF
165 {
166 .speed = SPEED_1000,
167 .duplex = DUPLEX_FULL,
168 .setting = SUPPORTED_1000baseT_Full,
169 },
170 {
171 .speed = SPEED_1000,
172 .duplex = DUPLEX_HALF,
173 .setting = SUPPORTED_1000baseT_Half,
174 },
175 {
176 .speed = SPEED_100,
177 .duplex = DUPLEX_FULL,
178 .setting = SUPPORTED_100baseT_Full,
179 },
180 {
181 .speed = SPEED_100,
182 .duplex = DUPLEX_HALF,
183 .setting = SUPPORTED_100baseT_Half,
184 },
185 {
186 .speed = SPEED_10,
187 .duplex = DUPLEX_FULL,
188 .setting = SUPPORTED_10baseT_Full,
189 },
190 {
191 .speed = SPEED_10,
192 .duplex = DUPLEX_HALF,
193 .setting = SUPPORTED_10baseT_Half,
194 },
195};
196
ff8ac609 197#define MAX_NUM_SETTINGS ARRAY_SIZE(settings)
00db8189 198
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RD
199/**
200 * phy_find_setting - find a PHY settings array entry that matches speed & duplex
201 * @speed: speed to match
202 * @duplex: duplex to match
00db8189 203 *
b3df0da8 204 * Description: Searches the settings array for the setting which
00db8189
AF
205 * matches the desired speed and duplex, and returns the index
206 * of that setting. Returns the index of the last setting if
207 * none of the others match.
208 */
4ae6e50c 209static inline unsigned int phy_find_setting(int speed, int duplex)
00db8189 210{
4ae6e50c 211 unsigned int idx = 0;
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AF
212
213 while (idx < ARRAY_SIZE(settings) &&
2f53e904 214 (settings[idx].speed != speed || settings[idx].duplex != duplex))
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AF
215 idx++;
216
217 return idx < MAX_NUM_SETTINGS ? idx : MAX_NUM_SETTINGS - 1;
218}
219
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RD
220/**
221 * phy_find_valid - find a PHY setting that matches the requested features mask
222 * @idx: The first index in settings[] to search
223 * @features: A mask of the valid settings
00db8189 224 *
b3df0da8 225 * Description: Returns the index of the first valid setting less
00db8189
AF
226 * than or equal to the one pointed to by idx, as determined by
227 * the mask in features. Returns the index of the last setting
228 * if nothing else matches.
229 */
4ae6e50c 230static inline unsigned int phy_find_valid(unsigned int idx, u32 features)
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AF
231{
232 while (idx < MAX_NUM_SETTINGS && !(settings[idx].setting & features))
233 idx++;
234
235 return idx < MAX_NUM_SETTINGS ? idx : MAX_NUM_SETTINGS - 1;
236}
237
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RD
238/**
239 * phy_sanitize_settings - make sure the PHY is set to supported speed and duplex
240 * @phydev: the target phy_device struct
00db8189 241 *
b3df0da8 242 * Description: Make sure the PHY is set to supported speeds and
00db8189 243 * duplexes. Drop down by one in this order: 1000/FULL,
b3df0da8 244 * 1000/HALF, 100/FULL, 100/HALF, 10/FULL, 10/HALF.
00db8189 245 */
89ff05ec 246static void phy_sanitize_settings(struct phy_device *phydev)
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AF
247{
248 u32 features = phydev->supported;
4ae6e50c 249 unsigned int idx;
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AF
250
251 /* Sanitize settings based on PHY capabilities */
252 if ((features & SUPPORTED_Autoneg) == 0)
163642a2 253 phydev->autoneg = AUTONEG_DISABLE;
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AF
254
255 idx = phy_find_valid(phy_find_setting(phydev->speed, phydev->duplex),
256 features);
257
258 phydev->speed = settings[idx].speed;
259 phydev->duplex = settings[idx].duplex;
260}
00db8189 261
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RD
262/**
263 * phy_ethtool_sset - generic ethtool sset function, handles all the details
264 * @phydev: target phy_device struct
265 * @cmd: ethtool_cmd
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AF
266 *
267 * A few notes about parameter checking:
268 * - We don't set port or transceiver, so we don't care what they
269 * were set to.
270 * - phy_start_aneg() will make sure forced settings are sane, and
271 * choose the next best ones from the ones selected, so we don't
b3df0da8 272 * care if ethtool tries to give us bad values.
00db8189
AF
273 */
274int phy_ethtool_sset(struct phy_device *phydev, struct ethtool_cmd *cmd)
275{
25db0338
DD
276 u32 speed = ethtool_cmd_speed(cmd);
277
00db8189
AF
278 if (cmd->phy_address != phydev->addr)
279 return -EINVAL;
280
2f53e904 281 /* We make sure that we don't pass unsupported values in to the PHY */
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AF
282 cmd->advertising &= phydev->supported;
283
284 /* Verify the settings we care about. */
285 if (cmd->autoneg != AUTONEG_ENABLE && cmd->autoneg != AUTONEG_DISABLE)
286 return -EINVAL;
287
288 if (cmd->autoneg == AUTONEG_ENABLE && cmd->advertising == 0)
289 return -EINVAL;
290
8e95a202 291 if (cmd->autoneg == AUTONEG_DISABLE &&
25db0338
DD
292 ((speed != SPEED_1000 &&
293 speed != SPEED_100 &&
294 speed != SPEED_10) ||
8e95a202
JP
295 (cmd->duplex != DUPLEX_HALF &&
296 cmd->duplex != DUPLEX_FULL)))
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AF
297 return -EINVAL;
298
299 phydev->autoneg = cmd->autoneg;
300
25db0338 301 phydev->speed = speed;
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AF
302
303 phydev->advertising = cmd->advertising;
304
305 if (AUTONEG_ENABLE == cmd->autoneg)
306 phydev->advertising |= ADVERTISED_Autoneg;
307 else
308 phydev->advertising &= ~ADVERTISED_Autoneg;
309
310 phydev->duplex = cmd->duplex;
311
312 /* Restart the PHY */
313 phy_start_aneg(phydev);
314
315 return 0;
316}
9f6d55d0 317EXPORT_SYMBOL(phy_ethtool_sset);
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AF
318
319int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd)
320{
321 cmd->supported = phydev->supported;
322
323 cmd->advertising = phydev->advertising;
114002bc 324 cmd->lp_advertising = phydev->lp_advertising;
00db8189 325
70739497 326 ethtool_cmd_speed_set(cmd, phydev->speed);
00db8189 327 cmd->duplex = phydev->duplex;
c88838ce
FF
328 if (phydev->interface == PHY_INTERFACE_MODE_MOCA)
329 cmd->port = PORT_BNC;
330 else
331 cmd->port = PORT_MII;
00db8189 332 cmd->phy_address = phydev->addr;
4284b6a5
FF
333 cmd->transceiver = phy_is_internal(phydev) ?
334 XCVR_INTERNAL : XCVR_EXTERNAL;
00db8189
AF
335 cmd->autoneg = phydev->autoneg;
336
337 return 0;
338}
9f6d55d0 339EXPORT_SYMBOL(phy_ethtool_gset);
00db8189 340
b3df0da8
RD
341/**
342 * phy_mii_ioctl - generic PHY MII ioctl interface
343 * @phydev: the phy_device struct
00c7d920 344 * @ifr: &struct ifreq for socket ioctl's
b3df0da8
RD
345 * @cmd: ioctl cmd to execute
346 *
347 * Note that this function is currently incompatible with the
00db8189 348 * PHYCONTROL layer. It changes registers without regard to
b3df0da8 349 * current state. Use at own risk.
00db8189 350 */
2f53e904 351int phy_mii_ioctl(struct phy_device *phydev, struct ifreq *ifr, int cmd)
00db8189 352{
28b04113 353 struct mii_ioctl_data *mii_data = if_mii(ifr);
00db8189
AF
354 u16 val = mii_data->val_in;
355
356 switch (cmd) {
357 case SIOCGMIIPHY:
358 mii_data->phy_id = phydev->addr;
c6d6a511
LB
359 /* fall through */
360
00db8189 361 case SIOCGMIIREG:
af1dc13e
PK
362 mii_data->val_out = mdiobus_read(phydev->bus, mii_data->phy_id,
363 mii_data->reg_num);
e62a768f 364 return 0;
00db8189
AF
365
366 case SIOCSMIIREG:
00db8189 367 if (mii_data->phy_id == phydev->addr) {
e109374f 368 switch (mii_data->reg_num) {
00db8189 369 case MII_BMCR:
2f53e904 370 if ((val & (BMCR_RESET | BMCR_ANENABLE)) == 0)
00db8189
AF
371 phydev->autoneg = AUTONEG_DISABLE;
372 else
373 phydev->autoneg = AUTONEG_ENABLE;
2f53e904 374 if (!phydev->autoneg && (val & BMCR_FULLDPLX))
00db8189
AF
375 phydev->duplex = DUPLEX_FULL;
376 else
377 phydev->duplex = DUPLEX_HALF;
2f53e904 378 if (!phydev->autoneg && (val & BMCR_SPEED1000))
024a0a3c 379 phydev->speed = SPEED_1000;
2f53e904
SS
380 else if (!phydev->autoneg &&
381 (val & BMCR_SPEED100))
024a0a3c 382 phydev->speed = SPEED_100;
00db8189
AF
383 break;
384 case MII_ADVERTISE:
385 phydev->advertising = val;
386 break;
387 default:
388 /* do nothing */
389 break;
390 }
391 }
392
af1dc13e
PK
393 mdiobus_write(phydev->bus, mii_data->phy_id,
394 mii_data->reg_num, val);
395
8e95a202 396 if (mii_data->reg_num == MII_BMCR &&
2613f95f 397 val & BMCR_RESET)
e62a768f
SS
398 return phy_init_hw(phydev);
399 return 0;
dda93b48 400
c1f19b51
RC
401 case SIOCSHWTSTAMP:
402 if (phydev->drv->hwtstamp)
403 return phydev->drv->hwtstamp(phydev, ifr);
404 /* fall through */
405
dda93b48 406 default:
c6d6a511 407 return -EOPNOTSUPP;
00db8189 408 }
00db8189 409}
680e9fe9 410EXPORT_SYMBOL(phy_mii_ioctl);
00db8189 411
b3df0da8
RD
412/**
413 * phy_start_aneg - start auto-negotiation for this PHY device
414 * @phydev: the phy_device struct
e1393456 415 *
b3df0da8
RD
416 * Description: Sanitizes the settings (if we're not autonegotiating
417 * them), and then calls the driver's config_aneg function.
418 * If the PHYCONTROL Layer is operating, we change the state to
419 * reflect the beginning of Auto-negotiation or forcing.
e1393456
AF
420 */
421int phy_start_aneg(struct phy_device *phydev)
422{
423 int err;
424
35b5f6b1 425 mutex_lock(&phydev->lock);
e1393456
AF
426
427 if (AUTONEG_DISABLE == phydev->autoneg)
428 phy_sanitize_settings(phydev);
429
430 err = phydev->drv->config_aneg(phydev);
e1393456
AF
431 if (err < 0)
432 goto out_unlock;
433
434 if (phydev->state != PHY_HALTED) {
435 if (AUTONEG_ENABLE == phydev->autoneg) {
436 phydev->state = PHY_AN;
437 phydev->link_timeout = PHY_AN_TIMEOUT;
438 } else {
439 phydev->state = PHY_FORCING;
440 phydev->link_timeout = PHY_FORCE_TIMEOUT;
441 }
442 }
443
444out_unlock:
35b5f6b1 445 mutex_unlock(&phydev->lock);
e1393456
AF
446 return err;
447}
448EXPORT_SYMBOL(phy_start_aneg);
449
b3df0da8
RD
450/**
451 * phy_start_machine - start PHY state machine tracking
452 * @phydev: the phy_device struct
00db8189 453 *
b3df0da8 454 * Description: The PHY infrastructure can run a state machine
00db8189
AF
455 * which tracks whether the PHY is starting up, negotiating,
456 * etc. This function starts the timer which tracks the state
29935aeb
SS
457 * of the PHY. If you want to maintain your own state machine,
458 * do not call this function.
b3df0da8 459 */
29935aeb 460void phy_start_machine(struct phy_device *phydev)
00db8189 461{
bbb47bde 462 queue_delayed_work(system_power_efficient_wq, &phydev->state_queue, HZ);
00db8189
AF
463}
464
b3df0da8
RD
465/**
466 * phy_stop_machine - stop the PHY state machine tracking
467 * @phydev: target phy_device struct
00db8189 468 *
b3df0da8 469 * Description: Stops the state machine timer, sets the state to UP
817acf5e 470 * (unless it wasn't up yet). This function must be called BEFORE
00db8189
AF
471 * phy_detach.
472 */
473void phy_stop_machine(struct phy_device *phydev)
474{
a390d1f3 475 cancel_delayed_work_sync(&phydev->state_queue);
00db8189 476
35b5f6b1 477 mutex_lock(&phydev->lock);
00db8189
AF
478 if (phydev->state > PHY_UP)
479 phydev->state = PHY_UP;
35b5f6b1 480 mutex_unlock(&phydev->lock);
00db8189
AF
481}
482
b3df0da8
RD
483/**
484 * phy_error - enter HALTED state for this PHY device
485 * @phydev: target phy_device struct
00db8189
AF
486 *
487 * Moves the PHY to the HALTED state in response to a read
488 * or write error, and tells the controller the link is down.
489 * Must not be called from interrupt context, or while the
490 * phydev->lock is held.
491 */
9b9a8bfc 492static void phy_error(struct phy_device *phydev)
00db8189 493{
35b5f6b1 494 mutex_lock(&phydev->lock);
00db8189 495 phydev->state = PHY_HALTED;
35b5f6b1 496 mutex_unlock(&phydev->lock);
00db8189
AF
497}
498
b3df0da8
RD
499/**
500 * phy_interrupt - PHY interrupt handler
501 * @irq: interrupt line
502 * @phy_dat: phy_device pointer
e1393456 503 *
b3df0da8 504 * Description: When a PHY interrupt occurs, the handler disables
e1393456
AF
505 * interrupts, and schedules a work task to clear the interrupt.
506 */
7d12e780 507static irqreturn_t phy_interrupt(int irq, void *phy_dat)
e1393456
AF
508{
509 struct phy_device *phydev = phy_dat;
510
3c3070d7
MR
511 if (PHY_HALTED == phydev->state)
512 return IRQ_NONE; /* It can't be ours. */
513
e1393456
AF
514 /* The MDIO bus is not allowed to be written in interrupt
515 * context, so we need to disable the irq here. A work
516 * queue will write the PHY to disable and clear the
2f53e904
SS
517 * interrupt, and then reenable the irq line.
518 */
e1393456 519 disable_irq_nosync(irq);
0ac49527 520 atomic_inc(&phydev->irq_disable);
e1393456 521
bbb47bde 522 queue_work(system_power_efficient_wq, &phydev->phy_queue);
e1393456
AF
523
524 return IRQ_HANDLED;
525}
526
b3df0da8
RD
527/**
528 * phy_enable_interrupts - Enable the interrupts from the PHY side
529 * @phydev: target phy_device struct
530 */
89ff05ec 531static int phy_enable_interrupts(struct phy_device *phydev)
00db8189 532{
553fe92b 533 int err = phy_clear_interrupt(phydev);
00db8189 534
e1393456
AF
535 if (err < 0)
536 return err;
00db8189 537
553fe92b 538 return phy_config_interrupt(phydev, PHY_INTERRUPT_ENABLED);
00db8189 539}
00db8189 540
b3df0da8
RD
541/**
542 * phy_disable_interrupts - Disable the PHY interrupts from the PHY side
543 * @phydev: target phy_device struct
544 */
89ff05ec 545static int phy_disable_interrupts(struct phy_device *phydev)
00db8189
AF
546{
547 int err;
548
549 /* Disable PHY interrupts */
550 err = phy_config_interrupt(phydev, PHY_INTERRUPT_DISABLED);
00db8189
AF
551 if (err)
552 goto phy_err;
553
554 /* Clear the interrupt */
555 err = phy_clear_interrupt(phydev);
00db8189
AF
556 if (err)
557 goto phy_err;
558
559 return 0;
560
561phy_err:
562 phy_error(phydev);
563
564 return err;
565}
e1393456 566
b3df0da8
RD
567/**
568 * phy_start_interrupts - request and enable interrupts for a PHY device
569 * @phydev: target phy_device struct
e1393456 570 *
b3df0da8
RD
571 * Description: Request the interrupt for the given PHY.
572 * If this fails, then we set irq to PHY_POLL.
e1393456 573 * Otherwise, we enable the interrupts in the PHY.
e1393456 574 * This should only be called with a valid IRQ number.
b3df0da8 575 * Returns 0 on success or < 0 on error.
e1393456
AF
576 */
577int phy_start_interrupts(struct phy_device *phydev)
578{
0ac49527 579 atomic_set(&phydev->irq_disable, 0);
33c133cc
SS
580 if (request_irq(phydev->irq, phy_interrupt, 0, "phy_interrupt",
581 phydev) < 0) {
8d242488
JP
582 pr_warn("%s: Can't get IRQ %d (PHY)\n",
583 phydev->bus->name, phydev->irq);
e1393456
AF
584 phydev->irq = PHY_POLL;
585 return 0;
586 }
587
e62a768f 588 return phy_enable_interrupts(phydev);
e1393456
AF
589}
590EXPORT_SYMBOL(phy_start_interrupts);
591
b3df0da8
RD
592/**
593 * phy_stop_interrupts - disable interrupts from a PHY device
594 * @phydev: target phy_device struct
595 */
e1393456
AF
596int phy_stop_interrupts(struct phy_device *phydev)
597{
553fe92b 598 int err = phy_disable_interrupts(phydev);
e1393456
AF
599
600 if (err)
601 phy_error(phydev);
602
0ac49527
MR
603 free_irq(phydev->irq, phydev);
604
2f53e904 605 /* Cannot call flush_scheduled_work() here as desired because
0ac49527
MR
606 * of rtnl_lock(), but we do not really care about what would
607 * be done, except from enable_irq(), so cancel any work
608 * possibly pending and take care of the matter below.
3c3070d7 609 */
28e53bdd 610 cancel_work_sync(&phydev->phy_queue);
2f53e904 611 /* If work indeed has been cancelled, disable_irq() will have
0ac49527
MR
612 * been left unbalanced from phy_interrupt() and enable_irq()
613 * has to be called so that other devices on the line work.
614 */
615 while (atomic_dec_return(&phydev->irq_disable) >= 0)
616 enable_irq(phydev->irq);
e1393456
AF
617
618 return err;
619}
620EXPORT_SYMBOL(phy_stop_interrupts);
621
b3df0da8
RD
622/**
623 * phy_change - Scheduled by the phy_interrupt/timer to handle PHY changes
624 * @work: work_struct that describes the work to be done
625 */
5ea94e76 626void phy_change(struct work_struct *work)
e1393456 627{
c4028958
DH
628 struct phy_device *phydev =
629 container_of(work, struct phy_device, phy_queue);
e1393456 630
a8729eb3
AG
631 if (phydev->drv->did_interrupt &&
632 !phydev->drv->did_interrupt(phydev))
633 goto ignore;
634
e62a768f 635 if (phy_disable_interrupts(phydev))
e1393456
AF
636 goto phy_err;
637
35b5f6b1 638 mutex_lock(&phydev->lock);
e1393456
AF
639 if ((PHY_RUNNING == phydev->state) || (PHY_NOLINK == phydev->state))
640 phydev->state = PHY_CHANGELINK;
35b5f6b1 641 mutex_unlock(&phydev->lock);
e1393456 642
0ac49527 643 atomic_dec(&phydev->irq_disable);
e1393456
AF
644 enable_irq(phydev->irq);
645
646 /* Reenable interrupts */
e62a768f
SS
647 if (PHY_HALTED != phydev->state &&
648 phy_config_interrupt(phydev, PHY_INTERRUPT_ENABLED))
e1393456
AF
649 goto irq_enable_err;
650
a390d1f3
MS
651 /* reschedule state queue work to run as soon as possible */
652 cancel_delayed_work_sync(&phydev->state_queue);
bbb47bde 653 queue_delayed_work(system_power_efficient_wq, &phydev->state_queue, 0);
e1393456
AF
654 return;
655
a8729eb3
AG
656ignore:
657 atomic_dec(&phydev->irq_disable);
658 enable_irq(phydev->irq);
659 return;
660
e1393456
AF
661irq_enable_err:
662 disable_irq(phydev->irq);
0ac49527 663 atomic_inc(&phydev->irq_disable);
e1393456
AF
664phy_err:
665 phy_error(phydev);
666}
667
b3df0da8
RD
668/**
669 * phy_stop - Bring down the PHY link, and stop checking the status
670 * @phydev: target phy_device struct
671 */
e1393456
AF
672void phy_stop(struct phy_device *phydev)
673{
35b5f6b1 674 mutex_lock(&phydev->lock);
e1393456
AF
675
676 if (PHY_HALTED == phydev->state)
677 goto out_unlock;
678
2c7b4921 679 if (phy_interrupt_is_valid(phydev)) {
e1393456
AF
680 /* Disable PHY Interrupts */
681 phy_config_interrupt(phydev, PHY_INTERRUPT_DISABLED);
e1393456 682
3c3070d7
MR
683 /* Clear any pending interrupts */
684 phy_clear_interrupt(phydev);
685 }
e1393456 686
6daf6531
MR
687 phydev->state = PHY_HALTED;
688
e1393456 689out_unlock:
35b5f6b1 690 mutex_unlock(&phydev->lock);
3c3070d7 691
2f53e904 692 /* Cannot call flush_scheduled_work() here as desired because
3c3070d7
MR
693 * of rtnl_lock(), but PHY_HALTED shall guarantee phy_change()
694 * will not reenable interrupts.
695 */
e1393456 696}
2f53e904 697EXPORT_SYMBOL(phy_stop);
e1393456 698
b3df0da8
RD
699/**
700 * phy_start - start or restart a PHY device
701 * @phydev: target phy_device struct
e1393456 702 *
b3df0da8 703 * Description: Indicates the attached device's readiness to
e1393456
AF
704 * handle PHY-related work. Used during startup to start the
705 * PHY, and after a call to phy_stop() to resume operation.
706 * Also used to indicate the MDIO bus has cleared an error
707 * condition.
708 */
709void phy_start(struct phy_device *phydev)
710{
35b5f6b1 711 mutex_lock(&phydev->lock);
e1393456
AF
712
713 switch (phydev->state) {
e109374f
FF
714 case PHY_STARTING:
715 phydev->state = PHY_PENDING;
716 break;
717 case PHY_READY:
718 phydev->state = PHY_UP;
719 break;
720 case PHY_HALTED:
721 phydev->state = PHY_RESUMING;
722 default:
723 break;
e1393456 724 }
35b5f6b1 725 mutex_unlock(&phydev->lock);
e1393456 726}
e1393456 727EXPORT_SYMBOL(phy_start);
67c4f3fa 728
35b5f6b1
NC
729/**
730 * phy_state_machine - Handle the state machine
731 * @work: work_struct that describes the work to be done
35b5f6b1 732 */
4f9c85a1 733void phy_state_machine(struct work_struct *work)
00db8189 734{
bf6aede7 735 struct delayed_work *dwork = to_delayed_work(work);
35b5f6b1 736 struct phy_device *phydev =
a390d1f3 737 container_of(dwork, struct phy_device, state_queue);
6e14a5ee 738 bool needs_aneg = false, do_suspend = false, do_resume = false;
00db8189
AF
739 int err = 0;
740
35b5f6b1 741 mutex_lock(&phydev->lock);
00db8189 742
2b8f2a28
DM
743 if (phydev->drv->link_change_notify)
744 phydev->drv->link_change_notify(phydev);
745
e109374f
FF
746 switch (phydev->state) {
747 case PHY_DOWN:
748 case PHY_STARTING:
749 case PHY_READY:
750 case PHY_PENDING:
751 break;
752 case PHY_UP:
6e14a5ee 753 needs_aneg = true;
00db8189 754
e109374f
FF
755 phydev->link_timeout = PHY_AN_TIMEOUT;
756
757 break;
758 case PHY_AN:
759 err = phy_read_status(phydev);
e109374f 760 if (err < 0)
00db8189 761 break;
6b655529 762
2f53e904 763 /* If the link is down, give up on negotiation for now */
e109374f
FF
764 if (!phydev->link) {
765 phydev->state = PHY_NOLINK;
766 netif_carrier_off(phydev->attached_dev);
767 phydev->adjust_link(phydev->attached_dev);
768 break;
769 }
6b655529 770
2f53e904 771 /* Check if negotiation is done. Break if there's an error */
e109374f
FF
772 err = phy_aneg_done(phydev);
773 if (err < 0)
774 break;
6b655529 775
e109374f
FF
776 /* If AN is done, we're running */
777 if (err > 0) {
778 phydev->state = PHY_RUNNING;
779 netif_carrier_on(phydev->attached_dev);
780 phydev->adjust_link(phydev->attached_dev);
00db8189 781
fa8cddaf 782 } else if (0 == phydev->link_timeout--)
6e14a5ee 783 needs_aneg = true;
e109374f
FF
784 break;
785 case PHY_NOLINK:
786 err = phy_read_status(phydev);
e109374f 787 if (err)
00db8189 788 break;
00db8189 789
e109374f 790 if (phydev->link) {
e46e08b8
BK
791 if (AUTONEG_ENABLE == phydev->autoneg) {
792 err = phy_aneg_done(phydev);
793 if (err < 0)
794 break;
795
796 if (!err) {
797 phydev->state = PHY_AN;
798 phydev->link_timeout = PHY_AN_TIMEOUT;
799 break;
800 }
801 }
e109374f
FF
802 phydev->state = PHY_RUNNING;
803 netif_carrier_on(phydev->attached_dev);
804 phydev->adjust_link(phydev->attached_dev);
805 }
806 break;
807 case PHY_FORCING:
808 err = genphy_update_link(phydev);
e109374f 809 if (err)
00db8189 810 break;
00db8189 811
e109374f
FF
812 if (phydev->link) {
813 phydev->state = PHY_RUNNING;
814 netif_carrier_on(phydev->attached_dev);
815 } else {
816 if (0 == phydev->link_timeout--)
6e14a5ee 817 needs_aneg = true;
e109374f 818 }
00db8189 819
e109374f
FF
820 phydev->adjust_link(phydev->attached_dev);
821 break;
822 case PHY_RUNNING:
823 /* Only register a CHANGE if we are
824 * polling or ignoring interrupts
825 */
826 if (!phy_interrupt_is_valid(phydev))
827 phydev->state = PHY_CHANGELINK;
828 break;
829 case PHY_CHANGELINK:
830 err = phy_read_status(phydev);
e109374f 831 if (err)
00db8189 832 break;
00db8189 833
e109374f
FF
834 if (phydev->link) {
835 phydev->state = PHY_RUNNING;
836 netif_carrier_on(phydev->attached_dev);
837 } else {
838 phydev->state = PHY_NOLINK;
839 netif_carrier_off(phydev->attached_dev);
840 }
00db8189 841
e109374f 842 phydev->adjust_link(phydev->attached_dev);
00db8189 843
e109374f
FF
844 if (phy_interrupt_is_valid(phydev))
845 err = phy_config_interrupt(phydev,
2f53e904 846 PHY_INTERRUPT_ENABLED);
e109374f
FF
847 break;
848 case PHY_HALTED:
849 if (phydev->link) {
850 phydev->link = 0;
851 netif_carrier_off(phydev->attached_dev);
00db8189 852 phydev->adjust_link(phydev->attached_dev);
6e14a5ee 853 do_suspend = true;
e109374f
FF
854 }
855 break;
856 case PHY_RESUMING:
e109374f 857 err = phy_clear_interrupt(phydev);
e109374f
FF
858 if (err)
859 break;
00db8189 860
2f53e904 861 err = phy_config_interrupt(phydev, PHY_INTERRUPT_ENABLED);
e109374f
FF
862 if (err)
863 break;
00db8189 864
e109374f
FF
865 if (AUTONEG_ENABLE == phydev->autoneg) {
866 err = phy_aneg_done(phydev);
867 if (err < 0)
00db8189
AF
868 break;
869
e109374f 870 /* err > 0 if AN is done.
2f53e904
SS
871 * Otherwise, it's 0, and we're still waiting for AN
872 */
e109374f 873 if (err > 0) {
42caa074
WF
874 err = phy_read_status(phydev);
875 if (err)
876 break;
877
878 if (phydev->link) {
879 phydev->state = PHY_RUNNING;
880 netif_carrier_on(phydev->attached_dev);
2f53e904 881 } else {
42caa074 882 phydev->state = PHY_NOLINK;
2f53e904 883 }
42caa074 884 phydev->adjust_link(phydev->attached_dev);
e109374f
FF
885 } else {
886 phydev->state = PHY_AN;
887 phydev->link_timeout = PHY_AN_TIMEOUT;
42caa074 888 }
e109374f
FF
889 } else {
890 err = phy_read_status(phydev);
891 if (err)
892 break;
893
894 if (phydev->link) {
895 phydev->state = PHY_RUNNING;
896 netif_carrier_on(phydev->attached_dev);
2f53e904 897 } else {
e109374f 898 phydev->state = PHY_NOLINK;
2f53e904 899 }
e109374f
FF
900 phydev->adjust_link(phydev->attached_dev);
901 }
6e14a5ee 902 do_resume = true;
e109374f 903 break;
00db8189
AF
904 }
905
35b5f6b1 906 mutex_unlock(&phydev->lock);
00db8189
AF
907
908 if (needs_aneg)
909 err = phy_start_aneg(phydev);
6e14a5ee 910 else if (do_suspend)
be9dad1f 911 phy_suspend(phydev);
6e14a5ee
ZG
912 else if (do_resume)
913 phy_resume(phydev);
be9dad1f 914
00db8189
AF
915 if (err < 0)
916 phy_error(phydev);
917
bbb47bde 918 queue_delayed_work(system_power_efficient_wq, &phydev->state_queue,
2f53e904 919 PHY_STATE_TIME * HZ);
35b5f6b1 920}
a59a4d19 921
5ea94e76
FF
922void phy_mac_interrupt(struct phy_device *phydev, int new_link)
923{
924 cancel_work_sync(&phydev->phy_queue);
925 phydev->link = new_link;
926 schedule_work(&phydev->phy_queue);
927}
928EXPORT_SYMBOL(phy_mac_interrupt);
929
a59a4d19
GC
930static inline void mmd_phy_indirect(struct mii_bus *bus, int prtad, int devad,
931 int addr)
932{
933 /* Write the desired MMD Devad */
934 bus->write(bus, addr, MII_MMD_CTRL, devad);
935
936 /* Write the desired MMD register address */
937 bus->write(bus, addr, MII_MMD_DATA, prtad);
938
939 /* Select the Function : DATA with no post increment */
940 bus->write(bus, addr, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
941}
942
943/**
944 * phy_read_mmd_indirect - reads data from the MMD registers
0c1d77df 945 * @phydev: The PHY device bus
a59a4d19
GC
946 * @prtad: MMD Address
947 * @devad: MMD DEVAD
948 * @addr: PHY address on the MII bus
949 *
950 * Description: it reads data from the MMD registers (clause 22 to access to
951 * clause 45) of the specified phy address.
952 * To read these register we have:
953 * 1) Write reg 13 // DEVAD
954 * 2) Write reg 14 // MMD Address
955 * 3) Write reg 13 // MMD Data Command for MMD DEVAD
956 * 3) Read reg 14 // Read MMD data
957 */
66ce7fb9 958int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
0c1d77df 959 int devad, int addr)
a59a4d19 960{
0c1d77df
VB
961 struct phy_driver *phydrv = phydev->drv;
962 int value = -1;
a59a4d19 963
0c1d77df
VB
964 if (phydrv->read_mmd_indirect == NULL) {
965 mmd_phy_indirect(phydev->bus, prtad, devad, addr);
966
967 /* Read the content of the MMD's selected register */
968 value = phydev->bus->read(phydev->bus, addr, MII_MMD_DATA);
969 } else {
970 value = phydrv->read_mmd_indirect(phydev, prtad, devad, addr);
971 }
972 return value;
a59a4d19 973}
66ce7fb9 974EXPORT_SYMBOL(phy_read_mmd_indirect);
a59a4d19
GC
975
976/**
977 * phy_write_mmd_indirect - writes data to the MMD registers
0c1d77df 978 * @phydev: The PHY device
a59a4d19
GC
979 * @prtad: MMD Address
980 * @devad: MMD DEVAD
981 * @addr: PHY address on the MII bus
982 * @data: data to write in the MMD register
983 *
984 * Description: Write data from the MMD registers of the specified
985 * phy address.
986 * To write these register we have:
987 * 1) Write reg 13 // DEVAD
988 * 2) Write reg 14 // MMD Address
989 * 3) Write reg 13 // MMD Data Command for MMD DEVAD
990 * 3) Write reg 14 // Write MMD data
991 */
66ce7fb9 992void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
0c1d77df 993 int devad, int addr, u32 data)
a59a4d19 994{
0c1d77df 995 struct phy_driver *phydrv = phydev->drv;
a59a4d19 996
0c1d77df
VB
997 if (phydrv->write_mmd_indirect == NULL) {
998 mmd_phy_indirect(phydev->bus, prtad, devad, addr);
999
1000 /* Write the data into MMD's selected register */
1001 phydev->bus->write(phydev->bus, addr, MII_MMD_DATA, data);
1002 } else {
1003 phydrv->write_mmd_indirect(phydev, prtad, devad, addr, data);
1004 }
a59a4d19 1005}
66ce7fb9 1006EXPORT_SYMBOL(phy_write_mmd_indirect);
a59a4d19 1007
a59a4d19
GC
1008/**
1009 * phy_init_eee - init and check the EEE feature
1010 * @phydev: target phy_device struct
1011 * @clk_stop_enable: PHY may stop the clock during LPI
1012 *
1013 * Description: it checks if the Energy-Efficient Ethernet (EEE)
1014 * is supported by looking at the MMD registers 3.20 and 7.60/61
1015 * and it programs the MMD register 3.0 setting the "Clock stop enable"
1016 * bit if required.
1017 */
1018int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable)
1019{
a59a4d19
GC
1020 /* According to 802.3az,the EEE is supported only in full duplex-mode.
1021 * Also EEE feature is active when core is operating with MII, GMII
a9f63095
FF
1022 * or RGMII. Internal PHYs are also allowed to proceed and should
1023 * return an error if they do not support EEE.
a59a4d19
GC
1024 */
1025 if ((phydev->duplex == DUPLEX_FULL) &&
1026 ((phydev->interface == PHY_INTERFACE_MODE_MII) ||
1027 (phydev->interface == PHY_INTERFACE_MODE_GMII) ||
a9f63095
FF
1028 (phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
1029 phy_is_internal(phydev))) {
a59a4d19
GC
1030 int eee_lp, eee_cap, eee_adv;
1031 u32 lp, cap, adv;
4ae6e50c
BH
1032 int status;
1033 unsigned int idx;
a59a4d19
GC
1034
1035 /* Read phy status to properly get the right settings */
1036 status = phy_read_status(phydev);
1037 if (status)
1038 return status;
1039
1040 /* First check if the EEE ability is supported */
0c1d77df 1041 eee_cap = phy_read_mmd_indirect(phydev, MDIO_PCS_EEE_ABLE,
a59a4d19 1042 MDIO_MMD_PCS, phydev->addr);
7a4cecf7
GC
1043 if (eee_cap <= 0)
1044 goto eee_exit_err;
a59a4d19 1045
b32607dd 1046 cap = mmd_eee_cap_to_ethtool_sup_t(eee_cap);
a59a4d19 1047 if (!cap)
7a4cecf7 1048 goto eee_exit_err;
a59a4d19
GC
1049
1050 /* Check which link settings negotiated and verify it in
1051 * the EEE advertising registers.
1052 */
0c1d77df 1053 eee_lp = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_LPABLE,
a59a4d19 1054 MDIO_MMD_AN, phydev->addr);
7a4cecf7
GC
1055 if (eee_lp <= 0)
1056 goto eee_exit_err;
a59a4d19 1057
0c1d77df 1058 eee_adv = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
a59a4d19 1059 MDIO_MMD_AN, phydev->addr);
7a4cecf7
GC
1060 if (eee_adv <= 0)
1061 goto eee_exit_err;
a59a4d19 1062
b32607dd
AB
1063 adv = mmd_eee_adv_to_ethtool_adv_t(eee_adv);
1064 lp = mmd_eee_adv_to_ethtool_adv_t(eee_lp);
a59a4d19 1065 idx = phy_find_setting(phydev->speed, phydev->duplex);
9a9c56cb 1066 if (!(lp & adv & settings[idx].setting))
7a4cecf7 1067 goto eee_exit_err;
a59a4d19
GC
1068
1069 if (clk_stop_enable) {
1070 /* Configure the PHY to stop receiving xMII
1071 * clock while it is signaling LPI.
1072 */
0c1d77df 1073 int val = phy_read_mmd_indirect(phydev, MDIO_CTRL1,
a59a4d19
GC
1074 MDIO_MMD_PCS,
1075 phydev->addr);
1076 if (val < 0)
1077 return val;
1078
1079 val |= MDIO_PCS_CTRL1_CLKSTOP_EN;
0c1d77df
VB
1080 phy_write_mmd_indirect(phydev, MDIO_CTRL1,
1081 MDIO_MMD_PCS, phydev->addr,
1082 val);
a59a4d19
GC
1083 }
1084
e62a768f 1085 return 0; /* EEE supported */
a59a4d19 1086 }
7a4cecf7 1087eee_exit_err:
e62a768f 1088 return -EPROTONOSUPPORT;
a59a4d19
GC
1089}
1090EXPORT_SYMBOL(phy_init_eee);
1091
1092/**
1093 * phy_get_eee_err - report the EEE wake error count
1094 * @phydev: target phy_device struct
1095 *
1096 * Description: it is to report the number of time where the PHY
1097 * failed to complete its normal wake sequence.
1098 */
1099int phy_get_eee_err(struct phy_device *phydev)
1100{
0c1d77df 1101 return phy_read_mmd_indirect(phydev, MDIO_PCS_EEE_WK_ERR,
a59a4d19 1102 MDIO_MMD_PCS, phydev->addr);
a59a4d19
GC
1103}
1104EXPORT_SYMBOL(phy_get_eee_err);
1105
1106/**
1107 * phy_ethtool_get_eee - get EEE supported and status
1108 * @phydev: target phy_device struct
1109 * @data: ethtool_eee data
1110 *
1111 * Description: it reportes the Supported/Advertisement/LP Advertisement
1112 * capabilities.
1113 */
1114int phy_ethtool_get_eee(struct phy_device *phydev, struct ethtool_eee *data)
1115{
1116 int val;
1117
1118 /* Get Supported EEE */
0c1d77df 1119 val = phy_read_mmd_indirect(phydev, MDIO_PCS_EEE_ABLE,
a59a4d19
GC
1120 MDIO_MMD_PCS, phydev->addr);
1121 if (val < 0)
1122 return val;
b32607dd 1123 data->supported = mmd_eee_cap_to_ethtool_sup_t(val);
a59a4d19
GC
1124
1125 /* Get advertisement EEE */
0c1d77df 1126 val = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
a59a4d19
GC
1127 MDIO_MMD_AN, phydev->addr);
1128 if (val < 0)
1129 return val;
b32607dd 1130 data->advertised = mmd_eee_adv_to_ethtool_adv_t(val);
a59a4d19
GC
1131
1132 /* Get LP advertisement EEE */
0c1d77df 1133 val = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_LPABLE,
a59a4d19
GC
1134 MDIO_MMD_AN, phydev->addr);
1135 if (val < 0)
1136 return val;
b32607dd 1137 data->lp_advertised = mmd_eee_adv_to_ethtool_adv_t(val);
a59a4d19
GC
1138
1139 return 0;
1140}
1141EXPORT_SYMBOL(phy_ethtool_get_eee);
1142
1143/**
1144 * phy_ethtool_set_eee - set EEE supported and status
1145 * @phydev: target phy_device struct
1146 * @data: ethtool_eee data
1147 *
1148 * Description: it is to program the Advertisement EEE register.
1149 */
1150int phy_ethtool_set_eee(struct phy_device *phydev, struct ethtool_eee *data)
1151{
553fe92b 1152 int val = ethtool_adv_to_mmd_eee_adv_t(data->advertised);
a59a4d19 1153
0c1d77df 1154 phy_write_mmd_indirect(phydev, MDIO_AN_EEE_ADV, MDIO_MMD_AN,
a59a4d19
GC
1155 phydev->addr, val);
1156
1157 return 0;
1158}
1159EXPORT_SYMBOL(phy_ethtool_set_eee);
42e836eb
MS
1160
1161int phy_ethtool_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1162{
1163 if (phydev->drv->set_wol)
1164 return phydev->drv->set_wol(phydev, wol);
1165
1166 return -EOPNOTSUPP;
1167}
1168EXPORT_SYMBOL(phy_ethtool_set_wol);
1169
1170void phy_ethtool_get_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol)
1171{
1172 if (phydev->drv->get_wol)
1173 phydev->drv->get_wol(phydev, wol);
1174}
1175EXPORT_SYMBOL(phy_ethtool_get_wol);