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Merge branch 'x86-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-bionic-kernel.git] / drivers / net / qla3xxx.c
CommitLineData
5a4faa87
RM		 1/*
2 * QLogic QLA3xxx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qla3xxx for copyright and licensing details.
6 */
7
eddc5fbd
JP		 8#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9
5a4faa87
RM		 10#include <linux/kernel.h>
11#include <linux/init.h>
12#include <linux/types.h>
13#include <linux/module.h>
14#include <linux/list.h>
15#include <linux/pci.h>
16#include <linux/dma-mapping.h>
17#include <linux/sched.h>
18#include <linux/slab.h>
19#include <linux/dmapool.h>
20#include <linux/mempool.h>
21#include <linux/spinlock.h>
22#include <linux/kthread.h>
23#include <linux/interrupt.h>
24#include <linux/errno.h>
25#include <linux/ioport.h>
26#include <linux/ip.h>
bd36b0ac 27#include <linux/in.h>
5a4faa87
RM		 28#include <linux/if_arp.h>
29#include <linux/if_ether.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/skbuff.h>
34#include <linux/rtnetlink.h>
35#include <linux/if_vlan.h>
5a4faa87
RM		 36#include <linux/delay.h>
37#include <linux/mm.h>
70c71606 38#include <linux/prefetch.h>
5a4faa87
RM		 39
40#include "qla3xxx.h"
41
d7f61777
JP		 42#define DRV_NAME "qla3xxx"
43#define DRV_STRING "QLogic ISP3XXX Network Driver"
b08c42b2 44#define DRV_VERSION "v2.03.00-k5"
5a4faa87
RM		 45
46static const char ql3xxx_driver_name[] = DRV_NAME;
47static const char ql3xxx_driver_version[] = DRV_VERSION;
48
eddc5fbd
JP		 49#define TIMED_OUT_MSG \
50"Timed out waiting for management port to get free before issuing command\n"
51
5a4faa87
RM		 52MODULE_AUTHOR("QLogic Corporation");
53MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " ");
54MODULE_LICENSE("GPL");
55MODULE_VERSION(DRV_VERSION);
56
57static const u32 default_msg
58 = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
59 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
60
61static int debug = -1; /* defaults above */
62module_param(debug, int, 0);
63MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
64
65static int msi;
66module_param(msi, int, 0);
67MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts.");
68
a3aa1884 69static DEFINE_PCI_DEVICE_TABLE(ql3xxx_pci_tbl) = {
5a4faa87 70 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)},
bd36b0ac 71 {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)},
5a4faa87
RM		 72 /* required last entry */
73 {0,}
74};
75
76MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl);
77
3efedf2e
RM		 78/*
79 * These are the known PHY's which are used
80 */
d7f61777 81enum PHY_DEVICE_TYPE {
3efedf2e
RM		 82 PHY_TYPE_UNKNOWN = 0,
83 PHY_VITESSE_VSC8211,
84 PHY_AGERE_ET1011C,
85 MAX_PHY_DEV_TYPES
d7f61777
JP		 86};
87
88struct PHY_DEVICE_INFO {
89 const enum PHY_DEVICE_TYPE phyDevice;
90 const u32 phyIdOUI;
91 const u16 phyIdModel;
92 const char *name;
93};
94
95static const struct PHY_DEVICE_INFO PHY_DEVICES[] = {
96 {PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"},
97 {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"},
98 {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"},
3efedf2e
RM		 99};
100
101
5a4faa87
RM		 102/*
103 * Caller must take hw_lock.
104 */
105static int ql_sem_spinlock(struct ql3_adapter *qdev,
106 u32 sem_mask, u32 sem_bits)
107{
d7f61777
JP		 108 struct ql3xxx_port_registers __iomem *port_regs =
109 qdev->mem_map_registers;
5a4faa87
RM		 110 u32 value;
111 unsigned int seconds = 3;
112
113 do {
114 writel((sem_mask | sem_bits),
115 &port_regs->CommonRegs.semaphoreReg);
116 value = readl(&port_regs->CommonRegs.semaphoreReg);
117 if ((value & (sem_mask >> 16)) == sem_bits)
118 return 0;
119 ssleep(1);
d7f61777 120 } while (--seconds);
5a4faa87
RM		 121 return -1;
122}
123
124static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask)
125{
d7f61777
JP		 126 struct ql3xxx_port_registers __iomem *port_regs =
127 qdev->mem_map_registers;
5a4faa87
RM		 128 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
129 readl(&port_regs->CommonRegs.semaphoreReg);
130}
131
132static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits)
133{
d7f61777
JP		 134 struct ql3xxx_port_registers __iomem *port_regs =
135 qdev->mem_map_registers;
5a4faa87
RM		 136 u32 value;
137
138 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
139 value = readl(&port_regs->CommonRegs.semaphoreReg);
140 return ((value & (sem_mask >> 16)) == sem_bits);
141}
142
143/*
144 * Caller holds hw_lock.
145 */
146static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev)
147{
148 int i = 0;
149
eddc5fbd
JP		 150 while (i < 10) {
151 if (i)
152 ssleep(1);
153
154 if (ql_sem_lock(qdev,
155 QL_DRVR_SEM_MASK,
156 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
157 * 2) << 1)) {
158 netdev_printk(KERN_DEBUG, qdev->ndev,
159 "driver lock acquired\n");
5a4faa87
RM		 160 return 1;
161 }
162 }
eddc5fbd
JP		 163
164 netdev_err(qdev->ndev, "Timed out waiting for driver lock...\n");
165 return 0;
5a4faa87
RM		 166}
167
168static void ql_set_register_page(struct ql3_adapter *qdev, u32 page)
169{
d7f61777
JP		 170 struct ql3xxx_port_registers __iomem *port_regs =
171 qdev->mem_map_registers;
5a4faa87
RM		 172
173 writel(((ISP_CONTROL_NP_MASK << 16) | page),
174 &port_regs->CommonRegs.ispControlStatus);
175 readl(&port_regs->CommonRegs.ispControlStatus);
176 qdev->current_page = page;
177}
178
d7f61777 179static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
5a4faa87
RM		 180{
181 u32 value;
182 unsigned long hw_flags;
183
184 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
185 value = readl(reg);
186 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
187
188 return value;
189}
190
d7f61777 191static u32 ql_read_common_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
5a4faa87
RM		 192{
193 return readl(reg);
194}
195
196static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg)
197{
198 u32 value;
199 unsigned long hw_flags;
200
201 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
202
203 if (qdev->current_page != 0)
d7f61777 204 ql_set_register_page(qdev, 0);
5a4faa87
RM		 205 value = readl(reg);
206
207 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
208 return value;
209}
210
211static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg)
212{
213 if (qdev->current_page != 0)
d7f61777 214 ql_set_register_page(qdev, 0);
5a4faa87
RM		 215 return readl(reg);
216}
217
218static void ql_write_common_reg_l(struct ql3_adapter *qdev,
ee111d11 219 u32 __iomem *reg, u32 value)
5a4faa87
RM		 220{
221 unsigned long hw_flags;
222
223 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
ee111d11 224 writel(value, reg);
5a4faa87
RM		 225 readl(reg);
226 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87
RM		 227}
228
229static void ql_write_common_reg(struct ql3_adapter *qdev,
ee111d11 230 u32 __iomem *reg, u32 value)
5a4faa87 231{
ee111d11 232 writel(value, reg);
5a4faa87 233 readl(reg);
5a4faa87
RM		 234}
235
80b02e59
RM		 236static void ql_write_nvram_reg(struct ql3_adapter *qdev,
237 u32 __iomem *reg, u32 value)
238{
239 writel(value, reg);
240 readl(reg);
241 udelay(1);
80b02e59
RM		 242}
243
5a4faa87 244static void ql_write_page0_reg(struct ql3_adapter *qdev,
ee111d11 245 u32 __iomem *reg, u32 value)
5a4faa87
RM		 246{
247 if (qdev->current_page != 0)
d7f61777 248 ql_set_register_page(qdev, 0);
ee111d11 249 writel(value, reg);
5a4faa87 250 readl(reg);
5a4faa87
RM		 251}
252
253/*
254 * Caller holds hw_lock. Only called during init.
255 */
256static void ql_write_page1_reg(struct ql3_adapter *qdev,
ee111d11 257 u32 __iomem *reg, u32 value)
5a4faa87
RM		 258{
259 if (qdev->current_page != 1)
d7f61777 260 ql_set_register_page(qdev, 1);
ee111d11 261 writel(value, reg);
5a4faa87 262 readl(reg);
5a4faa87
RM		 263}
264
265/*
266 * Caller holds hw_lock. Only called during init.
267 */
268static void ql_write_page2_reg(struct ql3_adapter *qdev,
ee111d11 269 u32 __iomem *reg, u32 value)
5a4faa87
RM		 270{
271 if (qdev->current_page != 2)
d7f61777 272 ql_set_register_page(qdev, 2);
ee111d11 273 writel(value, reg);
5a4faa87 274 readl(reg);
5a4faa87
RM		 275}
276
277static void ql_disable_interrupts(struct ql3_adapter *qdev)
278{
d7f61777
JP		 279 struct ql3xxx_port_registers __iomem *port_regs =
280 qdev->mem_map_registers;
5a4faa87
RM		 281
282 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
283 (ISP_IMR_ENABLE_INT << 16));
284
285}
286
287static void ql_enable_interrupts(struct ql3_adapter *qdev)
288{
d7f61777
JP		 289 struct ql3xxx_port_registers __iomem *port_regs =
290 qdev->mem_map_registers;
5a4faa87
RM		 291
292 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
293 ((0xff << 16) | ISP_IMR_ENABLE_INT));
294
295}
296
297static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev,
298 struct ql_rcv_buf_cb *lrg_buf_cb)
299{
0f8ab89e
BL		 300 dma_addr_t map;
301 int err;
5a4faa87
RM		 302 lrg_buf_cb->next = NULL;
303
304 if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */
305 qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb;
306 } else {
307 qdev->lrg_buf_free_tail->next = lrg_buf_cb;
308 qdev->lrg_buf_free_tail = lrg_buf_cb;
309 }
310
311 if (!lrg_buf_cb->skb) {
cd238faa
BL		 312 lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev,
313 qdev->lrg_buffer_len);
5a4faa87 314 if (unlikely(!lrg_buf_cb->skb)) {
eddc5fbd 315 netdev_err(qdev->ndev, "failed netdev_alloc_skb()\n");
5a4faa87
RM		 316 qdev->lrg_buf_skb_check++;
317 } else {
318 /*
319 * We save some space to copy the ethhdr from first
320 * buffer
321 */
322 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
323 map = pci_map_single(qdev->pdev,
324 lrg_buf_cb->skb->data,
325 qdev->lrg_buffer_len -
326 QL_HEADER_SPACE,
327 PCI_DMA_FROMDEVICE);
8d8bb39b 328 err = pci_dma_mapping_error(qdev->pdev, map);
d7f61777 329 if (err) {
eddc5fbd
JP		 330 netdev_err(qdev->ndev,
331 "PCI mapping failed with error: %d\n",
332 err);
0f8ab89e
BL		 333 dev_kfree_skb(lrg_buf_cb->skb);
334 lrg_buf_cb->skb = NULL;
335
336 qdev->lrg_buf_skb_check++;
337 return;
338 }
339
5a4faa87
RM		 340 lrg_buf_cb->buf_phy_addr_low =
341 cpu_to_le32(LS_64BITS(map));
342 lrg_buf_cb->buf_phy_addr_high =
343 cpu_to_le32(MS_64BITS(map));
87196eb7
FT		 344 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
345 dma_unmap_len_set(lrg_buf_cb, maplen,
5a4faa87
RM		 346 qdev->lrg_buffer_len -
347 QL_HEADER_SPACE);
348 }
349 }
350
351 qdev->lrg_buf_free_count++;
352}
353
354static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter
355 *qdev)
356{
d7f61777 357 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
5a4faa87 358
d7f61777
JP		 359 if (lrg_buf_cb != NULL) {
360 qdev->lrg_buf_free_head = lrg_buf_cb->next;
361 if (qdev->lrg_buf_free_head == NULL)
5a4faa87
RM		 362 qdev->lrg_buf_free_tail = NULL;
363 qdev->lrg_buf_free_count--;
364 }
365
366 return lrg_buf_cb;
367}
368
369static u32 addrBits = EEPROM_NO_ADDR_BITS;
370static u32 dataBits = EEPROM_NO_DATA_BITS;
371
372static void fm93c56a_deselect(struct ql3_adapter *qdev);
373static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr,
374 unsigned short *value);
375
376/*
377 * Caller holds hw_lock.
378 */
379static void fm93c56a_select(struct ql3_adapter *qdev)
380{
381 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 382 qdev->mem_map_registers;
6f2e154b 383 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
5a4faa87
RM		 384
385 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
d7f61777
JP		 386 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
387 ql_write_nvram_reg(qdev, spir,
388 ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
5a4faa87
RM		 389}
390
391/*
392 * Caller holds hw_lock.
393 */
394static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr)
395{
396 int i;
397 u32 mask;
398 u32 dataBit;
399 u32 previousBit;
400 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 401 qdev->mem_map_registers;
6f2e154b 402 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
5a4faa87
RM		 403
404 /* Clock in a zero, then do the start bit */
d7f61777
JP		 405 ql_write_nvram_reg(qdev, spir,
406 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
407 AUBURN_EEPROM_DO_1));
408 ql_write_nvram_reg(qdev, spir,
409 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
410 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_RISE));
411 ql_write_nvram_reg(qdev, spir,
412 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
413 AUBURN_EEPROM_DO_1 | AUBURN_EEPROM_CLK_FALL));
5a4faa87
RM		 414
415 mask = 1 << (FM93C56A_CMD_BITS - 1);
416 /* Force the previous data bit to be different */
417 previousBit = 0xffff;
418 for (i = 0; i < FM93C56A_CMD_BITS; i++) {
d7f61777
JP		 419 dataBit = (cmd & mask)
420 ? AUBURN_EEPROM_DO_1
421 : AUBURN_EEPROM_DO_0;
5a4faa87 422 if (previousBit != dataBit) {
d7f61777
JP		 423 /* If the bit changed, change the DO state to match */
424 ql_write_nvram_reg(qdev, spir,
425 (ISP_NVRAM_MASK |
426 qdev->eeprom_cmd_data | dataBit));
5a4faa87
RM		 427 previousBit = dataBit;
428 }
d7f61777
JP		 429 ql_write_nvram_reg(qdev, spir,
430 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
431 dataBit | AUBURN_EEPROM_CLK_RISE));
432 ql_write_nvram_reg(qdev, spir,
433 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
434 dataBit | AUBURN_EEPROM_CLK_FALL));
5a4faa87
RM		 435 cmd = cmd << 1;
436 }
437
438 mask = 1 << (addrBits - 1);
439 /* Force the previous data bit to be different */
440 previousBit = 0xffff;
441 for (i = 0; i < addrBits; i++) {
d7f61777
JP		 442 dataBit = (eepromAddr & mask) ? AUBURN_EEPROM_DO_1
443 : AUBURN_EEPROM_DO_0;
5a4faa87
RM		 444 if (previousBit != dataBit) {
445 /*
446 * If the bit changed, then change the DO state to
447 * match
448 */
d7f61777
JP		 449 ql_write_nvram_reg(qdev, spir,
450 (ISP_NVRAM_MASK |
451 qdev->eeprom_cmd_data | dataBit));
5a4faa87
RM		 452 previousBit = dataBit;
453 }
d7f61777
JP		 454 ql_write_nvram_reg(qdev, spir,
455 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
456 dataBit | AUBURN_EEPROM_CLK_RISE));
457 ql_write_nvram_reg(qdev, spir,
458 (ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
459 dataBit | AUBURN_EEPROM_CLK_FALL));
5a4faa87
RM		 460 eepromAddr = eepromAddr << 1;
461 }
462}
463
464/*
465 * Caller holds hw_lock.
466 */
467static void fm93c56a_deselect(struct ql3_adapter *qdev)
468{
469 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 470 qdev->mem_map_registers;
6f2e154b 471 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
d7f61777 472
5a4faa87 473 qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
d7f61777 474 ql_write_nvram_reg(qdev, spir, ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
5a4faa87
RM		 475}
476
477/*
478 * Caller holds hw_lock.
479 */
480static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
481{
482 int i;
483 u32 data = 0;
484 u32 dataBit;
485 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 486 qdev->mem_map_registers;
6f2e154b 487 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
5a4faa87
RM		 488
489 /* Read the data bits */
490 /* The first bit is a dummy. Clock right over it. */
491 for (i = 0; i < dataBits; i++) {
d7f61777
JP		 492 ql_write_nvram_reg(qdev, spir,
493 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
494 AUBURN_EEPROM_CLK_RISE);
495 ql_write_nvram_reg(qdev, spir,
496 ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
497 AUBURN_EEPROM_CLK_FALL);
498 dataBit = (ql_read_common_reg(qdev, spir) &
499 AUBURN_EEPROM_DI_1) ? 1 : 0;
5a4faa87
RM		 500 data = (data << 1) | dataBit;
501 }
d7f61777 502 *value = (u16)data;
5a4faa87
RM		 503}
504
505/*
506 * Caller holds hw_lock.
507 */
508static void eeprom_readword(struct ql3_adapter *qdev,
509 u32 eepromAddr, unsigned short *value)
510{
511 fm93c56a_select(qdev);
512 fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr);
513 fm93c56a_datain(qdev, value);
514 fm93c56a_deselect(qdev);
515}
516
804d8541
AV		 517static void ql_set_mac_addr(struct net_device *ndev, u16 *addr)
518{
519 __le16 *p = (__le16 *)ndev->dev_addr;
520 p[0] = cpu_to_le16(addr[0]);
521 p[1] = cpu_to_le16(addr[1]);
522 p[2] = cpu_to_le16(addr[2]);
5a4faa87
RM		 523}
524
525static int ql_get_nvram_params(struct ql3_adapter *qdev)
526{
527 u16 *pEEPROMData;
528 u16 checksum = 0;
529 u32 index;
530 unsigned long hw_flags;
531
532 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
533
d7f61777 534 pEEPROMData = (u16 *)&qdev->nvram_data;
5a4faa87 535 qdev->eeprom_cmd_data = 0;
d7f61777 536 if (ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK,
5a4faa87
RM		 537 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
538 2) << 10)) {
eddc5fbd 539 pr_err("%s: Failed ql_sem_spinlock()\n", __func__);
5a4faa87
RM		 540 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
541 return -1;
542 }
543
544 for (index = 0; index < EEPROM_SIZE; index++) {
545 eeprom_readword(qdev, index, pEEPROMData);
546 checksum += *pEEPROMData;
547 pEEPROMData++;
548 }
549 ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK);
550
551 if (checksum != 0) {
eddc5fbd
JP		 552 netdev_err(qdev->ndev, "checksum should be zero, is %x!!\n",
553 checksum);
5a4faa87
RM		 554 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
555 return -1;
556 }
557
5a4faa87
RM		 558 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
559 return checksum;
560}
561
562static const u32 PHYAddr[2] = {
563 PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS
564};
565
566static int ql_wait_for_mii_ready(struct ql3_adapter *qdev)
567{
568 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 569 qdev->mem_map_registers;
5a4faa87
RM		 570 u32 temp;
571 int count = 1000;
572
573 while (count) {
574 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
575 if (!(temp & MAC_MII_STATUS_BSY))
576 return 0;
577 udelay(10);
578 count--;
579 }
580 return -1;
581}
582
583static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev)
584{
585 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 586 qdev->mem_map_registers;
5a4faa87
RM		 587 u32 scanControl;
588
589 if (qdev->numPorts > 1) {
590 /* Auto scan will cycle through multiple ports */
591 scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC;
592 } else {
593 scanControl = MAC_MII_CONTROL_SC;
594 }
595
596 /*
597 * Scan register 1 of PHY/PETBI,
598 * Set up to scan both devices
599 * The autoscan starts from the first register, completes
600 * the last one before rolling over to the first
601 */
602 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
603 PHYAddr[0] | MII_SCAN_REGISTER);
604
605 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
606 (scanControl) |
607 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16));
608}
609
610static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev)
611{
612 u8 ret;
613 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 614 qdev->mem_map_registers;
5a4faa87
RM		 615
616 /* See if scan mode is enabled before we turn it off */
617 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
618 (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) {
619 /* Scan is enabled */
620 ret = 1;
621 } else {
622 /* Scan is disabled */
623 ret = 0;
624 }
625
626 /*
627 * When disabling scan mode you must first change the MII register
628 * address
629 */
630 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
631 PHYAddr[0] | MII_SCAN_REGISTER);
632
633 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
634 ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS |
635 MAC_MII_CONTROL_RC) << 16));
636
637 return ret;
638}
639
640static int ql_mii_write_reg_ex(struct ql3_adapter *qdev,
3efedf2e 641 u16 regAddr, u16 value, u32 phyAddr)
5a4faa87
RM		 642{
643 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 644 qdev->mem_map_registers;
5a4faa87
RM		 645 u8 scanWasEnabled;
646
647 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
648
649 if (ql_wait_for_mii_ready(qdev)) {
eddc5fbd 650 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
5a4faa87
RM		 651 return -1;
652 }
653
654 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
3efedf2e 655 phyAddr | regAddr);
5a4faa87
RM		 656
657 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
658
659 /* Wait for write to complete 9/10/04 SJP */
660 if (ql_wait_for_mii_ready(qdev)) {
eddc5fbd 661 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
5a4faa87
RM		 662 return -1;
663 }
664
665 if (scanWasEnabled)
666 ql_mii_enable_scan_mode(qdev);
667
668 return 0;
669}
670
671static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr,
d7f61777 672 u16 *value, u32 phyAddr)
5a4faa87
RM		 673{
674 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 675 qdev->mem_map_registers;
5a4faa87
RM		 676 u8 scanWasEnabled;
677 u32 temp;
678
679 scanWasEnabled = ql_mii_disable_scan_mode(qdev);
680
681 if (ql_wait_for_mii_ready(qdev)) {
eddc5fbd 682 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
5a4faa87
RM		 683 return -1;
684 }
685
686 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
3efedf2e 687 phyAddr | regAddr);
5a4faa87
RM		 688
689 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
690 (MAC_MII_CONTROL_RC << 16));
691
692 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
693 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
694
695 /* Wait for the read to complete */
696 if (ql_wait_for_mii_ready(qdev)) {
eddc5fbd 697 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
5a4faa87
RM		 698 return -1;
699 }
700
701 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
702 *value = (u16) temp;
703
704 if (scanWasEnabled)
705 ql_mii_enable_scan_mode(qdev);
706
707 return 0;
708}
709
710static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
711{
712 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 713 qdev->mem_map_registers;
5a4faa87
RM		 714
715 ql_mii_disable_scan_mode(qdev);
716
717 if (ql_wait_for_mii_ready(qdev)) {
eddc5fbd 718 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
5a4faa87
RM		 719 return -1;
720 }
721
722 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
723 qdev->PHYAddr | regAddr);
724
725 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
726
727 /* Wait for write to complete. */
728 if (ql_wait_for_mii_ready(qdev)) {
eddc5fbd 729 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
5a4faa87
RM		 730 return -1;
731 }
732
733 ql_mii_enable_scan_mode(qdev);
734
735 return 0;
736}
737
738static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
739{
740 u32 temp;
741 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 742 qdev->mem_map_registers;
5a4faa87
RM		 743
744 ql_mii_disable_scan_mode(qdev);
745
746 if (ql_wait_for_mii_ready(qdev)) {
eddc5fbd 747 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
5a4faa87
RM		 748 return -1;
749 }
750
751 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
752 qdev->PHYAddr | regAddr);
753
754 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
755 (MAC_MII_CONTROL_RC << 16));
756
757 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
758 (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC);
759
760 /* Wait for the read to complete */
761 if (ql_wait_for_mii_ready(qdev)) {
eddc5fbd 762 netif_warn(qdev, link, qdev->ndev, TIMED_OUT_MSG);
5a4faa87
RM		 763 return -1;
764 }
765
766 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
767 *value = (u16) temp;
768
769 ql_mii_enable_scan_mode(qdev);
770
771 return 0;
772}
773
774static void ql_petbi_reset(struct ql3_adapter *qdev)
775{
776 ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET);
777}
778
779static void ql_petbi_start_neg(struct ql3_adapter *qdev)
780{
781 u16 reg;
782
783 /* Enable Auto-negotiation sense */
784 ql_mii_read_reg(qdev, PETBI_TBI_CTRL, &reg);
785 reg |= PETBI_TBI_AUTO_SENSE;
786 ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg);
787
788 ql_mii_write_reg(qdev, PETBI_NEG_ADVER,
789 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX);
790
791 ql_mii_write_reg(qdev, PETBI_CONTROL_REG,
792 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
793 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000);
794
795}
796
3efedf2e 797static void ql_petbi_reset_ex(struct ql3_adapter *qdev)
5a4faa87
RM		 798{
799 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET,
3efedf2e 800 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 801}
802
3efedf2e 803static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev)
5a4faa87
RM		 804{
805 u16 reg;
806
807 /* Enable Auto-negotiation sense */
9ddf7774 808 ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, &reg,
3efedf2e 809 PHYAddr[qdev->mac_index]);
5a4faa87 810 reg |= PETBI_TBI_AUTO_SENSE;
9ddf7774 811 ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg,
3efedf2e 812 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 813
814 ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER,
9ddf7774 815 PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX,
3efedf2e 816 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 817
818 ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG,
819 PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG |
820 PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000,
3efedf2e 821 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 822}
823
824static void ql_petbi_init(struct ql3_adapter *qdev)
825{
826 ql_petbi_reset(qdev);
827 ql_petbi_start_neg(qdev);
828}
829
3efedf2e 830static void ql_petbi_init_ex(struct ql3_adapter *qdev)
5a4faa87 831{
3efedf2e
RM		 832 ql_petbi_reset_ex(qdev);
833 ql_petbi_start_neg_ex(qdev);
5a4faa87
RM		 834}
835
836static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev)
837{
838 u16 reg;
839
840 if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, &reg) < 0)
841 return 0;
842
843 return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE;
844}
845
3efedf2e
RM		 846static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr)
847{
eddc5fbd 848 netdev_info(qdev->ndev, "enabling Agere specific PHY\n");
3efedf2e
RM		 849 /* power down device bit 11 = 1 */
850 ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr);
851 /* enable diagnostic mode bit 2 = 1 */
852 ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr);
853 /* 1000MB amplitude adjust (see Agere errata) */
854 ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr);
855 /* 1000MB amplitude adjust (see Agere errata) */
856 ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr);
857 /* 100MB amplitude adjust (see Agere errata) */
858 ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr);
859 /* 100MB amplitude adjust (see Agere errata) */
860 ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr);
861 /* 10MB amplitude adjust (see Agere errata) */
862 ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr);
863 /* 10MB amplitude adjust (see Agere errata) */
864 ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr);
865 /* point to hidden reg 0x2806 */
866 ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr);
867 /* Write new PHYAD w/bit 5 set */
d7f61777
JP		 868 ql_mii_write_reg_ex(qdev, 0x11,
869 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr);
9ddf7774 870 /*
3efedf2e
RM		 871 * Disable diagnostic mode bit 2 = 0
872 * Power up device bit 11 = 0
873 * Link up (on) and activity (blink)
874 */
875 ql_mii_write_reg(qdev, 0x12, 0x840a);
876 ql_mii_write_reg(qdev, 0x00, 0x1140);
877 ql_mii_write_reg(qdev, 0x1c, 0xfaf0);
878}
879
d7f61777
JP		 880static enum PHY_DEVICE_TYPE getPhyType(struct ql3_adapter *qdev,
881 u16 phyIdReg0, u16 phyIdReg1)
3efedf2e 882{
d7f61777 883 enum PHY_DEVICE_TYPE result = PHY_TYPE_UNKNOWN;
9ddf7774 884 u32 oui;
3efedf2e 885 u16 model;
9ddf7774 886 int i;
3efedf2e 887
d7f61777 888 if (phyIdReg0 == 0xffff)
3efedf2e 889 return result;
9ddf7774 890
d7f61777 891 if (phyIdReg1 == 0xffff)
3efedf2e 892 return result;
3efedf2e
RM		 893
894 /* oui is split between two registers */
895 oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10);
896
897 model = (phyIdReg1 & PHY_MODEL_MASK) >> 4;
898
899 /* Scan table for this PHY */
d7f61777 900 for (i = 0; i < MAX_PHY_DEV_TYPES; i++) {
eddc5fbd
JP		 901 if ((oui == PHY_DEVICES[i].phyIdOUI) &&
902 (model == PHY_DEVICES[i].phyIdModel)) {
eddc5fbd
JP		 903 netdev_info(qdev->ndev, "Phy: %s\n",
904 PHY_DEVICES[i].name);
d7f61777
JP		 905 result = PHY_DEVICES[i].phyDevice;
906 break;
3efedf2e
RM		 907 }
908 }
909
910 return result;
911}
912
5a4faa87
RM		 913static int ql_phy_get_speed(struct ql3_adapter *qdev)
914{
915 u16 reg;
916
d7f61777
JP		 917 switch (qdev->phyType) {
918 case PHY_AGERE_ET1011C: {
3efedf2e
RM		 919 if (ql_mii_read_reg(qdev, 0x1A, &reg) < 0)
920 return 0;
921
922 reg = (reg >> 8) & 3;
923 break;
924 }
925 default:
d7f61777
JP		 926 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
927 return 0;
5a4faa87 928
d7f61777 929 reg = (((reg & 0x18) >> 3) & 3);
3efedf2e 930 }
5a4faa87 931
d7f61777
JP		 932 switch (reg) {
933 case 2:
5a4faa87 934 return SPEED_1000;
d7f61777 935 case 1:
5a4faa87 936 return SPEED_100;
d7f61777 937 case 0:
5a4faa87 938 return SPEED_10;
d7f61777 939 default:
5a4faa87 940 return -1;
3efedf2e 941 }
5a4faa87
RM		 942}
943
944static int ql_is_full_dup(struct ql3_adapter *qdev)
945{
946 u16 reg;
947
d7f61777
JP		 948 switch (qdev->phyType) {
949 case PHY_AGERE_ET1011C: {
3efedf2e
RM		 950 if (ql_mii_read_reg(qdev, 0x1A, &reg))
951 return 0;
9ddf7774 952
3efedf2e
RM		 953 return ((reg & 0x0080) && (reg & 0x1000)) != 0;
954 }
955 case PHY_VITESSE_VSC8211:
d7f61777 956 default: {
3efedf2e
RM		 957 if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, &reg) < 0)
958 return 0;
959 return (reg & PHY_AUX_DUPLEX_STAT) != 0;
960 }
961 }
5a4faa87
RM		 962}
963
964static int ql_is_phy_neg_pause(struct ql3_adapter *qdev)
965{
966 u16 reg;
967
968 if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, &reg) < 0)
969 return 0;
970
971 return (reg & PHY_NEG_PAUSE) != 0;
972}
973
3efedf2e
RM		 974static int PHY_Setup(struct ql3_adapter *qdev)
975{
976 u16 reg1;
977 u16 reg2;
978 bool agereAddrChangeNeeded = false;
979 u32 miiAddr = 0;
980 int err;
981
982 /* Determine the PHY we are using by reading the ID's */
983 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1);
d7f61777 984 if (err != 0) {
eddc5fbd 985 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_0_REG\n");
d7f61777 986 return err;
3efedf2e
RM		 987 }
988
989 err = ql_mii_read_reg(qdev, PHY_ID_1_REG, &reg2);
d7f61777 990 if (err != 0) {
eddc5fbd 991 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG\n");
d7f61777 992 return err;
3efedf2e
RM		 993 }
994
995 /* Check if we have a Agere PHY */
996 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
997
9ddf7774 998 /* Determine which MII address we should be using
3efedf2e 999 determined by the index of the card */
d7f61777 1000 if (qdev->mac_index == 0)
3efedf2e 1001 miiAddr = MII_AGERE_ADDR_1;
d7f61777 1002 else
3efedf2e 1003 miiAddr = MII_AGERE_ADDR_2;
9ddf7774 1004
d7f61777
JP		 1005 err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr);
1006 if (err != 0) {
eddc5fbd
JP		 1007 netdev_err(qdev->ndev,
1008 "Could not read from reg PHY_ID_0_REG after Agere detected\n");
9ddf7774 1009 return err;
3efedf2e
RM		 1010 }
1011
1012 err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, &reg2, miiAddr);
d7f61777 1013 if (err != 0) {
eddc5fbd 1014 netdev_err(qdev->ndev, "Could not read from reg PHY_ID_1_REG after Agere detected\n");
d7f61777 1015 return err;
3efedf2e 1016 }
9ddf7774 1017
3efedf2e 1018 /* We need to remember to initialize the Agere PHY */
9ddf7774 1019 agereAddrChangeNeeded = true;
3efedf2e
RM		 1020 }
1021
1022 /* Determine the particular PHY we have on board to apply
1023 PHY specific initializations */
1024 qdev->phyType = getPhyType(qdev, reg1, reg2);
1025
1026 if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) {
1027 /* need this here so address gets changed */
9ddf7774 1028 phyAgereSpecificInit(qdev, miiAddr);
3efedf2e 1029 } else if (qdev->phyType == PHY_TYPE_UNKNOWN) {
eddc5fbd 1030 netdev_err(qdev->ndev, "PHY is unknown\n");
3efedf2e
RM		 1031 return -EIO;
1032 }
1033
1034 return 0;
1035}
1036
5a4faa87
RM		 1037/*
1038 * Caller holds hw_lock.
1039 */
1040static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable)
1041{
1042 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1043 qdev->mem_map_registers;
5a4faa87
RM		 1044 u32 value;
1045
1046 if (enable)
1047 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1048 else
1049 value = (MAC_CONFIG_REG_PE << 16);
1050
1051 if (qdev->mac_index)
1052 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1053 else
1054 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1055}
1056
1057/*
1058 * Caller holds hw_lock.
1059 */
1060static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable)
1061{
1062 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1063 qdev->mem_map_registers;
5a4faa87
RM		 1064 u32 value;
1065
1066 if (enable)
1067 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1068 else
1069 value = (MAC_CONFIG_REG_SR << 16);
1070
1071 if (qdev->mac_index)
1072 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1073 else
1074 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1075}
1076
1077/*
1078 * Caller holds hw_lock.
1079 */
1080static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable)
1081{
1082 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1083 qdev->mem_map_registers;
5a4faa87
RM		 1084 u32 value;
1085
1086 if (enable)
1087 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1088 else
1089 value = (MAC_CONFIG_REG_GM << 16);
1090
1091 if (qdev->mac_index)
1092 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1093 else
1094 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1095}
1096
1097/*
1098 * Caller holds hw_lock.
1099 */
1100static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable)
1101{
1102 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1103 qdev->mem_map_registers;
5a4faa87
RM		 1104 u32 value;
1105
1106 if (enable)
1107 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1108 else
1109 value = (MAC_CONFIG_REG_FD << 16);
1110
1111 if (qdev->mac_index)
1112 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1113 else
1114 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1115}
1116
1117/*
1118 * Caller holds hw_lock.
1119 */
1120static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable)
1121{
1122 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1123 qdev->mem_map_registers;
5a4faa87
RM		 1124 u32 value;
1125
1126 if (enable)
1127 value =
1128 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) |
1129 ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16));
1130 else
1131 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1132
1133 if (qdev->mac_index)
1134 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1135 else
1136 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1137}
1138
1139/*
1140 * Caller holds hw_lock.
1141 */
1142static int ql_is_fiber(struct ql3_adapter *qdev)
1143{
1144 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1145 qdev->mem_map_registers;
5a4faa87
RM		 1146 u32 bitToCheck = 0;
1147 u32 temp;
1148
1149 switch (qdev->mac_index) {
1150 case 0:
1151 bitToCheck = PORT_STATUS_SM0;
1152 break;
1153 case 1:
1154 bitToCheck = PORT_STATUS_SM1;
1155 break;
1156 }
1157
1158 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1159 return (temp & bitToCheck) != 0;
1160}
1161
1162static int ql_is_auto_cfg(struct ql3_adapter *qdev)
1163{
1164 u16 reg;
1165 ql_mii_read_reg(qdev, 0x00, &reg);
1166 return (reg & 0x1000) != 0;
1167}
1168
1169/*
1170 * Caller holds hw_lock.
1171 */
1172static int ql_is_auto_neg_complete(struct ql3_adapter *qdev)
1173{
1174 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1175 qdev->mem_map_registers;
5a4faa87
RM		 1176 u32 bitToCheck = 0;
1177 u32 temp;
1178
1179 switch (qdev->mac_index) {
1180 case 0:
1181 bitToCheck = PORT_STATUS_AC0;
1182 break;
1183 case 1:
1184 bitToCheck = PORT_STATUS_AC1;
1185 break;
1186 }
1187
1188 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1189 if (temp & bitToCheck) {
eddc5fbd 1190 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate complete\n");
5a4faa87 1191 return 1;
5a4faa87 1192 }
eddc5fbd
JP		 1193 netif_info(qdev, link, qdev->ndev, "Auto-Negotiate incomplete\n");
1194 return 0;
5a4faa87
RM		 1195}
1196
1197/*
1198 * ql_is_neg_pause() returns 1 if pause was negotiated to be on
1199 */
1200static int ql_is_neg_pause(struct ql3_adapter *qdev)
1201{
1202 if (ql_is_fiber(qdev))
1203 return ql_is_petbi_neg_pause(qdev);
1204 else
1205 return ql_is_phy_neg_pause(qdev);
1206}
1207
1208static int ql_auto_neg_error(struct ql3_adapter *qdev)
1209{
1210 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1211 qdev->mem_map_registers;
5a4faa87
RM		 1212 u32 bitToCheck = 0;
1213 u32 temp;
1214
1215 switch (qdev->mac_index) {
1216 case 0:
1217 bitToCheck = PORT_STATUS_AE0;
1218 break;
1219 case 1:
1220 bitToCheck = PORT_STATUS_AE1;
1221 break;
1222 }
1223 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1224 return (temp & bitToCheck) != 0;
1225}
1226
1227static u32 ql_get_link_speed(struct ql3_adapter *qdev)
1228{
1229 if (ql_is_fiber(qdev))
1230 return SPEED_1000;
1231 else
1232 return ql_phy_get_speed(qdev);
1233}
1234
1235static int ql_is_link_full_dup(struct ql3_adapter *qdev)
1236{
1237 if (ql_is_fiber(qdev))
1238 return 1;
1239 else
1240 return ql_is_full_dup(qdev);
1241}
1242
1243/*
1244 * Caller holds hw_lock.
1245 */
1246static int ql_link_down_detect(struct ql3_adapter *qdev)
1247{
1248 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1249 qdev->mem_map_registers;
5a4faa87
RM		 1250 u32 bitToCheck = 0;
1251 u32 temp;
1252
1253 switch (qdev->mac_index) {
1254 case 0:
1255 bitToCheck = ISP_CONTROL_LINK_DN_0;
1256 break;
1257 case 1:
1258 bitToCheck = ISP_CONTROL_LINK_DN_1;
1259 break;
1260 }
1261
1262 temp =
1263 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1264 return (temp & bitToCheck) != 0;
1265}
1266
1267/*
1268 * Caller holds hw_lock.
1269 */
1270static int ql_link_down_detect_clear(struct ql3_adapter *qdev)
1271{
1272 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1273 qdev->mem_map_registers;
5a4faa87
RM		 1274
1275 switch (qdev->mac_index) {
1276 case 0:
1277 ql_write_common_reg(qdev,
1278 &port_regs->CommonRegs.ispControlStatus,
1279 (ISP_CONTROL_LINK_DN_0) |
1280 (ISP_CONTROL_LINK_DN_0 << 16));
1281 break;
1282
1283 case 1:
1284 ql_write_common_reg(qdev,
1285 &port_regs->CommonRegs.ispControlStatus,
1286 (ISP_CONTROL_LINK_DN_1) |
1287 (ISP_CONTROL_LINK_DN_1 << 16));
1288 break;
1289
1290 default:
1291 return 1;
1292 }
1293
1294 return 0;
1295}
1296
1297/*
1298 * Caller holds hw_lock.
1299 */
3efedf2e 1300static int ql_this_adapter_controls_port(struct ql3_adapter *qdev)
5a4faa87
RM		 1301{
1302 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1303 qdev->mem_map_registers;
5a4faa87
RM		 1304 u32 bitToCheck = 0;
1305 u32 temp;
1306
3efedf2e 1307 switch (qdev->mac_index) {
5a4faa87
RM		 1308 case 0:
1309 bitToCheck = PORT_STATUS_F1_ENABLED;
1310 break;
1311 case 1:
1312 bitToCheck = PORT_STATUS_F3_ENABLED;
1313 break;
1314 default:
1315 break;
1316 }
1317
1318 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1319 if (temp & bitToCheck) {
eddc5fbd
JP		 1320 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1321 "not link master\n");
5a4faa87 1322 return 0;
5a4faa87 1323 }
eddc5fbd
JP		 1324
1325 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev, "link master\n");
1326 return 1;
5a4faa87
RM		 1327}
1328
3efedf2e 1329static void ql_phy_reset_ex(struct ql3_adapter *qdev)
5a4faa87 1330{
9ddf7774 1331 ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET,
3efedf2e 1332 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 1333}
1334
3efedf2e 1335static void ql_phy_start_neg_ex(struct ql3_adapter *qdev)
5a4faa87
RM		 1336{
1337 u16 reg;
3efedf2e
RM		 1338 u16 portConfiguration;
1339
d7f61777 1340 if (qdev->phyType == PHY_AGERE_ET1011C)
9ddf7774 1341 ql_mii_write_reg(qdev, 0x13, 0x0000);
d7f61777 1342 /* turn off external loopback */
5a4faa87 1343
d7f61777
JP		 1344 if (qdev->mac_index == 0)
1345 portConfiguration =
1346 qdev->nvram_data.macCfg_port0.portConfiguration;
3efedf2e 1347 else
d7f61777
JP		 1348 portConfiguration =
1349 qdev->nvram_data.macCfg_port1.portConfiguration;
3efedf2e
RM		 1350
1351 /* Some HBA's in the field are set to 0 and they need to
1352 be reinterpreted with a default value */
d7f61777 1353 if (portConfiguration == 0)
3efedf2e
RM		 1354 portConfiguration = PORT_CONFIG_DEFAULT;
1355
1356 /* Set the 1000 advertisements */
9ddf7774 1357 ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, &reg,
3efedf2e
RM		 1358 PHYAddr[qdev->mac_index]);
1359 reg &= ~PHY_GIG_ALL_PARAMS;
1360
d7f61777
JP		 1361 if (portConfiguration & PORT_CONFIG_1000MB_SPEED) {
1362 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
ad4c9a09 1363 reg |= PHY_GIG_ADV_1000F;
7d2e3cb7 1364 else
ad4c9a09 1365 reg |= PHY_GIG_ADV_1000H;
3efedf2e
RM		 1366 }
1367
9ddf7774 1368 ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg,
3efedf2e
RM		 1369 PHYAddr[qdev->mac_index]);
1370
1371 /* Set the 10/100 & pause negotiation advertisements */
1372 ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, &reg,
1373 PHYAddr[qdev->mac_index]);
1374 reg &= ~PHY_NEG_ALL_PARAMS;
1375
d7f61777 1376 if (portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED)
3efedf2e
RM		 1377 reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE;
1378
d7f61777
JP		 1379 if (portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) {
1380 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
3efedf2e 1381 reg |= PHY_NEG_ADV_100F;
9ddf7774 1382
d7f61777 1383 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
3efedf2e
RM		 1384 reg |= PHY_NEG_ADV_10F;
1385 }
1386
d7f61777
JP		 1387 if (portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) {
1388 if (portConfiguration & PORT_CONFIG_100MB_SPEED)
3efedf2e 1389 reg |= PHY_NEG_ADV_100H;
9ddf7774 1390
d7f61777 1391 if (portConfiguration & PORT_CONFIG_10MB_SPEED)
3efedf2e
RM		 1392 reg |= PHY_NEG_ADV_10H;
1393 }
1394
d7f61777 1395 if (portConfiguration & PORT_CONFIG_1000MB_SPEED)
9ddf7774 1396 reg |= 1;
3efedf2e 1397
9ddf7774 1398 ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg,
3efedf2e 1399 PHYAddr[qdev->mac_index]);
5a4faa87 1400
3efedf2e 1401 ql_mii_read_reg_ex(qdev, CONTROL_REG, &reg, PHYAddr[qdev->mac_index]);
9ddf7774
JG		 1402
1403 ql_mii_write_reg_ex(qdev, CONTROL_REG,
3efedf2e
RM		 1404 reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG,
1405 PHYAddr[qdev->mac_index]);
5a4faa87
RM		 1406}
1407
3efedf2e 1408static void ql_phy_init_ex(struct ql3_adapter *qdev)
5a4faa87 1409{
3efedf2e
RM		 1410 ql_phy_reset_ex(qdev);
1411 PHY_Setup(qdev);
1412 ql_phy_start_neg_ex(qdev);
5a4faa87
RM		 1413}
1414
1415/*
1416 * Caller holds hw_lock.
1417 */
1418static u32 ql_get_link_state(struct ql3_adapter *qdev)
1419{
1420 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1421 qdev->mem_map_registers;
5a4faa87
RM		 1422 u32 bitToCheck = 0;
1423 u32 temp, linkState;
1424
1425 switch (qdev->mac_index) {
1426 case 0:
1427 bitToCheck = PORT_STATUS_UP0;
1428 break;
1429 case 1:
1430 bitToCheck = PORT_STATUS_UP1;
1431 break;
1432 }
d7f61777 1433
5a4faa87 1434 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
d7f61777 1435 if (temp & bitToCheck)
5a4faa87 1436 linkState = LS_UP;
d7f61777 1437 else
5a4faa87 1438 linkState = LS_DOWN;
d7f61777 1439
5a4faa87
RM		 1440 return linkState;
1441}
1442
1443static int ql_port_start(struct ql3_adapter *qdev)
1444{
d7f61777 1445 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
5a4faa87 1446 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3efedf2e 1447 2) << 7)) {
eddc5fbd 1448 netdev_err(qdev->ndev, "Could not get hw lock for GIO\n");
5a4faa87 1449 return -1;
3efedf2e 1450 }
5a4faa87
RM		 1451
1452 if (ql_is_fiber(qdev)) {
1453 ql_petbi_init(qdev);
1454 } else {
1455 /* Copper port */
3efedf2e 1456 ql_phy_init_ex(qdev);
5a4faa87
RM		 1457 }
1458
1459 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1460 return 0;
1461}
1462
1463static int ql_finish_auto_neg(struct ql3_adapter *qdev)
1464{
1465
d7f61777 1466 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
5a4faa87
RM		 1467 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1468 2) << 7))
1469 return -1;
1470
1471 if (!ql_auto_neg_error(qdev)) {
d7f61777 1472 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
5a4faa87 1473 /* configure the MAC */
eddc5fbd
JP		 1474 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1475 "Configuring link\n");
5a4faa87
RM		 1476 ql_mac_cfg_soft_reset(qdev, 1);
1477 ql_mac_cfg_gig(qdev,
1478 (ql_get_link_speed
1479 (qdev) ==
1480 SPEED_1000));
1481 ql_mac_cfg_full_dup(qdev,
1482 ql_is_link_full_dup
1483 (qdev));
1484 ql_mac_cfg_pause(qdev,
1485 ql_is_neg_pause
1486 (qdev));
1487 ql_mac_cfg_soft_reset(qdev, 0);
1488
1489 /* enable the MAC */
eddc5fbd
JP		 1490 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1491 "Enabling mac\n");
5a4faa87
RM		 1492 ql_mac_enable(qdev, 1);
1493 }
1494
5a4faa87
RM		 1495 qdev->port_link_state = LS_UP;
1496 netif_start_queue(qdev->ndev);
1497 netif_carrier_on(qdev->ndev);
eddc5fbd
JP		 1498 netif_info(qdev, link, qdev->ndev,
1499 "Link is up at %d Mbps, %s duplex\n",
1500 ql_get_link_speed(qdev),
1501 ql_is_link_full_dup(qdev) ? "full" : "half");
5a4faa87
RM		 1502
1503 } else { /* Remote error detected */
1504
d7f61777 1505 if (test_bit(QL_LINK_MASTER, &qdev->flags)) {
eddc5fbd
JP		 1506 netif_printk(qdev, link, KERN_DEBUG, qdev->ndev,
1507 "Remote error detected. Calling ql_port_start()\n");
5a4faa87
RM		 1508 /*
1509 * ql_port_start() is shared code and needs
1510 * to lock the PHY on it's own.
1511 */
1512 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
d7f61777 1513 if (ql_port_start(qdev)) /* Restart port */
5a4faa87 1514 return -1;
d7f61777 1515 return 0;
5a4faa87
RM		 1516 }
1517 }
1518 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1519 return 0;
1520}
1521
3e23b7d3 1522static void ql_link_state_machine_work(struct work_struct *work)
5a4faa87 1523{
3e23b7d3
RM		 1524 struct ql3_adapter *qdev =
1525 container_of(work, struct ql3_adapter, link_state_work.work);
1526
5a4faa87
RM		 1527 u32 curr_link_state;
1528 unsigned long hw_flags;
1529
1530 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
1531
1532 curr_link_state = ql_get_link_state(qdev);
1533
d7f61777 1534 if (test_bit(QL_RESET_ACTIVE, &qdev->flags)) {
eddc5fbd
JP		 1535 netif_info(qdev, link, qdev->ndev,
1536 "Reset in progress, skip processing link state\n");
04f10773 1537
9ddf7774 1538 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3e23b7d3
RM		 1539
1540 /* Restart timer on 2 second interval. */
eddc5fbd 1541 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3e23b7d3 1542
5a4faa87
RM		 1543 return;
1544 }
1545
1546 switch (qdev->port_link_state) {
1547 default:
d7f61777 1548 if (test_bit(QL_LINK_MASTER, &qdev->flags))
5a4faa87 1549 ql_port_start(qdev);
5a4faa87
RM		 1550 qdev->port_link_state = LS_DOWN;
1551 /* Fall Through */
1552
1553 case LS_DOWN:
5a4faa87 1554 if (curr_link_state == LS_UP) {
eddc5fbd 1555 netif_info(qdev, link, qdev->ndev, "Link is up\n");
5a4faa87
RM		 1556 if (ql_is_auto_neg_complete(qdev))
1557 ql_finish_auto_neg(qdev);
1558
1559 if (qdev->port_link_state == LS_UP)
1560 ql_link_down_detect_clear(qdev);
1561
0f807044 1562 qdev->port_link_state = LS_UP;
5a4faa87
RM		 1563 }
1564 break;
1565
1566 case LS_UP:
1567 /*
1568 * See if the link is currently down or went down and came
1569 * back up
1570 */
0f807044 1571 if (curr_link_state == LS_DOWN) {
eddc5fbd 1572 netif_info(qdev, link, qdev->ndev, "Link is down\n");
5a4faa87
RM		 1573 qdev->port_link_state = LS_DOWN;
1574 }
0f807044
RM		 1575 if (ql_link_down_detect(qdev))
1576 qdev->port_link_state = LS_DOWN;
5a4faa87
RM		 1577 break;
1578 }
1579 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3e23b7d3
RM		 1580
1581 /* Restart timer on 2 second interval. */
1582 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
5a4faa87
RM		 1583}
1584
1585/*
1586 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1587 */
1588static void ql_get_phy_owner(struct ql3_adapter *qdev)
1589{
3efedf2e 1590 if (ql_this_adapter_controls_port(qdev))
d7f61777 1591 set_bit(QL_LINK_MASTER, &qdev->flags);
5a4faa87 1592 else
d7f61777 1593 clear_bit(QL_LINK_MASTER, &qdev->flags);
5a4faa87
RM		 1594}
1595
1596/*
1597 * Caller must take hw_lock and QL_PHY_GIO_SEM.
1598 */
1599static void ql_init_scan_mode(struct ql3_adapter *qdev)
1600{
1601 ql_mii_enable_scan_mode(qdev);
1602
d7f61777 1603 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
3efedf2e
RM		 1604 if (ql_this_adapter_controls_port(qdev))
1605 ql_petbi_init_ex(qdev);
5a4faa87 1606 } else {
3efedf2e
RM		 1607 if (ql_this_adapter_controls_port(qdev))
1608 ql_phy_init_ex(qdev);
5a4faa87
RM		 1609 }
1610}
1611
1612/*
d7f61777
JP		 1613 * MII_Setup needs to be called before taking the PHY out of reset
1614 * so that the management interface clock speed can be set properly.
1615 * It would be better if we had a way to disable MDC until after the
1616 * PHY is out of reset, but we don't have that capability.
5a4faa87
RM		 1617 */
1618static int ql_mii_setup(struct ql3_adapter *qdev)
1619{
1620 u32 reg;
1621 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 1622 qdev->mem_map_registers;
5a4faa87 1623
d7f61777 1624 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
5a4faa87
RM		 1625 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
1626 2) << 7))
1627 return -1;
1628
bd36b0ac 1629 if (qdev->device_id == QL3032_DEVICE_ID)
9ddf7774 1630 ql_write_page0_reg(qdev,
bd36b0ac
RM		 1631 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1632
5a4faa87
RM		 1633 /* Divide 125MHz clock by 28 to meet PHY timing requirements */
1634 reg = MAC_MII_CONTROL_CLK_SEL_DIV28;
1635
1636 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1637 reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16));
1638
1639 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1640 return 0;
1641}
1642
d7f61777
JP		 1643#define SUPPORTED_OPTICAL_MODES (SUPPORTED_1000baseT_Full | \
1644 SUPPORTED_FIBRE | \
1645 SUPPORTED_Autoneg)
1646#define SUPPORTED_TP_MODES (SUPPORTED_10baseT_Half | \
1647 SUPPORTED_10baseT_Full | \
1648 SUPPORTED_100baseT_Half | \
1649 SUPPORTED_100baseT_Full | \
1650 SUPPORTED_1000baseT_Half | \
1651 SUPPORTED_1000baseT_Full | \
1652 SUPPORTED_Autoneg | \
1653 SUPPORTED_TP); \
1654
5a4faa87
RM		 1655static u32 ql_supported_modes(struct ql3_adapter *qdev)
1656{
d7f61777
JP		 1657 if (test_bit(QL_LINK_OPTICAL, &qdev->flags))
1658 return SUPPORTED_OPTICAL_MODES;
5a4faa87 1659
d7f61777 1660 return SUPPORTED_TP_MODES;
5a4faa87
RM		 1661}
1662
1663static int ql_get_auto_cfg_status(struct ql3_adapter *qdev)
1664{
1665 int status;
1666 unsigned long hw_flags;
1667 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
d7f61777
JP		 1668 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1669 (QL_RESOURCE_BITS_BASE_CODE |
1670 (qdev->mac_index) * 2) << 7)) {
04f10773 1671 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1672 return 0;
04f10773 1673 }
5a4faa87
RM		 1674 status = ql_is_auto_cfg(qdev);
1675 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1676 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1677 return status;
1678}
1679
1680static u32 ql_get_speed(struct ql3_adapter *qdev)
1681{
1682 u32 status;
1683 unsigned long hw_flags;
1684 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
d7f61777
JP		 1685 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1686 (QL_RESOURCE_BITS_BASE_CODE |
1687 (qdev->mac_index) * 2) << 7)) {
04f10773 1688 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1689 return 0;
04f10773 1690 }
5a4faa87
RM		 1691 status = ql_get_link_speed(qdev);
1692 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1693 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1694 return status;
1695}
1696
1697static int ql_get_full_dup(struct ql3_adapter *qdev)
1698{
1699 int status;
1700 unsigned long hw_flags;
1701 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
d7f61777
JP		 1702 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
1703 (QL_RESOURCE_BITS_BASE_CODE |
1704 (qdev->mac_index) * 2) << 7)) {
04f10773 1705 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 1706 return 0;
04f10773 1707 }
5a4faa87
RM		 1708 status = ql_is_link_full_dup(qdev);
1709 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
1710 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
1711 return status;
1712}
1713
5a4faa87
RM		 1714static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd)
1715{
1716 struct ql3_adapter *qdev = netdev_priv(ndev);
1717
1718 ecmd->transceiver = XCVR_INTERNAL;
1719 ecmd->supported = ql_supported_modes(qdev);
1720
d7f61777 1721 if (test_bit(QL_LINK_OPTICAL, &qdev->flags)) {
5a4faa87
RM		 1722 ecmd->port = PORT_FIBRE;
1723 } else {
1724 ecmd->port = PORT_TP;
1725 ecmd->phy_address = qdev->PHYAddr;
1726 }
1727 ecmd->advertising = ql_supported_modes(qdev);
1728 ecmd->autoneg = ql_get_auto_cfg_status(qdev);
70739497 1729 ethtool_cmd_speed_set(ecmd, ql_get_speed(qdev));
5a4faa87
RM		 1730 ecmd->duplex = ql_get_full_dup(qdev);
1731 return 0;
1732}
1733
1734static void ql_get_drvinfo(struct net_device *ndev,
1735 struct ethtool_drvinfo *drvinfo)
1736{
1737 struct ql3_adapter *qdev = netdev_priv(ndev);
1738 strncpy(drvinfo->driver, ql3xxx_driver_name, 32);
1739 strncpy(drvinfo->version, ql3xxx_driver_version, 32);
1740 strncpy(drvinfo->fw_version, "N/A", 32);
1741 strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32);
5a4faa87
RM		 1742 drvinfo->regdump_len = 0;
1743 drvinfo->eedump_len = 0;
1744}
1745
1746static u32 ql_get_msglevel(struct net_device *ndev)
1747{
1748 struct ql3_adapter *qdev = netdev_priv(ndev);
1749 return qdev->msg_enable;
1750}
1751
1752static void ql_set_msglevel(struct net_device *ndev, u32 value)
1753{
1754 struct ql3_adapter *qdev = netdev_priv(ndev);
1755 qdev->msg_enable = value;
1756}
1757
ec826383
RM		 1758static void ql_get_pauseparam(struct net_device *ndev,
1759 struct ethtool_pauseparam *pause)
1760{
1761 struct ql3_adapter *qdev = netdev_priv(ndev);
d7f61777
JP		 1762 struct ql3xxx_port_registers __iomem *port_regs =
1763 qdev->mem_map_registers;
ec826383
RM		 1764
1765 u32 reg;
d7f61777 1766 if (qdev->mac_index == 0)
ec826383
RM		 1767 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1768 else
1769 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1770
1771 pause->autoneg = ql_get_auto_cfg_status(qdev);
1772 pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2;
1773 pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1;
1774}
1775
7282d491 1776static const struct ethtool_ops ql3xxx_ethtool_ops = {
5a4faa87
RM		 1777 .get_settings = ql_get_settings,
1778 .get_drvinfo = ql_get_drvinfo,
5a4faa87
RM		 1779 .get_link = ethtool_op_get_link,
1780 .get_msglevel = ql_get_msglevel,
1781 .set_msglevel = ql_set_msglevel,
ec826383 1782 .get_pauseparam = ql_get_pauseparam,
5a4faa87
RM		 1783};
1784
1785static int ql_populate_free_queue(struct ql3_adapter *qdev)
1786{
1787 struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head;
0f8ab89e
BL		 1788 dma_addr_t map;
1789 int err;
5a4faa87
RM		 1790
1791 while (lrg_buf_cb) {
1792 if (!lrg_buf_cb->skb) {
d7f61777
JP		 1793 lrg_buf_cb->skb =
1794 netdev_alloc_skb(qdev->ndev,
1795 qdev->lrg_buffer_len);
5a4faa87 1796 if (unlikely(!lrg_buf_cb->skb)) {
eddc5fbd
JP		 1797 netdev_printk(KERN_DEBUG, qdev->ndev,
1798 "Failed netdev_alloc_skb()\n");
5a4faa87
RM		 1799 break;
1800 } else {
1801 /*
1802 * We save some space to copy the ethhdr from
1803 * first buffer
1804 */
1805 skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE);
1806 map = pci_map_single(qdev->pdev,
1807 lrg_buf_cb->skb->data,
1808 qdev->lrg_buffer_len -
1809 QL_HEADER_SPACE,
1810 PCI_DMA_FROMDEVICE);
0f8ab89e 1811
8d8bb39b 1812 err = pci_dma_mapping_error(qdev->pdev, map);
d7f61777 1813 if (err) {
eddc5fbd
JP		 1814 netdev_err(qdev->ndev,
1815 "PCI mapping failed with error: %d\n",
1816 err);
0f8ab89e
BL		 1817 dev_kfree_skb(lrg_buf_cb->skb);
1818 lrg_buf_cb->skb = NULL;
1819 break;
1820 }
1821
1822
5a4faa87 1823 lrg_buf_cb->buf_phy_addr_low =
d7f61777 1824 cpu_to_le32(LS_64BITS(map));
5a4faa87 1825 lrg_buf_cb->buf_phy_addr_high =
d7f61777 1826 cpu_to_le32(MS_64BITS(map));
87196eb7
FT		 1827 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
1828 dma_unmap_len_set(lrg_buf_cb, maplen,
5a4faa87
RM		 1829 qdev->lrg_buffer_len -
1830 QL_HEADER_SPACE);
1831 --qdev->lrg_buf_skb_check;
1832 if (!qdev->lrg_buf_skb_check)
1833 return 1;
1834 }
1835 }
1836 lrg_buf_cb = lrg_buf_cb->next;
1837 }
1838 return 0;
1839}
1840
f67cac01
RM		 1841/*
1842 * Caller holds hw_lock.
1843 */
1844static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev)
1845{
d7f61777
JP		 1846 struct ql3xxx_port_registers __iomem *port_regs =
1847 qdev->mem_map_registers;
1848
f67cac01
RM		 1849 if (qdev->small_buf_release_cnt >= 16) {
1850 while (qdev->small_buf_release_cnt >= 16) {
1851 qdev->small_buf_q_producer_index++;
1852
1853 if (qdev->small_buf_q_producer_index ==
1854 NUM_SBUFQ_ENTRIES)
1855 qdev->small_buf_q_producer_index = 0;
1856 qdev->small_buf_release_cnt -= 8;
1857 }
1858 wmb();
1859 writel(qdev->small_buf_q_producer_index,
1860 &port_regs->CommonRegs.rxSmallQProducerIndex);
1861 }
1862}
1863
5a4faa87
RM		 1864/*
1865 * Caller holds hw_lock.
1866 */
1867static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev)
1868{
1869 struct bufq_addr_element *lrg_buf_q_ele;
1870 int i;
1871 struct ql_rcv_buf_cb *lrg_buf_cb;
d7f61777
JP		 1872 struct ql3xxx_port_registers __iomem *port_regs =
1873 qdev->mem_map_registers;
5a4faa87 1874
8e95a202
JP		 1875 if ((qdev->lrg_buf_free_count >= 8) &&
1876 (qdev->lrg_buf_release_cnt >= 16)) {
5a4faa87
RM		 1877
1878 if (qdev->lrg_buf_skb_check)
1879 if (!ql_populate_free_queue(qdev))
1880 return;
1881
1882 lrg_buf_q_ele = qdev->lrg_buf_next_free;
1883
8e95a202
JP		 1884 while ((qdev->lrg_buf_release_cnt >= 16) &&
1885 (qdev->lrg_buf_free_count >= 8)) {
5a4faa87
RM		 1886
1887 for (i = 0; i < 8; i++) {
1888 lrg_buf_cb =
1889 ql_get_from_lrg_buf_free_list(qdev);
1890 lrg_buf_q_ele->addr_high =
1891 lrg_buf_cb->buf_phy_addr_high;
1892 lrg_buf_q_ele->addr_low =
1893 lrg_buf_cb->buf_phy_addr_low;
1894 lrg_buf_q_ele++;
1895
1896 qdev->lrg_buf_release_cnt--;
1897 }
1898
1899 qdev->lrg_buf_q_producer_index++;
1900
d7f61777
JP		 1901 if (qdev->lrg_buf_q_producer_index ==
1902 qdev->num_lbufq_entries)
5a4faa87
RM		 1903 qdev->lrg_buf_q_producer_index = 0;
1904
1905 if (qdev->lrg_buf_q_producer_index ==
1357bfcf 1906 (qdev->num_lbufq_entries - 1)) {
5a4faa87
RM		 1907 lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr;
1908 }
1909 }
f67cac01 1910 wmb();
5a4faa87 1911 qdev->lrg_buf_next_free = lrg_buf_q_ele;
f67cac01
RM		 1912 writel(qdev->lrg_buf_q_producer_index,
1913 &port_regs->CommonRegs.rxLargeQProducerIndex);
5a4faa87
RM		 1914 }
1915}
1916
1917static void ql_process_mac_tx_intr(struct ql3_adapter *qdev,
1918 struct ob_mac_iocb_rsp *mac_rsp)
1919{
1920 struct ql_tx_buf_cb *tx_cb;
bd36b0ac 1921 int i;
e8f4df24 1922 int retval = 0;
5a4faa87 1923
d7f61777 1924 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
eddc5fbd
JP		 1925 netdev_warn(qdev->ndev,
1926 "Frame too short but it was padded and sent\n");
e8f4df24 1927 }
9ddf7774 1928
5a4faa87 1929 tx_cb = &qdev->tx_buf[mac_rsp->transaction_id];
e8f4df24
BL		 1930
1931 /* Check the transmit response flags for any errors */
d7f61777 1932 if (mac_rsp->flags & OB_MAC_IOCB_RSP_S) {
eddc5fbd
JP		 1933 netdev_err(qdev->ndev,
1934 "Frame too short to be legal, frame not sent\n");
e8f4df24 1935
09f75cd7 1936 qdev->ndev->stats.tx_errors++;
e8f4df24
BL		 1937 retval = -EIO;
1938 goto frame_not_sent;
1939 }
1940
d7f61777 1941 if (tx_cb->seg_count == 0) {
eddc5fbd
JP		 1942 netdev_err(qdev->ndev, "tx_cb->seg_count == 0: %d\n",
1943 mac_rsp->transaction_id);
e8f4df24 1944
09f75cd7 1945 qdev->ndev->stats.tx_errors++;
e8f4df24
BL		 1946 retval = -EIO;
1947 goto invalid_seg_count;
1948 }
1949
5a4faa87 1950 pci_unmap_single(qdev->pdev,
87196eb7
FT		 1951 dma_unmap_addr(&tx_cb->map[0], mapaddr),
1952 dma_unmap_len(&tx_cb->map[0], maplen),
bd36b0ac
RM		 1953 PCI_DMA_TODEVICE);
1954 tx_cb->seg_count--;
1955 if (tx_cb->seg_count) {
1956 for (i = 1; i < tx_cb->seg_count; i++) {
1957 pci_unmap_page(qdev->pdev,
87196eb7 1958 dma_unmap_addr(&tx_cb->map[i],
bd36b0ac 1959 mapaddr),
87196eb7 1960 dma_unmap_len(&tx_cb->map[i], maplen),
bd36b0ac
RM		 1961 PCI_DMA_TODEVICE);
1962 }
1963 }
09f75cd7
JG		 1964 qdev->ndev->stats.tx_packets++;
1965 qdev->ndev->stats.tx_bytes += tx_cb->skb->len;
e8f4df24
BL		 1966
1967frame_not_sent:
bd36b0ac 1968 dev_kfree_skb_irq(tx_cb->skb);
5a4faa87 1969 tx_cb->skb = NULL;
e8f4df24
BL		 1970
1971invalid_seg_count:
5a4faa87
RM		 1972 atomic_inc(&qdev->tx_count);
1973}
1974
3664006a 1975static void ql_get_sbuf(struct ql3_adapter *qdev)
97916330
RM		 1976{
1977 if (++qdev->small_buf_index == NUM_SMALL_BUFFERS)
1978 qdev->small_buf_index = 0;
1979 qdev->small_buf_release_cnt++;
1980}
1981
3664006a 1982static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev)
97916330
RM		 1983{
1984 struct ql_rcv_buf_cb *lrg_buf_cb = NULL;
1985 lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index];
1986 qdev->lrg_buf_release_cnt++;
1987 if (++qdev->lrg_buf_index == qdev->num_large_buffers)
1988 qdev->lrg_buf_index = 0;
d7f61777 1989 return lrg_buf_cb;
97916330
RM		 1990}
1991
bd36b0ac
RM		 1992/*
1993 * The difference between 3022 and 3032 for inbound completions:
9ddf7774
JG		 1994 * 3022 uses two buffers per completion. The first buffer contains
1995 * (some) header info, the second the remainder of the headers plus
1996 * the data. For this chip we reserve some space at the top of the
1997 * receive buffer so that the header info in buffer one can be
1998 * prepended to the buffer two. Buffer two is the sent up while
bd36b0ac 1999 * buffer one is returned to the hardware to be reused.
9ddf7774 2000 * 3032 receives all of it's data and headers in one buffer for a
bd36b0ac
RM		 2001 * simpler process. 3032 also supports checksum verification as
2002 * can be seen in ql_process_macip_rx_intr().
2003 */
5a4faa87
RM		 2004static void ql_process_mac_rx_intr(struct ql3_adapter *qdev,
2005 struct ib_mac_iocb_rsp *ib_mac_rsp_ptr)
2006{
5a4faa87
RM		 2007 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2008 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
5a4faa87
RM		 2009 struct sk_buff *skb;
2010 u16 length = le16_to_cpu(ib_mac_rsp_ptr->length);
2011
2012 /*
2013 * Get the inbound address list (small buffer).
2014 */
97916330 2015 ql_get_sbuf(qdev);
5a4faa87 2016
97916330
RM		 2017 if (qdev->device_id == QL3022_DEVICE_ID)
2018 lrg_buf_cb1 = ql_get_lbuf(qdev);
5a4faa87
RM		 2019
2020 /* start of second buffer */
97916330 2021 lrg_buf_cb2 = ql_get_lbuf(qdev);
5a4faa87
RM		 2022 skb = lrg_buf_cb2->skb;
2023
09f75cd7
JG		 2024 qdev->ndev->stats.rx_packets++;
2025 qdev->ndev->stats.rx_bytes += length;
5a4faa87
RM		 2026
2027 skb_put(skb, length);
2028 pci_unmap_single(qdev->pdev,
87196eb7
FT		 2029 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2030 dma_unmap_len(lrg_buf_cb2, maplen),
5a4faa87
RM		 2031 PCI_DMA_FROMDEVICE);
2032 prefetch(skb->data);
bc8acf2c 2033 skb_checksum_none_assert(skb);
5a4faa87
RM		 2034 skb->protocol = eth_type_trans(skb, qdev->ndev);
2035
2036 netif_receive_skb(skb);
5a4faa87
RM		 2037 lrg_buf_cb2->skb = NULL;
2038
bd36b0ac
RM		 2039 if (qdev->device_id == QL3022_DEVICE_ID)
2040 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
5a4faa87
RM		 2041 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2042}
2043
2044static void ql_process_macip_rx_intr(struct ql3_adapter *qdev,
2045 struct ib_ip_iocb_rsp *ib_ip_rsp_ptr)
2046{
5a4faa87
RM		 2047 struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL;
2048 struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL;
bd36b0ac 2049 struct sk_buff *skb1 = NULL, *skb2;
5a4faa87
RM		 2050 struct net_device *ndev = qdev->ndev;
2051 u16 length = le16_to_cpu(ib_ip_rsp_ptr->length);
2052 u16 size = 0;
2053
2054 /*
2055 * Get the inbound address list (small buffer).
2056 */
2057
97916330 2058 ql_get_sbuf(qdev);
5a4faa87 2059
bd36b0ac
RM		 2060 if (qdev->device_id == QL3022_DEVICE_ID) {
2061 /* start of first buffer on 3022 */
97916330 2062 lrg_buf_cb1 = ql_get_lbuf(qdev);
bd36b0ac 2063 skb1 = lrg_buf_cb1->skb;
bd36b0ac
RM		 2064 size = ETH_HLEN;
2065 if (*((u16 *) skb1->data) != 0xFFFF)
2066 size += VLAN_ETH_HLEN - ETH_HLEN;
2067 }
5a4faa87
RM		 2068
2069 /* start of second buffer */
97916330 2070 lrg_buf_cb2 = ql_get_lbuf(qdev);
5a4faa87 2071 skb2 = lrg_buf_cb2->skb;
5a4faa87 2072
5a4faa87
RM		 2073 skb_put(skb2, length); /* Just the second buffer length here. */
2074 pci_unmap_single(qdev->pdev,
87196eb7
FT		 2075 dma_unmap_addr(lrg_buf_cb2, mapaddr),
2076 dma_unmap_len(lrg_buf_cb2, maplen),
5a4faa87
RM		 2077 PCI_DMA_FROMDEVICE);
2078 prefetch(skb2->data);
2079
bc8acf2c 2080 skb_checksum_none_assert(skb2);
bd36b0ac
RM		 2081 if (qdev->device_id == QL3022_DEVICE_ID) {
2082 /*
2083 * Copy the ethhdr from first buffer to second. This
2084 * is necessary for 3022 IP completions.
2085 */
d626f62b
ACM		 2086 skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN,
2087 skb_push(skb2, size), size);
bd36b0ac
RM		 2088 } else {
2089 u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum);
9ddf7774
JG		 2090 if (checksum &
2091 (IB_IP_IOCB_RSP_3032_ICE |
2092 IB_IP_IOCB_RSP_3032_CE)) {
eddc5fbd
JP		 2093 netdev_err(ndev,
2094 "%s: Bad checksum for this %s packet, checksum = %x\n",
2095 __func__,
2096 ((checksum & IB_IP_IOCB_RSP_3032_TCP) ?
2097 "TCP" : "UDP"), checksum);
b3b1514c
RM		 2098 } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) ||
2099 (checksum & IB_IP_IOCB_RSP_3032_UDP &&
2100 !(checksum & IB_IP_IOCB_RSP_3032_NUC))) {
bd36b0ac 2101 skb2->ip_summed = CHECKSUM_UNNECESSARY;
b3b1514c 2102 }
bd36b0ac 2103 }
5a4faa87
RM		 2104 skb2->protocol = eth_type_trans(skb2, qdev->ndev);
2105
2106 netif_receive_skb(skb2);
09f75cd7
JG		 2107 ndev->stats.rx_packets++;
2108 ndev->stats.rx_bytes += length;
5a4faa87
RM		 2109 lrg_buf_cb2->skb = NULL;
2110
bd36b0ac
RM		 2111 if (qdev->device_id == QL3022_DEVICE_ID)
2112 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1);
5a4faa87
RM		 2113 ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2);
2114}
2115
2116static int ql_tx_rx_clean(struct ql3_adapter *qdev,
2117 int *tx_cleaned, int *rx_cleaned, int work_to_do)
2118{
5a4faa87
RM		 2119 struct net_rsp_iocb *net_rsp;
2120 struct net_device *ndev = qdev->ndev;
63b66d12 2121 int work_done = 0;
5a4faa87
RM		 2122
2123 /* While there are entries in the completion queue. */
f67cac01 2124 while ((le32_to_cpu(*(qdev->prsp_producer_index)) !=
63b66d12 2125 qdev->rsp_consumer_index) && (work_done < work_to_do)) {
5a4faa87
RM		 2126
2127 net_rsp = qdev->rsp_current;
b323e0e4 2128 rmb();
50626297 2129 /*
d7f61777
JP		 2130 * Fix 4032 chip's undocumented "feature" where bit-8 is set
2131 * if the inbound completion is for a VLAN.
50626297
RM		 2132 */
2133 if (qdev->device_id == QL3032_DEVICE_ID)
2134 net_rsp->opcode &= 0x7f;
5a4faa87
RM		 2135 switch (net_rsp->opcode) {
2136
2137 case OPCODE_OB_MAC_IOCB_FN0:
2138 case OPCODE_OB_MAC_IOCB_FN2:
2139 ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *)
2140 net_rsp);
2141 (*tx_cleaned)++;
2142 break;
2143
2144 case OPCODE_IB_MAC_IOCB:
bd36b0ac 2145 case OPCODE_IB_3032_MAC_IOCB:
5a4faa87
RM		 2146 ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *)
2147 net_rsp);
2148 (*rx_cleaned)++;
2149 break;
2150
2151 case OPCODE_IB_IP_IOCB:
bd36b0ac 2152 case OPCODE_IB_3032_IP_IOCB:
5a4faa87
RM		 2153 ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *)
2154 net_rsp);
2155 (*rx_cleaned)++;
2156 break;
d7f61777
JP		 2157 default: {
2158 u32 *tmp = (u32 *)net_rsp;
2159 netdev_err(ndev,
2160 "Hit default case, not handled!\n"
2161 " dropping the packet, opcode = %x\n"
2162 "0x%08lx 0x%08lx 0x%08lx 0x%08lx\n",
2163 net_rsp->opcode,
2164 (unsigned long int)tmp[0],
2165 (unsigned long int)tmp[1],
2166 (unsigned long int)tmp[2],
2167 (unsigned long int)tmp[3]);
2168 }
5a4faa87
RM		 2169 }
2170
2171 qdev->rsp_consumer_index++;
2172
2173 if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) {
2174 qdev->rsp_consumer_index = 0;
2175 qdev->rsp_current = qdev->rsp_q_virt_addr;
2176 } else {
2177 qdev->rsp_current++;
2178 }
63b66d12
RM		 2179
2180 work_done = *tx_cleaned + *rx_cleaned;
5a4faa87
RM		 2181 }
2182
f67cac01 2183 return work_done;
5a4faa87
RM		 2184}
2185
bea3348e 2186static int ql_poll(struct napi_struct *napi, int budget)
5a4faa87 2187{
bea3348e 2188 struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi);
5a4faa87 2189 int rx_cleaned = 0, tx_cleaned = 0;
63b66d12 2190 unsigned long hw_flags;
d7f61777
JP		 2191 struct ql3xxx_port_registers __iomem *port_regs =
2192 qdev->mem_map_registers;
5a4faa87 2193
bea3348e 2194 ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, budget);
5a4faa87 2195
4ec24119 2196 if (tx_cleaned + rx_cleaned != budget) {
63b66d12 2197 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
288379f0 2198 __napi_complete(napi);
f67cac01
RM		 2199 ql_update_small_bufq_prod_index(qdev);
2200 ql_update_lrg_bufq_prod_index(qdev);
2201 writel(qdev->rsp_consumer_index,
2202 &port_regs->CommonRegs.rspQConsumerIndex);
63b66d12
RM		 2203 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
2204
5a4faa87 2205 ql_enable_interrupts(qdev);
5a4faa87 2206 }
bea3348e 2207 return tx_cleaned + rx_cleaned;
5a4faa87
RM		 2208}
2209
7d12e780 2210static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
5a4faa87
RM		 2211{
2212
2213 struct net_device *ndev = dev_id;
2214 struct ql3_adapter *qdev = netdev_priv(ndev);
d7f61777
JP		 2215 struct ql3xxx_port_registers __iomem *port_regs =
2216 qdev->mem_map_registers;
5a4faa87
RM		 2217 u32 value;
2218 int handled = 1;
2219 u32 var;
2220
d7f61777
JP		 2221 value = ql_read_common_reg_l(qdev,
2222 &port_regs->CommonRegs.ispControlStatus);
5a4faa87
RM		 2223
2224 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2225 spin_lock(&qdev->adapter_lock);
2226 netif_stop_queue(qdev->ndev);
2227 netif_carrier_off(qdev->ndev);
2228 ql_disable_interrupts(qdev);
2229 qdev->port_link_state = LS_DOWN;
d7f61777 2230 set_bit(QL_RESET_ACTIVE, &qdev->flags) ;
5a4faa87
RM		 2231
2232 if (value & ISP_CONTROL_FE) {
2233 /*
2234 * Chip Fatal Error.
2235 */
2236 var =
2237 ql_read_page0_reg_l(qdev,
2238 &port_regs->PortFatalErrStatus);
eddc5fbd
JP		 2239 netdev_warn(ndev,
2240 "Resetting chip. PortFatalErrStatus register = 0x%x\n",
2241 var);
d7f61777 2242 set_bit(QL_RESET_START, &qdev->flags) ;
5a4faa87
RM		 2243 } else {
2244 /*
2245 * Soft Reset Requested.
2246 */
d7f61777 2247 set_bit(QL_RESET_PER_SCSI, &qdev->flags) ;
eddc5fbd
JP		 2248 netdev_err(ndev,
2249 "Another function issued a reset to the chip. ISR value = %x\n",
2250 value);
5a4faa87 2251 }
c4028958 2252 queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
5a4faa87
RM		 2253 spin_unlock(&qdev->adapter_lock);
2254 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
e8f4df24 2255 ql_disable_interrupts(qdev);
d7f61777 2256 if (likely(napi_schedule_prep(&qdev->napi)))
288379f0 2257 __napi_schedule(&qdev->napi);
d7f61777 2258 } else
5a4faa87 2259 return IRQ_NONE;
5a4faa87
RM		 2260
2261 return IRQ_RETVAL(handled);
2262}
2263
bd36b0ac 2264/*
d7f61777
JP		 2265 * Get the total number of segments needed for the given number of fragments.
2266 * This is necessary because outbound address lists (OAL) will be used when
2267 * more than two frags are given. Each address list has 5 addr/len pairs.
2268 * The 5th pair in each OAL is used to point to the next OAL if more frags
2269 * are coming. That is why the frags:segment count ratio is not linear.
bd36b0ac 2270 */
d7f61777 2271static int ql_get_seg_count(struct ql3_adapter *qdev, unsigned short frags)
bd36b0ac 2272{
e8f4df24
BL		 2273 if (qdev->device_id == QL3022_DEVICE_ID)
2274 return 1;
2275
d7f61777
JP		 2276 if (frags <= 2)
2277 return frags + 1;
2278 else if (frags <= 6)
2279 return frags + 2;
2280 else if (frags <= 10)
2281 return frags + 3;
2282 else if (frags <= 14)
2283 return frags + 4;
2284 else if (frags <= 18)
2285 return frags + 5;
bd36b0ac
RM		 2286 return -1;
2287}
2288
91e745aa 2289static void ql_hw_csum_setup(const struct sk_buff *skb,
bd36b0ac
RM		 2290 struct ob_mac_iocb_req *mac_iocb_ptr)
2291{
91e745aa 2292 const struct iphdr *ip = ip_hdr(skb);
bd36b0ac 2293
91e745aa
SH		 2294 mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb);
2295 mac_iocb_ptr->ip_hdr_len = ip->ihl;
bd36b0ac 2296
91e745aa
SH		 2297 if (ip->protocol == IPPROTO_TCP) {
2298 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC |
3e71f6dd 2299 OB_3032MAC_IOCB_REQ_IC;
91e745aa
SH		 2300 } else {
2301 mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC |
3e71f6dd 2302 OB_3032MAC_IOCB_REQ_IC;
bd36b0ac 2303 }
91e745aa 2304
bd36b0ac
RM		 2305}
2306
2307/*
d7f61777
JP		 2308 * Map the buffers for this transmit.
2309 * This will return NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
bd36b0ac 2310 */
3e71f6dd
RM		 2311static int ql_send_map(struct ql3_adapter *qdev,
2312 struct ob_mac_iocb_req *mac_iocb_ptr,
2313 struct ql_tx_buf_cb *tx_cb,
2314 struct sk_buff *skb)
5a4faa87 2315{
bd36b0ac
RM		 2316 struct oal *oal;
2317 struct oal_entry *oal_entry;
63f77926 2318 int len = skb_headlen(skb);
0f8ab89e
BL		 2319 dma_addr_t map;
2320 int err;
2321 int completed_segs, i;
bd36b0ac
RM		 2322 int seg_cnt, seg = 0;
2323 int frag_cnt = (int)skb_shinfo(skb)->nr_frags;
5a4faa87 2324
b6967eb9 2325 seg_cnt = tx_cb->seg_count;
3e71f6dd
RM		 2326 /*
2327 * Map the skb buffer first.
2328 */
bd36b0ac 2329 map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
0f8ab89e 2330
8d8bb39b 2331 err = pci_dma_mapping_error(qdev->pdev, map);
d7f61777 2332 if (err) {
eddc5fbd
JP		 2333 netdev_err(qdev->ndev, "PCI mapping failed with error: %d\n",
2334 err);
0f8ab89e
BL		 2335
2336 return NETDEV_TX_BUSY;
2337 }
9ddf7774 2338
bd36b0ac
RM		 2339 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2340 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2341 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2342 oal_entry->len = cpu_to_le32(len);
87196eb7
FT		 2343 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2344 dma_unmap_len_set(&tx_cb->map[seg], maplen, len);
bd36b0ac
RM		 2345 seg++;
2346
e8f4df24 2347 if (seg_cnt == 1) {
bd36b0ac 2348 /* Terminate the last segment. */
b39b5a2b 2349 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
d7f61777
JP		 2350 return NETDEV_TX_OK;
2351 }
2352 oal = tx_cb->oal;
2353 for (completed_segs = 0;
2354 completed_segs < frag_cnt;
2355 completed_segs++, seg++) {
2356 skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs];
2357 oal_entry++;
2358 /*
2359 * Check for continuation requirements.
2360 * It's strange but necessary.
2361 * Continuation entry points to outbound address list.
2362 */
2363 if ((seg == 2 && seg_cnt > 3) ||
2364 (seg == 7 && seg_cnt > 8) ||
2365 (seg == 12 && seg_cnt > 13) ||
2366 (seg == 17 && seg_cnt > 18)) {
2367 map = pci_map_single(qdev->pdev, oal,
2368 sizeof(struct oal),
2369 PCI_DMA_TODEVICE);
0f8ab89e 2370
8d8bb39b 2371 err = pci_dma_mapping_error(qdev->pdev, map);
d7f61777 2372 if (err) {
eddc5fbd 2373 netdev_err(qdev->ndev,
d7f61777 2374 "PCI mapping outbound address list with error: %d\n",
eddc5fbd 2375 err);
0f8ab89e
BL		 2376 goto map_error;
2377 }
2378
bd36b0ac
RM		 2379 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2380 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
d7f61777
JP		 2381 oal_entry->len = cpu_to_le32(sizeof(struct oal) |
2382 OAL_CONT_ENTRY);
87196eb7
FT		 2383 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2384 dma_unmap_len_set(&tx_cb->map[seg], maplen,
d7f61777
JP		 2385 sizeof(struct oal));
2386 oal_entry = (struct oal_entry *)oal;
2387 oal++;
2388 seg++;
bd36b0ac 2389 }
0f8ab89e 2390
d7f61777
JP		 2391 map = pci_map_page(qdev->pdev, frag->page,
2392 frag->page_offset, frag->size,
2393 PCI_DMA_TODEVICE);
2394
2395 err = pci_dma_mapping_error(qdev->pdev, map);
2396 if (err) {
2397 netdev_err(qdev->ndev,
2398 "PCI mapping frags failed with error: %d\n",
2399 err);
2400 goto map_error;
2401 }
2402
2403 oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map));
2404 oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map));
2405 oal_entry->len = cpu_to_le32(frag->size);
2406 dma_unmap_addr_set(&tx_cb->map[seg], mapaddr, map);
2407 dma_unmap_len_set(&tx_cb->map[seg], maplen, frag->size);
2408 }
2409 /* Terminate the last segment. */
2410 oal_entry->len |= cpu_to_le32(OAL_LAST_ENTRY);
3e71f6dd 2411 return NETDEV_TX_OK;
0f8ab89e
BL		 2412
2413map_error:
2414 /* A PCI mapping failed and now we will need to back out
9ddf7774 2415 * We need to traverse through the oal's and associated pages which
0f8ab89e
BL		 2416 * have been mapped and now we must unmap them to clean up properly
2417 */
9ddf7774 2418
0f8ab89e
BL		 2419 seg = 1;
2420 oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low;
2421 oal = tx_cb->oal;
d7f61777 2422 for (i = 0; i < completed_segs; i++, seg++) {
0f8ab89e
BL		 2423 oal_entry++;
2424
d7f61777
JP		 2425 /*
2426 * Check for continuation requirements.
2427 * It's strange but necessary.
2428 */
2429
2430 if ((seg == 2 && seg_cnt > 3) ||
2431 (seg == 7 && seg_cnt > 8) ||
2432 (seg == 12 && seg_cnt > 13) ||
2433 (seg == 17 && seg_cnt > 18)) {
0f8ab89e 2434 pci_unmap_single(qdev->pdev,
87196eb7
FT		 2435 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2436 dma_unmap_len(&tx_cb->map[seg], maplen),
0f8ab89e
BL		 2437 PCI_DMA_TODEVICE);
2438 oal++;
2439 seg++;
2440 }
2441
2442 pci_unmap_page(qdev->pdev,
87196eb7
FT		 2443 dma_unmap_addr(&tx_cb->map[seg], mapaddr),
2444 dma_unmap_len(&tx_cb->map[seg], maplen),
0f8ab89e
BL		 2445 PCI_DMA_TODEVICE);
2446 }
2447
2448 pci_unmap_single(qdev->pdev,
87196eb7
FT		 2449 dma_unmap_addr(&tx_cb->map[0], mapaddr),
2450 dma_unmap_addr(&tx_cb->map[0], maplen),
0f8ab89e
BL		 2451 PCI_DMA_TODEVICE);
2452
2453 return NETDEV_TX_BUSY;
2454
3e71f6dd
RM		 2455}
2456
2457/*
2458 * The difference between 3022 and 3032 sends:
2459 * 3022 only supports a simple single segment transmission.
2460 * 3032 supports checksumming and scatter/gather lists (fragments).
9ddf7774
JG		 2461 * The 3032 supports sglists by using the 3 addr/len pairs (ALP)
2462 * in the IOCB plus a chain of outbound address lists (OAL) that
2463 * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th)
177b241d 2464 * will be used to point to an OAL when more ALP entries are required.
9ddf7774 2465 * The IOCB is always the top of the chain followed by one or more
3e71f6dd
RM		 2466 * OALs (when necessary).
2467 */
61357325
SH		 2468static netdev_tx_t ql3xxx_send(struct sk_buff *skb,
2469 struct net_device *ndev)
3e71f6dd 2470{
4dd15187 2471 struct ql3_adapter *qdev = netdev_priv(ndev);
d7f61777
JP		 2472 struct ql3xxx_port_registers __iomem *port_regs =
2473 qdev->mem_map_registers;
3e71f6dd
RM		 2474 struct ql_tx_buf_cb *tx_cb;
2475 u32 tot_len = skb->len;
2476 struct ob_mac_iocb_req *mac_iocb_ptr;
2477
d7f61777 2478 if (unlikely(atomic_read(&qdev->tx_count) < 2))
3e71f6dd 2479 return NETDEV_TX_BUSY;
9ddf7774 2480
d7f61777
JP		 2481 tx_cb = &qdev->tx_buf[qdev->req_producer_index];
2482 tx_cb->seg_count = ql_get_seg_count(qdev,
2483 skb_shinfo(skb)->nr_frags);
2484 if (tx_cb->seg_count == -1) {
eddc5fbd 2485 netdev_err(ndev, "%s: invalid segment count!\n", __func__);
3e71f6dd
RM		 2486 return NETDEV_TX_OK;
2487 }
9ddf7774 2488
3e71f6dd 2489 mac_iocb_ptr = tx_cb->queue_entry;
d8a759ff 2490 memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req));
3e71f6dd
RM		 2491 mac_iocb_ptr->opcode = qdev->mac_ob_opcode;
2492 mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X;
2493 mac_iocb_ptr->flags |= qdev->mb_bit_mask;
2494 mac_iocb_ptr->transaction_id = qdev->req_producer_index;
2495 mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len);
2496 tx_cb->skb = skb;
e8f4df24
BL		 2497 if (qdev->device_id == QL3032_DEVICE_ID &&
2498 skb->ip_summed == CHECKSUM_PARTIAL)
3e71f6dd 2499 ql_hw_csum_setup(skb, mac_iocb_ptr);
9ddf7774 2500
d7f61777 2501 if (ql_send_map(qdev, mac_iocb_ptr, tx_cb, skb) != NETDEV_TX_OK) {
eddc5fbd 2502 netdev_err(ndev, "%s: Could not map the segments!\n", __func__);
3e71f6dd
RM		 2503 return NETDEV_TX_BUSY;
2504 }
9ddf7774 2505
bd36b0ac 2506 wmb();
5a4faa87
RM		 2507 qdev->req_producer_index++;
2508 if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES)
2509 qdev->req_producer_index = 0;
2510 wmb();
2511 ql_write_common_reg_l(qdev,
ee111d11 2512 &port_regs->CommonRegs.reqQProducerIndex,
5a4faa87
RM		 2513 qdev->req_producer_index);
2514
eddc5fbd
JP		 2515 netif_printk(qdev, tx_queued, KERN_DEBUG, ndev,
2516 "tx queued, slot %d, len %d\n",
2517 qdev->req_producer_index, skb->len);
5a4faa87 2518
bd36b0ac 2519 atomic_dec(&qdev->tx_count);
5a4faa87
RM		 2520 return NETDEV_TX_OK;
2521}
bd36b0ac 2522
5a4faa87
RM		 2523static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev)
2524{
2525 qdev->req_q_size =
2526 (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req));
2527
2528 qdev->req_q_virt_addr =
2529 pci_alloc_consistent(qdev->pdev,
2530 (size_t) qdev->req_q_size,
2531 &qdev->req_q_phy_addr);
2532
2533 if ((qdev->req_q_virt_addr == NULL) ||
2534 LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) {
eddc5fbd 2535 netdev_err(qdev->ndev, "reqQ failed\n");
5a4faa87
RM		 2536 return -ENOMEM;
2537 }
2538
2539 qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb);
2540
2541 qdev->rsp_q_virt_addr =
2542 pci_alloc_consistent(qdev->pdev,
2543 (size_t) qdev->rsp_q_size,
2544 &qdev->rsp_q_phy_addr);
2545
2546 if ((qdev->rsp_q_virt_addr == NULL) ||
2547 LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) {
eddc5fbd 2548 netdev_err(qdev->ndev, "rspQ allocation failed\n");
5a4faa87
RM		 2549 pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size,
2550 qdev->req_q_virt_addr,
2551 qdev->req_q_phy_addr);
2552 return -ENOMEM;
2553 }
2554
d7f61777 2555 set_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
5a4faa87
RM		 2556
2557 return 0;
2558}
2559
2560static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev)
2561{
d7f61777 2562 if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags)) {
eddc5fbd 2563 netdev_info(qdev->ndev, "Already done\n");
5a4faa87
RM		 2564 return;
2565 }
2566
2567 pci_free_consistent(qdev->pdev,
2568 qdev->req_q_size,
2569 qdev->req_q_virt_addr, qdev->req_q_phy_addr);
2570
2571 qdev->req_q_virt_addr = NULL;
2572
2573 pci_free_consistent(qdev->pdev,
2574 qdev->rsp_q_size,
2575 qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr);
2576
2577 qdev->rsp_q_virt_addr = NULL;
2578
d7f61777 2579 clear_bit(QL_ALLOC_REQ_RSP_Q_DONE, &qdev->flags);
5a4faa87
RM		 2580}
2581
2582static int ql_alloc_buffer_queues(struct ql3_adapter *qdev)
2583{
2584 /* Create Large Buffer Queue */
2585 qdev->lrg_buf_q_size =
d7f61777 2586 qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry);
5a4faa87
RM		 2587 if (qdev->lrg_buf_q_size < PAGE_SIZE)
2588 qdev->lrg_buf_q_alloc_size = PAGE_SIZE;
2589 else
2590 qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2;
2591
d7f61777
JP		 2592 qdev->lrg_buf =
2593 kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),
2594 GFP_KERNEL);
1357bfcf 2595 if (qdev->lrg_buf == NULL) {
eddc5fbd 2596 netdev_err(qdev->ndev, "qdev->lrg_buf alloc failed\n");
1357bfcf
RM		 2597 return -ENOMEM;
2598 }
9ddf7774 2599
5a4faa87 2600 qdev->lrg_buf_q_alloc_virt_addr =
d7f61777
JP		 2601 pci_alloc_consistent(qdev->pdev,
2602 qdev->lrg_buf_q_alloc_size,
2603 &qdev->lrg_buf_q_alloc_phy_addr);
5a4faa87
RM		 2604
2605 if (qdev->lrg_buf_q_alloc_virt_addr == NULL) {
eddc5fbd 2606 netdev_err(qdev->ndev, "lBufQ failed\n");
5a4faa87
RM		 2607 return -ENOMEM;
2608 }
2609 qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr;
2610 qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr;
2611
2612 /* Create Small Buffer Queue */
2613 qdev->small_buf_q_size =
d7f61777 2614 NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry);
5a4faa87
RM		 2615 if (qdev->small_buf_q_size < PAGE_SIZE)
2616 qdev->small_buf_q_alloc_size = PAGE_SIZE;
2617 else
2618 qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2;
2619
2620 qdev->small_buf_q_alloc_virt_addr =
d7f61777
JP		 2621 pci_alloc_consistent(qdev->pdev,
2622 qdev->small_buf_q_alloc_size,
2623 &qdev->small_buf_q_alloc_phy_addr);
5a4faa87
RM		 2624
2625 if (qdev->small_buf_q_alloc_virt_addr == NULL) {
eddc5fbd 2626 netdev_err(qdev->ndev, "Small Buffer Queue allocation failed\n");
5a4faa87
RM		 2627 pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size,
2628 qdev->lrg_buf_q_alloc_virt_addr,
2629 qdev->lrg_buf_q_alloc_phy_addr);
2630 return -ENOMEM;
2631 }
2632
2633 qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr;
2634 qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr;
d7f61777 2635 set_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
5a4faa87
RM		 2636 return 0;
2637}
2638
2639static void ql_free_buffer_queues(struct ql3_adapter *qdev)
2640{
d7f61777 2641 if (!test_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags)) {
eddc5fbd 2642 netdev_info(qdev->ndev, "Already done\n");
5a4faa87
RM		 2643 return;
2644 }
d7f61777 2645 kfree(qdev->lrg_buf);
5a4faa87
RM		 2646 pci_free_consistent(qdev->pdev,
2647 qdev->lrg_buf_q_alloc_size,
2648 qdev->lrg_buf_q_alloc_virt_addr,
2649 qdev->lrg_buf_q_alloc_phy_addr);
2650
2651 qdev->lrg_buf_q_virt_addr = NULL;
2652
2653 pci_free_consistent(qdev->pdev,
2654 qdev->small_buf_q_alloc_size,
2655 qdev->small_buf_q_alloc_virt_addr,
2656 qdev->small_buf_q_alloc_phy_addr);
2657
2658 qdev->small_buf_q_virt_addr = NULL;
2659
d7f61777 2660 clear_bit(QL_ALLOC_BUFQS_DONE, &qdev->flags);
5a4faa87
RM		 2661}
2662
2663static int ql_alloc_small_buffers(struct ql3_adapter *qdev)
2664{
2665 int i;
2666 struct bufq_addr_element *small_buf_q_entry;
2667
2668 /* Currently we allocate on one of memory and use it for smallbuffers */
2669 qdev->small_buf_total_size =
d7f61777
JP		 2670 (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES *
2671 QL_SMALL_BUFFER_SIZE);
5a4faa87
RM		 2672
2673 qdev->small_buf_virt_addr =
d7f61777
JP		 2674 pci_alloc_consistent(qdev->pdev,
2675 qdev->small_buf_total_size,
2676 &qdev->small_buf_phy_addr);
5a4faa87
RM		 2677
2678 if (qdev->small_buf_virt_addr == NULL) {
eddc5fbd 2679 netdev_err(qdev->ndev, "Failed to get small buffer memory\n");
5a4faa87
RM		 2680 return -ENOMEM;
2681 }
2682
2683 qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr);
2684 qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr);
2685
2686 small_buf_q_entry = qdev->small_buf_q_virt_addr;
2687
5a4faa87
RM		 2688 /* Initialize the small buffer queue. */
2689 for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) {
2690 small_buf_q_entry->addr_high =
2691 cpu_to_le32(qdev->small_buf_phy_addr_high);
2692 small_buf_q_entry->addr_low =
2693 cpu_to_le32(qdev->small_buf_phy_addr_low +
2694 (i * QL_SMALL_BUFFER_SIZE));
2695 small_buf_q_entry++;
2696 }
2697 qdev->small_buf_index = 0;
d7f61777 2698 set_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags);
5a4faa87
RM		 2699 return 0;
2700}
2701
2702static void ql_free_small_buffers(struct ql3_adapter *qdev)
2703{
d7f61777 2704 if (!test_bit(QL_ALLOC_SMALL_BUF_DONE, &qdev->flags)) {
eddc5fbd 2705 netdev_info(qdev->ndev, "Already done\n");
5a4faa87
RM		 2706 return;
2707 }
2708 if (qdev->small_buf_virt_addr != NULL) {
2709 pci_free_consistent(qdev->pdev,
2710 qdev->small_buf_total_size,
2711 qdev->small_buf_virt_addr,
2712 qdev->small_buf_phy_addr);
2713
2714 qdev->small_buf_virt_addr = NULL;
2715 }
2716}
2717
2718static void ql_free_large_buffers(struct ql3_adapter *qdev)
2719{
2720 int i = 0;
2721 struct ql_rcv_buf_cb *lrg_buf_cb;
2722
1357bfcf 2723 for (i = 0; i < qdev->num_large_buffers; i++) {
5a4faa87
RM		 2724 lrg_buf_cb = &qdev->lrg_buf[i];
2725 if (lrg_buf_cb->skb) {
2726 dev_kfree_skb(lrg_buf_cb->skb);
2727 pci_unmap_single(qdev->pdev,
87196eb7
FT		 2728 dma_unmap_addr(lrg_buf_cb, mapaddr),
2729 dma_unmap_len(lrg_buf_cb, maplen),
5a4faa87
RM		 2730 PCI_DMA_FROMDEVICE);
2731 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2732 } else {
2733 break;
2734 }
2735 }
2736}
2737
2738static void ql_init_large_buffers(struct ql3_adapter *qdev)
2739{
2740 int i;
2741 struct ql_rcv_buf_cb *lrg_buf_cb;
2742 struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr;
2743
1357bfcf 2744 for (i = 0; i < qdev->num_large_buffers; i++) {
5a4faa87
RM		 2745 lrg_buf_cb = &qdev->lrg_buf[i];
2746 buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high;
2747 buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low;
2748 buf_addr_ele++;
2749 }
2750 qdev->lrg_buf_index = 0;
2751 qdev->lrg_buf_skb_check = 0;
2752}
2753
2754static int ql_alloc_large_buffers(struct ql3_adapter *qdev)
2755{
2756 int i;
2757 struct ql_rcv_buf_cb *lrg_buf_cb;
2758 struct sk_buff *skb;
0f8ab89e
BL		 2759 dma_addr_t map;
2760 int err;
5a4faa87 2761
1357bfcf 2762 for (i = 0; i < qdev->num_large_buffers; i++) {
cd238faa
BL		 2763 skb = netdev_alloc_skb(qdev->ndev,
2764 qdev->lrg_buffer_len);
5a4faa87
RM		 2765 if (unlikely(!skb)) {
2766 /* Better luck next round */
eddc5fbd
JP		 2767 netdev_err(qdev->ndev,
2768 "large buff alloc failed for %d bytes at index %d\n",
2769 qdev->lrg_buffer_len * 2, i);
5a4faa87
RM		 2770 ql_free_large_buffers(qdev);
2771 return -ENOMEM;
2772 } else {
2773
2774 lrg_buf_cb = &qdev->lrg_buf[i];
2775 memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb));
2776 lrg_buf_cb->index = i;
2777 lrg_buf_cb->skb = skb;
2778 /*
2779 * We save some space to copy the ethhdr from first
2780 * buffer
2781 */
2782 skb_reserve(skb, QL_HEADER_SPACE);
2783 map = pci_map_single(qdev->pdev,
2784 skb->data,
2785 qdev->lrg_buffer_len -
2786 QL_HEADER_SPACE,
2787 PCI_DMA_FROMDEVICE);
0f8ab89e 2788
8d8bb39b 2789 err = pci_dma_mapping_error(qdev->pdev, map);
d7f61777 2790 if (err) {
eddc5fbd
JP		 2791 netdev_err(qdev->ndev,
2792 "PCI mapping failed with error: %d\n",
2793 err);
0f8ab89e
BL		 2794 ql_free_large_buffers(qdev);
2795 return -ENOMEM;
2796 }
2797
87196eb7
FT		 2798 dma_unmap_addr_set(lrg_buf_cb, mapaddr, map);
2799 dma_unmap_len_set(lrg_buf_cb, maplen,
5a4faa87
RM		 2800 qdev->lrg_buffer_len -
2801 QL_HEADER_SPACE);
2802 lrg_buf_cb->buf_phy_addr_low =
2803 cpu_to_le32(LS_64BITS(map));
2804 lrg_buf_cb->buf_phy_addr_high =
2805 cpu_to_le32(MS_64BITS(map));
2806 }
2807 }
2808 return 0;
2809}
2810
bd36b0ac
RM		 2811static void ql_free_send_free_list(struct ql3_adapter *qdev)
2812{
2813 struct ql_tx_buf_cb *tx_cb;
2814 int i;
2815
2816 tx_cb = &qdev->tx_buf[0];
2817 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
d7f61777
JP		 2818 kfree(tx_cb->oal);
2819 tx_cb->oal = NULL;
bd36b0ac
RM		 2820 tx_cb++;
2821 }
2822}
2823
2824static int ql_create_send_free_list(struct ql3_adapter *qdev)
5a4faa87
RM		 2825{
2826 struct ql_tx_buf_cb *tx_cb;
2827 int i;
d7f61777 2828 struct ob_mac_iocb_req *req_q_curr = qdev->req_q_virt_addr;
5a4faa87
RM		 2829
2830 /* Create free list of transmit buffers */
2831 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
bd36b0ac 2832
5a4faa87
RM		 2833 tx_cb = &qdev->tx_buf[i];
2834 tx_cb->skb = NULL;
2835 tx_cb->queue_entry = req_q_curr;
2836 req_q_curr++;
bd36b0ac
RM		 2837 tx_cb->oal = kmalloc(512, GFP_KERNEL);
2838 if (tx_cb->oal == NULL)
2839 return -1;
5a4faa87 2840 }
bd36b0ac 2841 return 0;
5a4faa87
RM		 2842}
2843
2844static int ql_alloc_mem_resources(struct ql3_adapter *qdev)
2845{
1357bfcf
RM		 2846 if (qdev->ndev->mtu == NORMAL_MTU_SIZE) {
2847 qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES;
5a4faa87 2848 qdev->lrg_buffer_len = NORMAL_MTU_SIZE;
d7f61777 2849 } else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) {
1357bfcf
RM		 2850 /*
2851 * Bigger buffers, so less of them.
2852 */
2853 qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES;
5a4faa87
RM		 2854 qdev->lrg_buffer_len = JUMBO_MTU_SIZE;
2855 } else {
eddc5fbd
JP		 2856 netdev_err(qdev->ndev, "Invalid mtu size: %d. Only %d and %d are accepted.\n",
2857 qdev->ndev->mtu, NORMAL_MTU_SIZE, JUMBO_MTU_SIZE);
5a4faa87
RM		 2858 return -ENOMEM;
2859 }
d7f61777
JP		 2860 qdev->num_large_buffers =
2861 qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY;
5a4faa87
RM		 2862 qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE;
2863 qdev->max_frame_size =
d7f61777 2864 (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE;
5a4faa87
RM		 2865
2866 /*
2867 * First allocate a page of shared memory and use it for shadow
2868 * locations of Network Request Queue Consumer Address Register and
2869 * Network Completion Queue Producer Index Register
2870 */
2871 qdev->shadow_reg_virt_addr =
d7f61777
JP		 2872 pci_alloc_consistent(qdev->pdev,
2873 PAGE_SIZE, &qdev->shadow_reg_phy_addr);
5a4faa87
RM		 2874
2875 if (qdev->shadow_reg_virt_addr != NULL) {
2876 qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr;
2877 qdev->req_consumer_index_phy_addr_high =
d7f61777 2878 MS_64BITS(qdev->shadow_reg_phy_addr);
5a4faa87 2879 qdev->req_consumer_index_phy_addr_low =
d7f61777 2880 LS_64BITS(qdev->shadow_reg_phy_addr);
5a4faa87
RM		 2881
2882 qdev->prsp_producer_index =
d7f61777 2883 (__le32 *) (((u8 *) qdev->preq_consumer_index) + 8);
5a4faa87 2884 qdev->rsp_producer_index_phy_addr_high =
d7f61777 2885 qdev->req_consumer_index_phy_addr_high;
5a4faa87 2886 qdev->rsp_producer_index_phy_addr_low =
d7f61777 2887 qdev->req_consumer_index_phy_addr_low + 8;
5a4faa87 2888 } else {
eddc5fbd 2889 netdev_err(qdev->ndev, "shadowReg Alloc failed\n");
5a4faa87
RM		 2890 return -ENOMEM;
2891 }
2892
2893 if (ql_alloc_net_req_rsp_queues(qdev) != 0) {
eddc5fbd 2894 netdev_err(qdev->ndev, "ql_alloc_net_req_rsp_queues failed\n");
5a4faa87
RM		 2895 goto err_req_rsp;
2896 }
2897
2898 if (ql_alloc_buffer_queues(qdev) != 0) {
eddc5fbd 2899 netdev_err(qdev->ndev, "ql_alloc_buffer_queues failed\n");
5a4faa87
RM		 2900 goto err_buffer_queues;
2901 }
2902
2903 if (ql_alloc_small_buffers(qdev) != 0) {
eddc5fbd 2904 netdev_err(qdev->ndev, "ql_alloc_small_buffers failed\n");
5a4faa87
RM		 2905 goto err_small_buffers;
2906 }
2907
2908 if (ql_alloc_large_buffers(qdev) != 0) {
eddc5fbd 2909 netdev_err(qdev->ndev, "ql_alloc_large_buffers failed\n");
5a4faa87
RM		 2910 goto err_small_buffers;
2911 }
2912
2913 /* Initialize the large buffer queue. */
2914 ql_init_large_buffers(qdev);
bd36b0ac
RM		 2915 if (ql_create_send_free_list(qdev))
2916 goto err_free_list;
5a4faa87
RM		 2917
2918 qdev->rsp_current = qdev->rsp_q_virt_addr;
2919
2920 return 0;
bd36b0ac
RM		 2921err_free_list:
2922 ql_free_send_free_list(qdev);
5a4faa87
RM		 2923err_small_buffers:
2924 ql_free_buffer_queues(qdev);
2925err_buffer_queues:
2926 ql_free_net_req_rsp_queues(qdev);
2927err_req_rsp:
2928 pci_free_consistent(qdev->pdev,
2929 PAGE_SIZE,
2930 qdev->shadow_reg_virt_addr,
2931 qdev->shadow_reg_phy_addr);
2932
2933 return -ENOMEM;
2934}
2935
2936static void ql_free_mem_resources(struct ql3_adapter *qdev)
2937{
bd36b0ac 2938 ql_free_send_free_list(qdev);
5a4faa87
RM		 2939 ql_free_large_buffers(qdev);
2940 ql_free_small_buffers(qdev);
2941 ql_free_buffer_queues(qdev);
2942 ql_free_net_req_rsp_queues(qdev);
2943 if (qdev->shadow_reg_virt_addr != NULL) {
2944 pci_free_consistent(qdev->pdev,
2945 PAGE_SIZE,
2946 qdev->shadow_reg_virt_addr,
2947 qdev->shadow_reg_phy_addr);
2948 qdev->shadow_reg_virt_addr = NULL;
2949 }
2950}
2951
2952static int ql_init_misc_registers(struct ql3_adapter *qdev)
2953{
ee111d11
AV		 2954 struct ql3xxx_local_ram_registers __iomem *local_ram =
2955 (void __iomem *)qdev->mem_map_registers;
5a4faa87 2956
d7f61777 2957 if (ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
5a4faa87
RM		 2958 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
2959 2) << 4))
2960 return -1;
2961
2962 ql_write_page2_reg(qdev,
2963 &local_ram->bufletSize, qdev->nvram_data.bufletSize);
2964
2965 ql_write_page2_reg(qdev,
2966 &local_ram->maxBufletCount,
2967 qdev->nvram_data.bufletCount);
2968
2969 ql_write_page2_reg(qdev,
2970 &local_ram->freeBufletThresholdLow,
2971 (qdev->nvram_data.tcpWindowThreshold25 << 16) |
2972 (qdev->nvram_data.tcpWindowThreshold0));
2973
2974 ql_write_page2_reg(qdev,
2975 &local_ram->freeBufletThresholdHigh,
2976 qdev->nvram_data.tcpWindowThreshold50);
2977
2978 ql_write_page2_reg(qdev,
2979 &local_ram->ipHashTableBase,
2980 (qdev->nvram_data.ipHashTableBaseHi << 16) |
2981 qdev->nvram_data.ipHashTableBaseLo);
2982 ql_write_page2_reg(qdev,
2983 &local_ram->ipHashTableCount,
2984 qdev->nvram_data.ipHashTableSize);
2985 ql_write_page2_reg(qdev,
2986 &local_ram->tcpHashTableBase,
2987 (qdev->nvram_data.tcpHashTableBaseHi << 16) |
2988 qdev->nvram_data.tcpHashTableBaseLo);
2989 ql_write_page2_reg(qdev,
2990 &local_ram->tcpHashTableCount,
2991 qdev->nvram_data.tcpHashTableSize);
2992 ql_write_page2_reg(qdev,
2993 &local_ram->ncbBase,
2994 (qdev->nvram_data.ncbTableBaseHi << 16) |
2995 qdev->nvram_data.ncbTableBaseLo);
2996 ql_write_page2_reg(qdev,
2997 &local_ram->maxNcbCount,
2998 qdev->nvram_data.ncbTableSize);
2999 ql_write_page2_reg(qdev,
3000 &local_ram->drbBase,
3001 (qdev->nvram_data.drbTableBaseHi << 16) |
3002 qdev->nvram_data.drbTableBaseLo);
3003 ql_write_page2_reg(qdev,
3004 &local_ram->maxDrbCount,
3005 qdev->nvram_data.drbTableSize);
3006 ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK);
3007 return 0;
3008}
3009
3010static int ql_adapter_initialize(struct ql3_adapter *qdev)
3011{
3012 u32 value;
d7f61777
JP		 3013 struct ql3xxx_port_registers __iomem *port_regs =
3014 qdev->mem_map_registers;
6f2e154b 3015 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
5a4faa87 3016 struct ql3xxx_host_memory_registers __iomem *hmem_regs =
d7f61777 3017 (void __iomem *)port_regs;
5a4faa87
RM		 3018 u32 delay = 10;
3019 int status = 0;
0f77ca92 3020 unsigned long hw_flags = 0;
5a4faa87 3021
d7f61777 3022 if (ql_mii_setup(qdev))
5a4faa87
RM		 3023 return -1;
3024
3025 /* Bring out PHY out of reset */
d7f61777 3026 ql_write_common_reg(qdev, spir,
5a4faa87
RM		 3027 (ISP_SERIAL_PORT_IF_WE |
3028 (ISP_SERIAL_PORT_IF_WE << 16)));
e5a67374
RM		 3029 /* Give the PHY time to come out of reset. */
3030 mdelay(100);
5a4faa87
RM		 3031 qdev->port_link_state = LS_DOWN;
3032 netif_carrier_off(qdev->ndev);
3033
3034 /* V2 chip fix for ARS-39168. */
d7f61777 3035 ql_write_common_reg(qdev, spir,
5a4faa87
RM		 3036 (ISP_SERIAL_PORT_IF_SDE |
3037 (ISP_SERIAL_PORT_IF_SDE << 16)));
3038
3039 /* Request Queue Registers */
d7f61777
JP		 3040 *((u32 *)(qdev->preq_consumer_index)) = 0;
3041 atomic_set(&qdev->tx_count, NUM_REQ_Q_ENTRIES);
5a4faa87
RM		 3042 qdev->req_producer_index = 0;
3043
3044 ql_write_page1_reg(qdev,
3045 &hmem_regs->reqConsumerIndexAddrHigh,
3046 qdev->req_consumer_index_phy_addr_high);
3047 ql_write_page1_reg(qdev,
3048 &hmem_regs->reqConsumerIndexAddrLow,
3049 qdev->req_consumer_index_phy_addr_low);
3050
3051 ql_write_page1_reg(qdev,
3052 &hmem_regs->reqBaseAddrHigh,
3053 MS_64BITS(qdev->req_q_phy_addr));
3054 ql_write_page1_reg(qdev,
3055 &hmem_regs->reqBaseAddrLow,
3056 LS_64BITS(qdev->req_q_phy_addr));
3057 ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES);
3058
3059 /* Response Queue Registers */
804d8541 3060 *((__le16 *) (qdev->prsp_producer_index)) = 0;
5a4faa87
RM		 3061 qdev->rsp_consumer_index = 0;
3062 qdev->rsp_current = qdev->rsp_q_virt_addr;
3063
3064 ql_write_page1_reg(qdev,
3065 &hmem_regs->rspProducerIndexAddrHigh,
3066 qdev->rsp_producer_index_phy_addr_high);
3067
3068 ql_write_page1_reg(qdev,
3069 &hmem_regs->rspProducerIndexAddrLow,
3070 qdev->rsp_producer_index_phy_addr_low);
3071
3072 ql_write_page1_reg(qdev,
3073 &hmem_regs->rspBaseAddrHigh,
3074 MS_64BITS(qdev->rsp_q_phy_addr));
3075
3076 ql_write_page1_reg(qdev,
3077 &hmem_regs->rspBaseAddrLow,
3078 LS_64BITS(qdev->rsp_q_phy_addr));
3079
3080 ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES);
3081
3082 /* Large Buffer Queue */
3083 ql_write_page1_reg(qdev,
3084 &hmem_regs->rxLargeQBaseAddrHigh,
3085 MS_64BITS(qdev->lrg_buf_q_phy_addr));
3086
3087 ql_write_page1_reg(qdev,
3088 &hmem_regs->rxLargeQBaseAddrLow,
3089 LS_64BITS(qdev->lrg_buf_q_phy_addr));
3090
d7f61777
JP		 3091 ql_write_page1_reg(qdev,
3092 &hmem_regs->rxLargeQLength,
3093 qdev->num_lbufq_entries);
5a4faa87
RM		 3094
3095 ql_write_page1_reg(qdev,
3096 &hmem_regs->rxLargeBufferLength,
3097 qdev->lrg_buffer_len);
3098
3099 /* Small Buffer Queue */
3100 ql_write_page1_reg(qdev,
3101 &hmem_regs->rxSmallQBaseAddrHigh,
3102 MS_64BITS(qdev->small_buf_q_phy_addr));
3103
3104 ql_write_page1_reg(qdev,
3105 &hmem_regs->rxSmallQBaseAddrLow,
3106 LS_64BITS(qdev->small_buf_q_phy_addr));
3107
3108 ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES);
3109 ql_write_page1_reg(qdev,
3110 &hmem_regs->rxSmallBufferLength,
3111 QL_SMALL_BUFFER_SIZE);
3112
3113 qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1;
3114 qdev->small_buf_release_cnt = 8;
1357bfcf 3115 qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1;
5a4faa87
RM		 3116 qdev->lrg_buf_release_cnt = 8;
3117 qdev->lrg_buf_next_free =
3118 (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr;
3119 qdev->small_buf_index = 0;
3120 qdev->lrg_buf_index = 0;
3121 qdev->lrg_buf_free_count = 0;
3122 qdev->lrg_buf_free_head = NULL;
3123 qdev->lrg_buf_free_tail = NULL;
3124
3125 ql_write_common_reg(qdev,
ee111d11 3126 &port_regs->CommonRegs.
5a4faa87
RM		 3127 rxSmallQProducerIndex,
3128 qdev->small_buf_q_producer_index);
3129 ql_write_common_reg(qdev,
ee111d11 3130 &port_regs->CommonRegs.
5a4faa87
RM		 3131 rxLargeQProducerIndex,
3132 qdev->lrg_buf_q_producer_index);
3133
3134 /*
3135 * Find out if the chip has already been initialized. If it has, then
3136 * we skip some of the initialization.
3137 */
3138 clear_bit(QL_LINK_MASTER, &qdev->flags);
3139 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3140 if ((value & PORT_STATUS_IC) == 0) {
3141
3142 /* Chip has not been configured yet, so let it rip. */
d7f61777 3143 if (ql_init_misc_registers(qdev)) {
5a4faa87
RM		 3144 status = -1;
3145 goto out;
3146 }
3147
5a4faa87
RM		 3148 value = qdev->nvram_data.tcpMaxWindowSize;
3149 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3150
3151 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3152
d7f61777 3153 if (ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK,
5a4faa87
RM		 3154 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index)
3155 * 2) << 13)) {
3156 status = -1;
3157 goto out;
3158 }
3159 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3160 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3161 (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) <<
3162 16) | (INTERNAL_CHIP_SD |
3163 INTERNAL_CHIP_WE)));
3164 ql_sem_unlock(qdev, QL_FLASH_SEM_MASK);
3165 }
3166
b3b1514c
RM		 3167 if (qdev->mac_index)
3168 ql_write_page0_reg(qdev,
3169 &port_regs->mac1MaxFrameLengthReg,
3170 qdev->max_frame_size);
3171 else
3172 ql_write_page0_reg(qdev,
3173 &port_regs->mac0MaxFrameLengthReg,
3174 qdev->max_frame_size);
5a4faa87 3175
d7f61777 3176 if (ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK,
5a4faa87
RM		 3177 (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
3178 2) << 7)) {
3179 status = -1;
3180 goto out;
3181 }
3182
3efedf2e 3183 PHY_Setup(qdev);
5a4faa87
RM		 3184 ql_init_scan_mode(qdev);
3185 ql_get_phy_owner(qdev);
3186
3187 /* Load the MAC Configuration */
3188
3189 /* Program lower 32 bits of the MAC address */
3190 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3191 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3192 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3193 ((qdev->ndev->dev_addr[2] << 24)
3194 | (qdev->ndev->dev_addr[3] << 16)
3195 | (qdev->ndev->dev_addr[4] << 8)
3196 | qdev->ndev->dev_addr[5]));
3197
3198 /* Program top 16 bits of the MAC address */
3199 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3200 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3201 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3202 ((qdev->ndev->dev_addr[0] << 8)
3203 | qdev->ndev->dev_addr[1]));
3204
3205 /* Enable Primary MAC */
3206 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3207 ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) |
3208 MAC_ADDR_INDIRECT_PTR_REG_PE));
3209
3210 /* Clear Primary and Secondary IP addresses */
3211 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3212 ((IP_ADDR_INDEX_REG_MASK << 16) |
3213 (qdev->mac_index << 2)));
3214 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3215
3216 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3217 ((IP_ADDR_INDEX_REG_MASK << 16) |
3218 ((qdev->mac_index << 2) + 1)));
3219 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3220
3221 ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK);
3222
3223 /* Indicate Configuration Complete */
3224 ql_write_page0_reg(qdev,
3225 &port_regs->portControl,
3226 ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC));
3227
3228 do {
3229 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3230 if (value & PORT_STATUS_IC)
3231 break;
0f77ca92 3232 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 3233 msleep(500);
0f77ca92 3234 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
5a4faa87
RM		 3235 } while (--delay);
3236
3237 if (delay == 0) {
eddc5fbd 3238 netdev_err(qdev->ndev, "Hw Initialization timeout\n");
5a4faa87
RM		 3239 status = -1;
3240 goto out;
3241 }
3242
3243 /* Enable Ethernet Function */
bd36b0ac
RM		 3244 if (qdev->device_id == QL3032_DEVICE_ID) {
3245 value =
3246 (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE |
b3b1514c
RM		 3247 QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 |
3248 QL3032_PORT_CONTROL_ET);
bd36b0ac
RM		 3249 ql_write_page0_reg(qdev, &port_regs->functionControl,
3250 ((value << 16) | value));
3251 } else {
3252 value =
3253 (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI |
3254 PORT_CONTROL_HH);
3255 ql_write_page0_reg(qdev, &port_regs->portControl,
3256 ((value << 16) | value));
3257 }
3258
5a4faa87
RM		 3259
3260out:
3261 return status;
3262}
3263
3264/*
3265 * Caller holds hw_lock.
3266 */
3267static int ql_adapter_reset(struct ql3_adapter *qdev)
3268{
d7f61777
JP		 3269 struct ql3xxx_port_registers __iomem *port_regs =
3270 qdev->mem_map_registers;
5a4faa87
RM		 3271 int status = 0;
3272 u16 value;
3273 int max_wait_time;
3274
3275 set_bit(QL_RESET_ACTIVE, &qdev->flags);
3276 clear_bit(QL_RESET_DONE, &qdev->flags);
3277
3278 /*
3279 * Issue soft reset to chip.
3280 */
eddc5fbd 3281 netdev_printk(KERN_DEBUG, qdev->ndev, "Issue soft reset to chip\n");
5a4faa87 3282 ql_write_common_reg(qdev,
ee111d11 3283 &port_regs->CommonRegs.ispControlStatus,
5a4faa87
RM		 3284 ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
3285
3286 /* Wait 3 seconds for reset to complete. */
eddc5fbd
JP		 3287 netdev_printk(KERN_DEBUG, qdev->ndev,
3288 "Wait 10 milliseconds for reset to complete\n");
5a4faa87
RM		 3289
3290 /* Wait until the firmware tells us the Soft Reset is done */
3291 max_wait_time = 5;
3292 do {
3293 value =
3294 ql_read_common_reg(qdev,
3295 &port_regs->CommonRegs.ispControlStatus);
3296 if ((value & ISP_CONTROL_SR) == 0)
3297 break;
3298
3299 ssleep(1);
3300 } while ((--max_wait_time));
3301
3302 /*
3303 * Also, make sure that the Network Reset Interrupt bit has been
3304 * cleared after the soft reset has taken place.
3305 */
3306 value =
3307 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3308 if (value & ISP_CONTROL_RI) {
eddc5fbd
JP		 3309 netdev_printk(KERN_DEBUG, qdev->ndev,
3310 "clearing RI after reset\n");
5a4faa87 3311 ql_write_common_reg(qdev,
ee111d11 3312 &port_regs->CommonRegs.
5a4faa87
RM		 3313 ispControlStatus,
3314 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3315 }
3316
3317 if (max_wait_time == 0) {
3318 /* Issue Force Soft Reset */
3319 ql_write_common_reg(qdev,
ee111d11 3320 &port_regs->CommonRegs.
5a4faa87
RM		 3321 ispControlStatus,
3322 ((ISP_CONTROL_FSR << 16) |
3323 ISP_CONTROL_FSR));
3324 /*
3325 * Wait until the firmware tells us the Force Soft Reset is
3326 * done
3327 */
3328 max_wait_time = 5;
3329 do {
d7f61777
JP		 3330 value = ql_read_common_reg(qdev,
3331 &port_regs->CommonRegs.
3332 ispControlStatus);
3333 if ((value & ISP_CONTROL_FSR) == 0)
5a4faa87 3334 break;
5a4faa87
RM		 3335 ssleep(1);
3336 } while ((--max_wait_time));
3337 }
3338 if (max_wait_time == 0)
3339 status = 1;
3340
3341 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3342 set_bit(QL_RESET_DONE, &qdev->flags);
3343 return status;
3344}
3345
3346static void ql_set_mac_info(struct ql3_adapter *qdev)
3347{
d7f61777
JP		 3348 struct ql3xxx_port_registers __iomem *port_regs =
3349 qdev->mem_map_registers;
5a4faa87
RM		 3350 u32 value, port_status;
3351 u8 func_number;
3352
3353 /* Get the function number */
3354 value =
3355 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3356 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3357 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3358 switch (value & ISP_CONTROL_FN_MASK) {
3359 case ISP_CONTROL_FN0_NET:
3360 qdev->mac_index = 0;
3361 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
5a4faa87
RM		 3362 qdev->mb_bit_mask = FN0_MA_BITS_MASK;
3363 qdev->PHYAddr = PORT0_PHY_ADDRESS;
3364 if (port_status & PORT_STATUS_SM0)
d7f61777 3365 set_bit(QL_LINK_OPTICAL, &qdev->flags);
5a4faa87 3366 else
d7f61777 3367 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
5a4faa87
RM		 3368 break;
3369
3370 case ISP_CONTROL_FN1_NET:
3371 qdev->mac_index = 1;
3372 qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number;
5a4faa87
RM		 3373 qdev->mb_bit_mask = FN1_MA_BITS_MASK;
3374 qdev->PHYAddr = PORT1_PHY_ADDRESS;
3375 if (port_status & PORT_STATUS_SM1)
d7f61777 3376 set_bit(QL_LINK_OPTICAL, &qdev->flags);
5a4faa87 3377 else
d7f61777 3378 clear_bit(QL_LINK_OPTICAL, &qdev->flags);
5a4faa87
RM		 3379 break;
3380
3381 case ISP_CONTROL_FN0_SCSI:
3382 case ISP_CONTROL_FN1_SCSI:
3383 default:
eddc5fbd
JP		 3384 netdev_printk(KERN_DEBUG, qdev->ndev,
3385 "Invalid function number, ispControlStatus = 0x%x\n",
3386 value);
5a4faa87
RM		 3387 break;
3388 }
804d8541 3389 qdev->numPorts = qdev->nvram_data.version_and_numPorts >> 8;
5a4faa87
RM		 3390}
3391
3392static void ql_display_dev_info(struct net_device *ndev)
3393{
4dd15187 3394 struct ql3_adapter *qdev = netdev_priv(ndev);
5a4faa87
RM		 3395 struct pci_dev *pdev = qdev->pdev;
3396
eddc5fbd
JP		 3397 netdev_info(ndev,
3398 "%s Adapter %d RevisionID %d found %s on PCI slot %d\n",
3399 DRV_NAME, qdev->index, qdev->chip_rev_id,
d7f61777 3400 qdev->device_id == QL3032_DEVICE_ID ? "QLA3032" : "QLA3022",
eddc5fbd
JP		 3401 qdev->pci_slot);
3402 netdev_info(ndev, "%s Interface\n",
3403 test_bit(QL_LINK_OPTICAL, &qdev->flags) ? "OPTICAL" : "COPPER");
5a4faa87
RM		 3404
3405 /*
3406 * Print PCI bus width/type.
3407 */
eddc5fbd
JP		 3408 netdev_info(ndev, "Bus interface is %s %s\n",
3409 ((qdev->pci_width == 64) ? "64-bit" : "32-bit"),
3410 ((qdev->pci_x) ? "PCI-X" : "PCI"));
5a4faa87 3411
eddc5fbd
JP		 3412 netdev_info(ndev, "mem IO base address adjusted = 0x%p\n",
3413 qdev->mem_map_registers);
3414 netdev_info(ndev, "Interrupt number = %d\n", pdev->irq);
5a4faa87 3415
eddc5fbd 3416 netif_info(qdev, probe, ndev, "MAC address %pM\n", ndev->dev_addr);
5a4faa87
RM		 3417}
3418
3419static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset)
3420{
3421 struct net_device *ndev = qdev->ndev;
3422 int retval = 0;
3423
3424 netif_stop_queue(ndev);
3425 netif_carrier_off(ndev);
3426
d7f61777
JP		 3427 clear_bit(QL_ADAPTER_UP, &qdev->flags);
3428 clear_bit(QL_LINK_MASTER, &qdev->flags);
5a4faa87
RM		 3429
3430 ql_disable_interrupts(qdev);
3431
3432 free_irq(qdev->pdev->irq, ndev);
3433
d7f61777 3434 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
eddc5fbd 3435 netdev_info(qdev->ndev, "calling pci_disable_msi()\n");
d7f61777 3436 clear_bit(QL_MSI_ENABLED, &qdev->flags);
5a4faa87
RM		 3437 pci_disable_msi(qdev->pdev);
3438 }
3439
3440 del_timer_sync(&qdev->adapter_timer);
3441
bea3348e 3442 napi_disable(&qdev->napi);
5a4faa87
RM		 3443
3444 if (do_reset) {
3445 int soft_reset;
3446 unsigned long hw_flags;
3447
3448 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3449 if (ql_wait_for_drvr_lock(qdev)) {
d7f61777
JP		 3450 soft_reset = ql_adapter_reset(qdev);
3451 if (soft_reset) {
eddc5fbd
JP		 3452 netdev_err(ndev, "ql_adapter_reset(%d) FAILED!\n",
3453 qdev->index);
5a4faa87 3454 }
eddc5fbd
JP		 3455 netdev_err(ndev,
3456 "Releasing driver lock via chip reset\n");
5a4faa87 3457 } else {
eddc5fbd
JP		 3458 netdev_err(ndev,
3459 "Could not acquire driver lock to do reset!\n");
5a4faa87
RM		 3460 retval = -1;
3461 }
3462 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3463 }
3464 ql_free_mem_resources(qdev);
3465 return retval;
3466}
3467
3468static int ql_adapter_up(struct ql3_adapter *qdev)
3469{
3470 struct net_device *ndev = qdev->ndev;
3471 int err;
ab392d2d 3472 unsigned long irq_flags = IRQF_SHARED;
5a4faa87
RM		 3473 unsigned long hw_flags;
3474
3475 if (ql_alloc_mem_resources(qdev)) {
eddc5fbd 3476 netdev_err(ndev, "Unable to allocate buffers\n");
5a4faa87
RM		 3477 return -ENOMEM;
3478 }
3479
3480 if (qdev->msi) {
3481 if (pci_enable_msi(qdev->pdev)) {
eddc5fbd
JP		 3482 netdev_err(ndev,
3483 "User requested MSI, but MSI failed to initialize. Continuing without MSI.\n");
5a4faa87
RM		 3484 qdev->msi = 0;
3485 } else {
eddc5fbd 3486 netdev_info(ndev, "MSI Enabled...\n");
d7f61777 3487 set_bit(QL_MSI_ENABLED, &qdev->flags);
38515e90 3488 irq_flags &= ~IRQF_SHARED;
5a4faa87
RM		 3489 }
3490 }
3491
d7f61777
JP		 3492 err = request_irq(qdev->pdev->irq, ql3xxx_isr,
3493 irq_flags, ndev->name, ndev);
3494 if (err) {
eddc5fbd 3495 netdev_err(ndev,
d7f61777 3496 "Failed to reserve interrupt %d - already in use\n",
eddc5fbd 3497 qdev->pdev->irq);
5a4faa87
RM		 3498 goto err_irq;
3499 }
3500
3501 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3502
d7f61777
JP		 3503 err = ql_wait_for_drvr_lock(qdev);
3504 if (err) {
3505 err = ql_adapter_initialize(qdev);
3506 if (err) {
eddc5fbd 3507 netdev_err(ndev, "Unable to initialize adapter\n");
5a4faa87
RM		 3508 goto err_init;
3509 }
eddc5fbd 3510 netdev_err(ndev, "Releasing driver lock\n");
5a4faa87
RM		 3511 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3512 } else {
eddc5fbd 3513 netdev_err(ndev, "Could not acquire driver lock\n");
5a4faa87
RM		 3514 goto err_lock;
3515 }
3516
3517 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3518
d7f61777 3519 set_bit(QL_ADAPTER_UP, &qdev->flags);
5a4faa87
RM		 3520
3521 mod_timer(&qdev->adapter_timer, jiffies + HZ * 1);
3522
bea3348e 3523 napi_enable(&qdev->napi);
5a4faa87
RM		 3524 ql_enable_interrupts(qdev);
3525 return 0;
3526
3527err_init:
3528 ql_sem_unlock(qdev, QL_DRVR_SEM_MASK);
3529err_lock:
04f10773 3530 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87
RM		 3531 free_irq(qdev->pdev->irq, ndev);
3532err_irq:
d7f61777 3533 if (qdev->msi && test_bit(QL_MSI_ENABLED, &qdev->flags)) {
eddc5fbd 3534 netdev_info(ndev, "calling pci_disable_msi()\n");
d7f61777 3535 clear_bit(QL_MSI_ENABLED, &qdev->flags);
5a4faa87
RM		 3536 pci_disable_msi(qdev->pdev);
3537 }
3538 return err;
3539}
3540
3541static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset)
3542{
d7f61777 3543 if (ql_adapter_down(qdev, reset) || ql_adapter_up(qdev)) {
eddc5fbd
JP		 3544 netdev_err(qdev->ndev,
3545 "Driver up/down cycle failed, closing device\n");
c81ec80b 3546 rtnl_lock();
5a4faa87 3547 dev_close(qdev->ndev);
c81ec80b 3548 rtnl_unlock();
5a4faa87
RM		 3549 return -1;
3550 }
3551 return 0;
3552}
3553
3554static int ql3xxx_close(struct net_device *ndev)
3555{
3556 struct ql3_adapter *qdev = netdev_priv(ndev);
3557
3558 /*
3559 * Wait for device to recover from a reset.
3560 * (Rarely happens, but possible.)
3561 */
d7f61777 3562 while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
5a4faa87
RM		 3563 msleep(50);
3564
d7f61777 3565 ql_adapter_down(qdev, QL_DO_RESET);
5a4faa87
RM		 3566 return 0;
3567}
3568
3569static int ql3xxx_open(struct net_device *ndev)
3570{
3571 struct ql3_adapter *qdev = netdev_priv(ndev);
d7f61777 3572 return ql_adapter_up(qdev);
5a4faa87
RM		 3573}
3574
5a4faa87
RM		 3575static int ql3xxx_set_mac_address(struct net_device *ndev, void *p)
3576{
4dd15187 3577 struct ql3_adapter *qdev = netdev_priv(ndev);
5a4faa87 3578 struct ql3xxx_port_registers __iomem *port_regs =
d7f61777 3579 qdev->mem_map_registers;
5a4faa87
RM		 3580 struct sockaddr *addr = p;
3581 unsigned long hw_flags;
3582
3583 if (netif_running(ndev))
3584 return -EBUSY;
3585
3586 if (!is_valid_ether_addr(addr->sa_data))
3587 return -EADDRNOTAVAIL;
3588
3589 memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3590
3591 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3592 /* Program lower 32 bits of the MAC address */
3593 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3594 (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16));
3595 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3596 ((ndev->dev_addr[2] << 24) | (ndev->
3597 dev_addr[3] << 16) |
3598 (ndev->dev_addr[4] << 8) | ndev->dev_addr[5]));
3599
3600 /* Program top 16 bits of the MAC address */
3601 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3602 ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1));
3603 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3604 ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1]));
3605 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3606
3607 return 0;
3608}
3609
3610static void ql3xxx_tx_timeout(struct net_device *ndev)
3611{
4dd15187 3612 struct ql3_adapter *qdev = netdev_priv(ndev);
5a4faa87 3613
eddc5fbd 3614 netdev_err(ndev, "Resetting...\n");
5a4faa87
RM		 3615 /*
3616 * Stop the queues, we've got a problem.
3617 */
3618 netif_stop_queue(ndev);
3619
3620 /*
3621 * Wake up the worker to process this event.
3622 */
c4028958 3623 queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
5a4faa87
RM		 3624}
3625
c4028958 3626static void ql_reset_work(struct work_struct *work)
5a4faa87 3627{
c4028958
DH		 3628 struct ql3_adapter *qdev =
3629 container_of(work, struct ql3_adapter, reset_work.work);
5a4faa87
RM		 3630 struct net_device *ndev = qdev->ndev;
3631 u32 value;
3632 struct ql_tx_buf_cb *tx_cb;
3633 int max_wait_time, i;
d7f61777
JP		 3634 struct ql3xxx_port_registers __iomem *port_regs =
3635 qdev->mem_map_registers;
5a4faa87
RM		 3636 unsigned long hw_flags;
3637
d7f61777
JP		 3638 if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START), &qdev->flags)) {
3639 clear_bit(QL_LINK_MASTER, &qdev->flags);
5a4faa87
RM		 3640
3641 /*
3642 * Loop through the active list and return the skb.
3643 */
3644 for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) {
bd36b0ac 3645 int j;
5a4faa87
RM		 3646 tx_cb = &qdev->tx_buf[i];
3647 if (tx_cb->skb) {
eddc5fbd
JP		 3648 netdev_printk(KERN_DEBUG, ndev,
3649 "Freeing lost SKB\n");
5a4faa87 3650 pci_unmap_single(qdev->pdev,
d7f61777
JP		 3651 dma_unmap_addr(&tx_cb->map[0],
3652 mapaddr),
87196eb7 3653 dma_unmap_len(&tx_cb->map[0], maplen),
bd36b0ac 3654 PCI_DMA_TODEVICE);
d7f61777 3655 for (j = 1; j < tx_cb->seg_count; j++) {
bd36b0ac 3656 pci_unmap_page(qdev->pdev,
d7f61777
JP		 3657 dma_unmap_addr(&tx_cb->map[j],
3658 mapaddr),
3659 dma_unmap_len(&tx_cb->map[j],
3660 maplen),
bd36b0ac
RM		 3661 PCI_DMA_TODEVICE);
3662 }
5a4faa87
RM		 3663 dev_kfree_skb(tx_cb->skb);
3664 tx_cb->skb = NULL;
3665 }
3666 }
3667
eddc5fbd 3668 netdev_err(ndev, "Clearing NRI after reset\n");
5a4faa87
RM		 3669 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
3670 ql_write_common_reg(qdev,
3671 &port_regs->CommonRegs.
3672 ispControlStatus,
3673 ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
3674 /*
3675 * Wait the for Soft Reset to Complete.
3676 */
3677 max_wait_time = 10;
3678 do {
3679 value = ql_read_common_reg(qdev,
3680 &port_regs->CommonRegs.
3681
3682 ispControlStatus);
3683 if ((value & ISP_CONTROL_SR) == 0) {
eddc5fbd
JP		 3684 netdev_printk(KERN_DEBUG, ndev,
3685 "reset completed\n");
5a4faa87
RM		 3686 break;
3687 }
3688
3689 if (value & ISP_CONTROL_RI) {
eddc5fbd
JP		 3690 netdev_printk(KERN_DEBUG, ndev,
3691 "clearing NRI after reset\n");
5a4faa87 3692 ql_write_common_reg(qdev,
ee111d11 3693 &port_regs->
5a4faa87
RM		 3694 CommonRegs.
3695 ispControlStatus,
3696 ((ISP_CONTROL_RI <<
3697 16) | ISP_CONTROL_RI));
3698 }
3699
83b462c6 3700 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
5a4faa87 3701 ssleep(1);
83b462c6 3702 spin_lock_irqsave(&qdev->hw_lock, hw_flags);
5a4faa87
RM		 3703 } while (--max_wait_time);
3704 spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
3705
3706 if (value & ISP_CONTROL_SR) {
3707
3708 /*
3709 * Set the reset flags and clear the board again.
3710 * Nothing else to do...
3711 */
eddc5fbd
JP		 3712 netdev_err(ndev,
3713 "Timed out waiting for reset to complete\n");
3714 netdev_err(ndev, "Do a reset\n");
d7f61777
JP		 3715 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3716 clear_bit(QL_RESET_START, &qdev->flags);
3717 ql_cycle_adapter(qdev, QL_DO_RESET);
5a4faa87
RM		 3718 return;
3719 }
3720
d7f61777
JP		 3721 clear_bit(QL_RESET_ACTIVE, &qdev->flags);
3722 clear_bit(QL_RESET_PER_SCSI, &qdev->flags);
3723 clear_bit(QL_RESET_START, &qdev->flags);
3724 ql_cycle_adapter(qdev, QL_NO_RESET);
5a4faa87
RM		 3725 }
3726}
3727
c4028958 3728static void ql_tx_timeout_work(struct work_struct *work)
5a4faa87 3729{
c4028958
DH		 3730 struct ql3_adapter *qdev =
3731 container_of(work, struct ql3_adapter, tx_timeout_work.work);
3732
3733 ql_cycle_adapter(qdev, QL_DO_RESET);
5a4faa87
RM		 3734}
3735
3736static void ql_get_board_info(struct ql3_adapter *qdev)
3737{
d7f61777
JP		 3738 struct ql3xxx_port_registers __iomem *port_regs =
3739 qdev->mem_map_registers;
5a4faa87
RM		 3740 u32 value;
3741
3742 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3743
3744 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3745 if (value & PORT_STATUS_64)
3746 qdev->pci_width = 64;
3747 else
3748 qdev->pci_width = 32;
3749 if (value & PORT_STATUS_X)
3750 qdev->pci_x = 1;
3751 else
3752 qdev->pci_x = 0;
3753 qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn);
3754}
3755
3756static void ql3xxx_timer(unsigned long ptr)
3757{
3758 struct ql3_adapter *qdev = (struct ql3_adapter *)ptr;
3e23b7d3 3759 queue_delayed_work(qdev->workqueue, &qdev->link_state_work, 0);
5a4faa87
RM		 3760}
3761
da1c14a1
SH		 3762static const struct net_device_ops ql3xxx_netdev_ops = {
3763 .ndo_open = ql3xxx_open,
3764 .ndo_start_xmit = ql3xxx_send,
3765 .ndo_stop = ql3xxx_close,
3766 .ndo_set_multicast_list = NULL, /* not allowed on NIC side */
3767 .ndo_change_mtu = eth_change_mtu,
3768 .ndo_validate_addr = eth_validate_addr,
3769 .ndo_set_mac_address = ql3xxx_set_mac_address,
3770 .ndo_tx_timeout = ql3xxx_tx_timeout,
3771};
3772
5a4faa87
RM		 3773static int __devinit ql3xxx_probe(struct pci_dev *pdev,
3774 const struct pci_device_id *pci_entry)
3775{
3776 struct net_device *ndev = NULL;
3777 struct ql3_adapter *qdev = NULL;
d7f61777 3778 static int cards_found;
be5a3c62 3779 int uninitialized_var(pci_using_dac), err;
5a4faa87
RM		 3780
3781 err = pci_enable_device(pdev);
3782 if (err) {
eddc5fbd 3783 pr_err("%s cannot enable PCI device\n", pci_name(pdev));
5a4faa87
RM		 3784 goto err_out;
3785 }
3786
3787 err = pci_request_regions(pdev, DRV_NAME);
3788 if (err) {
eddc5fbd 3789 pr_err("%s cannot obtain PCI resources\n", pci_name(pdev));
5a4faa87
RM		 3790 goto err_out_disable_pdev;
3791 }
3792
3793 pci_set_master(pdev);
3794
6a35528a 3795 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
5a4faa87 3796 pci_using_dac = 1;
6a35528a 3797 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
284901a9 3798 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
5a4faa87 3799 pci_using_dac = 0;
284901a9 3800 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5a4faa87
RM		 3801 }
3802
3803 if (err) {
eddc5fbd 3804 pr_err("%s no usable DMA configuration\n", pci_name(pdev));
5a4faa87
RM		 3805 goto err_out_free_regions;
3806 }
3807
3808 ndev = alloc_etherdev(sizeof(struct ql3_adapter));
546faf07 3809 if (!ndev) {
eddc5fbd 3810 pr_err("%s could not alloc etherdev\n", pci_name(pdev));
546faf07 3811 err = -ENOMEM;
5a4faa87 3812 goto err_out_free_regions;
546faf07 3813 }
5a4faa87 3814
5a4faa87
RM		 3815 SET_NETDEV_DEV(ndev, &pdev->dev);
3816
5a4faa87
RM		 3817 pci_set_drvdata(pdev, ndev);
3818
3819 qdev = netdev_priv(ndev);
3820 qdev->index = cards_found;
3821 qdev->ndev = ndev;
3822 qdev->pdev = pdev;
bd36b0ac 3823 qdev->device_id = pci_entry->device;
5a4faa87
RM		 3824 qdev->port_link_state = LS_DOWN;
3825 if (msi)
3826 qdev->msi = 1;
3827
3828 qdev->msg_enable = netif_msg_init(debug, default_msg);
3829
bd36b0ac
RM		 3830 if (pci_using_dac)
3831 ndev->features |= NETIF_F_HIGHDMA;
3832 if (qdev->device_id == QL3032_DEVICE_ID)
e68a8c10 3833 ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
bd36b0ac 3834
275f165f 3835 qdev->mem_map_registers = pci_ioremap_bar(pdev, 1);
5a4faa87 3836 if (!qdev->mem_map_registers) {
eddc5fbd 3837 pr_err("%s: cannot map device registers\n", pci_name(pdev));
546faf07 3838 err = -EIO;
5a4faa87
RM		 3839 goto err_out_free_ndev;
3840 }
3841
3842 spin_lock_init(&qdev->adapter_lock);
3843 spin_lock_init(&qdev->hw_lock);
3844
3845 /* Set driver entry points */
da1c14a1 3846 ndev->netdev_ops = &ql3xxx_netdev_ops;
5a4faa87 3847 SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops);
5a4faa87
RM		 3848 ndev->watchdog_timeo = 5 * HZ;
3849
bea3348e 3850 netif_napi_add(ndev, &qdev->napi, ql_poll, 64);
5a4faa87
RM		 3851
3852 ndev->irq = pdev->irq;
3853
3854 /* make sure the EEPROM is good */
3855 if (ql_get_nvram_params(qdev)) {
eddc5fbd
JP		 3856 pr_alert("%s: Adapter #%d, Invalid NVRAM parameters\n",
3857 __func__, qdev->index);
546faf07 3858 err = -EIO;
5a4faa87
RM		 3859 goto err_out_iounmap;
3860 }
3861
3862 ql_set_mac_info(qdev);
3863
3864 /* Validate and set parameters */
3865 if (qdev->mac_index) {
cb8bac12 3866 ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ;
804d8541 3867 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn2.macAddress);
5a4faa87 3868 } else {
cb8bac12 3869 ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ;
804d8541 3870 ql_set_mac_addr(ndev, qdev->nvram_data.funcCfg_fn0.macAddress);
5a4faa87
RM		 3871 }
3872 memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3873
3874 ndev->tx_queue_len = NUM_REQ_Q_ENTRIES;
3875
5a4faa87
RM		 3876 /* Record PCI bus information. */
3877 ql_get_board_info(qdev);
3878
3879 /*
3880 * Set the Maximum Memory Read Byte Count value. We do this to handle
3881 * jumbo frames.
3882 */
d7f61777 3883 if (qdev->pci_x)
5a4faa87 3884 pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036);
5a4faa87
RM		 3885
3886 err = register_netdev(ndev);
3887 if (err) {
eddc5fbd 3888 pr_err("%s: cannot register net device\n", pci_name(pdev));
5a4faa87
RM		 3889 goto err_out_iounmap;
3890 }
3891
3892 /* we're going to reset, so assume we have no link for now */
3893
3894 netif_carrier_off(ndev);
3895 netif_stop_queue(ndev);
3896
3897 qdev->workqueue = create_singlethread_workqueue(ndev->name);
c4028958
DH		 3898 INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
3899 INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
3e23b7d3 3900 INIT_DELAYED_WORK(&qdev->link_state_work, ql_link_state_machine_work);
5a4faa87
RM		 3901
3902 init_timer(&qdev->adapter_timer);
3903 qdev->adapter_timer.function = ql3xxx_timer;
3904 qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */
3905 qdev->adapter_timer.data = (unsigned long)qdev;
3906
eddc5fbd
JP		 3907 if (!cards_found) {
3908 pr_alert("%s\n", DRV_STRING);
3909 pr_alert("Driver name: %s, Version: %s\n",
3910 DRV_NAME, DRV_VERSION);
5a4faa87
RM		 3911 }
3912 ql_display_dev_info(ndev);
3913
3914 cards_found++;
3915 return 0;
3916
3917err_out_iounmap:
3918 iounmap(qdev->mem_map_registers);
3919err_out_free_ndev:
3920 free_netdev(ndev);
3921err_out_free_regions:
3922 pci_release_regions(pdev);
3923err_out_disable_pdev:
3924 pci_disable_device(pdev);
3925 pci_set_drvdata(pdev, NULL);
3926err_out:
3927 return err;
3928}
3929
3930static void __devexit ql3xxx_remove(struct pci_dev *pdev)
3931{
3932 struct net_device *ndev = pci_get_drvdata(pdev);
3933 struct ql3_adapter *qdev = netdev_priv(ndev);
3934
3935 unregister_netdev(ndev);
5a4faa87
RM		 3936
3937 ql_disable_interrupts(qdev);
3938
3939 if (qdev->workqueue) {
3940 cancel_delayed_work(&qdev->reset_work);
3941 cancel_delayed_work(&qdev->tx_timeout_work);
3942 destroy_workqueue(qdev->workqueue);
3943 qdev->workqueue = NULL;
3944 }
3945
855fc73b 3946 iounmap(qdev->mem_map_registers);
5a4faa87
RM		 3947 pci_release_regions(pdev);
3948 pci_set_drvdata(pdev, NULL);
3949 free_netdev(ndev);
3950}
3951
3952static struct pci_driver ql3xxx_driver = {
3953
3954 .name = DRV_NAME,
3955 .id_table = ql3xxx_pci_tbl,
3956 .probe = ql3xxx_probe,
3957 .remove = __devexit_p(ql3xxx_remove),
3958};
3959
3960static int __init ql3xxx_init_module(void)
3961{
3962 return pci_register_driver(&ql3xxx_driver);
3963}
3964
3965static void __exit ql3xxx_exit(void)
3966{
3967 pci_unregister_driver(&ql3xxx_driver);
3968}
3969
3970module_init(ql3xxx_init_module);
3971module_exit(ql3xxx_exit);
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