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Commit | Line | Data |
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5a4faa87 RM |
1 | /* |
2 | * QLogic QLA3xxx NIC HBA Driver | |
3 | * Copyright (c) 2003-2006 QLogic Corporation | |
4 | * | |
5 | * See LICENSE.qla3xxx for copyright and licensing details. | |
6 | */ | |
7 | ||
8 | #include <linux/kernel.h> | |
9 | #include <linux/init.h> | |
10 | #include <linux/types.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/list.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/dma-mapping.h> | |
15 | #include <linux/sched.h> | |
16 | #include <linux/slab.h> | |
17 | #include <linux/dmapool.h> | |
18 | #include <linux/mempool.h> | |
19 | #include <linux/spinlock.h> | |
20 | #include <linux/kthread.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/errno.h> | |
23 | #include <linux/ioport.h> | |
24 | #include <linux/ip.h> | |
bd36b0ac | 25 | #include <linux/in.h> |
5a4faa87 RM |
26 | #include <linux/if_arp.h> |
27 | #include <linux/if_ether.h> | |
28 | #include <linux/netdevice.h> | |
29 | #include <linux/etherdevice.h> | |
30 | #include <linux/ethtool.h> | |
31 | #include <linux/skbuff.h> | |
32 | #include <linux/rtnetlink.h> | |
33 | #include <linux/if_vlan.h> | |
5a4faa87 RM |
34 | #include <linux/delay.h> |
35 | #include <linux/mm.h> | |
36 | ||
37 | #include "qla3xxx.h" | |
38 | ||
39 | #define DRV_NAME "qla3xxx" | |
40 | #define DRV_STRING "QLogic ISP3XXX Network Driver" | |
201f27e6 | 41 | #define DRV_VERSION "v2.03.00-k4" |
5a4faa87 RM |
42 | #define PFX DRV_NAME " " |
43 | ||
44 | static const char ql3xxx_driver_name[] = DRV_NAME; | |
45 | static const char ql3xxx_driver_version[] = DRV_VERSION; | |
46 | ||
47 | MODULE_AUTHOR("QLogic Corporation"); | |
48 | MODULE_DESCRIPTION("QLogic ISP3XXX Network Driver " DRV_VERSION " "); | |
49 | MODULE_LICENSE("GPL"); | |
50 | MODULE_VERSION(DRV_VERSION); | |
51 | ||
52 | static const u32 default_msg | |
53 | = NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | |
54 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; | |
55 | ||
56 | static int debug = -1; /* defaults above */ | |
57 | module_param(debug, int, 0); | |
58 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
59 | ||
60 | static int msi; | |
61 | module_param(msi, int, 0); | |
62 | MODULE_PARM_DESC(msi, "Turn on Message Signaled Interrupts."); | |
63 | ||
64 | static struct pci_device_id ql3xxx_pci_tbl[] __devinitdata = { | |
65 | {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3022_DEVICE_ID)}, | |
bd36b0ac | 66 | {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QL3032_DEVICE_ID)}, |
5a4faa87 RM |
67 | /* required last entry */ |
68 | {0,} | |
69 | }; | |
70 | ||
71 | MODULE_DEVICE_TABLE(pci, ql3xxx_pci_tbl); | |
72 | ||
3efedf2e RM |
73 | /* |
74 | * These are the known PHY's which are used | |
75 | */ | |
76 | typedef enum { | |
77 | PHY_TYPE_UNKNOWN = 0, | |
78 | PHY_VITESSE_VSC8211, | |
79 | PHY_AGERE_ET1011C, | |
80 | MAX_PHY_DEV_TYPES | |
81 | } PHY_DEVICE_et; | |
82 | ||
83 | typedef struct { | |
84 | PHY_DEVICE_et phyDevice; | |
85 | u32 phyIdOUI; | |
86 | u16 phyIdModel; | |
87 | char *name; | |
88 | } PHY_DEVICE_INFO_t; | |
89 | ||
b1fc1fa9 | 90 | static const PHY_DEVICE_INFO_t PHY_DEVICES[] = |
3efedf2e RM |
91 | {{PHY_TYPE_UNKNOWN, 0x000000, 0x0, "PHY_TYPE_UNKNOWN"}, |
92 | {PHY_VITESSE_VSC8211, 0x0003f1, 0xb, "PHY_VITESSE_VSC8211"}, | |
93 | {PHY_AGERE_ET1011C, 0x00a0bc, 0x1, "PHY_AGERE_ET1011C"}, | |
94 | }; | |
95 | ||
96 | ||
5a4faa87 RM |
97 | /* |
98 | * Caller must take hw_lock. | |
99 | */ | |
100 | static int ql_sem_spinlock(struct ql3_adapter *qdev, | |
101 | u32 sem_mask, u32 sem_bits) | |
102 | { | |
103 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
104 | u32 value; | |
105 | unsigned int seconds = 3; | |
106 | ||
107 | do { | |
108 | writel((sem_mask | sem_bits), | |
109 | &port_regs->CommonRegs.semaphoreReg); | |
110 | value = readl(&port_regs->CommonRegs.semaphoreReg); | |
111 | if ((value & (sem_mask >> 16)) == sem_bits) | |
112 | return 0; | |
113 | ssleep(1); | |
114 | } while(--seconds); | |
115 | return -1; | |
116 | } | |
117 | ||
118 | static void ql_sem_unlock(struct ql3_adapter *qdev, u32 sem_mask) | |
119 | { | |
120 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
121 | writel(sem_mask, &port_regs->CommonRegs.semaphoreReg); | |
122 | readl(&port_regs->CommonRegs.semaphoreReg); | |
123 | } | |
124 | ||
125 | static int ql_sem_lock(struct ql3_adapter *qdev, u32 sem_mask, u32 sem_bits) | |
126 | { | |
127 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
128 | u32 value; | |
129 | ||
130 | writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg); | |
131 | value = readl(&port_regs->CommonRegs.semaphoreReg); | |
132 | return ((value & (sem_mask >> 16)) == sem_bits); | |
133 | } | |
134 | ||
135 | /* | |
136 | * Caller holds hw_lock. | |
137 | */ | |
138 | static int ql_wait_for_drvr_lock(struct ql3_adapter *qdev) | |
139 | { | |
140 | int i = 0; | |
141 | ||
142 | while (1) { | |
143 | if (!ql_sem_lock(qdev, | |
144 | QL_DRVR_SEM_MASK, | |
145 | (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) | |
146 | * 2) << 1)) { | |
147 | if (i < 10) { | |
148 | ssleep(1); | |
149 | i++; | |
150 | } else { | |
151 | printk(KERN_ERR PFX "%s: Timed out waiting for " | |
152 | "driver lock...\n", | |
153 | qdev->ndev->name); | |
154 | return 0; | |
155 | } | |
156 | } else { | |
157 | printk(KERN_DEBUG PFX | |
158 | "%s: driver lock acquired.\n", | |
159 | qdev->ndev->name); | |
160 | return 1; | |
161 | } | |
162 | } | |
163 | } | |
164 | ||
165 | static void ql_set_register_page(struct ql3_adapter *qdev, u32 page) | |
166 | { | |
167 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
168 | ||
169 | writel(((ISP_CONTROL_NP_MASK << 16) | page), | |
170 | &port_regs->CommonRegs.ispControlStatus); | |
171 | readl(&port_regs->CommonRegs.ispControlStatus); | |
172 | qdev->current_page = page; | |
173 | } | |
174 | ||
175 | static u32 ql_read_common_reg_l(struct ql3_adapter *qdev, | |
176 | u32 __iomem * reg) | |
177 | { | |
178 | u32 value; | |
179 | unsigned long hw_flags; | |
180 | ||
181 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
182 | value = readl(reg); | |
183 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
184 | ||
185 | return value; | |
186 | } | |
187 | ||
188 | static u32 ql_read_common_reg(struct ql3_adapter *qdev, | |
189 | u32 __iomem * reg) | |
190 | { | |
191 | return readl(reg); | |
192 | } | |
193 | ||
194 | static u32 ql_read_page0_reg_l(struct ql3_adapter *qdev, u32 __iomem *reg) | |
195 | { | |
196 | u32 value; | |
197 | unsigned long hw_flags; | |
198 | ||
199 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
200 | ||
201 | if (qdev->current_page != 0) | |
202 | ql_set_register_page(qdev,0); | |
203 | value = readl(reg); | |
204 | ||
205 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
206 | return value; | |
207 | } | |
208 | ||
209 | static u32 ql_read_page0_reg(struct ql3_adapter *qdev, u32 __iomem *reg) | |
210 | { | |
211 | if (qdev->current_page != 0) | |
212 | ql_set_register_page(qdev,0); | |
213 | return readl(reg); | |
214 | } | |
215 | ||
216 | static void ql_write_common_reg_l(struct ql3_adapter *qdev, | |
ee111d11 | 217 | u32 __iomem *reg, u32 value) |
5a4faa87 RM |
218 | { |
219 | unsigned long hw_flags; | |
220 | ||
221 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
ee111d11 | 222 | writel(value, reg); |
5a4faa87 RM |
223 | readl(reg); |
224 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
225 | return; | |
226 | } | |
227 | ||
228 | static void ql_write_common_reg(struct ql3_adapter *qdev, | |
ee111d11 | 229 | u32 __iomem *reg, u32 value) |
5a4faa87 | 230 | { |
ee111d11 | 231 | writel(value, reg); |
5a4faa87 RM |
232 | readl(reg); |
233 | return; | |
234 | } | |
235 | ||
80b02e59 RM |
236 | static void ql_write_nvram_reg(struct ql3_adapter *qdev, |
237 | u32 __iomem *reg, u32 value) | |
238 | { | |
239 | writel(value, reg); | |
240 | readl(reg); | |
241 | udelay(1); | |
242 | return; | |
243 | } | |
244 | ||
5a4faa87 | 245 | static void ql_write_page0_reg(struct ql3_adapter *qdev, |
ee111d11 | 246 | u32 __iomem *reg, u32 value) |
5a4faa87 RM |
247 | { |
248 | if (qdev->current_page != 0) | |
249 | ql_set_register_page(qdev,0); | |
ee111d11 | 250 | writel(value, reg); |
5a4faa87 RM |
251 | readl(reg); |
252 | return; | |
253 | } | |
254 | ||
255 | /* | |
256 | * Caller holds hw_lock. Only called during init. | |
257 | */ | |
258 | static void ql_write_page1_reg(struct ql3_adapter *qdev, | |
ee111d11 | 259 | u32 __iomem *reg, u32 value) |
5a4faa87 RM |
260 | { |
261 | if (qdev->current_page != 1) | |
262 | ql_set_register_page(qdev,1); | |
ee111d11 | 263 | writel(value, reg); |
5a4faa87 RM |
264 | readl(reg); |
265 | return; | |
266 | } | |
267 | ||
268 | /* | |
269 | * Caller holds hw_lock. Only called during init. | |
270 | */ | |
271 | static void ql_write_page2_reg(struct ql3_adapter *qdev, | |
ee111d11 | 272 | u32 __iomem *reg, u32 value) |
5a4faa87 RM |
273 | { |
274 | if (qdev->current_page != 2) | |
275 | ql_set_register_page(qdev,2); | |
ee111d11 | 276 | writel(value, reg); |
5a4faa87 RM |
277 | readl(reg); |
278 | return; | |
279 | } | |
280 | ||
281 | static void ql_disable_interrupts(struct ql3_adapter *qdev) | |
282 | { | |
283 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
284 | ||
285 | ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg, | |
286 | (ISP_IMR_ENABLE_INT << 16)); | |
287 | ||
288 | } | |
289 | ||
290 | static void ql_enable_interrupts(struct ql3_adapter *qdev) | |
291 | { | |
292 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
293 | ||
294 | ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg, | |
295 | ((0xff << 16) | ISP_IMR_ENABLE_INT)); | |
296 | ||
297 | } | |
298 | ||
299 | static void ql_release_to_lrg_buf_free_list(struct ql3_adapter *qdev, | |
300 | struct ql_rcv_buf_cb *lrg_buf_cb) | |
301 | { | |
0f8ab89e BL |
302 | dma_addr_t map; |
303 | int err; | |
5a4faa87 RM |
304 | lrg_buf_cb->next = NULL; |
305 | ||
306 | if (qdev->lrg_buf_free_tail == NULL) { /* The list is empty */ | |
307 | qdev->lrg_buf_free_head = qdev->lrg_buf_free_tail = lrg_buf_cb; | |
308 | } else { | |
309 | qdev->lrg_buf_free_tail->next = lrg_buf_cb; | |
310 | qdev->lrg_buf_free_tail = lrg_buf_cb; | |
311 | } | |
312 | ||
313 | if (!lrg_buf_cb->skb) { | |
cd238faa BL |
314 | lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev, |
315 | qdev->lrg_buffer_len); | |
5a4faa87 | 316 | if (unlikely(!lrg_buf_cb->skb)) { |
cd238faa | 317 | printk(KERN_ERR PFX "%s: failed netdev_alloc_skb().\n", |
5a4faa87 RM |
318 | qdev->ndev->name); |
319 | qdev->lrg_buf_skb_check++; | |
320 | } else { | |
321 | /* | |
322 | * We save some space to copy the ethhdr from first | |
323 | * buffer | |
324 | */ | |
325 | skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE); | |
326 | map = pci_map_single(qdev->pdev, | |
327 | lrg_buf_cb->skb->data, | |
328 | qdev->lrg_buffer_len - | |
329 | QL_HEADER_SPACE, | |
330 | PCI_DMA_FROMDEVICE); | |
0f8ab89e BL |
331 | err = pci_dma_mapping_error(map); |
332 | if(err) { | |
333 | printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", | |
334 | qdev->ndev->name, err); | |
335 | dev_kfree_skb(lrg_buf_cb->skb); | |
336 | lrg_buf_cb->skb = NULL; | |
337 | ||
338 | qdev->lrg_buf_skb_check++; | |
339 | return; | |
340 | } | |
341 | ||
5a4faa87 RM |
342 | lrg_buf_cb->buf_phy_addr_low = |
343 | cpu_to_le32(LS_64BITS(map)); | |
344 | lrg_buf_cb->buf_phy_addr_high = | |
345 | cpu_to_le32(MS_64BITS(map)); | |
346 | pci_unmap_addr_set(lrg_buf_cb, mapaddr, map); | |
347 | pci_unmap_len_set(lrg_buf_cb, maplen, | |
348 | qdev->lrg_buffer_len - | |
349 | QL_HEADER_SPACE); | |
350 | } | |
351 | } | |
352 | ||
353 | qdev->lrg_buf_free_count++; | |
354 | } | |
355 | ||
356 | static struct ql_rcv_buf_cb *ql_get_from_lrg_buf_free_list(struct ql3_adapter | |
357 | *qdev) | |
358 | { | |
359 | struct ql_rcv_buf_cb *lrg_buf_cb; | |
360 | ||
361 | if ((lrg_buf_cb = qdev->lrg_buf_free_head) != NULL) { | |
362 | if ((qdev->lrg_buf_free_head = lrg_buf_cb->next) == NULL) | |
363 | qdev->lrg_buf_free_tail = NULL; | |
364 | qdev->lrg_buf_free_count--; | |
365 | } | |
366 | ||
367 | return lrg_buf_cb; | |
368 | } | |
369 | ||
370 | static u32 addrBits = EEPROM_NO_ADDR_BITS; | |
371 | static u32 dataBits = EEPROM_NO_DATA_BITS; | |
372 | ||
373 | static void fm93c56a_deselect(struct ql3_adapter *qdev); | |
374 | static void eeprom_readword(struct ql3_adapter *qdev, u32 eepromAddr, | |
375 | unsigned short *value); | |
376 | ||
377 | /* | |
378 | * Caller holds hw_lock. | |
379 | */ | |
380 | static void fm93c56a_select(struct ql3_adapter *qdev) | |
381 | { | |
382 | struct ql3xxx_port_registers __iomem *port_regs = | |
383 | qdev->mem_map_registers; | |
384 | ||
385 | qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1; | |
80b02e59 | 386 | ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg, |
5a4faa87 | 387 | ISP_NVRAM_MASK | qdev->eeprom_cmd_data); |
80b02e59 | 388 | ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg, |
5a4faa87 RM |
389 | ((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data)); |
390 | } | |
391 | ||
392 | /* | |
393 | * Caller holds hw_lock. | |
394 | */ | |
395 | static void fm93c56a_cmd(struct ql3_adapter *qdev, u32 cmd, u32 eepromAddr) | |
396 | { | |
397 | int i; | |
398 | u32 mask; | |
399 | u32 dataBit; | |
400 | u32 previousBit; | |
401 | struct ql3xxx_port_registers __iomem *port_regs = | |
402 | qdev->mem_map_registers; | |
403 | ||
404 | /* Clock in a zero, then do the start bit */ | |
80b02e59 | 405 | ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg, |
5a4faa87 RM |
406 | ISP_NVRAM_MASK | qdev->eeprom_cmd_data | |
407 | AUBURN_EEPROM_DO_1); | |
80b02e59 | 408 | ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg, |
5a4faa87 RM |
409 | ISP_NVRAM_MASK | qdev-> |
410 | eeprom_cmd_data | AUBURN_EEPROM_DO_1 | | |
411 | AUBURN_EEPROM_CLK_RISE); | |
80b02e59 | 412 | ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg, |
5a4faa87 RM |
413 | ISP_NVRAM_MASK | qdev-> |
414 | eeprom_cmd_data | AUBURN_EEPROM_DO_1 | | |
415 | AUBURN_EEPROM_CLK_FALL); | |
416 | ||
417 | mask = 1 << (FM93C56A_CMD_BITS - 1); | |
418 | /* Force the previous data bit to be different */ | |
419 | previousBit = 0xffff; | |
420 | for (i = 0; i < FM93C56A_CMD_BITS; i++) { | |
421 | dataBit = | |
422 | (cmd & mask) ? AUBURN_EEPROM_DO_1 : AUBURN_EEPROM_DO_0; | |
423 | if (previousBit != dataBit) { | |
424 | /* | |
425 | * If the bit changed, then change the DO state to | |
426 | * match | |
427 | */ | |
80b02e59 | 428 | ql_write_nvram_reg(qdev, |
5a4faa87 RM |
429 | &port_regs->CommonRegs. |
430 | serialPortInterfaceReg, | |
431 | ISP_NVRAM_MASK | qdev-> | |
432 | eeprom_cmd_data | dataBit); | |
433 | previousBit = dataBit; | |
434 | } | |
80b02e59 | 435 | ql_write_nvram_reg(qdev, |
5a4faa87 RM |
436 | &port_regs->CommonRegs. |
437 | serialPortInterfaceReg, | |
438 | ISP_NVRAM_MASK | qdev-> | |
439 | eeprom_cmd_data | dataBit | | |
440 | AUBURN_EEPROM_CLK_RISE); | |
80b02e59 | 441 | ql_write_nvram_reg(qdev, |
5a4faa87 RM |
442 | &port_regs->CommonRegs. |
443 | serialPortInterfaceReg, | |
444 | ISP_NVRAM_MASK | qdev-> | |
445 | eeprom_cmd_data | dataBit | | |
446 | AUBURN_EEPROM_CLK_FALL); | |
447 | cmd = cmd << 1; | |
448 | } | |
449 | ||
450 | mask = 1 << (addrBits - 1); | |
451 | /* Force the previous data bit to be different */ | |
452 | previousBit = 0xffff; | |
453 | for (i = 0; i < addrBits; i++) { | |
454 | dataBit = | |
455 | (eepromAddr & mask) ? AUBURN_EEPROM_DO_1 : | |
456 | AUBURN_EEPROM_DO_0; | |
457 | if (previousBit != dataBit) { | |
458 | /* | |
459 | * If the bit changed, then change the DO state to | |
460 | * match | |
461 | */ | |
80b02e59 | 462 | ql_write_nvram_reg(qdev, |
5a4faa87 RM |
463 | &port_regs->CommonRegs. |
464 | serialPortInterfaceReg, | |
465 | ISP_NVRAM_MASK | qdev-> | |
466 | eeprom_cmd_data | dataBit); | |
467 | previousBit = dataBit; | |
468 | } | |
80b02e59 | 469 | ql_write_nvram_reg(qdev, |
5a4faa87 RM |
470 | &port_regs->CommonRegs. |
471 | serialPortInterfaceReg, | |
472 | ISP_NVRAM_MASK | qdev-> | |
473 | eeprom_cmd_data | dataBit | | |
474 | AUBURN_EEPROM_CLK_RISE); | |
80b02e59 | 475 | ql_write_nvram_reg(qdev, |
5a4faa87 RM |
476 | &port_regs->CommonRegs. |
477 | serialPortInterfaceReg, | |
478 | ISP_NVRAM_MASK | qdev-> | |
479 | eeprom_cmd_data | dataBit | | |
480 | AUBURN_EEPROM_CLK_FALL); | |
481 | eepromAddr = eepromAddr << 1; | |
482 | } | |
483 | } | |
484 | ||
485 | /* | |
486 | * Caller holds hw_lock. | |
487 | */ | |
488 | static void fm93c56a_deselect(struct ql3_adapter *qdev) | |
489 | { | |
490 | struct ql3xxx_port_registers __iomem *port_regs = | |
491 | qdev->mem_map_registers; | |
492 | qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0; | |
80b02e59 | 493 | ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg, |
5a4faa87 RM |
494 | ISP_NVRAM_MASK | qdev->eeprom_cmd_data); |
495 | } | |
496 | ||
497 | /* | |
498 | * Caller holds hw_lock. | |
499 | */ | |
500 | static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value) | |
501 | { | |
502 | int i; | |
503 | u32 data = 0; | |
504 | u32 dataBit; | |
505 | struct ql3xxx_port_registers __iomem *port_regs = | |
506 | qdev->mem_map_registers; | |
507 | ||
508 | /* Read the data bits */ | |
509 | /* The first bit is a dummy. Clock right over it. */ | |
510 | for (i = 0; i < dataBits; i++) { | |
80b02e59 | 511 | ql_write_nvram_reg(qdev, |
5a4faa87 RM |
512 | &port_regs->CommonRegs. |
513 | serialPortInterfaceReg, | |
514 | ISP_NVRAM_MASK | qdev->eeprom_cmd_data | | |
515 | AUBURN_EEPROM_CLK_RISE); | |
80b02e59 | 516 | ql_write_nvram_reg(qdev, |
5a4faa87 RM |
517 | &port_regs->CommonRegs. |
518 | serialPortInterfaceReg, | |
519 | ISP_NVRAM_MASK | qdev->eeprom_cmd_data | | |
520 | AUBURN_EEPROM_CLK_FALL); | |
521 | dataBit = | |
522 | (ql_read_common_reg | |
523 | (qdev, | |
524 | &port_regs->CommonRegs. | |
525 | serialPortInterfaceReg) & AUBURN_EEPROM_DI_1) ? 1 : 0; | |
526 | data = (data << 1) | dataBit; | |
527 | } | |
528 | *value = (u16) data; | |
529 | } | |
530 | ||
531 | /* | |
532 | * Caller holds hw_lock. | |
533 | */ | |
534 | static void eeprom_readword(struct ql3_adapter *qdev, | |
535 | u32 eepromAddr, unsigned short *value) | |
536 | { | |
537 | fm93c56a_select(qdev); | |
538 | fm93c56a_cmd(qdev, (int)FM93C56A_READ, eepromAddr); | |
539 | fm93c56a_datain(qdev, value); | |
540 | fm93c56a_deselect(qdev); | |
541 | } | |
542 | ||
543 | static void ql_swap_mac_addr(u8 * macAddress) | |
544 | { | |
545 | #ifdef __BIG_ENDIAN | |
546 | u8 temp; | |
547 | temp = macAddress[0]; | |
548 | macAddress[0] = macAddress[1]; | |
549 | macAddress[1] = temp; | |
550 | temp = macAddress[2]; | |
551 | macAddress[2] = macAddress[3]; | |
552 | macAddress[3] = temp; | |
553 | temp = macAddress[4]; | |
554 | macAddress[4] = macAddress[5]; | |
555 | macAddress[5] = temp; | |
556 | #endif | |
557 | } | |
558 | ||
559 | static int ql_get_nvram_params(struct ql3_adapter *qdev) | |
560 | { | |
561 | u16 *pEEPROMData; | |
562 | u16 checksum = 0; | |
563 | u32 index; | |
564 | unsigned long hw_flags; | |
565 | ||
566 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
567 | ||
568 | pEEPROMData = (u16 *) & qdev->nvram_data; | |
569 | qdev->eeprom_cmd_data = 0; | |
570 | if(ql_sem_spinlock(qdev, QL_NVRAM_SEM_MASK, | |
571 | (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * | |
572 | 2) << 10)) { | |
573 | printk(KERN_ERR PFX"%s: Failed ql_sem_spinlock().\n", | |
574 | __func__); | |
575 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
576 | return -1; | |
577 | } | |
578 | ||
579 | for (index = 0; index < EEPROM_SIZE; index++) { | |
580 | eeprom_readword(qdev, index, pEEPROMData); | |
581 | checksum += *pEEPROMData; | |
582 | pEEPROMData++; | |
583 | } | |
584 | ql_sem_unlock(qdev, QL_NVRAM_SEM_MASK); | |
585 | ||
586 | if (checksum != 0) { | |
587 | printk(KERN_ERR PFX "%s: checksum should be zero, is %x!!\n", | |
588 | qdev->ndev->name, checksum); | |
589 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
590 | return -1; | |
591 | } | |
592 | ||
593 | /* | |
594 | * We have a problem with endianness for the MAC addresses | |
595 | * and the two 8-bit values version, and numPorts. We | |
596 | * have to swap them on big endian systems. | |
597 | */ | |
598 | ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn0.macAddress); | |
599 | ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn1.macAddress); | |
600 | ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn2.macAddress); | |
601 | ql_swap_mac_addr(qdev->nvram_data.funcCfg_fn3.macAddress); | |
602 | pEEPROMData = (u16 *) & qdev->nvram_data.version; | |
603 | *pEEPROMData = le16_to_cpu(*pEEPROMData); | |
604 | ||
605 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
606 | return checksum; | |
607 | } | |
608 | ||
609 | static const u32 PHYAddr[2] = { | |
610 | PORT0_PHY_ADDRESS, PORT1_PHY_ADDRESS | |
611 | }; | |
612 | ||
613 | static int ql_wait_for_mii_ready(struct ql3_adapter *qdev) | |
614 | { | |
615 | struct ql3xxx_port_registers __iomem *port_regs = | |
616 | qdev->mem_map_registers; | |
617 | u32 temp; | |
618 | int count = 1000; | |
619 | ||
620 | while (count) { | |
621 | temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg); | |
622 | if (!(temp & MAC_MII_STATUS_BSY)) | |
623 | return 0; | |
624 | udelay(10); | |
625 | count--; | |
626 | } | |
627 | return -1; | |
628 | } | |
629 | ||
630 | static void ql_mii_enable_scan_mode(struct ql3_adapter *qdev) | |
631 | { | |
632 | struct ql3xxx_port_registers __iomem *port_regs = | |
633 | qdev->mem_map_registers; | |
634 | u32 scanControl; | |
635 | ||
636 | if (qdev->numPorts > 1) { | |
637 | /* Auto scan will cycle through multiple ports */ | |
638 | scanControl = MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC; | |
639 | } else { | |
640 | scanControl = MAC_MII_CONTROL_SC; | |
641 | } | |
642 | ||
643 | /* | |
644 | * Scan register 1 of PHY/PETBI, | |
645 | * Set up to scan both devices | |
646 | * The autoscan starts from the first register, completes | |
647 | * the last one before rolling over to the first | |
648 | */ | |
649 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg, | |
650 | PHYAddr[0] | MII_SCAN_REGISTER); | |
651 | ||
652 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, | |
653 | (scanControl) | | |
654 | ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS) << 16)); | |
655 | } | |
656 | ||
657 | static u8 ql_mii_disable_scan_mode(struct ql3_adapter *qdev) | |
658 | { | |
659 | u8 ret; | |
660 | struct ql3xxx_port_registers __iomem *port_regs = | |
661 | qdev->mem_map_registers; | |
662 | ||
663 | /* See if scan mode is enabled before we turn it off */ | |
664 | if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) & | |
665 | (MAC_MII_CONTROL_AS | MAC_MII_CONTROL_SC)) { | |
666 | /* Scan is enabled */ | |
667 | ret = 1; | |
668 | } else { | |
669 | /* Scan is disabled */ | |
670 | ret = 0; | |
671 | } | |
672 | ||
673 | /* | |
674 | * When disabling scan mode you must first change the MII register | |
675 | * address | |
676 | */ | |
677 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg, | |
678 | PHYAddr[0] | MII_SCAN_REGISTER); | |
679 | ||
680 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, | |
681 | ((MAC_MII_CONTROL_SC | MAC_MII_CONTROL_AS | | |
682 | MAC_MII_CONTROL_RC) << 16)); | |
683 | ||
684 | return ret; | |
685 | } | |
686 | ||
687 | static int ql_mii_write_reg_ex(struct ql3_adapter *qdev, | |
3efedf2e | 688 | u16 regAddr, u16 value, u32 phyAddr) |
5a4faa87 RM |
689 | { |
690 | struct ql3xxx_port_registers __iomem *port_regs = | |
691 | qdev->mem_map_registers; | |
692 | u8 scanWasEnabled; | |
693 | ||
694 | scanWasEnabled = ql_mii_disable_scan_mode(qdev); | |
695 | ||
696 | if (ql_wait_for_mii_ready(qdev)) { | |
697 | if (netif_msg_link(qdev)) | |
698 | printk(KERN_WARNING PFX | |
699 | "%s Timed out waiting for management port to " | |
700 | "get free before issuing command.\n", | |
701 | qdev->ndev->name); | |
702 | return -1; | |
703 | } | |
704 | ||
705 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg, | |
3efedf2e | 706 | phyAddr | regAddr); |
5a4faa87 RM |
707 | |
708 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value); | |
709 | ||
710 | /* Wait for write to complete 9/10/04 SJP */ | |
711 | if (ql_wait_for_mii_ready(qdev)) { | |
712 | if (netif_msg_link(qdev)) | |
713 | printk(KERN_WARNING PFX | |
714 | "%s: Timed out waiting for management port to" | |
715 | "get free before issuing command.\n", | |
716 | qdev->ndev->name); | |
717 | return -1; | |
718 | } | |
719 | ||
720 | if (scanWasEnabled) | |
721 | ql_mii_enable_scan_mode(qdev); | |
722 | ||
723 | return 0; | |
724 | } | |
725 | ||
726 | static int ql_mii_read_reg_ex(struct ql3_adapter *qdev, u16 regAddr, | |
3efedf2e | 727 | u16 * value, u32 phyAddr) |
5a4faa87 RM |
728 | { |
729 | struct ql3xxx_port_registers __iomem *port_regs = | |
730 | qdev->mem_map_registers; | |
731 | u8 scanWasEnabled; | |
732 | u32 temp; | |
733 | ||
734 | scanWasEnabled = ql_mii_disable_scan_mode(qdev); | |
735 | ||
736 | if (ql_wait_for_mii_ready(qdev)) { | |
737 | if (netif_msg_link(qdev)) | |
738 | printk(KERN_WARNING PFX | |
739 | "%s: Timed out waiting for management port to " | |
740 | "get free before issuing command.\n", | |
741 | qdev->ndev->name); | |
742 | return -1; | |
743 | } | |
744 | ||
745 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg, | |
3efedf2e | 746 | phyAddr | regAddr); |
5a4faa87 RM |
747 | |
748 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, | |
749 | (MAC_MII_CONTROL_RC << 16)); | |
750 | ||
751 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, | |
752 | (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC); | |
753 | ||
754 | /* Wait for the read to complete */ | |
755 | if (ql_wait_for_mii_ready(qdev)) { | |
756 | if (netif_msg_link(qdev)) | |
757 | printk(KERN_WARNING PFX | |
758 | "%s: Timed out waiting for management port to " | |
759 | "get free after issuing command.\n", | |
760 | qdev->ndev->name); | |
761 | return -1; | |
762 | } | |
763 | ||
764 | temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg); | |
765 | *value = (u16) temp; | |
766 | ||
767 | if (scanWasEnabled) | |
768 | ql_mii_enable_scan_mode(qdev); | |
769 | ||
770 | return 0; | |
771 | } | |
772 | ||
773 | static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value) | |
774 | { | |
775 | struct ql3xxx_port_registers __iomem *port_regs = | |
776 | qdev->mem_map_registers; | |
777 | ||
778 | ql_mii_disable_scan_mode(qdev); | |
779 | ||
780 | if (ql_wait_for_mii_ready(qdev)) { | |
781 | if (netif_msg_link(qdev)) | |
782 | printk(KERN_WARNING PFX | |
783 | "%s: Timed out waiting for management port to " | |
784 | "get free before issuing command.\n", | |
785 | qdev->ndev->name); | |
786 | return -1; | |
787 | } | |
788 | ||
789 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg, | |
790 | qdev->PHYAddr | regAddr); | |
791 | ||
792 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value); | |
793 | ||
794 | /* Wait for write to complete. */ | |
795 | if (ql_wait_for_mii_ready(qdev)) { | |
796 | if (netif_msg_link(qdev)) | |
797 | printk(KERN_WARNING PFX | |
798 | "%s: Timed out waiting for management port to " | |
799 | "get free before issuing command.\n", | |
800 | qdev->ndev->name); | |
801 | return -1; | |
802 | } | |
803 | ||
804 | ql_mii_enable_scan_mode(qdev); | |
805 | ||
806 | return 0; | |
807 | } | |
808 | ||
809 | static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value) | |
810 | { | |
811 | u32 temp; | |
812 | struct ql3xxx_port_registers __iomem *port_regs = | |
813 | qdev->mem_map_registers; | |
814 | ||
815 | ql_mii_disable_scan_mode(qdev); | |
816 | ||
817 | if (ql_wait_for_mii_ready(qdev)) { | |
818 | if (netif_msg_link(qdev)) | |
819 | printk(KERN_WARNING PFX | |
820 | "%s: Timed out waiting for management port to " | |
821 | "get free before issuing command.\n", | |
822 | qdev->ndev->name); | |
823 | return -1; | |
824 | } | |
825 | ||
826 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg, | |
827 | qdev->PHYAddr | regAddr); | |
828 | ||
829 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, | |
830 | (MAC_MII_CONTROL_RC << 16)); | |
831 | ||
832 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, | |
833 | (MAC_MII_CONTROL_RC << 16) | MAC_MII_CONTROL_RC); | |
834 | ||
835 | /* Wait for the read to complete */ | |
836 | if (ql_wait_for_mii_ready(qdev)) { | |
837 | if (netif_msg_link(qdev)) | |
838 | printk(KERN_WARNING PFX | |
839 | "%s: Timed out waiting for management port to " | |
840 | "get free before issuing command.\n", | |
841 | qdev->ndev->name); | |
842 | return -1; | |
843 | } | |
844 | ||
845 | temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg); | |
846 | *value = (u16) temp; | |
847 | ||
848 | ql_mii_enable_scan_mode(qdev); | |
849 | ||
850 | return 0; | |
851 | } | |
852 | ||
853 | static void ql_petbi_reset(struct ql3_adapter *qdev) | |
854 | { | |
855 | ql_mii_write_reg(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET); | |
856 | } | |
857 | ||
858 | static void ql_petbi_start_neg(struct ql3_adapter *qdev) | |
859 | { | |
860 | u16 reg; | |
861 | ||
862 | /* Enable Auto-negotiation sense */ | |
863 | ql_mii_read_reg(qdev, PETBI_TBI_CTRL, ®); | |
864 | reg |= PETBI_TBI_AUTO_SENSE; | |
865 | ql_mii_write_reg(qdev, PETBI_TBI_CTRL, reg); | |
866 | ||
867 | ql_mii_write_reg(qdev, PETBI_NEG_ADVER, | |
868 | PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX); | |
869 | ||
870 | ql_mii_write_reg(qdev, PETBI_CONTROL_REG, | |
871 | PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG | | |
872 | PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000); | |
873 | ||
874 | } | |
875 | ||
3efedf2e | 876 | static void ql_petbi_reset_ex(struct ql3_adapter *qdev) |
5a4faa87 RM |
877 | { |
878 | ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, PETBI_CTRL_SOFT_RESET, | |
3efedf2e | 879 | PHYAddr[qdev->mac_index]); |
5a4faa87 RM |
880 | } |
881 | ||
3efedf2e | 882 | static void ql_petbi_start_neg_ex(struct ql3_adapter *qdev) |
5a4faa87 RM |
883 | { |
884 | u16 reg; | |
885 | ||
886 | /* Enable Auto-negotiation sense */ | |
3efedf2e RM |
887 | ql_mii_read_reg_ex(qdev, PETBI_TBI_CTRL, ®, |
888 | PHYAddr[qdev->mac_index]); | |
5a4faa87 | 889 | reg |= PETBI_TBI_AUTO_SENSE; |
3efedf2e RM |
890 | ql_mii_write_reg_ex(qdev, PETBI_TBI_CTRL, reg, |
891 | PHYAddr[qdev->mac_index]); | |
5a4faa87 RM |
892 | |
893 | ql_mii_write_reg_ex(qdev, PETBI_NEG_ADVER, | |
3efedf2e RM |
894 | PETBI_NEG_PAUSE | PETBI_NEG_DUPLEX, |
895 | PHYAddr[qdev->mac_index]); | |
5a4faa87 RM |
896 | |
897 | ql_mii_write_reg_ex(qdev, PETBI_CONTROL_REG, | |
898 | PETBI_CTRL_AUTO_NEG | PETBI_CTRL_RESTART_NEG | | |
899 | PETBI_CTRL_FULL_DUPLEX | PETBI_CTRL_SPEED_1000, | |
3efedf2e | 900 | PHYAddr[qdev->mac_index]); |
5a4faa87 RM |
901 | } |
902 | ||
903 | static void ql_petbi_init(struct ql3_adapter *qdev) | |
904 | { | |
905 | ql_petbi_reset(qdev); | |
906 | ql_petbi_start_neg(qdev); | |
907 | } | |
908 | ||
3efedf2e | 909 | static void ql_petbi_init_ex(struct ql3_adapter *qdev) |
5a4faa87 | 910 | { |
3efedf2e RM |
911 | ql_petbi_reset_ex(qdev); |
912 | ql_petbi_start_neg_ex(qdev); | |
5a4faa87 RM |
913 | } |
914 | ||
915 | static int ql_is_petbi_neg_pause(struct ql3_adapter *qdev) | |
916 | { | |
917 | u16 reg; | |
918 | ||
919 | if (ql_mii_read_reg(qdev, PETBI_NEG_PARTNER, ®) < 0) | |
920 | return 0; | |
921 | ||
922 | return (reg & PETBI_NEG_PAUSE_MASK) == PETBI_NEG_PAUSE; | |
923 | } | |
924 | ||
3efedf2e RM |
925 | static void phyAgereSpecificInit(struct ql3_adapter *qdev, u32 miiAddr) |
926 | { | |
927 | printk(KERN_INFO "%s: enabling Agere specific PHY\n", qdev->ndev->name); | |
928 | /* power down device bit 11 = 1 */ | |
929 | ql_mii_write_reg_ex(qdev, 0x00, 0x1940, miiAddr); | |
930 | /* enable diagnostic mode bit 2 = 1 */ | |
931 | ql_mii_write_reg_ex(qdev, 0x12, 0x840e, miiAddr); | |
932 | /* 1000MB amplitude adjust (see Agere errata) */ | |
933 | ql_mii_write_reg_ex(qdev, 0x10, 0x8805, miiAddr); | |
934 | /* 1000MB amplitude adjust (see Agere errata) */ | |
935 | ql_mii_write_reg_ex(qdev, 0x11, 0xf03e, miiAddr); | |
936 | /* 100MB amplitude adjust (see Agere errata) */ | |
937 | ql_mii_write_reg_ex(qdev, 0x10, 0x8806, miiAddr); | |
938 | /* 100MB amplitude adjust (see Agere errata) */ | |
939 | ql_mii_write_reg_ex(qdev, 0x11, 0x003e, miiAddr); | |
940 | /* 10MB amplitude adjust (see Agere errata) */ | |
941 | ql_mii_write_reg_ex(qdev, 0x10, 0x8807, miiAddr); | |
942 | /* 10MB amplitude adjust (see Agere errata) */ | |
943 | ql_mii_write_reg_ex(qdev, 0x11, 0x1f00, miiAddr); | |
944 | /* point to hidden reg 0x2806 */ | |
945 | ql_mii_write_reg_ex(qdev, 0x10, 0x2806, miiAddr); | |
946 | /* Write new PHYAD w/bit 5 set */ | |
947 | ql_mii_write_reg_ex(qdev, 0x11, 0x0020 | (PHYAddr[qdev->mac_index] >> 8), miiAddr); | |
948 | /* | |
949 | * Disable diagnostic mode bit 2 = 0 | |
950 | * Power up device bit 11 = 0 | |
951 | * Link up (on) and activity (blink) | |
952 | */ | |
953 | ql_mii_write_reg(qdev, 0x12, 0x840a); | |
954 | ql_mii_write_reg(qdev, 0x00, 0x1140); | |
955 | ql_mii_write_reg(qdev, 0x1c, 0xfaf0); | |
956 | } | |
957 | ||
958 | static PHY_DEVICE_et getPhyType (struct ql3_adapter *qdev, | |
959 | u16 phyIdReg0, u16 phyIdReg1) | |
960 | { | |
961 | PHY_DEVICE_et result = PHY_TYPE_UNKNOWN; | |
962 | u32 oui; | |
963 | u16 model; | |
964 | int i; | |
965 | ||
966 | if (phyIdReg0 == 0xffff) { | |
967 | return result; | |
968 | } | |
969 | ||
970 | if (phyIdReg1 == 0xffff) { | |
971 | return result; | |
972 | } | |
973 | ||
974 | /* oui is split between two registers */ | |
975 | oui = (phyIdReg0 << 6) | ((phyIdReg1 & PHY_OUI_1_MASK) >> 10); | |
976 | ||
977 | model = (phyIdReg1 & PHY_MODEL_MASK) >> 4; | |
978 | ||
979 | /* Scan table for this PHY */ | |
980 | for(i = 0; i < MAX_PHY_DEV_TYPES; i++) { | |
981 | if ((oui == PHY_DEVICES[i].phyIdOUI) && (model == PHY_DEVICES[i].phyIdModel)) | |
982 | { | |
983 | result = PHY_DEVICES[i].phyDevice; | |
984 | ||
985 | printk(KERN_INFO "%s: Phy: %s\n", | |
986 | qdev->ndev->name, PHY_DEVICES[i].name); | |
987 | ||
988 | break; | |
989 | } | |
990 | } | |
991 | ||
992 | return result; | |
993 | } | |
994 | ||
5a4faa87 RM |
995 | static int ql_phy_get_speed(struct ql3_adapter *qdev) |
996 | { | |
997 | u16 reg; | |
998 | ||
3efedf2e RM |
999 | switch(qdev->phyType) { |
1000 | case PHY_AGERE_ET1011C: | |
1001 | { | |
1002 | if (ql_mii_read_reg(qdev, 0x1A, ®) < 0) | |
1003 | return 0; | |
1004 | ||
1005 | reg = (reg >> 8) & 3; | |
1006 | break; | |
1007 | } | |
1008 | default: | |
5a4faa87 RM |
1009 | if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0) |
1010 | return 0; | |
1011 | ||
1012 | reg = (((reg & 0x18) >> 3) & 3); | |
3efedf2e | 1013 | } |
5a4faa87 | 1014 | |
3efedf2e RM |
1015 | switch(reg) { |
1016 | case 2: | |
5a4faa87 | 1017 | return SPEED_1000; |
3efedf2e | 1018 | case 1: |
5a4faa87 | 1019 | return SPEED_100; |
3efedf2e | 1020 | case 0: |
5a4faa87 | 1021 | return SPEED_10; |
3efedf2e | 1022 | default: |
5a4faa87 | 1023 | return -1; |
3efedf2e | 1024 | } |
5a4faa87 RM |
1025 | } |
1026 | ||
1027 | static int ql_is_full_dup(struct ql3_adapter *qdev) | |
1028 | { | |
1029 | u16 reg; | |
1030 | ||
3efedf2e RM |
1031 | switch(qdev->phyType) { |
1032 | case PHY_AGERE_ET1011C: | |
1033 | { | |
1034 | if (ql_mii_read_reg(qdev, 0x1A, ®)) | |
1035 | return 0; | |
1036 | ||
1037 | return ((reg & 0x0080) && (reg & 0x1000)) != 0; | |
1038 | } | |
1039 | case PHY_VITESSE_VSC8211: | |
1040 | default: | |
1041 | { | |
1042 | if (ql_mii_read_reg(qdev, AUX_CONTROL_STATUS, ®) < 0) | |
1043 | return 0; | |
1044 | return (reg & PHY_AUX_DUPLEX_STAT) != 0; | |
1045 | } | |
1046 | } | |
5a4faa87 RM |
1047 | } |
1048 | ||
1049 | static int ql_is_phy_neg_pause(struct ql3_adapter *qdev) | |
1050 | { | |
1051 | u16 reg; | |
1052 | ||
1053 | if (ql_mii_read_reg(qdev, PHY_NEG_PARTNER, ®) < 0) | |
1054 | return 0; | |
1055 | ||
1056 | return (reg & PHY_NEG_PAUSE) != 0; | |
1057 | } | |
1058 | ||
3efedf2e RM |
1059 | static int PHY_Setup(struct ql3_adapter *qdev) |
1060 | { | |
1061 | u16 reg1; | |
1062 | u16 reg2; | |
1063 | bool agereAddrChangeNeeded = false; | |
1064 | u32 miiAddr = 0; | |
1065 | int err; | |
1066 | ||
1067 | /* Determine the PHY we are using by reading the ID's */ | |
1068 | err = ql_mii_read_reg(qdev, PHY_ID_0_REG, ®1); | |
1069 | if(err != 0) { | |
1070 | printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n", | |
1071 | qdev->ndev->name); | |
1072 | return err; | |
1073 | } | |
1074 | ||
1075 | err = ql_mii_read_reg(qdev, PHY_ID_1_REG, ®2); | |
1076 | if(err != 0) { | |
1077 | printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG\n", | |
1078 | qdev->ndev->name); | |
1079 | return err; | |
1080 | } | |
1081 | ||
1082 | /* Check if we have a Agere PHY */ | |
1083 | if ((reg1 == 0xffff) || (reg2 == 0xffff)) { | |
1084 | ||
1085 | /* Determine which MII address we should be using | |
1086 | determined by the index of the card */ | |
1087 | if (qdev->mac_index == 0) { | |
1088 | miiAddr = MII_AGERE_ADDR_1; | |
1089 | } else { | |
1090 | miiAddr = MII_AGERE_ADDR_2; | |
1091 | } | |
1092 | ||
1093 | err =ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, ®1, miiAddr); | |
1094 | if(err != 0) { | |
1095 | printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n", | |
1096 | qdev->ndev->name); | |
1097 | return err; | |
1098 | } | |
1099 | ||
1100 | err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, ®2, miiAddr); | |
1101 | if(err != 0) { | |
1102 | printk(KERN_ERR "%s: Could not read from reg PHY_ID_0_REG after Agere detected\n", | |
1103 | qdev->ndev->name); | |
1104 | return err; | |
1105 | } | |
1106 | ||
1107 | /* We need to remember to initialize the Agere PHY */ | |
1108 | agereAddrChangeNeeded = true; | |
1109 | } | |
1110 | ||
1111 | /* Determine the particular PHY we have on board to apply | |
1112 | PHY specific initializations */ | |
1113 | qdev->phyType = getPhyType(qdev, reg1, reg2); | |
1114 | ||
1115 | if ((qdev->phyType == PHY_AGERE_ET1011C) && agereAddrChangeNeeded) { | |
1116 | /* need this here so address gets changed */ | |
1117 | phyAgereSpecificInit(qdev, miiAddr); | |
1118 | } else if (qdev->phyType == PHY_TYPE_UNKNOWN) { | |
1119 | printk(KERN_ERR "%s: PHY is unknown\n", qdev->ndev->name); | |
1120 | return -EIO; | |
1121 | } | |
1122 | ||
1123 | return 0; | |
1124 | } | |
1125 | ||
5a4faa87 RM |
1126 | /* |
1127 | * Caller holds hw_lock. | |
1128 | */ | |
1129 | static void ql_mac_enable(struct ql3_adapter *qdev, u32 enable) | |
1130 | { | |
1131 | struct ql3xxx_port_registers __iomem *port_regs = | |
1132 | qdev->mem_map_registers; | |
1133 | u32 value; | |
1134 | ||
1135 | if (enable) | |
1136 | value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16)); | |
1137 | else | |
1138 | value = (MAC_CONFIG_REG_PE << 16); | |
1139 | ||
1140 | if (qdev->mac_index) | |
1141 | ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value); | |
1142 | else | |
1143 | ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value); | |
1144 | } | |
1145 | ||
1146 | /* | |
1147 | * Caller holds hw_lock. | |
1148 | */ | |
1149 | static void ql_mac_cfg_soft_reset(struct ql3_adapter *qdev, u32 enable) | |
1150 | { | |
1151 | struct ql3xxx_port_registers __iomem *port_regs = | |
1152 | qdev->mem_map_registers; | |
1153 | u32 value; | |
1154 | ||
1155 | if (enable) | |
1156 | value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16)); | |
1157 | else | |
1158 | value = (MAC_CONFIG_REG_SR << 16); | |
1159 | ||
1160 | if (qdev->mac_index) | |
1161 | ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value); | |
1162 | else | |
1163 | ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value); | |
1164 | } | |
1165 | ||
1166 | /* | |
1167 | * Caller holds hw_lock. | |
1168 | */ | |
1169 | static void ql_mac_cfg_gig(struct ql3_adapter *qdev, u32 enable) | |
1170 | { | |
1171 | struct ql3xxx_port_registers __iomem *port_regs = | |
1172 | qdev->mem_map_registers; | |
1173 | u32 value; | |
1174 | ||
1175 | if (enable) | |
1176 | value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16)); | |
1177 | else | |
1178 | value = (MAC_CONFIG_REG_GM << 16); | |
1179 | ||
1180 | if (qdev->mac_index) | |
1181 | ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value); | |
1182 | else | |
1183 | ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value); | |
1184 | } | |
1185 | ||
1186 | /* | |
1187 | * Caller holds hw_lock. | |
1188 | */ | |
1189 | static void ql_mac_cfg_full_dup(struct ql3_adapter *qdev, u32 enable) | |
1190 | { | |
1191 | struct ql3xxx_port_registers __iomem *port_regs = | |
1192 | qdev->mem_map_registers; | |
1193 | u32 value; | |
1194 | ||
1195 | if (enable) | |
1196 | value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16)); | |
1197 | else | |
1198 | value = (MAC_CONFIG_REG_FD << 16); | |
1199 | ||
1200 | if (qdev->mac_index) | |
1201 | ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value); | |
1202 | else | |
1203 | ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value); | |
1204 | } | |
1205 | ||
1206 | /* | |
1207 | * Caller holds hw_lock. | |
1208 | */ | |
1209 | static void ql_mac_cfg_pause(struct ql3_adapter *qdev, u32 enable) | |
1210 | { | |
1211 | struct ql3xxx_port_registers __iomem *port_regs = | |
1212 | qdev->mem_map_registers; | |
1213 | u32 value; | |
1214 | ||
1215 | if (enable) | |
1216 | value = | |
1217 | ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) | | |
1218 | ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16)); | |
1219 | else | |
1220 | value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16); | |
1221 | ||
1222 | if (qdev->mac_index) | |
1223 | ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value); | |
1224 | else | |
1225 | ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value); | |
1226 | } | |
1227 | ||
1228 | /* | |
1229 | * Caller holds hw_lock. | |
1230 | */ | |
1231 | static int ql_is_fiber(struct ql3_adapter *qdev) | |
1232 | { | |
1233 | struct ql3xxx_port_registers __iomem *port_regs = | |
1234 | qdev->mem_map_registers; | |
1235 | u32 bitToCheck = 0; | |
1236 | u32 temp; | |
1237 | ||
1238 | switch (qdev->mac_index) { | |
1239 | case 0: | |
1240 | bitToCheck = PORT_STATUS_SM0; | |
1241 | break; | |
1242 | case 1: | |
1243 | bitToCheck = PORT_STATUS_SM1; | |
1244 | break; | |
1245 | } | |
1246 | ||
1247 | temp = ql_read_page0_reg(qdev, &port_regs->portStatus); | |
1248 | return (temp & bitToCheck) != 0; | |
1249 | } | |
1250 | ||
1251 | static int ql_is_auto_cfg(struct ql3_adapter *qdev) | |
1252 | { | |
1253 | u16 reg; | |
1254 | ql_mii_read_reg(qdev, 0x00, ®); | |
1255 | return (reg & 0x1000) != 0; | |
1256 | } | |
1257 | ||
1258 | /* | |
1259 | * Caller holds hw_lock. | |
1260 | */ | |
1261 | static int ql_is_auto_neg_complete(struct ql3_adapter *qdev) | |
1262 | { | |
1263 | struct ql3xxx_port_registers __iomem *port_regs = | |
1264 | qdev->mem_map_registers; | |
1265 | u32 bitToCheck = 0; | |
1266 | u32 temp; | |
1267 | ||
1268 | switch (qdev->mac_index) { | |
1269 | case 0: | |
1270 | bitToCheck = PORT_STATUS_AC0; | |
1271 | break; | |
1272 | case 1: | |
1273 | bitToCheck = PORT_STATUS_AC1; | |
1274 | break; | |
1275 | } | |
1276 | ||
1277 | temp = ql_read_page0_reg(qdev, &port_regs->portStatus); | |
1278 | if (temp & bitToCheck) { | |
1279 | if (netif_msg_link(qdev)) | |
1280 | printk(KERN_INFO PFX | |
1281 | "%s: Auto-Negotiate complete.\n", | |
1282 | qdev->ndev->name); | |
1283 | return 1; | |
1284 | } else { | |
1285 | if (netif_msg_link(qdev)) | |
1286 | printk(KERN_WARNING PFX | |
1287 | "%s: Auto-Negotiate incomplete.\n", | |
1288 | qdev->ndev->name); | |
1289 | return 0; | |
1290 | } | |
1291 | } | |
1292 | ||
1293 | /* | |
1294 | * ql_is_neg_pause() returns 1 if pause was negotiated to be on | |
1295 | */ | |
1296 | static int ql_is_neg_pause(struct ql3_adapter *qdev) | |
1297 | { | |
1298 | if (ql_is_fiber(qdev)) | |
1299 | return ql_is_petbi_neg_pause(qdev); | |
1300 | else | |
1301 | return ql_is_phy_neg_pause(qdev); | |
1302 | } | |
1303 | ||
1304 | static int ql_auto_neg_error(struct ql3_adapter *qdev) | |
1305 | { | |
1306 | struct ql3xxx_port_registers __iomem *port_regs = | |
1307 | qdev->mem_map_registers; | |
1308 | u32 bitToCheck = 0; | |
1309 | u32 temp; | |
1310 | ||
1311 | switch (qdev->mac_index) { | |
1312 | case 0: | |
1313 | bitToCheck = PORT_STATUS_AE0; | |
1314 | break; | |
1315 | case 1: | |
1316 | bitToCheck = PORT_STATUS_AE1; | |
1317 | break; | |
1318 | } | |
1319 | temp = ql_read_page0_reg(qdev, &port_regs->portStatus); | |
1320 | return (temp & bitToCheck) != 0; | |
1321 | } | |
1322 | ||
1323 | static u32 ql_get_link_speed(struct ql3_adapter *qdev) | |
1324 | { | |
1325 | if (ql_is_fiber(qdev)) | |
1326 | return SPEED_1000; | |
1327 | else | |
1328 | return ql_phy_get_speed(qdev); | |
1329 | } | |
1330 | ||
1331 | static int ql_is_link_full_dup(struct ql3_adapter *qdev) | |
1332 | { | |
1333 | if (ql_is_fiber(qdev)) | |
1334 | return 1; | |
1335 | else | |
1336 | return ql_is_full_dup(qdev); | |
1337 | } | |
1338 | ||
1339 | /* | |
1340 | * Caller holds hw_lock. | |
1341 | */ | |
1342 | static int ql_link_down_detect(struct ql3_adapter *qdev) | |
1343 | { | |
1344 | struct ql3xxx_port_registers __iomem *port_regs = | |
1345 | qdev->mem_map_registers; | |
1346 | u32 bitToCheck = 0; | |
1347 | u32 temp; | |
1348 | ||
1349 | switch (qdev->mac_index) { | |
1350 | case 0: | |
1351 | bitToCheck = ISP_CONTROL_LINK_DN_0; | |
1352 | break; | |
1353 | case 1: | |
1354 | bitToCheck = ISP_CONTROL_LINK_DN_1; | |
1355 | break; | |
1356 | } | |
1357 | ||
1358 | temp = | |
1359 | ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus); | |
1360 | return (temp & bitToCheck) != 0; | |
1361 | } | |
1362 | ||
1363 | /* | |
1364 | * Caller holds hw_lock. | |
1365 | */ | |
1366 | static int ql_link_down_detect_clear(struct ql3_adapter *qdev) | |
1367 | { | |
1368 | struct ql3xxx_port_registers __iomem *port_regs = | |
1369 | qdev->mem_map_registers; | |
1370 | ||
1371 | switch (qdev->mac_index) { | |
1372 | case 0: | |
1373 | ql_write_common_reg(qdev, | |
1374 | &port_regs->CommonRegs.ispControlStatus, | |
1375 | (ISP_CONTROL_LINK_DN_0) | | |
1376 | (ISP_CONTROL_LINK_DN_0 << 16)); | |
1377 | break; | |
1378 | ||
1379 | case 1: | |
1380 | ql_write_common_reg(qdev, | |
1381 | &port_regs->CommonRegs.ispControlStatus, | |
1382 | (ISP_CONTROL_LINK_DN_1) | | |
1383 | (ISP_CONTROL_LINK_DN_1 << 16)); | |
1384 | break; | |
1385 | ||
1386 | default: | |
1387 | return 1; | |
1388 | } | |
1389 | ||
1390 | return 0; | |
1391 | } | |
1392 | ||
1393 | /* | |
1394 | * Caller holds hw_lock. | |
1395 | */ | |
3efedf2e | 1396 | static int ql_this_adapter_controls_port(struct ql3_adapter *qdev) |
5a4faa87 RM |
1397 | { |
1398 | struct ql3xxx_port_registers __iomem *port_regs = | |
1399 | qdev->mem_map_registers; | |
1400 | u32 bitToCheck = 0; | |
1401 | u32 temp; | |
1402 | ||
3efedf2e | 1403 | switch (qdev->mac_index) { |
5a4faa87 RM |
1404 | case 0: |
1405 | bitToCheck = PORT_STATUS_F1_ENABLED; | |
1406 | break; | |
1407 | case 1: | |
1408 | bitToCheck = PORT_STATUS_F3_ENABLED; | |
1409 | break; | |
1410 | default: | |
1411 | break; | |
1412 | } | |
1413 | ||
1414 | temp = ql_read_page0_reg(qdev, &port_regs->portStatus); | |
1415 | if (temp & bitToCheck) { | |
1416 | if (netif_msg_link(qdev)) | |
1417 | printk(KERN_DEBUG PFX | |
1418 | "%s: is not link master.\n", qdev->ndev->name); | |
1419 | return 0; | |
1420 | } else { | |
1421 | if (netif_msg_link(qdev)) | |
1422 | printk(KERN_DEBUG PFX | |
1423 | "%s: is link master.\n", qdev->ndev->name); | |
1424 | return 1; | |
1425 | } | |
1426 | } | |
1427 | ||
3efedf2e | 1428 | static void ql_phy_reset_ex(struct ql3_adapter *qdev) |
5a4faa87 | 1429 | { |
3efedf2e RM |
1430 | ql_mii_write_reg_ex(qdev, CONTROL_REG, PHY_CTRL_SOFT_RESET, |
1431 | PHYAddr[qdev->mac_index]); | |
5a4faa87 RM |
1432 | } |
1433 | ||
3efedf2e | 1434 | static void ql_phy_start_neg_ex(struct ql3_adapter *qdev) |
5a4faa87 RM |
1435 | { |
1436 | u16 reg; | |
3efedf2e RM |
1437 | u16 portConfiguration; |
1438 | ||
1439 | if(qdev->phyType == PHY_AGERE_ET1011C) { | |
1440 | /* turn off external loopback */ | |
1441 | ql_mii_write_reg(qdev, 0x13, 0x0000); | |
1442 | } | |
5a4faa87 | 1443 | |
3efedf2e RM |
1444 | if(qdev->mac_index == 0) |
1445 | portConfiguration = qdev->nvram_data.macCfg_port0.portConfiguration; | |
1446 | else | |
1447 | portConfiguration = qdev->nvram_data.macCfg_port1.portConfiguration; | |
1448 | ||
1449 | /* Some HBA's in the field are set to 0 and they need to | |
1450 | be reinterpreted with a default value */ | |
1451 | if(portConfiguration == 0) | |
1452 | portConfiguration = PORT_CONFIG_DEFAULT; | |
1453 | ||
1454 | /* Set the 1000 advertisements */ | |
1455 | ql_mii_read_reg_ex(qdev, PHY_GIG_CONTROL, ®, | |
1456 | PHYAddr[qdev->mac_index]); | |
1457 | reg &= ~PHY_GIG_ALL_PARAMS; | |
1458 | ||
1459 | if(portConfiguration & | |
1460 | PORT_CONFIG_FULL_DUPLEX_ENABLED & | |
1461 | PORT_CONFIG_1000MB_SPEED) { | |
1462 | reg |= PHY_GIG_ADV_1000F; | |
1463 | } | |
1464 | ||
1465 | if(portConfiguration & | |
1466 | PORT_CONFIG_HALF_DUPLEX_ENABLED & | |
1467 | PORT_CONFIG_1000MB_SPEED) { | |
1468 | reg |= PHY_GIG_ADV_1000H; | |
1469 | } | |
1470 | ||
1471 | ql_mii_write_reg_ex(qdev, PHY_GIG_CONTROL, reg, | |
1472 | PHYAddr[qdev->mac_index]); | |
1473 | ||
1474 | /* Set the 10/100 & pause negotiation advertisements */ | |
1475 | ql_mii_read_reg_ex(qdev, PHY_NEG_ADVER, ®, | |
1476 | PHYAddr[qdev->mac_index]); | |
1477 | reg &= ~PHY_NEG_ALL_PARAMS; | |
1478 | ||
1479 | if(portConfiguration & PORT_CONFIG_SYM_PAUSE_ENABLED) | |
1480 | reg |= PHY_NEG_ASY_PAUSE | PHY_NEG_SYM_PAUSE; | |
1481 | ||
1482 | if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) { | |
1483 | if(portConfiguration & PORT_CONFIG_100MB_SPEED) | |
1484 | reg |= PHY_NEG_ADV_100F; | |
1485 | ||
1486 | if(portConfiguration & PORT_CONFIG_10MB_SPEED) | |
1487 | reg |= PHY_NEG_ADV_10F; | |
1488 | } | |
1489 | ||
1490 | if(portConfiguration & PORT_CONFIG_HALF_DUPLEX_ENABLED) { | |
1491 | if(portConfiguration & PORT_CONFIG_100MB_SPEED) | |
1492 | reg |= PHY_NEG_ADV_100H; | |
1493 | ||
1494 | if(portConfiguration & PORT_CONFIG_10MB_SPEED) | |
1495 | reg |= PHY_NEG_ADV_10H; | |
1496 | } | |
1497 | ||
1498 | if(portConfiguration & | |
1499 | PORT_CONFIG_1000MB_SPEED) { | |
1500 | reg |= 1; | |
1501 | } | |
1502 | ||
1503 | ql_mii_write_reg_ex(qdev, PHY_NEG_ADVER, reg, | |
1504 | PHYAddr[qdev->mac_index]); | |
5a4faa87 | 1505 | |
3efedf2e RM |
1506 | ql_mii_read_reg_ex(qdev, CONTROL_REG, ®, PHYAddr[qdev->mac_index]); |
1507 | ||
1508 | ql_mii_write_reg_ex(qdev, CONTROL_REG, | |
1509 | reg | PHY_CTRL_RESTART_NEG | PHY_CTRL_AUTO_NEG, | |
1510 | PHYAddr[qdev->mac_index]); | |
5a4faa87 RM |
1511 | } |
1512 | ||
3efedf2e | 1513 | static void ql_phy_init_ex(struct ql3_adapter *qdev) |
5a4faa87 | 1514 | { |
3efedf2e RM |
1515 | ql_phy_reset_ex(qdev); |
1516 | PHY_Setup(qdev); | |
1517 | ql_phy_start_neg_ex(qdev); | |
5a4faa87 RM |
1518 | } |
1519 | ||
1520 | /* | |
1521 | * Caller holds hw_lock. | |
1522 | */ | |
1523 | static u32 ql_get_link_state(struct ql3_adapter *qdev) | |
1524 | { | |
1525 | struct ql3xxx_port_registers __iomem *port_regs = | |
1526 | qdev->mem_map_registers; | |
1527 | u32 bitToCheck = 0; | |
1528 | u32 temp, linkState; | |
1529 | ||
1530 | switch (qdev->mac_index) { | |
1531 | case 0: | |
1532 | bitToCheck = PORT_STATUS_UP0; | |
1533 | break; | |
1534 | case 1: | |
1535 | bitToCheck = PORT_STATUS_UP1; | |
1536 | break; | |
1537 | } | |
1538 | temp = ql_read_page0_reg(qdev, &port_regs->portStatus); | |
1539 | if (temp & bitToCheck) { | |
1540 | linkState = LS_UP; | |
1541 | } else { | |
1542 | linkState = LS_DOWN; | |
1543 | if (netif_msg_link(qdev)) | |
1544 | printk(KERN_WARNING PFX | |
1545 | "%s: Link is down.\n", qdev->ndev->name); | |
1546 | } | |
1547 | return linkState; | |
1548 | } | |
1549 | ||
1550 | static int ql_port_start(struct ql3_adapter *qdev) | |
1551 | { | |
1552 | if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, | |
1553 | (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * | |
3efedf2e RM |
1554 | 2) << 7)) { |
1555 | printk(KERN_ERR "%s: Could not get hw lock for GIO\n", | |
1556 | qdev->ndev->name); | |
5a4faa87 | 1557 | return -1; |
3efedf2e | 1558 | } |
5a4faa87 RM |
1559 | |
1560 | if (ql_is_fiber(qdev)) { | |
1561 | ql_petbi_init(qdev); | |
1562 | } else { | |
1563 | /* Copper port */ | |
3efedf2e | 1564 | ql_phy_init_ex(qdev); |
5a4faa87 RM |
1565 | } |
1566 | ||
1567 | ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); | |
1568 | return 0; | |
1569 | } | |
1570 | ||
1571 | static int ql_finish_auto_neg(struct ql3_adapter *qdev) | |
1572 | { | |
1573 | ||
1574 | if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, | |
1575 | (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * | |
1576 | 2) << 7)) | |
1577 | return -1; | |
1578 | ||
1579 | if (!ql_auto_neg_error(qdev)) { | |
1580 | if (test_bit(QL_LINK_MASTER,&qdev->flags)) { | |
1581 | /* configure the MAC */ | |
1582 | if (netif_msg_link(qdev)) | |
1583 | printk(KERN_DEBUG PFX | |
1584 | "%s: Configuring link.\n", | |
1585 | qdev->ndev-> | |
1586 | name); | |
1587 | ql_mac_cfg_soft_reset(qdev, 1); | |
1588 | ql_mac_cfg_gig(qdev, | |
1589 | (ql_get_link_speed | |
1590 | (qdev) == | |
1591 | SPEED_1000)); | |
1592 | ql_mac_cfg_full_dup(qdev, | |
1593 | ql_is_link_full_dup | |
1594 | (qdev)); | |
1595 | ql_mac_cfg_pause(qdev, | |
1596 | ql_is_neg_pause | |
1597 | (qdev)); | |
1598 | ql_mac_cfg_soft_reset(qdev, 0); | |
1599 | ||
1600 | /* enable the MAC */ | |
1601 | if (netif_msg_link(qdev)) | |
1602 | printk(KERN_DEBUG PFX | |
1603 | "%s: Enabling mac.\n", | |
1604 | qdev->ndev-> | |
1605 | name); | |
1606 | ql_mac_enable(qdev, 1); | |
1607 | } | |
1608 | ||
1609 | if (netif_msg_link(qdev)) | |
1610 | printk(KERN_DEBUG PFX | |
1611 | "%s: Change port_link_state LS_DOWN to LS_UP.\n", | |
1612 | qdev->ndev->name); | |
1613 | qdev->port_link_state = LS_UP; | |
1614 | netif_start_queue(qdev->ndev); | |
1615 | netif_carrier_on(qdev->ndev); | |
1616 | if (netif_msg_link(qdev)) | |
1617 | printk(KERN_INFO PFX | |
1618 | "%s: Link is up at %d Mbps, %s duplex.\n", | |
1619 | qdev->ndev->name, | |
1620 | ql_get_link_speed(qdev), | |
1621 | ql_is_link_full_dup(qdev) | |
1622 | ? "full" : "half"); | |
1623 | ||
1624 | } else { /* Remote error detected */ | |
1625 | ||
1626 | if (test_bit(QL_LINK_MASTER,&qdev->flags)) { | |
1627 | if (netif_msg_link(qdev)) | |
1628 | printk(KERN_DEBUG PFX | |
1629 | "%s: Remote error detected. " | |
1630 | "Calling ql_port_start().\n", | |
1631 | qdev->ndev-> | |
1632 | name); | |
1633 | /* | |
1634 | * ql_port_start() is shared code and needs | |
1635 | * to lock the PHY on it's own. | |
1636 | */ | |
1637 | ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); | |
1638 | if(ql_port_start(qdev)) {/* Restart port */ | |
1639 | return -1; | |
1640 | } else | |
1641 | return 0; | |
1642 | } | |
1643 | } | |
1644 | ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); | |
1645 | return 0; | |
1646 | } | |
1647 | ||
1648 | static void ql_link_state_machine(struct ql3_adapter *qdev) | |
1649 | { | |
1650 | u32 curr_link_state; | |
1651 | unsigned long hw_flags; | |
1652 | ||
1653 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
1654 | ||
1655 | curr_link_state = ql_get_link_state(qdev); | |
1656 | ||
1657 | if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) { | |
1658 | if (netif_msg_link(qdev)) | |
1659 | printk(KERN_INFO PFX | |
1660 | "%s: Reset in progress, skip processing link " | |
1661 | "state.\n", qdev->ndev->name); | |
04f10773 BL |
1662 | |
1663 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
5a4faa87 RM |
1664 | return; |
1665 | } | |
1666 | ||
1667 | switch (qdev->port_link_state) { | |
1668 | default: | |
1669 | if (test_bit(QL_LINK_MASTER,&qdev->flags)) { | |
1670 | ql_port_start(qdev); | |
1671 | } | |
1672 | qdev->port_link_state = LS_DOWN; | |
1673 | /* Fall Through */ | |
1674 | ||
1675 | case LS_DOWN: | |
1676 | if (netif_msg_link(qdev)) | |
1677 | printk(KERN_DEBUG PFX | |
1678 | "%s: port_link_state = LS_DOWN.\n", | |
1679 | qdev->ndev->name); | |
1680 | if (curr_link_state == LS_UP) { | |
1681 | if (netif_msg_link(qdev)) | |
1682 | printk(KERN_DEBUG PFX | |
1683 | "%s: curr_link_state = LS_UP.\n", | |
1684 | qdev->ndev->name); | |
1685 | if (ql_is_auto_neg_complete(qdev)) | |
1686 | ql_finish_auto_neg(qdev); | |
1687 | ||
1688 | if (qdev->port_link_state == LS_UP) | |
1689 | ql_link_down_detect_clear(qdev); | |
1690 | ||
1691 | } | |
1692 | break; | |
1693 | ||
1694 | case LS_UP: | |
1695 | /* | |
1696 | * See if the link is currently down or went down and came | |
1697 | * back up | |
1698 | */ | |
1699 | if ((curr_link_state == LS_DOWN) || ql_link_down_detect(qdev)) { | |
1700 | if (netif_msg_link(qdev)) | |
1701 | printk(KERN_INFO PFX "%s: Link is down.\n", | |
1702 | qdev->ndev->name); | |
1703 | qdev->port_link_state = LS_DOWN; | |
1704 | } | |
1705 | break; | |
1706 | } | |
1707 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
1708 | } | |
1709 | ||
1710 | /* | |
1711 | * Caller must take hw_lock and QL_PHY_GIO_SEM. | |
1712 | */ | |
1713 | static void ql_get_phy_owner(struct ql3_adapter *qdev) | |
1714 | { | |
3efedf2e | 1715 | if (ql_this_adapter_controls_port(qdev)) |
5a4faa87 RM |
1716 | set_bit(QL_LINK_MASTER,&qdev->flags); |
1717 | else | |
1718 | clear_bit(QL_LINK_MASTER,&qdev->flags); | |
1719 | } | |
1720 | ||
1721 | /* | |
1722 | * Caller must take hw_lock and QL_PHY_GIO_SEM. | |
1723 | */ | |
1724 | static void ql_init_scan_mode(struct ql3_adapter *qdev) | |
1725 | { | |
1726 | ql_mii_enable_scan_mode(qdev); | |
1727 | ||
1728 | if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) { | |
3efedf2e RM |
1729 | if (ql_this_adapter_controls_port(qdev)) |
1730 | ql_petbi_init_ex(qdev); | |
5a4faa87 | 1731 | } else { |
3efedf2e RM |
1732 | if (ql_this_adapter_controls_port(qdev)) |
1733 | ql_phy_init_ex(qdev); | |
5a4faa87 RM |
1734 | } |
1735 | } | |
1736 | ||
1737 | /* | |
1738 | * MII_Setup needs to be called before taking the PHY out of reset so that the | |
1739 | * management interface clock speed can be set properly. It would be better if | |
1740 | * we had a way to disable MDC until after the PHY is out of reset, but we | |
1741 | * don't have that capability. | |
1742 | */ | |
1743 | static int ql_mii_setup(struct ql3_adapter *qdev) | |
1744 | { | |
1745 | u32 reg; | |
1746 | struct ql3xxx_port_registers __iomem *port_regs = | |
1747 | qdev->mem_map_registers; | |
1748 | ||
1749 | if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, | |
1750 | (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * | |
1751 | 2) << 7)) | |
1752 | return -1; | |
1753 | ||
bd36b0ac RM |
1754 | if (qdev->device_id == QL3032_DEVICE_ID) |
1755 | ql_write_page0_reg(qdev, | |
1756 | &port_regs->macMIIMgmtControlReg, 0x0f00000); | |
1757 | ||
5a4faa87 RM |
1758 | /* Divide 125MHz clock by 28 to meet PHY timing requirements */ |
1759 | reg = MAC_MII_CONTROL_CLK_SEL_DIV28; | |
1760 | ||
1761 | ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg, | |
1762 | reg | ((MAC_MII_CONTROL_CLK_SEL_MASK) << 16)); | |
1763 | ||
1764 | ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); | |
1765 | return 0; | |
1766 | } | |
1767 | ||
1768 | static u32 ql_supported_modes(struct ql3_adapter *qdev) | |
1769 | { | |
1770 | u32 supported; | |
1771 | ||
1772 | if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) { | |
1773 | supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | |
1774 | | SUPPORTED_Autoneg; | |
1775 | } else { | |
1776 | supported = SUPPORTED_10baseT_Half | |
1777 | | SUPPORTED_10baseT_Full | |
1778 | | SUPPORTED_100baseT_Half | |
1779 | | SUPPORTED_100baseT_Full | |
1780 | | SUPPORTED_1000baseT_Half | |
1781 | | SUPPORTED_1000baseT_Full | |
1782 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
1783 | } | |
1784 | ||
1785 | return supported; | |
1786 | } | |
1787 | ||
1788 | static int ql_get_auto_cfg_status(struct ql3_adapter *qdev) | |
1789 | { | |
1790 | int status; | |
1791 | unsigned long hw_flags; | |
1792 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
1793 | if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, | |
1794 | (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * | |
04f10773 BL |
1795 | 2) << 7)) { |
1796 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
5a4faa87 | 1797 | return 0; |
04f10773 | 1798 | } |
5a4faa87 RM |
1799 | status = ql_is_auto_cfg(qdev); |
1800 | ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); | |
1801 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
1802 | return status; | |
1803 | } | |
1804 | ||
1805 | static u32 ql_get_speed(struct ql3_adapter *qdev) | |
1806 | { | |
1807 | u32 status; | |
1808 | unsigned long hw_flags; | |
1809 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
1810 | if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, | |
1811 | (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * | |
04f10773 BL |
1812 | 2) << 7)) { |
1813 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
5a4faa87 | 1814 | return 0; |
04f10773 | 1815 | } |
5a4faa87 RM |
1816 | status = ql_get_link_speed(qdev); |
1817 | ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); | |
1818 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
1819 | return status; | |
1820 | } | |
1821 | ||
1822 | static int ql_get_full_dup(struct ql3_adapter *qdev) | |
1823 | { | |
1824 | int status; | |
1825 | unsigned long hw_flags; | |
1826 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
1827 | if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, | |
1828 | (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * | |
04f10773 BL |
1829 | 2) << 7)) { |
1830 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
5a4faa87 | 1831 | return 0; |
04f10773 | 1832 | } |
5a4faa87 RM |
1833 | status = ql_is_link_full_dup(qdev); |
1834 | ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); | |
1835 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
1836 | return status; | |
1837 | } | |
1838 | ||
1839 | ||
1840 | static int ql_get_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) | |
1841 | { | |
1842 | struct ql3_adapter *qdev = netdev_priv(ndev); | |
1843 | ||
1844 | ecmd->transceiver = XCVR_INTERNAL; | |
1845 | ecmd->supported = ql_supported_modes(qdev); | |
1846 | ||
1847 | if (test_bit(QL_LINK_OPTICAL,&qdev->flags)) { | |
1848 | ecmd->port = PORT_FIBRE; | |
1849 | } else { | |
1850 | ecmd->port = PORT_TP; | |
1851 | ecmd->phy_address = qdev->PHYAddr; | |
1852 | } | |
1853 | ecmd->advertising = ql_supported_modes(qdev); | |
1854 | ecmd->autoneg = ql_get_auto_cfg_status(qdev); | |
1855 | ecmd->speed = ql_get_speed(qdev); | |
1856 | ecmd->duplex = ql_get_full_dup(qdev); | |
1857 | return 0; | |
1858 | } | |
1859 | ||
1860 | static void ql_get_drvinfo(struct net_device *ndev, | |
1861 | struct ethtool_drvinfo *drvinfo) | |
1862 | { | |
1863 | struct ql3_adapter *qdev = netdev_priv(ndev); | |
1864 | strncpy(drvinfo->driver, ql3xxx_driver_name, 32); | |
1865 | strncpy(drvinfo->version, ql3xxx_driver_version, 32); | |
1866 | strncpy(drvinfo->fw_version, "N/A", 32); | |
1867 | strncpy(drvinfo->bus_info, pci_name(qdev->pdev), 32); | |
1868 | drvinfo->n_stats = 0; | |
1869 | drvinfo->testinfo_len = 0; | |
1870 | drvinfo->regdump_len = 0; | |
1871 | drvinfo->eedump_len = 0; | |
1872 | } | |
1873 | ||
1874 | static u32 ql_get_msglevel(struct net_device *ndev) | |
1875 | { | |
1876 | struct ql3_adapter *qdev = netdev_priv(ndev); | |
1877 | return qdev->msg_enable; | |
1878 | } | |
1879 | ||
1880 | static void ql_set_msglevel(struct net_device *ndev, u32 value) | |
1881 | { | |
1882 | struct ql3_adapter *qdev = netdev_priv(ndev); | |
1883 | qdev->msg_enable = value; | |
1884 | } | |
1885 | ||
ec826383 RM |
1886 | static void ql_get_pauseparam(struct net_device *ndev, |
1887 | struct ethtool_pauseparam *pause) | |
1888 | { | |
1889 | struct ql3_adapter *qdev = netdev_priv(ndev); | |
1890 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
1891 | ||
1892 | u32 reg; | |
1893 | if(qdev->mac_index == 0) | |
1894 | reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg); | |
1895 | else | |
1896 | reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg); | |
1897 | ||
1898 | pause->autoneg = ql_get_auto_cfg_status(qdev); | |
1899 | pause->rx_pause = (reg & MAC_CONFIG_REG_RF) >> 2; | |
1900 | pause->tx_pause = (reg & MAC_CONFIG_REG_TF) >> 1; | |
1901 | } | |
1902 | ||
7282d491 | 1903 | static const struct ethtool_ops ql3xxx_ethtool_ops = { |
5a4faa87 RM |
1904 | .get_settings = ql_get_settings, |
1905 | .get_drvinfo = ql_get_drvinfo, | |
5a4faa87 RM |
1906 | .get_link = ethtool_op_get_link, |
1907 | .get_msglevel = ql_get_msglevel, | |
1908 | .set_msglevel = ql_set_msglevel, | |
ec826383 | 1909 | .get_pauseparam = ql_get_pauseparam, |
5a4faa87 RM |
1910 | }; |
1911 | ||
1912 | static int ql_populate_free_queue(struct ql3_adapter *qdev) | |
1913 | { | |
1914 | struct ql_rcv_buf_cb *lrg_buf_cb = qdev->lrg_buf_free_head; | |
0f8ab89e BL |
1915 | dma_addr_t map; |
1916 | int err; | |
5a4faa87 RM |
1917 | |
1918 | while (lrg_buf_cb) { | |
1919 | if (!lrg_buf_cb->skb) { | |
cd238faa BL |
1920 | lrg_buf_cb->skb = netdev_alloc_skb(qdev->ndev, |
1921 | qdev->lrg_buffer_len); | |
5a4faa87 RM |
1922 | if (unlikely(!lrg_buf_cb->skb)) { |
1923 | printk(KERN_DEBUG PFX | |
cd238faa | 1924 | "%s: Failed netdev_alloc_skb().\n", |
5a4faa87 RM |
1925 | qdev->ndev->name); |
1926 | break; | |
1927 | } else { | |
1928 | /* | |
1929 | * We save some space to copy the ethhdr from | |
1930 | * first buffer | |
1931 | */ | |
1932 | skb_reserve(lrg_buf_cb->skb, QL_HEADER_SPACE); | |
1933 | map = pci_map_single(qdev->pdev, | |
1934 | lrg_buf_cb->skb->data, | |
1935 | qdev->lrg_buffer_len - | |
1936 | QL_HEADER_SPACE, | |
1937 | PCI_DMA_FROMDEVICE); | |
0f8ab89e BL |
1938 | |
1939 | err = pci_dma_mapping_error(map); | |
1940 | if(err) { | |
1941 | printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", | |
1942 | qdev->ndev->name, err); | |
1943 | dev_kfree_skb(lrg_buf_cb->skb); | |
1944 | lrg_buf_cb->skb = NULL; | |
1945 | break; | |
1946 | } | |
1947 | ||
1948 | ||
5a4faa87 RM |
1949 | lrg_buf_cb->buf_phy_addr_low = |
1950 | cpu_to_le32(LS_64BITS(map)); | |
1951 | lrg_buf_cb->buf_phy_addr_high = | |
1952 | cpu_to_le32(MS_64BITS(map)); | |
1953 | pci_unmap_addr_set(lrg_buf_cb, mapaddr, map); | |
1954 | pci_unmap_len_set(lrg_buf_cb, maplen, | |
1955 | qdev->lrg_buffer_len - | |
1956 | QL_HEADER_SPACE); | |
1957 | --qdev->lrg_buf_skb_check; | |
1958 | if (!qdev->lrg_buf_skb_check) | |
1959 | return 1; | |
1960 | } | |
1961 | } | |
1962 | lrg_buf_cb = lrg_buf_cb->next; | |
1963 | } | |
1964 | return 0; | |
1965 | } | |
1966 | ||
f67cac01 RM |
1967 | /* |
1968 | * Caller holds hw_lock. | |
1969 | */ | |
1970 | static void ql_update_small_bufq_prod_index(struct ql3_adapter *qdev) | |
1971 | { | |
1972 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
1973 | if (qdev->small_buf_release_cnt >= 16) { | |
1974 | while (qdev->small_buf_release_cnt >= 16) { | |
1975 | qdev->small_buf_q_producer_index++; | |
1976 | ||
1977 | if (qdev->small_buf_q_producer_index == | |
1978 | NUM_SBUFQ_ENTRIES) | |
1979 | qdev->small_buf_q_producer_index = 0; | |
1980 | qdev->small_buf_release_cnt -= 8; | |
1981 | } | |
1982 | wmb(); | |
1983 | writel(qdev->small_buf_q_producer_index, | |
1984 | &port_regs->CommonRegs.rxSmallQProducerIndex); | |
1985 | } | |
1986 | } | |
1987 | ||
5a4faa87 RM |
1988 | /* |
1989 | * Caller holds hw_lock. | |
1990 | */ | |
1991 | static void ql_update_lrg_bufq_prod_index(struct ql3_adapter *qdev) | |
1992 | { | |
1993 | struct bufq_addr_element *lrg_buf_q_ele; | |
1994 | int i; | |
1995 | struct ql_rcv_buf_cb *lrg_buf_cb; | |
1996 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
1997 | ||
1998 | if ((qdev->lrg_buf_free_count >= 8) | |
1999 | && (qdev->lrg_buf_release_cnt >= 16)) { | |
2000 | ||
2001 | if (qdev->lrg_buf_skb_check) | |
2002 | if (!ql_populate_free_queue(qdev)) | |
2003 | return; | |
2004 | ||
2005 | lrg_buf_q_ele = qdev->lrg_buf_next_free; | |
2006 | ||
2007 | while ((qdev->lrg_buf_release_cnt >= 16) | |
2008 | && (qdev->lrg_buf_free_count >= 8)) { | |
2009 | ||
2010 | for (i = 0; i < 8; i++) { | |
2011 | lrg_buf_cb = | |
2012 | ql_get_from_lrg_buf_free_list(qdev); | |
2013 | lrg_buf_q_ele->addr_high = | |
2014 | lrg_buf_cb->buf_phy_addr_high; | |
2015 | lrg_buf_q_ele->addr_low = | |
2016 | lrg_buf_cb->buf_phy_addr_low; | |
2017 | lrg_buf_q_ele++; | |
2018 | ||
2019 | qdev->lrg_buf_release_cnt--; | |
2020 | } | |
2021 | ||
2022 | qdev->lrg_buf_q_producer_index++; | |
2023 | ||
1357bfcf | 2024 | if (qdev->lrg_buf_q_producer_index == qdev->num_lbufq_entries) |
5a4faa87 RM |
2025 | qdev->lrg_buf_q_producer_index = 0; |
2026 | ||
2027 | if (qdev->lrg_buf_q_producer_index == | |
1357bfcf | 2028 | (qdev->num_lbufq_entries - 1)) { |
5a4faa87 RM |
2029 | lrg_buf_q_ele = qdev->lrg_buf_q_virt_addr; |
2030 | } | |
2031 | } | |
f67cac01 | 2032 | wmb(); |
5a4faa87 | 2033 | qdev->lrg_buf_next_free = lrg_buf_q_ele; |
f67cac01 RM |
2034 | writel(qdev->lrg_buf_q_producer_index, |
2035 | &port_regs->CommonRegs.rxLargeQProducerIndex); | |
5a4faa87 RM |
2036 | } |
2037 | } | |
2038 | ||
2039 | static void ql_process_mac_tx_intr(struct ql3_adapter *qdev, | |
2040 | struct ob_mac_iocb_rsp *mac_rsp) | |
2041 | { | |
2042 | struct ql_tx_buf_cb *tx_cb; | |
bd36b0ac | 2043 | int i; |
e8f4df24 | 2044 | int retval = 0; |
5a4faa87 | 2045 | |
e8f4df24 BL |
2046 | if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) { |
2047 | printk(KERN_WARNING "Frame short but, frame was padded and sent.\n"); | |
2048 | } | |
2049 | ||
5a4faa87 | 2050 | tx_cb = &qdev->tx_buf[mac_rsp->transaction_id]; |
e8f4df24 BL |
2051 | |
2052 | /* Check the transmit response flags for any errors */ | |
2053 | if(mac_rsp->flags & OB_MAC_IOCB_RSP_S) { | |
2054 | printk(KERN_ERR "Frame too short to be legal, frame not sent.\n"); | |
2055 | ||
09f75cd7 | 2056 | qdev->ndev->stats.tx_errors++; |
e8f4df24 BL |
2057 | retval = -EIO; |
2058 | goto frame_not_sent; | |
2059 | } | |
2060 | ||
2061 | if(tx_cb->seg_count == 0) { | |
2062 | printk(KERN_ERR "tx_cb->seg_count == 0: %d\n", mac_rsp->transaction_id); | |
2063 | ||
09f75cd7 | 2064 | qdev->ndev->stats.tx_errors++; |
e8f4df24 BL |
2065 | retval = -EIO; |
2066 | goto invalid_seg_count; | |
2067 | } | |
2068 | ||
5a4faa87 | 2069 | pci_unmap_single(qdev->pdev, |
bd36b0ac RM |
2070 | pci_unmap_addr(&tx_cb->map[0], mapaddr), |
2071 | pci_unmap_len(&tx_cb->map[0], maplen), | |
2072 | PCI_DMA_TODEVICE); | |
2073 | tx_cb->seg_count--; | |
2074 | if (tx_cb->seg_count) { | |
2075 | for (i = 1; i < tx_cb->seg_count; i++) { | |
2076 | pci_unmap_page(qdev->pdev, | |
2077 | pci_unmap_addr(&tx_cb->map[i], | |
2078 | mapaddr), | |
2079 | pci_unmap_len(&tx_cb->map[i], maplen), | |
2080 | PCI_DMA_TODEVICE); | |
2081 | } | |
2082 | } | |
09f75cd7 JG |
2083 | qdev->ndev->stats.tx_packets++; |
2084 | qdev->ndev->stats.tx_bytes += tx_cb->skb->len; | |
e8f4df24 BL |
2085 | |
2086 | frame_not_sent: | |
bd36b0ac | 2087 | dev_kfree_skb_irq(tx_cb->skb); |
5a4faa87 | 2088 | tx_cb->skb = NULL; |
e8f4df24 BL |
2089 | |
2090 | invalid_seg_count: | |
5a4faa87 RM |
2091 | atomic_inc(&qdev->tx_count); |
2092 | } | |
2093 | ||
3664006a | 2094 | static void ql_get_sbuf(struct ql3_adapter *qdev) |
97916330 RM |
2095 | { |
2096 | if (++qdev->small_buf_index == NUM_SMALL_BUFFERS) | |
2097 | qdev->small_buf_index = 0; | |
2098 | qdev->small_buf_release_cnt++; | |
2099 | } | |
2100 | ||
3664006a | 2101 | static struct ql_rcv_buf_cb *ql_get_lbuf(struct ql3_adapter *qdev) |
97916330 RM |
2102 | { |
2103 | struct ql_rcv_buf_cb *lrg_buf_cb = NULL; | |
2104 | lrg_buf_cb = &qdev->lrg_buf[qdev->lrg_buf_index]; | |
2105 | qdev->lrg_buf_release_cnt++; | |
2106 | if (++qdev->lrg_buf_index == qdev->num_large_buffers) | |
2107 | qdev->lrg_buf_index = 0; | |
2108 | return(lrg_buf_cb); | |
2109 | } | |
2110 | ||
bd36b0ac RM |
2111 | /* |
2112 | * The difference between 3022 and 3032 for inbound completions: | |
2113 | * 3022 uses two buffers per completion. The first buffer contains | |
2114 | * (some) header info, the second the remainder of the headers plus | |
2115 | * the data. For this chip we reserve some space at the top of the | |
2116 | * receive buffer so that the header info in buffer one can be | |
2117 | * prepended to the buffer two. Buffer two is the sent up while | |
2118 | * buffer one is returned to the hardware to be reused. | |
2119 | * 3032 receives all of it's data and headers in one buffer for a | |
2120 | * simpler process. 3032 also supports checksum verification as | |
2121 | * can be seen in ql_process_macip_rx_intr(). | |
2122 | */ | |
5a4faa87 RM |
2123 | static void ql_process_mac_rx_intr(struct ql3_adapter *qdev, |
2124 | struct ib_mac_iocb_rsp *ib_mac_rsp_ptr) | |
2125 | { | |
5a4faa87 RM |
2126 | struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL; |
2127 | struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL; | |
5a4faa87 RM |
2128 | struct sk_buff *skb; |
2129 | u16 length = le16_to_cpu(ib_mac_rsp_ptr->length); | |
2130 | ||
2131 | /* | |
2132 | * Get the inbound address list (small buffer). | |
2133 | */ | |
97916330 | 2134 | ql_get_sbuf(qdev); |
5a4faa87 | 2135 | |
97916330 RM |
2136 | if (qdev->device_id == QL3022_DEVICE_ID) |
2137 | lrg_buf_cb1 = ql_get_lbuf(qdev); | |
5a4faa87 RM |
2138 | |
2139 | /* start of second buffer */ | |
97916330 | 2140 | lrg_buf_cb2 = ql_get_lbuf(qdev); |
5a4faa87 RM |
2141 | skb = lrg_buf_cb2->skb; |
2142 | ||
09f75cd7 JG |
2143 | qdev->ndev->stats.rx_packets++; |
2144 | qdev->ndev->stats.rx_bytes += length; | |
5a4faa87 RM |
2145 | |
2146 | skb_put(skb, length); | |
2147 | pci_unmap_single(qdev->pdev, | |
2148 | pci_unmap_addr(lrg_buf_cb2, mapaddr), | |
2149 | pci_unmap_len(lrg_buf_cb2, maplen), | |
2150 | PCI_DMA_FROMDEVICE); | |
2151 | prefetch(skb->data); | |
5a4faa87 RM |
2152 | skb->ip_summed = CHECKSUM_NONE; |
2153 | skb->protocol = eth_type_trans(skb, qdev->ndev); | |
2154 | ||
2155 | netif_receive_skb(skb); | |
2156 | qdev->ndev->last_rx = jiffies; | |
2157 | lrg_buf_cb2->skb = NULL; | |
2158 | ||
bd36b0ac RM |
2159 | if (qdev->device_id == QL3022_DEVICE_ID) |
2160 | ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1); | |
5a4faa87 RM |
2161 | ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2); |
2162 | } | |
2163 | ||
2164 | static void ql_process_macip_rx_intr(struct ql3_adapter *qdev, | |
2165 | struct ib_ip_iocb_rsp *ib_ip_rsp_ptr) | |
2166 | { | |
5a4faa87 RM |
2167 | struct ql_rcv_buf_cb *lrg_buf_cb1 = NULL; |
2168 | struct ql_rcv_buf_cb *lrg_buf_cb2 = NULL; | |
bd36b0ac | 2169 | struct sk_buff *skb1 = NULL, *skb2; |
5a4faa87 RM |
2170 | struct net_device *ndev = qdev->ndev; |
2171 | u16 length = le16_to_cpu(ib_ip_rsp_ptr->length); | |
2172 | u16 size = 0; | |
2173 | ||
2174 | /* | |
2175 | * Get the inbound address list (small buffer). | |
2176 | */ | |
2177 | ||
97916330 | 2178 | ql_get_sbuf(qdev); |
5a4faa87 | 2179 | |
bd36b0ac RM |
2180 | if (qdev->device_id == QL3022_DEVICE_ID) { |
2181 | /* start of first buffer on 3022 */ | |
97916330 | 2182 | lrg_buf_cb1 = ql_get_lbuf(qdev); |
bd36b0ac | 2183 | skb1 = lrg_buf_cb1->skb; |
bd36b0ac RM |
2184 | size = ETH_HLEN; |
2185 | if (*((u16 *) skb1->data) != 0xFFFF) | |
2186 | size += VLAN_ETH_HLEN - ETH_HLEN; | |
2187 | } | |
5a4faa87 RM |
2188 | |
2189 | /* start of second buffer */ | |
97916330 | 2190 | lrg_buf_cb2 = ql_get_lbuf(qdev); |
5a4faa87 | 2191 | skb2 = lrg_buf_cb2->skb; |
5a4faa87 | 2192 | |
5a4faa87 RM |
2193 | skb_put(skb2, length); /* Just the second buffer length here. */ |
2194 | pci_unmap_single(qdev->pdev, | |
2195 | pci_unmap_addr(lrg_buf_cb2, mapaddr), | |
2196 | pci_unmap_len(lrg_buf_cb2, maplen), | |
2197 | PCI_DMA_FROMDEVICE); | |
2198 | prefetch(skb2->data); | |
2199 | ||
5a4faa87 | 2200 | skb2->ip_summed = CHECKSUM_NONE; |
bd36b0ac RM |
2201 | if (qdev->device_id == QL3022_DEVICE_ID) { |
2202 | /* | |
2203 | * Copy the ethhdr from first buffer to second. This | |
2204 | * is necessary for 3022 IP completions. | |
2205 | */ | |
d626f62b ACM |
2206 | skb_copy_from_linear_data_offset(skb1, VLAN_ID_LEN, |
2207 | skb_push(skb2, size), size); | |
bd36b0ac RM |
2208 | } else { |
2209 | u16 checksum = le16_to_cpu(ib_ip_rsp_ptr->checksum); | |
2210 | if (checksum & | |
2211 | (IB_IP_IOCB_RSP_3032_ICE | | |
b3b1514c | 2212 | IB_IP_IOCB_RSP_3032_CE)) { |
bd36b0ac RM |
2213 | printk(KERN_ERR |
2214 | "%s: Bad checksum for this %s packet, checksum = %x.\n", | |
2215 | __func__, | |
2216 | ((checksum & | |
2217 | IB_IP_IOCB_RSP_3032_TCP) ? "TCP" : | |
2218 | "UDP"),checksum); | |
b3b1514c RM |
2219 | } else if ((checksum & IB_IP_IOCB_RSP_3032_TCP) || |
2220 | (checksum & IB_IP_IOCB_RSP_3032_UDP && | |
2221 | !(checksum & IB_IP_IOCB_RSP_3032_NUC))) { | |
bd36b0ac | 2222 | skb2->ip_summed = CHECKSUM_UNNECESSARY; |
b3b1514c | 2223 | } |
bd36b0ac | 2224 | } |
5a4faa87 RM |
2225 | skb2->protocol = eth_type_trans(skb2, qdev->ndev); |
2226 | ||
2227 | netif_receive_skb(skb2); | |
09f75cd7 JG |
2228 | ndev->stats.rx_packets++; |
2229 | ndev->stats.rx_bytes += length; | |
5a4faa87 RM |
2230 | ndev->last_rx = jiffies; |
2231 | lrg_buf_cb2->skb = NULL; | |
2232 | ||
bd36b0ac RM |
2233 | if (qdev->device_id == QL3022_DEVICE_ID) |
2234 | ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb1); | |
5a4faa87 RM |
2235 | ql_release_to_lrg_buf_free_list(qdev, lrg_buf_cb2); |
2236 | } | |
2237 | ||
2238 | static int ql_tx_rx_clean(struct ql3_adapter *qdev, | |
2239 | int *tx_cleaned, int *rx_cleaned, int work_to_do) | |
2240 | { | |
5a4faa87 RM |
2241 | struct net_rsp_iocb *net_rsp; |
2242 | struct net_device *ndev = qdev->ndev; | |
63b66d12 | 2243 | int work_done = 0; |
5a4faa87 RM |
2244 | |
2245 | /* While there are entries in the completion queue. */ | |
f67cac01 | 2246 | while ((le32_to_cpu(*(qdev->prsp_producer_index)) != |
63b66d12 | 2247 | qdev->rsp_consumer_index) && (work_done < work_to_do)) { |
5a4faa87 RM |
2248 | |
2249 | net_rsp = qdev->rsp_current; | |
b323e0e4 | 2250 | rmb(); |
50626297 RM |
2251 | /* |
2252 | * Fix 4032 chipe undocumented "feature" where bit-8 is set if the | |
2253 | * inbound completion is for a VLAN. | |
2254 | */ | |
2255 | if (qdev->device_id == QL3032_DEVICE_ID) | |
2256 | net_rsp->opcode &= 0x7f; | |
5a4faa87 RM |
2257 | switch (net_rsp->opcode) { |
2258 | ||
2259 | case OPCODE_OB_MAC_IOCB_FN0: | |
2260 | case OPCODE_OB_MAC_IOCB_FN2: | |
2261 | ql_process_mac_tx_intr(qdev, (struct ob_mac_iocb_rsp *) | |
2262 | net_rsp); | |
2263 | (*tx_cleaned)++; | |
2264 | break; | |
2265 | ||
2266 | case OPCODE_IB_MAC_IOCB: | |
bd36b0ac | 2267 | case OPCODE_IB_3032_MAC_IOCB: |
5a4faa87 RM |
2268 | ql_process_mac_rx_intr(qdev, (struct ib_mac_iocb_rsp *) |
2269 | net_rsp); | |
2270 | (*rx_cleaned)++; | |
2271 | break; | |
2272 | ||
2273 | case OPCODE_IB_IP_IOCB: | |
bd36b0ac | 2274 | case OPCODE_IB_3032_IP_IOCB: |
5a4faa87 RM |
2275 | ql_process_macip_rx_intr(qdev, (struct ib_ip_iocb_rsp *) |
2276 | net_rsp); | |
2277 | (*rx_cleaned)++; | |
2278 | break; | |
2279 | default: | |
2280 | { | |
2281 | u32 *tmp = (u32 *) net_rsp; | |
2282 | printk(KERN_ERR PFX | |
2283 | "%s: Hit default case, not " | |
2284 | "handled!\n" | |
2285 | " dropping the packet, opcode = " | |
2286 | "%x.\n", | |
2287 | ndev->name, net_rsp->opcode); | |
2288 | printk(KERN_ERR PFX | |
2289 | "0x%08lx 0x%08lx 0x%08lx 0x%08lx \n", | |
2290 | (unsigned long int)tmp[0], | |
2291 | (unsigned long int)tmp[1], | |
2292 | (unsigned long int)tmp[2], | |
2293 | (unsigned long int)tmp[3]); | |
2294 | } | |
2295 | } | |
2296 | ||
2297 | qdev->rsp_consumer_index++; | |
2298 | ||
2299 | if (qdev->rsp_consumer_index == NUM_RSP_Q_ENTRIES) { | |
2300 | qdev->rsp_consumer_index = 0; | |
2301 | qdev->rsp_current = qdev->rsp_q_virt_addr; | |
2302 | } else { | |
2303 | qdev->rsp_current++; | |
2304 | } | |
63b66d12 RM |
2305 | |
2306 | work_done = *tx_cleaned + *rx_cleaned; | |
5a4faa87 RM |
2307 | } |
2308 | ||
f67cac01 | 2309 | return work_done; |
5a4faa87 RM |
2310 | } |
2311 | ||
bea3348e | 2312 | static int ql_poll(struct napi_struct *napi, int budget) |
5a4faa87 | 2313 | { |
bea3348e SH |
2314 | struct ql3_adapter *qdev = container_of(napi, struct ql3_adapter, napi); |
2315 | struct net_device *ndev = qdev->ndev; | |
5a4faa87 | 2316 | int rx_cleaned = 0, tx_cleaned = 0; |
63b66d12 RM |
2317 | unsigned long hw_flags; |
2318 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
5a4faa87 RM |
2319 | |
2320 | if (!netif_carrier_ok(ndev)) | |
2321 | goto quit_polling; | |
2322 | ||
bea3348e | 2323 | ql_tx_rx_clean(qdev, &tx_cleaned, &rx_cleaned, budget); |
5a4faa87 | 2324 | |
bea3348e | 2325 | if (tx_cleaned + rx_cleaned != budget || |
e8f4df24 | 2326 | !netif_running(ndev)) { |
5a4faa87 | 2327 | quit_polling: |
63b66d12 | 2328 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); |
bea3348e | 2329 | __netif_rx_complete(ndev, napi); |
f67cac01 RM |
2330 | ql_update_small_bufq_prod_index(qdev); |
2331 | ql_update_lrg_bufq_prod_index(qdev); | |
2332 | writel(qdev->rsp_consumer_index, | |
2333 | &port_regs->CommonRegs.rspQConsumerIndex); | |
63b66d12 RM |
2334 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); |
2335 | ||
5a4faa87 | 2336 | ql_enable_interrupts(qdev); |
5a4faa87 | 2337 | } |
bea3348e | 2338 | return tx_cleaned + rx_cleaned; |
5a4faa87 RM |
2339 | } |
2340 | ||
7d12e780 | 2341 | static irqreturn_t ql3xxx_isr(int irq, void *dev_id) |
5a4faa87 RM |
2342 | { |
2343 | ||
2344 | struct net_device *ndev = dev_id; | |
2345 | struct ql3_adapter *qdev = netdev_priv(ndev); | |
2346 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
2347 | u32 value; | |
2348 | int handled = 1; | |
2349 | u32 var; | |
2350 | ||
2351 | port_regs = qdev->mem_map_registers; | |
2352 | ||
2353 | value = | |
2354 | ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus); | |
2355 | ||
2356 | if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) { | |
2357 | spin_lock(&qdev->adapter_lock); | |
2358 | netif_stop_queue(qdev->ndev); | |
2359 | netif_carrier_off(qdev->ndev); | |
2360 | ql_disable_interrupts(qdev); | |
2361 | qdev->port_link_state = LS_DOWN; | |
2362 | set_bit(QL_RESET_ACTIVE,&qdev->flags) ; | |
2363 | ||
2364 | if (value & ISP_CONTROL_FE) { | |
2365 | /* | |
2366 | * Chip Fatal Error. | |
2367 | */ | |
2368 | var = | |
2369 | ql_read_page0_reg_l(qdev, | |
2370 | &port_regs->PortFatalErrStatus); | |
2371 | printk(KERN_WARNING PFX | |
2372 | "%s: Resetting chip. PortFatalErrStatus " | |
2373 | "register = 0x%x\n", ndev->name, var); | |
2374 | set_bit(QL_RESET_START,&qdev->flags) ; | |
2375 | } else { | |
2376 | /* | |
2377 | * Soft Reset Requested. | |
2378 | */ | |
2379 | set_bit(QL_RESET_PER_SCSI,&qdev->flags) ; | |
2380 | printk(KERN_ERR PFX | |
2381 | "%s: Another function issued a reset to the " | |
2382 | "chip. ISR value = %x.\n", ndev->name, value); | |
2383 | } | |
c4028958 | 2384 | queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0); |
5a4faa87 RM |
2385 | spin_unlock(&qdev->adapter_lock); |
2386 | } else if (value & ISP_IMR_DISABLE_CMPL_INT) { | |
e8f4df24 | 2387 | ql_disable_interrupts(qdev); |
bea3348e SH |
2388 | if (likely(netif_rx_schedule_prep(ndev, &qdev->napi))) { |
2389 | __netif_rx_schedule(ndev, &qdev->napi); | |
63b66d12 | 2390 | } |
5a4faa87 RM |
2391 | } else { |
2392 | return IRQ_NONE; | |
2393 | } | |
2394 | ||
2395 | return IRQ_RETVAL(handled); | |
2396 | } | |
2397 | ||
bd36b0ac RM |
2398 | /* |
2399 | * Get the total number of segments needed for the | |
2400 | * given number of fragments. This is necessary because | |
2401 | * outbound address lists (OAL) will be used when more than | |
2402 | * two frags are given. Each address list has 5 addr/len | |
2403 | * pairs. The 5th pair in each AOL is used to point to | |
2404 | * the next AOL if more frags are coming. | |
2405 | * That is why the frags:segment count ratio is not linear. | |
2406 | */ | |
e8f4df24 BL |
2407 | static int ql_get_seg_count(struct ql3_adapter *qdev, |
2408 | unsigned short frags) | |
bd36b0ac | 2409 | { |
e8f4df24 BL |
2410 | if (qdev->device_id == QL3022_DEVICE_ID) |
2411 | return 1; | |
2412 | ||
bd36b0ac RM |
2413 | switch(frags) { |
2414 | case 0: return 1; /* just the skb->data seg */ | |
2415 | case 1: return 2; /* skb->data + 1 frag */ | |
2416 | case 2: return 3; /* skb->data + 2 frags */ | |
2417 | case 3: return 5; /* skb->data + 1 frag + 1 AOL containting 2 frags */ | |
2418 | case 4: return 6; | |
2419 | case 5: return 7; | |
2420 | case 6: return 8; | |
2421 | case 7: return 10; | |
2422 | case 8: return 11; | |
2423 | case 9: return 12; | |
2424 | case 10: return 13; | |
2425 | case 11: return 15; | |
2426 | case 12: return 16; | |
2427 | case 13: return 17; | |
2428 | case 14: return 18; | |
2429 | case 15: return 20; | |
2430 | case 16: return 21; | |
2431 | case 17: return 22; | |
2432 | case 18: return 23; | |
2433 | } | |
2434 | return -1; | |
2435 | } | |
2436 | ||
91e745aa | 2437 | static void ql_hw_csum_setup(const struct sk_buff *skb, |
bd36b0ac RM |
2438 | struct ob_mac_iocb_req *mac_iocb_ptr) |
2439 | { | |
91e745aa | 2440 | const struct iphdr *ip = ip_hdr(skb); |
bd36b0ac | 2441 | |
91e745aa SH |
2442 | mac_iocb_ptr->ip_hdr_off = skb_network_offset(skb); |
2443 | mac_iocb_ptr->ip_hdr_len = ip->ihl; | |
bd36b0ac | 2444 | |
91e745aa SH |
2445 | if (ip->protocol == IPPROTO_TCP) { |
2446 | mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_TC | | |
3e71f6dd | 2447 | OB_3032MAC_IOCB_REQ_IC; |
91e745aa SH |
2448 | } else { |
2449 | mac_iocb_ptr->flags1 |= OB_3032MAC_IOCB_REQ_UC | | |
3e71f6dd | 2450 | OB_3032MAC_IOCB_REQ_IC; |
bd36b0ac | 2451 | } |
91e745aa | 2452 | |
bd36b0ac RM |
2453 | } |
2454 | ||
2455 | /* | |
3e71f6dd RM |
2456 | * Map the buffers for this transmit. This will return |
2457 | * NETDEV_TX_BUSY or NETDEV_TX_OK based on success. | |
bd36b0ac | 2458 | */ |
3e71f6dd RM |
2459 | static int ql_send_map(struct ql3_adapter *qdev, |
2460 | struct ob_mac_iocb_req *mac_iocb_ptr, | |
2461 | struct ql_tx_buf_cb *tx_cb, | |
2462 | struct sk_buff *skb) | |
5a4faa87 | 2463 | { |
bd36b0ac RM |
2464 | struct oal *oal; |
2465 | struct oal_entry *oal_entry; | |
63f77926 | 2466 | int len = skb_headlen(skb); |
0f8ab89e BL |
2467 | dma_addr_t map; |
2468 | int err; | |
2469 | int completed_segs, i; | |
bd36b0ac RM |
2470 | int seg_cnt, seg = 0; |
2471 | int frag_cnt = (int)skb_shinfo(skb)->nr_frags; | |
5a4faa87 | 2472 | |
b6967eb9 | 2473 | seg_cnt = tx_cb->seg_count; |
3e71f6dd RM |
2474 | /* |
2475 | * Map the skb buffer first. | |
2476 | */ | |
bd36b0ac | 2477 | map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE); |
0f8ab89e BL |
2478 | |
2479 | err = pci_dma_mapping_error(map); | |
2480 | if(err) { | |
2481 | printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", | |
2482 | qdev->ndev->name, err); | |
2483 | ||
2484 | return NETDEV_TX_BUSY; | |
2485 | } | |
2486 | ||
bd36b0ac RM |
2487 | oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low; |
2488 | oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map)); | |
2489 | oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map)); | |
2490 | oal_entry->len = cpu_to_le32(len); | |
2491 | pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map); | |
2492 | pci_unmap_len_set(&tx_cb->map[seg], maplen, len); | |
2493 | seg++; | |
2494 | ||
e8f4df24 | 2495 | if (seg_cnt == 1) { |
bd36b0ac RM |
2496 | /* Terminate the last segment. */ |
2497 | oal_entry->len = | |
2498 | cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY); | |
2499 | } else { | |
bd36b0ac | 2500 | oal = tx_cb->oal; |
0f8ab89e BL |
2501 | for (completed_segs=0; completed_segs<frag_cnt; completed_segs++,seg++) { |
2502 | skb_frag_t *frag = &skb_shinfo(skb)->frags[completed_segs]; | |
bd36b0ac RM |
2503 | oal_entry++; |
2504 | if ((seg == 2 && seg_cnt > 3) || /* Check for continuation */ | |
2505 | (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */ | |
2506 | (seg == 12 && seg_cnt > 13) || /* but necessary. */ | |
2507 | (seg == 17 && seg_cnt > 18)) { | |
2508 | /* Continuation entry points to outbound address list. */ | |
2509 | map = pci_map_single(qdev->pdev, oal, | |
2510 | sizeof(struct oal), | |
2511 | PCI_DMA_TODEVICE); | |
0f8ab89e BL |
2512 | |
2513 | err = pci_dma_mapping_error(map); | |
2514 | if(err) { | |
2515 | ||
2516 | printk(KERN_ERR "%s: PCI mapping outbound address list with error: %d\n", | |
2517 | qdev->ndev->name, err); | |
2518 | goto map_error; | |
2519 | } | |
2520 | ||
bd36b0ac RM |
2521 | oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map)); |
2522 | oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map)); | |
2523 | oal_entry->len = | |
2524 | cpu_to_le32(sizeof(struct oal) | | |
2525 | OAL_CONT_ENTRY); | |
2526 | pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, | |
2527 | map); | |
2528 | pci_unmap_len_set(&tx_cb->map[seg], maplen, | |
b6967eb9 | 2529 | sizeof(struct oal)); |
bd36b0ac RM |
2530 | oal_entry = (struct oal_entry *)oal; |
2531 | oal++; | |
2532 | seg++; | |
2533 | } | |
5a4faa87 | 2534 | |
bd36b0ac RM |
2535 | map = |
2536 | pci_map_page(qdev->pdev, frag->page, | |
2537 | frag->page_offset, frag->size, | |
2538 | PCI_DMA_TODEVICE); | |
0f8ab89e BL |
2539 | |
2540 | err = pci_dma_mapping_error(map); | |
2541 | if(err) { | |
2542 | printk(KERN_ERR "%s: PCI mapping frags failed with error: %d\n", | |
2543 | qdev->ndev->name, err); | |
2544 | goto map_error; | |
2545 | } | |
2546 | ||
bd36b0ac RM |
2547 | oal_entry->dma_lo = cpu_to_le32(LS_64BITS(map)); |
2548 | oal_entry->dma_hi = cpu_to_le32(MS_64BITS(map)); | |
2549 | oal_entry->len = cpu_to_le32(frag->size); | |
2550 | pci_unmap_addr_set(&tx_cb->map[seg], mapaddr, map); | |
2551 | pci_unmap_len_set(&tx_cb->map[seg], maplen, | |
2552 | frag->size); | |
2553 | } | |
2554 | /* Terminate the last segment. */ | |
2555 | oal_entry->len = | |
2556 | cpu_to_le32(le32_to_cpu(oal_entry->len) | OAL_LAST_ENTRY); | |
2557 | } | |
0f8ab89e | 2558 | |
3e71f6dd | 2559 | return NETDEV_TX_OK; |
0f8ab89e BL |
2560 | |
2561 | map_error: | |
2562 | /* A PCI mapping failed and now we will need to back out | |
2563 | * We need to traverse through the oal's and associated pages which | |
2564 | * have been mapped and now we must unmap them to clean up properly | |
2565 | */ | |
2566 | ||
2567 | seg = 1; | |
2568 | oal_entry = (struct oal_entry *)&mac_iocb_ptr->buf_addr0_low; | |
2569 | oal = tx_cb->oal; | |
2570 | for (i=0; i<completed_segs; i++,seg++) { | |
2571 | oal_entry++; | |
2572 | ||
2573 | if((seg == 2 && seg_cnt > 3) || /* Check for continuation */ | |
2574 | (seg == 7 && seg_cnt > 8) || /* requirements. It's strange */ | |
2575 | (seg == 12 && seg_cnt > 13) || /* but necessary. */ | |
2576 | (seg == 17 && seg_cnt > 18)) { | |
2577 | pci_unmap_single(qdev->pdev, | |
2578 | pci_unmap_addr(&tx_cb->map[seg], mapaddr), | |
2579 | pci_unmap_len(&tx_cb->map[seg], maplen), | |
2580 | PCI_DMA_TODEVICE); | |
2581 | oal++; | |
2582 | seg++; | |
2583 | } | |
2584 | ||
2585 | pci_unmap_page(qdev->pdev, | |
2586 | pci_unmap_addr(&tx_cb->map[seg], mapaddr), | |
2587 | pci_unmap_len(&tx_cb->map[seg], maplen), | |
2588 | PCI_DMA_TODEVICE); | |
2589 | } | |
2590 | ||
2591 | pci_unmap_single(qdev->pdev, | |
2592 | pci_unmap_addr(&tx_cb->map[0], mapaddr), | |
2593 | pci_unmap_addr(&tx_cb->map[0], maplen), | |
2594 | PCI_DMA_TODEVICE); | |
2595 | ||
2596 | return NETDEV_TX_BUSY; | |
2597 | ||
3e71f6dd RM |
2598 | } |
2599 | ||
2600 | /* | |
2601 | * The difference between 3022 and 3032 sends: | |
2602 | * 3022 only supports a simple single segment transmission. | |
2603 | * 3032 supports checksumming and scatter/gather lists (fragments). | |
2604 | * The 3032 supports sglists by using the 3 addr/len pairs (ALP) | |
2605 | * in the IOCB plus a chain of outbound address lists (OAL) that | |
2606 | * each contain 5 ALPs. The last ALP of the IOCB (3rd) or OAL (5th) | |
2607 | * will used to point to an OAL when more ALP entries are required. | |
2608 | * The IOCB is always the top of the chain followed by one or more | |
2609 | * OALs (when necessary). | |
2610 | */ | |
2611 | static int ql3xxx_send(struct sk_buff *skb, struct net_device *ndev) | |
2612 | { | |
2613 | struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev); | |
2614 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
2615 | struct ql_tx_buf_cb *tx_cb; | |
2616 | u32 tot_len = skb->len; | |
2617 | struct ob_mac_iocb_req *mac_iocb_ptr; | |
2618 | ||
2619 | if (unlikely(atomic_read(&qdev->tx_count) < 2)) { | |
3e71f6dd RM |
2620 | return NETDEV_TX_BUSY; |
2621 | } | |
2622 | ||
2623 | tx_cb = &qdev->tx_buf[qdev->req_producer_index] ; | |
e8f4df24 BL |
2624 | if((tx_cb->seg_count = ql_get_seg_count(qdev, |
2625 | (skb_shinfo(skb)->nr_frags))) == -1) { | |
3e71f6dd RM |
2626 | printk(KERN_ERR PFX"%s: invalid segment count!\n",__func__); |
2627 | return NETDEV_TX_OK; | |
2628 | } | |
2629 | ||
2630 | mac_iocb_ptr = tx_cb->queue_entry; | |
d8a759ff | 2631 | memset((void *)mac_iocb_ptr, 0, sizeof(struct ob_mac_iocb_req)); |
3e71f6dd RM |
2632 | mac_iocb_ptr->opcode = qdev->mac_ob_opcode; |
2633 | mac_iocb_ptr->flags = OB_MAC_IOCB_REQ_X; | |
2634 | mac_iocb_ptr->flags |= qdev->mb_bit_mask; | |
2635 | mac_iocb_ptr->transaction_id = qdev->req_producer_index; | |
2636 | mac_iocb_ptr->data_len = cpu_to_le16((u16) tot_len); | |
2637 | tx_cb->skb = skb; | |
e8f4df24 BL |
2638 | if (qdev->device_id == QL3032_DEVICE_ID && |
2639 | skb->ip_summed == CHECKSUM_PARTIAL) | |
3e71f6dd RM |
2640 | ql_hw_csum_setup(skb, mac_iocb_ptr); |
2641 | ||
2642 | if(ql_send_map(qdev,mac_iocb_ptr,tx_cb,skb) != NETDEV_TX_OK) { | |
2643 | printk(KERN_ERR PFX"%s: Could not map the segments!\n",__func__); | |
2644 | return NETDEV_TX_BUSY; | |
2645 | } | |
2646 | ||
bd36b0ac | 2647 | wmb(); |
5a4faa87 RM |
2648 | qdev->req_producer_index++; |
2649 | if (qdev->req_producer_index == NUM_REQ_Q_ENTRIES) | |
2650 | qdev->req_producer_index = 0; | |
2651 | wmb(); | |
2652 | ql_write_common_reg_l(qdev, | |
ee111d11 | 2653 | &port_regs->CommonRegs.reqQProducerIndex, |
5a4faa87 RM |
2654 | qdev->req_producer_index); |
2655 | ||
2656 | ndev->trans_start = jiffies; | |
2657 | if (netif_msg_tx_queued(qdev)) | |
2658 | printk(KERN_DEBUG PFX "%s: tx queued, slot %d, len %d\n", | |
2659 | ndev->name, qdev->req_producer_index, skb->len); | |
2660 | ||
bd36b0ac | 2661 | atomic_dec(&qdev->tx_count); |
5a4faa87 RM |
2662 | return NETDEV_TX_OK; |
2663 | } | |
bd36b0ac | 2664 | |
5a4faa87 RM |
2665 | static int ql_alloc_net_req_rsp_queues(struct ql3_adapter *qdev) |
2666 | { | |
2667 | qdev->req_q_size = | |
2668 | (u32) (NUM_REQ_Q_ENTRIES * sizeof(struct ob_mac_iocb_req)); | |
2669 | ||
2670 | qdev->req_q_virt_addr = | |
2671 | pci_alloc_consistent(qdev->pdev, | |
2672 | (size_t) qdev->req_q_size, | |
2673 | &qdev->req_q_phy_addr); | |
2674 | ||
2675 | if ((qdev->req_q_virt_addr == NULL) || | |
2676 | LS_64BITS(qdev->req_q_phy_addr) & (qdev->req_q_size - 1)) { | |
2677 | printk(KERN_ERR PFX "%s: reqQ failed.\n", | |
2678 | qdev->ndev->name); | |
2679 | return -ENOMEM; | |
2680 | } | |
2681 | ||
2682 | qdev->rsp_q_size = NUM_RSP_Q_ENTRIES * sizeof(struct net_rsp_iocb); | |
2683 | ||
2684 | qdev->rsp_q_virt_addr = | |
2685 | pci_alloc_consistent(qdev->pdev, | |
2686 | (size_t) qdev->rsp_q_size, | |
2687 | &qdev->rsp_q_phy_addr); | |
2688 | ||
2689 | if ((qdev->rsp_q_virt_addr == NULL) || | |
2690 | LS_64BITS(qdev->rsp_q_phy_addr) & (qdev->rsp_q_size - 1)) { | |
2691 | printk(KERN_ERR PFX | |
2692 | "%s: rspQ allocation failed\n", | |
2693 | qdev->ndev->name); | |
2694 | pci_free_consistent(qdev->pdev, (size_t) qdev->req_q_size, | |
2695 | qdev->req_q_virt_addr, | |
2696 | qdev->req_q_phy_addr); | |
2697 | return -ENOMEM; | |
2698 | } | |
2699 | ||
2700 | set_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags); | |
2701 | ||
2702 | return 0; | |
2703 | } | |
2704 | ||
2705 | static void ql_free_net_req_rsp_queues(struct ql3_adapter *qdev) | |
2706 | { | |
2707 | if (!test_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags)) { | |
2708 | printk(KERN_INFO PFX | |
2709 | "%s: Already done.\n", qdev->ndev->name); | |
2710 | return; | |
2711 | } | |
2712 | ||
2713 | pci_free_consistent(qdev->pdev, | |
2714 | qdev->req_q_size, | |
2715 | qdev->req_q_virt_addr, qdev->req_q_phy_addr); | |
2716 | ||
2717 | qdev->req_q_virt_addr = NULL; | |
2718 | ||
2719 | pci_free_consistent(qdev->pdev, | |
2720 | qdev->rsp_q_size, | |
2721 | qdev->rsp_q_virt_addr, qdev->rsp_q_phy_addr); | |
2722 | ||
2723 | qdev->rsp_q_virt_addr = NULL; | |
2724 | ||
2725 | clear_bit(QL_ALLOC_REQ_RSP_Q_DONE,&qdev->flags); | |
2726 | } | |
2727 | ||
2728 | static int ql_alloc_buffer_queues(struct ql3_adapter *qdev) | |
2729 | { | |
2730 | /* Create Large Buffer Queue */ | |
2731 | qdev->lrg_buf_q_size = | |
1357bfcf | 2732 | qdev->num_lbufq_entries * sizeof(struct lrg_buf_q_entry); |
5a4faa87 RM |
2733 | if (qdev->lrg_buf_q_size < PAGE_SIZE) |
2734 | qdev->lrg_buf_q_alloc_size = PAGE_SIZE; | |
2735 | else | |
2736 | qdev->lrg_buf_q_alloc_size = qdev->lrg_buf_q_size * 2; | |
2737 | ||
1357bfcf RM |
2738 | qdev->lrg_buf = kmalloc(qdev->num_large_buffers * sizeof(struct ql_rcv_buf_cb),GFP_KERNEL); |
2739 | if (qdev->lrg_buf == NULL) { | |
2740 | printk(KERN_ERR PFX | |
2741 | "%s: qdev->lrg_buf alloc failed.\n", qdev->ndev->name); | |
2742 | return -ENOMEM; | |
2743 | } | |
2744 | ||
5a4faa87 RM |
2745 | qdev->lrg_buf_q_alloc_virt_addr = |
2746 | pci_alloc_consistent(qdev->pdev, | |
2747 | qdev->lrg_buf_q_alloc_size, | |
2748 | &qdev->lrg_buf_q_alloc_phy_addr); | |
2749 | ||
2750 | if (qdev->lrg_buf_q_alloc_virt_addr == NULL) { | |
2751 | printk(KERN_ERR PFX | |
2752 | "%s: lBufQ failed\n", qdev->ndev->name); | |
2753 | return -ENOMEM; | |
2754 | } | |
2755 | qdev->lrg_buf_q_virt_addr = qdev->lrg_buf_q_alloc_virt_addr; | |
2756 | qdev->lrg_buf_q_phy_addr = qdev->lrg_buf_q_alloc_phy_addr; | |
2757 | ||
2758 | /* Create Small Buffer Queue */ | |
2759 | qdev->small_buf_q_size = | |
2760 | NUM_SBUFQ_ENTRIES * sizeof(struct lrg_buf_q_entry); | |
2761 | if (qdev->small_buf_q_size < PAGE_SIZE) | |
2762 | qdev->small_buf_q_alloc_size = PAGE_SIZE; | |
2763 | else | |
2764 | qdev->small_buf_q_alloc_size = qdev->small_buf_q_size * 2; | |
2765 | ||
2766 | qdev->small_buf_q_alloc_virt_addr = | |
2767 | pci_alloc_consistent(qdev->pdev, | |
2768 | qdev->small_buf_q_alloc_size, | |
2769 | &qdev->small_buf_q_alloc_phy_addr); | |
2770 | ||
2771 | if (qdev->small_buf_q_alloc_virt_addr == NULL) { | |
2772 | printk(KERN_ERR PFX | |
2773 | "%s: Small Buffer Queue allocation failed.\n", | |
2774 | qdev->ndev->name); | |
2775 | pci_free_consistent(qdev->pdev, qdev->lrg_buf_q_alloc_size, | |
2776 | qdev->lrg_buf_q_alloc_virt_addr, | |
2777 | qdev->lrg_buf_q_alloc_phy_addr); | |
2778 | return -ENOMEM; | |
2779 | } | |
2780 | ||
2781 | qdev->small_buf_q_virt_addr = qdev->small_buf_q_alloc_virt_addr; | |
2782 | qdev->small_buf_q_phy_addr = qdev->small_buf_q_alloc_phy_addr; | |
2783 | set_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags); | |
2784 | return 0; | |
2785 | } | |
2786 | ||
2787 | static void ql_free_buffer_queues(struct ql3_adapter *qdev) | |
2788 | { | |
2789 | if (!test_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags)) { | |
2790 | printk(KERN_INFO PFX | |
2791 | "%s: Already done.\n", qdev->ndev->name); | |
2792 | return; | |
2793 | } | |
1357bfcf | 2794 | if(qdev->lrg_buf) kfree(qdev->lrg_buf); |
5a4faa87 RM |
2795 | pci_free_consistent(qdev->pdev, |
2796 | qdev->lrg_buf_q_alloc_size, | |
2797 | qdev->lrg_buf_q_alloc_virt_addr, | |
2798 | qdev->lrg_buf_q_alloc_phy_addr); | |
2799 | ||
2800 | qdev->lrg_buf_q_virt_addr = NULL; | |
2801 | ||
2802 | pci_free_consistent(qdev->pdev, | |
2803 | qdev->small_buf_q_alloc_size, | |
2804 | qdev->small_buf_q_alloc_virt_addr, | |
2805 | qdev->small_buf_q_alloc_phy_addr); | |
2806 | ||
2807 | qdev->small_buf_q_virt_addr = NULL; | |
2808 | ||
2809 | clear_bit(QL_ALLOC_BUFQS_DONE,&qdev->flags); | |
2810 | } | |
2811 | ||
2812 | static int ql_alloc_small_buffers(struct ql3_adapter *qdev) | |
2813 | { | |
2814 | int i; | |
2815 | struct bufq_addr_element *small_buf_q_entry; | |
2816 | ||
2817 | /* Currently we allocate on one of memory and use it for smallbuffers */ | |
2818 | qdev->small_buf_total_size = | |
2819 | (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES * | |
2820 | QL_SMALL_BUFFER_SIZE); | |
2821 | ||
2822 | qdev->small_buf_virt_addr = | |
2823 | pci_alloc_consistent(qdev->pdev, | |
2824 | qdev->small_buf_total_size, | |
2825 | &qdev->small_buf_phy_addr); | |
2826 | ||
2827 | if (qdev->small_buf_virt_addr == NULL) { | |
2828 | printk(KERN_ERR PFX | |
2829 | "%s: Failed to get small buffer memory.\n", | |
2830 | qdev->ndev->name); | |
2831 | return -ENOMEM; | |
2832 | } | |
2833 | ||
2834 | qdev->small_buf_phy_addr_low = LS_64BITS(qdev->small_buf_phy_addr); | |
2835 | qdev->small_buf_phy_addr_high = MS_64BITS(qdev->small_buf_phy_addr); | |
2836 | ||
2837 | small_buf_q_entry = qdev->small_buf_q_virt_addr; | |
2838 | ||
5a4faa87 RM |
2839 | /* Initialize the small buffer queue. */ |
2840 | for (i = 0; i < (QL_ADDR_ELE_PER_BUFQ_ENTRY * NUM_SBUFQ_ENTRIES); i++) { | |
2841 | small_buf_q_entry->addr_high = | |
2842 | cpu_to_le32(qdev->small_buf_phy_addr_high); | |
2843 | small_buf_q_entry->addr_low = | |
2844 | cpu_to_le32(qdev->small_buf_phy_addr_low + | |
2845 | (i * QL_SMALL_BUFFER_SIZE)); | |
2846 | small_buf_q_entry++; | |
2847 | } | |
2848 | qdev->small_buf_index = 0; | |
2849 | set_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags); | |
2850 | return 0; | |
2851 | } | |
2852 | ||
2853 | static void ql_free_small_buffers(struct ql3_adapter *qdev) | |
2854 | { | |
2855 | if (!test_bit(QL_ALLOC_SMALL_BUF_DONE,&qdev->flags)) { | |
2856 | printk(KERN_INFO PFX | |
2857 | "%s: Already done.\n", qdev->ndev->name); | |
2858 | return; | |
2859 | } | |
2860 | if (qdev->small_buf_virt_addr != NULL) { | |
2861 | pci_free_consistent(qdev->pdev, | |
2862 | qdev->small_buf_total_size, | |
2863 | qdev->small_buf_virt_addr, | |
2864 | qdev->small_buf_phy_addr); | |
2865 | ||
2866 | qdev->small_buf_virt_addr = NULL; | |
2867 | } | |
2868 | } | |
2869 | ||
2870 | static void ql_free_large_buffers(struct ql3_adapter *qdev) | |
2871 | { | |
2872 | int i = 0; | |
2873 | struct ql_rcv_buf_cb *lrg_buf_cb; | |
2874 | ||
1357bfcf | 2875 | for (i = 0; i < qdev->num_large_buffers; i++) { |
5a4faa87 RM |
2876 | lrg_buf_cb = &qdev->lrg_buf[i]; |
2877 | if (lrg_buf_cb->skb) { | |
2878 | dev_kfree_skb(lrg_buf_cb->skb); | |
2879 | pci_unmap_single(qdev->pdev, | |
2880 | pci_unmap_addr(lrg_buf_cb, mapaddr), | |
2881 | pci_unmap_len(lrg_buf_cb, maplen), | |
2882 | PCI_DMA_FROMDEVICE); | |
2883 | memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb)); | |
2884 | } else { | |
2885 | break; | |
2886 | } | |
2887 | } | |
2888 | } | |
2889 | ||
2890 | static void ql_init_large_buffers(struct ql3_adapter *qdev) | |
2891 | { | |
2892 | int i; | |
2893 | struct ql_rcv_buf_cb *lrg_buf_cb; | |
2894 | struct bufq_addr_element *buf_addr_ele = qdev->lrg_buf_q_virt_addr; | |
2895 | ||
1357bfcf | 2896 | for (i = 0; i < qdev->num_large_buffers; i++) { |
5a4faa87 RM |
2897 | lrg_buf_cb = &qdev->lrg_buf[i]; |
2898 | buf_addr_ele->addr_high = lrg_buf_cb->buf_phy_addr_high; | |
2899 | buf_addr_ele->addr_low = lrg_buf_cb->buf_phy_addr_low; | |
2900 | buf_addr_ele++; | |
2901 | } | |
2902 | qdev->lrg_buf_index = 0; | |
2903 | qdev->lrg_buf_skb_check = 0; | |
2904 | } | |
2905 | ||
2906 | static int ql_alloc_large_buffers(struct ql3_adapter *qdev) | |
2907 | { | |
2908 | int i; | |
2909 | struct ql_rcv_buf_cb *lrg_buf_cb; | |
2910 | struct sk_buff *skb; | |
0f8ab89e BL |
2911 | dma_addr_t map; |
2912 | int err; | |
5a4faa87 | 2913 | |
1357bfcf | 2914 | for (i = 0; i < qdev->num_large_buffers; i++) { |
cd238faa BL |
2915 | skb = netdev_alloc_skb(qdev->ndev, |
2916 | qdev->lrg_buffer_len); | |
5a4faa87 RM |
2917 | if (unlikely(!skb)) { |
2918 | /* Better luck next round */ | |
2919 | printk(KERN_ERR PFX | |
2920 | "%s: large buff alloc failed, " | |
2921 | "for %d bytes at index %d.\n", | |
2922 | qdev->ndev->name, | |
2923 | qdev->lrg_buffer_len * 2, i); | |
2924 | ql_free_large_buffers(qdev); | |
2925 | return -ENOMEM; | |
2926 | } else { | |
2927 | ||
2928 | lrg_buf_cb = &qdev->lrg_buf[i]; | |
2929 | memset(lrg_buf_cb, 0, sizeof(struct ql_rcv_buf_cb)); | |
2930 | lrg_buf_cb->index = i; | |
2931 | lrg_buf_cb->skb = skb; | |
2932 | /* | |
2933 | * We save some space to copy the ethhdr from first | |
2934 | * buffer | |
2935 | */ | |
2936 | skb_reserve(skb, QL_HEADER_SPACE); | |
2937 | map = pci_map_single(qdev->pdev, | |
2938 | skb->data, | |
2939 | qdev->lrg_buffer_len - | |
2940 | QL_HEADER_SPACE, | |
2941 | PCI_DMA_FROMDEVICE); | |
0f8ab89e BL |
2942 | |
2943 | err = pci_dma_mapping_error(map); | |
2944 | if(err) { | |
2945 | printk(KERN_ERR "%s: PCI mapping failed with error: %d\n", | |
2946 | qdev->ndev->name, err); | |
2947 | ql_free_large_buffers(qdev); | |
2948 | return -ENOMEM; | |
2949 | } | |
2950 | ||
5a4faa87 RM |
2951 | pci_unmap_addr_set(lrg_buf_cb, mapaddr, map); |
2952 | pci_unmap_len_set(lrg_buf_cb, maplen, | |
2953 | qdev->lrg_buffer_len - | |
2954 | QL_HEADER_SPACE); | |
2955 | lrg_buf_cb->buf_phy_addr_low = | |
2956 | cpu_to_le32(LS_64BITS(map)); | |
2957 | lrg_buf_cb->buf_phy_addr_high = | |
2958 | cpu_to_le32(MS_64BITS(map)); | |
2959 | } | |
2960 | } | |
2961 | return 0; | |
2962 | } | |
2963 | ||
bd36b0ac RM |
2964 | static void ql_free_send_free_list(struct ql3_adapter *qdev) |
2965 | { | |
2966 | struct ql_tx_buf_cb *tx_cb; | |
2967 | int i; | |
2968 | ||
2969 | tx_cb = &qdev->tx_buf[0]; | |
2970 | for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) { | |
2971 | if (tx_cb->oal) { | |
2972 | kfree(tx_cb->oal); | |
2973 | tx_cb->oal = NULL; | |
2974 | } | |
2975 | tx_cb++; | |
2976 | } | |
2977 | } | |
2978 | ||
2979 | static int ql_create_send_free_list(struct ql3_adapter *qdev) | |
5a4faa87 RM |
2980 | { |
2981 | struct ql_tx_buf_cb *tx_cb; | |
2982 | int i; | |
2983 | struct ob_mac_iocb_req *req_q_curr = | |
2984 | qdev->req_q_virt_addr; | |
2985 | ||
2986 | /* Create free list of transmit buffers */ | |
2987 | for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) { | |
bd36b0ac | 2988 | |
5a4faa87 RM |
2989 | tx_cb = &qdev->tx_buf[i]; |
2990 | tx_cb->skb = NULL; | |
2991 | tx_cb->queue_entry = req_q_curr; | |
2992 | req_q_curr++; | |
bd36b0ac RM |
2993 | tx_cb->oal = kmalloc(512, GFP_KERNEL); |
2994 | if (tx_cb->oal == NULL) | |
2995 | return -1; | |
5a4faa87 | 2996 | } |
bd36b0ac | 2997 | return 0; |
5a4faa87 RM |
2998 | } |
2999 | ||
3000 | static int ql_alloc_mem_resources(struct ql3_adapter *qdev) | |
3001 | { | |
1357bfcf RM |
3002 | if (qdev->ndev->mtu == NORMAL_MTU_SIZE) { |
3003 | qdev->num_lbufq_entries = NUM_LBUFQ_ENTRIES; | |
5a4faa87 | 3004 | qdev->lrg_buffer_len = NORMAL_MTU_SIZE; |
1357bfcf | 3005 | } |
5a4faa87 | 3006 | else if (qdev->ndev->mtu == JUMBO_MTU_SIZE) { |
1357bfcf RM |
3007 | /* |
3008 | * Bigger buffers, so less of them. | |
3009 | */ | |
3010 | qdev->num_lbufq_entries = JUMBO_NUM_LBUFQ_ENTRIES; | |
5a4faa87 RM |
3011 | qdev->lrg_buffer_len = JUMBO_MTU_SIZE; |
3012 | } else { | |
3013 | printk(KERN_ERR PFX | |
3014 | "%s: Invalid mtu size. Only 1500 and 9000 are accepted.\n", | |
3015 | qdev->ndev->name); | |
3016 | return -ENOMEM; | |
3017 | } | |
1357bfcf | 3018 | qdev->num_large_buffers = qdev->num_lbufq_entries * QL_ADDR_ELE_PER_BUFQ_ENTRY; |
5a4faa87 RM |
3019 | qdev->lrg_buffer_len += VLAN_ETH_HLEN + VLAN_ID_LEN + QL_HEADER_SPACE; |
3020 | qdev->max_frame_size = | |
3021 | (qdev->lrg_buffer_len - QL_HEADER_SPACE) + ETHERNET_CRC_SIZE; | |
3022 | ||
3023 | /* | |
3024 | * First allocate a page of shared memory and use it for shadow | |
3025 | * locations of Network Request Queue Consumer Address Register and | |
3026 | * Network Completion Queue Producer Index Register | |
3027 | */ | |
3028 | qdev->shadow_reg_virt_addr = | |
3029 | pci_alloc_consistent(qdev->pdev, | |
3030 | PAGE_SIZE, &qdev->shadow_reg_phy_addr); | |
3031 | ||
3032 | if (qdev->shadow_reg_virt_addr != NULL) { | |
3033 | qdev->preq_consumer_index = (u16 *) qdev->shadow_reg_virt_addr; | |
3034 | qdev->req_consumer_index_phy_addr_high = | |
3035 | MS_64BITS(qdev->shadow_reg_phy_addr); | |
3036 | qdev->req_consumer_index_phy_addr_low = | |
3037 | LS_64BITS(qdev->shadow_reg_phy_addr); | |
3038 | ||
3039 | qdev->prsp_producer_index = | |
3040 | (u32 *) (((u8 *) qdev->preq_consumer_index) + 8); | |
3041 | qdev->rsp_producer_index_phy_addr_high = | |
3042 | qdev->req_consumer_index_phy_addr_high; | |
3043 | qdev->rsp_producer_index_phy_addr_low = | |
3044 | qdev->req_consumer_index_phy_addr_low + 8; | |
3045 | } else { | |
3046 | printk(KERN_ERR PFX | |
3047 | "%s: shadowReg Alloc failed.\n", qdev->ndev->name); | |
3048 | return -ENOMEM; | |
3049 | } | |
3050 | ||
3051 | if (ql_alloc_net_req_rsp_queues(qdev) != 0) { | |
3052 | printk(KERN_ERR PFX | |
3053 | "%s: ql_alloc_net_req_rsp_queues failed.\n", | |
3054 | qdev->ndev->name); | |
3055 | goto err_req_rsp; | |
3056 | } | |
3057 | ||
3058 | if (ql_alloc_buffer_queues(qdev) != 0) { | |
3059 | printk(KERN_ERR PFX | |
3060 | "%s: ql_alloc_buffer_queues failed.\n", | |
3061 | qdev->ndev->name); | |
3062 | goto err_buffer_queues; | |
3063 | } | |
3064 | ||
3065 | if (ql_alloc_small_buffers(qdev) != 0) { | |
3066 | printk(KERN_ERR PFX | |
3067 | "%s: ql_alloc_small_buffers failed\n", qdev->ndev->name); | |
3068 | goto err_small_buffers; | |
3069 | } | |
3070 | ||
3071 | if (ql_alloc_large_buffers(qdev) != 0) { | |
3072 | printk(KERN_ERR PFX | |
3073 | "%s: ql_alloc_large_buffers failed\n", qdev->ndev->name); | |
3074 | goto err_small_buffers; | |
3075 | } | |
3076 | ||
3077 | /* Initialize the large buffer queue. */ | |
3078 | ql_init_large_buffers(qdev); | |
bd36b0ac RM |
3079 | if (ql_create_send_free_list(qdev)) |
3080 | goto err_free_list; | |
5a4faa87 RM |
3081 | |
3082 | qdev->rsp_current = qdev->rsp_q_virt_addr; | |
3083 | ||
3084 | return 0; | |
bd36b0ac RM |
3085 | err_free_list: |
3086 | ql_free_send_free_list(qdev); | |
5a4faa87 RM |
3087 | err_small_buffers: |
3088 | ql_free_buffer_queues(qdev); | |
3089 | err_buffer_queues: | |
3090 | ql_free_net_req_rsp_queues(qdev); | |
3091 | err_req_rsp: | |
3092 | pci_free_consistent(qdev->pdev, | |
3093 | PAGE_SIZE, | |
3094 | qdev->shadow_reg_virt_addr, | |
3095 | qdev->shadow_reg_phy_addr); | |
3096 | ||
3097 | return -ENOMEM; | |
3098 | } | |
3099 | ||
3100 | static void ql_free_mem_resources(struct ql3_adapter *qdev) | |
3101 | { | |
bd36b0ac | 3102 | ql_free_send_free_list(qdev); |
5a4faa87 RM |
3103 | ql_free_large_buffers(qdev); |
3104 | ql_free_small_buffers(qdev); | |
3105 | ql_free_buffer_queues(qdev); | |
3106 | ql_free_net_req_rsp_queues(qdev); | |
3107 | if (qdev->shadow_reg_virt_addr != NULL) { | |
3108 | pci_free_consistent(qdev->pdev, | |
3109 | PAGE_SIZE, | |
3110 | qdev->shadow_reg_virt_addr, | |
3111 | qdev->shadow_reg_phy_addr); | |
3112 | qdev->shadow_reg_virt_addr = NULL; | |
3113 | } | |
3114 | } | |
3115 | ||
3116 | static int ql_init_misc_registers(struct ql3_adapter *qdev) | |
3117 | { | |
ee111d11 AV |
3118 | struct ql3xxx_local_ram_registers __iomem *local_ram = |
3119 | (void __iomem *)qdev->mem_map_registers; | |
5a4faa87 RM |
3120 | |
3121 | if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK, | |
3122 | (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * | |
3123 | 2) << 4)) | |
3124 | return -1; | |
3125 | ||
3126 | ql_write_page2_reg(qdev, | |
3127 | &local_ram->bufletSize, qdev->nvram_data.bufletSize); | |
3128 | ||
3129 | ql_write_page2_reg(qdev, | |
3130 | &local_ram->maxBufletCount, | |
3131 | qdev->nvram_data.bufletCount); | |
3132 | ||
3133 | ql_write_page2_reg(qdev, | |
3134 | &local_ram->freeBufletThresholdLow, | |
3135 | (qdev->nvram_data.tcpWindowThreshold25 << 16) | | |
3136 | (qdev->nvram_data.tcpWindowThreshold0)); | |
3137 | ||
3138 | ql_write_page2_reg(qdev, | |
3139 | &local_ram->freeBufletThresholdHigh, | |
3140 | qdev->nvram_data.tcpWindowThreshold50); | |
3141 | ||
3142 | ql_write_page2_reg(qdev, | |
3143 | &local_ram->ipHashTableBase, | |
3144 | (qdev->nvram_data.ipHashTableBaseHi << 16) | | |
3145 | qdev->nvram_data.ipHashTableBaseLo); | |
3146 | ql_write_page2_reg(qdev, | |
3147 | &local_ram->ipHashTableCount, | |
3148 | qdev->nvram_data.ipHashTableSize); | |
3149 | ql_write_page2_reg(qdev, | |
3150 | &local_ram->tcpHashTableBase, | |
3151 | (qdev->nvram_data.tcpHashTableBaseHi << 16) | | |
3152 | qdev->nvram_data.tcpHashTableBaseLo); | |
3153 | ql_write_page2_reg(qdev, | |
3154 | &local_ram->tcpHashTableCount, | |
3155 | qdev->nvram_data.tcpHashTableSize); | |
3156 | ql_write_page2_reg(qdev, | |
3157 | &local_ram->ncbBase, | |
3158 | (qdev->nvram_data.ncbTableBaseHi << 16) | | |
3159 | qdev->nvram_data.ncbTableBaseLo); | |
3160 | ql_write_page2_reg(qdev, | |
3161 | &local_ram->maxNcbCount, | |
3162 | qdev->nvram_data.ncbTableSize); | |
3163 | ql_write_page2_reg(qdev, | |
3164 | &local_ram->drbBase, | |
3165 | (qdev->nvram_data.drbTableBaseHi << 16) | | |
3166 | qdev->nvram_data.drbTableBaseLo); | |
3167 | ql_write_page2_reg(qdev, | |
3168 | &local_ram->maxDrbCount, | |
3169 | qdev->nvram_data.drbTableSize); | |
3170 | ql_sem_unlock(qdev, QL_DDR_RAM_SEM_MASK); | |
3171 | return 0; | |
3172 | } | |
3173 | ||
3174 | static int ql_adapter_initialize(struct ql3_adapter *qdev) | |
3175 | { | |
3176 | u32 value; | |
3177 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
3178 | struct ql3xxx_host_memory_registers __iomem *hmem_regs = | |
ee111d11 | 3179 | (void __iomem *)port_regs; |
5a4faa87 RM |
3180 | u32 delay = 10; |
3181 | int status = 0; | |
3182 | ||
3183 | if(ql_mii_setup(qdev)) | |
3184 | return -1; | |
3185 | ||
3186 | /* Bring out PHY out of reset */ | |
3187 | ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg, | |
3188 | (ISP_SERIAL_PORT_IF_WE | | |
3189 | (ISP_SERIAL_PORT_IF_WE << 16))); | |
3190 | ||
3191 | qdev->port_link_state = LS_DOWN; | |
3192 | netif_carrier_off(qdev->ndev); | |
3193 | ||
3194 | /* V2 chip fix for ARS-39168. */ | |
3195 | ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg, | |
3196 | (ISP_SERIAL_PORT_IF_SDE | | |
3197 | (ISP_SERIAL_PORT_IF_SDE << 16))); | |
3198 | ||
3199 | /* Request Queue Registers */ | |
3200 | *((u32 *) (qdev->preq_consumer_index)) = 0; | |
3201 | atomic_set(&qdev->tx_count,NUM_REQ_Q_ENTRIES); | |
3202 | qdev->req_producer_index = 0; | |
3203 | ||
3204 | ql_write_page1_reg(qdev, | |
3205 | &hmem_regs->reqConsumerIndexAddrHigh, | |
3206 | qdev->req_consumer_index_phy_addr_high); | |
3207 | ql_write_page1_reg(qdev, | |
3208 | &hmem_regs->reqConsumerIndexAddrLow, | |
3209 | qdev->req_consumer_index_phy_addr_low); | |
3210 | ||
3211 | ql_write_page1_reg(qdev, | |
3212 | &hmem_regs->reqBaseAddrHigh, | |
3213 | MS_64BITS(qdev->req_q_phy_addr)); | |
3214 | ql_write_page1_reg(qdev, | |
3215 | &hmem_regs->reqBaseAddrLow, | |
3216 | LS_64BITS(qdev->req_q_phy_addr)); | |
3217 | ql_write_page1_reg(qdev, &hmem_regs->reqLength, NUM_REQ_Q_ENTRIES); | |
3218 | ||
3219 | /* Response Queue Registers */ | |
3220 | *((u16 *) (qdev->prsp_producer_index)) = 0; | |
3221 | qdev->rsp_consumer_index = 0; | |
3222 | qdev->rsp_current = qdev->rsp_q_virt_addr; | |
3223 | ||
3224 | ql_write_page1_reg(qdev, | |
3225 | &hmem_regs->rspProducerIndexAddrHigh, | |
3226 | qdev->rsp_producer_index_phy_addr_high); | |
3227 | ||
3228 | ql_write_page1_reg(qdev, | |
3229 | &hmem_regs->rspProducerIndexAddrLow, | |
3230 | qdev->rsp_producer_index_phy_addr_low); | |
3231 | ||
3232 | ql_write_page1_reg(qdev, | |
3233 | &hmem_regs->rspBaseAddrHigh, | |
3234 | MS_64BITS(qdev->rsp_q_phy_addr)); | |
3235 | ||
3236 | ql_write_page1_reg(qdev, | |
3237 | &hmem_regs->rspBaseAddrLow, | |
3238 | LS_64BITS(qdev->rsp_q_phy_addr)); | |
3239 | ||
3240 | ql_write_page1_reg(qdev, &hmem_regs->rspLength, NUM_RSP_Q_ENTRIES); | |
3241 | ||
3242 | /* Large Buffer Queue */ | |
3243 | ql_write_page1_reg(qdev, | |
3244 | &hmem_regs->rxLargeQBaseAddrHigh, | |
3245 | MS_64BITS(qdev->lrg_buf_q_phy_addr)); | |
3246 | ||
3247 | ql_write_page1_reg(qdev, | |
3248 | &hmem_regs->rxLargeQBaseAddrLow, | |
3249 | LS_64BITS(qdev->lrg_buf_q_phy_addr)); | |
3250 | ||
1357bfcf | 3251 | ql_write_page1_reg(qdev, &hmem_regs->rxLargeQLength, qdev->num_lbufq_entries); |
5a4faa87 RM |
3252 | |
3253 | ql_write_page1_reg(qdev, | |
3254 | &hmem_regs->rxLargeBufferLength, | |
3255 | qdev->lrg_buffer_len); | |
3256 | ||
3257 | /* Small Buffer Queue */ | |
3258 | ql_write_page1_reg(qdev, | |
3259 | &hmem_regs->rxSmallQBaseAddrHigh, | |
3260 | MS_64BITS(qdev->small_buf_q_phy_addr)); | |
3261 | ||
3262 | ql_write_page1_reg(qdev, | |
3263 | &hmem_regs->rxSmallQBaseAddrLow, | |
3264 | LS_64BITS(qdev->small_buf_q_phy_addr)); | |
3265 | ||
3266 | ql_write_page1_reg(qdev, &hmem_regs->rxSmallQLength, NUM_SBUFQ_ENTRIES); | |
3267 | ql_write_page1_reg(qdev, | |
3268 | &hmem_regs->rxSmallBufferLength, | |
3269 | QL_SMALL_BUFFER_SIZE); | |
3270 | ||
3271 | qdev->small_buf_q_producer_index = NUM_SBUFQ_ENTRIES - 1; | |
3272 | qdev->small_buf_release_cnt = 8; | |
1357bfcf | 3273 | qdev->lrg_buf_q_producer_index = qdev->num_lbufq_entries - 1; |
5a4faa87 RM |
3274 | qdev->lrg_buf_release_cnt = 8; |
3275 | qdev->lrg_buf_next_free = | |
3276 | (struct bufq_addr_element *)qdev->lrg_buf_q_virt_addr; | |
3277 | qdev->small_buf_index = 0; | |
3278 | qdev->lrg_buf_index = 0; | |
3279 | qdev->lrg_buf_free_count = 0; | |
3280 | qdev->lrg_buf_free_head = NULL; | |
3281 | qdev->lrg_buf_free_tail = NULL; | |
3282 | ||
3283 | ql_write_common_reg(qdev, | |
ee111d11 | 3284 | &port_regs->CommonRegs. |
5a4faa87 RM |
3285 | rxSmallQProducerIndex, |
3286 | qdev->small_buf_q_producer_index); | |
3287 | ql_write_common_reg(qdev, | |
ee111d11 | 3288 | &port_regs->CommonRegs. |
5a4faa87 RM |
3289 | rxLargeQProducerIndex, |
3290 | qdev->lrg_buf_q_producer_index); | |
3291 | ||
3292 | /* | |
3293 | * Find out if the chip has already been initialized. If it has, then | |
3294 | * we skip some of the initialization. | |
3295 | */ | |
3296 | clear_bit(QL_LINK_MASTER, &qdev->flags); | |
3297 | value = ql_read_page0_reg(qdev, &port_regs->portStatus); | |
3298 | if ((value & PORT_STATUS_IC) == 0) { | |
3299 | ||
3300 | /* Chip has not been configured yet, so let it rip. */ | |
3301 | if(ql_init_misc_registers(qdev)) { | |
3302 | status = -1; | |
3303 | goto out; | |
3304 | } | |
3305 | ||
5a4faa87 RM |
3306 | value = qdev->nvram_data.tcpMaxWindowSize; |
3307 | ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value); | |
3308 | ||
3309 | value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig; | |
3310 | ||
3311 | if(ql_sem_spinlock(qdev, QL_FLASH_SEM_MASK, | |
3312 | (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) | |
3313 | * 2) << 13)) { | |
3314 | status = -1; | |
3315 | goto out; | |
3316 | } | |
3317 | ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value); | |
3318 | ql_write_page0_reg(qdev, &port_regs->InternalChipConfig, | |
3319 | (((INTERNAL_CHIP_SD | INTERNAL_CHIP_WE) << | |
3320 | 16) | (INTERNAL_CHIP_SD | | |
3321 | INTERNAL_CHIP_WE))); | |
3322 | ql_sem_unlock(qdev, QL_FLASH_SEM_MASK); | |
3323 | } | |
3324 | ||
b3b1514c RM |
3325 | if (qdev->mac_index) |
3326 | ql_write_page0_reg(qdev, | |
3327 | &port_regs->mac1MaxFrameLengthReg, | |
3328 | qdev->max_frame_size); | |
3329 | else | |
3330 | ql_write_page0_reg(qdev, | |
3331 | &port_regs->mac0MaxFrameLengthReg, | |
3332 | qdev->max_frame_size); | |
5a4faa87 RM |
3333 | |
3334 | if(ql_sem_spinlock(qdev, QL_PHY_GIO_SEM_MASK, | |
3335 | (QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) * | |
3336 | 2) << 7)) { | |
3337 | status = -1; | |
3338 | goto out; | |
3339 | } | |
3340 | ||
3efedf2e | 3341 | PHY_Setup(qdev); |
5a4faa87 RM |
3342 | ql_init_scan_mode(qdev); |
3343 | ql_get_phy_owner(qdev); | |
3344 | ||
3345 | /* Load the MAC Configuration */ | |
3346 | ||
3347 | /* Program lower 32 bits of the MAC address */ | |
3348 | ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg, | |
3349 | (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16)); | |
3350 | ql_write_page0_reg(qdev, &port_regs->macAddrDataReg, | |
3351 | ((qdev->ndev->dev_addr[2] << 24) | |
3352 | | (qdev->ndev->dev_addr[3] << 16) | |
3353 | | (qdev->ndev->dev_addr[4] << 8) | |
3354 | | qdev->ndev->dev_addr[5])); | |
3355 | ||
3356 | /* Program top 16 bits of the MAC address */ | |
3357 | ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg, | |
3358 | ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1)); | |
3359 | ql_write_page0_reg(qdev, &port_regs->macAddrDataReg, | |
3360 | ((qdev->ndev->dev_addr[0] << 8) | |
3361 | | qdev->ndev->dev_addr[1])); | |
3362 | ||
3363 | /* Enable Primary MAC */ | |
3364 | ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg, | |
3365 | ((MAC_ADDR_INDIRECT_PTR_REG_PE << 16) | | |
3366 | MAC_ADDR_INDIRECT_PTR_REG_PE)); | |
3367 | ||
3368 | /* Clear Primary and Secondary IP addresses */ | |
3369 | ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg, | |
3370 | ((IP_ADDR_INDEX_REG_MASK << 16) | | |
3371 | (qdev->mac_index << 2))); | |
3372 | ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0); | |
3373 | ||
3374 | ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg, | |
3375 | ((IP_ADDR_INDEX_REG_MASK << 16) | | |
3376 | ((qdev->mac_index << 2) + 1))); | |
3377 | ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0); | |
3378 | ||
3379 | ql_sem_unlock(qdev, QL_PHY_GIO_SEM_MASK); | |
3380 | ||
3381 | /* Indicate Configuration Complete */ | |
3382 | ql_write_page0_reg(qdev, | |
3383 | &port_regs->portControl, | |
3384 | ((PORT_CONTROL_CC << 16) | PORT_CONTROL_CC)); | |
3385 | ||
3386 | do { | |
3387 | value = ql_read_page0_reg(qdev, &port_regs->portStatus); | |
3388 | if (value & PORT_STATUS_IC) | |
3389 | break; | |
3390 | msleep(500); | |
3391 | } while (--delay); | |
3392 | ||
3393 | if (delay == 0) { | |
3394 | printk(KERN_ERR PFX | |
3395 | "%s: Hw Initialization timeout.\n", qdev->ndev->name); | |
3396 | status = -1; | |
3397 | goto out; | |
3398 | } | |
3399 | ||
3400 | /* Enable Ethernet Function */ | |
bd36b0ac RM |
3401 | if (qdev->device_id == QL3032_DEVICE_ID) { |
3402 | value = | |
3403 | (QL3032_PORT_CONTROL_EF | QL3032_PORT_CONTROL_KIE | | |
b3b1514c RM |
3404 | QL3032_PORT_CONTROL_EIv6 | QL3032_PORT_CONTROL_EIv4 | |
3405 | QL3032_PORT_CONTROL_ET); | |
bd36b0ac RM |
3406 | ql_write_page0_reg(qdev, &port_regs->functionControl, |
3407 | ((value << 16) | value)); | |
3408 | } else { | |
3409 | value = | |
3410 | (PORT_CONTROL_EF | PORT_CONTROL_ET | PORT_CONTROL_EI | | |
3411 | PORT_CONTROL_HH); | |
3412 | ql_write_page0_reg(qdev, &port_regs->portControl, | |
3413 | ((value << 16) | value)); | |
3414 | } | |
3415 | ||
5a4faa87 RM |
3416 | |
3417 | out: | |
3418 | return status; | |
3419 | } | |
3420 | ||
3421 | /* | |
3422 | * Caller holds hw_lock. | |
3423 | */ | |
3424 | static int ql_adapter_reset(struct ql3_adapter *qdev) | |
3425 | { | |
3426 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
3427 | int status = 0; | |
3428 | u16 value; | |
3429 | int max_wait_time; | |
3430 | ||
3431 | set_bit(QL_RESET_ACTIVE, &qdev->flags); | |
3432 | clear_bit(QL_RESET_DONE, &qdev->flags); | |
3433 | ||
3434 | /* | |
3435 | * Issue soft reset to chip. | |
3436 | */ | |
3437 | printk(KERN_DEBUG PFX | |
3438 | "%s: Issue soft reset to chip.\n", | |
3439 | qdev->ndev->name); | |
3440 | ql_write_common_reg(qdev, | |
ee111d11 | 3441 | &port_regs->CommonRegs.ispControlStatus, |
5a4faa87 RM |
3442 | ((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR)); |
3443 | ||
3444 | /* Wait 3 seconds for reset to complete. */ | |
3445 | printk(KERN_DEBUG PFX | |
3446 | "%s: Wait 10 milliseconds for reset to complete.\n", | |
3447 | qdev->ndev->name); | |
3448 | ||
3449 | /* Wait until the firmware tells us the Soft Reset is done */ | |
3450 | max_wait_time = 5; | |
3451 | do { | |
3452 | value = | |
3453 | ql_read_common_reg(qdev, | |
3454 | &port_regs->CommonRegs.ispControlStatus); | |
3455 | if ((value & ISP_CONTROL_SR) == 0) | |
3456 | break; | |
3457 | ||
3458 | ssleep(1); | |
3459 | } while ((--max_wait_time)); | |
3460 | ||
3461 | /* | |
3462 | * Also, make sure that the Network Reset Interrupt bit has been | |
3463 | * cleared after the soft reset has taken place. | |
3464 | */ | |
3465 | value = | |
3466 | ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus); | |
3467 | if (value & ISP_CONTROL_RI) { | |
3468 | printk(KERN_DEBUG PFX | |
3469 | "ql_adapter_reset: clearing RI after reset.\n"); | |
3470 | ql_write_common_reg(qdev, | |
ee111d11 | 3471 | &port_regs->CommonRegs. |
5a4faa87 RM |
3472 | ispControlStatus, |
3473 | ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI)); | |
3474 | } | |
3475 | ||
3476 | if (max_wait_time == 0) { | |
3477 | /* Issue Force Soft Reset */ | |
3478 | ql_write_common_reg(qdev, | |
ee111d11 | 3479 | &port_regs->CommonRegs. |
5a4faa87 RM |
3480 | ispControlStatus, |
3481 | ((ISP_CONTROL_FSR << 16) | | |
3482 | ISP_CONTROL_FSR)); | |
3483 | /* | |
3484 | * Wait until the firmware tells us the Force Soft Reset is | |
3485 | * done | |
3486 | */ | |
3487 | max_wait_time = 5; | |
3488 | do { | |
3489 | value = | |
3490 | ql_read_common_reg(qdev, | |
3491 | &port_regs->CommonRegs. | |
3492 | ispControlStatus); | |
3493 | if ((value & ISP_CONTROL_FSR) == 0) { | |
3494 | break; | |
3495 | } | |
3496 | ssleep(1); | |
3497 | } while ((--max_wait_time)); | |
3498 | } | |
3499 | if (max_wait_time == 0) | |
3500 | status = 1; | |
3501 | ||
3502 | clear_bit(QL_RESET_ACTIVE, &qdev->flags); | |
3503 | set_bit(QL_RESET_DONE, &qdev->flags); | |
3504 | return status; | |
3505 | } | |
3506 | ||
3507 | static void ql_set_mac_info(struct ql3_adapter *qdev) | |
3508 | { | |
3509 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
3510 | u32 value, port_status; | |
3511 | u8 func_number; | |
3512 | ||
3513 | /* Get the function number */ | |
3514 | value = | |
3515 | ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus); | |
3516 | func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK); | |
3517 | port_status = ql_read_page0_reg(qdev, &port_regs->portStatus); | |
3518 | switch (value & ISP_CONTROL_FN_MASK) { | |
3519 | case ISP_CONTROL_FN0_NET: | |
3520 | qdev->mac_index = 0; | |
3521 | qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number; | |
3522 | qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number; | |
3523 | qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number; | |
3524 | qdev->mb_bit_mask = FN0_MA_BITS_MASK; | |
3525 | qdev->PHYAddr = PORT0_PHY_ADDRESS; | |
3526 | if (port_status & PORT_STATUS_SM0) | |
3527 | set_bit(QL_LINK_OPTICAL,&qdev->flags); | |
3528 | else | |
3529 | clear_bit(QL_LINK_OPTICAL,&qdev->flags); | |
3530 | break; | |
3531 | ||
3532 | case ISP_CONTROL_FN1_NET: | |
3533 | qdev->mac_index = 1; | |
3534 | qdev->mac_ob_opcode = OUTBOUND_MAC_IOCB | func_number; | |
3535 | qdev->tcp_ob_opcode = OUTBOUND_TCP_IOCB | func_number; | |
3536 | qdev->update_ob_opcode = UPDATE_NCB_IOCB | func_number; | |
3537 | qdev->mb_bit_mask = FN1_MA_BITS_MASK; | |
3538 | qdev->PHYAddr = PORT1_PHY_ADDRESS; | |
3539 | if (port_status & PORT_STATUS_SM1) | |
3540 | set_bit(QL_LINK_OPTICAL,&qdev->flags); | |
3541 | else | |
3542 | clear_bit(QL_LINK_OPTICAL,&qdev->flags); | |
3543 | break; | |
3544 | ||
3545 | case ISP_CONTROL_FN0_SCSI: | |
3546 | case ISP_CONTROL_FN1_SCSI: | |
3547 | default: | |
3548 | printk(KERN_DEBUG PFX | |
3549 | "%s: Invalid function number, ispControlStatus = 0x%x\n", | |
3550 | qdev->ndev->name,value); | |
3551 | break; | |
3552 | } | |
3553 | qdev->numPorts = qdev->nvram_data.numPorts; | |
3554 | } | |
3555 | ||
3556 | static void ql_display_dev_info(struct net_device *ndev) | |
3557 | { | |
3558 | struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev); | |
3559 | struct pci_dev *pdev = qdev->pdev; | |
3560 | ||
3561 | printk(KERN_INFO PFX | |
bd36b0ac RM |
3562 | "\n%s Adapter %d RevisionID %d found %s on PCI slot %d.\n", |
3563 | DRV_NAME, qdev->index, qdev->chip_rev_id, | |
3564 | (qdev->device_id == QL3032_DEVICE_ID) ? "QLA3032" : "QLA3022", | |
3565 | qdev->pci_slot); | |
5a4faa87 RM |
3566 | printk(KERN_INFO PFX |
3567 | "%s Interface.\n", | |
3568 | test_bit(QL_LINK_OPTICAL,&qdev->flags) ? "OPTICAL" : "COPPER"); | |
3569 | ||
3570 | /* | |
3571 | * Print PCI bus width/type. | |
3572 | */ | |
3573 | printk(KERN_INFO PFX | |
3574 | "Bus interface is %s %s.\n", | |
3575 | ((qdev->pci_width == 64) ? "64-bit" : "32-bit"), | |
3576 | ((qdev->pci_x) ? "PCI-X" : "PCI")); | |
3577 | ||
3578 | printk(KERN_INFO PFX | |
3579 | "mem IO base address adjusted = 0x%p\n", | |
3580 | qdev->mem_map_registers); | |
3581 | printk(KERN_INFO PFX "Interrupt number = %d\n", pdev->irq); | |
3582 | ||
3583 | if (netif_msg_probe(qdev)) | |
3584 | printk(KERN_INFO PFX | |
3585 | "%s: MAC address %02x:%02x:%02x:%02x:%02x:%02x\n", | |
3586 | ndev->name, ndev->dev_addr[0], ndev->dev_addr[1], | |
3587 | ndev->dev_addr[2], ndev->dev_addr[3], ndev->dev_addr[4], | |
3588 | ndev->dev_addr[5]); | |
3589 | } | |
3590 | ||
3591 | static int ql_adapter_down(struct ql3_adapter *qdev, int do_reset) | |
3592 | { | |
3593 | struct net_device *ndev = qdev->ndev; | |
3594 | int retval = 0; | |
3595 | ||
3596 | netif_stop_queue(ndev); | |
3597 | netif_carrier_off(ndev); | |
3598 | ||
3599 | clear_bit(QL_ADAPTER_UP,&qdev->flags); | |
3600 | clear_bit(QL_LINK_MASTER,&qdev->flags); | |
3601 | ||
3602 | ql_disable_interrupts(qdev); | |
3603 | ||
3604 | free_irq(qdev->pdev->irq, ndev); | |
3605 | ||
3606 | if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) { | |
3607 | printk(KERN_INFO PFX | |
3608 | "%s: calling pci_disable_msi().\n", qdev->ndev->name); | |
3609 | clear_bit(QL_MSI_ENABLED,&qdev->flags); | |
3610 | pci_disable_msi(qdev->pdev); | |
3611 | } | |
3612 | ||
3613 | del_timer_sync(&qdev->adapter_timer); | |
3614 | ||
bea3348e | 3615 | napi_disable(&qdev->napi); |
5a4faa87 RM |
3616 | |
3617 | if (do_reset) { | |
3618 | int soft_reset; | |
3619 | unsigned long hw_flags; | |
3620 | ||
3621 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
3622 | if (ql_wait_for_drvr_lock(qdev)) { | |
3623 | if ((soft_reset = ql_adapter_reset(qdev))) { | |
3624 | printk(KERN_ERR PFX | |
3625 | "%s: ql_adapter_reset(%d) FAILED!\n", | |
3626 | ndev->name, qdev->index); | |
3627 | } | |
3628 | printk(KERN_ERR PFX | |
3629 | "%s: Releaseing driver lock via chip reset.\n",ndev->name); | |
3630 | } else { | |
3631 | printk(KERN_ERR PFX | |
3632 | "%s: Could not acquire driver lock to do " | |
3633 | "reset!\n", ndev->name); | |
3634 | retval = -1; | |
3635 | } | |
3636 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
3637 | } | |
3638 | ql_free_mem_resources(qdev); | |
3639 | return retval; | |
3640 | } | |
3641 | ||
3642 | static int ql_adapter_up(struct ql3_adapter *qdev) | |
3643 | { | |
3644 | struct net_device *ndev = qdev->ndev; | |
3645 | int err; | |
38515e90 | 3646 | unsigned long irq_flags = IRQF_SAMPLE_RANDOM | IRQF_SHARED; |
5a4faa87 RM |
3647 | unsigned long hw_flags; |
3648 | ||
3649 | if (ql_alloc_mem_resources(qdev)) { | |
3650 | printk(KERN_ERR PFX | |
3651 | "%s Unable to allocate buffers.\n", ndev->name); | |
3652 | return -ENOMEM; | |
3653 | } | |
3654 | ||
3655 | if (qdev->msi) { | |
3656 | if (pci_enable_msi(qdev->pdev)) { | |
3657 | printk(KERN_ERR PFX | |
3658 | "%s: User requested MSI, but MSI failed to " | |
3659 | "initialize. Continuing without MSI.\n", | |
3660 | qdev->ndev->name); | |
3661 | qdev->msi = 0; | |
3662 | } else { | |
3663 | printk(KERN_INFO PFX "%s: MSI Enabled...\n", qdev->ndev->name); | |
3664 | set_bit(QL_MSI_ENABLED,&qdev->flags); | |
38515e90 | 3665 | irq_flags &= ~IRQF_SHARED; |
5a4faa87 RM |
3666 | } |
3667 | } | |
3668 | ||
3669 | if ((err = request_irq(qdev->pdev->irq, | |
3670 | ql3xxx_isr, | |
3671 | irq_flags, ndev->name, ndev))) { | |
3672 | printk(KERN_ERR PFX | |
3673 | "%s: Failed to reserve interrupt %d already in use.\n", | |
3674 | ndev->name, qdev->pdev->irq); | |
3675 | goto err_irq; | |
3676 | } | |
3677 | ||
3678 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
3679 | ||
3680 | if ((err = ql_wait_for_drvr_lock(qdev))) { | |
3681 | if ((err = ql_adapter_initialize(qdev))) { | |
3682 | printk(KERN_ERR PFX | |
3683 | "%s: Unable to initialize adapter.\n", | |
3684 | ndev->name); | |
3685 | goto err_init; | |
3686 | } | |
3687 | printk(KERN_ERR PFX | |
3688 | "%s: Releaseing driver lock.\n",ndev->name); | |
3689 | ql_sem_unlock(qdev, QL_DRVR_SEM_MASK); | |
3690 | } else { | |
3691 | printk(KERN_ERR PFX | |
3692 | "%s: Could not aquire driver lock.\n", | |
3693 | ndev->name); | |
3694 | goto err_lock; | |
3695 | } | |
3696 | ||
3697 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
3698 | ||
3699 | set_bit(QL_ADAPTER_UP,&qdev->flags); | |
3700 | ||
3701 | mod_timer(&qdev->adapter_timer, jiffies + HZ * 1); | |
3702 | ||
bea3348e | 3703 | napi_enable(&qdev->napi); |
5a4faa87 RM |
3704 | ql_enable_interrupts(qdev); |
3705 | return 0; | |
3706 | ||
3707 | err_init: | |
3708 | ql_sem_unlock(qdev, QL_DRVR_SEM_MASK); | |
3709 | err_lock: | |
04f10773 | 3710 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); |
5a4faa87 RM |
3711 | free_irq(qdev->pdev->irq, ndev); |
3712 | err_irq: | |
3713 | if (qdev->msi && test_bit(QL_MSI_ENABLED,&qdev->flags)) { | |
3714 | printk(KERN_INFO PFX | |
3715 | "%s: calling pci_disable_msi().\n", | |
3716 | qdev->ndev->name); | |
3717 | clear_bit(QL_MSI_ENABLED,&qdev->flags); | |
3718 | pci_disable_msi(qdev->pdev); | |
3719 | } | |
3720 | return err; | |
3721 | } | |
3722 | ||
3723 | static int ql_cycle_adapter(struct ql3_adapter *qdev, int reset) | |
3724 | { | |
3725 | if( ql_adapter_down(qdev,reset) || ql_adapter_up(qdev)) { | |
3726 | printk(KERN_ERR PFX | |
3727 | "%s: Driver up/down cycle failed, " | |
3728 | "closing device\n",qdev->ndev->name); | |
3729 | dev_close(qdev->ndev); | |
3730 | return -1; | |
3731 | } | |
3732 | return 0; | |
3733 | } | |
3734 | ||
3735 | static int ql3xxx_close(struct net_device *ndev) | |
3736 | { | |
3737 | struct ql3_adapter *qdev = netdev_priv(ndev); | |
3738 | ||
3739 | /* | |
3740 | * Wait for device to recover from a reset. | |
3741 | * (Rarely happens, but possible.) | |
3742 | */ | |
3743 | while (!test_bit(QL_ADAPTER_UP,&qdev->flags)) | |
3744 | msleep(50); | |
3745 | ||
3746 | ql_adapter_down(qdev,QL_DO_RESET); | |
3747 | return 0; | |
3748 | } | |
3749 | ||
3750 | static int ql3xxx_open(struct net_device *ndev) | |
3751 | { | |
3752 | struct ql3_adapter *qdev = netdev_priv(ndev); | |
3753 | return (ql_adapter_up(qdev)); | |
3754 | } | |
3755 | ||
5a4faa87 RM |
3756 | static void ql3xxx_set_multicast_list(struct net_device *ndev) |
3757 | { | |
3758 | /* | |
3759 | * We are manually parsing the list in the net_device structure. | |
3760 | */ | |
3761 | return; | |
3762 | } | |
3763 | ||
3764 | static int ql3xxx_set_mac_address(struct net_device *ndev, void *p) | |
3765 | { | |
3766 | struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev); | |
3767 | struct ql3xxx_port_registers __iomem *port_regs = | |
3768 | qdev->mem_map_registers; | |
3769 | struct sockaddr *addr = p; | |
3770 | unsigned long hw_flags; | |
3771 | ||
3772 | if (netif_running(ndev)) | |
3773 | return -EBUSY; | |
3774 | ||
3775 | if (!is_valid_ether_addr(addr->sa_data)) | |
3776 | return -EADDRNOTAVAIL; | |
3777 | ||
3778 | memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len); | |
3779 | ||
3780 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
3781 | /* Program lower 32 bits of the MAC address */ | |
3782 | ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg, | |
3783 | (MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16)); | |
3784 | ql_write_page0_reg(qdev, &port_regs->macAddrDataReg, | |
3785 | ((ndev->dev_addr[2] << 24) | (ndev-> | |
3786 | dev_addr[3] << 16) | | |
3787 | (ndev->dev_addr[4] << 8) | ndev->dev_addr[5])); | |
3788 | ||
3789 | /* Program top 16 bits of the MAC address */ | |
3790 | ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg, | |
3791 | ((MAC_ADDR_INDIRECT_PTR_REG_RP_MASK << 16) | 1)); | |
3792 | ql_write_page0_reg(qdev, &port_regs->macAddrDataReg, | |
3793 | ((ndev->dev_addr[0] << 8) | ndev->dev_addr[1])); | |
3794 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
3795 | ||
3796 | return 0; | |
3797 | } | |
3798 | ||
3799 | static void ql3xxx_tx_timeout(struct net_device *ndev) | |
3800 | { | |
3801 | struct ql3_adapter *qdev = (struct ql3_adapter *)netdev_priv(ndev); | |
3802 | ||
3803 | printk(KERN_ERR PFX "%s: Resetting...\n", ndev->name); | |
3804 | /* | |
3805 | * Stop the queues, we've got a problem. | |
3806 | */ | |
3807 | netif_stop_queue(ndev); | |
3808 | ||
3809 | /* | |
3810 | * Wake up the worker to process this event. | |
3811 | */ | |
c4028958 | 3812 | queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0); |
5a4faa87 RM |
3813 | } |
3814 | ||
c4028958 | 3815 | static void ql_reset_work(struct work_struct *work) |
5a4faa87 | 3816 | { |
c4028958 DH |
3817 | struct ql3_adapter *qdev = |
3818 | container_of(work, struct ql3_adapter, reset_work.work); | |
5a4faa87 RM |
3819 | struct net_device *ndev = qdev->ndev; |
3820 | u32 value; | |
3821 | struct ql_tx_buf_cb *tx_cb; | |
3822 | int max_wait_time, i; | |
3823 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
3824 | unsigned long hw_flags; | |
3825 | ||
3826 | if (test_bit((QL_RESET_PER_SCSI | QL_RESET_START),&qdev->flags)) { | |
3827 | clear_bit(QL_LINK_MASTER,&qdev->flags); | |
3828 | ||
3829 | /* | |
3830 | * Loop through the active list and return the skb. | |
3831 | */ | |
3832 | for (i = 0; i < NUM_REQ_Q_ENTRIES; i++) { | |
bd36b0ac | 3833 | int j; |
5a4faa87 RM |
3834 | tx_cb = &qdev->tx_buf[i]; |
3835 | if (tx_cb->skb) { | |
5a4faa87 RM |
3836 | printk(KERN_DEBUG PFX |
3837 | "%s: Freeing lost SKB.\n", | |
3838 | qdev->ndev->name); | |
3839 | pci_unmap_single(qdev->pdev, | |
bd36b0ac RM |
3840 | pci_unmap_addr(&tx_cb->map[0], mapaddr), |
3841 | pci_unmap_len(&tx_cb->map[0], maplen), | |
3842 | PCI_DMA_TODEVICE); | |
3843 | for(j=1;j<tx_cb->seg_count;j++) { | |
3844 | pci_unmap_page(qdev->pdev, | |
3845 | pci_unmap_addr(&tx_cb->map[j],mapaddr), | |
3846 | pci_unmap_len(&tx_cb->map[j],maplen), | |
3847 | PCI_DMA_TODEVICE); | |
3848 | } | |
5a4faa87 RM |
3849 | dev_kfree_skb(tx_cb->skb); |
3850 | tx_cb->skb = NULL; | |
3851 | } | |
3852 | } | |
3853 | ||
3854 | printk(KERN_ERR PFX | |
3855 | "%s: Clearing NRI after reset.\n", qdev->ndev->name); | |
3856 | spin_lock_irqsave(&qdev->hw_lock, hw_flags); | |
3857 | ql_write_common_reg(qdev, | |
3858 | &port_regs->CommonRegs. | |
3859 | ispControlStatus, | |
3860 | ((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI)); | |
3861 | /* | |
3862 | * Wait the for Soft Reset to Complete. | |
3863 | */ | |
3864 | max_wait_time = 10; | |
3865 | do { | |
3866 | value = ql_read_common_reg(qdev, | |
3867 | &port_regs->CommonRegs. | |
3868 | ||
3869 | ispControlStatus); | |
3870 | if ((value & ISP_CONTROL_SR) == 0) { | |
3871 | printk(KERN_DEBUG PFX | |
3872 | "%s: reset completed.\n", | |
3873 | qdev->ndev->name); | |
3874 | break; | |
3875 | } | |
3876 | ||
3877 | if (value & ISP_CONTROL_RI) { | |
3878 | printk(KERN_DEBUG PFX | |
3879 | "%s: clearing NRI after reset.\n", | |
3880 | qdev->ndev->name); | |
3881 | ql_write_common_reg(qdev, | |
ee111d11 | 3882 | &port_regs-> |
5a4faa87 RM |
3883 | CommonRegs. |
3884 | ispControlStatus, | |
3885 | ((ISP_CONTROL_RI << | |
3886 | 16) | ISP_CONTROL_RI)); | |
3887 | } | |
3888 | ||
3889 | ssleep(1); | |
3890 | } while (--max_wait_time); | |
3891 | spin_unlock_irqrestore(&qdev->hw_lock, hw_flags); | |
3892 | ||
3893 | if (value & ISP_CONTROL_SR) { | |
3894 | ||
3895 | /* | |
3896 | * Set the reset flags and clear the board again. | |
3897 | * Nothing else to do... | |
3898 | */ | |
3899 | printk(KERN_ERR PFX | |
3900 | "%s: Timed out waiting for reset to " | |
3901 | "complete.\n", ndev->name); | |
3902 | printk(KERN_ERR PFX | |
3903 | "%s: Do a reset.\n", ndev->name); | |
3904 | clear_bit(QL_RESET_PER_SCSI,&qdev->flags); | |
3905 | clear_bit(QL_RESET_START,&qdev->flags); | |
3906 | ql_cycle_adapter(qdev,QL_DO_RESET); | |
3907 | return; | |
3908 | } | |
3909 | ||
3910 | clear_bit(QL_RESET_ACTIVE,&qdev->flags); | |
3911 | clear_bit(QL_RESET_PER_SCSI,&qdev->flags); | |
3912 | clear_bit(QL_RESET_START,&qdev->flags); | |
3913 | ql_cycle_adapter(qdev,QL_NO_RESET); | |
3914 | } | |
3915 | } | |
3916 | ||
c4028958 | 3917 | static void ql_tx_timeout_work(struct work_struct *work) |
5a4faa87 | 3918 | { |
c4028958 DH |
3919 | struct ql3_adapter *qdev = |
3920 | container_of(work, struct ql3_adapter, tx_timeout_work.work); | |
3921 | ||
3922 | ql_cycle_adapter(qdev, QL_DO_RESET); | |
5a4faa87 RM |
3923 | } |
3924 | ||
3925 | static void ql_get_board_info(struct ql3_adapter *qdev) | |
3926 | { | |
3927 | struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers; | |
3928 | u32 value; | |
3929 | ||
3930 | value = ql_read_page0_reg_l(qdev, &port_regs->portStatus); | |
3931 | ||
3932 | qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12); | |
3933 | if (value & PORT_STATUS_64) | |
3934 | qdev->pci_width = 64; | |
3935 | else | |
3936 | qdev->pci_width = 32; | |
3937 | if (value & PORT_STATUS_X) | |
3938 | qdev->pci_x = 1; | |
3939 | else | |
3940 | qdev->pci_x = 0; | |
3941 | qdev->pci_slot = (u8) PCI_SLOT(qdev->pdev->devfn); | |
3942 | } | |
3943 | ||
3944 | static void ql3xxx_timer(unsigned long ptr) | |
3945 | { | |
3946 | struct ql3_adapter *qdev = (struct ql3_adapter *)ptr; | |
3947 | ||
3948 | if (test_bit(QL_RESET_ACTIVE,&qdev->flags)) { | |
3949 | printk(KERN_DEBUG PFX | |
3950 | "%s: Reset in progress.\n", | |
3951 | qdev->ndev->name); | |
3952 | goto end; | |
3953 | } | |
3954 | ||
3955 | ql_link_state_machine(qdev); | |
3956 | ||
3957 | /* Restart timer on 2 second interval. */ | |
3958 | end: | |
3959 | mod_timer(&qdev->adapter_timer, jiffies + HZ * 1); | |
3960 | } | |
3961 | ||
3962 | static int __devinit ql3xxx_probe(struct pci_dev *pdev, | |
3963 | const struct pci_device_id *pci_entry) | |
3964 | { | |
3965 | struct net_device *ndev = NULL; | |
3966 | struct ql3_adapter *qdev = NULL; | |
3967 | static int cards_found = 0; | |
3968 | int pci_using_dac, err; | |
3969 | ||
3970 | err = pci_enable_device(pdev); | |
3971 | if (err) { | |
3972 | printk(KERN_ERR PFX "%s cannot enable PCI device\n", | |
3973 | pci_name(pdev)); | |
3974 | goto err_out; | |
3975 | } | |
3976 | ||
3977 | err = pci_request_regions(pdev, DRV_NAME); | |
3978 | if (err) { | |
3979 | printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", | |
3980 | pci_name(pdev)); | |
3981 | goto err_out_disable_pdev; | |
3982 | } | |
3983 | ||
3984 | pci_set_master(pdev); | |
3985 | ||
3986 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { | |
3987 | pci_using_dac = 1; | |
3988 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
3989 | } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) { | |
3990 | pci_using_dac = 0; | |
3991 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
3992 | } | |
3993 | ||
3994 | if (err) { | |
3995 | printk(KERN_ERR PFX "%s no usable DMA configuration\n", | |
3996 | pci_name(pdev)); | |
3997 | goto err_out_free_regions; | |
3998 | } | |
3999 | ||
4000 | ndev = alloc_etherdev(sizeof(struct ql3_adapter)); | |
546faf07 BL |
4001 | if (!ndev) { |
4002 | printk(KERN_ERR PFX "%s could not alloc etherdev\n", | |
4003 | pci_name(pdev)); | |
4004 | err = -ENOMEM; | |
5a4faa87 | 4005 | goto err_out_free_regions; |
546faf07 | 4006 | } |
5a4faa87 | 4007 | |
5a4faa87 RM |
4008 | SET_NETDEV_DEV(ndev, &pdev->dev); |
4009 | ||
5a4faa87 RM |
4010 | pci_set_drvdata(pdev, ndev); |
4011 | ||
4012 | qdev = netdev_priv(ndev); | |
4013 | qdev->index = cards_found; | |
4014 | qdev->ndev = ndev; | |
4015 | qdev->pdev = pdev; | |
bd36b0ac | 4016 | qdev->device_id = pci_entry->device; |
5a4faa87 RM |
4017 | qdev->port_link_state = LS_DOWN; |
4018 | if (msi) | |
4019 | qdev->msi = 1; | |
4020 | ||
4021 | qdev->msg_enable = netif_msg_init(debug, default_msg); | |
4022 | ||
bd36b0ac RM |
4023 | if (pci_using_dac) |
4024 | ndev->features |= NETIF_F_HIGHDMA; | |
4025 | if (qdev->device_id == QL3032_DEVICE_ID) | |
e68a8c10 | 4026 | ndev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
bd36b0ac | 4027 | |
5a4faa87 RM |
4028 | qdev->mem_map_registers = |
4029 | ioremap_nocache(pci_resource_start(pdev, 1), | |
4030 | pci_resource_len(qdev->pdev, 1)); | |
4031 | if (!qdev->mem_map_registers) { | |
4032 | printk(KERN_ERR PFX "%s: cannot map device registers\n", | |
4033 | pci_name(pdev)); | |
546faf07 | 4034 | err = -EIO; |
5a4faa87 RM |
4035 | goto err_out_free_ndev; |
4036 | } | |
4037 | ||
4038 | spin_lock_init(&qdev->adapter_lock); | |
4039 | spin_lock_init(&qdev->hw_lock); | |
4040 | ||
4041 | /* Set driver entry points */ | |
4042 | ndev->open = ql3xxx_open; | |
4043 | ndev->hard_start_xmit = ql3xxx_send; | |
4044 | ndev->stop = ql3xxx_close; | |
5a4faa87 RM |
4045 | ndev->set_multicast_list = ql3xxx_set_multicast_list; |
4046 | SET_ETHTOOL_OPS(ndev, &ql3xxx_ethtool_ops); | |
4047 | ndev->set_mac_address = ql3xxx_set_mac_address; | |
4048 | ndev->tx_timeout = ql3xxx_tx_timeout; | |
4049 | ndev->watchdog_timeo = 5 * HZ; | |
4050 | ||
bea3348e | 4051 | netif_napi_add(ndev, &qdev->napi, ql_poll, 64); |
5a4faa87 RM |
4052 | |
4053 | ndev->irq = pdev->irq; | |
4054 | ||
4055 | /* make sure the EEPROM is good */ | |
4056 | if (ql_get_nvram_params(qdev)) { | |
4057 | printk(KERN_ALERT PFX | |
4058 | "ql3xxx_probe: Adapter #%d, Invalid NVRAM parameters.\n", | |
4059 | qdev->index); | |
546faf07 | 4060 | err = -EIO; |
5a4faa87 RM |
4061 | goto err_out_iounmap; |
4062 | } | |
4063 | ||
4064 | ql_set_mac_info(qdev); | |
4065 | ||
4066 | /* Validate and set parameters */ | |
4067 | if (qdev->mac_index) { | |
cb8bac12 | 4068 | ndev->mtu = qdev->nvram_data.macCfg_port1.etherMtu_mac ; |
5a4faa87 RM |
4069 | memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn2.macAddress, |
4070 | ETH_ALEN); | |
4071 | } else { | |
cb8bac12 | 4072 | ndev->mtu = qdev->nvram_data.macCfg_port0.etherMtu_mac ; |
5a4faa87 RM |
4073 | memcpy(ndev->dev_addr, &qdev->nvram_data.funcCfg_fn0.macAddress, |
4074 | ETH_ALEN); | |
4075 | } | |
4076 | memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len); | |
4077 | ||
4078 | ndev->tx_queue_len = NUM_REQ_Q_ENTRIES; | |
4079 | ||
4080 | /* Turn off support for multicasting */ | |
4081 | ndev->flags &= ~IFF_MULTICAST; | |
4082 | ||
4083 | /* Record PCI bus information. */ | |
4084 | ql_get_board_info(qdev); | |
4085 | ||
4086 | /* | |
4087 | * Set the Maximum Memory Read Byte Count value. We do this to handle | |
4088 | * jumbo frames. | |
4089 | */ | |
4090 | if (qdev->pci_x) { | |
4091 | pci_write_config_word(pdev, (int)0x4e, (u16) 0x0036); | |
4092 | } | |
4093 | ||
4094 | err = register_netdev(ndev); | |
4095 | if (err) { | |
4096 | printk(KERN_ERR PFX "%s: cannot register net device\n", | |
4097 | pci_name(pdev)); | |
4098 | goto err_out_iounmap; | |
4099 | } | |
4100 | ||
4101 | /* we're going to reset, so assume we have no link for now */ | |
4102 | ||
4103 | netif_carrier_off(ndev); | |
4104 | netif_stop_queue(ndev); | |
4105 | ||
4106 | qdev->workqueue = create_singlethread_workqueue(ndev->name); | |
c4028958 DH |
4107 | INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work); |
4108 | INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work); | |
5a4faa87 RM |
4109 | |
4110 | init_timer(&qdev->adapter_timer); | |
4111 | qdev->adapter_timer.function = ql3xxx_timer; | |
4112 | qdev->adapter_timer.expires = jiffies + HZ * 2; /* two second delay */ | |
4113 | qdev->adapter_timer.data = (unsigned long)qdev; | |
4114 | ||
4115 | if(!cards_found) { | |
4116 | printk(KERN_ALERT PFX "%s\n", DRV_STRING); | |
4117 | printk(KERN_ALERT PFX "Driver name: %s, Version: %s.\n", | |
4118 | DRV_NAME, DRV_VERSION); | |
4119 | } | |
4120 | ql_display_dev_info(ndev); | |
4121 | ||
4122 | cards_found++; | |
4123 | return 0; | |
4124 | ||
4125 | err_out_iounmap: | |
4126 | iounmap(qdev->mem_map_registers); | |
4127 | err_out_free_ndev: | |
4128 | free_netdev(ndev); | |
4129 | err_out_free_regions: | |
4130 | pci_release_regions(pdev); | |
4131 | err_out_disable_pdev: | |
4132 | pci_disable_device(pdev); | |
4133 | pci_set_drvdata(pdev, NULL); | |
4134 | err_out: | |
4135 | return err; | |
4136 | } | |
4137 | ||
4138 | static void __devexit ql3xxx_remove(struct pci_dev *pdev) | |
4139 | { | |
4140 | struct net_device *ndev = pci_get_drvdata(pdev); | |
4141 | struct ql3_adapter *qdev = netdev_priv(ndev); | |
4142 | ||
4143 | unregister_netdev(ndev); | |
4144 | qdev = netdev_priv(ndev); | |
4145 | ||
4146 | ql_disable_interrupts(qdev); | |
4147 | ||
4148 | if (qdev->workqueue) { | |
4149 | cancel_delayed_work(&qdev->reset_work); | |
4150 | cancel_delayed_work(&qdev->tx_timeout_work); | |
4151 | destroy_workqueue(qdev->workqueue); | |
4152 | qdev->workqueue = NULL; | |
4153 | } | |
4154 | ||
855fc73b | 4155 | iounmap(qdev->mem_map_registers); |
5a4faa87 RM |
4156 | pci_release_regions(pdev); |
4157 | pci_set_drvdata(pdev, NULL); | |
4158 | free_netdev(ndev); | |
4159 | } | |
4160 | ||
4161 | static struct pci_driver ql3xxx_driver = { | |
4162 | ||
4163 | .name = DRV_NAME, | |
4164 | .id_table = ql3xxx_pci_tbl, | |
4165 | .probe = ql3xxx_probe, | |
4166 | .remove = __devexit_p(ql3xxx_remove), | |
4167 | }; | |
4168 | ||
4169 | static int __init ql3xxx_init_module(void) | |
4170 | { | |
4171 | return pci_register_driver(&ql3xxx_driver); | |
4172 | } | |
4173 | ||
4174 | static void __exit ql3xxx_exit(void) | |
4175 | { | |
4176 | pci_unregister_driver(&ql3xxx_driver); | |
4177 | } | |
4178 | ||
4179 | module_init(ql3xxx_init_module); | |
4180 | module_exit(ql3xxx_exit); |