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af19b491 AKS |
1 | /* |
2 | * Copyright (C) 2009 - QLogic Corporation. | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License | |
7 | * as published by the Free Software Foundation; either version 2 | |
8 | * of the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, | |
18 | * MA 02111-1307, USA. | |
19 | * | |
20 | * The full GNU General Public License is included in this distribution | |
21 | * in the file called "COPYING". | |
22 | * | |
23 | */ | |
24 | ||
25 | #ifndef _QLCNIC_H_ | |
26 | #define _QLCNIC_H_ | |
27 | ||
28 | #include <linux/module.h> | |
29 | #include <linux/kernel.h> | |
30 | #include <linux/types.h> | |
31 | #include <linux/ioport.h> | |
32 | #include <linux/pci.h> | |
33 | #include <linux/netdevice.h> | |
34 | #include <linux/etherdevice.h> | |
35 | #include <linux/ip.h> | |
36 | #include <linux/in.h> | |
37 | #include <linux/tcp.h> | |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/firmware.h> | |
40 | ||
41 | #include <linux/ethtool.h> | |
42 | #include <linux/mii.h> | |
43 | #include <linux/timer.h> | |
44 | ||
45 | #include <linux/vmalloc.h> | |
46 | ||
47 | #include <linux/io.h> | |
48 | #include <asm/byteorder.h> | |
49 | ||
50 | #include "qlcnic_hdr.h" | |
51 | ||
52 | #define _QLCNIC_LINUX_MAJOR 5 | |
53 | #define _QLCNIC_LINUX_MINOR 0 | |
927b1375 AKS |
54 | #define _QLCNIC_LINUX_SUBVERSION 2 |
55 | #define QLCNIC_LINUX_VERSIONID "5.0.2" | |
96f8118c | 56 | #define QLCNIC_DRV_IDC_VER 0x01 |
af19b491 AKS |
57 | |
58 | #define QLCNIC_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) | |
59 | #define _major(v) (((v) >> 24) & 0xff) | |
60 | #define _minor(v) (((v) >> 16) & 0xff) | |
61 | #define _build(v) ((v) & 0xffff) | |
62 | ||
63 | /* version in image has weird encoding: | |
64 | * 7:0 - major | |
65 | * 15:8 - minor | |
66 | * 31:16 - build (little endian) | |
67 | */ | |
68 | #define QLCNIC_DECODE_VERSION(v) \ | |
69 | QLCNIC_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) | |
70 | ||
71 | #define QLCNIC_NUM_FLASH_SECTORS (64) | |
72 | #define QLCNIC_FLASH_SECTOR_SIZE (64 * 1024) | |
73 | #define QLCNIC_FLASH_TOTAL_SIZE (QLCNIC_NUM_FLASH_SECTORS \ | |
74 | * QLCNIC_FLASH_SECTOR_SIZE) | |
75 | ||
76 | #define RCV_DESC_RINGSIZE(rds_ring) \ | |
77 | (sizeof(struct rcv_desc) * (rds_ring)->num_desc) | |
78 | #define RCV_BUFF_RINGSIZE(rds_ring) \ | |
79 | (sizeof(struct qlcnic_rx_buffer) * rds_ring->num_desc) | |
80 | #define STATUS_DESC_RINGSIZE(sds_ring) \ | |
81 | (sizeof(struct status_desc) * (sds_ring)->num_desc) | |
82 | #define TX_BUFF_RINGSIZE(tx_ring) \ | |
83 | (sizeof(struct qlcnic_cmd_buffer) * tx_ring->num_desc) | |
84 | #define TX_DESC_RINGSIZE(tx_ring) \ | |
85 | (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) | |
86 | ||
87 | #define QLCNIC_P3P_A0 0x50 | |
88 | ||
89 | #define QLCNIC_IS_REVISION_P3P(REVISION) (REVISION >= QLCNIC_P3P_A0) | |
90 | ||
91 | #define FIRST_PAGE_GROUP_START 0 | |
92 | #define FIRST_PAGE_GROUP_END 0x100000 | |
93 | ||
94 | #define P3_MAX_MTU (9600) | |
95 | #define QLCNIC_MAX_ETHERHDR 32 /* This contains some padding */ | |
96 | ||
97 | #define QLCNIC_P3_RX_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + ETH_DATA_LEN) | |
98 | #define QLCNIC_P3_RX_JUMBO_BUF_MAX_LEN (QLCNIC_MAX_ETHERHDR + P3_MAX_MTU) | |
99 | #define QLCNIC_CT_DEFAULT_RX_BUF_LEN 2048 | |
100 | #define QLCNIC_LRO_BUFFER_EXTRA 2048 | |
101 | ||
af19b491 AKS |
102 | /* Opcodes to be used with the commands */ |
103 | #define TX_ETHER_PKT 0x01 | |
104 | #define TX_TCP_PKT 0x02 | |
105 | #define TX_UDP_PKT 0x03 | |
106 | #define TX_IP_PKT 0x04 | |
107 | #define TX_TCP_LSO 0x05 | |
108 | #define TX_TCP_LSO6 0x06 | |
109 | #define TX_IPSEC 0x07 | |
110 | #define TX_IPSEC_CMD 0x0a | |
111 | #define TX_TCPV6_PKT 0x0b | |
112 | #define TX_UDPV6_PKT 0x0c | |
113 | ||
114 | /* Tx defines */ | |
115 | #define MAX_BUFFERS_PER_CMD 32 | |
116 | #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + 4) | |
117 | #define QLCNIC_MAX_TX_TIMEOUTS 2 | |
118 | ||
119 | /* | |
120 | * Following are the states of the Phantom. Phantom will set them and | |
121 | * Host will read to check if the fields are correct. | |
122 | */ | |
123 | #define PHAN_INITIALIZE_FAILED 0xffff | |
124 | #define PHAN_INITIALIZE_COMPLETE 0xff01 | |
125 | ||
126 | /* Host writes the following to notify that it has done the init-handshake */ | |
127 | #define PHAN_INITIALIZE_ACK 0xf00f | |
128 | #define PHAN_PEG_RCV_INITIALIZED 0xff01 | |
129 | ||
130 | #define NUM_RCV_DESC_RINGS 3 | |
131 | #define NUM_STS_DESC_RINGS 4 | |
132 | ||
133 | #define RCV_RING_NORMAL 0 | |
134 | #define RCV_RING_JUMBO 1 | |
af19b491 AKS |
135 | |
136 | #define MIN_CMD_DESCRIPTORS 64 | |
137 | #define MIN_RCV_DESCRIPTORS 64 | |
138 | #define MIN_JUMBO_DESCRIPTORS 32 | |
139 | ||
140 | #define MAX_CMD_DESCRIPTORS 1024 | |
141 | #define MAX_RCV_DESCRIPTORS_1G 4096 | |
142 | #define MAX_RCV_DESCRIPTORS_10G 8192 | |
143 | #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 | |
144 | #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 | |
af19b491 AKS |
145 | |
146 | #define DEFAULT_RCV_DESCRIPTORS_1G 2048 | |
147 | #define DEFAULT_RCV_DESCRIPTORS_10G 4096 | |
148 | ||
149 | #define get_next_index(index, length) \ | |
150 | (((index) + 1) & ((length) - 1)) | |
151 | ||
af19b491 AKS |
152 | /* |
153 | * Following data structures describe the descriptors that will be used. | |
154 | * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when | |
155 | * we are doing LSO (above the 1500 size packet) only. | |
156 | */ | |
157 | ||
158 | #define FLAGS_VLAN_TAGGED 0x10 | |
159 | #define FLAGS_VLAN_OOB 0x40 | |
160 | ||
161 | #define qlcnic_set_tx_vlan_tci(cmd_desc, v) \ | |
162 | (cmd_desc)->vlan_TCI = cpu_to_le16(v); | |
163 | #define qlcnic_set_cmd_desc_port(cmd_desc, var) \ | |
164 | ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) | |
165 | #define qlcnic_set_cmd_desc_ctxid(cmd_desc, var) \ | |
166 | ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0)) | |
167 | ||
168 | #define qlcnic_set_tx_port(_desc, _port) \ | |
169 | ((_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)) | |
170 | ||
171 | #define qlcnic_set_tx_flags_opcode(_desc, _flags, _opcode) \ | |
172 | ((_desc)->flags_opcode = \ | |
173 | cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))) | |
174 | ||
175 | #define qlcnic_set_tx_frags_len(_desc, _frags, _len) \ | |
176 | ((_desc)->nfrags__length = \ | |
177 | cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))) | |
178 | ||
179 | struct cmd_desc_type0 { | |
180 | u8 tcp_hdr_offset; /* For LSO only */ | |
181 | u8 ip_hdr_offset; /* For LSO only */ | |
182 | __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ | |
183 | __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ | |
184 | ||
185 | __le64 addr_buffer2; | |
186 | ||
187 | __le16 reference_handle; | |
188 | __le16 mss; | |
189 | u8 port_ctxid; /* 7:4 ctxid 3:0 port */ | |
190 | u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ | |
191 | __le16 conn_id; /* IPSec offoad only */ | |
192 | ||
193 | __le64 addr_buffer3; | |
194 | __le64 addr_buffer1; | |
195 | ||
196 | __le16 buffer_length[4]; | |
197 | ||
198 | __le64 addr_buffer4; | |
199 | ||
200 | __le32 reserved2; | |
201 | __le16 reserved; | |
202 | __le16 vlan_TCI; | |
203 | ||
204 | } __attribute__ ((aligned(64))); | |
205 | ||
206 | /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ | |
207 | struct rcv_desc { | |
208 | __le16 reference_handle; | |
209 | __le16 reserved; | |
210 | __le32 buffer_length; /* allocated buffer length (usually 2K) */ | |
211 | __le64 addr_buffer; | |
212 | }; | |
213 | ||
214 | /* opcode field in status_desc */ | |
215 | #define QLCNIC_SYN_OFFLOAD 0x03 | |
216 | #define QLCNIC_RXPKT_DESC 0x04 | |
217 | #define QLCNIC_OLD_RXPKT_DESC 0x3f | |
218 | #define QLCNIC_RESPONSE_DESC 0x05 | |
219 | #define QLCNIC_LRO_DESC 0x12 | |
220 | ||
221 | /* for status field in status_desc */ | |
222 | #define STATUS_CKSUM_OK (2) | |
223 | ||
224 | /* owner bits of status_desc */ | |
225 | #define STATUS_OWNER_HOST (0x1ULL << 56) | |
226 | #define STATUS_OWNER_PHANTOM (0x2ULL << 56) | |
227 | ||
228 | /* Status descriptor: | |
229 | 0-3 port, 4-7 status, 8-11 type, 12-27 total_length | |
230 | 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset | |
231 | 53-55 desc_cnt, 56-57 owner, 58-63 opcode | |
232 | */ | |
233 | #define qlcnic_get_sts_port(sts_data) \ | |
234 | ((sts_data) & 0x0F) | |
235 | #define qlcnic_get_sts_status(sts_data) \ | |
236 | (((sts_data) >> 4) & 0x0F) | |
237 | #define qlcnic_get_sts_type(sts_data) \ | |
238 | (((sts_data) >> 8) & 0x0F) | |
239 | #define qlcnic_get_sts_totallength(sts_data) \ | |
240 | (((sts_data) >> 12) & 0xFFFF) | |
241 | #define qlcnic_get_sts_refhandle(sts_data) \ | |
242 | (((sts_data) >> 28) & 0xFFFF) | |
243 | #define qlcnic_get_sts_prot(sts_data) \ | |
244 | (((sts_data) >> 44) & 0x0F) | |
245 | #define qlcnic_get_sts_pkt_offset(sts_data) \ | |
246 | (((sts_data) >> 48) & 0x1F) | |
247 | #define qlcnic_get_sts_desc_cnt(sts_data) \ | |
248 | (((sts_data) >> 53) & 0x7) | |
249 | #define qlcnic_get_sts_opcode(sts_data) \ | |
250 | (((sts_data) >> 58) & 0x03F) | |
251 | ||
252 | #define qlcnic_get_lro_sts_refhandle(sts_data) \ | |
253 | ((sts_data) & 0x0FFFF) | |
254 | #define qlcnic_get_lro_sts_length(sts_data) \ | |
255 | (((sts_data) >> 16) & 0x0FFFF) | |
256 | #define qlcnic_get_lro_sts_l2_hdr_offset(sts_data) \ | |
257 | (((sts_data) >> 32) & 0x0FF) | |
258 | #define qlcnic_get_lro_sts_l4_hdr_offset(sts_data) \ | |
259 | (((sts_data) >> 40) & 0x0FF) | |
260 | #define qlcnic_get_lro_sts_timestamp(sts_data) \ | |
261 | (((sts_data) >> 48) & 0x1) | |
262 | #define qlcnic_get_lro_sts_type(sts_data) \ | |
263 | (((sts_data) >> 49) & 0x7) | |
264 | #define qlcnic_get_lro_sts_push_flag(sts_data) \ | |
265 | (((sts_data) >> 52) & 0x1) | |
266 | #define qlcnic_get_lro_sts_seq_number(sts_data) \ | |
267 | ((sts_data) & 0x0FFFFFFFF) | |
268 | ||
269 | ||
270 | struct status_desc { | |
271 | __le64 status_desc_data[2]; | |
272 | } __attribute__ ((aligned(16))); | |
273 | ||
274 | /* UNIFIED ROMIMAGE */ | |
275 | #define QLCNIC_UNI_FW_MIN_SIZE 0xc8000 | |
276 | #define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0 | |
277 | #define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6 | |
278 | #define QLCNIC_UNI_DIR_SECT_FW 0x7 | |
279 | ||
280 | /*Offsets */ | |
281 | #define QLCNIC_UNI_CHIP_REV_OFF 10 | |
282 | #define QLCNIC_UNI_FLAGS_OFF 11 | |
283 | #define QLCNIC_UNI_BIOS_VERSION_OFF 12 | |
284 | #define QLCNIC_UNI_BOOTLD_IDX_OFF 27 | |
285 | #define QLCNIC_UNI_FIRMWARE_IDX_OFF 29 | |
286 | ||
287 | struct uni_table_desc{ | |
288 | u32 findex; | |
289 | u32 num_entries; | |
290 | u32 entry_size; | |
291 | u32 reserved[5]; | |
292 | }; | |
293 | ||
294 | struct uni_data_desc{ | |
295 | u32 findex; | |
296 | u32 size; | |
297 | u32 reserved[5]; | |
298 | }; | |
299 | ||
300 | /* Magic number to let user know flash is programmed */ | |
301 | #define QLCNIC_BDINFO_MAGIC 0x12345678 | |
302 | ||
303 | #define QLCNIC_BRDTYPE_P3_REF_QG 0x0021 | |
304 | #define QLCNIC_BRDTYPE_P3_HMEZ 0x0022 | |
305 | #define QLCNIC_BRDTYPE_P3_10G_CX4_LP 0x0023 | |
306 | #define QLCNIC_BRDTYPE_P3_4_GB 0x0024 | |
307 | #define QLCNIC_BRDTYPE_P3_IMEZ 0x0025 | |
308 | #define QLCNIC_BRDTYPE_P3_10G_SFP_PLUS 0x0026 | |
309 | #define QLCNIC_BRDTYPE_P3_10000_BASE_T 0x0027 | |
310 | #define QLCNIC_BRDTYPE_P3_XG_LOM 0x0028 | |
311 | #define QLCNIC_BRDTYPE_P3_4_GB_MM 0x0029 | |
312 | #define QLCNIC_BRDTYPE_P3_10G_SFP_CT 0x002a | |
313 | #define QLCNIC_BRDTYPE_P3_10G_SFP_QT 0x002b | |
314 | #define QLCNIC_BRDTYPE_P3_10G_CX4 0x0031 | |
315 | #define QLCNIC_BRDTYPE_P3_10G_XFP 0x0032 | |
316 | #define QLCNIC_BRDTYPE_P3_10G_TP 0x0080 | |
317 | ||
318 | /* Flash memory map */ | |
319 | #define QLCNIC_BRDCFG_START 0x4000 /* board config */ | |
320 | #define QLCNIC_BOOTLD_START 0x10000 /* bootld */ | |
321 | #define QLCNIC_IMAGE_START 0x43000 /* compressed image */ | |
322 | #define QLCNIC_USER_START 0x3E8000 /* Firmare info */ | |
323 | ||
324 | #define QLCNIC_FW_VERSION_OFFSET (QLCNIC_USER_START+0x408) | |
325 | #define QLCNIC_FW_SIZE_OFFSET (QLCNIC_USER_START+0x40c) | |
326 | #define QLCNIC_FW_SERIAL_NUM_OFFSET (QLCNIC_USER_START+0x81c) | |
327 | #define QLCNIC_BIOS_VERSION_OFFSET (QLCNIC_USER_START+0x83c) | |
328 | ||
329 | #define QLCNIC_BRDTYPE_OFFSET (QLCNIC_BRDCFG_START+0x8) | |
330 | #define QLCNIC_FW_MAGIC_OFFSET (QLCNIC_BRDCFG_START+0x128) | |
331 | ||
332 | #define QLCNIC_FW_MIN_SIZE (0x3fffff) | |
333 | #define QLCNIC_UNIFIED_ROMIMAGE 0 | |
334 | #define QLCNIC_FLASH_ROMIMAGE 1 | |
335 | #define QLCNIC_UNKNOWN_ROMIMAGE 0xff | |
336 | ||
337 | #define QLCNIC_UNIFIED_ROMIMAGE_NAME "phanfw.bin" | |
338 | #define QLCNIC_FLASH_ROMIMAGE_NAME "flash" | |
339 | ||
340 | extern char qlcnic_driver_name[]; | |
341 | ||
342 | /* Number of status descriptors to handle per interrupt */ | |
343 | #define MAX_STATUS_HANDLE (64) | |
344 | ||
345 | /* | |
346 | * qlcnic_skb_frag{} is to contain mapping info for each SG list. This | |
347 | * has to be freed when DMA is complete. This is part of qlcnic_tx_buffer{}. | |
348 | */ | |
349 | struct qlcnic_skb_frag { | |
350 | u64 dma; | |
351 | u64 length; | |
352 | }; | |
353 | ||
354 | struct qlcnic_recv_crb { | |
355 | u32 crb_rcv_producer[NUM_RCV_DESC_RINGS]; | |
356 | u32 crb_sts_consumer[NUM_STS_DESC_RINGS]; | |
357 | u32 sw_int_mask[NUM_STS_DESC_RINGS]; | |
358 | }; | |
359 | ||
360 | /* Following defines are for the state of the buffers */ | |
361 | #define QLCNIC_BUFFER_FREE 0 | |
362 | #define QLCNIC_BUFFER_BUSY 1 | |
363 | ||
364 | /* | |
365 | * There will be one qlcnic_buffer per skb packet. These will be | |
366 | * used to save the dma info for pci_unmap_page() | |
367 | */ | |
368 | struct qlcnic_cmd_buffer { | |
369 | struct sk_buff *skb; | |
370 | struct qlcnic_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1]; | |
371 | u32 frag_count; | |
372 | }; | |
373 | ||
374 | /* In rx_buffer, we do not need multiple fragments as is a single buffer */ | |
375 | struct qlcnic_rx_buffer { | |
376 | struct list_head list; | |
377 | struct sk_buff *skb; | |
378 | u64 dma; | |
379 | u16 ref_handle; | |
380 | u16 state; | |
381 | }; | |
382 | ||
383 | /* Board types */ | |
384 | #define QLCNIC_GBE 0x01 | |
385 | #define QLCNIC_XGBE 0x02 | |
386 | ||
387 | /* | |
388 | * One hardware_context{} per adapter | |
389 | * contains interrupt info as well shared hardware info. | |
390 | */ | |
391 | struct qlcnic_hardware_context { | |
392 | void __iomem *pci_base0; | |
393 | void __iomem *ocm_win_crb; | |
394 | ||
395 | unsigned long pci_len0; | |
396 | ||
af19b491 AKS |
397 | rwlock_t crb_lock; |
398 | struct mutex mem_lock; | |
399 | ||
af19b491 AKS |
400 | u8 revision_id; |
401 | u8 pci_func; | |
402 | u8 linkup; | |
403 | u16 port_type; | |
404 | u16 board_type; | |
405 | }; | |
406 | ||
407 | struct qlcnic_adapter_stats { | |
408 | u64 xmitcalled; | |
409 | u64 xmitfinished; | |
410 | u64 rxdropped; | |
411 | u64 txdropped; | |
412 | u64 csummed; | |
413 | u64 rx_pkts; | |
414 | u64 lro_pkts; | |
415 | u64 rxbytes; | |
416 | u64 txbytes; | |
8bfe8b91 SC |
417 | u64 lrobytes; |
418 | u64 lso_frames; | |
419 | u64 xmit_on; | |
420 | u64 xmit_off; | |
421 | u64 skb_alloc_failure; | |
8ae6df97 AKS |
422 | u64 null_skb; |
423 | u64 null_rxbuf; | |
424 | u64 rx_dma_map_error; | |
425 | u64 tx_dma_map_error; | |
af19b491 AKS |
426 | }; |
427 | ||
428 | /* | |
429 | * Rcv Descriptor Context. One such per Rcv Descriptor. There may | |
430 | * be one Rcv Descriptor for normal packets, one for jumbo and may be others. | |
431 | */ | |
432 | struct qlcnic_host_rds_ring { | |
433 | u32 producer; | |
434 | u32 num_desc; | |
435 | u32 dma_size; | |
436 | u32 skb_size; | |
437 | u32 flags; | |
438 | void __iomem *crb_rcv_producer; | |
439 | struct rcv_desc *desc_head; | |
440 | struct qlcnic_rx_buffer *rx_buf_arr; | |
441 | struct list_head free_list; | |
442 | spinlock_t lock; | |
443 | dma_addr_t phys_addr; | |
444 | }; | |
445 | ||
446 | struct qlcnic_host_sds_ring { | |
447 | u32 consumer; | |
448 | u32 num_desc; | |
449 | void __iomem *crb_sts_consumer; | |
450 | void __iomem *crb_intr_mask; | |
451 | ||
452 | struct status_desc *desc_head; | |
453 | struct qlcnic_adapter *adapter; | |
454 | struct napi_struct napi; | |
455 | struct list_head free_list[NUM_RCV_DESC_RINGS]; | |
456 | ||
457 | int irq; | |
458 | ||
459 | dma_addr_t phys_addr; | |
460 | char name[IFNAMSIZ+4]; | |
461 | }; | |
462 | ||
463 | struct qlcnic_host_tx_ring { | |
464 | u32 producer; | |
465 | __le32 *hw_consumer; | |
466 | u32 sw_consumer; | |
467 | void __iomem *crb_cmd_producer; | |
468 | u32 num_desc; | |
469 | ||
470 | struct netdev_queue *txq; | |
471 | ||
472 | struct qlcnic_cmd_buffer *cmd_buf_arr; | |
473 | struct cmd_desc_type0 *desc_head; | |
474 | dma_addr_t phys_addr; | |
475 | dma_addr_t hw_cons_phys_addr; | |
476 | }; | |
477 | ||
478 | /* | |
479 | * Receive context. There is one such structure per instance of the | |
480 | * receive processing. Any state information that is relevant to | |
481 | * the receive, and is must be in this structure. The global data may be | |
482 | * present elsewhere. | |
483 | */ | |
484 | struct qlcnic_recv_context { | |
485 | u32 state; | |
486 | u16 context_id; | |
487 | u16 virt_port; | |
488 | ||
489 | struct qlcnic_host_rds_ring *rds_rings; | |
490 | struct qlcnic_host_sds_ring *sds_rings; | |
491 | }; | |
492 | ||
493 | /* HW context creation */ | |
494 | ||
495 | #define QLCNIC_OS_CRB_RETRY_COUNT 4000 | |
496 | #define QLCNIC_CDRP_SIGNATURE_MAKE(pcifn, version) \ | |
497 | (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) | |
498 | ||
499 | #define QLCNIC_CDRP_CMD_BIT 0x80000000 | |
500 | ||
501 | /* | |
502 | * All responses must have the QLCNIC_CDRP_CMD_BIT cleared | |
503 | * in the crb QLCNIC_CDRP_CRB_OFFSET. | |
504 | */ | |
505 | #define QLCNIC_CDRP_FORM_RSP(rsp) (rsp) | |
506 | #define QLCNIC_CDRP_IS_RSP(rsp) (((rsp) & QLCNIC_CDRP_CMD_BIT) == 0) | |
507 | ||
508 | #define QLCNIC_CDRP_RSP_OK 0x00000001 | |
509 | #define QLCNIC_CDRP_RSP_FAIL 0x00000002 | |
510 | #define QLCNIC_CDRP_RSP_TIMEOUT 0x00000003 | |
511 | ||
512 | /* | |
513 | * All commands must have the QLCNIC_CDRP_CMD_BIT set in | |
514 | * the crb QLCNIC_CDRP_CRB_OFFSET. | |
515 | */ | |
516 | #define QLCNIC_CDRP_FORM_CMD(cmd) (QLCNIC_CDRP_CMD_BIT | (cmd)) | |
517 | #define QLCNIC_CDRP_IS_CMD(cmd) (((cmd) & QLCNIC_CDRP_CMD_BIT) != 0) | |
518 | ||
519 | #define QLCNIC_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 | |
520 | #define QLCNIC_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 | |
521 | #define QLCNIC_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 | |
522 | #define QLCNIC_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 | |
523 | #define QLCNIC_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 | |
524 | #define QLCNIC_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 | |
525 | #define QLCNIC_CDRP_CMD_CREATE_RX_CTX 0x00000007 | |
526 | #define QLCNIC_CDRP_CMD_DESTROY_RX_CTX 0x00000008 | |
527 | #define QLCNIC_CDRP_CMD_CREATE_TX_CTX 0x00000009 | |
528 | #define QLCNIC_CDRP_CMD_DESTROY_TX_CTX 0x0000000a | |
529 | #define QLCNIC_CDRP_CMD_SETUP_STATISTICS 0x0000000e | |
530 | #define QLCNIC_CDRP_CMD_GET_STATISTICS 0x0000000f | |
531 | #define QLCNIC_CDRP_CMD_DELETE_STATISTICS 0x00000010 | |
532 | #define QLCNIC_CDRP_CMD_SET_MTU 0x00000012 | |
533 | #define QLCNIC_CDRP_CMD_READ_PHY 0x00000013 | |
534 | #define QLCNIC_CDRP_CMD_WRITE_PHY 0x00000014 | |
535 | #define QLCNIC_CDRP_CMD_READ_HW_REG 0x00000015 | |
536 | #define QLCNIC_CDRP_CMD_GET_FLOW_CTL 0x00000016 | |
537 | #define QLCNIC_CDRP_CMD_SET_FLOW_CTL 0x00000017 | |
538 | #define QLCNIC_CDRP_CMD_READ_MAX_MTU 0x00000018 | |
539 | #define QLCNIC_CDRP_CMD_READ_MAX_LRO 0x00000019 | |
540 | #define QLCNIC_CDRP_CMD_CONFIGURE_TOE 0x0000001a | |
541 | #define QLCNIC_CDRP_CMD_FUNC_ATTRIB 0x0000001b | |
542 | #define QLCNIC_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c | |
543 | #define QLCNIC_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d | |
544 | #define QLCNIC_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e | |
545 | #define QLCNIC_CDRP_CMD_MAX 0x0000001f | |
546 | ||
547 | #define QLCNIC_RCODE_SUCCESS 0 | |
548 | #define QLCNIC_RCODE_TIMEOUT 17 | |
549 | #define QLCNIC_DESTROY_CTX_RESET 0 | |
550 | ||
551 | /* | |
552 | * Capabilities Announced | |
553 | */ | |
554 | #define QLCNIC_CAP0_LEGACY_CONTEXT (1) | |
555 | #define QLCNIC_CAP0_LEGACY_MN (1 << 2) | |
556 | #define QLCNIC_CAP0_LSO (1 << 6) | |
557 | #define QLCNIC_CAP0_JUMBO_CONTIGUOUS (1 << 7) | |
558 | #define QLCNIC_CAP0_LRO_CONTIGUOUS (1 << 8) | |
559 | ||
560 | /* | |
561 | * Context state | |
562 | */ | |
7eb9855d AKS |
563 | #define QLCHAL_VERSION 1 |
564 | ||
af19b491 AKS |
565 | #define QLCNIC_HOST_CTX_STATE_ACTIVE 2 |
566 | ||
567 | /* | |
568 | * Rx context | |
569 | */ | |
570 | ||
571 | struct qlcnic_hostrq_sds_ring { | |
572 | __le64 host_phys_addr; /* Ring base addr */ | |
573 | __le32 ring_size; /* Ring entries */ | |
574 | __le16 msi_index; | |
575 | __le16 rsvd; /* Padding */ | |
576 | }; | |
577 | ||
578 | struct qlcnic_hostrq_rds_ring { | |
579 | __le64 host_phys_addr; /* Ring base addr */ | |
580 | __le64 buff_size; /* Packet buffer size */ | |
581 | __le32 ring_size; /* Ring entries */ | |
582 | __le32 ring_kind; /* Class of ring */ | |
583 | }; | |
584 | ||
585 | struct qlcnic_hostrq_rx_ctx { | |
586 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
587 | __le32 capabilities[4]; /* Flag bit vector */ | |
588 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
589 | __le32 host_rds_crb_mode; /* RDS crb usage */ | |
590 | /* These ring offsets are relative to data[0] below */ | |
591 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
592 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
593 | __le16 num_rds_rings; /* Count of RDS rings */ | |
594 | __le16 num_sds_rings; /* Count of SDS rings */ | |
595 | __le16 rsvd1; /* Padding */ | |
596 | __le16 rsvd2; /* Padding */ | |
597 | u8 reserved[128]; /* reserve space for future expansion*/ | |
598 | /* MUST BE 64-bit aligned. | |
599 | The following is packed: | |
600 | - N hostrq_rds_rings | |
601 | - N hostrq_sds_rings */ | |
602 | char data[0]; | |
603 | }; | |
604 | ||
605 | struct qlcnic_cardrsp_rds_ring{ | |
606 | __le32 host_producer_crb; /* Crb to use */ | |
607 | __le32 rsvd1; /* Padding */ | |
608 | }; | |
609 | ||
610 | struct qlcnic_cardrsp_sds_ring { | |
611 | __le32 host_consumer_crb; /* Crb to use */ | |
612 | __le32 interrupt_crb; /* Crb to use */ | |
613 | }; | |
614 | ||
615 | struct qlcnic_cardrsp_rx_ctx { | |
616 | /* These ring offsets are relative to data[0] below */ | |
617 | __le32 rds_ring_offset; /* Offset to RDS config */ | |
618 | __le32 sds_ring_offset; /* Offset to SDS config */ | |
619 | __le32 host_ctx_state; /* Starting State */ | |
620 | __le32 num_fn_per_port; /* How many PCI fn share the port */ | |
621 | __le16 num_rds_rings; /* Count of RDS rings */ | |
622 | __le16 num_sds_rings; /* Count of SDS rings */ | |
623 | __le16 context_id; /* Handle for context */ | |
624 | u8 phys_port; /* Physical id of port */ | |
625 | u8 virt_port; /* Virtual/Logical id of port */ | |
626 | u8 reserved[128]; /* save space for future expansion */ | |
627 | /* MUST BE 64-bit aligned. | |
628 | The following is packed: | |
629 | - N cardrsp_rds_rings | |
630 | - N cardrs_sds_rings */ | |
631 | char data[0]; | |
632 | }; | |
633 | ||
634 | #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ | |
635 | (sizeof(HOSTRQ_RX) + \ | |
636 | (rds_rings)*(sizeof(struct qlcnic_hostrq_rds_ring)) + \ | |
637 | (sds_rings)*(sizeof(struct qlcnic_hostrq_sds_ring))) | |
638 | ||
639 | #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ | |
640 | (sizeof(CARDRSP_RX) + \ | |
641 | (rds_rings)*(sizeof(struct qlcnic_cardrsp_rds_ring)) + \ | |
642 | (sds_rings)*(sizeof(struct qlcnic_cardrsp_sds_ring))) | |
643 | ||
644 | /* | |
645 | * Tx context | |
646 | */ | |
647 | ||
648 | struct qlcnic_hostrq_cds_ring { | |
649 | __le64 host_phys_addr; /* Ring base addr */ | |
650 | __le32 ring_size; /* Ring entries */ | |
651 | __le32 rsvd; /* Padding */ | |
652 | }; | |
653 | ||
654 | struct qlcnic_hostrq_tx_ctx { | |
655 | __le64 host_rsp_dma_addr; /* Response dma'd here */ | |
656 | __le64 cmd_cons_dma_addr; /* */ | |
657 | __le64 dummy_dma_addr; /* */ | |
658 | __le32 capabilities[4]; /* Flag bit vector */ | |
659 | __le32 host_int_crb_mode; /* Interrupt crb usage */ | |
660 | __le32 rsvd1; /* Padding */ | |
661 | __le16 rsvd2; /* Padding */ | |
662 | __le16 interrupt_ctl; | |
663 | __le16 msi_index; | |
664 | __le16 rsvd3; /* Padding */ | |
665 | struct qlcnic_hostrq_cds_ring cds_ring; /* Desc of cds ring */ | |
666 | u8 reserved[128]; /* future expansion */ | |
667 | }; | |
668 | ||
669 | struct qlcnic_cardrsp_cds_ring { | |
670 | __le32 host_producer_crb; /* Crb to use */ | |
671 | __le32 interrupt_crb; /* Crb to use */ | |
672 | }; | |
673 | ||
674 | struct qlcnic_cardrsp_tx_ctx { | |
675 | __le32 host_ctx_state; /* Starting state */ | |
676 | __le16 context_id; /* Handle for context */ | |
677 | u8 phys_port; /* Physical id of port */ | |
678 | u8 virt_port; /* Virtual/Logical id of port */ | |
679 | struct qlcnic_cardrsp_cds_ring cds_ring; /* Card cds settings */ | |
680 | u8 reserved[128]; /* future expansion */ | |
681 | }; | |
682 | ||
683 | #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) | |
684 | #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) | |
685 | ||
686 | /* CRB */ | |
687 | ||
688 | #define QLCNIC_HOST_RDS_CRB_MODE_UNIQUE 0 | |
689 | #define QLCNIC_HOST_RDS_CRB_MODE_SHARED 1 | |
690 | #define QLCNIC_HOST_RDS_CRB_MODE_CUSTOM 2 | |
691 | #define QLCNIC_HOST_RDS_CRB_MODE_MAX 3 | |
692 | ||
693 | #define QLCNIC_HOST_INT_CRB_MODE_UNIQUE 0 | |
694 | #define QLCNIC_HOST_INT_CRB_MODE_SHARED 1 | |
695 | #define QLCNIC_HOST_INT_CRB_MODE_NORX 2 | |
696 | #define QLCNIC_HOST_INT_CRB_MODE_NOTX 3 | |
697 | #define QLCNIC_HOST_INT_CRB_MODE_NORXTX 4 | |
698 | ||
699 | ||
700 | /* MAC */ | |
701 | ||
702 | #define MC_COUNT_P3 38 | |
703 | ||
704 | #define QLCNIC_MAC_NOOP 0 | |
705 | #define QLCNIC_MAC_ADD 1 | |
706 | #define QLCNIC_MAC_DEL 2 | |
707 | ||
708 | struct qlcnic_mac_list_s { | |
709 | struct list_head list; | |
710 | uint8_t mac_addr[ETH_ALEN+2]; | |
711 | }; | |
712 | ||
713 | /* | |
714 | * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is | |
715 | * adjusted based on configured MTU. | |
716 | */ | |
717 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_TIME_US 3 | |
718 | #define QLCNIC_DEFAULT_INTR_COALESCE_RX_PACKETS 256 | |
719 | #define QLCNIC_DEFAULT_INTR_COALESCE_TX_PACKETS 64 | |
720 | #define QLCNIC_DEFAULT_INTR_COALESCE_TX_TIME_US 4 | |
721 | ||
722 | #define QLCNIC_INTR_DEFAULT 0x04 | |
723 | ||
724 | union qlcnic_nic_intr_coalesce_data { | |
725 | struct { | |
726 | u16 rx_packets; | |
727 | u16 rx_time_us; | |
728 | u16 tx_packets; | |
729 | u16 tx_time_us; | |
730 | } data; | |
731 | u64 word; | |
732 | }; | |
733 | ||
734 | struct qlcnic_nic_intr_coalesce { | |
735 | u16 stats_time_us; | |
736 | u16 rate_sample_time; | |
737 | u16 flags; | |
738 | u16 rsvd_1; | |
739 | u32 low_threshold; | |
740 | u32 high_threshold; | |
741 | union qlcnic_nic_intr_coalesce_data normal; | |
742 | union qlcnic_nic_intr_coalesce_data low; | |
743 | union qlcnic_nic_intr_coalesce_data high; | |
744 | union qlcnic_nic_intr_coalesce_data irq; | |
745 | }; | |
746 | ||
747 | #define QLCNIC_HOST_REQUEST 0x13 | |
748 | #define QLCNIC_REQUEST 0x14 | |
749 | ||
750 | #define QLCNIC_MAC_EVENT 0x1 | |
751 | ||
752 | #define QLCNIC_IP_UP 2 | |
753 | #define QLCNIC_IP_DOWN 3 | |
754 | ||
755 | /* | |
756 | * Driver --> Firmware | |
757 | */ | |
758 | #define QLCNIC_H2C_OPCODE_START 0 | |
759 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS 1 | |
760 | #define QLCNIC_H2C_OPCODE_CONFIG_RSS_TBL 2 | |
761 | #define QLCNIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3 | |
762 | #define QLCNIC_H2C_OPCODE_CONFIG_LED 4 | |
763 | #define QLCNIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5 | |
764 | #define QLCNIC_H2C_OPCODE_CONFIG_L2_MAC 6 | |
765 | #define QLCNIC_H2C_OPCODE_LRO_REQUEST 7 | |
766 | #define QLCNIC_H2C_OPCODE_GET_SNMP_STATS 8 | |
767 | #define QLCNIC_H2C_OPCODE_PROXY_START_REQUEST 9 | |
768 | #define QLCNIC_H2C_OPCODE_PROXY_STOP_REQUEST 10 | |
769 | #define QLCNIC_H2C_OPCODE_PROXY_SET_MTU 11 | |
770 | #define QLCNIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12 | |
771 | #define QLCNIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13 | |
772 | #define QLCNIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14 | |
773 | #define QLCNIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15 | |
774 | #define QLCNIC_H2C_OPCODE_GET_NET_STATS 16 | |
775 | #define QLCNIC_H2C_OPCODE_PROXY_UPDATE_P2V 17 | |
776 | #define QLCNIC_H2C_OPCODE_CONFIG_IPADDR 18 | |
777 | #define QLCNIC_H2C_OPCODE_CONFIG_LOOPBACK 19 | |
778 | #define QLCNIC_H2C_OPCODE_PROXY_STOP_DONE 20 | |
779 | #define QLCNIC_H2C_OPCODE_GET_LINKEVENT 21 | |
780 | #define QLCNIC_C2C_OPCODE 22 | |
781 | #define QLCNIC_H2C_OPCODE_CONFIG_BRIDGING 23 | |
782 | #define QLCNIC_H2C_OPCODE_CONFIG_HW_LRO 24 | |
783 | #define QLCNIC_H2C_OPCODE_LAST 25 | |
784 | /* | |
785 | * Firmware --> Driver | |
786 | */ | |
787 | ||
788 | #define QLCNIC_C2H_OPCODE_START 128 | |
789 | #define QLCNIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129 | |
790 | #define QLCNIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130 | |
791 | #define QLCNIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131 | |
792 | #define QLCNIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132 | |
793 | #define QLCNIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133 | |
794 | #define QLCNIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134 | |
795 | #define QLCNIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135 | |
796 | #define QLCNIC_C2H_OPCODE_GET_SNMP_STATS 136 | |
797 | #define QLCNIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137 | |
798 | #define QLCNIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138 | |
799 | #define QLCNIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139 | |
800 | #define QLCNIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140 | |
801 | #define QLCNIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 | |
802 | #define QLCNIC_C2H_OPCODE_LAST 142 | |
803 | ||
804 | #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ | |
805 | #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ | |
806 | #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ | |
807 | ||
808 | #define QLCNIC_LRO_REQUEST_CLEANUP 4 | |
809 | ||
810 | /* Capabilites received */ | |
811 | #define QLCNIC_FW_CAPABILITY_BDG (1 << 8) | |
812 | #define QLCNIC_FW_CAPABILITY_FVLANTX (1 << 9) | |
813 | #define QLCNIC_FW_CAPABILITY_HW_LRO (1 << 10) | |
814 | ||
815 | /* module types */ | |
816 | #define LINKEVENT_MODULE_NOT_PRESENT 1 | |
817 | #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 | |
818 | #define LINKEVENT_MODULE_OPTICAL_SRLR 3 | |
819 | #define LINKEVENT_MODULE_OPTICAL_LRM 4 | |
820 | #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 | |
821 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 | |
822 | #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 | |
823 | #define LINKEVENT_MODULE_TWINAX 8 | |
824 | ||
825 | #define LINKSPEED_10GBPS 10000 | |
826 | #define LINKSPEED_1GBPS 1000 | |
827 | #define LINKSPEED_100MBPS 100 | |
828 | #define LINKSPEED_10MBPS 10 | |
829 | ||
830 | #define LINKSPEED_ENCODED_10MBPS 0 | |
831 | #define LINKSPEED_ENCODED_100MBPS 1 | |
832 | #define LINKSPEED_ENCODED_1GBPS 2 | |
833 | ||
834 | #define LINKEVENT_AUTONEG_DISABLED 0 | |
835 | #define LINKEVENT_AUTONEG_ENABLED 1 | |
836 | ||
837 | #define LINKEVENT_HALF_DUPLEX 0 | |
838 | #define LINKEVENT_FULL_DUPLEX 1 | |
839 | ||
840 | #define LINKEVENT_LINKSPEED_MBPS 0 | |
841 | #define LINKEVENT_LINKSPEED_ENCODED 1 | |
842 | ||
843 | #define AUTO_FW_RESET_ENABLED 0x01 | |
844 | /* firmware response header: | |
845 | * 63:58 - message type | |
846 | * 57:56 - owner | |
847 | * 55:53 - desc count | |
848 | * 52:48 - reserved | |
849 | * 47:40 - completion id | |
850 | * 39:32 - opcode | |
851 | * 31:16 - error code | |
852 | * 15:00 - reserved | |
853 | */ | |
854 | #define qlcnic_get_nic_msg_opcode(msg_hdr) \ | |
855 | ((msg_hdr >> 32) & 0xFF) | |
856 | ||
857 | struct qlcnic_fw_msg { | |
858 | union { | |
859 | struct { | |
860 | u64 hdr; | |
861 | u64 body[7]; | |
862 | }; | |
863 | u64 words[8]; | |
864 | }; | |
865 | }; | |
866 | ||
867 | struct qlcnic_nic_req { | |
868 | __le64 qhdr; | |
869 | __le64 req_hdr; | |
870 | __le64 words[6]; | |
871 | }; | |
872 | ||
873 | struct qlcnic_mac_req { | |
874 | u8 op; | |
875 | u8 tag; | |
876 | u8 mac_addr[6]; | |
877 | }; | |
878 | ||
879 | #define QLCNIC_MSI_ENABLED 0x02 | |
880 | #define QLCNIC_MSIX_ENABLED 0x04 | |
881 | #define QLCNIC_LRO_ENABLED 0x08 | |
882 | #define QLCNIC_BRIDGE_ENABLED 0X10 | |
883 | #define QLCNIC_DIAG_ENABLED 0x20 | |
884 | #define QLCNIC_IS_MSI_FAMILY(adapter) \ | |
885 | ((adapter)->flags & (QLCNIC_MSI_ENABLED | QLCNIC_MSIX_ENABLED)) | |
886 | ||
887 | #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS | |
888 | #define QLCNIC_MSIX_TBL_SPACE 8192 | |
889 | #define QLCNIC_PCI_REG_MSIX_TBL 0x44 | |
890 | ||
891 | #define QLCNIC_NETDEV_WEIGHT 128 | |
892 | #define QLCNIC_ADAPTER_UP_MAGIC 777 | |
893 | ||
894 | #define __QLCNIC_FW_ATTACHED 0 | |
895 | #define __QLCNIC_DEV_UP 1 | |
896 | #define __QLCNIC_RESETTING 2 | |
897 | #define __QLCNIC_START_FW 4 | |
898 | ||
7eb9855d | 899 | #define QLCNIC_INTERRUPT_TEST 1 |
cdaff185 | 900 | #define QLCNIC_LOOPBACK_TEST 2 |
7eb9855d | 901 | |
af19b491 AKS |
902 | struct qlcnic_adapter { |
903 | struct qlcnic_hardware_context ahw; | |
904 | ||
905 | struct net_device *netdev; | |
906 | struct pci_dev *pdev; | |
907 | struct list_head mac_list; | |
908 | ||
909 | spinlock_t tx_clean_lock; | |
910 | ||
911 | u16 num_txd; | |
912 | u16 num_rxd; | |
913 | u16 num_jumbo_rxd; | |
af19b491 AKS |
914 | |
915 | u8 max_rds_rings; | |
916 | u8 max_sds_rings; | |
917 | u8 driver_mismatch; | |
918 | u8 msix_supported; | |
919 | u8 rx_csum; | |
af19b491 AKS |
920 | u8 portnum; |
921 | u8 physical_port; | |
922 | ||
923 | u8 mc_enabled; | |
924 | u8 max_mc_count; | |
925 | u8 rss_supported; | |
926 | u8 rsrvd1; | |
927 | u8 fw_wait_cnt; | |
928 | u8 fw_fail_cnt; | |
929 | u8 tx_timeo_cnt; | |
930 | u8 need_fw_reset; | |
931 | ||
932 | u8 has_link_events; | |
933 | u8 fw_type; | |
934 | u16 tx_context_id; | |
935 | u16 mtu; | |
936 | u16 is_up; | |
937 | ||
938 | u16 link_speed; | |
939 | u16 link_duplex; | |
940 | u16 link_autoneg; | |
941 | u16 module_type; | |
942 | ||
943 | u32 capabilities; | |
944 | u32 flags; | |
945 | u32 irq; | |
946 | u32 temp; | |
947 | ||
948 | u32 int_vec_bit; | |
949 | u32 heartbit; | |
950 | ||
951 | u8 dev_state; | |
7eb9855d AKS |
952 | u8 diag_test; |
953 | u8 diag_cnt; | |
aa5e18c0 SC |
954 | u8 reset_ack_timeo; |
955 | u8 dev_init_timeo; | |
af19b491 | 956 | u8 rsrd1; |
65b5b420 | 957 | u16 msg_enable; |
af19b491 AKS |
958 | |
959 | u8 mac_addr[ETH_ALEN]; | |
960 | ||
6df900e9 SC |
961 | u64 dev_rst_time; |
962 | ||
af19b491 AKS |
963 | struct qlcnic_adapter_stats stats; |
964 | ||
965 | struct qlcnic_recv_context recv_ctx; | |
966 | struct qlcnic_host_tx_ring *tx_ring; | |
967 | ||
968 | void __iomem *tgt_mask_reg; | |
969 | void __iomem *tgt_status_reg; | |
970 | void __iomem *crb_int_state_reg; | |
971 | void __iomem *isr_int_vec; | |
972 | ||
973 | struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER]; | |
974 | ||
975 | struct delayed_work fw_work; | |
976 | ||
977 | struct work_struct tx_timeout_task; | |
978 | ||
979 | struct qlcnic_nic_intr_coalesce coal; | |
980 | ||
981 | unsigned long state; | |
982 | __le32 file_prd_off; /*File fw product offset*/ | |
983 | u32 fw_version; | |
984 | const struct firmware *fw; | |
985 | }; | |
986 | ||
987 | int qlcnic_fw_cmd_query_phy(struct qlcnic_adapter *adapter, u32 reg, u32 *val); | |
988 | int qlcnic_fw_cmd_set_phy(struct qlcnic_adapter *adapter, u32 reg, u32 val); | |
989 | ||
990 | u32 qlcnic_hw_read_wx_2M(struct qlcnic_adapter *adapter, ulong off); | |
991 | int qlcnic_hw_write_wx_2M(struct qlcnic_adapter *, ulong off, u32 data); | |
992 | int qlcnic_pci_mem_write_2M(struct qlcnic_adapter *, u64 off, u64 data); | |
993 | int qlcnic_pci_mem_read_2M(struct qlcnic_adapter *, u64 off, u64 *data); | |
897e8c7c DP |
994 | void qlcnic_pci_camqm_read_2M(struct qlcnic_adapter *, u64, u64 *); |
995 | void qlcnic_pci_camqm_write_2M(struct qlcnic_adapter *, u64, u64); | |
996 | ||
997 | #define ADDR_IN_RANGE(addr, low, high) \ | |
998 | (((addr) < (high)) && ((addr) >= (low))) | |
af19b491 AKS |
999 | |
1000 | #define QLCRD32(adapter, off) \ | |
1001 | (qlcnic_hw_read_wx_2M(adapter, off)) | |
1002 | #define QLCWR32(adapter, off, val) \ | |
1003 | (qlcnic_hw_write_wx_2M(adapter, off, val)) | |
1004 | ||
1005 | int qlcnic_pcie_sem_lock(struct qlcnic_adapter *, int, u32); | |
1006 | void qlcnic_pcie_sem_unlock(struct qlcnic_adapter *, int); | |
1007 | ||
1008 | #define qlcnic_rom_lock(a) \ | |
1009 | qlcnic_pcie_sem_lock((a), 2, QLCNIC_ROM_LOCK_ID) | |
1010 | #define qlcnic_rom_unlock(a) \ | |
1011 | qlcnic_pcie_sem_unlock((a), 2) | |
1012 | #define qlcnic_phy_lock(a) \ | |
1013 | qlcnic_pcie_sem_lock((a), 3, QLCNIC_PHY_LOCK_ID) | |
1014 | #define qlcnic_phy_unlock(a) \ | |
1015 | qlcnic_pcie_sem_unlock((a), 3) | |
1016 | #define qlcnic_api_lock(a) \ | |
1017 | qlcnic_pcie_sem_lock((a), 5, 0) | |
1018 | #define qlcnic_api_unlock(a) \ | |
1019 | qlcnic_pcie_sem_unlock((a), 5) | |
1020 | #define qlcnic_sw_lock(a) \ | |
1021 | qlcnic_pcie_sem_lock((a), 6, 0) | |
1022 | #define qlcnic_sw_unlock(a) \ | |
1023 | qlcnic_pcie_sem_unlock((a), 6) | |
1024 | #define crb_win_lock(a) \ | |
1025 | qlcnic_pcie_sem_lock((a), 7, QLCNIC_CRB_WIN_LOCK_ID) | |
1026 | #define crb_win_unlock(a) \ | |
1027 | qlcnic_pcie_sem_unlock((a), 7) | |
1028 | ||
1029 | int qlcnic_get_board_info(struct qlcnic_adapter *adapter); | |
1030 | int qlcnic_wol_supported(struct qlcnic_adapter *adapter); | |
897d3596 | 1031 | int qlcnic_config_led(struct qlcnic_adapter *adapter, u32 state, u32 rate); |
af19b491 AKS |
1032 | |
1033 | /* Functions from qlcnic_init.c */ | |
1034 | int qlcnic_phantom_init(struct qlcnic_adapter *adapter); | |
1035 | int qlcnic_load_firmware(struct qlcnic_adapter *adapter); | |
1036 | int qlcnic_need_fw_reset(struct qlcnic_adapter *adapter); | |
1037 | void qlcnic_request_firmware(struct qlcnic_adapter *adapter); | |
1038 | void qlcnic_release_firmware(struct qlcnic_adapter *adapter); | |
1039 | int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter); | |
b3a24649 | 1040 | int qlcnic_setup_idc_param(struct qlcnic_adapter *adapter); |
af19b491 AKS |
1041 | |
1042 | int qlcnic_rom_fast_read(struct qlcnic_adapter *adapter, int addr, int *valp); | |
1043 | int qlcnic_rom_fast_read_words(struct qlcnic_adapter *adapter, int addr, | |
1044 | u8 *bytes, size_t size); | |
1045 | int qlcnic_alloc_sw_resources(struct qlcnic_adapter *adapter); | |
1046 | void qlcnic_free_sw_resources(struct qlcnic_adapter *adapter); | |
1047 | ||
1048 | void __iomem *qlcnic_get_ioaddr(struct qlcnic_adapter *, u32); | |
1049 | ||
1050 | int qlcnic_alloc_hw_resources(struct qlcnic_adapter *adapter); | |
1051 | void qlcnic_free_hw_resources(struct qlcnic_adapter *adapter); | |
1052 | ||
1053 | void qlcnic_release_rx_buffers(struct qlcnic_adapter *adapter); | |
1054 | void qlcnic_release_tx_buffers(struct qlcnic_adapter *adapter); | |
1055 | ||
1056 | int qlcnic_init_firmware(struct qlcnic_adapter *adapter); | |
1057 | void qlcnic_watchdog_task(struct work_struct *work); | |
1058 | void qlcnic_post_rx_buffers(struct qlcnic_adapter *adapter, u32 ringid, | |
1059 | struct qlcnic_host_rds_ring *rds_ring); | |
1060 | int qlcnic_process_rcv_ring(struct qlcnic_host_sds_ring *sds_ring, int max); | |
1061 | void qlcnic_set_multi(struct net_device *netdev); | |
1062 | void qlcnic_free_mac_list(struct qlcnic_adapter *adapter); | |
1063 | int qlcnic_nic_set_promisc(struct qlcnic_adapter *adapter, u32); | |
1064 | int qlcnic_config_intr_coalesce(struct qlcnic_adapter *adapter); | |
1065 | int qlcnic_config_rss(struct qlcnic_adapter *adapter, int enable); | |
1066 | int qlcnic_config_ipaddr(struct qlcnic_adapter *adapter, u32 ip, int cmd); | |
1067 | int qlcnic_linkevent_request(struct qlcnic_adapter *adapter, int enable); | |
1068 | void qlcnic_advert_link_change(struct qlcnic_adapter *adapter, int linkup); | |
1069 | ||
1070 | int qlcnic_fw_cmd_set_mtu(struct qlcnic_adapter *adapter, int mtu); | |
1071 | int qlcnic_change_mtu(struct net_device *netdev, int new_mtu); | |
1072 | int qlcnic_config_hw_lro(struct qlcnic_adapter *adapter, int enable); | |
1073 | int qlcnic_config_bridged_mode(struct qlcnic_adapter *adapter, int enable); | |
1074 | int qlcnic_send_lro_cleanup(struct qlcnic_adapter *adapter); | |
1075 | void qlcnic_update_cmd_producer(struct qlcnic_adapter *adapter, | |
1076 | struct qlcnic_host_tx_ring *tx_ring); | |
1077 | int qlcnic_get_mac_addr(struct qlcnic_adapter *adapter, u64 *mac); | |
cdaff185 AKS |
1078 | void qlcnic_clear_ilb_mode(struct qlcnic_adapter *adapter); |
1079 | int qlcnic_set_ilb_mode(struct qlcnic_adapter *adapter); | |
af19b491 AKS |
1080 | |
1081 | /* Functions from qlcnic_main.c */ | |
1082 | int qlcnic_reset_context(struct qlcnic_adapter *); | |
7eb9855d AKS |
1083 | u32 qlcnic_issue_cmd(struct qlcnic_adapter *adapter, |
1084 | u32 pci_fn, u32 version, u32 arg1, u32 arg2, u32 arg3, u32 cmd); | |
1085 | void qlcnic_diag_free_res(struct net_device *netdev, int max_sds_rings); | |
1086 | int qlcnic_diag_alloc_res(struct net_device *netdev, int test); | |
cdaff185 AKS |
1087 | int qlcnic_check_loopback_buff(unsigned char *data); |
1088 | netdev_tx_t qlcnic_xmit_frame(struct sk_buff *skb, struct net_device *netdev); | |
1089 | void qlcnic_process_rcv_ring_diag(struct qlcnic_host_sds_ring *sds_ring); | |
af19b491 AKS |
1090 | |
1091 | /* | |
1092 | * QLOGIC Board information | |
1093 | */ | |
1094 | ||
02420be6 | 1095 | #define QLCNIC_MAX_BOARD_NAME_LEN 100 |
af19b491 AKS |
1096 | struct qlcnic_brdinfo { |
1097 | unsigned short vendor; | |
1098 | unsigned short device; | |
1099 | unsigned short sub_vendor; | |
1100 | unsigned short sub_device; | |
1101 | char short_name[QLCNIC_MAX_BOARD_NAME_LEN]; | |
1102 | }; | |
1103 | ||
1104 | static const struct qlcnic_brdinfo qlcnic_boards[] = { | |
02420be6 | 1105 | {0x1077, 0x8020, 0x1077, 0x203, |
1515faf2 AKS |
1106 | "8200 Series Single Port 10GbE Converged Network Adapter " |
1107 | "(TCP/IP Networking)"}, | |
02420be6 | 1108 | {0x1077, 0x8020, 0x1077, 0x207, |
1515faf2 AKS |
1109 | "8200 Series Dual Port 10GbE Converged Network Adapter " |
1110 | "(TCP/IP Networking)"}, | |
af19b491 AKS |
1111 | {0x1077, 0x8020, 0x1077, 0x20b, |
1112 | "3200 Series Dual Port 10Gb Intelligent Ethernet Adapter"}, | |
1113 | {0x1077, 0x8020, 0x1077, 0x20c, | |
1114 | "3200 Series Quad Port 1Gb Intelligent Ethernet Adapter"}, | |
1115 | {0x1077, 0x8020, 0x1077, 0x20f, | |
1116 | "3200 Series Single Port 10Gb Intelligent Ethernet Adapter"}, | |
1117 | {0x1077, 0x8020, 0x0, 0x0, "cLOM8214 1/10GbE Controller"}, | |
1118 | }; | |
1119 | ||
1120 | #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(qlcnic_boards) | |
1121 | ||
1122 | static inline u32 qlcnic_tx_avail(struct qlcnic_host_tx_ring *tx_ring) | |
1123 | { | |
1124 | smp_mb(); | |
1125 | if (tx_ring->producer < tx_ring->sw_consumer) | |
1126 | return tx_ring->sw_consumer - tx_ring->producer; | |
1127 | else | |
1128 | return tx_ring->sw_consumer + tx_ring->num_desc - | |
1129 | tx_ring->producer; | |
1130 | } | |
1131 | ||
1132 | extern const struct ethtool_ops qlcnic_ethtool_ops; | |
1133 | ||
65b5b420 AKS |
1134 | #define QLCDB(adapter, lvl, _fmt, _args...) do { \ |
1135 | if (NETIF_MSG_##lvl & adapter->msg_enable) \ | |
1136 | printk(KERN_INFO "%s: %s: " _fmt, \ | |
1137 | dev_name(&adapter->pdev->dev), \ | |
1138 | __func__, ##_args); \ | |
1139 | } while (0) | |
1140 | ||
af19b491 | 1141 | #endif /* __QLCNIC_H_ */ |