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Commit | Line | Data |
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5a0e3ad6 TH |
1 | #include <linux/slab.h> |
2 | ||
c4e84bde RM |
3 | #include "qlge.h" |
4 | ||
24bb55b4 RM |
5 | /* Read a NIC register from the alternate function. */ |
6 | static u32 ql_read_other_func_reg(struct ql_adapter *qdev, | |
7 | u32 reg) | |
8 | { | |
9 | u32 register_to_read; | |
10 | u32 reg_val; | |
11 | unsigned int status = 0; | |
12 | ||
13 | register_to_read = MPI_NIC_REG_BLOCK | |
14 | | MPI_NIC_READ | |
15 | | (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT) | |
16 | | reg; | |
17 | status = ql_read_mpi_reg(qdev, register_to_read, ®_val); | |
18 | if (status != 0) | |
19 | return 0xffffffff; | |
20 | ||
21 | return reg_val; | |
22 | } | |
a61f8026 | 23 | |
a48c86fd RM |
24 | /* Write a NIC register from the alternate function. */ |
25 | static int ql_write_other_func_reg(struct ql_adapter *qdev, | |
26 | u32 reg, u32 reg_val) | |
27 | { | |
28 | u32 register_to_read; | |
29 | int status = 0; | |
30 | ||
31 | register_to_read = MPI_NIC_REG_BLOCK | |
32 | | MPI_NIC_READ | |
33 | | (qdev->alt_func << MPI_NIC_FUNCTION_SHIFT) | |
34 | | reg; | |
35 | status = ql_write_mpi_reg(qdev, register_to_read, reg_val); | |
36 | ||
37 | return status; | |
38 | } | |
39 | ||
40 | static int ql_wait_other_func_reg_rdy(struct ql_adapter *qdev, u32 reg, | |
41 | u32 bit, u32 err_bit) | |
42 | { | |
43 | u32 temp; | |
44 | int count = 10; | |
45 | ||
46 | while (count) { | |
47 | temp = ql_read_other_func_reg(qdev, reg); | |
48 | ||
49 | /* check for errors */ | |
50 | if (temp & err_bit) | |
51 | return -1; | |
52 | else if (temp & bit) | |
53 | return 0; | |
54 | mdelay(10); | |
55 | count--; | |
56 | } | |
57 | return -1; | |
58 | } | |
59 | ||
60 | static int ql_read_other_func_serdes_reg(struct ql_adapter *qdev, u32 reg, | |
61 | u32 *data) | |
62 | { | |
63 | int status; | |
64 | ||
65 | /* wait for reg to come ready */ | |
66 | status = ql_wait_other_func_reg_rdy(qdev, XG_SERDES_ADDR / 4, | |
67 | XG_SERDES_ADDR_RDY, 0); | |
68 | if (status) | |
69 | goto exit; | |
70 | ||
71 | /* set up for reg read */ | |
72 | ql_write_other_func_reg(qdev, XG_SERDES_ADDR/4, reg | PROC_ADDR_R); | |
73 | ||
74 | /* wait for reg to come ready */ | |
75 | status = ql_wait_other_func_reg_rdy(qdev, XG_SERDES_ADDR / 4, | |
76 | XG_SERDES_ADDR_RDY, 0); | |
77 | if (status) | |
78 | goto exit; | |
79 | ||
80 | /* get the data */ | |
81 | *data = ql_read_other_func_reg(qdev, (XG_SERDES_DATA / 4)); | |
82 | exit: | |
83 | return status; | |
84 | } | |
85 | ||
86 | /* Read out the SERDES registers */ | |
87 | static int ql_read_serdes_reg(struct ql_adapter *qdev, u32 reg, u32 * data) | |
88 | { | |
89 | int status; | |
90 | ||
91 | /* wait for reg to come ready */ | |
92 | status = ql_wait_reg_rdy(qdev, XG_SERDES_ADDR, XG_SERDES_ADDR_RDY, 0); | |
93 | if (status) | |
94 | goto exit; | |
95 | ||
96 | /* set up for reg read */ | |
97 | ql_write32(qdev, XG_SERDES_ADDR, reg | PROC_ADDR_R); | |
98 | ||
99 | /* wait for reg to come ready */ | |
100 | status = ql_wait_reg_rdy(qdev, XG_SERDES_ADDR, XG_SERDES_ADDR_RDY, 0); | |
101 | if (status) | |
102 | goto exit; | |
103 | ||
104 | /* get the data */ | |
105 | *data = ql_read32(qdev, XG_SERDES_DATA); | |
106 | exit: | |
107 | return status; | |
108 | } | |
109 | ||
110 | static void ql_get_both_serdes(struct ql_adapter *qdev, u32 addr, | |
111 | u32 *direct_ptr, u32 *indirect_ptr, | |
112 | unsigned int direct_valid, unsigned int indirect_valid) | |
113 | { | |
114 | unsigned int status; | |
115 | ||
116 | status = 1; | |
117 | if (direct_valid) | |
118 | status = ql_read_serdes_reg(qdev, addr, direct_ptr); | |
119 | /* Dead fill any failures or invalids. */ | |
120 | if (status) | |
121 | *direct_ptr = 0xDEADBEEF; | |
122 | ||
123 | status = 1; | |
124 | if (indirect_valid) | |
125 | status = ql_read_other_func_serdes_reg( | |
126 | qdev, addr, indirect_ptr); | |
127 | /* Dead fill any failures or invalids. */ | |
128 | if (status) | |
129 | *indirect_ptr = 0xDEADBEEF; | |
130 | } | |
131 | ||
132 | static int ql_get_serdes_regs(struct ql_adapter *qdev, | |
133 | struct ql_mpi_coredump *mpi_coredump) | |
134 | { | |
135 | int status; | |
136 | unsigned int xfi_direct_valid, xfi_indirect_valid, xaui_direct_valid; | |
137 | unsigned int xaui_indirect_valid, i; | |
138 | u32 *direct_ptr, temp; | |
139 | u32 *indirect_ptr; | |
140 | ||
141 | xfi_direct_valid = xfi_indirect_valid = 0; | |
142 | xaui_direct_valid = xaui_indirect_valid = 1; | |
143 | ||
144 | /* The XAUI needs to be read out per port */ | |
145 | if (qdev->func & 1) { | |
146 | /* We are NIC 2 */ | |
147 | status = ql_read_other_func_serdes_reg(qdev, | |
148 | XG_SERDES_XAUI_HSS_PCS_START, &temp); | |
149 | if (status) | |
150 | temp = XG_SERDES_ADDR_XAUI_PWR_DOWN; | |
151 | if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) == | |
152 | XG_SERDES_ADDR_XAUI_PWR_DOWN) | |
153 | xaui_indirect_valid = 0; | |
154 | ||
155 | status = ql_read_serdes_reg(qdev, | |
156 | XG_SERDES_XAUI_HSS_PCS_START, &temp); | |
157 | if (status) | |
158 | temp = XG_SERDES_ADDR_XAUI_PWR_DOWN; | |
159 | ||
160 | if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) == | |
161 | XG_SERDES_ADDR_XAUI_PWR_DOWN) | |
162 | xaui_direct_valid = 0; | |
163 | } else { | |
164 | /* We are NIC 1 */ | |
165 | status = ql_read_other_func_serdes_reg(qdev, | |
166 | XG_SERDES_XAUI_HSS_PCS_START, &temp); | |
167 | if (status) | |
168 | temp = XG_SERDES_ADDR_XAUI_PWR_DOWN; | |
169 | if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) == | |
170 | XG_SERDES_ADDR_XAUI_PWR_DOWN) | |
171 | xaui_indirect_valid = 0; | |
172 | ||
173 | status = ql_read_serdes_reg(qdev, | |
174 | XG_SERDES_XAUI_HSS_PCS_START, &temp); | |
175 | if (status) | |
176 | temp = XG_SERDES_ADDR_XAUI_PWR_DOWN; | |
177 | if ((temp & XG_SERDES_ADDR_XAUI_PWR_DOWN) == | |
178 | XG_SERDES_ADDR_XAUI_PWR_DOWN) | |
179 | xaui_direct_valid = 0; | |
180 | } | |
181 | ||
182 | /* | |
183 | * XFI register is shared so only need to read one | |
184 | * functions and then check the bits. | |
185 | */ | |
186 | status = ql_read_serdes_reg(qdev, XG_SERDES_ADDR_STS, &temp); | |
187 | if (status) | |
188 | temp = 0; | |
189 | ||
190 | if ((temp & XG_SERDES_ADDR_XFI1_PWR_UP) == | |
191 | XG_SERDES_ADDR_XFI1_PWR_UP) { | |
192 | /* now see if i'm NIC 1 or NIC 2 */ | |
193 | if (qdev->func & 1) | |
194 | /* I'm NIC 2, so the indirect (NIC1) xfi is up. */ | |
195 | xfi_indirect_valid = 1; | |
196 | else | |
197 | xfi_direct_valid = 1; | |
198 | } | |
199 | if ((temp & XG_SERDES_ADDR_XFI2_PWR_UP) == | |
200 | XG_SERDES_ADDR_XFI2_PWR_UP) { | |
201 | /* now see if i'm NIC 1 or NIC 2 */ | |
202 | if (qdev->func & 1) | |
203 | /* I'm NIC 2, so the indirect (NIC1) xfi is up. */ | |
204 | xfi_direct_valid = 1; | |
205 | else | |
206 | xfi_indirect_valid = 1; | |
207 | } | |
208 | ||
209 | /* Get XAUI_AN register block. */ | |
210 | if (qdev->func & 1) { | |
211 | /* Function 2 is direct */ | |
212 | direct_ptr = mpi_coredump->serdes2_xaui_an; | |
213 | indirect_ptr = mpi_coredump->serdes_xaui_an; | |
214 | } else { | |
215 | /* Function 1 is direct */ | |
216 | direct_ptr = mpi_coredump->serdes_xaui_an; | |
217 | indirect_ptr = mpi_coredump->serdes2_xaui_an; | |
218 | } | |
219 | ||
220 | for (i = 0; i <= 0x000000034; i += 4, direct_ptr++, indirect_ptr++) | |
221 | ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr, | |
222 | xaui_direct_valid, xaui_indirect_valid); | |
223 | ||
224 | /* Get XAUI_HSS_PCS register block. */ | |
225 | if (qdev->func & 1) { | |
226 | direct_ptr = | |
227 | mpi_coredump->serdes2_xaui_hss_pcs; | |
228 | indirect_ptr = | |
229 | mpi_coredump->serdes_xaui_hss_pcs; | |
230 | } else { | |
231 | direct_ptr = | |
232 | mpi_coredump->serdes_xaui_hss_pcs; | |
233 | indirect_ptr = | |
234 | mpi_coredump->serdes2_xaui_hss_pcs; | |
235 | } | |
236 | ||
237 | for (i = 0x800; i <= 0x880; i += 4, direct_ptr++, indirect_ptr++) | |
238 | ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr, | |
239 | xaui_direct_valid, xaui_indirect_valid); | |
240 | ||
241 | /* Get XAUI_XFI_AN register block. */ | |
242 | if (qdev->func & 1) { | |
243 | direct_ptr = mpi_coredump->serdes2_xfi_an; | |
244 | indirect_ptr = mpi_coredump->serdes_xfi_an; | |
245 | } else { | |
246 | direct_ptr = mpi_coredump->serdes_xfi_an; | |
247 | indirect_ptr = mpi_coredump->serdes2_xfi_an; | |
248 | } | |
249 | ||
250 | for (i = 0x1000; i <= 0x1034; i += 4, direct_ptr++, indirect_ptr++) | |
251 | ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr, | |
252 | xfi_direct_valid, xfi_indirect_valid); | |
253 | ||
254 | /* Get XAUI_XFI_TRAIN register block. */ | |
255 | if (qdev->func & 1) { | |
256 | direct_ptr = mpi_coredump->serdes2_xfi_train; | |
257 | indirect_ptr = | |
258 | mpi_coredump->serdes_xfi_train; | |
259 | } else { | |
260 | direct_ptr = mpi_coredump->serdes_xfi_train; | |
261 | indirect_ptr = | |
262 | mpi_coredump->serdes2_xfi_train; | |
263 | } | |
264 | ||
265 | for (i = 0x1050; i <= 0x107c; i += 4, direct_ptr++, indirect_ptr++) | |
266 | ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr, | |
267 | xfi_direct_valid, xfi_indirect_valid); | |
268 | ||
269 | /* Get XAUI_XFI_HSS_PCS register block. */ | |
270 | if (qdev->func & 1) { | |
271 | direct_ptr = | |
272 | mpi_coredump->serdes2_xfi_hss_pcs; | |
273 | indirect_ptr = | |
274 | mpi_coredump->serdes_xfi_hss_pcs; | |
275 | } else { | |
276 | direct_ptr = | |
277 | mpi_coredump->serdes_xfi_hss_pcs; | |
278 | indirect_ptr = | |
279 | mpi_coredump->serdes2_xfi_hss_pcs; | |
280 | } | |
281 | ||
282 | for (i = 0x1800; i <= 0x1838; i += 4, direct_ptr++, indirect_ptr++) | |
283 | ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr, | |
284 | xfi_direct_valid, xfi_indirect_valid); | |
285 | ||
286 | /* Get XAUI_XFI_HSS_TX register block. */ | |
287 | if (qdev->func & 1) { | |
288 | direct_ptr = | |
289 | mpi_coredump->serdes2_xfi_hss_tx; | |
290 | indirect_ptr = | |
291 | mpi_coredump->serdes_xfi_hss_tx; | |
292 | } else { | |
293 | direct_ptr = mpi_coredump->serdes_xfi_hss_tx; | |
294 | indirect_ptr = | |
295 | mpi_coredump->serdes2_xfi_hss_tx; | |
296 | } | |
297 | for (i = 0x1c00; i <= 0x1c1f; i++, direct_ptr++, indirect_ptr++) | |
298 | ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr, | |
299 | xfi_direct_valid, xfi_indirect_valid); | |
300 | ||
301 | /* Get XAUI_XFI_HSS_RX register block. */ | |
302 | if (qdev->func & 1) { | |
303 | direct_ptr = | |
304 | mpi_coredump->serdes2_xfi_hss_rx; | |
305 | indirect_ptr = | |
306 | mpi_coredump->serdes_xfi_hss_rx; | |
307 | } else { | |
308 | direct_ptr = mpi_coredump->serdes_xfi_hss_rx; | |
309 | indirect_ptr = | |
310 | mpi_coredump->serdes2_xfi_hss_rx; | |
311 | } | |
312 | ||
313 | for (i = 0x1c40; i <= 0x1c5f; i++, direct_ptr++, indirect_ptr++) | |
314 | ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr, | |
315 | xfi_direct_valid, xfi_indirect_valid); | |
316 | ||
317 | ||
318 | /* Get XAUI_XFI_HSS_PLL register block. */ | |
319 | if (qdev->func & 1) { | |
320 | direct_ptr = | |
321 | mpi_coredump->serdes2_xfi_hss_pll; | |
322 | indirect_ptr = | |
323 | mpi_coredump->serdes_xfi_hss_pll; | |
324 | } else { | |
325 | direct_ptr = | |
326 | mpi_coredump->serdes_xfi_hss_pll; | |
327 | indirect_ptr = | |
328 | mpi_coredump->serdes2_xfi_hss_pll; | |
329 | } | |
330 | for (i = 0x1e00; i <= 0x1e1f; i++, direct_ptr++, indirect_ptr++) | |
331 | ql_get_both_serdes(qdev, i, direct_ptr, indirect_ptr, | |
332 | xfi_direct_valid, xfi_indirect_valid); | |
333 | return 0; | |
334 | } | |
335 | ||
a2f98232 RM |
336 | static int ql_read_other_func_xgmac_reg(struct ql_adapter *qdev, u32 reg, |
337 | u32 *data) | |
338 | { | |
339 | int status = 0; | |
340 | ||
341 | /* wait for reg to come ready */ | |
342 | status = ql_wait_other_func_reg_rdy(qdev, XGMAC_ADDR / 4, | |
343 | XGMAC_ADDR_RDY, XGMAC_ADDR_XME); | |
344 | if (status) | |
345 | goto exit; | |
346 | ||
347 | /* set up for reg read */ | |
348 | ql_write_other_func_reg(qdev, XGMAC_ADDR / 4, reg | XGMAC_ADDR_R); | |
349 | ||
350 | /* wait for reg to come ready */ | |
351 | status = ql_wait_other_func_reg_rdy(qdev, XGMAC_ADDR / 4, | |
352 | XGMAC_ADDR_RDY, XGMAC_ADDR_XME); | |
353 | if (status) | |
354 | goto exit; | |
355 | ||
356 | /* get the data */ | |
357 | *data = ql_read_other_func_reg(qdev, XGMAC_DATA / 4); | |
358 | exit: | |
359 | return status; | |
360 | } | |
361 | ||
362 | /* Read the 400 xgmac control/statistics registers | |
363 | * skipping unused locations. | |
364 | */ | |
365 | static int ql_get_xgmac_regs(struct ql_adapter *qdev, u32 * buf, | |
366 | unsigned int other_function) | |
367 | { | |
368 | int status = 0; | |
369 | int i; | |
370 | ||
371 | for (i = PAUSE_SRC_LO; i < XGMAC_REGISTER_END; i += 4, buf++) { | |
372 | /* We're reading 400 xgmac registers, but we filter out | |
373 | * serveral locations that are non-responsive to reads. | |
374 | */ | |
375 | if ((i == 0x00000114) || | |
376 | (i == 0x00000118) || | |
377 | (i == 0x0000013c) || | |
378 | (i == 0x00000140) || | |
379 | (i > 0x00000150 && i < 0x000001fc) || | |
380 | (i > 0x00000278 && i < 0x000002a0) || | |
381 | (i > 0x000002c0 && i < 0x000002cf) || | |
382 | (i > 0x000002dc && i < 0x000002f0) || | |
383 | (i > 0x000003c8 && i < 0x00000400) || | |
384 | (i > 0x00000400 && i < 0x00000410) || | |
385 | (i > 0x00000410 && i < 0x00000420) || | |
386 | (i > 0x00000420 && i < 0x00000430) || | |
387 | (i > 0x00000430 && i < 0x00000440) || | |
388 | (i > 0x00000440 && i < 0x00000450) || | |
389 | (i > 0x00000450 && i < 0x00000500) || | |
390 | (i > 0x0000054c && i < 0x00000568) || | |
391 | (i > 0x000005c8 && i < 0x00000600)) { | |
392 | if (other_function) | |
393 | status = | |
394 | ql_read_other_func_xgmac_reg(qdev, i, buf); | |
395 | else | |
396 | status = ql_read_xgmac_reg(qdev, i, buf); | |
397 | ||
398 | if (status) | |
399 | *buf = 0xdeadbeef; | |
400 | break; | |
401 | } | |
402 | } | |
403 | return status; | |
404 | } | |
405 | ||
a61f8026 RM |
406 | static int ql_get_ets_regs(struct ql_adapter *qdev, u32 * buf) |
407 | { | |
408 | int status = 0; | |
409 | int i; | |
410 | ||
411 | for (i = 0; i < 8; i++, buf++) { | |
412 | ql_write32(qdev, NIC_ETS, i << 29 | 0x08000000); | |
413 | *buf = ql_read32(qdev, NIC_ETS); | |
414 | } | |
415 | ||
416 | for (i = 0; i < 2; i++, buf++) { | |
417 | ql_write32(qdev, CNA_ETS, i << 29 | 0x08000000); | |
418 | *buf = ql_read32(qdev, CNA_ETS); | |
419 | } | |
420 | ||
421 | return status; | |
422 | } | |
423 | ||
424 | static void ql_get_intr_states(struct ql_adapter *qdev, u32 * buf) | |
425 | { | |
426 | int i; | |
427 | ||
428 | for (i = 0; i < qdev->rx_ring_count; i++, buf++) { | |
429 | ql_write32(qdev, INTR_EN, | |
430 | qdev->intr_context[i].intr_read_mask); | |
431 | *buf = ql_read32(qdev, INTR_EN); | |
432 | } | |
433 | } | |
434 | ||
435 | static int ql_get_cam_entries(struct ql_adapter *qdev, u32 * buf) | |
436 | { | |
437 | int i, status; | |
438 | u32 value[3]; | |
439 | ||
440 | status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); | |
441 | if (status) | |
442 | return status; | |
443 | ||
444 | for (i = 0; i < 16; i++) { | |
445 | status = ql_get_mac_addr_reg(qdev, | |
446 | MAC_ADDR_TYPE_CAM_MAC, i, value); | |
447 | if (status) { | |
ae9540f7 JP |
448 | netif_err(qdev, drv, qdev->ndev, |
449 | "Failed read of mac index register.\n"); | |
a61f8026 RM |
450 | goto err; |
451 | } | |
452 | *buf++ = value[0]; /* lower MAC address */ | |
453 | *buf++ = value[1]; /* upper MAC address */ | |
454 | *buf++ = value[2]; /* output */ | |
455 | } | |
456 | for (i = 0; i < 32; i++) { | |
457 | status = ql_get_mac_addr_reg(qdev, | |
458 | MAC_ADDR_TYPE_MULTI_MAC, i, value); | |
459 | if (status) { | |
ae9540f7 JP |
460 | netif_err(qdev, drv, qdev->ndev, |
461 | "Failed read of mac index register.\n"); | |
a61f8026 RM |
462 | goto err; |
463 | } | |
464 | *buf++ = value[0]; /* lower Mcast address */ | |
465 | *buf++ = value[1]; /* upper Mcast address */ | |
466 | } | |
467 | err: | |
468 | ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); | |
469 | return status; | |
470 | } | |
471 | ||
472 | static int ql_get_routing_entries(struct ql_adapter *qdev, u32 * buf) | |
473 | { | |
474 | int status; | |
475 | u32 value, i; | |
476 | ||
477 | status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); | |
478 | if (status) | |
479 | return status; | |
480 | ||
481 | for (i = 0; i < 16; i++) { | |
482 | status = ql_get_routing_reg(qdev, i, &value); | |
483 | if (status) { | |
ae9540f7 JP |
484 | netif_err(qdev, drv, qdev->ndev, |
485 | "Failed read of routing index register.\n"); | |
a61f8026 RM |
486 | goto err; |
487 | } else { | |
488 | *buf++ = value; | |
489 | } | |
490 | } | |
491 | err: | |
492 | ql_sem_unlock(qdev, SEM_RT_IDX_MASK); | |
493 | return status; | |
494 | } | |
495 | ||
8aae2600 RM |
496 | /* Read the MPI Processor shadow registers */ |
497 | static int ql_get_mpi_shadow_regs(struct ql_adapter *qdev, u32 * buf) | |
498 | { | |
499 | u32 i; | |
500 | int status; | |
501 | ||
502 | for (i = 0; i < MPI_CORE_SH_REGS_CNT; i++, buf++) { | |
503 | status = ql_write_mpi_reg(qdev, RISC_124, | |
504 | (SHADOW_OFFSET | i << SHADOW_REG_SHIFT)); | |
505 | if (status) | |
506 | goto end; | |
507 | status = ql_read_mpi_reg(qdev, RISC_127, buf); | |
508 | if (status) | |
509 | goto end; | |
510 | } | |
511 | end: | |
512 | return status; | |
513 | } | |
514 | ||
515 | /* Read the MPI Processor core registers */ | |
516 | static int ql_get_mpi_regs(struct ql_adapter *qdev, u32 * buf, | |
517 | u32 offset, u32 count) | |
518 | { | |
519 | int i, status = 0; | |
520 | for (i = 0; i < count; i++, buf++) { | |
521 | status = ql_read_mpi_reg(qdev, offset + i, buf); | |
522 | if (status) | |
523 | return status; | |
524 | } | |
525 | return status; | |
526 | } | |
527 | ||
c89ec8b9 RM |
528 | /* Read the ASIC probe dump */ |
529 | static unsigned int *ql_get_probe(struct ql_adapter *qdev, u32 clock, | |
530 | u32 valid, u32 *buf) | |
531 | { | |
532 | u32 module, mux_sel, probe, lo_val, hi_val; | |
533 | ||
534 | for (module = 0; module < PRB_MX_ADDR_MAX_MODS; module++) { | |
535 | if (!((valid >> module) & 1)) | |
536 | continue; | |
537 | for (mux_sel = 0; mux_sel < PRB_MX_ADDR_MAX_MUX; mux_sel++) { | |
538 | probe = clock | |
539 | | PRB_MX_ADDR_ARE | |
540 | | mux_sel | |
541 | | (module << PRB_MX_ADDR_MOD_SEL_SHIFT); | |
542 | ql_write32(qdev, PRB_MX_ADDR, probe); | |
543 | lo_val = ql_read32(qdev, PRB_MX_DATA); | |
544 | if (mux_sel == 0) { | |
545 | *buf = probe; | |
546 | buf++; | |
547 | } | |
548 | probe |= PRB_MX_ADDR_UP; | |
549 | ql_write32(qdev, PRB_MX_ADDR, probe); | |
550 | hi_val = ql_read32(qdev, PRB_MX_DATA); | |
551 | *buf = lo_val; | |
552 | buf++; | |
553 | *buf = hi_val; | |
554 | buf++; | |
555 | } | |
556 | } | |
557 | return buf; | |
558 | } | |
559 | ||
560 | static int ql_get_probe_dump(struct ql_adapter *qdev, unsigned int *buf) | |
561 | { | |
562 | /* First we have to enable the probe mux */ | |
563 | ql_write_mpi_reg(qdev, MPI_TEST_FUNC_PRB_CTL, MPI_TEST_FUNC_PRB_EN); | |
564 | buf = ql_get_probe(qdev, PRB_MX_ADDR_SYS_CLOCK, | |
565 | PRB_MX_ADDR_VALID_SYS_MOD, buf); | |
566 | buf = ql_get_probe(qdev, PRB_MX_ADDR_PCI_CLOCK, | |
567 | PRB_MX_ADDR_VALID_PCI_MOD, buf); | |
568 | buf = ql_get_probe(qdev, PRB_MX_ADDR_XGM_CLOCK, | |
569 | PRB_MX_ADDR_VALID_XGM_MOD, buf); | |
570 | buf = ql_get_probe(qdev, PRB_MX_ADDR_FC_CLOCK, | |
571 | PRB_MX_ADDR_VALID_FC_MOD, buf); | |
572 | return 0; | |
573 | ||
574 | } | |
8aae2600 RM |
575 | |
576 | /* Read out the routing index registers */ | |
577 | static int ql_get_routing_index_registers(struct ql_adapter *qdev, u32 *buf) | |
578 | { | |
579 | int status; | |
580 | u32 type, index, index_max; | |
581 | u32 result_index; | |
582 | u32 result_data; | |
583 | u32 val; | |
584 | ||
585 | status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); | |
586 | if (status) | |
587 | return status; | |
588 | ||
589 | for (type = 0; type < 4; type++) { | |
590 | if (type < 2) | |
591 | index_max = 8; | |
592 | else | |
593 | index_max = 16; | |
594 | for (index = 0; index < index_max; index++) { | |
595 | val = RT_IDX_RS | |
596 | | (type << RT_IDX_TYPE_SHIFT) | |
597 | | (index << RT_IDX_IDX_SHIFT); | |
598 | ql_write32(qdev, RT_IDX, val); | |
599 | result_index = 0; | |
600 | while ((result_index & RT_IDX_MR) == 0) | |
601 | result_index = ql_read32(qdev, RT_IDX); | |
602 | result_data = ql_read32(qdev, RT_DATA); | |
603 | *buf = type; | |
604 | buf++; | |
605 | *buf = index; | |
606 | buf++; | |
607 | *buf = result_index; | |
608 | buf++; | |
609 | *buf = result_data; | |
610 | buf++; | |
611 | } | |
612 | } | |
613 | ql_sem_unlock(qdev, SEM_RT_IDX_MASK); | |
614 | return status; | |
615 | } | |
616 | ||
617 | /* Read out the MAC protocol registers */ | |
618 | static void ql_get_mac_protocol_registers(struct ql_adapter *qdev, u32 *buf) | |
619 | { | |
620 | u32 result_index, result_data; | |
621 | u32 type; | |
622 | u32 index; | |
623 | u32 offset; | |
624 | u32 val; | |
625 | u32 initial_val = MAC_ADDR_RS; | |
626 | u32 max_index; | |
627 | u32 max_offset; | |
628 | ||
629 | for (type = 0; type < MAC_ADDR_TYPE_COUNT; type++) { | |
630 | switch (type) { | |
631 | ||
632 | case 0: /* CAM */ | |
633 | initial_val |= MAC_ADDR_ADR; | |
634 | max_index = MAC_ADDR_MAX_CAM_ENTRIES; | |
635 | max_offset = MAC_ADDR_MAX_CAM_WCOUNT; | |
636 | break; | |
637 | case 1: /* Multicast MAC Address */ | |
638 | max_index = MAC_ADDR_MAX_CAM_WCOUNT; | |
639 | max_offset = MAC_ADDR_MAX_CAM_WCOUNT; | |
640 | break; | |
641 | case 2: /* VLAN filter mask */ | |
642 | case 3: /* MC filter mask */ | |
643 | max_index = MAC_ADDR_MAX_CAM_WCOUNT; | |
644 | max_offset = MAC_ADDR_MAX_CAM_WCOUNT; | |
645 | break; | |
646 | case 4: /* FC MAC addresses */ | |
647 | max_index = MAC_ADDR_MAX_FC_MAC_ENTRIES; | |
648 | max_offset = MAC_ADDR_MAX_FC_MAC_WCOUNT; | |
649 | break; | |
650 | case 5: /* Mgmt MAC addresses */ | |
651 | max_index = MAC_ADDR_MAX_MGMT_MAC_ENTRIES; | |
652 | max_offset = MAC_ADDR_MAX_MGMT_MAC_WCOUNT; | |
653 | break; | |
654 | case 6: /* Mgmt VLAN addresses */ | |
655 | max_index = MAC_ADDR_MAX_MGMT_VLAN_ENTRIES; | |
656 | max_offset = MAC_ADDR_MAX_MGMT_VLAN_WCOUNT; | |
657 | break; | |
658 | case 7: /* Mgmt IPv4 address */ | |
659 | max_index = MAC_ADDR_MAX_MGMT_V4_ENTRIES; | |
660 | max_offset = MAC_ADDR_MAX_MGMT_V4_WCOUNT; | |
661 | break; | |
662 | case 8: /* Mgmt IPv6 address */ | |
663 | max_index = MAC_ADDR_MAX_MGMT_V6_ENTRIES; | |
664 | max_offset = MAC_ADDR_MAX_MGMT_V6_WCOUNT; | |
665 | break; | |
666 | case 9: /* Mgmt TCP/UDP Dest port */ | |
667 | max_index = MAC_ADDR_MAX_MGMT_TU_DP_ENTRIES; | |
668 | max_offset = MAC_ADDR_MAX_MGMT_TU_DP_WCOUNT; | |
669 | break; | |
670 | default: | |
671 | printk(KERN_ERR"Bad type!!! 0x%08x\n", type); | |
672 | max_index = 0; | |
673 | max_offset = 0; | |
674 | break; | |
675 | } | |
676 | for (index = 0; index < max_index; index++) { | |
677 | for (offset = 0; offset < max_offset; offset++) { | |
678 | val = initial_val | |
679 | | (type << MAC_ADDR_TYPE_SHIFT) | |
680 | | (index << MAC_ADDR_IDX_SHIFT) | |
681 | | (offset); | |
682 | ql_write32(qdev, MAC_ADDR_IDX, val); | |
683 | result_index = 0; | |
684 | while ((result_index & MAC_ADDR_MR) == 0) { | |
685 | result_index = ql_read32(qdev, | |
686 | MAC_ADDR_IDX); | |
687 | } | |
688 | result_data = ql_read32(qdev, MAC_ADDR_DATA); | |
689 | *buf = result_index; | |
690 | buf++; | |
691 | *buf = result_data; | |
692 | buf++; | |
693 | } | |
694 | } | |
695 | } | |
696 | } | |
697 | ||
698 | static void ql_get_sem_registers(struct ql_adapter *qdev, u32 *buf) | |
699 | { | |
700 | u32 func_num, reg, reg_val; | |
701 | int status; | |
702 | ||
703 | for (func_num = 0; func_num < MAX_SEMAPHORE_FUNCTIONS ; func_num++) { | |
704 | reg = MPI_NIC_REG_BLOCK | |
705 | | (func_num << MPI_NIC_FUNCTION_SHIFT) | |
706 | | (SEM / 4); | |
707 | status = ql_read_mpi_reg(qdev, reg, ®_val); | |
708 | *buf = reg_val; | |
709 | /* if the read failed then dead fill the element. */ | |
710 | if (!status) | |
711 | *buf = 0xdeadbeef; | |
712 | buf++; | |
713 | } | |
714 | } | |
715 | ||
a61f8026 RM |
716 | /* Create a coredump segment header */ |
717 | static void ql_build_coredump_seg_header( | |
718 | struct mpi_coredump_segment_header *seg_hdr, | |
719 | u32 seg_number, u32 seg_size, u8 *desc) | |
720 | { | |
721 | memset(seg_hdr, 0, sizeof(struct mpi_coredump_segment_header)); | |
722 | seg_hdr->cookie = MPI_COREDUMP_COOKIE; | |
723 | seg_hdr->segNum = seg_number; | |
724 | seg_hdr->segSize = seg_size; | |
725 | memcpy(seg_hdr->description, desc, (sizeof(seg_hdr->description)) - 1); | |
726 | } | |
727 | ||
8aae2600 RM |
728 | /* |
729 | * This function should be called when a coredump / probedump | |
730 | * is to be extracted from the HBA. It is assumed there is a | |
731 | * qdev structure that contains the base address of the register | |
732 | * space for this function as well as a coredump structure that | |
733 | * will contain the dump. | |
734 | */ | |
735 | int ql_core_dump(struct ql_adapter *qdev, struct ql_mpi_coredump *mpi_coredump) | |
736 | { | |
737 | int status; | |
738 | int i; | |
739 | ||
740 | if (!mpi_coredump) { | |
ae9540f7 | 741 | netif_err(qdev, drv, qdev->ndev, "No memory available.\n"); |
8aae2600 RM |
742 | return -ENOMEM; |
743 | } | |
744 | ||
745 | /* Try to get the spinlock, but dont worry if | |
746 | * it isn't available. If the firmware died it | |
747 | * might be holding the sem. | |
748 | */ | |
749 | ql_sem_spinlock(qdev, SEM_PROC_REG_MASK); | |
750 | ||
751 | status = ql_pause_mpi_risc(qdev); | |
752 | if (status) { | |
ae9540f7 JP |
753 | netif_err(qdev, drv, qdev->ndev, |
754 | "Failed RISC pause. Status = 0x%.08x\n", status); | |
8aae2600 RM |
755 | goto err; |
756 | } | |
757 | ||
758 | /* Insert the global header */ | |
759 | memset(&(mpi_coredump->mpi_global_header), 0, | |
760 | sizeof(struct mpi_coredump_global_header)); | |
761 | mpi_coredump->mpi_global_header.cookie = MPI_COREDUMP_COOKIE; | |
762 | mpi_coredump->mpi_global_header.headerSize = | |
763 | sizeof(struct mpi_coredump_global_header); | |
764 | mpi_coredump->mpi_global_header.imageSize = | |
765 | sizeof(struct ql_mpi_coredump); | |
766 | memcpy(mpi_coredump->mpi_global_header.idString, "MPI Coredump", | |
767 | sizeof(mpi_coredump->mpi_global_header.idString)); | |
768 | ||
769 | /* Get generic NIC reg dump */ | |
770 | ql_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr, | |
771 | NIC1_CONTROL_SEG_NUM, | |
772 | sizeof(struct mpi_coredump_segment_header) + | |
773 | sizeof(mpi_coredump->nic_regs), "NIC1 Registers"); | |
774 | ||
24bb55b4 RM |
775 | ql_build_coredump_seg_header(&mpi_coredump->nic2_regs_seg_hdr, |
776 | NIC2_CONTROL_SEG_NUM, | |
777 | sizeof(struct mpi_coredump_segment_header) + | |
778 | sizeof(mpi_coredump->nic2_regs), "NIC2 Registers"); | |
779 | ||
a2f98232 RM |
780 | /* Get XGMac registers. (Segment 18, Rev C. step 21) */ |
781 | ql_build_coredump_seg_header(&mpi_coredump->xgmac1_seg_hdr, | |
782 | NIC1_XGMAC_SEG_NUM, | |
783 | sizeof(struct mpi_coredump_segment_header) + | |
784 | sizeof(mpi_coredump->xgmac1), "NIC1 XGMac Registers"); | |
785 | ||
786 | ql_build_coredump_seg_header(&mpi_coredump->xgmac2_seg_hdr, | |
787 | NIC2_XGMAC_SEG_NUM, | |
788 | sizeof(struct mpi_coredump_segment_header) + | |
789 | sizeof(mpi_coredump->xgmac2), "NIC2 XGMac Registers"); | |
790 | ||
8aae2600 RM |
791 | if (qdev->func & 1) { |
792 | /* Odd means our function is NIC 2 */ | |
793 | for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++) | |
794 | mpi_coredump->nic2_regs[i] = | |
795 | ql_read32(qdev, i * sizeof(u32)); | |
24bb55b4 RM |
796 | |
797 | for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++) | |
798 | mpi_coredump->nic_regs[i] = | |
799 | ql_read_other_func_reg(qdev, (i * sizeof(u32)) / 4); | |
a2f98232 RM |
800 | |
801 | ql_get_xgmac_regs(qdev, &mpi_coredump->xgmac2[0], 0); | |
802 | ql_get_xgmac_regs(qdev, &mpi_coredump->xgmac1[0], 1); | |
8aae2600 RM |
803 | } else { |
804 | /* Even means our function is NIC 1 */ | |
805 | for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++) | |
806 | mpi_coredump->nic_regs[i] = | |
807 | ql_read32(qdev, i * sizeof(u32)); | |
24bb55b4 RM |
808 | for (i = 0; i < NIC_REGS_DUMP_WORD_COUNT; i++) |
809 | mpi_coredump->nic2_regs[i] = | |
810 | ql_read_other_func_reg(qdev, (i * sizeof(u32)) / 4); | |
a2f98232 RM |
811 | |
812 | ql_get_xgmac_regs(qdev, &mpi_coredump->xgmac1[0], 0); | |
813 | ql_get_xgmac_regs(qdev, &mpi_coredump->xgmac2[0], 1); | |
8aae2600 RM |
814 | } |
815 | ||
a48c86fd RM |
816 | /* Rev C. Step 20a */ |
817 | ql_build_coredump_seg_header(&mpi_coredump->xaui_an_hdr, | |
818 | XAUI_AN_SEG_NUM, | |
819 | sizeof(struct mpi_coredump_segment_header) + | |
820 | sizeof(mpi_coredump->serdes_xaui_an), | |
821 | "XAUI AN Registers"); | |
822 | ||
823 | /* Rev C. Step 20b */ | |
824 | ql_build_coredump_seg_header(&mpi_coredump->xaui_hss_pcs_hdr, | |
825 | XAUI_HSS_PCS_SEG_NUM, | |
826 | sizeof(struct mpi_coredump_segment_header) + | |
827 | sizeof(mpi_coredump->serdes_xaui_hss_pcs), | |
828 | "XAUI HSS PCS Registers"); | |
829 | ||
830 | ql_build_coredump_seg_header(&mpi_coredump->xfi_an_hdr, XFI_AN_SEG_NUM, | |
831 | sizeof(struct mpi_coredump_segment_header) + | |
832 | sizeof(mpi_coredump->serdes_xfi_an), | |
833 | "XFI AN Registers"); | |
834 | ||
835 | ql_build_coredump_seg_header(&mpi_coredump->xfi_train_hdr, | |
836 | XFI_TRAIN_SEG_NUM, | |
837 | sizeof(struct mpi_coredump_segment_header) + | |
838 | sizeof(mpi_coredump->serdes_xfi_train), | |
839 | "XFI TRAIN Registers"); | |
840 | ||
841 | ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_pcs_hdr, | |
842 | XFI_HSS_PCS_SEG_NUM, | |
843 | sizeof(struct mpi_coredump_segment_header) + | |
844 | sizeof(mpi_coredump->serdes_xfi_hss_pcs), | |
845 | "XFI HSS PCS Registers"); | |
846 | ||
847 | ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_tx_hdr, | |
848 | XFI_HSS_TX_SEG_NUM, | |
849 | sizeof(struct mpi_coredump_segment_header) + | |
850 | sizeof(mpi_coredump->serdes_xfi_hss_tx), | |
851 | "XFI HSS TX Registers"); | |
852 | ||
853 | ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_rx_hdr, | |
854 | XFI_HSS_RX_SEG_NUM, | |
855 | sizeof(struct mpi_coredump_segment_header) + | |
856 | sizeof(mpi_coredump->serdes_xfi_hss_rx), | |
857 | "XFI HSS RX Registers"); | |
858 | ||
859 | ql_build_coredump_seg_header(&mpi_coredump->xfi_hss_pll_hdr, | |
860 | XFI_HSS_PLL_SEG_NUM, | |
861 | sizeof(struct mpi_coredump_segment_header) + | |
862 | sizeof(mpi_coredump->serdes_xfi_hss_pll), | |
863 | "XFI HSS PLL Registers"); | |
864 | ||
865 | ql_build_coredump_seg_header(&mpi_coredump->xaui2_an_hdr, | |
866 | XAUI2_AN_SEG_NUM, | |
867 | sizeof(struct mpi_coredump_segment_header) + | |
868 | sizeof(mpi_coredump->serdes2_xaui_an), | |
869 | "XAUI2 AN Registers"); | |
870 | ||
871 | ql_build_coredump_seg_header(&mpi_coredump->xaui2_hss_pcs_hdr, | |
872 | XAUI2_HSS_PCS_SEG_NUM, | |
873 | sizeof(struct mpi_coredump_segment_header) + | |
874 | sizeof(mpi_coredump->serdes2_xaui_hss_pcs), | |
875 | "XAUI2 HSS PCS Registers"); | |
876 | ||
877 | ql_build_coredump_seg_header(&mpi_coredump->xfi2_an_hdr, | |
878 | XFI2_AN_SEG_NUM, | |
879 | sizeof(struct mpi_coredump_segment_header) + | |
880 | sizeof(mpi_coredump->serdes2_xfi_an), | |
881 | "XFI2 AN Registers"); | |
882 | ||
883 | ql_build_coredump_seg_header(&mpi_coredump->xfi2_train_hdr, | |
884 | XFI2_TRAIN_SEG_NUM, | |
885 | sizeof(struct mpi_coredump_segment_header) + | |
886 | sizeof(mpi_coredump->serdes2_xfi_train), | |
887 | "XFI2 TRAIN Registers"); | |
888 | ||
889 | ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_pcs_hdr, | |
890 | XFI2_HSS_PCS_SEG_NUM, | |
891 | sizeof(struct mpi_coredump_segment_header) + | |
892 | sizeof(mpi_coredump->serdes2_xfi_hss_pcs), | |
893 | "XFI2 HSS PCS Registers"); | |
894 | ||
895 | ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_tx_hdr, | |
896 | XFI2_HSS_TX_SEG_NUM, | |
897 | sizeof(struct mpi_coredump_segment_header) + | |
898 | sizeof(mpi_coredump->serdes2_xfi_hss_tx), | |
899 | "XFI2 HSS TX Registers"); | |
900 | ||
901 | ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_rx_hdr, | |
902 | XFI2_HSS_RX_SEG_NUM, | |
903 | sizeof(struct mpi_coredump_segment_header) + | |
904 | sizeof(mpi_coredump->serdes2_xfi_hss_rx), | |
905 | "XFI2 HSS RX Registers"); | |
906 | ||
907 | ql_build_coredump_seg_header(&mpi_coredump->xfi2_hss_pll_hdr, | |
908 | XFI2_HSS_PLL_SEG_NUM, | |
909 | sizeof(struct mpi_coredump_segment_header) + | |
910 | sizeof(mpi_coredump->serdes2_xfi_hss_pll), | |
911 | "XFI2 HSS PLL Registers"); | |
912 | ||
913 | status = ql_get_serdes_regs(qdev, mpi_coredump); | |
914 | if (status) { | |
ae9540f7 JP |
915 | netif_err(qdev, drv, qdev->ndev, |
916 | "Failed Dump of Serdes Registers. Status = 0x%.08x\n", | |
917 | status); | |
a48c86fd RM |
918 | goto err; |
919 | } | |
920 | ||
8aae2600 RM |
921 | ql_build_coredump_seg_header(&mpi_coredump->core_regs_seg_hdr, |
922 | CORE_SEG_NUM, | |
923 | sizeof(mpi_coredump->core_regs_seg_hdr) + | |
924 | sizeof(mpi_coredump->mpi_core_regs) + | |
925 | sizeof(mpi_coredump->mpi_core_sh_regs), | |
926 | "Core Registers"); | |
927 | ||
928 | /* Get the MPI Core Registers */ | |
929 | status = ql_get_mpi_regs(qdev, &mpi_coredump->mpi_core_regs[0], | |
930 | MPI_CORE_REGS_ADDR, MPI_CORE_REGS_CNT); | |
931 | if (status) | |
932 | goto err; | |
933 | /* Get the 16 MPI shadow registers */ | |
934 | status = ql_get_mpi_shadow_regs(qdev, | |
935 | &mpi_coredump->mpi_core_sh_regs[0]); | |
936 | if (status) | |
937 | goto err; | |
938 | ||
939 | /* Get the Test Logic Registers */ | |
940 | ql_build_coredump_seg_header(&mpi_coredump->test_logic_regs_seg_hdr, | |
941 | TEST_LOGIC_SEG_NUM, | |
942 | sizeof(struct mpi_coredump_segment_header) | |
943 | + sizeof(mpi_coredump->test_logic_regs), | |
944 | "Test Logic Regs"); | |
945 | status = ql_get_mpi_regs(qdev, &mpi_coredump->test_logic_regs[0], | |
946 | TEST_REGS_ADDR, TEST_REGS_CNT); | |
947 | if (status) | |
948 | goto err; | |
949 | ||
950 | /* Get the RMII Registers */ | |
951 | ql_build_coredump_seg_header(&mpi_coredump->rmii_regs_seg_hdr, | |
952 | RMII_SEG_NUM, | |
953 | sizeof(struct mpi_coredump_segment_header) | |
954 | + sizeof(mpi_coredump->rmii_regs), | |
955 | "RMII Registers"); | |
956 | status = ql_get_mpi_regs(qdev, &mpi_coredump->rmii_regs[0], | |
957 | RMII_REGS_ADDR, RMII_REGS_CNT); | |
958 | if (status) | |
959 | goto err; | |
960 | ||
961 | /* Get the FCMAC1 Registers */ | |
962 | ql_build_coredump_seg_header(&mpi_coredump->fcmac1_regs_seg_hdr, | |
963 | FCMAC1_SEG_NUM, | |
964 | sizeof(struct mpi_coredump_segment_header) | |
965 | + sizeof(mpi_coredump->fcmac1_regs), | |
966 | "FCMAC1 Registers"); | |
967 | status = ql_get_mpi_regs(qdev, &mpi_coredump->fcmac1_regs[0], | |
968 | FCMAC1_REGS_ADDR, FCMAC_REGS_CNT); | |
969 | if (status) | |
970 | goto err; | |
971 | ||
972 | /* Get the FCMAC2 Registers */ | |
973 | ||
974 | ql_build_coredump_seg_header(&mpi_coredump->fcmac2_regs_seg_hdr, | |
975 | FCMAC2_SEG_NUM, | |
976 | sizeof(struct mpi_coredump_segment_header) | |
977 | + sizeof(mpi_coredump->fcmac2_regs), | |
978 | "FCMAC2 Registers"); | |
979 | ||
980 | status = ql_get_mpi_regs(qdev, &mpi_coredump->fcmac2_regs[0], | |
981 | FCMAC2_REGS_ADDR, FCMAC_REGS_CNT); | |
982 | if (status) | |
983 | goto err; | |
984 | ||
985 | /* Get the FC1 MBX Registers */ | |
986 | ql_build_coredump_seg_header(&mpi_coredump->fc1_mbx_regs_seg_hdr, | |
987 | FC1_MBOX_SEG_NUM, | |
988 | sizeof(struct mpi_coredump_segment_header) | |
989 | + sizeof(mpi_coredump->fc1_mbx_regs), | |
990 | "FC1 MBox Regs"); | |
991 | status = ql_get_mpi_regs(qdev, &mpi_coredump->fc1_mbx_regs[0], | |
992 | FC1_MBX_REGS_ADDR, FC_MBX_REGS_CNT); | |
993 | if (status) | |
994 | goto err; | |
995 | ||
996 | /* Get the IDE Registers */ | |
997 | ql_build_coredump_seg_header(&mpi_coredump->ide_regs_seg_hdr, | |
998 | IDE_SEG_NUM, | |
999 | sizeof(struct mpi_coredump_segment_header) | |
1000 | + sizeof(mpi_coredump->ide_regs), | |
1001 | "IDE Registers"); | |
1002 | status = ql_get_mpi_regs(qdev, &mpi_coredump->ide_regs[0], | |
1003 | IDE_REGS_ADDR, IDE_REGS_CNT); | |
1004 | if (status) | |
1005 | goto err; | |
1006 | ||
1007 | /* Get the NIC1 MBX Registers */ | |
1008 | ql_build_coredump_seg_header(&mpi_coredump->nic1_mbx_regs_seg_hdr, | |
1009 | NIC1_MBOX_SEG_NUM, | |
1010 | sizeof(struct mpi_coredump_segment_header) | |
1011 | + sizeof(mpi_coredump->nic1_mbx_regs), | |
1012 | "NIC1 MBox Regs"); | |
1013 | status = ql_get_mpi_regs(qdev, &mpi_coredump->nic1_mbx_regs[0], | |
1014 | NIC1_MBX_REGS_ADDR, NIC_MBX_REGS_CNT); | |
1015 | if (status) | |
1016 | goto err; | |
1017 | ||
1018 | /* Get the SMBus Registers */ | |
1019 | ql_build_coredump_seg_header(&mpi_coredump->smbus_regs_seg_hdr, | |
1020 | SMBUS_SEG_NUM, | |
1021 | sizeof(struct mpi_coredump_segment_header) | |
1022 | + sizeof(mpi_coredump->smbus_regs), | |
1023 | "SMBus Registers"); | |
1024 | status = ql_get_mpi_regs(qdev, &mpi_coredump->smbus_regs[0], | |
1025 | SMBUS_REGS_ADDR, SMBUS_REGS_CNT); | |
1026 | if (status) | |
1027 | goto err; | |
1028 | ||
1029 | /* Get the FC2 MBX Registers */ | |
1030 | ql_build_coredump_seg_header(&mpi_coredump->fc2_mbx_regs_seg_hdr, | |
1031 | FC2_MBOX_SEG_NUM, | |
1032 | sizeof(struct mpi_coredump_segment_header) | |
1033 | + sizeof(mpi_coredump->fc2_mbx_regs), | |
1034 | "FC2 MBox Regs"); | |
1035 | status = ql_get_mpi_regs(qdev, &mpi_coredump->fc2_mbx_regs[0], | |
1036 | FC2_MBX_REGS_ADDR, FC_MBX_REGS_CNT); | |
1037 | if (status) | |
1038 | goto err; | |
1039 | ||
1040 | /* Get the NIC2 MBX Registers */ | |
1041 | ql_build_coredump_seg_header(&mpi_coredump->nic2_mbx_regs_seg_hdr, | |
1042 | NIC2_MBOX_SEG_NUM, | |
1043 | sizeof(struct mpi_coredump_segment_header) | |
1044 | + sizeof(mpi_coredump->nic2_mbx_regs), | |
1045 | "NIC2 MBox Regs"); | |
1046 | status = ql_get_mpi_regs(qdev, &mpi_coredump->nic2_mbx_regs[0], | |
1047 | NIC2_MBX_REGS_ADDR, NIC_MBX_REGS_CNT); | |
1048 | if (status) | |
1049 | goto err; | |
1050 | ||
1051 | /* Get the I2C Registers */ | |
1052 | ql_build_coredump_seg_header(&mpi_coredump->i2c_regs_seg_hdr, | |
1053 | I2C_SEG_NUM, | |
1054 | sizeof(struct mpi_coredump_segment_header) | |
1055 | + sizeof(mpi_coredump->i2c_regs), | |
1056 | "I2C Registers"); | |
1057 | status = ql_get_mpi_regs(qdev, &mpi_coredump->i2c_regs[0], | |
1058 | I2C_REGS_ADDR, I2C_REGS_CNT); | |
1059 | if (status) | |
1060 | goto err; | |
1061 | ||
1062 | /* Get the MEMC Registers */ | |
1063 | ql_build_coredump_seg_header(&mpi_coredump->memc_regs_seg_hdr, | |
1064 | MEMC_SEG_NUM, | |
1065 | sizeof(struct mpi_coredump_segment_header) | |
1066 | + sizeof(mpi_coredump->memc_regs), | |
1067 | "MEMC Registers"); | |
1068 | status = ql_get_mpi_regs(qdev, &mpi_coredump->memc_regs[0], | |
1069 | MEMC_REGS_ADDR, MEMC_REGS_CNT); | |
1070 | if (status) | |
1071 | goto err; | |
1072 | ||
1073 | /* Get the PBus Registers */ | |
1074 | ql_build_coredump_seg_header(&mpi_coredump->pbus_regs_seg_hdr, | |
1075 | PBUS_SEG_NUM, | |
1076 | sizeof(struct mpi_coredump_segment_header) | |
1077 | + sizeof(mpi_coredump->pbus_regs), | |
1078 | "PBUS Registers"); | |
1079 | status = ql_get_mpi_regs(qdev, &mpi_coredump->pbus_regs[0], | |
1080 | PBUS_REGS_ADDR, PBUS_REGS_CNT); | |
1081 | if (status) | |
1082 | goto err; | |
1083 | ||
1084 | /* Get the MDE Registers */ | |
1085 | ql_build_coredump_seg_header(&mpi_coredump->mde_regs_seg_hdr, | |
1086 | MDE_SEG_NUM, | |
1087 | sizeof(struct mpi_coredump_segment_header) | |
1088 | + sizeof(mpi_coredump->mde_regs), | |
1089 | "MDE Registers"); | |
1090 | status = ql_get_mpi_regs(qdev, &mpi_coredump->mde_regs[0], | |
1091 | MDE_REGS_ADDR, MDE_REGS_CNT); | |
1092 | if (status) | |
1093 | goto err; | |
1094 | ||
1095 | ql_build_coredump_seg_header(&mpi_coredump->misc_nic_seg_hdr, | |
1096 | MISC_NIC_INFO_SEG_NUM, | |
1097 | sizeof(struct mpi_coredump_segment_header) | |
1098 | + sizeof(mpi_coredump->misc_nic_info), | |
1099 | "MISC NIC INFO"); | |
1100 | mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count; | |
1101 | mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count; | |
1102 | mpi_coredump->misc_nic_info.intr_count = qdev->intr_count; | |
1103 | mpi_coredump->misc_nic_info.function = qdev->func; | |
1104 | ||
1105 | /* Segment 31 */ | |
1106 | /* Get indexed register values. */ | |
1107 | ql_build_coredump_seg_header(&mpi_coredump->intr_states_seg_hdr, | |
1108 | INTR_STATES_SEG_NUM, | |
1109 | sizeof(struct mpi_coredump_segment_header) | |
1110 | + sizeof(mpi_coredump->intr_states), | |
1111 | "INTR States"); | |
1112 | ql_get_intr_states(qdev, &mpi_coredump->intr_states[0]); | |
1113 | ||
1114 | ql_build_coredump_seg_header(&mpi_coredump->cam_entries_seg_hdr, | |
1115 | CAM_ENTRIES_SEG_NUM, | |
1116 | sizeof(struct mpi_coredump_segment_header) | |
1117 | + sizeof(mpi_coredump->cam_entries), | |
1118 | "CAM Entries"); | |
1119 | status = ql_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]); | |
1120 | if (status) | |
1121 | goto err; | |
1122 | ||
1123 | ql_build_coredump_seg_header(&mpi_coredump->nic_routing_words_seg_hdr, | |
1124 | ROUTING_WORDS_SEG_NUM, | |
1125 | sizeof(struct mpi_coredump_segment_header) | |
1126 | + sizeof(mpi_coredump->nic_routing_words), | |
1127 | "Routing Words"); | |
1128 | status = ql_get_routing_entries(qdev, | |
1129 | &mpi_coredump->nic_routing_words[0]); | |
1130 | if (status) | |
1131 | goto err; | |
1132 | ||
1133 | /* Segment 34 (Rev C. step 23) */ | |
1134 | ql_build_coredump_seg_header(&mpi_coredump->ets_seg_hdr, | |
1135 | ETS_SEG_NUM, | |
1136 | sizeof(struct mpi_coredump_segment_header) | |
1137 | + sizeof(mpi_coredump->ets), | |
1138 | "ETS Registers"); | |
1139 | status = ql_get_ets_regs(qdev, &mpi_coredump->ets[0]); | |
1140 | if (status) | |
1141 | goto err; | |
1142 | ||
c89ec8b9 RM |
1143 | ql_build_coredump_seg_header(&mpi_coredump->probe_dump_seg_hdr, |
1144 | PROBE_DUMP_SEG_NUM, | |
1145 | sizeof(struct mpi_coredump_segment_header) | |
1146 | + sizeof(mpi_coredump->probe_dump), | |
1147 | "Probe Dump"); | |
1148 | ql_get_probe_dump(qdev, &mpi_coredump->probe_dump[0]); | |
1149 | ||
8aae2600 RM |
1150 | ql_build_coredump_seg_header(&mpi_coredump->routing_reg_seg_hdr, |
1151 | ROUTING_INDEX_SEG_NUM, | |
1152 | sizeof(struct mpi_coredump_segment_header) | |
1153 | + sizeof(mpi_coredump->routing_regs), | |
1154 | "Routing Regs"); | |
1155 | status = ql_get_routing_index_registers(qdev, | |
1156 | &mpi_coredump->routing_regs[0]); | |
1157 | if (status) | |
1158 | goto err; | |
1159 | ||
1160 | ql_build_coredump_seg_header(&mpi_coredump->mac_prot_reg_seg_hdr, | |
1161 | MAC_PROTOCOL_SEG_NUM, | |
1162 | sizeof(struct mpi_coredump_segment_header) | |
1163 | + sizeof(mpi_coredump->mac_prot_regs), | |
1164 | "MAC Prot Regs"); | |
1165 | ql_get_mac_protocol_registers(qdev, &mpi_coredump->mac_prot_regs[0]); | |
1166 | ||
1167 | /* Get the semaphore registers for all 5 functions */ | |
1168 | ql_build_coredump_seg_header(&mpi_coredump->sem_regs_seg_hdr, | |
1169 | SEM_REGS_SEG_NUM, | |
1170 | sizeof(struct mpi_coredump_segment_header) + | |
1171 | sizeof(mpi_coredump->sem_regs), "Sem Registers"); | |
1172 | ||
1173 | ql_get_sem_registers(qdev, &mpi_coredump->sem_regs[0]); | |
1174 | ||
1175 | /* Prevent the mpi restarting while we dump the memory.*/ | |
1176 | ql_write_mpi_reg(qdev, MPI_TEST_FUNC_RST_STS, MPI_TEST_FUNC_RST_FRC); | |
1177 | ||
1178 | /* clear the pause */ | |
1179 | status = ql_unpause_mpi_risc(qdev); | |
1180 | if (status) { | |
ae9540f7 JP |
1181 | netif_err(qdev, drv, qdev->ndev, |
1182 | "Failed RISC unpause. Status = 0x%.08x\n", status); | |
8aae2600 RM |
1183 | goto err; |
1184 | } | |
2c1f73c3 RM |
1185 | |
1186 | /* Reset the RISC so we can dump RAM */ | |
1187 | status = ql_hard_reset_mpi_risc(qdev); | |
1188 | if (status) { | |
ae9540f7 JP |
1189 | netif_err(qdev, drv, qdev->ndev, |
1190 | "Failed RISC reset. Status = 0x%.08x\n", status); | |
2c1f73c3 RM |
1191 | goto err; |
1192 | } | |
1193 | ||
1194 | ql_build_coredump_seg_header(&mpi_coredump->code_ram_seg_hdr, | |
1195 | WCS_RAM_SEG_NUM, | |
1196 | sizeof(struct mpi_coredump_segment_header) | |
1197 | + sizeof(mpi_coredump->code_ram), | |
1198 | "WCS RAM"); | |
1199 | status = ql_dump_risc_ram_area(qdev, &mpi_coredump->code_ram[0], | |
1200 | CODE_RAM_ADDR, CODE_RAM_CNT); | |
1201 | if (status) { | |
ae9540f7 JP |
1202 | netif_err(qdev, drv, qdev->ndev, |
1203 | "Failed Dump of CODE RAM. Status = 0x%.08x\n", | |
1204 | status); | |
2c1f73c3 RM |
1205 | goto err; |
1206 | } | |
1207 | ||
1208 | /* Insert the segment header */ | |
1209 | ql_build_coredump_seg_header(&mpi_coredump->memc_ram_seg_hdr, | |
1210 | MEMC_RAM_SEG_NUM, | |
1211 | sizeof(struct mpi_coredump_segment_header) | |
1212 | + sizeof(mpi_coredump->memc_ram), | |
1213 | "MEMC RAM"); | |
1214 | status = ql_dump_risc_ram_area(qdev, &mpi_coredump->memc_ram[0], | |
1215 | MEMC_RAM_ADDR, MEMC_RAM_CNT); | |
1216 | if (status) { | |
ae9540f7 JP |
1217 | netif_err(qdev, drv, qdev->ndev, |
1218 | "Failed Dump of MEMC RAM. Status = 0x%.08x\n", | |
1219 | status); | |
2c1f73c3 RM |
1220 | goto err; |
1221 | } | |
8aae2600 RM |
1222 | err: |
1223 | ql_sem_unlock(qdev, SEM_PROC_REG_MASK); /* does flush too */ | |
1224 | return status; | |
1225 | ||
1226 | } | |
1227 | ||
d5c1da56 RM |
1228 | static void ql_get_core_dump(struct ql_adapter *qdev) |
1229 | { | |
1230 | if (!ql_own_firmware(qdev)) { | |
ae9540f7 | 1231 | netif_err(qdev, drv, qdev->ndev, "Don't own firmware!\n"); |
d5c1da56 RM |
1232 | return; |
1233 | } | |
1234 | ||
1235 | if (!netif_running(qdev->ndev)) { | |
ae9540f7 JP |
1236 | netif_err(qdev, ifup, qdev->ndev, |
1237 | "Force Coredump can only be done from interface that is up.\n"); | |
d5c1da56 RM |
1238 | return; |
1239 | } | |
1240 | ||
1241 | if (ql_mb_sys_err(qdev)) { | |
ae9540f7 JP |
1242 | netif_err(qdev, ifup, qdev->ndev, |
1243 | "Fail force coredump with ql_mb_sys_err().\n"); | |
d5c1da56 RM |
1244 | return; |
1245 | } | |
1246 | } | |
1247 | ||
a61f8026 RM |
1248 | void ql_gen_reg_dump(struct ql_adapter *qdev, |
1249 | struct ql_reg_dump *mpi_coredump) | |
1250 | { | |
1251 | int i, status; | |
1252 | ||
1253 | ||
1254 | memset(&(mpi_coredump->mpi_global_header), 0, | |
1255 | sizeof(struct mpi_coredump_global_header)); | |
1256 | mpi_coredump->mpi_global_header.cookie = MPI_COREDUMP_COOKIE; | |
1257 | mpi_coredump->mpi_global_header.headerSize = | |
1258 | sizeof(struct mpi_coredump_global_header); | |
1259 | mpi_coredump->mpi_global_header.imageSize = | |
1260 | sizeof(struct ql_reg_dump); | |
1261 | memcpy(mpi_coredump->mpi_global_header.idString, "MPI Coredump", | |
1262 | sizeof(mpi_coredump->mpi_global_header.idString)); | |
1263 | ||
1264 | ||
1265 | /* segment 16 */ | |
1266 | ql_build_coredump_seg_header(&mpi_coredump->misc_nic_seg_hdr, | |
1267 | MISC_NIC_INFO_SEG_NUM, | |
1268 | sizeof(struct mpi_coredump_segment_header) | |
1269 | + sizeof(mpi_coredump->misc_nic_info), | |
1270 | "MISC NIC INFO"); | |
1271 | mpi_coredump->misc_nic_info.rx_ring_count = qdev->rx_ring_count; | |
1272 | mpi_coredump->misc_nic_info.tx_ring_count = qdev->tx_ring_count; | |
1273 | mpi_coredump->misc_nic_info.intr_count = qdev->intr_count; | |
1274 | mpi_coredump->misc_nic_info.function = qdev->func; | |
1275 | ||
1276 | /* Segment 16, Rev C. Step 18 */ | |
1277 | ql_build_coredump_seg_header(&mpi_coredump->nic_regs_seg_hdr, | |
1278 | NIC1_CONTROL_SEG_NUM, | |
1279 | sizeof(struct mpi_coredump_segment_header) | |
1280 | + sizeof(mpi_coredump->nic_regs), | |
1281 | "NIC Registers"); | |
1282 | /* Get generic reg dump */ | |
1283 | for (i = 0; i < 64; i++) | |
1284 | mpi_coredump->nic_regs[i] = ql_read32(qdev, i * sizeof(u32)); | |
1285 | ||
1286 | /* Segment 31 */ | |
1287 | /* Get indexed register values. */ | |
1288 | ql_build_coredump_seg_header(&mpi_coredump->intr_states_seg_hdr, | |
1289 | INTR_STATES_SEG_NUM, | |
1290 | sizeof(struct mpi_coredump_segment_header) | |
1291 | + sizeof(mpi_coredump->intr_states), | |
1292 | "INTR States"); | |
1293 | ql_get_intr_states(qdev, &mpi_coredump->intr_states[0]); | |
1294 | ||
1295 | ql_build_coredump_seg_header(&mpi_coredump->cam_entries_seg_hdr, | |
1296 | CAM_ENTRIES_SEG_NUM, | |
1297 | sizeof(struct mpi_coredump_segment_header) | |
1298 | + sizeof(mpi_coredump->cam_entries), | |
1299 | "CAM Entries"); | |
1300 | status = ql_get_cam_entries(qdev, &mpi_coredump->cam_entries[0]); | |
1301 | if (status) | |
1302 | return; | |
1303 | ||
1304 | ql_build_coredump_seg_header(&mpi_coredump->nic_routing_words_seg_hdr, | |
1305 | ROUTING_WORDS_SEG_NUM, | |
1306 | sizeof(struct mpi_coredump_segment_header) | |
1307 | + sizeof(mpi_coredump->nic_routing_words), | |
1308 | "Routing Words"); | |
1309 | status = ql_get_routing_entries(qdev, | |
1310 | &mpi_coredump->nic_routing_words[0]); | |
1311 | if (status) | |
1312 | return; | |
1313 | ||
1314 | /* Segment 34 (Rev C. step 23) */ | |
1315 | ql_build_coredump_seg_header(&mpi_coredump->ets_seg_hdr, | |
1316 | ETS_SEG_NUM, | |
1317 | sizeof(struct mpi_coredump_segment_header) | |
1318 | + sizeof(mpi_coredump->ets), | |
1319 | "ETS Registers"); | |
1320 | status = ql_get_ets_regs(qdev, &mpi_coredump->ets[0]); | |
1321 | if (status) | |
1322 | return; | |
d5c1da56 RM |
1323 | |
1324 | if (test_bit(QL_FRC_COREDUMP, &qdev->flags)) | |
1325 | ql_get_core_dump(qdev); | |
a61f8026 RM |
1326 | } |
1327 | ||
8aae2600 RM |
1328 | /* Coredump to messages log file using separate worker thread */ |
1329 | void ql_mpi_core_to_log(struct work_struct *work) | |
1330 | { | |
1331 | struct ql_adapter *qdev = | |
1332 | container_of(work, struct ql_adapter, mpi_core_to_log.work); | |
1333 | u32 *tmp, count; | |
1334 | int i; | |
1335 | ||
1336 | count = sizeof(struct ql_mpi_coredump) / sizeof(u32); | |
1337 | tmp = (u32 *)qdev->mpi_coredump; | |
ae9540f7 JP |
1338 | netif_printk(qdev, drv, KERN_DEBUG, qdev->ndev, |
1339 | "Core is dumping to log file!\n"); | |
8aae2600 RM |
1340 | |
1341 | for (i = 0; i < count; i += 8) { | |
1342 | printk(KERN_ERR "%.08x: %.08x %.08x %.08x %.08x %.08x " | |
1343 | "%.08x %.08x %.08x \n", i, | |
1344 | tmp[i + 0], | |
1345 | tmp[i + 1], | |
1346 | tmp[i + 2], | |
1347 | tmp[i + 3], | |
1348 | tmp[i + 4], | |
1349 | tmp[i + 5], | |
1350 | tmp[i + 6], | |
1351 | tmp[i + 7]); | |
1352 | msleep(5); | |
1353 | } | |
1354 | } | |
1355 | ||
c4e84bde RM |
1356 | #ifdef QL_REG_DUMP |
1357 | static void ql_dump_intr_states(struct ql_adapter *qdev) | |
1358 | { | |
1359 | int i; | |
1360 | u32 value; | |
1361 | for (i = 0; i < qdev->intr_count; i++) { | |
1362 | ql_write32(qdev, INTR_EN, qdev->intr_context[i].intr_read_mask); | |
1363 | value = ql_read32(qdev, INTR_EN); | |
1364 | printk(KERN_ERR PFX | |
1365 | "%s: Interrupt %d is %s.\n", | |
1366 | qdev->ndev->name, i, | |
1367 | (value & INTR_EN_EN ? "enabled" : "disabled")); | |
1368 | } | |
1369 | } | |
1370 | ||
1371 | void ql_dump_xgmac_control_regs(struct ql_adapter *qdev) | |
1372 | { | |
1373 | u32 data; | |
1374 | if (ql_sem_spinlock(qdev, qdev->xg_sem_mask)) { | |
1375 | printk(KERN_ERR "%s: Couldn't get xgmac sem.\n", __func__); | |
1376 | return; | |
1377 | } | |
1378 | ql_read_xgmac_reg(qdev, PAUSE_SRC_LO, &data); | |
1379 | printk(KERN_ERR PFX "%s: PAUSE_SRC_LO = 0x%.08x.\n", qdev->ndev->name, | |
1380 | data); | |
1381 | ql_read_xgmac_reg(qdev, PAUSE_SRC_HI, &data); | |
1382 | printk(KERN_ERR PFX "%s: PAUSE_SRC_HI = 0x%.08x.\n", qdev->ndev->name, | |
1383 | data); | |
1384 | ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data); | |
1385 | printk(KERN_ERR PFX "%s: GLOBAL_CFG = 0x%.08x.\n", qdev->ndev->name, | |
1386 | data); | |
1387 | ql_read_xgmac_reg(qdev, TX_CFG, &data); | |
1388 | printk(KERN_ERR PFX "%s: TX_CFG = 0x%.08x.\n", qdev->ndev->name, data); | |
1389 | ql_read_xgmac_reg(qdev, RX_CFG, &data); | |
1390 | printk(KERN_ERR PFX "%s: RX_CFG = 0x%.08x.\n", qdev->ndev->name, data); | |
1391 | ql_read_xgmac_reg(qdev, FLOW_CTL, &data); | |
1392 | printk(KERN_ERR PFX "%s: FLOW_CTL = 0x%.08x.\n", qdev->ndev->name, | |
1393 | data); | |
1394 | ql_read_xgmac_reg(qdev, PAUSE_OPCODE, &data); | |
1395 | printk(KERN_ERR PFX "%s: PAUSE_OPCODE = 0x%.08x.\n", qdev->ndev->name, | |
1396 | data); | |
1397 | ql_read_xgmac_reg(qdev, PAUSE_TIMER, &data); | |
1398 | printk(KERN_ERR PFX "%s: PAUSE_TIMER = 0x%.08x.\n", qdev->ndev->name, | |
1399 | data); | |
1400 | ql_read_xgmac_reg(qdev, PAUSE_FRM_DEST_LO, &data); | |
1401 | printk(KERN_ERR PFX "%s: PAUSE_FRM_DEST_LO = 0x%.08x.\n", | |
1402 | qdev->ndev->name, data); | |
1403 | ql_read_xgmac_reg(qdev, PAUSE_FRM_DEST_HI, &data); | |
1404 | printk(KERN_ERR PFX "%s: PAUSE_FRM_DEST_HI = 0x%.08x.\n", | |
1405 | qdev->ndev->name, data); | |
1406 | ql_read_xgmac_reg(qdev, MAC_TX_PARAMS, &data); | |
1407 | printk(KERN_ERR PFX "%s: MAC_TX_PARAMS = 0x%.08x.\n", qdev->ndev->name, | |
1408 | data); | |
1409 | ql_read_xgmac_reg(qdev, MAC_RX_PARAMS, &data); | |
1410 | printk(KERN_ERR PFX "%s: MAC_RX_PARAMS = 0x%.08x.\n", qdev->ndev->name, | |
1411 | data); | |
1412 | ql_read_xgmac_reg(qdev, MAC_SYS_INT, &data); | |
1413 | printk(KERN_ERR PFX "%s: MAC_SYS_INT = 0x%.08x.\n", qdev->ndev->name, | |
1414 | data); | |
1415 | ql_read_xgmac_reg(qdev, MAC_SYS_INT_MASK, &data); | |
1416 | printk(KERN_ERR PFX "%s: MAC_SYS_INT_MASK = 0x%.08x.\n", | |
1417 | qdev->ndev->name, data); | |
1418 | ql_read_xgmac_reg(qdev, MAC_MGMT_INT, &data); | |
1419 | printk(KERN_ERR PFX "%s: MAC_MGMT_INT = 0x%.08x.\n", qdev->ndev->name, | |
1420 | data); | |
1421 | ql_read_xgmac_reg(qdev, MAC_MGMT_IN_MASK, &data); | |
1422 | printk(KERN_ERR PFX "%s: MAC_MGMT_IN_MASK = 0x%.08x.\n", | |
1423 | qdev->ndev->name, data); | |
1424 | ql_read_xgmac_reg(qdev, EXT_ARB_MODE, &data); | |
1425 | printk(KERN_ERR PFX "%s: EXT_ARB_MODE = 0x%.08x.\n", qdev->ndev->name, | |
1426 | data); | |
1427 | ql_sem_unlock(qdev, qdev->xg_sem_mask); | |
1428 | ||
1429 | } | |
1430 | ||
1431 | static void ql_dump_ets_regs(struct ql_adapter *qdev) | |
1432 | { | |
1433 | } | |
1434 | ||
1435 | static void ql_dump_cam_entries(struct ql_adapter *qdev) | |
1436 | { | |
1437 | int i; | |
1438 | u32 value[3]; | |
cc288f54 RM |
1439 | |
1440 | i = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK); | |
1441 | if (i) | |
1442 | return; | |
c4e84bde RM |
1443 | for (i = 0; i < 4; i++) { |
1444 | if (ql_get_mac_addr_reg(qdev, MAC_ADDR_TYPE_CAM_MAC, i, value)) { | |
1445 | printk(KERN_ERR PFX | |
1446 | "%s: Failed read of mac index register.\n", | |
1447 | __func__); | |
1448 | return; | |
1449 | } else { | |
1450 | if (value[0]) | |
1451 | printk(KERN_ERR PFX | |
1452 | "%s: CAM index %d CAM Lookup Lower = 0x%.08x:%.08x, Output = 0x%.08x.\n", | |
1453 | qdev->ndev->name, i, value[1], value[0], | |
1454 | value[2]); | |
1455 | } | |
1456 | } | |
1457 | for (i = 0; i < 32; i++) { | |
1458 | if (ql_get_mac_addr_reg | |
1459 | (qdev, MAC_ADDR_TYPE_MULTI_MAC, i, value)) { | |
1460 | printk(KERN_ERR PFX | |
1461 | "%s: Failed read of mac index register.\n", | |
1462 | __func__); | |
1463 | return; | |
1464 | } else { | |
1465 | if (value[0]) | |
1466 | printk(KERN_ERR PFX | |
1467 | "%s: MCAST index %d CAM Lookup Lower = 0x%.08x:%.08x.\n", | |
1468 | qdev->ndev->name, i, value[1], value[0]); | |
1469 | } | |
1470 | } | |
cc288f54 | 1471 | ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK); |
c4e84bde RM |
1472 | } |
1473 | ||
1474 | void ql_dump_routing_entries(struct ql_adapter *qdev) | |
1475 | { | |
1476 | int i; | |
1477 | u32 value; | |
cc288f54 RM |
1478 | i = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK); |
1479 | if (i) | |
1480 | return; | |
c4e84bde RM |
1481 | for (i = 0; i < 16; i++) { |
1482 | value = 0; | |
1483 | if (ql_get_routing_reg(qdev, i, &value)) { | |
1484 | printk(KERN_ERR PFX | |
1485 | "%s: Failed read of routing index register.\n", | |
1486 | __func__); | |
1487 | return; | |
1488 | } else { | |
1489 | if (value) | |
1490 | printk(KERN_ERR PFX | |
1491 | "%s: Routing Mask %d = 0x%.08x.\n", | |
1492 | qdev->ndev->name, i, value); | |
1493 | } | |
1494 | } | |
cc288f54 | 1495 | ql_sem_unlock(qdev, SEM_RT_IDX_MASK); |
c4e84bde RM |
1496 | } |
1497 | ||
1498 | void ql_dump_regs(struct ql_adapter *qdev) | |
1499 | { | |
1500 | printk(KERN_ERR PFX "reg dump for function #%d.\n", qdev->func); | |
1501 | printk(KERN_ERR PFX "SYS = 0x%x.\n", | |
1502 | ql_read32(qdev, SYS)); | |
1503 | printk(KERN_ERR PFX "RST_FO = 0x%x.\n", | |
1504 | ql_read32(qdev, RST_FO)); | |
1505 | printk(KERN_ERR PFX "FSC = 0x%x.\n", | |
1506 | ql_read32(qdev, FSC)); | |
1507 | printk(KERN_ERR PFX "CSR = 0x%x.\n", | |
1508 | ql_read32(qdev, CSR)); | |
1509 | printk(KERN_ERR PFX "ICB_RID = 0x%x.\n", | |
1510 | ql_read32(qdev, ICB_RID)); | |
1511 | printk(KERN_ERR PFX "ICB_L = 0x%x.\n", | |
1512 | ql_read32(qdev, ICB_L)); | |
1513 | printk(KERN_ERR PFX "ICB_H = 0x%x.\n", | |
1514 | ql_read32(qdev, ICB_H)); | |
1515 | printk(KERN_ERR PFX "CFG = 0x%x.\n", | |
1516 | ql_read32(qdev, CFG)); | |
1517 | printk(KERN_ERR PFX "BIOS_ADDR = 0x%x.\n", | |
1518 | ql_read32(qdev, BIOS_ADDR)); | |
1519 | printk(KERN_ERR PFX "STS = 0x%x.\n", | |
1520 | ql_read32(qdev, STS)); | |
1521 | printk(KERN_ERR PFX "INTR_EN = 0x%x.\n", | |
1522 | ql_read32(qdev, INTR_EN)); | |
1523 | printk(KERN_ERR PFX "INTR_MASK = 0x%x.\n", | |
1524 | ql_read32(qdev, INTR_MASK)); | |
1525 | printk(KERN_ERR PFX "ISR1 = 0x%x.\n", | |
1526 | ql_read32(qdev, ISR1)); | |
1527 | printk(KERN_ERR PFX "ISR2 = 0x%x.\n", | |
1528 | ql_read32(qdev, ISR2)); | |
1529 | printk(KERN_ERR PFX "ISR3 = 0x%x.\n", | |
1530 | ql_read32(qdev, ISR3)); | |
1531 | printk(KERN_ERR PFX "ISR4 = 0x%x.\n", | |
1532 | ql_read32(qdev, ISR4)); | |
1533 | printk(KERN_ERR PFX "REV_ID = 0x%x.\n", | |
1534 | ql_read32(qdev, REV_ID)); | |
1535 | printk(KERN_ERR PFX "FRC_ECC_ERR = 0x%x.\n", | |
1536 | ql_read32(qdev, FRC_ECC_ERR)); | |
1537 | printk(KERN_ERR PFX "ERR_STS = 0x%x.\n", | |
1538 | ql_read32(qdev, ERR_STS)); | |
1539 | printk(KERN_ERR PFX "RAM_DBG_ADDR = 0x%x.\n", | |
1540 | ql_read32(qdev, RAM_DBG_ADDR)); | |
1541 | printk(KERN_ERR PFX "RAM_DBG_DATA = 0x%x.\n", | |
1542 | ql_read32(qdev, RAM_DBG_DATA)); | |
1543 | printk(KERN_ERR PFX "ECC_ERR_CNT = 0x%x.\n", | |
1544 | ql_read32(qdev, ECC_ERR_CNT)); | |
1545 | printk(KERN_ERR PFX "SEM = 0x%x.\n", | |
1546 | ql_read32(qdev, SEM)); | |
1547 | printk(KERN_ERR PFX "GPIO_1 = 0x%x.\n", | |
1548 | ql_read32(qdev, GPIO_1)); | |
1549 | printk(KERN_ERR PFX "GPIO_2 = 0x%x.\n", | |
1550 | ql_read32(qdev, GPIO_2)); | |
1551 | printk(KERN_ERR PFX "GPIO_3 = 0x%x.\n", | |
1552 | ql_read32(qdev, GPIO_3)); | |
1553 | printk(KERN_ERR PFX "XGMAC_ADDR = 0x%x.\n", | |
1554 | ql_read32(qdev, XGMAC_ADDR)); | |
1555 | printk(KERN_ERR PFX "XGMAC_DATA = 0x%x.\n", | |
1556 | ql_read32(qdev, XGMAC_DATA)); | |
1557 | printk(KERN_ERR PFX "NIC_ETS = 0x%x.\n", | |
1558 | ql_read32(qdev, NIC_ETS)); | |
1559 | printk(KERN_ERR PFX "CNA_ETS = 0x%x.\n", | |
1560 | ql_read32(qdev, CNA_ETS)); | |
1561 | printk(KERN_ERR PFX "FLASH_ADDR = 0x%x.\n", | |
1562 | ql_read32(qdev, FLASH_ADDR)); | |
1563 | printk(KERN_ERR PFX "FLASH_DATA = 0x%x.\n", | |
1564 | ql_read32(qdev, FLASH_DATA)); | |
1565 | printk(KERN_ERR PFX "CQ_STOP = 0x%x.\n", | |
1566 | ql_read32(qdev, CQ_STOP)); | |
1567 | printk(KERN_ERR PFX "PAGE_TBL_RID = 0x%x.\n", | |
1568 | ql_read32(qdev, PAGE_TBL_RID)); | |
1569 | printk(KERN_ERR PFX "WQ_PAGE_TBL_LO = 0x%x.\n", | |
1570 | ql_read32(qdev, WQ_PAGE_TBL_LO)); | |
1571 | printk(KERN_ERR PFX "WQ_PAGE_TBL_HI = 0x%x.\n", | |
1572 | ql_read32(qdev, WQ_PAGE_TBL_HI)); | |
1573 | printk(KERN_ERR PFX "CQ_PAGE_TBL_LO = 0x%x.\n", | |
1574 | ql_read32(qdev, CQ_PAGE_TBL_LO)); | |
1575 | printk(KERN_ERR PFX "CQ_PAGE_TBL_HI = 0x%x.\n", | |
1576 | ql_read32(qdev, CQ_PAGE_TBL_HI)); | |
1577 | printk(KERN_ERR PFX "COS_DFLT_CQ1 = 0x%x.\n", | |
1578 | ql_read32(qdev, COS_DFLT_CQ1)); | |
1579 | printk(KERN_ERR PFX "COS_DFLT_CQ2 = 0x%x.\n", | |
1580 | ql_read32(qdev, COS_DFLT_CQ2)); | |
1581 | printk(KERN_ERR PFX "SPLT_HDR = 0x%x.\n", | |
1582 | ql_read32(qdev, SPLT_HDR)); | |
1583 | printk(KERN_ERR PFX "FC_PAUSE_THRES = 0x%x.\n", | |
1584 | ql_read32(qdev, FC_PAUSE_THRES)); | |
1585 | printk(KERN_ERR PFX "NIC_PAUSE_THRES = 0x%x.\n", | |
1586 | ql_read32(qdev, NIC_PAUSE_THRES)); | |
1587 | printk(KERN_ERR PFX "FC_ETHERTYPE = 0x%x.\n", | |
1588 | ql_read32(qdev, FC_ETHERTYPE)); | |
1589 | printk(KERN_ERR PFX "FC_RCV_CFG = 0x%x.\n", | |
1590 | ql_read32(qdev, FC_RCV_CFG)); | |
1591 | printk(KERN_ERR PFX "NIC_RCV_CFG = 0x%x.\n", | |
1592 | ql_read32(qdev, NIC_RCV_CFG)); | |
1593 | printk(KERN_ERR PFX "FC_COS_TAGS = 0x%x.\n", | |
1594 | ql_read32(qdev, FC_COS_TAGS)); | |
1595 | printk(KERN_ERR PFX "NIC_COS_TAGS = 0x%x.\n", | |
1596 | ql_read32(qdev, NIC_COS_TAGS)); | |
1597 | printk(KERN_ERR PFX "MGMT_RCV_CFG = 0x%x.\n", | |
1598 | ql_read32(qdev, MGMT_RCV_CFG)); | |
1599 | printk(KERN_ERR PFX "XG_SERDES_ADDR = 0x%x.\n", | |
1600 | ql_read32(qdev, XG_SERDES_ADDR)); | |
1601 | printk(KERN_ERR PFX "XG_SERDES_DATA = 0x%x.\n", | |
1602 | ql_read32(qdev, XG_SERDES_DATA)); | |
1603 | printk(KERN_ERR PFX "PRB_MX_ADDR = 0x%x.\n", | |
1604 | ql_read32(qdev, PRB_MX_ADDR)); | |
1605 | printk(KERN_ERR PFX "PRB_MX_DATA = 0x%x.\n", | |
1606 | ql_read32(qdev, PRB_MX_DATA)); | |
1607 | ql_dump_intr_states(qdev); | |
1608 | ql_dump_xgmac_control_regs(qdev); | |
1609 | ql_dump_ets_regs(qdev); | |
1610 | ql_dump_cam_entries(qdev); | |
1611 | ql_dump_routing_entries(qdev); | |
1612 | } | |
1613 | #endif | |
1614 | ||
1615 | #ifdef QL_STAT_DUMP | |
1616 | void ql_dump_stat(struct ql_adapter *qdev) | |
1617 | { | |
1618 | printk(KERN_ERR "%s: Enter.\n", __func__); | |
1619 | printk(KERN_ERR "tx_pkts = %ld\n", | |
1620 | (unsigned long)qdev->nic_stats.tx_pkts); | |
1621 | printk(KERN_ERR "tx_bytes = %ld\n", | |
1622 | (unsigned long)qdev->nic_stats.tx_bytes); | |
1623 | printk(KERN_ERR "tx_mcast_pkts = %ld.\n", | |
1624 | (unsigned long)qdev->nic_stats.tx_mcast_pkts); | |
1625 | printk(KERN_ERR "tx_bcast_pkts = %ld.\n", | |
1626 | (unsigned long)qdev->nic_stats.tx_bcast_pkts); | |
1627 | printk(KERN_ERR "tx_ucast_pkts = %ld.\n", | |
1628 | (unsigned long)qdev->nic_stats.tx_ucast_pkts); | |
1629 | printk(KERN_ERR "tx_ctl_pkts = %ld.\n", | |
1630 | (unsigned long)qdev->nic_stats.tx_ctl_pkts); | |
1631 | printk(KERN_ERR "tx_pause_pkts = %ld.\n", | |
1632 | (unsigned long)qdev->nic_stats.tx_pause_pkts); | |
1633 | printk(KERN_ERR "tx_64_pkt = %ld.\n", | |
1634 | (unsigned long)qdev->nic_stats.tx_64_pkt); | |
1635 | printk(KERN_ERR "tx_65_to_127_pkt = %ld.\n", | |
1636 | (unsigned long)qdev->nic_stats.tx_65_to_127_pkt); | |
1637 | printk(KERN_ERR "tx_128_to_255_pkt = %ld.\n", | |
1638 | (unsigned long)qdev->nic_stats.tx_128_to_255_pkt); | |
1639 | printk(KERN_ERR "tx_256_511_pkt = %ld.\n", | |
1640 | (unsigned long)qdev->nic_stats.tx_256_511_pkt); | |
1641 | printk(KERN_ERR "tx_512_to_1023_pkt = %ld.\n", | |
1642 | (unsigned long)qdev->nic_stats.tx_512_to_1023_pkt); | |
1643 | printk(KERN_ERR "tx_1024_to_1518_pkt = %ld.\n", | |
1644 | (unsigned long)qdev->nic_stats.tx_1024_to_1518_pkt); | |
1645 | printk(KERN_ERR "tx_1519_to_max_pkt = %ld.\n", | |
1646 | (unsigned long)qdev->nic_stats.tx_1519_to_max_pkt); | |
1647 | printk(KERN_ERR "tx_undersize_pkt = %ld.\n", | |
1648 | (unsigned long)qdev->nic_stats.tx_undersize_pkt); | |
1649 | printk(KERN_ERR "tx_oversize_pkt = %ld.\n", | |
1650 | (unsigned long)qdev->nic_stats.tx_oversize_pkt); | |
1651 | printk(KERN_ERR "rx_bytes = %ld.\n", | |
1652 | (unsigned long)qdev->nic_stats.rx_bytes); | |
1653 | printk(KERN_ERR "rx_bytes_ok = %ld.\n", | |
1654 | (unsigned long)qdev->nic_stats.rx_bytes_ok); | |
1655 | printk(KERN_ERR "rx_pkts = %ld.\n", | |
1656 | (unsigned long)qdev->nic_stats.rx_pkts); | |
1657 | printk(KERN_ERR "rx_pkts_ok = %ld.\n", | |
1658 | (unsigned long)qdev->nic_stats.rx_pkts_ok); | |
1659 | printk(KERN_ERR "rx_bcast_pkts = %ld.\n", | |
1660 | (unsigned long)qdev->nic_stats.rx_bcast_pkts); | |
1661 | printk(KERN_ERR "rx_mcast_pkts = %ld.\n", | |
1662 | (unsigned long)qdev->nic_stats.rx_mcast_pkts); | |
1663 | printk(KERN_ERR "rx_ucast_pkts = %ld.\n", | |
1664 | (unsigned long)qdev->nic_stats.rx_ucast_pkts); | |
1665 | printk(KERN_ERR "rx_undersize_pkts = %ld.\n", | |
1666 | (unsigned long)qdev->nic_stats.rx_undersize_pkts); | |
1667 | printk(KERN_ERR "rx_oversize_pkts = %ld.\n", | |
1668 | (unsigned long)qdev->nic_stats.rx_oversize_pkts); | |
1669 | printk(KERN_ERR "rx_jabber_pkts = %ld.\n", | |
1670 | (unsigned long)qdev->nic_stats.rx_jabber_pkts); | |
1671 | printk(KERN_ERR "rx_undersize_fcerr_pkts = %ld.\n", | |
1672 | (unsigned long)qdev->nic_stats.rx_undersize_fcerr_pkts); | |
1673 | printk(KERN_ERR "rx_drop_events = %ld.\n", | |
1674 | (unsigned long)qdev->nic_stats.rx_drop_events); | |
1675 | printk(KERN_ERR "rx_fcerr_pkts = %ld.\n", | |
1676 | (unsigned long)qdev->nic_stats.rx_fcerr_pkts); | |
1677 | printk(KERN_ERR "rx_align_err = %ld.\n", | |
1678 | (unsigned long)qdev->nic_stats.rx_align_err); | |
1679 | printk(KERN_ERR "rx_symbol_err = %ld.\n", | |
1680 | (unsigned long)qdev->nic_stats.rx_symbol_err); | |
1681 | printk(KERN_ERR "rx_mac_err = %ld.\n", | |
1682 | (unsigned long)qdev->nic_stats.rx_mac_err); | |
1683 | printk(KERN_ERR "rx_ctl_pkts = %ld.\n", | |
1684 | (unsigned long)qdev->nic_stats.rx_ctl_pkts); | |
1685 | printk(KERN_ERR "rx_pause_pkts = %ld.\n", | |
1686 | (unsigned long)qdev->nic_stats.rx_pause_pkts); | |
1687 | printk(KERN_ERR "rx_64_pkts = %ld.\n", | |
1688 | (unsigned long)qdev->nic_stats.rx_64_pkts); | |
1689 | printk(KERN_ERR "rx_65_to_127_pkts = %ld.\n", | |
1690 | (unsigned long)qdev->nic_stats.rx_65_to_127_pkts); | |
1691 | printk(KERN_ERR "rx_128_255_pkts = %ld.\n", | |
1692 | (unsigned long)qdev->nic_stats.rx_128_255_pkts); | |
1693 | printk(KERN_ERR "rx_256_511_pkts = %ld.\n", | |
1694 | (unsigned long)qdev->nic_stats.rx_256_511_pkts); | |
1695 | printk(KERN_ERR "rx_512_to_1023_pkts = %ld.\n", | |
1696 | (unsigned long)qdev->nic_stats.rx_512_to_1023_pkts); | |
1697 | printk(KERN_ERR "rx_1024_to_1518_pkts = %ld.\n", | |
1698 | (unsigned long)qdev->nic_stats.rx_1024_to_1518_pkts); | |
1699 | printk(KERN_ERR "rx_1519_to_max_pkts = %ld.\n", | |
1700 | (unsigned long)qdev->nic_stats.rx_1519_to_max_pkts); | |
1701 | printk(KERN_ERR "rx_len_err_pkts = %ld.\n", | |
1702 | (unsigned long)qdev->nic_stats.rx_len_err_pkts); | |
1703 | }; | |
1704 | #endif | |
1705 | ||
1706 | #ifdef QL_DEV_DUMP | |
1707 | void ql_dump_qdev(struct ql_adapter *qdev) | |
1708 | { | |
1709 | int i; | |
1710 | printk(KERN_ERR PFX "qdev->flags = %lx.\n", | |
1711 | qdev->flags); | |
1712 | printk(KERN_ERR PFX "qdev->vlgrp = %p.\n", | |
1713 | qdev->vlgrp); | |
1714 | printk(KERN_ERR PFX "qdev->pdev = %p.\n", | |
1715 | qdev->pdev); | |
1716 | printk(KERN_ERR PFX "qdev->ndev = %p.\n", | |
1717 | qdev->ndev); | |
1718 | printk(KERN_ERR PFX "qdev->chip_rev_id = %d.\n", | |
1719 | qdev->chip_rev_id); | |
1720 | printk(KERN_ERR PFX "qdev->reg_base = %p.\n", | |
1721 | qdev->reg_base); | |
1722 | printk(KERN_ERR PFX "qdev->doorbell_area = %p.\n", | |
1723 | qdev->doorbell_area); | |
1724 | printk(KERN_ERR PFX "qdev->doorbell_area_size = %d.\n", | |
1725 | qdev->doorbell_area_size); | |
1726 | printk(KERN_ERR PFX "msg_enable = %x.\n", | |
1727 | qdev->msg_enable); | |
1728 | printk(KERN_ERR PFX "qdev->rx_ring_shadow_reg_area = %p.\n", | |
1729 | qdev->rx_ring_shadow_reg_area); | |
53159d06 DM |
1730 | printk(KERN_ERR PFX "qdev->rx_ring_shadow_reg_dma = %llx.\n", |
1731 | (unsigned long long) qdev->rx_ring_shadow_reg_dma); | |
c4e84bde RM |
1732 | printk(KERN_ERR PFX "qdev->tx_ring_shadow_reg_area = %p.\n", |
1733 | qdev->tx_ring_shadow_reg_area); | |
53159d06 DM |
1734 | printk(KERN_ERR PFX "qdev->tx_ring_shadow_reg_dma = %llx.\n", |
1735 | (unsigned long long) qdev->tx_ring_shadow_reg_dma); | |
c4e84bde RM |
1736 | printk(KERN_ERR PFX "qdev->intr_count = %d.\n", |
1737 | qdev->intr_count); | |
1738 | if (qdev->msi_x_entry) | |
1739 | for (i = 0; i < qdev->intr_count; i++) { | |
1740 | printk(KERN_ERR PFX | |
1741 | "msi_x_entry.[%d]vector = %d.\n", i, | |
1742 | qdev->msi_x_entry[i].vector); | |
1743 | printk(KERN_ERR PFX | |
1744 | "msi_x_entry.[%d]entry = %d.\n", i, | |
1745 | qdev->msi_x_entry[i].entry); | |
1746 | } | |
1747 | for (i = 0; i < qdev->intr_count; i++) { | |
1748 | printk(KERN_ERR PFX | |
1749 | "intr_context[%d].qdev = %p.\n", i, | |
1750 | qdev->intr_context[i].qdev); | |
1751 | printk(KERN_ERR PFX | |
1752 | "intr_context[%d].intr = %d.\n", i, | |
1753 | qdev->intr_context[i].intr); | |
1754 | printk(KERN_ERR PFX | |
1755 | "intr_context[%d].hooked = %d.\n", i, | |
1756 | qdev->intr_context[i].hooked); | |
1757 | printk(KERN_ERR PFX | |
1758 | "intr_context[%d].intr_en_mask = 0x%08x.\n", i, | |
1759 | qdev->intr_context[i].intr_en_mask); | |
1760 | printk(KERN_ERR PFX | |
1761 | "intr_context[%d].intr_dis_mask = 0x%08x.\n", i, | |
1762 | qdev->intr_context[i].intr_dis_mask); | |
1763 | printk(KERN_ERR PFX | |
1764 | "intr_context[%d].intr_read_mask = 0x%08x.\n", i, | |
1765 | qdev->intr_context[i].intr_read_mask); | |
1766 | } | |
1767 | printk(KERN_ERR PFX "qdev->tx_ring_count = %d.\n", qdev->tx_ring_count); | |
1768 | printk(KERN_ERR PFX "qdev->rx_ring_count = %d.\n", qdev->rx_ring_count); | |
1769 | printk(KERN_ERR PFX "qdev->ring_mem_size = %d.\n", qdev->ring_mem_size); | |
1770 | printk(KERN_ERR PFX "qdev->ring_mem = %p.\n", qdev->ring_mem); | |
1771 | printk(KERN_ERR PFX "qdev->intr_count = %d.\n", qdev->intr_count); | |
1772 | printk(KERN_ERR PFX "qdev->tx_ring = %p.\n", | |
1773 | qdev->tx_ring); | |
c4e84bde RM |
1774 | printk(KERN_ERR PFX "qdev->rss_ring_count = %d.\n", |
1775 | qdev->rss_ring_count); | |
1776 | printk(KERN_ERR PFX "qdev->rx_ring = %p.\n", qdev->rx_ring); | |
1777 | printk(KERN_ERR PFX "qdev->default_rx_queue = %d.\n", | |
1778 | qdev->default_rx_queue); | |
1779 | printk(KERN_ERR PFX "qdev->xg_sem_mask = 0x%08x.\n", | |
1780 | qdev->xg_sem_mask); | |
1781 | printk(KERN_ERR PFX "qdev->port_link_up = 0x%08x.\n", | |
1782 | qdev->port_link_up); | |
1783 | printk(KERN_ERR PFX "qdev->port_init = 0x%08x.\n", | |
1784 | qdev->port_init); | |
1785 | ||
1786 | } | |
1787 | #endif | |
1788 | ||
1789 | #ifdef QL_CB_DUMP | |
1790 | void ql_dump_wqicb(struct wqicb *wqicb) | |
1791 | { | |
1792 | printk(KERN_ERR PFX "Dumping wqicb stuff...\n"); | |
1793 | printk(KERN_ERR PFX "wqicb->len = 0x%x.\n", le16_to_cpu(wqicb->len)); | |
1794 | printk(KERN_ERR PFX "wqicb->flags = %x.\n", le16_to_cpu(wqicb->flags)); | |
1795 | printk(KERN_ERR PFX "wqicb->cq_id_rss = %d.\n", | |
1796 | le16_to_cpu(wqicb->cq_id_rss)); | |
1797 | printk(KERN_ERR PFX "wqicb->rid = 0x%x.\n", le16_to_cpu(wqicb->rid)); | |
97345524 RM |
1798 | printk(KERN_ERR PFX "wqicb->wq_addr = 0x%llx.\n", |
1799 | (unsigned long long) le64_to_cpu(wqicb->addr)); | |
1800 | printk(KERN_ERR PFX "wqicb->wq_cnsmr_idx_addr = 0x%llx.\n", | |
1801 | (unsigned long long) le64_to_cpu(wqicb->cnsmr_idx_addr)); | |
c4e84bde RM |
1802 | } |
1803 | ||
1804 | void ql_dump_tx_ring(struct tx_ring *tx_ring) | |
1805 | { | |
1806 | if (tx_ring == NULL) | |
1807 | return; | |
1808 | printk(KERN_ERR PFX | |
1809 | "===================== Dumping tx_ring %d ===============.\n", | |
1810 | tx_ring->wq_id); | |
1811 | printk(KERN_ERR PFX "tx_ring->base = %p.\n", tx_ring->wq_base); | |
1812 | printk(KERN_ERR PFX "tx_ring->base_dma = 0x%llx.\n", | |
53159d06 | 1813 | (unsigned long long) tx_ring->wq_base_dma); |
ba7cd3ba RM |
1814 | printk(KERN_ERR PFX |
1815 | "tx_ring->cnsmr_idx_sh_reg, addr = 0x%p, value = %d.\n", | |
1816 | tx_ring->cnsmr_idx_sh_reg, | |
1817 | tx_ring->cnsmr_idx_sh_reg | |
1818 | ? ql_read_sh_reg(tx_ring->cnsmr_idx_sh_reg) : 0); | |
c4e84bde RM |
1819 | printk(KERN_ERR PFX "tx_ring->size = %d.\n", tx_ring->wq_size); |
1820 | printk(KERN_ERR PFX "tx_ring->len = %d.\n", tx_ring->wq_len); | |
1821 | printk(KERN_ERR PFX "tx_ring->prod_idx_db_reg = %p.\n", | |
1822 | tx_ring->prod_idx_db_reg); | |
1823 | printk(KERN_ERR PFX "tx_ring->valid_db_reg = %p.\n", | |
1824 | tx_ring->valid_db_reg); | |
1825 | printk(KERN_ERR PFX "tx_ring->prod_idx = %d.\n", tx_ring->prod_idx); | |
1826 | printk(KERN_ERR PFX "tx_ring->cq_id = %d.\n", tx_ring->cq_id); | |
1827 | printk(KERN_ERR PFX "tx_ring->wq_id = %d.\n", tx_ring->wq_id); | |
1828 | printk(KERN_ERR PFX "tx_ring->q = %p.\n", tx_ring->q); | |
1829 | printk(KERN_ERR PFX "tx_ring->tx_count = %d.\n", | |
1830 | atomic_read(&tx_ring->tx_count)); | |
1831 | } | |
1832 | ||
1833 | void ql_dump_ricb(struct ricb *ricb) | |
1834 | { | |
1835 | int i; | |
1836 | printk(KERN_ERR PFX | |
1837 | "===================== Dumping ricb ===============.\n"); | |
1838 | printk(KERN_ERR PFX "Dumping ricb stuff...\n"); | |
1839 | ||
1840 | printk(KERN_ERR PFX "ricb->base_cq = %d.\n", ricb->base_cq & 0x1f); | |
1841 | printk(KERN_ERR PFX "ricb->flags = %s%s%s%s%s%s%s%s%s.\n", | |
1842 | ricb->base_cq & RSS_L4K ? "RSS_L4K " : "", | |
1843 | ricb->flags & RSS_L6K ? "RSS_L6K " : "", | |
1844 | ricb->flags & RSS_LI ? "RSS_LI " : "", | |
1845 | ricb->flags & RSS_LB ? "RSS_LB " : "", | |
1846 | ricb->flags & RSS_LM ? "RSS_LM " : "", | |
1847 | ricb->flags & RSS_RI4 ? "RSS_RI4 " : "", | |
1848 | ricb->flags & RSS_RT4 ? "RSS_RT4 " : "", | |
1849 | ricb->flags & RSS_RI6 ? "RSS_RI6 " : "", | |
1850 | ricb->flags & RSS_RT6 ? "RSS_RT6 " : ""); | |
1851 | printk(KERN_ERR PFX "ricb->mask = 0x%.04x.\n", le16_to_cpu(ricb->mask)); | |
1852 | for (i = 0; i < 16; i++) | |
1853 | printk(KERN_ERR PFX "ricb->hash_cq_id[%d] = 0x%.08x.\n", i, | |
1854 | le32_to_cpu(ricb->hash_cq_id[i])); | |
1855 | for (i = 0; i < 10; i++) | |
1856 | printk(KERN_ERR PFX "ricb->ipv6_hash_key[%d] = 0x%.08x.\n", i, | |
1857 | le32_to_cpu(ricb->ipv6_hash_key[i])); | |
1858 | for (i = 0; i < 4; i++) | |
1859 | printk(KERN_ERR PFX "ricb->ipv4_hash_key[%d] = 0x%.08x.\n", i, | |
1860 | le32_to_cpu(ricb->ipv4_hash_key[i])); | |
1861 | } | |
1862 | ||
1863 | void ql_dump_cqicb(struct cqicb *cqicb) | |
1864 | { | |
1865 | printk(KERN_ERR PFX "Dumping cqicb stuff...\n"); | |
1866 | ||
1867 | printk(KERN_ERR PFX "cqicb->msix_vect = %d.\n", cqicb->msix_vect); | |
1868 | printk(KERN_ERR PFX "cqicb->flags = %x.\n", cqicb->flags); | |
1869 | printk(KERN_ERR PFX "cqicb->len = %d.\n", le16_to_cpu(cqicb->len)); | |
97345524 RM |
1870 | printk(KERN_ERR PFX "cqicb->addr = 0x%llx.\n", |
1871 | (unsigned long long) le64_to_cpu(cqicb->addr)); | |
1872 | printk(KERN_ERR PFX "cqicb->prod_idx_addr = 0x%llx.\n", | |
1873 | (unsigned long long) le64_to_cpu(cqicb->prod_idx_addr)); | |
c4e84bde RM |
1874 | printk(KERN_ERR PFX "cqicb->pkt_delay = 0x%.04x.\n", |
1875 | le16_to_cpu(cqicb->pkt_delay)); | |
1876 | printk(KERN_ERR PFX "cqicb->irq_delay = 0x%.04x.\n", | |
1877 | le16_to_cpu(cqicb->irq_delay)); | |
97345524 RM |
1878 | printk(KERN_ERR PFX "cqicb->lbq_addr = 0x%llx.\n", |
1879 | (unsigned long long) le64_to_cpu(cqicb->lbq_addr)); | |
c4e84bde RM |
1880 | printk(KERN_ERR PFX "cqicb->lbq_buf_size = 0x%.04x.\n", |
1881 | le16_to_cpu(cqicb->lbq_buf_size)); | |
1882 | printk(KERN_ERR PFX "cqicb->lbq_len = 0x%.04x.\n", | |
1883 | le16_to_cpu(cqicb->lbq_len)); | |
97345524 RM |
1884 | printk(KERN_ERR PFX "cqicb->sbq_addr = 0x%llx.\n", |
1885 | (unsigned long long) le64_to_cpu(cqicb->sbq_addr)); | |
c4e84bde RM |
1886 | printk(KERN_ERR PFX "cqicb->sbq_buf_size = 0x%.04x.\n", |
1887 | le16_to_cpu(cqicb->sbq_buf_size)); | |
1888 | printk(KERN_ERR PFX "cqicb->sbq_len = 0x%.04x.\n", | |
1889 | le16_to_cpu(cqicb->sbq_len)); | |
1890 | } | |
1891 | ||
1892 | void ql_dump_rx_ring(struct rx_ring *rx_ring) | |
1893 | { | |
1894 | if (rx_ring == NULL) | |
1895 | return; | |
1896 | printk(KERN_ERR PFX | |
1897 | "===================== Dumping rx_ring %d ===============.\n", | |
1898 | rx_ring->cq_id); | |
1899 | printk(KERN_ERR PFX "Dumping rx_ring %d, type = %s%s%s.\n", | |
1900 | rx_ring->cq_id, rx_ring->type == DEFAULT_Q ? "DEFAULT" : "", | |
1901 | rx_ring->type == TX_Q ? "OUTBOUND COMPLETIONS" : "", | |
1902 | rx_ring->type == RX_Q ? "INBOUND_COMPLETIONS" : ""); | |
1903 | printk(KERN_ERR PFX "rx_ring->cqicb = %p.\n", &rx_ring->cqicb); | |
1904 | printk(KERN_ERR PFX "rx_ring->cq_base = %p.\n", rx_ring->cq_base); | |
1905 | printk(KERN_ERR PFX "rx_ring->cq_base_dma = %llx.\n", | |
53159d06 | 1906 | (unsigned long long) rx_ring->cq_base_dma); |
c4e84bde RM |
1907 | printk(KERN_ERR PFX "rx_ring->cq_size = %d.\n", rx_ring->cq_size); |
1908 | printk(KERN_ERR PFX "rx_ring->cq_len = %d.\n", rx_ring->cq_len); | |
1909 | printk(KERN_ERR PFX | |
ba7cd3ba | 1910 | "rx_ring->prod_idx_sh_reg, addr = 0x%p, value = %d.\n", |
c4e84bde | 1911 | rx_ring->prod_idx_sh_reg, |
ba7cd3ba RM |
1912 | rx_ring->prod_idx_sh_reg |
1913 | ? ql_read_sh_reg(rx_ring->prod_idx_sh_reg) : 0); | |
c4e84bde | 1914 | printk(KERN_ERR PFX "rx_ring->prod_idx_sh_reg_dma = %llx.\n", |
53159d06 | 1915 | (unsigned long long) rx_ring->prod_idx_sh_reg_dma); |
c4e84bde RM |
1916 | printk(KERN_ERR PFX "rx_ring->cnsmr_idx_db_reg = %p.\n", |
1917 | rx_ring->cnsmr_idx_db_reg); | |
1918 | printk(KERN_ERR PFX "rx_ring->cnsmr_idx = %d.\n", rx_ring->cnsmr_idx); | |
1919 | printk(KERN_ERR PFX "rx_ring->curr_entry = %p.\n", rx_ring->curr_entry); | |
1920 | printk(KERN_ERR PFX "rx_ring->valid_db_reg = %p.\n", | |
1921 | rx_ring->valid_db_reg); | |
1922 | ||
1923 | printk(KERN_ERR PFX "rx_ring->lbq_base = %p.\n", rx_ring->lbq_base); | |
1924 | printk(KERN_ERR PFX "rx_ring->lbq_base_dma = %llx.\n", | |
53159d06 | 1925 | (unsigned long long) rx_ring->lbq_base_dma); |
c4e84bde RM |
1926 | printk(KERN_ERR PFX "rx_ring->lbq_base_indirect = %p.\n", |
1927 | rx_ring->lbq_base_indirect); | |
1928 | printk(KERN_ERR PFX "rx_ring->lbq_base_indirect_dma = %llx.\n", | |
53159d06 | 1929 | (unsigned long long) rx_ring->lbq_base_indirect_dma); |
c4e84bde RM |
1930 | printk(KERN_ERR PFX "rx_ring->lbq = %p.\n", rx_ring->lbq); |
1931 | printk(KERN_ERR PFX "rx_ring->lbq_len = %d.\n", rx_ring->lbq_len); | |
1932 | printk(KERN_ERR PFX "rx_ring->lbq_size = %d.\n", rx_ring->lbq_size); | |
1933 | printk(KERN_ERR PFX "rx_ring->lbq_prod_idx_db_reg = %p.\n", | |
1934 | rx_ring->lbq_prod_idx_db_reg); | |
1935 | printk(KERN_ERR PFX "rx_ring->lbq_prod_idx = %d.\n", | |
1936 | rx_ring->lbq_prod_idx); | |
1937 | printk(KERN_ERR PFX "rx_ring->lbq_curr_idx = %d.\n", | |
1938 | rx_ring->lbq_curr_idx); | |
1939 | printk(KERN_ERR PFX "rx_ring->lbq_clean_idx = %d.\n", | |
1940 | rx_ring->lbq_clean_idx); | |
1941 | printk(KERN_ERR PFX "rx_ring->lbq_free_cnt = %d.\n", | |
1942 | rx_ring->lbq_free_cnt); | |
1943 | printk(KERN_ERR PFX "rx_ring->lbq_buf_size = %d.\n", | |
1944 | rx_ring->lbq_buf_size); | |
1945 | ||
1946 | printk(KERN_ERR PFX "rx_ring->sbq_base = %p.\n", rx_ring->sbq_base); | |
1947 | printk(KERN_ERR PFX "rx_ring->sbq_base_dma = %llx.\n", | |
53159d06 | 1948 | (unsigned long long) rx_ring->sbq_base_dma); |
c4e84bde RM |
1949 | printk(KERN_ERR PFX "rx_ring->sbq_base_indirect = %p.\n", |
1950 | rx_ring->sbq_base_indirect); | |
1951 | printk(KERN_ERR PFX "rx_ring->sbq_base_indirect_dma = %llx.\n", | |
53159d06 | 1952 | (unsigned long long) rx_ring->sbq_base_indirect_dma); |
c4e84bde RM |
1953 | printk(KERN_ERR PFX "rx_ring->sbq = %p.\n", rx_ring->sbq); |
1954 | printk(KERN_ERR PFX "rx_ring->sbq_len = %d.\n", rx_ring->sbq_len); | |
1955 | printk(KERN_ERR PFX "rx_ring->sbq_size = %d.\n", rx_ring->sbq_size); | |
1956 | printk(KERN_ERR PFX "rx_ring->sbq_prod_idx_db_reg addr = %p.\n", | |
1957 | rx_ring->sbq_prod_idx_db_reg); | |
1958 | printk(KERN_ERR PFX "rx_ring->sbq_prod_idx = %d.\n", | |
1959 | rx_ring->sbq_prod_idx); | |
1960 | printk(KERN_ERR PFX "rx_ring->sbq_curr_idx = %d.\n", | |
1961 | rx_ring->sbq_curr_idx); | |
1962 | printk(KERN_ERR PFX "rx_ring->sbq_clean_idx = %d.\n", | |
1963 | rx_ring->sbq_clean_idx); | |
1964 | printk(KERN_ERR PFX "rx_ring->sbq_free_cnt = %d.\n", | |
1965 | rx_ring->sbq_free_cnt); | |
1966 | printk(KERN_ERR PFX "rx_ring->sbq_buf_size = %d.\n", | |
1967 | rx_ring->sbq_buf_size); | |
1968 | printk(KERN_ERR PFX "rx_ring->cq_id = %d.\n", rx_ring->cq_id); | |
1969 | printk(KERN_ERR PFX "rx_ring->irq = %d.\n", rx_ring->irq); | |
1970 | printk(KERN_ERR PFX "rx_ring->cpu = %d.\n", rx_ring->cpu); | |
1971 | printk(KERN_ERR PFX "rx_ring->qdev = %p.\n", rx_ring->qdev); | |
1972 | } | |
1973 | ||
1974 | void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id) | |
1975 | { | |
1976 | void *ptr; | |
1977 | ||
1978 | printk(KERN_ERR PFX "%s: Enter.\n", __func__); | |
1979 | ||
1980 | ptr = kmalloc(size, GFP_ATOMIC); | |
1981 | if (ptr == NULL) { | |
1982 | printk(KERN_ERR PFX "%s: Couldn't allocate a buffer.\n", | |
1983 | __func__); | |
1984 | return; | |
1985 | } | |
1986 | ||
1987 | if (ql_write_cfg(qdev, ptr, size, bit, q_id)) { | |
1988 | printk(KERN_ERR "%s: Failed to upload control block!\n", | |
1989 | __func__); | |
1990 | goto fail_it; | |
1991 | } | |
1992 | switch (bit) { | |
1993 | case CFG_DRQ: | |
1994 | ql_dump_wqicb((struct wqicb *)ptr); | |
1995 | break; | |
1996 | case CFG_DCQ: | |
1997 | ql_dump_cqicb((struct cqicb *)ptr); | |
1998 | break; | |
1999 | case CFG_DR: | |
2000 | ql_dump_ricb((struct ricb *)ptr); | |
2001 | break; | |
2002 | default: | |
2003 | printk(KERN_ERR PFX "%s: Invalid bit value = %x.\n", | |
2004 | __func__, bit); | |
2005 | break; | |
2006 | } | |
2007 | fail_it: | |
2008 | kfree(ptr); | |
2009 | } | |
2010 | #endif | |
2011 | ||
2012 | #ifdef QL_OB_DUMP | |
2013 | void ql_dump_tx_desc(struct tx_buf_desc *tbd) | |
2014 | { | |
2015 | printk(KERN_ERR PFX "tbd->addr = 0x%llx\n", | |
2016 | le64_to_cpu((u64) tbd->addr)); | |
2017 | printk(KERN_ERR PFX "tbd->len = %d\n", | |
2018 | le32_to_cpu(tbd->len & TX_DESC_LEN_MASK)); | |
2019 | printk(KERN_ERR PFX "tbd->flags = %s %s\n", | |
2020 | tbd->len & TX_DESC_C ? "C" : ".", | |
2021 | tbd->len & TX_DESC_E ? "E" : "."); | |
2022 | tbd++; | |
2023 | printk(KERN_ERR PFX "tbd->addr = 0x%llx\n", | |
2024 | le64_to_cpu((u64) tbd->addr)); | |
2025 | printk(KERN_ERR PFX "tbd->len = %d\n", | |
2026 | le32_to_cpu(tbd->len & TX_DESC_LEN_MASK)); | |
2027 | printk(KERN_ERR PFX "tbd->flags = %s %s\n", | |
2028 | tbd->len & TX_DESC_C ? "C" : ".", | |
2029 | tbd->len & TX_DESC_E ? "E" : "."); | |
2030 | tbd++; | |
2031 | printk(KERN_ERR PFX "tbd->addr = 0x%llx\n", | |
2032 | le64_to_cpu((u64) tbd->addr)); | |
2033 | printk(KERN_ERR PFX "tbd->len = %d\n", | |
2034 | le32_to_cpu(tbd->len & TX_DESC_LEN_MASK)); | |
2035 | printk(KERN_ERR PFX "tbd->flags = %s %s\n", | |
2036 | tbd->len & TX_DESC_C ? "C" : ".", | |
2037 | tbd->len & TX_DESC_E ? "E" : "."); | |
2038 | ||
2039 | } | |
2040 | ||
2041 | void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb) | |
2042 | { | |
2043 | struct ob_mac_tso_iocb_req *ob_mac_tso_iocb = | |
2044 | (struct ob_mac_tso_iocb_req *)ob_mac_iocb; | |
2045 | struct tx_buf_desc *tbd; | |
2046 | u16 frame_len; | |
2047 | ||
2048 | printk(KERN_ERR PFX "%s\n", __func__); | |
2049 | printk(KERN_ERR PFX "opcode = %s\n", | |
2050 | (ob_mac_iocb->opcode == OPCODE_OB_MAC_IOCB) ? "MAC" : "TSO"); | |
2051 | printk(KERN_ERR PFX "flags1 = %s %s %s %s %s\n", | |
2052 | ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_OI ? "OI" : "", | |
2053 | ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_I ? "I" : "", | |
2054 | ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_D ? "D" : "", | |
2055 | ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_IP4 ? "IP4" : "", | |
2056 | ob_mac_tso_iocb->flags1 & OB_MAC_TSO_IOCB_IP6 ? "IP6" : ""); | |
2057 | printk(KERN_ERR PFX "flags2 = %s %s %s\n", | |
2058 | ob_mac_tso_iocb->flags2 & OB_MAC_TSO_IOCB_LSO ? "LSO" : "", | |
2059 | ob_mac_tso_iocb->flags2 & OB_MAC_TSO_IOCB_UC ? "UC" : "", | |
2060 | ob_mac_tso_iocb->flags2 & OB_MAC_TSO_IOCB_TC ? "TC" : ""); | |
2061 | printk(KERN_ERR PFX "flags3 = %s %s %s \n", | |
2062 | ob_mac_tso_iocb->flags3 & OB_MAC_TSO_IOCB_IC ? "IC" : "", | |
2063 | ob_mac_tso_iocb->flags3 & OB_MAC_TSO_IOCB_DFP ? "DFP" : "", | |
2064 | ob_mac_tso_iocb->flags3 & OB_MAC_TSO_IOCB_V ? "V" : ""); | |
2065 | printk(KERN_ERR PFX "tid = %x\n", ob_mac_iocb->tid); | |
2066 | printk(KERN_ERR PFX "txq_idx = %d\n", ob_mac_iocb->txq_idx); | |
2067 | printk(KERN_ERR PFX "vlan_tci = %x\n", ob_mac_tso_iocb->vlan_tci); | |
2068 | if (ob_mac_iocb->opcode == OPCODE_OB_MAC_TSO_IOCB) { | |
2069 | printk(KERN_ERR PFX "frame_len = %d\n", | |
2070 | le32_to_cpu(ob_mac_tso_iocb->frame_len)); | |
2071 | printk(KERN_ERR PFX "mss = %d\n", | |
2072 | le16_to_cpu(ob_mac_tso_iocb->mss)); | |
2073 | printk(KERN_ERR PFX "prot_hdr_len = %d\n", | |
2074 | le16_to_cpu(ob_mac_tso_iocb->total_hdrs_len)); | |
2075 | printk(KERN_ERR PFX "hdr_offset = 0x%.04x\n", | |
2076 | le16_to_cpu(ob_mac_tso_iocb->net_trans_offset)); | |
2077 | frame_len = le32_to_cpu(ob_mac_tso_iocb->frame_len); | |
2078 | } else { | |
2079 | printk(KERN_ERR PFX "frame_len = %d\n", | |
2080 | le16_to_cpu(ob_mac_iocb->frame_len)); | |
2081 | frame_len = le16_to_cpu(ob_mac_iocb->frame_len); | |
2082 | } | |
2083 | tbd = &ob_mac_iocb->tbd[0]; | |
2084 | ql_dump_tx_desc(tbd); | |
2085 | } | |
2086 | ||
2087 | void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp) | |
2088 | { | |
2089 | printk(KERN_ERR PFX "%s\n", __func__); | |
2090 | printk(KERN_ERR PFX "opcode = %d\n", ob_mac_rsp->opcode); | |
2091 | printk(KERN_ERR PFX "flags = %s %s %s %s %s %s %s\n", | |
2092 | ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_OI ? "OI" : ".", | |
2093 | ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_I ? "I" : ".", | |
2094 | ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_E ? "E" : ".", | |
2095 | ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_S ? "S" : ".", | |
2096 | ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_L ? "L" : ".", | |
2097 | ob_mac_rsp->flags1 & OB_MAC_IOCB_RSP_P ? "P" : ".", | |
2098 | ob_mac_rsp->flags2 & OB_MAC_IOCB_RSP_B ? "B" : "."); | |
2099 | printk(KERN_ERR PFX "tid = %x\n", ob_mac_rsp->tid); | |
2100 | } | |
2101 | #endif | |
2102 | ||
2103 | #ifdef QL_IB_DUMP | |
2104 | void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp) | |
2105 | { | |
2106 | printk(KERN_ERR PFX "%s\n", __func__); | |
2107 | printk(KERN_ERR PFX "opcode = 0x%x\n", ib_mac_rsp->opcode); | |
2108 | printk(KERN_ERR PFX "flags1 = %s%s%s%s%s%s\n", | |
2109 | ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_OI ? "OI " : "", | |
2110 | ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_I ? "I " : "", | |
2111 | ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_TE ? "TE " : "", | |
2112 | ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_NU ? "NU " : "", | |
2113 | ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_IE ? "IE " : "", | |
2114 | ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_B ? "B " : ""); | |
2115 | ||
2116 | if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) | |
2117 | printk(KERN_ERR PFX "%s%s%s Multicast.\n", | |
2118 | (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) == | |
2119 | IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "", | |
2120 | (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) == | |
2121 | IB_MAC_IOCB_RSP_M_REG ? "Registered" : "", | |
2122 | (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) == | |
2123 | IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : ""); | |
2124 | ||
2125 | printk(KERN_ERR PFX "flags2 = %s%s%s%s%s\n", | |
2126 | (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) ? "P " : "", | |
2127 | (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ? "V " : "", | |
2128 | (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) ? "U " : "", | |
2129 | (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) ? "T " : "", | |
2130 | (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_FO) ? "FO " : ""); | |
2131 | ||
2132 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) | |
2133 | printk(KERN_ERR PFX "%s%s%s%s%s error.\n", | |
2134 | (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) == | |
2135 | IB_MAC_IOCB_RSP_ERR_OVERSIZE ? "oversize" : "", | |
2136 | (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) == | |
2137 | IB_MAC_IOCB_RSP_ERR_UNDERSIZE ? "undersize" : "", | |
2138 | (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) == | |
2139 | IB_MAC_IOCB_RSP_ERR_PREAMBLE ? "preamble" : "", | |
2140 | (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) == | |
2141 | IB_MAC_IOCB_RSP_ERR_FRAME_LEN ? "frame length" : "", | |
2142 | (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) == | |
2143 | IB_MAC_IOCB_RSP_ERR_CRC ? "CRC" : ""); | |
2144 | ||
2145 | printk(KERN_ERR PFX "flags3 = %s%s.\n", | |
2146 | ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS ? "DS " : "", | |
2147 | ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL ? "DL " : ""); | |
2148 | ||
2149 | if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) | |
2150 | printk(KERN_ERR PFX "RSS flags = %s%s%s%s.\n", | |
2151 | ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) == | |
2152 | IB_MAC_IOCB_RSP_M_IPV4) ? "IPv4 RSS" : "", | |
2153 | ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) == | |
2154 | IB_MAC_IOCB_RSP_M_IPV6) ? "IPv6 RSS " : "", | |
2155 | ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) == | |
2156 | IB_MAC_IOCB_RSP_M_TCP_V4) ? "TCP/IPv4 RSS" : "", | |
2157 | ((ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) == | |
2158 | IB_MAC_IOCB_RSP_M_TCP_V6) ? "TCP/IPv6 RSS" : ""); | |
2159 | ||
2160 | printk(KERN_ERR PFX "data_len = %d\n", | |
2161 | le32_to_cpu(ib_mac_rsp->data_len)); | |
97345524 RM |
2162 | printk(KERN_ERR PFX "data_addr = 0x%llx\n", |
2163 | (unsigned long long) le64_to_cpu(ib_mac_rsp->data_addr)); | |
c4e84bde RM |
2164 | if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_RSS_MASK) |
2165 | printk(KERN_ERR PFX "rss = %x\n", | |
2166 | le32_to_cpu(ib_mac_rsp->rss)); | |
2167 | if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) | |
2168 | printk(KERN_ERR PFX "vlan_id = %x\n", | |
2169 | le16_to_cpu(ib_mac_rsp->vlan_id)); | |
2170 | ||
2171 | printk(KERN_ERR PFX "flags4 = %s%s%s.\n", | |
a303ce09 RM |
2172 | ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV ? "HV " : "", |
2173 | ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS ? "HS " : "", | |
2174 | ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HL ? "HL " : ""); | |
2175 | ||
2176 | if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV) { | |
c4e84bde RM |
2177 | printk(KERN_ERR PFX "hdr length = %d.\n", |
2178 | le32_to_cpu(ib_mac_rsp->hdr_len)); | |
97345524 RM |
2179 | printk(KERN_ERR PFX "hdr addr = 0x%llx.\n", |
2180 | (unsigned long long) le64_to_cpu(ib_mac_rsp->hdr_addr)); | |
c4e84bde RM |
2181 | } |
2182 | } | |
2183 | #endif | |
2184 | ||
2185 | #ifdef QL_ALL_DUMP | |
2186 | void ql_dump_all(struct ql_adapter *qdev) | |
2187 | { | |
2188 | int i; | |
2189 | ||
2190 | QL_DUMP_REGS(qdev); | |
2191 | QL_DUMP_QDEV(qdev); | |
2192 | for (i = 0; i < qdev->tx_ring_count; i++) { | |
2193 | QL_DUMP_TX_RING(&qdev->tx_ring[i]); | |
2194 | QL_DUMP_WQICB((struct wqicb *)&qdev->tx_ring[i]); | |
2195 | } | |
2196 | for (i = 0; i < qdev->rx_ring_count; i++) { | |
2197 | QL_DUMP_RX_RING(&qdev->rx_ring[i]); | |
2198 | QL_DUMP_CQICB((struct cqicb *)&qdev->rx_ring[i]); | |
2199 | } | |
2200 | } | |
2201 | #endif |