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7a47dd7a SW |
1 | /* |
2 | * RDC R6040 Fast Ethernet MAC support | |
3 | * | |
4 | * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw> | |
5 | * Copyright (C) 2007 | |
5ac5d616 | 6 | * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us> |
7a47dd7a SW |
7 | * Florian Fainelli <florian@openwrt.org> |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version 2 | |
12 | * of the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the | |
21 | * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
22 | * Boston, MA 02110-1301, USA. | |
23 | */ | |
24 | ||
25 | #include <linux/kernel.h> | |
26 | #include <linux/module.h> | |
27 | #include <linux/version.h> | |
28 | #include <linux/moduleparam.h> | |
29 | #include <linux/string.h> | |
30 | #include <linux/timer.h> | |
31 | #include <linux/errno.h> | |
32 | #include <linux/ioport.h> | |
33 | #include <linux/slab.h> | |
34 | #include <linux/interrupt.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/netdevice.h> | |
37 | #include <linux/etherdevice.h> | |
38 | #include <linux/skbuff.h> | |
39 | #include <linux/init.h> | |
40 | #include <linux/delay.h> | |
41 | #include <linux/mii.h> | |
42 | #include <linux/ethtool.h> | |
43 | #include <linux/crc32.h> | |
44 | #include <linux/spinlock.h> | |
092427be JG |
45 | #include <linux/bitops.h> |
46 | #include <linux/io.h> | |
47 | #include <linux/irq.h> | |
48 | #include <linux/uaccess.h> | |
7a47dd7a SW |
49 | |
50 | #include <asm/processor.h> | |
7a47dd7a SW |
51 | |
52 | #define DRV_NAME "r6040" | |
53 | #define DRV_VERSION "0.16" | |
54 | #define DRV_RELDATE "10Nov2007" | |
55 | ||
56 | /* PHY CHIP Address */ | |
57 | #define PHY1_ADDR 1 /* For MAC1 */ | |
58 | #define PHY2_ADDR 2 /* For MAC2 */ | |
59 | #define PHY_MODE 0x3100 /* PHY CHIP Register 0 */ | |
60 | #define PHY_CAP 0x01E1 /* PHY CHIP Register 4 */ | |
61 | ||
62 | /* Time in jiffies before concluding the transmitter is hung. */ | |
5ac5d616 | 63 | #define TX_TIMEOUT (6000 * HZ / 1000) |
7a47dd7a SW |
64 | |
65 | /* RDC MAC I/O Size */ | |
66 | #define R6040_IO_SIZE 256 | |
67 | ||
68 | /* MAX RDC MAC */ | |
69 | #define MAX_MAC 2 | |
70 | ||
71 | /* MAC registers */ | |
72 | #define MCR0 0x00 /* Control register 0 */ | |
73 | #define MCR1 0x04 /* Control register 1 */ | |
74 | #define MAC_RST 0x0001 /* Reset the MAC */ | |
75 | #define MBCR 0x08 /* Bus control */ | |
76 | #define MT_ICR 0x0C /* TX interrupt control */ | |
77 | #define MR_ICR 0x10 /* RX interrupt control */ | |
78 | #define MTPR 0x14 /* TX poll command register */ | |
79 | #define MR_BSR 0x18 /* RX buffer size */ | |
80 | #define MR_DCR 0x1A /* RX descriptor control */ | |
81 | #define MLSR 0x1C /* Last status */ | |
82 | #define MMDIO 0x20 /* MDIO control register */ | |
83 | #define MDIO_WRITE 0x4000 /* MDIO write */ | |
84 | #define MDIO_READ 0x2000 /* MDIO read */ | |
85 | #define MMRD 0x24 /* MDIO read data register */ | |
86 | #define MMWD 0x28 /* MDIO write data register */ | |
87 | #define MTD_SA0 0x2C /* TX descriptor start address 0 */ | |
88 | #define MTD_SA1 0x30 /* TX descriptor start address 1 */ | |
89 | #define MRD_SA0 0x34 /* RX descriptor start address 0 */ | |
90 | #define MRD_SA1 0x38 /* RX descriptor start address 1 */ | |
91 | #define MISR 0x3C /* Status register */ | |
92 | #define MIER 0x40 /* INT enable register */ | |
93 | #define MSK_INT 0x0000 /* Mask off interrupts */ | |
3d254348 FF |
94 | #define RX_FINISH 0x0001 /* RX finished */ |
95 | #define RX_NO_DESC 0x0002 /* No RX descriptor available */ | |
96 | #define RX_FIFO_FULL 0x0004 /* RX FIFO full */ | |
97 | #define RX_EARLY 0x0008 /* RX early */ | |
98 | #define TX_FINISH 0x0010 /* TX finished */ | |
99 | #define TX_EARLY 0x0080 /* TX early */ | |
100 | #define EVENT_OVRFL 0x0100 /* Event counter overflow */ | |
101 | #define LINK_CHANGED 0x0200 /* PHY link changed */ | |
7a47dd7a SW |
102 | #define ME_CISR 0x44 /* Event counter INT status */ |
103 | #define ME_CIER 0x48 /* Event counter INT enable */ | |
104 | #define MR_CNT 0x50 /* Successfully received packet counter */ | |
105 | #define ME_CNT0 0x52 /* Event counter 0 */ | |
106 | #define ME_CNT1 0x54 /* Event counter 1 */ | |
107 | #define ME_CNT2 0x56 /* Event counter 2 */ | |
108 | #define ME_CNT3 0x58 /* Event counter 3 */ | |
109 | #define MT_CNT 0x5A /* Successfully transmit packet counter */ | |
110 | #define ME_CNT4 0x5C /* Event counter 4 */ | |
111 | #define MP_CNT 0x5E /* Pause frame counter register */ | |
112 | #define MAR0 0x60 /* Hash table 0 */ | |
113 | #define MAR1 0x62 /* Hash table 1 */ | |
114 | #define MAR2 0x64 /* Hash table 2 */ | |
115 | #define MAR3 0x66 /* Hash table 3 */ | |
116 | #define MID_0L 0x68 /* Multicast address MID0 Low */ | |
117 | #define MID_0M 0x6A /* Multicast address MID0 Medium */ | |
118 | #define MID_0H 0x6C /* Multicast address MID0 High */ | |
119 | #define MID_1L 0x70 /* MID1 Low */ | |
120 | #define MID_1M 0x72 /* MID1 Medium */ | |
121 | #define MID_1H 0x74 /* MID1 High */ | |
122 | #define MID_2L 0x78 /* MID2 Low */ | |
123 | #define MID_2M 0x7A /* MID2 Medium */ | |
124 | #define MID_2H 0x7C /* MID2 High */ | |
125 | #define MID_3L 0x80 /* MID3 Low */ | |
126 | #define MID_3M 0x82 /* MID3 Medium */ | |
127 | #define MID_3H 0x84 /* MID3 High */ | |
128 | #define PHY_CC 0x88 /* PHY status change configuration register */ | |
129 | #define PHY_ST 0x8A /* PHY status register */ | |
130 | #define MAC_SM 0xAC /* MAC status machine */ | |
131 | #define MAC_ID 0xBE /* Identifier register */ | |
132 | ||
133 | #define TX_DCNT 0x80 /* TX descriptor count */ | |
134 | #define RX_DCNT 0x80 /* RX descriptor count */ | |
135 | #define MAX_BUF_SIZE 0x600 | |
6c323103 FR |
136 | #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor)) |
137 | #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor)) | |
7a47dd7a SW |
138 | #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */ |
139 | #define MCAST_MAX 4 /* Max number multicast addresses to filter */ | |
140 | ||
141 | /* PHY settings */ | |
142 | #define ICPLUS_PHY_ID 0x0243 | |
143 | ||
144 | MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>," | |
145 | "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>," | |
146 | "Florian Fainelli <florian@openwrt.org>"); | |
147 | MODULE_LICENSE("GPL"); | |
148 | MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver"); | |
149 | ||
3d254348 FF |
150 | /* RX and TX interrupts that we handle */ |
151 | #define RX_INT (RX_FINISH) | |
152 | #define TX_INT (TX_FINISH) | |
153 | #define INT_MASK (RX_INT | TX_INT) | |
7a47dd7a SW |
154 | |
155 | struct r6040_descriptor { | |
156 | u16 status, len; /* 0-3 */ | |
157 | __le32 buf; /* 4-7 */ | |
158 | __le32 ndesc; /* 8-B */ | |
159 | u32 rev1; /* C-F */ | |
160 | char *vbufp; /* 10-13 */ | |
161 | struct r6040_descriptor *vndescp; /* 14-17 */ | |
162 | struct sk_buff *skb_ptr; /* 18-1B */ | |
163 | u32 rev2; /* 1C-1F */ | |
164 | } __attribute__((aligned(32))); | |
165 | ||
166 | struct r6040_private { | |
167 | spinlock_t lock; /* driver lock */ | |
168 | struct timer_list timer; | |
169 | struct pci_dev *pdev; | |
170 | struct r6040_descriptor *rx_insert_ptr; | |
171 | struct r6040_descriptor *rx_remove_ptr; | |
172 | struct r6040_descriptor *tx_insert_ptr; | |
173 | struct r6040_descriptor *tx_remove_ptr; | |
6c323103 FR |
174 | struct r6040_descriptor *rx_ring; |
175 | struct r6040_descriptor *tx_ring; | |
176 | dma_addr_t rx_ring_dma; | |
177 | dma_addr_t tx_ring_dma; | |
7a47dd7a SW |
178 | u16 tx_free_desc, rx_free_desc, phy_addr, phy_mode; |
179 | u16 mcr0, mcr1; | |
7a47dd7a SW |
180 | u16 switch_sig; |
181 | struct net_device *dev; | |
182 | struct mii_if_info mii_if; | |
183 | struct napi_struct napi; | |
7a47dd7a SW |
184 | void __iomem *base; |
185 | }; | |
186 | ||
187 | static char version[] __devinitdata = KERN_INFO DRV_NAME | |
188 | ": RDC R6040 NAPI net driver," | |
189 | "version "DRV_VERSION " (" DRV_RELDATE ")\n"; | |
190 | ||
092427be | 191 | static int phy_table[] = { PHY1_ADDR, PHY2_ADDR }; |
7a47dd7a SW |
192 | |
193 | /* Read a word data from PHY Chip */ | |
c6e69bb9 | 194 | static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg) |
7a47dd7a SW |
195 | { |
196 | int limit = 2048; | |
197 | u16 cmd; | |
198 | ||
199 | iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO); | |
200 | /* Wait for the read bit to be cleared */ | |
201 | while (limit--) { | |
202 | cmd = ioread16(ioaddr + MMDIO); | |
203 | if (cmd & MDIO_READ) | |
204 | break; | |
205 | } | |
206 | ||
207 | return ioread16(ioaddr + MMRD); | |
208 | } | |
209 | ||
210 | /* Write a word data from PHY Chip */ | |
c6e69bb9 | 211 | static void r6040_phy_write(void __iomem *ioaddr, int phy_addr, int reg, u16 val) |
7a47dd7a SW |
212 | { |
213 | int limit = 2048; | |
214 | u16 cmd; | |
215 | ||
216 | iowrite16(val, ioaddr + MMWD); | |
217 | /* Write the command to the MDIO bus */ | |
218 | iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO); | |
219 | /* Wait for the write bit to be cleared */ | |
220 | while (limit--) { | |
221 | cmd = ioread16(ioaddr + MMDIO); | |
222 | if (cmd & MDIO_WRITE) | |
223 | break; | |
224 | } | |
225 | } | |
226 | ||
c6e69bb9 | 227 | static int r6040_mdio_read(struct net_device *dev, int mii_id, int reg) |
7a47dd7a SW |
228 | { |
229 | struct r6040_private *lp = netdev_priv(dev); | |
230 | void __iomem *ioaddr = lp->base; | |
231 | ||
c6e69bb9 | 232 | return (r6040_phy_read(ioaddr, lp->phy_addr, reg)); |
7a47dd7a SW |
233 | } |
234 | ||
c6e69bb9 | 235 | static void r6040_mdio_write(struct net_device *dev, int mii_id, int reg, int val) |
7a47dd7a SW |
236 | { |
237 | struct r6040_private *lp = netdev_priv(dev); | |
238 | void __iomem *ioaddr = lp->base; | |
239 | ||
c6e69bb9 | 240 | r6040_phy_write(ioaddr, lp->phy_addr, reg, val); |
7a47dd7a SW |
241 | } |
242 | ||
b4f1255d FF |
243 | static void r6040_free_txbufs(struct net_device *dev) |
244 | { | |
245 | struct r6040_private *lp = netdev_priv(dev); | |
246 | int i; | |
247 | ||
248 | for (i = 0; i < TX_DCNT; i++) { | |
249 | if (lp->tx_insert_ptr->skb_ptr) { | |
ed773b4a AV |
250 | pci_unmap_single(lp->pdev, |
251 | le32_to_cpu(lp->tx_insert_ptr->buf), | |
b4f1255d FF |
252 | MAX_BUF_SIZE, PCI_DMA_TODEVICE); |
253 | dev_kfree_skb(lp->tx_insert_ptr->skb_ptr); | |
254 | lp->rx_insert_ptr->skb_ptr = NULL; | |
255 | } | |
256 | lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp; | |
257 | } | |
258 | } | |
259 | ||
260 | static void r6040_free_rxbufs(struct net_device *dev) | |
261 | { | |
262 | struct r6040_private *lp = netdev_priv(dev); | |
263 | int i; | |
264 | ||
265 | for (i = 0; i < RX_DCNT; i++) { | |
266 | if (lp->rx_insert_ptr->skb_ptr) { | |
ed773b4a AV |
267 | pci_unmap_single(lp->pdev, |
268 | le32_to_cpu(lp->rx_insert_ptr->buf), | |
b4f1255d FF |
269 | MAX_BUF_SIZE, PCI_DMA_FROMDEVICE); |
270 | dev_kfree_skb(lp->rx_insert_ptr->skb_ptr); | |
271 | lp->rx_insert_ptr->skb_ptr = NULL; | |
272 | } | |
273 | lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp; | |
274 | } | |
275 | } | |
276 | ||
b4f1255d FF |
277 | static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring, |
278 | dma_addr_t desc_dma, int size) | |
279 | { | |
280 | struct r6040_descriptor *desc = desc_ring; | |
281 | dma_addr_t mapping = desc_dma; | |
282 | ||
283 | while (size-- > 0) { | |
3f6602ad | 284 | mapping += sizeof(*desc); |
b4f1255d FF |
285 | desc->ndesc = cpu_to_le32(mapping); |
286 | desc->vndescp = desc + 1; | |
287 | desc++; | |
288 | } | |
289 | desc--; | |
290 | desc->ndesc = cpu_to_le32(desc_dma); | |
291 | desc->vndescp = desc_ring; | |
292 | } | |
293 | ||
7a47dd7a | 294 | /* Allocate skb buffer for rx descriptor */ |
c6e69bb9 | 295 | static void r6040_rx_buf_alloc(struct r6040_private *lp, struct net_device *dev) |
7a47dd7a SW |
296 | { |
297 | struct r6040_descriptor *descptr; | |
7a47dd7a SW |
298 | |
299 | descptr = lp->rx_insert_ptr; | |
300 | while (lp->rx_free_desc < RX_DCNT) { | |
ec6d2d45 | 301 | descptr->skb_ptr = netdev_alloc_skb(dev, MAX_BUF_SIZE); |
7a47dd7a SW |
302 | |
303 | if (!descptr->skb_ptr) | |
304 | break; | |
305 | descptr->buf = cpu_to_le32(pci_map_single(lp->pdev, | |
5125a786 | 306 | descptr->skb_ptr->data, |
7a47dd7a SW |
307 | MAX_BUF_SIZE, PCI_DMA_FROMDEVICE)); |
308 | descptr->status = 0x8000; | |
309 | descptr = descptr->vndescp; | |
310 | lp->rx_free_desc++; | |
7a47dd7a SW |
311 | } |
312 | lp->rx_insert_ptr = descptr; | |
313 | } | |
314 | ||
3d463419 | 315 | static void r6040_init_txbufs(struct net_device *dev) |
b4f1255d FF |
316 | { |
317 | struct r6040_private *lp = netdev_priv(dev); | |
b4f1255d FF |
318 | |
319 | lp->tx_free_desc = TX_DCNT; | |
320 | ||
321 | lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring; | |
322 | r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT); | |
b4f1255d FF |
323 | } |
324 | ||
3d463419 | 325 | static int r6040_alloc_rxbufs(struct net_device *dev) |
b4f1255d FF |
326 | { |
327 | struct r6040_private *lp = netdev_priv(dev); | |
3d463419 FF |
328 | struct r6040_descriptor *desc; |
329 | struct sk_buff *skb; | |
330 | int rc; | |
b4f1255d FF |
331 | |
332 | lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring; | |
333 | r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT); | |
334 | ||
3d463419 FF |
335 | /* Allocate skbs for the rx descriptors */ |
336 | desc = lp->rx_ring; | |
337 | do { | |
338 | skb = netdev_alloc_skb(dev, MAX_BUF_SIZE); | |
339 | if (!skb) { | |
340 | printk(KERN_ERR "%s: failed to alloc skb for rx\n", dev->name); | |
341 | rc = -ENOMEM; | |
342 | goto err_exit; | |
343 | } | |
344 | desc->skb_ptr = skb; | |
345 | desc->buf = cpu_to_le32(pci_map_single(lp->pdev, | |
346 | desc->skb_ptr->data, | |
347 | MAX_BUF_SIZE, PCI_DMA_FROMDEVICE)); | |
348 | desc->status = 0x8000; | |
349 | desc = desc->vndescp; | |
350 | } while (desc != lp->rx_ring); | |
351 | ||
352 | return 0; | |
353 | ||
354 | err_exit: | |
355 | /* Deallocate all previously allocated skbs */ | |
356 | r6040_free_rxbufs(dev); | |
357 | return rc; | |
fec3a23b FF |
358 | } |
359 | ||
360 | static void r6040_init_mac_regs(struct net_device *dev) | |
361 | { | |
362 | struct r6040_private *lp = netdev_priv(dev); | |
363 | void __iomem *ioaddr = lp->base; | |
364 | int limit = 2048; | |
365 | u16 cmd; | |
366 | ||
367 | /* Mask Off Interrupt */ | |
368 | iowrite16(MSK_INT, ioaddr + MIER); | |
369 | ||
370 | /* Reset RDC MAC */ | |
371 | iowrite16(MAC_RST, ioaddr + MCR1); | |
372 | while (limit--) { | |
373 | cmd = ioread16(ioaddr + MCR1); | |
374 | if (cmd & 0x1) | |
375 | break; | |
376 | } | |
377 | /* Reset internal state machine */ | |
378 | iowrite16(2, ioaddr + MAC_SM); | |
379 | iowrite16(0, ioaddr + MAC_SM); | |
380 | udelay(5000); | |
381 | ||
382 | /* MAC Bus Control Register */ | |
383 | iowrite16(MBCR_DEFAULT, ioaddr + MBCR); | |
384 | ||
385 | /* Buffer Size Register */ | |
386 | iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR); | |
387 | ||
388 | /* Write TX ring start address */ | |
389 | iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0); | |
390 | iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1); | |
b4f1255d | 391 | |
fec3a23b | 392 | /* Write RX ring start address */ |
b4f1255d FF |
393 | iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0); |
394 | iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1); | |
fec3a23b FF |
395 | |
396 | /* Set interrupt waiting time and packet numbers */ | |
397 | iowrite16(0x0F06, ioaddr + MT_ICR); | |
398 | iowrite16(0x0F06, ioaddr + MR_ICR); | |
399 | ||
400 | /* Enable interrupts */ | |
401 | iowrite16(INT_MASK, ioaddr + MIER); | |
402 | ||
403 | /* Enable TX and RX */ | |
404 | iowrite16(lp->mcr0 | 0x0002, ioaddr); | |
405 | ||
406 | /* Let TX poll the descriptors | |
407 | * we may got called by r6040_tx_timeout which has left | |
408 | * some unsent tx buffers */ | |
409 | iowrite16(0x01, ioaddr + MTPR); | |
b4f1255d | 410 | } |
7a47dd7a | 411 | |
106adf3c FF |
412 | static void r6040_tx_timeout(struct net_device *dev) |
413 | { | |
414 | struct r6040_private *priv = netdev_priv(dev); | |
415 | void __iomem *ioaddr = priv->base; | |
416 | ||
fec3a23b FF |
417 | printk(KERN_WARNING "%s: transmit timed out, int enable %4.4x " |
418 | "status %4.4x, PHY status %4.4x\n", | |
106adf3c | 419 | dev->name, ioread16(ioaddr + MIER), |
fec3a23b | 420 | ioread16(ioaddr + MISR), |
c6e69bb9 | 421 | r6040_mdio_read(dev, priv->mii_if.phy_id, MII_BMSR)); |
106adf3c | 422 | |
106adf3c | 423 | dev->stats.tx_errors++; |
fec3a23b FF |
424 | |
425 | /* Reset MAC and re-init all registers */ | |
426 | r6040_init_mac_regs(dev); | |
106adf3c FF |
427 | } |
428 | ||
7a47dd7a SW |
429 | static struct net_device_stats *r6040_get_stats(struct net_device *dev) |
430 | { | |
431 | struct r6040_private *priv = netdev_priv(dev); | |
432 | void __iomem *ioaddr = priv->base; | |
433 | unsigned long flags; | |
434 | ||
435 | spin_lock_irqsave(&priv->lock, flags); | |
d248fd77 FF |
436 | dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1); |
437 | dev->stats.multicast += ioread8(ioaddr + ME_CNT0); | |
7a47dd7a SW |
438 | spin_unlock_irqrestore(&priv->lock, flags); |
439 | ||
d248fd77 | 440 | return &dev->stats; |
7a47dd7a SW |
441 | } |
442 | ||
443 | /* Stop RDC MAC and Free the allocated resource */ | |
444 | static void r6040_down(struct net_device *dev) | |
445 | { | |
446 | struct r6040_private *lp = netdev_priv(dev); | |
447 | void __iomem *ioaddr = lp->base; | |
6c323103 | 448 | struct pci_dev *pdev = lp->pdev; |
7a47dd7a SW |
449 | int limit = 2048; |
450 | u16 *adrp; | |
451 | u16 cmd; | |
452 | ||
453 | /* Stop MAC */ | |
454 | iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */ | |
455 | iowrite16(MAC_RST, ioaddr + MCR1); /* Reset RDC MAC */ | |
456 | while (limit--) { | |
457 | cmd = ioread16(ioaddr + MCR1); | |
458 | if (cmd & 0x1) | |
459 | break; | |
460 | } | |
461 | ||
462 | /* Restore MAC Address to MIDx */ | |
463 | adrp = (u16 *) dev->dev_addr; | |
464 | iowrite16(adrp[0], ioaddr + MID_0L); | |
465 | iowrite16(adrp[1], ioaddr + MID_0M); | |
466 | iowrite16(adrp[2], ioaddr + MID_0H); | |
467 | free_irq(dev->irq, dev); | |
b4f1255d | 468 | |
7a47dd7a | 469 | /* Free RX buffer */ |
b4f1255d | 470 | r6040_free_rxbufs(dev); |
7a47dd7a SW |
471 | |
472 | /* Free TX buffer */ | |
b4f1255d | 473 | r6040_free_txbufs(dev); |
7a47dd7a SW |
474 | |
475 | /* Free Descriptor memory */ | |
6c323103 FR |
476 | pci_free_consistent(pdev, RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma); |
477 | pci_free_consistent(pdev, TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma); | |
7a47dd7a SW |
478 | } |
479 | ||
5ac5d616 | 480 | static int r6040_close(struct net_device *dev) |
7a47dd7a SW |
481 | { |
482 | struct r6040_private *lp = netdev_priv(dev); | |
483 | ||
484 | /* deleted timer */ | |
485 | del_timer_sync(&lp->timer); | |
486 | ||
487 | spin_lock_irq(&lp->lock); | |
129cf9a7 | 488 | napi_disable(&lp->napi); |
7a47dd7a SW |
489 | netif_stop_queue(dev); |
490 | r6040_down(dev); | |
491 | spin_unlock_irq(&lp->lock); | |
492 | ||
493 | return 0; | |
494 | } | |
495 | ||
496 | /* Status of PHY CHIP */ | |
c6e69bb9 | 497 | static int r6040_phy_mode_chk(struct net_device *dev) |
7a47dd7a SW |
498 | { |
499 | struct r6040_private *lp = netdev_priv(dev); | |
500 | void __iomem *ioaddr = lp->base; | |
501 | int phy_dat; | |
502 | ||
503 | /* PHY Link Status Check */ | |
c6e69bb9 | 504 | phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1); |
7a47dd7a SW |
505 | if (!(phy_dat & 0x4)) |
506 | phy_dat = 0x8000; /* Link Failed, full duplex */ | |
507 | ||
508 | /* PHY Chip Auto-Negotiation Status */ | |
c6e69bb9 | 509 | phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 1); |
7a47dd7a SW |
510 | if (phy_dat & 0x0020) { |
511 | /* Auto Negotiation Mode */ | |
c6e69bb9 FF |
512 | phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 5); |
513 | phy_dat &= r6040_phy_read(ioaddr, lp->phy_addr, 4); | |
7a47dd7a SW |
514 | if (phy_dat & 0x140) |
515 | /* Force full duplex */ | |
516 | phy_dat = 0x8000; | |
517 | else | |
518 | phy_dat = 0; | |
519 | } else { | |
520 | /* Force Mode */ | |
c6e69bb9 | 521 | phy_dat = r6040_phy_read(ioaddr, lp->phy_addr, 0); |
7a47dd7a SW |
522 | if (phy_dat & 0x100) |
523 | phy_dat = 0x8000; | |
524 | else | |
525 | phy_dat = 0x0000; | |
526 | } | |
527 | ||
528 | return phy_dat; | |
529 | }; | |
530 | ||
531 | static void r6040_set_carrier(struct mii_if_info *mii) | |
532 | { | |
c6e69bb9 | 533 | if (r6040_phy_mode_chk(mii->dev)) { |
7a47dd7a SW |
534 | /* autoneg is off: Link is always assumed to be up */ |
535 | if (!netif_carrier_ok(mii->dev)) | |
536 | netif_carrier_on(mii->dev); | |
537 | } else | |
c6e69bb9 | 538 | r6040_phy_mode_chk(mii->dev); |
7a47dd7a SW |
539 | } |
540 | ||
541 | static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) | |
542 | { | |
543 | struct r6040_private *lp = netdev_priv(dev); | |
5ac5d616 | 544 | struct mii_ioctl_data *data = if_mii(rq); |
7a47dd7a SW |
545 | int rc; |
546 | ||
547 | if (!netif_running(dev)) | |
548 | return -EINVAL; | |
549 | spin_lock_irq(&lp->lock); | |
550 | rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL); | |
551 | spin_unlock_irq(&lp->lock); | |
552 | r6040_set_carrier(&lp->mii_if); | |
553 | return rc; | |
554 | } | |
555 | ||
556 | static int r6040_rx(struct net_device *dev, int limit) | |
557 | { | |
558 | struct r6040_private *priv = netdev_priv(dev); | |
559 | int count; | |
560 | void __iomem *ioaddr = priv->base; | |
561 | u16 err; | |
562 | ||
563 | for (count = 0; count < limit; ++count) { | |
564 | struct r6040_descriptor *descptr = priv->rx_remove_ptr; | |
565 | struct sk_buff *skb_ptr; | |
566 | ||
7a47dd7a SW |
567 | descptr = priv->rx_remove_ptr; |
568 | ||
569 | /* Check for errors */ | |
570 | err = ioread16(ioaddr + MLSR); | |
d248fd77 FF |
571 | if (err & 0x0400) |
572 | dev->stats.rx_errors++; | |
7a47dd7a | 573 | /* RX FIFO over-run */ |
d248fd77 FF |
574 | if (err & 0x8000) |
575 | dev->stats.rx_fifo_errors++; | |
7a47dd7a | 576 | /* RX descriptor unavailable */ |
d248fd77 FF |
577 | if (err & 0x0080) |
578 | dev->stats.rx_frame_errors++; | |
7a47dd7a | 579 | /* Received packet with length over buffer lenght */ |
d248fd77 FF |
580 | if (err & 0x0020) |
581 | dev->stats.rx_over_errors++; | |
7a47dd7a | 582 | /* Received packet with too long or short */ |
d248fd77 FF |
583 | if (err & (0x0010 | 0x0008)) |
584 | dev->stats.rx_length_errors++; | |
7a47dd7a SW |
585 | /* Received packet with CRC errors */ |
586 | if (err & 0x0004) { | |
587 | spin_lock(&priv->lock); | |
d248fd77 | 588 | dev->stats.rx_crc_errors++; |
7a47dd7a SW |
589 | spin_unlock(&priv->lock); |
590 | } | |
591 | ||
592 | while (priv->rx_free_desc) { | |
593 | /* No RX packet */ | |
594 | if (descptr->status & 0x8000) | |
595 | break; | |
596 | skb_ptr = descptr->skb_ptr; | |
597 | if (!skb_ptr) { | |
598 | printk(KERN_ERR "%s: Inconsistent RX" | |
599 | "descriptor chain\n", | |
600 | dev->name); | |
601 | break; | |
602 | } | |
603 | descptr->skb_ptr = NULL; | |
604 | skb_ptr->dev = priv->dev; | |
605 | /* Do not count the CRC */ | |
606 | skb_put(skb_ptr, descptr->len - 4); | |
ed773b4a | 607 | pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf), |
7a47dd7a SW |
608 | MAX_BUF_SIZE, PCI_DMA_FROMDEVICE); |
609 | skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev); | |
610 | /* Send to upper layer */ | |
611 | netif_receive_skb(skb_ptr); | |
612 | dev->last_rx = jiffies; | |
d248fd77 FF |
613 | dev->stats.rx_packets++; |
614 | dev->stats.rx_bytes += descptr->len; | |
7a47dd7a SW |
615 | /* To next descriptor */ |
616 | descptr = descptr->vndescp; | |
617 | priv->rx_free_desc--; | |
618 | } | |
619 | priv->rx_remove_ptr = descptr; | |
620 | } | |
621 | /* Allocate new RX buffer */ | |
622 | if (priv->rx_free_desc < RX_DCNT) | |
c6e69bb9 | 623 | r6040_rx_buf_alloc(priv, priv->dev); |
7a47dd7a SW |
624 | |
625 | return count; | |
626 | } | |
627 | ||
628 | static void r6040_tx(struct net_device *dev) | |
629 | { | |
630 | struct r6040_private *priv = netdev_priv(dev); | |
631 | struct r6040_descriptor *descptr; | |
632 | void __iomem *ioaddr = priv->base; | |
633 | struct sk_buff *skb_ptr; | |
634 | u16 err; | |
635 | ||
636 | spin_lock(&priv->lock); | |
637 | descptr = priv->tx_remove_ptr; | |
638 | while (priv->tx_free_desc < TX_DCNT) { | |
639 | /* Check for errors */ | |
640 | err = ioread16(ioaddr + MLSR); | |
641 | ||
d248fd77 FF |
642 | if (err & 0x0200) |
643 | dev->stats.rx_fifo_errors++; | |
644 | if (err & (0x2000 | 0x4000)) | |
645 | dev->stats.tx_carrier_errors++; | |
7a47dd7a SW |
646 | |
647 | if (descptr->status & 0x8000) | |
ec6d2d45 | 648 | break; /* Not complete */ |
7a47dd7a | 649 | skb_ptr = descptr->skb_ptr; |
ed773b4a | 650 | pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf), |
7a47dd7a SW |
651 | skb_ptr->len, PCI_DMA_TODEVICE); |
652 | /* Free buffer */ | |
653 | dev_kfree_skb_irq(skb_ptr); | |
654 | descptr->skb_ptr = NULL; | |
655 | /* To next descriptor */ | |
656 | descptr = descptr->vndescp; | |
657 | priv->tx_free_desc++; | |
658 | } | |
659 | priv->tx_remove_ptr = descptr; | |
660 | ||
661 | if (priv->tx_free_desc) | |
662 | netif_wake_queue(dev); | |
663 | spin_unlock(&priv->lock); | |
664 | } | |
665 | ||
666 | static int r6040_poll(struct napi_struct *napi, int budget) | |
667 | { | |
668 | struct r6040_private *priv = | |
669 | container_of(napi, struct r6040_private, napi); | |
670 | struct net_device *dev = priv->dev; | |
671 | void __iomem *ioaddr = priv->base; | |
672 | int work_done; | |
673 | ||
674 | work_done = r6040_rx(dev, budget); | |
675 | ||
676 | if (work_done < budget) { | |
677 | netif_rx_complete(dev, napi); | |
678 | /* Enable RX interrupt */ | |
679 | iowrite16(ioread16(ioaddr + MIER) | RX_INT, ioaddr + MIER); | |
680 | } | |
681 | return work_done; | |
682 | } | |
683 | ||
684 | /* The RDC interrupt handler. */ | |
685 | static irqreturn_t r6040_interrupt(int irq, void *dev_id) | |
686 | { | |
687 | struct net_device *dev = dev_id; | |
688 | struct r6040_private *lp = netdev_priv(dev); | |
689 | void __iomem *ioaddr = lp->base; | |
690 | u16 status; | |
7a47dd7a SW |
691 | |
692 | /* Mask off RDC MAC interrupt */ | |
693 | iowrite16(MSK_INT, ioaddr + MIER); | |
694 | /* Read MISR status and clear */ | |
695 | status = ioread16(ioaddr + MISR); | |
696 | ||
697 | if (status == 0x0000 || status == 0xffff) | |
698 | return IRQ_NONE; | |
699 | ||
700 | /* RX interrupt request */ | |
701 | if (status & 0x01) { | |
3d254348 FF |
702 | /* Mask off RX interrupt */ |
703 | iowrite16(ioread16(ioaddr + MIER) & ~RX_INT, ioaddr + MIER); | |
7a47dd7a | 704 | netif_rx_schedule(dev, &lp->napi); |
7a47dd7a SW |
705 | } |
706 | ||
707 | /* TX interrupt request */ | |
708 | if (status & 0x10) | |
709 | r6040_tx(dev); | |
710 | ||
ec6d2d45 | 711 | return IRQ_HANDLED; |
7a47dd7a SW |
712 | } |
713 | ||
714 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
715 | static void r6040_poll_controller(struct net_device *dev) | |
716 | { | |
717 | disable_irq(dev->irq); | |
5ac5d616 | 718 | r6040_interrupt(dev->irq, dev); |
7a47dd7a SW |
719 | enable_irq(dev->irq); |
720 | } | |
721 | #endif | |
722 | ||
7a47dd7a | 723 | /* Init RDC MAC */ |
3d463419 | 724 | static int r6040_up(struct net_device *dev) |
7a47dd7a SW |
725 | { |
726 | struct r6040_private *lp = netdev_priv(dev); | |
7a47dd7a | 727 | void __iomem *ioaddr = lp->base; |
3d463419 | 728 | int ret; |
7a47dd7a | 729 | |
b4f1255d | 730 | /* Initialise and alloc RX/TX buffers */ |
3d463419 FF |
731 | r6040_init_txbufs(dev); |
732 | ret = r6040_alloc_rxbufs(dev); | |
733 | if (ret) | |
734 | return ret; | |
7a47dd7a | 735 | |
7a47dd7a | 736 | /* Read the PHY ID */ |
c6e69bb9 | 737 | lp->switch_sig = r6040_phy_read(ioaddr, 0, 2); |
7a47dd7a SW |
738 | |
739 | if (lp->switch_sig == ICPLUS_PHY_ID) { | |
c6e69bb9 | 740 | r6040_phy_write(ioaddr, 29, 31, 0x175C); /* Enable registers */ |
7a47dd7a SW |
741 | lp->phy_mode = 0x8000; |
742 | } else { | |
743 | /* PHY Mode Check */ | |
c6e69bb9 FF |
744 | r6040_phy_write(ioaddr, lp->phy_addr, 4, PHY_CAP); |
745 | r6040_phy_write(ioaddr, lp->phy_addr, 0, PHY_MODE); | |
7a47dd7a SW |
746 | |
747 | if (PHY_MODE == 0x3100) | |
c6e69bb9 | 748 | lp->phy_mode = r6040_phy_mode_chk(dev); |
7a47dd7a SW |
749 | else |
750 | lp->phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0; | |
751 | } | |
7a47dd7a | 752 | |
fec3a23b | 753 | /* Set duplex mode */ |
7a47dd7a | 754 | lp->mcr0 |= lp->phy_mode; |
7a47dd7a SW |
755 | |
756 | /* improve performance (by RDC guys) */ | |
c6e69bb9 FF |
757 | r6040_phy_write(ioaddr, 30, 17, (r6040_phy_read(ioaddr, 30, 17) | 0x4000)); |
758 | r6040_phy_write(ioaddr, 30, 17, ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000)); | |
759 | r6040_phy_write(ioaddr, 0, 19, 0x0000); | |
760 | r6040_phy_write(ioaddr, 0, 30, 0x01F0); | |
7a47dd7a | 761 | |
fec3a23b FF |
762 | /* Initialize all MAC registers */ |
763 | r6040_init_mac_regs(dev); | |
3d463419 FF |
764 | |
765 | return 0; | |
7a47dd7a SW |
766 | } |
767 | ||
768 | /* | |
769 | A periodic timer routine | |
770 | Polling PHY Chip Link Status | |
771 | */ | |
772 | static void r6040_timer(unsigned long data) | |
773 | { | |
774 | struct net_device *dev = (struct net_device *)data; | |
e6a9ea10 | 775 | struct r6040_private *lp = netdev_priv(dev); |
7a47dd7a SW |
776 | void __iomem *ioaddr = lp->base; |
777 | u16 phy_mode; | |
778 | ||
779 | /* Polling PHY Chip Status */ | |
780 | if (PHY_MODE == 0x3100) | |
c6e69bb9 | 781 | phy_mode = r6040_phy_mode_chk(dev); |
7a47dd7a SW |
782 | else |
783 | phy_mode = (PHY_MODE & 0x0100) ? 0x8000:0x0; | |
784 | ||
785 | if (phy_mode != lp->phy_mode) { | |
786 | lp->phy_mode = phy_mode; | |
787 | lp->mcr0 = (lp->mcr0 & 0x7fff) | phy_mode; | |
788 | iowrite16(lp->mcr0, ioaddr); | |
789 | printk(KERN_INFO "Link Change %x \n", ioread16(ioaddr)); | |
790 | } | |
791 | ||
792 | /* Timer active again */ | |
208aefa2 | 793 | mod_timer(&lp->timer, round_jiffies(jiffies + HZ)); |
7a47dd7a SW |
794 | } |
795 | ||
796 | /* Read/set MAC address routines */ | |
797 | static void r6040_mac_address(struct net_device *dev) | |
798 | { | |
799 | struct r6040_private *lp = netdev_priv(dev); | |
800 | void __iomem *ioaddr = lp->base; | |
801 | u16 *adrp; | |
802 | ||
803 | /* MAC operation register */ | |
804 | iowrite16(0x01, ioaddr + MCR1); /* Reset MAC */ | |
805 | iowrite16(2, ioaddr + MAC_SM); /* Reset internal state machine */ | |
806 | iowrite16(0, ioaddr + MAC_SM); | |
807 | udelay(5000); | |
808 | ||
809 | /* Restore MAC Address */ | |
810 | adrp = (u16 *) dev->dev_addr; | |
811 | iowrite16(adrp[0], ioaddr + MID_0L); | |
812 | iowrite16(adrp[1], ioaddr + MID_0M); | |
813 | iowrite16(adrp[2], ioaddr + MID_0H); | |
814 | } | |
815 | ||
5ac5d616 | 816 | static int r6040_open(struct net_device *dev) |
7a47dd7a | 817 | { |
5ac5d616 | 818 | struct r6040_private *lp = netdev_priv(dev); |
7a47dd7a SW |
819 | int ret; |
820 | ||
821 | /* Request IRQ and Register interrupt handler */ | |
822 | ret = request_irq(dev->irq, &r6040_interrupt, | |
823 | IRQF_SHARED, dev->name, dev); | |
824 | if (ret) | |
825 | return ret; | |
826 | ||
827 | /* Set MAC address */ | |
828 | r6040_mac_address(dev); | |
829 | ||
830 | /* Allocate Descriptor memory */ | |
6c323103 FR |
831 | lp->rx_ring = |
832 | pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma); | |
833 | if (!lp->rx_ring) | |
7a47dd7a SW |
834 | return -ENOMEM; |
835 | ||
6c323103 FR |
836 | lp->tx_ring = |
837 | pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma); | |
838 | if (!lp->tx_ring) { | |
839 | pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring, | |
840 | lp->rx_ring_dma); | |
841 | return -ENOMEM; | |
842 | } | |
843 | ||
3d463419 FF |
844 | ret = r6040_up(dev); |
845 | if (ret) { | |
846 | pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring, | |
847 | lp->tx_ring_dma); | |
848 | pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring, | |
849 | lp->rx_ring_dma); | |
850 | return ret; | |
851 | } | |
7a47dd7a SW |
852 | |
853 | napi_enable(&lp->napi); | |
854 | netif_start_queue(dev); | |
855 | ||
106adf3c FF |
856 | /* set and active a timer process */ |
857 | setup_timer(&lp->timer, r6040_timer, (unsigned long) dev); | |
858 | if (lp->switch_sig != ICPLUS_PHY_ID) | |
859 | mod_timer(&lp->timer, jiffies + HZ); | |
7a47dd7a SW |
860 | return 0; |
861 | } | |
862 | ||
5ac5d616 | 863 | static int r6040_start_xmit(struct sk_buff *skb, struct net_device *dev) |
7a47dd7a SW |
864 | { |
865 | struct r6040_private *lp = netdev_priv(dev); | |
866 | struct r6040_descriptor *descptr; | |
867 | void __iomem *ioaddr = lp->base; | |
868 | unsigned long flags; | |
092427be | 869 | int ret = NETDEV_TX_OK; |
7a47dd7a SW |
870 | |
871 | /* Critical Section */ | |
872 | spin_lock_irqsave(&lp->lock, flags); | |
873 | ||
874 | /* TX resource check */ | |
875 | if (!lp->tx_free_desc) { | |
876 | spin_unlock_irqrestore(&lp->lock, flags); | |
092427be | 877 | netif_stop_queue(dev); |
7a47dd7a | 878 | printk(KERN_ERR DRV_NAME ": no tx descriptor\n"); |
092427be | 879 | ret = NETDEV_TX_BUSY; |
7a47dd7a SW |
880 | return ret; |
881 | } | |
882 | ||
883 | /* Statistic Counter */ | |
884 | dev->stats.tx_packets++; | |
885 | dev->stats.tx_bytes += skb->len; | |
886 | /* Set TX descriptor & Transmit it */ | |
887 | lp->tx_free_desc--; | |
888 | descptr = lp->tx_insert_ptr; | |
889 | if (skb->len < MISR) | |
890 | descptr->len = MISR; | |
891 | else | |
892 | descptr->len = skb->len; | |
893 | ||
894 | descptr->skb_ptr = skb; | |
895 | descptr->buf = cpu_to_le32(pci_map_single(lp->pdev, | |
896 | skb->data, skb->len, PCI_DMA_TODEVICE)); | |
897 | descptr->status = 0x8000; | |
898 | /* Trigger the MAC to check the TX descriptor */ | |
899 | iowrite16(0x01, ioaddr + MTPR); | |
900 | lp->tx_insert_ptr = descptr->vndescp; | |
901 | ||
902 | /* If no tx resource, stop */ | |
903 | if (!lp->tx_free_desc) | |
904 | netif_stop_queue(dev); | |
905 | ||
906 | dev->trans_start = jiffies; | |
907 | spin_unlock_irqrestore(&lp->lock, flags); | |
908 | return ret; | |
909 | } | |
910 | ||
5ac5d616 | 911 | static void r6040_multicast_list(struct net_device *dev) |
7a47dd7a SW |
912 | { |
913 | struct r6040_private *lp = netdev_priv(dev); | |
914 | void __iomem *ioaddr = lp->base; | |
915 | u16 *adrp; | |
916 | u16 reg; | |
917 | unsigned long flags; | |
918 | struct dev_mc_list *dmi = dev->mc_list; | |
919 | int i; | |
920 | ||
921 | /* MAC Address */ | |
922 | adrp = (u16 *)dev->dev_addr; | |
923 | iowrite16(adrp[0], ioaddr + MID_0L); | |
924 | iowrite16(adrp[1], ioaddr + MID_0M); | |
925 | iowrite16(adrp[2], ioaddr + MID_0H); | |
926 | ||
927 | /* Promiscous Mode */ | |
928 | spin_lock_irqsave(&lp->lock, flags); | |
929 | ||
930 | /* Clear AMCP & PROM bits */ | |
931 | reg = ioread16(ioaddr) & ~0x0120; | |
932 | if (dev->flags & IFF_PROMISC) { | |
933 | reg |= 0x0020; | |
934 | lp->mcr0 |= 0x0020; | |
935 | } | |
936 | /* Too many multicast addresses | |
937 | * accept all traffic */ | |
938 | else if ((dev->mc_count > MCAST_MAX) | |
939 | || (dev->flags & IFF_ALLMULTI)) | |
940 | reg |= 0x0020; | |
941 | ||
942 | iowrite16(reg, ioaddr); | |
943 | spin_unlock_irqrestore(&lp->lock, flags); | |
944 | ||
945 | /* Build the hash table */ | |
946 | if (dev->mc_count > MCAST_MAX) { | |
947 | u16 hash_table[4]; | |
948 | u32 crc; | |
949 | ||
950 | for (i = 0; i < 4; i++) | |
951 | hash_table[i] = 0; | |
952 | ||
953 | for (i = 0; i < dev->mc_count; i++) { | |
954 | char *addrs = dmi->dmi_addr; | |
955 | ||
956 | dmi = dmi->next; | |
957 | ||
958 | if (!(*addrs & 1)) | |
959 | continue; | |
960 | ||
961 | crc = ether_crc_le(6, addrs); | |
962 | crc >>= 26; | |
963 | hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); | |
964 | } | |
965 | /* Write the index of the hash table */ | |
966 | for (i = 0; i < 4; i++) | |
967 | iowrite16(hash_table[i] << 14, ioaddr + MCR1); | |
968 | /* Fill the MAC hash tables with their values */ | |
969 | iowrite16(hash_table[0], ioaddr + MAR0); | |
970 | iowrite16(hash_table[1], ioaddr + MAR1); | |
971 | iowrite16(hash_table[2], ioaddr + MAR2); | |
972 | iowrite16(hash_table[3], ioaddr + MAR3); | |
973 | } | |
974 | /* Multicast Address 1~4 case */ | |
975 | for (i = 0, dmi; (i < dev->mc_count) && (i < MCAST_MAX); i++) { | |
976 | adrp = (u16 *)dmi->dmi_addr; | |
977 | iowrite16(adrp[0], ioaddr + MID_1L + 8*i); | |
978 | iowrite16(adrp[1], ioaddr + MID_1M + 8*i); | |
979 | iowrite16(adrp[2], ioaddr + MID_1H + 8*i); | |
980 | dmi = dmi->next; | |
981 | } | |
982 | for (i = dev->mc_count; i < MCAST_MAX; i++) { | |
983 | iowrite16(0xffff, ioaddr + MID_0L + 8*i); | |
984 | iowrite16(0xffff, ioaddr + MID_0M + 8*i); | |
985 | iowrite16(0xffff, ioaddr + MID_0H + 8*i); | |
986 | } | |
987 | } | |
988 | ||
989 | static void netdev_get_drvinfo(struct net_device *dev, | |
990 | struct ethtool_drvinfo *info) | |
991 | { | |
992 | struct r6040_private *rp = netdev_priv(dev); | |
993 | ||
994 | strcpy(info->driver, DRV_NAME); | |
995 | strcpy(info->version, DRV_VERSION); | |
996 | strcpy(info->bus_info, pci_name(rp->pdev)); | |
997 | } | |
998 | ||
999 | static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1000 | { | |
1001 | struct r6040_private *rp = netdev_priv(dev); | |
1002 | int rc; | |
1003 | ||
1004 | spin_lock_irq(&rp->lock); | |
1005 | rc = mii_ethtool_gset(&rp->mii_if, cmd); | |
092427be | 1006 | spin_unlock_irq(&rp->lock); |
7a47dd7a SW |
1007 | |
1008 | return rc; | |
1009 | } | |
1010 | ||
1011 | static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1012 | { | |
1013 | struct r6040_private *rp = netdev_priv(dev); | |
1014 | int rc; | |
1015 | ||
1016 | spin_lock_irq(&rp->lock); | |
1017 | rc = mii_ethtool_sset(&rp->mii_if, cmd); | |
1018 | spin_unlock_irq(&rp->lock); | |
1019 | r6040_set_carrier(&rp->mii_if); | |
1020 | ||
1021 | return rc; | |
1022 | } | |
1023 | ||
1024 | static u32 netdev_get_link(struct net_device *dev) | |
1025 | { | |
1026 | struct r6040_private *rp = netdev_priv(dev); | |
1027 | ||
1028 | return mii_link_ok(&rp->mii_if); | |
1029 | } | |
1030 | ||
1031 | static struct ethtool_ops netdev_ethtool_ops = { | |
1032 | .get_drvinfo = netdev_get_drvinfo, | |
1033 | .get_settings = netdev_get_settings, | |
1034 | .set_settings = netdev_set_settings, | |
1035 | .get_link = netdev_get_link, | |
1036 | }; | |
1037 | ||
7a47dd7a SW |
1038 | static int __devinit r6040_init_one(struct pci_dev *pdev, |
1039 | const struct pci_device_id *ent) | |
1040 | { | |
1041 | struct net_device *dev; | |
1042 | struct r6040_private *lp; | |
1043 | void __iomem *ioaddr; | |
1044 | int err, io_size = R6040_IO_SIZE; | |
1045 | static int card_idx = -1; | |
1046 | int bar = 0; | |
1047 | long pioaddr; | |
1048 | u16 *adrp; | |
1049 | ||
1050 | printk(KERN_INFO "%s\n", version); | |
1051 | ||
1052 | err = pci_enable_device(pdev); | |
1053 | if (err) | |
1054 | return err; | |
1055 | ||
1056 | /* this should always be supported */ | |
1057 | if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) { | |
1058 | printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses" | |
1059 | "not supported by the card\n"); | |
1060 | return -ENODEV; | |
1061 | } | |
092427be JG |
1062 | if (pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK)) { |
1063 | printk(KERN_ERR DRV_NAME "32-bit PCI DMA addresses" | |
1064 | "not supported by the card\n"); | |
1065 | return -ENODEV; | |
1066 | } | |
7a47dd7a SW |
1067 | |
1068 | /* IO Size check */ | |
1069 | if (pci_resource_len(pdev, 0) < io_size) { | |
1070 | printk(KERN_ERR "Insufficient PCI resources, aborting\n"); | |
1071 | return -EIO; | |
1072 | } | |
1073 | ||
1074 | pioaddr = pci_resource_start(pdev, 0); /* IO map base address */ | |
1075 | pci_set_master(pdev); | |
1076 | ||
1077 | dev = alloc_etherdev(sizeof(struct r6040_private)); | |
1078 | if (!dev) { | |
1079 | printk(KERN_ERR "Failed to allocate etherdev\n"); | |
1080 | return -ENOMEM; | |
1081 | } | |
1082 | SET_NETDEV_DEV(dev, &pdev->dev); | |
1083 | lp = netdev_priv(dev); | |
7a47dd7a SW |
1084 | |
1085 | if (pci_request_regions(pdev, DRV_NAME)) { | |
1086 | printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n"); | |
1087 | err = -ENODEV; | |
1088 | goto err_out_disable; | |
1089 | } | |
1090 | ||
1091 | ioaddr = pci_iomap(pdev, bar, io_size); | |
1092 | if (!ioaddr) { | |
1093 | printk(KERN_ERR "ioremap failed for device %s\n", | |
1094 | pci_name(pdev)); | |
1095 | return -EIO; | |
1096 | } | |
1097 | ||
1098 | /* Init system & device */ | |
7a47dd7a SW |
1099 | lp->base = ioaddr; |
1100 | dev->irq = pdev->irq; | |
1101 | ||
1102 | spin_lock_init(&lp->lock); | |
1103 | pci_set_drvdata(pdev, dev); | |
1104 | ||
1105 | /* Set MAC address */ | |
1106 | card_idx++; | |
1107 | ||
1108 | adrp = (u16 *)dev->dev_addr; | |
1109 | adrp[0] = ioread16(ioaddr + MID_0L); | |
1110 | adrp[1] = ioread16(ioaddr + MID_0M); | |
1111 | adrp[2] = ioread16(ioaddr + MID_0H); | |
1112 | ||
1113 | /* Link new device into r6040_root_dev */ | |
1114 | lp->pdev = pdev; | |
129cf9a7 | 1115 | lp->dev = dev; |
7a47dd7a SW |
1116 | |
1117 | /* Init RDC private data */ | |
1118 | lp->mcr0 = 0x1002; | |
1119 | lp->phy_addr = phy_table[card_idx]; | |
1120 | lp->switch_sig = 0; | |
1121 | ||
1122 | /* The RDC-specific entries in the device structure. */ | |
1123 | dev->open = &r6040_open; | |
1124 | dev->hard_start_xmit = &r6040_start_xmit; | |
1125 | dev->stop = &r6040_close; | |
1126 | dev->get_stats = r6040_get_stats; | |
1127 | dev->set_multicast_list = &r6040_multicast_list; | |
1128 | dev->do_ioctl = &r6040_ioctl; | |
1129 | dev->ethtool_ops = &netdev_ethtool_ops; | |
1130 | dev->tx_timeout = &r6040_tx_timeout; | |
1131 | dev->watchdog_timeo = TX_TIMEOUT; | |
1132 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1133 | dev->poll_controller = r6040_poll_controller; | |
1134 | #endif | |
1135 | netif_napi_add(dev, &lp->napi, r6040_poll, 64); | |
1136 | lp->mii_if.dev = dev; | |
c6e69bb9 FF |
1137 | lp->mii_if.mdio_read = r6040_mdio_read; |
1138 | lp->mii_if.mdio_write = r6040_mdio_write; | |
7a47dd7a SW |
1139 | lp->mii_if.phy_id = lp->phy_addr; |
1140 | lp->mii_if.phy_id_mask = 0x1f; | |
1141 | lp->mii_if.reg_num_mask = 0x1f; | |
1142 | ||
1143 | /* Register net device. After this dev->name assign */ | |
1144 | err = register_netdev(dev); | |
1145 | if (err) { | |
1146 | printk(KERN_ERR DRV_NAME ": Failed to register net device\n"); | |
1147 | goto err_out_res; | |
1148 | } | |
1149 | return 0; | |
1150 | ||
1151 | err_out_res: | |
1152 | pci_release_regions(pdev); | |
1153 | err_out_disable: | |
1154 | pci_disable_device(pdev); | |
1155 | pci_set_drvdata(pdev, NULL); | |
1156 | free_netdev(dev); | |
1157 | ||
1158 | return err; | |
1159 | } | |
1160 | ||
1161 | static void __devexit r6040_remove_one(struct pci_dev *pdev) | |
1162 | { | |
1163 | struct net_device *dev = pci_get_drvdata(pdev); | |
1164 | ||
1165 | unregister_netdev(dev); | |
1166 | pci_release_regions(pdev); | |
1167 | free_netdev(dev); | |
1168 | pci_disable_device(pdev); | |
1169 | pci_set_drvdata(pdev, NULL); | |
1170 | } | |
1171 | ||
1172 | ||
1173 | static struct pci_device_id r6040_pci_tbl[] = { | |
5ac5d616 FR |
1174 | { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) }, |
1175 | { 0 } | |
7a47dd7a SW |
1176 | }; |
1177 | MODULE_DEVICE_TABLE(pci, r6040_pci_tbl); | |
1178 | ||
1179 | static struct pci_driver r6040_driver = { | |
5ac5d616 | 1180 | .name = DRV_NAME, |
7a47dd7a SW |
1181 | .id_table = r6040_pci_tbl, |
1182 | .probe = r6040_init_one, | |
1183 | .remove = __devexit_p(r6040_remove_one), | |
1184 | }; | |
1185 | ||
1186 | ||
1187 | static int __init r6040_init(void) | |
1188 | { | |
1189 | return pci_register_driver(&r6040_driver); | |
1190 | } | |
1191 | ||
1192 | ||
1193 | static void __exit r6040_cleanup(void) | |
1194 | { | |
1195 | pci_unregister_driver(&r6040_driver); | |
1196 | } | |
1197 | ||
1198 | module_init(r6040_init); | |
1199 | module_exit(r6040_cleanup); |