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r8169: fix WOL setting for 8105 and 8111evl
[mirror_ubuntu-zesty-kernel.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4 31
99f252b0 32#include <asm/system.h>
1da177e4
LT		 33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
70090424 44#define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
5a5e4443 45#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 46
1da177e4
LT		 47#ifdef RTL8169_DEBUG
48#define assert(expr) \
5b0384f4
FR		 49 if (!(expr)) { \
50 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 51 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 52 }
06fa7358
JP		 53#define dprintk(fmt, args...) \
54 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 55#else
56#define assert(expr) do {} while (0)
57#define dprintk(fmt, args...) do {} while (0)
58#endif /* RTL8169_DEBUG */
59
b57b7e5a 60#define R8169_MSG_DEFAULT \
f0e837d9 61 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 62
1da177e4
LT		 63#define TX_BUFFS_AVAIL(tp) \
64 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
65
1da177e4
LT		 66/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
67 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 68static const int multicast_filter_limit = 32;
1da177e4
LT		 69
70/* MAC address length */
71#define MAC_ADDR_LEN 6
72
9c14ceaf 73#define MAX_READ_REQUEST_SHIFT 12
1da177e4 74#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 75#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77
78#define R8169_REGS_SIZE 256
79#define R8169_NAPI_WEIGHT 64
80#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82#define RX_BUF_SIZE 1536 /* Rx Buffer size */
83#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85
86#define RTL8169_TX_TIMEOUT (6*HZ)
87#define RTL8169_PHY_TIMEOUT (10*HZ)
88
ea8dbdd1 89#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 91#define RTL_EEPROM_SIG_ADDR 0x0000
92
1da177e4
LT		 93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
70090424 135 RTL_GIGA_MAC_VER_34,
85bffe6c 136 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 137};
138
2b7b4318
FR		 139enum rtl_tx_desc_version {
140 RTL_TD_0 = 0,
141 RTL_TD_1 = 1,
142};
143
85bffe6c
FR		 144#define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
1da177e4 146
3c6bee1d 147static const struct {
1da177e4 148 const char *name;
2b7b4318 149 enum rtl_tx_desc_version txd_version;
953a12cc 150 const char *fw_name;
85bffe6c
FR		 151} rtl_chip_infos[] = {
152 /* PCI devices. */
153 [RTL_GIGA_MAC_VER_01] =
154 _R("RTL8169", RTL_TD_0, NULL),
155 [RTL_GIGA_MAC_VER_02] =
156 _R("RTL8169s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_03] =
158 _R("RTL8110s", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_04] =
160 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_05] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 [RTL_GIGA_MAC_VER_06] =
164 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
165 /* PCI-E devices. */
166 [RTL_GIGA_MAC_VER_07] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_08] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_09] =
171 _R("RTL8102e", RTL_TD_1, NULL),
172 [RTL_GIGA_MAC_VER_10] =
173 _R("RTL8101e", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_11] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_12] =
177 _R("RTL8168b/8111b", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_13] =
179 _R("RTL8101e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_14] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_15] =
183 _R("RTL8100e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_16] =
185 _R("RTL8101e", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_17] =
187 _R("RTL8168b/8111b", RTL_TD_0, NULL),
188 [RTL_GIGA_MAC_VER_18] =
189 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_19] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_20] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_21] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_22] =
197 _R("RTL8168c/8111c", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_23] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_24] =
201 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
202 [RTL_GIGA_MAC_VER_25] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
204 [RTL_GIGA_MAC_VER_26] =
205 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
206 [RTL_GIGA_MAC_VER_27] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_28] =
209 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
210 [RTL_GIGA_MAC_VER_29] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_30] =
213 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
214 [RTL_GIGA_MAC_VER_31] =
215 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
216 [RTL_GIGA_MAC_VER_32] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
218 [RTL_GIGA_MAC_VER_33] =
70090424
HW		 219 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2),
220 [RTL_GIGA_MAC_VER_34] =
221 _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3)
953a12cc 222};
85bffe6c 223#undef _R
953a12cc 224
bcf0bf90
FR		 225enum cfg_version {
226 RTL_CFG_0 = 0x00,
227 RTL_CFG_1,
228 RTL_CFG_2
229};
230
07ce4064
FR		 231static void rtl_hw_start_8169(struct net_device *);
232static void rtl_hw_start_8168(struct net_device *);
233static void rtl_hw_start_8101(struct net_device *);
234
a3aa1884 235static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 239 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 240 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
241 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
93a3aa25 242 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
bc1660b5 243 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 244 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
245 { PCI_VENDOR_ID_LINKSYS, 0x1032,
246 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 247 { 0x0001, 0x8168,
248 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 249 {0,},
250};
251
252MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
253
6f0333b8 254static int rx_buf_sz = 16383;
4300e8c7 255static int use_dac;
b57b7e5a
SH		 256static struct {
257 u32 msg_enable;
258} debug = { -1 };
1da177e4 259
07d3f51f
FR		 260enum rtl_registers {
261 MAC0 = 0, /* Ethernet hardware address. */
773d2021 262 MAC4 = 4,
07d3f51f
FR		 263 MAR0 = 8, /* Multicast filter. */
264 CounterAddrLow = 0x10,
265 CounterAddrHigh = 0x14,
266 TxDescStartAddrLow = 0x20,
267 TxDescStartAddrHigh = 0x24,
268 TxHDescStartAddrLow = 0x28,
269 TxHDescStartAddrHigh = 0x2c,
270 FLASH = 0x30,
271 ERSR = 0x36,
272 ChipCmd = 0x37,
273 TxPoll = 0x38,
274 IntrMask = 0x3c,
275 IntrStatus = 0x3e,
4f6b00e5 276
07d3f51f 277 TxConfig = 0x40,
4f6b00e5
HW		 278#define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
279#define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
2b7b4318 280
4f6b00e5
HW		 281 RxConfig = 0x44,
282#define RX128_INT_EN (1 << 15) /* 8111c and later */
283#define RX_MULTI_EN (1 << 14) /* 8111c only */
284#define RXCFG_FIFO_SHIFT 13
285 /* No threshold before first PCI xfer */
286#define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
287#define RXCFG_DMA_SHIFT 8
288 /* Unlimited maximum PCI burst. */
289#define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
2b7b4318 290
07d3f51f
FR		 291 RxMissed = 0x4c,
292 Cfg9346 = 0x50,
293 Config0 = 0x51,
294 Config1 = 0x52,
295 Config2 = 0x53,
296 Config3 = 0x54,
297 Config4 = 0x55,
298 Config5 = 0x56,
299 MultiIntr = 0x5c,
300 PHYAR = 0x60,
07d3f51f
FR		 301 PHYstatus = 0x6c,
302 RxMaxSize = 0xda,
303 CPlusCmd = 0xe0,
304 IntrMitigate = 0xe2,
305 RxDescAddrLow = 0xe4,
306 RxDescAddrHigh = 0xe8,
f0298f81 307 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
308
309#define NoEarlyTx 0x3f /* Max value : no early transmit. */
310
311 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
312
313#define TxPacketMax (8064 >> 7)
314
07d3f51f
FR		 315 FuncEvent = 0xf0,
316 FuncEventMask = 0xf4,
317 FuncPresetState = 0xf8,
318 FuncForceEvent = 0xfc,
1da177e4
LT		 319};
320
f162a5d1
FR		 321enum rtl8110_registers {
322 TBICSR = 0x64,
323 TBI_ANAR = 0x68,
324 TBI_LPAR = 0x6a,
325};
326
327enum rtl8168_8101_registers {
328 CSIDR = 0x64,
329 CSIAR = 0x68,
330#define CSIAR_FLAG 0x80000000
331#define CSIAR_WRITE_CMD 0x80000000
332#define CSIAR_BYTE_ENABLE 0x0f
333#define CSIAR_BYTE_ENABLE_SHIFT 12
334#define CSIAR_ADDR_MASK 0x0fff
065c27c1 335 PMCH = 0x6f,
f162a5d1
FR		 336 EPHYAR = 0x80,
337#define EPHYAR_FLAG 0x80000000
338#define EPHYAR_WRITE_CMD 0x80000000
339#define EPHYAR_REG_MASK 0x1f
340#define EPHYAR_REG_SHIFT 16
341#define EPHYAR_DATA_MASK 0xffff
5a5e4443 342 DLLPR = 0xd0,
4f6b00e5 343#define PFM_EN (1 << 6)
f162a5d1
FR		 344 DBG_REG = 0xd1,
345#define FIX_NAK_1 (1 << 4)
346#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 347 TWSI = 0xd2,
348 MCU = 0xd3,
4f6b00e5 349#define NOW_IS_OOB (1 << 7)
5a5e4443
HW		 350#define EN_NDP (1 << 3)
351#define EN_OOB_RESET (1 << 2)
daf9df6d 352 EFUSEAR = 0xdc,
353#define EFUSEAR_FLAG 0x80000000
354#define EFUSEAR_WRITE_CMD 0x80000000
355#define EFUSEAR_READ_CMD 0x00000000
356#define EFUSEAR_REG_MASK 0x03ff
357#define EFUSEAR_REG_SHIFT 8
358#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 359};
360
c0e45c1c 361enum rtl8168_registers {
4f6b00e5
HW		 362 LED_FREQ = 0x1a,
363 EEE_LED = 0x1b,
b646d900 364 ERIDR = 0x70,
365 ERIAR = 0x74,
366#define ERIAR_FLAG 0x80000000
367#define ERIAR_WRITE_CMD 0x80000000
368#define ERIAR_READ_CMD 0x00000000
369#define ERIAR_ADDR_BYTE_ALIGN 4
b646d900 370#define ERIAR_TYPE_SHIFT 16
4f6b00e5
HW		 371#define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
372#define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
373#define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
374#define ERIAR_MASK_SHIFT 12
375#define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
376#define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
377#define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
c0e45c1c 378 EPHY_RXER_NUM = 0x7c,
379 OCPDR = 0xb0, /* OCP GPHY access */
380#define OCPDR_WRITE_CMD 0x80000000
381#define OCPDR_READ_CMD 0x00000000
382#define OCPDR_REG_MASK 0x7f
383#define OCPDR_GPHY_REG_SHIFT 16
384#define OCPDR_DATA_MASK 0xffff
385 OCPAR = 0xb4,
386#define OCPAR_FLAG 0x80000000
387#define OCPAR_GPHY_WRITE_CMD 0x8000f060
388#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 389 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
390 MISC = 0xf0, /* 8168e only. */
cecb5fd7 391#define TXPLA_RST (1 << 29)
4f6b00e5 392#define PWM_EN (1 << 22)
c0e45c1c 393};
394
07d3f51f 395enum rtl_register_content {
1da177e4 396 /* InterruptStatusBits */
07d3f51f
FR		 397 SYSErr = 0x8000,
398 PCSTimeout = 0x4000,
399 SWInt = 0x0100,
400 TxDescUnavail = 0x0080,
401 RxFIFOOver = 0x0040,
402 LinkChg = 0x0020,
403 RxOverflow = 0x0010,
404 TxErr = 0x0008,
405 TxOK = 0x0004,
406 RxErr = 0x0002,
407 RxOK = 0x0001,
1da177e4
LT		 408
409 /* RxStatusDesc */
9dccf611
FR		 410 RxFOVF = (1 << 23),
411 RxRWT = (1 << 22),
412 RxRES = (1 << 21),
413 RxRUNT = (1 << 20),
414 RxCRC = (1 << 19),
1da177e4
LT		 415
416 /* ChipCmdBits */
4f6b00e5 417 StopReq = 0x80,
07d3f51f
FR		 418 CmdReset = 0x10,
419 CmdRxEnb = 0x08,
420 CmdTxEnb = 0x04,
421 RxBufEmpty = 0x01,
1da177e4 422
275391a4
FR		 423 /* TXPoll register p.5 */
424 HPQ = 0x80, /* Poll cmd on the high prio queue */
425 NPQ = 0x40, /* Poll cmd on the low prio queue */
426 FSWInt = 0x01, /* Forced software interrupt */
427
1da177e4 428 /* Cfg9346Bits */
07d3f51f
FR		 429 Cfg9346_Lock = 0x00,
430 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 431
432 /* rx_mode_bits */
07d3f51f
FR		 433 AcceptErr = 0x20,
434 AcceptRunt = 0x10,
435 AcceptBroadcast = 0x08,
436 AcceptMulticast = 0x04,
437 AcceptMyPhys = 0x02,
438 AcceptAllPhys = 0x01,
1687b566 439#define RX_CONFIG_ACCEPT_MASK 0x3f
1da177e4 440
1da177e4
LT		 441 /* TxConfigBits */
442 TxInterFrameGapShift = 24,
443 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
444
5d06a99f 445 /* Config1 register p.24 */
f162a5d1
FR		 446 LEDS1 = (1 << 7),
447 LEDS0 = (1 << 6),
fbac58fc 448 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 449 Speed_down = (1 << 4),
450 MEMMAP = (1 << 3),
451 IOMAP = (1 << 2),
452 VPD = (1 << 1),
5d06a99f
FR		 453 PMEnable = (1 << 0), /* Power Management Enable */
454
6dccd16b
FR		 455 /* Config2 register p. 25 */
456 PCI_Clock_66MHz = 0x01,
457 PCI_Clock_33MHz = 0x00,
458
61a4dcc2
FR		 459 /* Config3 register p.25 */
460 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
461 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 462 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 463
5d06a99f 464 /* Config5 register p.27 */
61a4dcc2
FR		 465 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
466 MWF = (1 << 5), /* Accept Multicast wakeup frame */
467 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 468 Spi_en = (1 << 3),
61a4dcc2 469 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 470 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
471
1da177e4
LT		 472 /* TBICSR p.28 */
473 TBIReset = 0x80000000,
474 TBILoopback = 0x40000000,
475 TBINwEnable = 0x20000000,
476 TBINwRestart = 0x10000000,
477 TBILinkOk = 0x02000000,
478 TBINwComplete = 0x01000000,
479
480 /* CPlusCmd p.31 */
f162a5d1
FR		 481 EnableBist = (1 << 15), // 8168 8101
482 Mac_dbgo_oe = (1 << 14), // 8168 8101
483 Normal_mode = (1 << 13), // unused
484 Force_half_dup = (1 << 12), // 8168 8101
485 Force_rxflow_en = (1 << 11), // 8168 8101
486 Force_txflow_en = (1 << 10), // 8168 8101
487 Cxpl_dbg_sel = (1 << 9), // 8168 8101
488 ASF = (1 << 8), // 8168 8101
489 PktCntrDisable = (1 << 7), // 8168 8101
490 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 491 RxVlan = (1 << 6),
492 RxChkSum = (1 << 5),
493 PCIDAC = (1 << 4),
494 PCIMulRW = (1 << 3),
0e485150
FR		 495 INTT_0 = 0x0000, // 8168
496 INTT_1 = 0x0001, // 8168
497 INTT_2 = 0x0002, // 8168
498 INTT_3 = 0x0003, // 8168
1da177e4
LT		 499
500 /* rtl8169_PHYstatus */
07d3f51f
FR		 501 TBI_Enable = 0x80,
502 TxFlowCtrl = 0x40,
503 RxFlowCtrl = 0x20,
504 _1000bpsF = 0x10,
505 _100bps = 0x08,
506 _10bps = 0x04,
507 LinkStatus = 0x02,
508 FullDup = 0x01,
1da177e4 509
1da177e4 510 /* _TBICSRBit */
07d3f51f 511 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 512
513 /* DumpCounterCommand */
07d3f51f 514 CounterDump = 0x8,
1da177e4
LT		 515};
516
2b7b4318
FR		 517enum rtl_desc_bit {
518 /* First doubleword. */
1da177e4
LT		 519 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
520 RingEnd = (1 << 30), /* End of descriptor ring */
521 FirstFrag = (1 << 29), /* First segment of a packet */
522 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 523};
524
525/* Generic case. */
526enum rtl_tx_desc_bit {
527 /* First doubleword. */
528 TD_LSO = (1 << 27), /* Large Send Offload */
529#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 530
2b7b4318
FR		 531 /* Second doubleword. */
532 TxVlanTag = (1 << 17), /* Add VLAN tag */
533};
534
535/* 8169, 8168b and 810x except 8102e. */
536enum rtl_tx_desc_bit_0 {
537 /* First doubleword. */
538#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
539 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
540 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
541 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
542};
543
544/* 8102e, 8168c and beyond. */
545enum rtl_tx_desc_bit_1 {
546 /* Second doubleword. */
547#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
548 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
549 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
550 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
551};
1da177e4 552
2b7b4318
FR		 553static const struct rtl_tx_desc_info {
554 struct {
555 u32 udp;
556 u32 tcp;
557 } checksum;
558 u16 mss_shift;
559 u16 opts_offset;
560} tx_desc_info [] = {
561 [RTL_TD_0] = {
562 .checksum = {
563 .udp = TD0_IP_CS | TD0_UDP_CS,
564 .tcp = TD0_IP_CS | TD0_TCP_CS
565 },
566 .mss_shift = TD0_MSS_SHIFT,
567 .opts_offset = 0
568 },
569 [RTL_TD_1] = {
570 .checksum = {
571 .udp = TD1_IP_CS | TD1_UDP_CS,
572 .tcp = TD1_IP_CS | TD1_TCP_CS
573 },
574 .mss_shift = TD1_MSS_SHIFT,
575 .opts_offset = 1
576 }
577};
578
579enum rtl_rx_desc_bit {
1da177e4
LT		 580 /* Rx private */
581 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
582 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
583
584#define RxProtoUDP (PID1)
585#define RxProtoTCP (PID0)
586#define RxProtoIP (PID1 | PID0)
587#define RxProtoMask RxProtoIP
588
589 IPFail = (1 << 16), /* IP checksum failed */
590 UDPFail = (1 << 15), /* UDP/IP checksum failed */
591 TCPFail = (1 << 14), /* TCP/IP checksum failed */
592 RxVlanTag = (1 << 16), /* VLAN tag available */
593};
594
595#define RsvdMask 0x3fffc000
596
597struct TxDesc {
6cccd6e7
REB		 598 __le32 opts1;
599 __le32 opts2;
600 __le64 addr;
1da177e4
LT		 601};
602
603struct RxDesc {
6cccd6e7
REB		 604 __le32 opts1;
605 __le32 opts2;
606 __le64 addr;
1da177e4
LT		 607};
608
609struct ring_info {
610 struct sk_buff *skb;
611 u32 len;
612 u8 __pad[sizeof(void *) - sizeof(u32)];
613};
614
f23e7fda 615enum features {
ccdffb9a
FR		 616 RTL_FEATURE_WOL = (1 << 0),
617 RTL_FEATURE_MSI = (1 << 1),
618 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 619};
620
355423d0
IV		 621struct rtl8169_counters {
622 __le64 tx_packets;
623 __le64 rx_packets;
624 __le64 tx_errors;
625 __le32 rx_errors;
626 __le16 rx_missed;
627 __le16 align_errors;
628 __le32 tx_one_collision;
629 __le32 tx_multi_collision;
630 __le64 rx_unicast;
631 __le64 rx_broadcast;
632 __le32 rx_multicast;
633 __le16 tx_aborted;
634 __le16 tx_underun;
635};
636
1da177e4
LT		 637struct rtl8169_private {
638 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 639 struct pci_dev *pci_dev;
c4028958 640 struct net_device *dev;
bea3348e 641 struct napi_struct napi;
cecb5fd7 642 spinlock_t lock;
b57b7e5a 643 u32 msg_enable;
2b7b4318
FR		 644 u16 txd_version;
645 u16 mac_version;
1da177e4
LT		 646 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
647 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
648 u32 dirty_rx;
649 u32 dirty_tx;
650 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
651 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
652 dma_addr_t TxPhyAddr;
653 dma_addr_t RxPhyAddr;
6f0333b8 654 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 655 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 656 struct timer_list timer;
657 u16 cp_cmd;
0e485150
FR		 658 u16 intr_event;
659 u16 napi_event;
1da177e4 660 u16 intr_mask;
c0e45c1c 661
662 struct mdio_ops {
663 void (*write)(void __iomem *, int, int);
664 int (*read)(void __iomem *, int);
665 } mdio_ops;
666
065c27c1 667 struct pll_power_ops {
668 void (*down)(struct rtl8169_private *);
669 void (*up)(struct rtl8169_private *);
670 } pll_power_ops;
671
54405cde 672 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 673 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 674 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 675 void (*hw_start)(struct net_device *);
4da19633 676 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 677 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 678 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
c4028958 679 struct delayed_work task;
f23e7fda 680 unsigned features;
ccdffb9a
FR		 681
682 struct mii_if_info mii;
355423d0 683 struct rtl8169_counters counters;
e1759441 684 u32 saved_wolopts;
f1e02ed1 685
b6ffd97f
FR		 686 struct rtl_fw {
687 const struct firmware *fw;
1c361efb
FR		 688
689#define RTL_VER_SIZE 32
690
691 char version[RTL_VER_SIZE];
692
693 struct rtl_fw_phy_action {
694 __le32 *code;
695 size_t size;
696 } phy_action;
b6ffd97f 697 } *rtl_fw;
497888cf 698#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
1da177e4
LT		 699};
700
979b6c13 701MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 702MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 703module_param(use_dac, int, 0);
4300e8c7 704MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 705module_param_named(debug, debug.msg_enable, int, 0);
706MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 707MODULE_LICENSE("GPL");
708MODULE_VERSION(RTL8169_VERSION);
bca03d5f 709MODULE_FIRMWARE(FIRMWARE_8168D_1);
710MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 711MODULE_FIRMWARE(FIRMWARE_8168E_1);
712MODULE_FIRMWARE(FIRMWARE_8168E_2);
bbb8af75 713MODULE_FIRMWARE(FIRMWARE_8168E_3);
5a5e4443 714MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 715
716static int rtl8169_open(struct net_device *dev);
61357325
SH		 717static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
718 struct net_device *dev);
7d12e780 719static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 720static int rtl8169_init_ring(struct net_device *dev);
07ce4064 721static void rtl_hw_start(struct net_device *dev);
1da177e4 722static int rtl8169_close(struct net_device *dev);
07ce4064 723static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 724static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 725static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 726static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 727 void __iomem *, u32 budget);
4dcb7d33 728static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 729static void rtl8169_down(struct net_device *dev);
99f252b0 730static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 731static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 732
b646d900 733static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
734{
735 void __iomem *ioaddr = tp->mmio_addr;
736 int i;
737
738 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
739 for (i = 0; i < 20; i++) {
740 udelay(100);
741 if (RTL_R32(OCPAR) & OCPAR_FLAG)
742 break;
743 }
744 return RTL_R32(OCPDR);
745}
746
747static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
748{
749 void __iomem *ioaddr = tp->mmio_addr;
750 int i;
751
752 RTL_W32(OCPDR, data);
753 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
754 for (i = 0; i < 20; i++) {
755 udelay(100);
756 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
757 break;
758 }
759}
760
fac5b3ca 761static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 762{
fac5b3ca 763 void __iomem *ioaddr = tp->mmio_addr;
b646d900 764 int i;
765
766 RTL_W8(ERIDR, cmd);
767 RTL_W32(ERIAR, 0x800010e8);
768 msleep(2);
769 for (i = 0; i < 5; i++) {
770 udelay(100);
1e4e82ba 771 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
b646d900 772 break;
773 }
774
fac5b3ca 775 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 776}
777
778#define OOB_CMD_RESET 0x00
779#define OOB_CMD_DRIVER_START 0x05
780#define OOB_CMD_DRIVER_STOP 0x06
781
cecb5fd7
FR		 782static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
783{
784 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
785}
786
b646d900 787static void rtl8168_driver_start(struct rtl8169_private *tp)
788{
cecb5fd7 789 u16 reg;
b646d900 790 int i;
791
792 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
793
cecb5fd7 794 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 795
b646d900 796 for (i = 0; i < 10; i++) {
797 msleep(10);
4804b3b3 798 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 799 break;
800 }
801}
802
803static void rtl8168_driver_stop(struct rtl8169_private *tp)
804{
cecb5fd7 805 u16 reg;
b646d900 806 int i;
807
808 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
809
cecb5fd7 810 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 811
b646d900 812 for (i = 0; i < 10; i++) {
813 msleep(10);
4804b3b3 814 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 815 break;
816 }
817}
818
4804b3b3 819static int r8168dp_check_dash(struct rtl8169_private *tp)
820{
cecb5fd7 821 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 822
cecb5fd7 823 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 824}
b646d900 825
4da19633 826static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 827{
828 int i;
829
a6baf3af 830 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 831
2371408c 832 for (i = 20; i > 0; i--) {
07d3f51f
FR		 833 /*
834 * Check if the RTL8169 has completed writing to the specified
835 * MII register.
836 */
5b0384f4 837 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 838 break;
2371408c 839 udelay(25);
1da177e4 840 }
024a07ba 841 /*
81a95f04
TT		 842 * According to hardware specs a 20us delay is required after write
843 * complete indication, but before sending next command.
024a07ba 844 */
81a95f04 845 udelay(20);
1da177e4
LT		 846}
847
4da19633 848static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 849{
850 int i, value = -1;
851
a6baf3af 852 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 853
2371408c 854 for (i = 20; i > 0; i--) {
07d3f51f
FR		 855 /*
856 * Check if the RTL8169 has completed retrieving data from
857 * the specified MII register.
858 */
1da177e4 859 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 860 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 861 break;
862 }
2371408c 863 udelay(25);
1da177e4 864 }
81a95f04
TT		 865 /*
866 * According to hardware specs a 20us delay is required after read
867 * complete indication, but before sending next command.
868 */
869 udelay(20);
870
1da177e4
LT		 871 return value;
872}
873
c0e45c1c 874static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
875{
876 int i;
877
878 RTL_W32(OCPDR, data |
879 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
880 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
881 RTL_W32(EPHY_RXER_NUM, 0);
882
883 for (i = 0; i < 100; i++) {
884 mdelay(1);
885 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
886 break;
887 }
888}
889
890static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
891{
892 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
893 (value & OCPDR_DATA_MASK));
894}
895
896static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
897{
898 int i;
899
900 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
901
902 mdelay(1);
903 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
904 RTL_W32(EPHY_RXER_NUM, 0);
905
906 for (i = 0; i < 100; i++) {
907 mdelay(1);
908 if (RTL_R32(OCPAR) & OCPAR_FLAG)
909 break;
910 }
911
912 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
913}
914
e6de30d6 915#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
916
917static void r8168dp_2_mdio_start(void __iomem *ioaddr)
918{
919 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
920}
921
922static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
923{
924 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
925}
926
927static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
928{
929 r8168dp_2_mdio_start(ioaddr);
930
931 r8169_mdio_write(ioaddr, reg_addr, value);
932
933 r8168dp_2_mdio_stop(ioaddr);
934}
935
936static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
937{
938 int value;
939
940 r8168dp_2_mdio_start(ioaddr);
941
942 value = r8169_mdio_read(ioaddr, reg_addr);
943
944 r8168dp_2_mdio_stop(ioaddr);
945
946 return value;
947}
948
4da19633 949static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 950{
c0e45c1c 951 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 952}
953
4da19633 954static int rtl_readphy(struct rtl8169_private *tp, int location)
955{
c0e45c1c 956 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 957}
958
959static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
960{
961 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
962}
963
964static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 965{
966 int val;
967
4da19633 968 val = rtl_readphy(tp, reg_addr);
969 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 970}
971
ccdffb9a
FR		 972static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
973 int val)
974{
975 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 976
4da19633 977 rtl_writephy(tp, location, val);
ccdffb9a
FR		 978}
979
980static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
981{
982 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 983
4da19633 984 return rtl_readphy(tp, location);
ccdffb9a
FR		 985}
986
dacf8154
FR		 987static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
988{
989 unsigned int i;
990
991 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
992 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
993
994 for (i = 0; i < 100; i++) {
995 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
996 break;
997 udelay(10);
998 }
999}
1000
1001static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
1002{
1003 u16 value = 0xffff;
1004 unsigned int i;
1005
1006 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1007
1008 for (i = 0; i < 100; i++) {
1009 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
1010 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
1011 break;
1012 }
1013 udelay(10);
1014 }
1015
1016 return value;
1017}
1018
1019static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1020{
1021 unsigned int i;
1022
1023 RTL_W32(CSIDR, value);
1024 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1025 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1026
1027 for (i = 0; i < 100; i++) {
1028 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1029 break;
1030 udelay(10);
1031 }
1032}
1033
1034static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1035{
1036 u32 value = ~0x00;
1037 unsigned int i;
1038
1039 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1040 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1041
1042 for (i = 0; i < 100; i++) {
1043 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1044 value = RTL_R32(CSIDR);
1045 break;
1046 }
1047 udelay(10);
1048 }
1049
1050 return value;
1051}
1052
133ac40a
HW		 1053static
1054void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type)
1055{
1056 unsigned int i;
1057
1058 BUG_ON((addr & 3) || (mask == 0));
1059 RTL_W32(ERIDR, val);
1060 RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1061
1062 for (i = 0; i < 100; i++) {
1063 if (!(RTL_R32(ERIAR) & ERIAR_FLAG))
1064 break;
1065 udelay(100);
1066 }
1067}
1068
1069static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type)
1070{
1071 u32 value = ~0x00;
1072 unsigned int i;
1073
1074 RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1075
1076 for (i = 0; i < 100; i++) {
1077 if (RTL_R32(ERIAR) & ERIAR_FLAG) {
1078 value = RTL_R32(ERIDR);
1079 break;
1080 }
1081 udelay(100);
1082 }
1083
1084 return value;
1085}
1086
1087static void
1088rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type)
1089{
1090 u32 val;
1091
1092 val = rtl_eri_read(ioaddr, addr, type);
1093 rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type);
1094}
1095
c28aa385 1096struct exgmac_reg {
1097 u16 addr;
1098 u16 mask;
1099 u32 val;
1100};
1101
1102static void rtl_write_exgmac_batch(void __iomem *ioaddr,
1103 const struct exgmac_reg *r, int len)
1104{
1105 while (len-- > 0) {
1106 rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1107 r++;
1108 }
1109}
1110
daf9df6d 1111static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1112{
1113 u8 value = 0xff;
1114 unsigned int i;
1115
1116 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1117
1118 for (i = 0; i < 300; i++) {
1119 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1120 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1121 break;
1122 }
1123 udelay(100);
1124 }
1125
1126 return value;
1127}
1128
1da177e4
LT		 1129static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1130{
1131 RTL_W16(IntrMask, 0x0000);
1132
1133 RTL_W16(IntrStatus, 0xffff);
1134}
1135
4da19633 1136static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1137{
4da19633 1138 void __iomem *ioaddr = tp->mmio_addr;
1139
1da177e4
LT		 1140 return RTL_R32(TBICSR) & TBIReset;
1141}
1142
4da19633 1143static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1144{
4da19633 1145 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1146}
1147
1148static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1149{
1150 return RTL_R32(TBICSR) & TBILinkOk;
1151}
1152
1153static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1154{
1155 return RTL_R8(PHYstatus) & LinkStatus;
1156}
1157
4da19633 1158static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1159{
4da19633 1160 void __iomem *ioaddr = tp->mmio_addr;
1161
1da177e4
LT		 1162 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1163}
1164
4da19633 1165static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1166{
1167 unsigned int val;
1168
4da19633 1169 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1170 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1171}
1172
70090424
HW		 1173static void rtl_link_chg_patch(struct rtl8169_private *tp)
1174{
1175 void __iomem *ioaddr = tp->mmio_addr;
1176 struct net_device *dev = tp->dev;
1177
1178 if (!netif_running(dev))
1179 return;
1180
1181 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
1182 if (RTL_R8(PHYstatus) & _1000bpsF) {
1183 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1184 0x00000011, ERIAR_EXGMAC);
1185 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1186 0x00000005, ERIAR_EXGMAC);
1187 } else if (RTL_R8(PHYstatus) & _100bps) {
1188 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1189 0x0000001f, ERIAR_EXGMAC);
1190 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1191 0x00000005, ERIAR_EXGMAC);
1192 } else {
1193 rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111,
1194 0x0000001f, ERIAR_EXGMAC);
1195 rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111,
1196 0x0000003f, ERIAR_EXGMAC);
1197 }
1198 /* Reset packet filter */
1199 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1200 ERIAR_EXGMAC);
1201 rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1202 ERIAR_EXGMAC);
1203 }
1204}
1205
e4fbce74 1206static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1207 struct rtl8169_private *tp,
1208 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1209{
1210 unsigned long flags;
1211
1212 spin_lock_irqsave(&tp->lock, flags);
1213 if (tp->link_ok(ioaddr)) {
70090424 1214 rtl_link_chg_patch(tp);
e1759441 1215 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1216 if (pm)
1217 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1218 netif_carrier_on(dev);
1519e57f
FR		 1219 if (net_ratelimit())
1220 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1221 } else {
1da177e4 1222 netif_carrier_off(dev);
bf82c189 1223 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1224 if (pm)
1225 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1226 }
1da177e4
LT		 1227 spin_unlock_irqrestore(&tp->lock, flags);
1228}
1229
e4fbce74
RW		 1230static void rtl8169_check_link_status(struct net_device *dev,
1231 struct rtl8169_private *tp,
1232 void __iomem *ioaddr)
1233{
1234 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1235}
1236
e1759441
RW		 1237#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1238
1239static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1240{
61a4dcc2
FR		 1241 void __iomem *ioaddr = tp->mmio_addr;
1242 u8 options;
e1759441 1243 u32 wolopts = 0;
61a4dcc2
FR		 1244
1245 options = RTL_R8(Config1);
1246 if (!(options & PMEnable))
e1759441 1247 return 0;
61a4dcc2
FR		 1248
1249 options = RTL_R8(Config3);
1250 if (options & LinkUp)
e1759441 1251 wolopts |= WAKE_PHY;
61a4dcc2 1252 if (options & MagicPacket)
e1759441 1253 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1254
1255 options = RTL_R8(Config5);
1256 if (options & UWF)
e1759441 1257 wolopts |= WAKE_UCAST;
61a4dcc2 1258 if (options & BWF)
e1759441 1259 wolopts |= WAKE_BCAST;
61a4dcc2 1260 if (options & MWF)
e1759441 1261 wolopts |= WAKE_MCAST;
61a4dcc2 1262
e1759441 1263 return wolopts;
61a4dcc2
FR		 1264}
1265
e1759441 1266static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1267{
1268 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1269
1270 spin_lock_irq(&tp->lock);
1271
1272 wol->supported = WAKE_ANY;
1273 wol->wolopts = __rtl8169_get_wol(tp);
1274
1275 spin_unlock_irq(&tp->lock);
1276}
1277
1278static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1279{
61a4dcc2 1280 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1281 unsigned int i;
350f7596 1282 static const struct {
61a4dcc2
FR		 1283 u32 opt;
1284 u16 reg;
1285 u8 mask;
1286 } cfg[] = {
1287 { WAKE_ANY, Config1, PMEnable },
1288 { WAKE_PHY, Config3, LinkUp },
1289 { WAKE_MAGIC, Config3, MagicPacket },
1290 { WAKE_UCAST, Config5, UWF },
1291 { WAKE_BCAST, Config5, BWF },
1292 { WAKE_MCAST, Config5, MWF },
1293 { WAKE_ANY, Config5, LanWake }
1294 };
1295
61a4dcc2
FR		 1296 RTL_W8(Cfg9346, Cfg9346_Unlock);
1297
1298 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1299 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1300 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1301 options |= cfg[i].mask;
1302 RTL_W8(cfg[i].reg, options);
1303 }
1304
1305 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1306}
1307
1308static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1309{
1310 struct rtl8169_private *tp = netdev_priv(dev);
1311
1312 spin_lock_irq(&tp->lock);
61a4dcc2 1313
f23e7fda
FR		 1314 if (wol->wolopts)
1315 tp->features |= RTL_FEATURE_WOL;
1316 else
1317 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1318 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1319 spin_unlock_irq(&tp->lock);
1320
ea80907f 1321 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1322
61a4dcc2
FR		 1323 return 0;
1324}
1325
31bd204f
FR		 1326static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1327{
85bffe6c 1328 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1329}
1330
1da177e4
LT		 1331static void rtl8169_get_drvinfo(struct net_device *dev,
1332 struct ethtool_drvinfo *info)
1333{
1334 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1335 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4
LT		 1336
1337 strcpy(info->driver, MODULENAME);
1338 strcpy(info->version, RTL8169_VERSION);
1339 strcpy(info->bus_info, pci_name(tp->pci_dev));
1c361efb
FR		 1340 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1341 strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1342 rtl_fw->version);
1da177e4
LT		 1343}
1344
1345static int rtl8169_get_regs_len(struct net_device *dev)
1346{
1347 return R8169_REGS_SIZE;
1348}
1349
1350static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1351 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1352{
1353 struct rtl8169_private *tp = netdev_priv(dev);
1354 void __iomem *ioaddr = tp->mmio_addr;
1355 int ret = 0;
1356 u32 reg;
1357
1358 reg = RTL_R32(TBICSR);
1359 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1360 (duplex == DUPLEX_FULL)) {
1361 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1362 } else if (autoneg == AUTONEG_ENABLE)
1363 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1364 else {
bf82c189
JP		 1365 netif_warn(tp, link, dev,
1366 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1367 ret = -EOPNOTSUPP;
1368 }
1369
1370 return ret;
1371}
1372
1373static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1374 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1375{
1376 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1377 int giga_ctrl, bmcr;
54405cde 1378 int rc = -EINVAL;
1da177e4 1379
716b50a3 1380 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1381
1382 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1383 int auto_nego;
1384
4da19633 1385 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1386 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1387 ADVERTISE_100HALF | ADVERTISE_100FULL);
1388
1389 if (adv & ADVERTISED_10baseT_Half)
1390 auto_nego |= ADVERTISE_10HALF;
1391 if (adv & ADVERTISED_10baseT_Full)
1392 auto_nego |= ADVERTISE_10FULL;
1393 if (adv & ADVERTISED_100baseT_Half)
1394 auto_nego |= ADVERTISE_100HALF;
1395 if (adv & ADVERTISED_100baseT_Full)
1396 auto_nego |= ADVERTISE_100FULL;
1397
3577aa1b 1398 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1399
4da19633 1400 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1401 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1402
3577aa1b 1403 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1404 if (tp->mii.supports_gmii) {
54405cde
ON		 1405 if (adv & ADVERTISED_1000baseT_Half)
1406 giga_ctrl |= ADVERTISE_1000HALF;
1407 if (adv & ADVERTISED_1000baseT_Full)
1408 giga_ctrl |= ADVERTISE_1000FULL;
1409 } else if (adv & (ADVERTISED_1000baseT_Half |
1410 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1411 netif_info(tp, link, dev,
1412 "PHY does not support 1000Mbps\n");
54405cde 1413 goto out;
bcf0bf90 1414 }
1da177e4 1415
3577aa1b 1416 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1417
4da19633 1418 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1419 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1420 } else {
1421 giga_ctrl = 0;
1422
1423 if (speed == SPEED_10)
1424 bmcr = 0;
1425 else if (speed == SPEED_100)
1426 bmcr = BMCR_SPEED100;
1427 else
54405cde 1428 goto out;
3577aa1b 1429
1430 if (duplex == DUPLEX_FULL)
1431 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1432 }
1433
4da19633 1434 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1435
cecb5fd7
FR		 1436 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1437 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1438 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1439 rtl_writephy(tp, 0x17, 0x2138);
1440 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1441 } else {
4da19633 1442 rtl_writephy(tp, 0x17, 0x2108);
1443 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1444 }
1445 }
1446
54405cde
ON		 1447 rc = 0;
1448out:
1449 return rc;
1da177e4
LT		 1450}
1451
1452static int rtl8169_set_speed(struct net_device *dev,
54405cde 1453 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1454{
1455 struct rtl8169_private *tp = netdev_priv(dev);
1456 int ret;
1457
54405cde 1458 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1459 if (ret < 0)
1460 goto out;
1da177e4 1461
4876cc1e
FR		 1462 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1463 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1464 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1465 }
1466out:
1da177e4
LT		 1467 return ret;
1468}
1469
1470static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1471{
1472 struct rtl8169_private *tp = netdev_priv(dev);
1473 unsigned long flags;
1474 int ret;
1475
4876cc1e
FR		 1476 del_timer_sync(&tp->timer);
1477
1da177e4 1478 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1479 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1480 cmd->duplex, cmd->advertising);
1da177e4 1481 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1482
1da177e4
LT		 1483 return ret;
1484}
1485
350fb32a 1486static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1487{
2b7b4318 1488 if (dev->mtu > TD_MSS_MAX)
350fb32a 1489 features &= ~NETIF_F_ALL_TSO;
1da177e4 1490
350fb32a 1491 return features;
1da177e4
LT		 1492}
1493
350fb32a 1494static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1495{
1496 struct rtl8169_private *tp = netdev_priv(dev);
1497 void __iomem *ioaddr = tp->mmio_addr;
1498 unsigned long flags;
1499
1500 spin_lock_irqsave(&tp->lock, flags);
1501
350fb32a 1502 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1503 tp->cp_cmd |= RxChkSum;
1504 else
1505 tp->cp_cmd &= ~RxChkSum;
1506
350fb32a
MM		 1507 if (dev->features & NETIF_F_HW_VLAN_RX)
1508 tp->cp_cmd |= RxVlan;
1509 else
1510 tp->cp_cmd &= ~RxVlan;
1511
1da177e4
LT		 1512 RTL_W16(CPlusCmd, tp->cp_cmd);
1513 RTL_R16(CPlusCmd);
1514
1515 spin_unlock_irqrestore(&tp->lock, flags);
1516
1517 return 0;
1518}
1519
1da177e4
LT		 1520static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1521 struct sk_buff *skb)
1522{
eab6d18d 1523 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1524 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1525}
1526
7a8fc77b 1527static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1528{
1529 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1530
7a8fc77b
FR		 1531 if (opts2 & RxVlanTag)
1532 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1533
1da177e4 1534 desc->opts2 = 0;
1da177e4
LT		 1535}
1536
ccdffb9a 1537static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1538{
1539 struct rtl8169_private *tp = netdev_priv(dev);
1540 void __iomem *ioaddr = tp->mmio_addr;
1541 u32 status;
1542
1543 cmd->supported =
1544 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1545 cmd->port = PORT_FIBRE;
1546 cmd->transceiver = XCVR_INTERNAL;
1547
1548 status = RTL_R32(TBICSR);
1549 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1550 cmd->autoneg = !!(status & TBINwEnable);
1551
70739497 1552 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1553 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1554
1555 return 0;
1da177e4
LT		 1556}
1557
ccdffb9a 1558static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1559{
1560 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1561
1562 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1563}
1564
1565static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1566{
1567 struct rtl8169_private *tp = netdev_priv(dev);
1568 unsigned long flags;
ccdffb9a 1569 int rc;
1da177e4
LT		 1570
1571 spin_lock_irqsave(&tp->lock, flags);
1572
ccdffb9a 1573 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1574
1575 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1576 return rc;
1da177e4
LT		 1577}
1578
1579static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1580 void *p)
1581{
5b0384f4
FR		 1582 struct rtl8169_private *tp = netdev_priv(dev);
1583 unsigned long flags;
1da177e4 1584
5b0384f4
FR		 1585 if (regs->len > R8169_REGS_SIZE)
1586 regs->len = R8169_REGS_SIZE;
1da177e4 1587
5b0384f4
FR		 1588 spin_lock_irqsave(&tp->lock, flags);
1589 memcpy_fromio(p, tp->mmio_addr, regs->len);
1590 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1591}
1592
b57b7e5a
SH		 1593static u32 rtl8169_get_msglevel(struct net_device *dev)
1594{
1595 struct rtl8169_private *tp = netdev_priv(dev);
1596
1597 return tp->msg_enable;
1598}
1599
1600static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1601{
1602 struct rtl8169_private *tp = netdev_priv(dev);
1603
1604 tp->msg_enable = value;
1605}
1606
d4a3a0fc
SH		 1607static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1608 "tx_packets",
1609 "rx_packets",
1610 "tx_errors",
1611 "rx_errors",
1612 "rx_missed",
1613 "align_errors",
1614 "tx_single_collisions",
1615 "tx_multi_collisions",
1616 "unicast",
1617 "broadcast",
1618 "multicast",
1619 "tx_aborted",
1620 "tx_underrun",
1621};
1622
b9f2c044 1623static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1624{
b9f2c044
JG		 1625 switch (sset) {
1626 case ETH_SS_STATS:
1627 return ARRAY_SIZE(rtl8169_gstrings);
1628 default:
1629 return -EOPNOTSUPP;
1630 }
d4a3a0fc
SH		 1631}
1632
355423d0 1633static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1634{
1635 struct rtl8169_private *tp = netdev_priv(dev);
1636 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1637 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1638 struct rtl8169_counters *counters;
1639 dma_addr_t paddr;
1640 u32 cmd;
355423d0 1641 int wait = 1000;
d4a3a0fc 1642
355423d0
IV		 1643 /*
1644 * Some chips are unable to dump tally counters when the receiver
1645 * is disabled.
1646 */
1647 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1648 return;
d4a3a0fc 1649
48addcc9 1650 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1651 if (!counters)
1652 return;
1653
1654 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1655 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1656 RTL_W32(CounterAddrLow, cmd);
1657 RTL_W32(CounterAddrLow, cmd | CounterDump);
1658
355423d0
IV		 1659 while (wait--) {
1660 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1661 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1662 break;
355423d0
IV		 1663 }
1664 udelay(10);
d4a3a0fc
SH		 1665 }
1666
1667 RTL_W32(CounterAddrLow, 0);
1668 RTL_W32(CounterAddrHigh, 0);
1669
48addcc9 1670 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1671}
1672
355423d0
IV		 1673static void rtl8169_get_ethtool_stats(struct net_device *dev,
1674 struct ethtool_stats *stats, u64 *data)
1675{
1676 struct rtl8169_private *tp = netdev_priv(dev);
1677
1678 ASSERT_RTNL();
1679
1680 rtl8169_update_counters(dev);
1681
1682 data[0] = le64_to_cpu(tp->counters.tx_packets);
1683 data[1] = le64_to_cpu(tp->counters.rx_packets);
1684 data[2] = le64_to_cpu(tp->counters.tx_errors);
1685 data[3] = le32_to_cpu(tp->counters.rx_errors);
1686 data[4] = le16_to_cpu(tp->counters.rx_missed);
1687 data[5] = le16_to_cpu(tp->counters.align_errors);
1688 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1689 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1690 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1691 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1692 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1693 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1694 data[12] = le16_to_cpu(tp->counters.tx_underun);
1695}
1696
d4a3a0fc
SH		 1697static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1698{
1699 switch(stringset) {
1700 case ETH_SS_STATS:
1701 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1702 break;
1703 }
1704}
1705
7282d491 1706static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1707 .get_drvinfo = rtl8169_get_drvinfo,
1708 .get_regs_len = rtl8169_get_regs_len,
1709 .get_link = ethtool_op_get_link,
1710 .get_settings = rtl8169_get_settings,
1711 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1712 .get_msglevel = rtl8169_get_msglevel,
1713 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1714 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1715 .get_wol = rtl8169_get_wol,
1716 .set_wol = rtl8169_set_wol,
d4a3a0fc 1717 .get_strings = rtl8169_get_strings,
b9f2c044 1718 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1719 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1720};
1721
07d3f51f 1722static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1723 struct net_device *dev, u8 default_version)
1da177e4 1724{
5d320a20 1725 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1726 /*
1727 * The driver currently handles the 8168Bf and the 8168Be identically
1728 * but they can be identified more specifically through the test below
1729 * if needed:
1730 *
1731 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1732 *
1733 * Same thing for the 8101Eb and the 8101Ec:
1734 *
1735 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1736 */
3744100e 1737 static const struct rtl_mac_info {
1da177e4 1738 u32 mask;
e3cf0cc0 1739 u32 val;
1da177e4
LT		 1740 int mac_version;
1741 } mac_info[] = {
01dc7fec 1742 /* 8168E family. */
70090424 1743 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
01dc7fec 1744 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1745 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1746 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1747
5b538df9 1748 /* 8168D family. */
daf9df6d 1749 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1750 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1751 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1752
e6de30d6 1753 /* 8168DP family. */
1754 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1755 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1756 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1757
ef808d50 1758 /* 8168C family. */
17c99297 1759 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1760 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1761 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1762 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1763 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1764 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1765 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1766 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1767 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1768
1769 /* 8168B family. */
1770 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1771 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1772 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1773 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1774
1775 /* 8101 family. */
36a0e6c2 1776 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1777 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1778 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1779 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1780 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1781 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1782 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1783 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1784 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1785 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1786 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1787 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1788 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1789 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1790 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1791 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1792 /* FIXME: where did these entries come from ? -- FR */
1793 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1794 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1795
1796 /* 8110 family. */
1797 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1798 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1799 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1800 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1801 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1802 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1803
f21b75e9
JD		 1804 /* Catch-all */
1805 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
3744100e
FR		 1806 };
1807 const struct rtl_mac_info *p = mac_info;
1da177e4
LT		 1808 u32 reg;
1809
e3cf0cc0
FR		 1810 reg = RTL_R32(TxConfig);
1811 while ((reg & p->mask) != p->val)
1da177e4
LT		 1812 p++;
1813 tp->mac_version = p->mac_version;
5d320a20
FR		 1814
1815 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1816 netif_notice(tp, probe, dev,
1817 "unknown MAC, using family default\n");
1818 tp->mac_version = default_version;
1819 }
1da177e4
LT		 1820}
1821
1822static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1823{
bcf0bf90 1824 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1825}
1826
867763c1
FR		 1827struct phy_reg {
1828 u16 reg;
1829 u16 val;
1830};
1831
4da19633 1832static void rtl_writephy_batch(struct rtl8169_private *tp,
1833 const struct phy_reg *regs, int len)
867763c1
FR		 1834{
1835 while (len-- > 0) {
4da19633 1836 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1837 regs++;
1838 }
1839}
1840
bca03d5f 1841#define PHY_READ 0x00000000
1842#define PHY_DATA_OR 0x10000000
1843#define PHY_DATA_AND 0x20000000
1844#define PHY_BJMPN 0x30000000
1845#define PHY_READ_EFUSE 0x40000000
1846#define PHY_READ_MAC_BYTE 0x50000000
1847#define PHY_WRITE_MAC_BYTE 0x60000000
1848#define PHY_CLEAR_READCOUNT 0x70000000
1849#define PHY_WRITE 0x80000000
1850#define PHY_READCOUNT_EQ_SKIP 0x90000000
1851#define PHY_COMP_EQ_SKIPN 0xa0000000
1852#define PHY_COMP_NEQ_SKIPN 0xb0000000
1853#define PHY_WRITE_PREVIOUS 0xc0000000
1854#define PHY_SKIPN 0xd0000000
1855#define PHY_DELAY_MS 0xe0000000
1856#define PHY_WRITE_ERI_WORD 0xf0000000
1857
960aee6c
HW		 1858struct fw_info {
1859 u32 magic;
1860 char version[RTL_VER_SIZE];
1861 __le32 fw_start;
1862 __le32 fw_len;
1863 u8 chksum;
1864} __packed;
1865
1c361efb
FR		 1866#define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1867
1868static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 1869{
b6ffd97f 1870 const struct firmware *fw = rtl_fw->fw;
960aee6c 1871 struct fw_info *fw_info = (struct fw_info *)fw->data;
1c361efb
FR		 1872 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1873 char *version = rtl_fw->version;
1874 bool rc = false;
1875
1876 if (fw->size < FW_OPCODE_SIZE)
1877 goto out;
960aee6c
HW		 1878
1879 if (!fw_info->magic) {
1880 size_t i, size, start;
1881 u8 checksum = 0;
1882
1883 if (fw->size < sizeof(*fw_info))
1884 goto out;
1885
1886 for (i = 0; i < fw->size; i++)
1887 checksum += fw->data[i];
1888 if (checksum != 0)
1889 goto out;
1890
1891 start = le32_to_cpu(fw_info->fw_start);
1892 if (start > fw->size)
1893 goto out;
1894
1895 size = le32_to_cpu(fw_info->fw_len);
1896 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1897 goto out;
1898
1899 memcpy(version, fw_info->version, RTL_VER_SIZE);
1900
1901 pa->code = (__le32 *)(fw->data + start);
1902 pa->size = size;
1903 } else {
1c361efb
FR		 1904 if (fw->size % FW_OPCODE_SIZE)
1905 goto out;
1906
1907 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1908
1909 pa->code = (__le32 *)fw->data;
1910 pa->size = fw->size / FW_OPCODE_SIZE;
1911 }
1912 version[RTL_VER_SIZE - 1] = 0;
1913
1914 rc = true;
1915out:
1916 return rc;
1917}
1918
fd112f2e
FR		 1919static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1920 struct rtl_fw_phy_action *pa)
1c361efb 1921{
fd112f2e 1922 bool rc = false;
1c361efb 1923 size_t index;
bca03d5f 1924
1c361efb
FR		 1925 for (index = 0; index < pa->size; index++) {
1926 u32 action = le32_to_cpu(pa->code[index]);
42b82dc1 1927 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1928
42b82dc1 1929 switch(action & 0xf0000000) {
1930 case PHY_READ:
1931 case PHY_DATA_OR:
1932 case PHY_DATA_AND:
1933 case PHY_READ_EFUSE:
1934 case PHY_CLEAR_READCOUNT:
1935 case PHY_WRITE:
1936 case PHY_WRITE_PREVIOUS:
1937 case PHY_DELAY_MS:
1938 break;
1939
1940 case PHY_BJMPN:
1941 if (regno > index) {
fd112f2e 1942 netif_err(tp, ifup, tp->dev,
cecb5fd7 1943 "Out of range of firmware\n");
fd112f2e 1944 goto out;
42b82dc1 1945 }
1946 break;
1947 case PHY_READCOUNT_EQ_SKIP:
1c361efb 1948 if (index + 2 >= pa->size) {
fd112f2e 1949 netif_err(tp, ifup, tp->dev,
cecb5fd7 1950 "Out of range of firmware\n");
fd112f2e 1951 goto out;
42b82dc1 1952 }
1953 break;
1954 case PHY_COMP_EQ_SKIPN:
1955 case PHY_COMP_NEQ_SKIPN:
1956 case PHY_SKIPN:
1c361efb 1957 if (index + 1 + regno >= pa->size) {
fd112f2e 1958 netif_err(tp, ifup, tp->dev,
cecb5fd7 1959 "Out of range of firmware\n");
fd112f2e 1960 goto out;
42b82dc1 1961 }
bca03d5f 1962 break;
1963
42b82dc1 1964 case PHY_READ_MAC_BYTE:
1965 case PHY_WRITE_MAC_BYTE:
1966 case PHY_WRITE_ERI_WORD:
1967 default:
fd112f2e 1968 netif_err(tp, ifup, tp->dev,
42b82dc1 1969 "Invalid action 0x%08x\n", action);
fd112f2e 1970 goto out;
bca03d5f 1971 }
1972 }
fd112f2e
FR		 1973 rc = true;
1974out:
1975 return rc;
1976}
bca03d5f 1977
fd112f2e
FR		 1978static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1979{
1980 struct net_device *dev = tp->dev;
1981 int rc = -EINVAL;
1982
1983 if (!rtl_fw_format_ok(tp, rtl_fw)) {
1984 netif_err(tp, ifup, dev, "invalid firwmare\n");
1985 goto out;
1986 }
1987
1988 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1989 rc = 0;
1990out:
1991 return rc;
1992}
1993
1994static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1995{
1996 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1997 u32 predata, count;
1998 size_t index;
1999
2000 predata = count = 0;
42b82dc1 2001
1c361efb
FR		 2002 for (index = 0; index < pa->size; ) {
2003 u32 action = le32_to_cpu(pa->code[index]);
bca03d5f 2004 u32 data = action & 0x0000ffff;
42b82dc1 2005 u32 regno = (action & 0x0fff0000) >> 16;
2006
2007 if (!action)
2008 break;
bca03d5f 2009
2010 switch(action & 0xf0000000) {
42b82dc1 2011 case PHY_READ:
2012 predata = rtl_readphy(tp, regno);
2013 count++;
2014 index++;
2015 break;
2016 case PHY_DATA_OR:
2017 predata |= data;
2018 index++;
2019 break;
2020 case PHY_DATA_AND:
2021 predata &= data;
2022 index++;
2023 break;
2024 case PHY_BJMPN:
2025 index -= regno;
2026 break;
2027 case PHY_READ_EFUSE:
2028 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
2029 index++;
2030 break;
2031 case PHY_CLEAR_READCOUNT:
2032 count = 0;
2033 index++;
2034 break;
bca03d5f 2035 case PHY_WRITE:
42b82dc1 2036 rtl_writephy(tp, regno, data);
2037 index++;
2038 break;
2039 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 2040 index += (count == data) ? 2 : 1;
bca03d5f 2041 break;
42b82dc1 2042 case PHY_COMP_EQ_SKIPN:
2043 if (predata == data)
2044 index += regno;
2045 index++;
2046 break;
2047 case PHY_COMP_NEQ_SKIPN:
2048 if (predata != data)
2049 index += regno;
2050 index++;
2051 break;
2052 case PHY_WRITE_PREVIOUS:
2053 rtl_writephy(tp, regno, predata);
2054 index++;
2055 break;
2056 case PHY_SKIPN:
2057 index += regno + 1;
2058 break;
2059 case PHY_DELAY_MS:
2060 mdelay(data);
2061 index++;
2062 break;
2063
2064 case PHY_READ_MAC_BYTE:
2065 case PHY_WRITE_MAC_BYTE:
2066 case PHY_WRITE_ERI_WORD:
bca03d5f 2067 default:
2068 BUG();
2069 }
2070 }
2071}
2072
f1e02ed1 2073static void rtl_release_firmware(struct rtl8169_private *tp)
2074{
b6ffd97f
FR		 2075 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2076 release_firmware(tp->rtl_fw->fw);
2077 kfree(tp->rtl_fw);
2078 }
2079 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 2080}
2081
953a12cc 2082static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 2083{
b6ffd97f 2084 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 2085
2086 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 2087 if (!IS_ERR_OR_NULL(rtl_fw))
2088 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 2089}
2090
2091static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2092{
2093 if (rtl_readphy(tp, reg) != val)
2094 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2095 else
2096 rtl_apply_firmware(tp);
f1e02ed1 2097}
2098
4da19633 2099static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 2100{
350f7596 2101 static const struct phy_reg phy_reg_init[] = {
0b9b571d 2102 { 0x1f, 0x0001 },
2103 { 0x06, 0x006e },
2104 { 0x08, 0x0708 },
2105 { 0x15, 0x4000 },
2106 { 0x18, 0x65c7 },
1da177e4 2107
0b9b571d 2108 { 0x1f, 0x0001 },
2109 { 0x03, 0x00a1 },
2110 { 0x02, 0x0008 },
2111 { 0x01, 0x0120 },
2112 { 0x00, 0x1000 },
2113 { 0x04, 0x0800 },
2114 { 0x04, 0x0000 },
1da177e4 2115
0b9b571d 2116 { 0x03, 0xff41 },
2117 { 0x02, 0xdf60 },
2118 { 0x01, 0x0140 },
2119 { 0x00, 0x0077 },
2120 { 0x04, 0x7800 },
2121 { 0x04, 0x7000 },
2122
2123 { 0x03, 0x802f },
2124 { 0x02, 0x4f02 },
2125 { 0x01, 0x0409 },
2126 { 0x00, 0xf0f9 },
2127 { 0x04, 0x9800 },
2128 { 0x04, 0x9000 },
2129
2130 { 0x03, 0xdf01 },
2131 { 0x02, 0xdf20 },
2132 { 0x01, 0xff95 },
2133 { 0x00, 0xba00 },
2134 { 0x04, 0xa800 },
2135 { 0x04, 0xa000 },
2136
2137 { 0x03, 0xff41 },
2138 { 0x02, 0xdf20 },
2139 { 0x01, 0x0140 },
2140 { 0x00, 0x00bb },
2141 { 0x04, 0xb800 },
2142 { 0x04, 0xb000 },
2143
2144 { 0x03, 0xdf41 },
2145 { 0x02, 0xdc60 },
2146 { 0x01, 0x6340 },
2147 { 0x00, 0x007d },
2148 { 0x04, 0xd800 },
2149 { 0x04, 0xd000 },
2150
2151 { 0x03, 0xdf01 },
2152 { 0x02, 0xdf20 },
2153 { 0x01, 0x100a },
2154 { 0x00, 0xa0ff },
2155 { 0x04, 0xf800 },
2156 { 0x04, 0xf000 },
2157
2158 { 0x1f, 0x0000 },
2159 { 0x0b, 0x0000 },
2160 { 0x00, 0x9200 }
2161 };
1da177e4 2162
4da19633 2163 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 2164}
2165
4da19633 2166static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 2167{
350f7596 2168 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 2169 { 0x1f, 0x0002 },
2170 { 0x01, 0x90d0 },
2171 { 0x1f, 0x0000 }
2172 };
2173
4da19633 2174 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 2175}
2176
4da19633 2177static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 2178{
2179 struct pci_dev *pdev = tp->pci_dev;
2e955856 2180
ccbae55e
SS		 2181 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2182 (pdev->subsystem_device != 0xe000))
2e955856 2183 return;
2184
4da19633 2185 rtl_writephy(tp, 0x1f, 0x0001);
2186 rtl_writephy(tp, 0x10, 0xf01b);
2187 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2188}
2189
4da19633 2190static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2191{
350f7596 2192 static const struct phy_reg phy_reg_init[] = {
2e955856 2193 { 0x1f, 0x0001 },
2194 { 0x04, 0x0000 },
2195 { 0x03, 0x00a1 },
2196 { 0x02, 0x0008 },
2197 { 0x01, 0x0120 },
2198 { 0x00, 0x1000 },
2199 { 0x04, 0x0800 },
2200 { 0x04, 0x9000 },
2201 { 0x03, 0x802f },
2202 { 0x02, 0x4f02 },
2203 { 0x01, 0x0409 },
2204 { 0x00, 0xf099 },
2205 { 0x04, 0x9800 },
2206 { 0x04, 0xa000 },
2207 { 0x03, 0xdf01 },
2208 { 0x02, 0xdf20 },
2209 { 0x01, 0xff95 },
2210 { 0x00, 0xba00 },
2211 { 0x04, 0xa800 },
2212 { 0x04, 0xf000 },
2213 { 0x03, 0xdf01 },
2214 { 0x02, 0xdf20 },
2215 { 0x01, 0x101a },
2216 { 0x00, 0xa0ff },
2217 { 0x04, 0xf800 },
2218 { 0x04, 0x0000 },
2219 { 0x1f, 0x0000 },
2220
2221 { 0x1f, 0x0001 },
2222 { 0x10, 0xf41b },
2223 { 0x14, 0xfb54 },
2224 { 0x18, 0xf5c7 },
2225 { 0x1f, 0x0000 },
2226
2227 { 0x1f, 0x0001 },
2228 { 0x17, 0x0cc0 },
2229 { 0x1f, 0x0000 }
2230 };
2231
4da19633 2232 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2233
4da19633 2234 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2235}
2236
4da19633 2237static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2238{
350f7596 2239 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2240 { 0x1f, 0x0001 },
2241 { 0x04, 0x0000 },
2242 { 0x03, 0x00a1 },
2243 { 0x02, 0x0008 },
2244 { 0x01, 0x0120 },
2245 { 0x00, 0x1000 },
2246 { 0x04, 0x0800 },
2247 { 0x04, 0x9000 },
2248 { 0x03, 0x802f },
2249 { 0x02, 0x4f02 },
2250 { 0x01, 0x0409 },
2251 { 0x00, 0xf099 },
2252 { 0x04, 0x9800 },
2253 { 0x04, 0xa000 },
2254 { 0x03, 0xdf01 },
2255 { 0x02, 0xdf20 },
2256 { 0x01, 0xff95 },
2257 { 0x00, 0xba00 },
2258 { 0x04, 0xa800 },
2259 { 0x04, 0xf000 },
2260 { 0x03, 0xdf01 },
2261 { 0x02, 0xdf20 },
2262 { 0x01, 0x101a },
2263 { 0x00, 0xa0ff },
2264 { 0x04, 0xf800 },
2265 { 0x04, 0x0000 },
2266 { 0x1f, 0x0000 },
2267
2268 { 0x1f, 0x0001 },
2269 { 0x0b, 0x8480 },
2270 { 0x1f, 0x0000 },
2271
2272 { 0x1f, 0x0001 },
2273 { 0x18, 0x67c7 },
2274 { 0x04, 0x2000 },
2275 { 0x03, 0x002f },
2276 { 0x02, 0x4360 },
2277 { 0x01, 0x0109 },
2278 { 0x00, 0x3022 },
2279 { 0x04, 0x2800 },
2280 { 0x1f, 0x0000 },
2281
2282 { 0x1f, 0x0001 },
2283 { 0x17, 0x0cc0 },
2284 { 0x1f, 0x0000 }
2285 };
2286
4da19633 2287 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2288}
2289
4da19633 2290static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2291{
350f7596 2292 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2293 { 0x10, 0xf41b },
2294 { 0x1f, 0x0000 }
2295 };
2296
4da19633 2297 rtl_writephy(tp, 0x1f, 0x0001);
2298 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2299
4da19633 2300 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2301}
2302
4da19633 2303static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2304{
350f7596 2305 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2306 { 0x1f, 0x0001 },
2307 { 0x10, 0xf41b },
2308 { 0x1f, 0x0000 }
2309 };
2310
4da19633 2311 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2312}
2313
4da19633 2314static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2315{
350f7596 2316 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2317 { 0x1f, 0x0000 },
2318 { 0x1d, 0x0f00 },
2319 { 0x1f, 0x0002 },
2320 { 0x0c, 0x1ec8 },
2321 { 0x1f, 0x0000 }
2322 };
2323
4da19633 2324 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2325}
2326
4da19633 2327static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2328{
350f7596 2329 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2330 { 0x1f, 0x0001 },
2331 { 0x1d, 0x3d98 },
2332 { 0x1f, 0x0000 }
2333 };
2334
4da19633 2335 rtl_writephy(tp, 0x1f, 0x0000);
2336 rtl_patchphy(tp, 0x14, 1 << 5);
2337 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2338
4da19633 2339 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2340}
2341
4da19633 2342static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2343{
350f7596 2344 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2345 { 0x1f, 0x0001 },
2346 { 0x12, 0x2300 },
867763c1
FR		 2347 { 0x1f, 0x0002 },
2348 { 0x00, 0x88d4 },
2349 { 0x01, 0x82b1 },
2350 { 0x03, 0x7002 },
2351 { 0x08, 0x9e30 },
2352 { 0x09, 0x01f0 },
2353 { 0x0a, 0x5500 },
2354 { 0x0c, 0x00c8 },
2355 { 0x1f, 0x0003 },
2356 { 0x12, 0xc096 },
2357 { 0x16, 0x000a },
f50d4275
FR		 2358 { 0x1f, 0x0000 },
2359 { 0x1f, 0x0000 },
2360 { 0x09, 0x2000 },
2361 { 0x09, 0x0000 }
867763c1
FR		 2362 };
2363
4da19633 2364 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2365
4da19633 2366 rtl_patchphy(tp, 0x14, 1 << 5);
2367 rtl_patchphy(tp, 0x0d, 1 << 5);
2368 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2369}
2370
4da19633 2371static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2372{
350f7596 2373 static const struct phy_reg phy_reg_init[] = {
f50d4275 2374 { 0x1f, 0x0001 },
7da97ec9 2375 { 0x12, 0x2300 },
f50d4275
FR		 2376 { 0x03, 0x802f },
2377 { 0x02, 0x4f02 },
2378 { 0x01, 0x0409 },
2379 { 0x00, 0xf099 },
2380 { 0x04, 0x9800 },
2381 { 0x04, 0x9000 },
2382 { 0x1d, 0x3d98 },
7da97ec9
FR		 2383 { 0x1f, 0x0002 },
2384 { 0x0c, 0x7eb8 },
f50d4275
FR		 2385 { 0x06, 0x0761 },
2386 { 0x1f, 0x0003 },
2387 { 0x16, 0x0f0a },
7da97ec9
FR		 2388 { 0x1f, 0x0000 }
2389 };
2390
4da19633 2391 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2392
4da19633 2393 rtl_patchphy(tp, 0x16, 1 << 0);
2394 rtl_patchphy(tp, 0x14, 1 << 5);
2395 rtl_patchphy(tp, 0x0d, 1 << 5);
2396 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2397}
2398
4da19633 2399static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2400{
350f7596 2401 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2402 { 0x1f, 0x0001 },
2403 { 0x12, 0x2300 },
2404 { 0x1d, 0x3d98 },
2405 { 0x1f, 0x0002 },
2406 { 0x0c, 0x7eb8 },
2407 { 0x06, 0x5461 },
2408 { 0x1f, 0x0003 },
2409 { 0x16, 0x0f0a },
2410 { 0x1f, 0x0000 }
2411 };
2412
4da19633 2413 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2414
4da19633 2415 rtl_patchphy(tp, 0x16, 1 << 0);
2416 rtl_patchphy(tp, 0x14, 1 << 5);
2417 rtl_patchphy(tp, 0x0d, 1 << 5);
2418 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2419}
2420
4da19633 2421static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2422{
4da19633 2423 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2424}
2425
bca03d5f 2426static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2427{
350f7596 2428 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2429 /* Channel Estimation */
5b538df9 2430 { 0x1f, 0x0001 },
daf9df6d 2431 { 0x06, 0x4064 },
2432 { 0x07, 0x2863 },
2433 { 0x08, 0x059c },
2434 { 0x09, 0x26b4 },
2435 { 0x0a, 0x6a19 },
2436 { 0x0b, 0xdcc8 },
2437 { 0x10, 0xf06d },
2438 { 0x14, 0x7f68 },
2439 { 0x18, 0x7fd9 },
2440 { 0x1c, 0xf0ff },
2441 { 0x1d, 0x3d9c },
5b538df9 2442 { 0x1f, 0x0003 },
daf9df6d 2443 { 0x12, 0xf49f },
2444 { 0x13, 0x070b },
2445 { 0x1a, 0x05ad },
bca03d5f 2446 { 0x14, 0x94c0 },
2447
2448 /*
2449 * Tx Error Issue
cecb5fd7 2450 * Enhance line driver power
bca03d5f 2451 */
5b538df9 2452 { 0x1f, 0x0002 },
daf9df6d 2453 { 0x06, 0x5561 },
2454 { 0x1f, 0x0005 },
2455 { 0x05, 0x8332 },
bca03d5f 2456 { 0x06, 0x5561 },
2457
2458 /*
2459 * Can not link to 1Gbps with bad cable
2460 * Decrease SNR threshold form 21.07dB to 19.04dB
2461 */
2462 { 0x1f, 0x0001 },
2463 { 0x17, 0x0cc0 },
daf9df6d 2464
5b538df9 2465 { 0x1f, 0x0000 },
bca03d5f 2466 { 0x0d, 0xf880 }
daf9df6d 2467 };
bca03d5f 2468 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2469
4da19633 2470 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2471
bca03d5f 2472 /*
2473 * Rx Error Issue
2474 * Fine Tune Switching regulator parameter
2475 */
4da19633 2476 rtl_writephy(tp, 0x1f, 0x0002);
2477 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2478 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2479
daf9df6d 2480 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2481 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2482 { 0x1f, 0x0002 },
2483 { 0x05, 0x669a },
2484 { 0x1f, 0x0005 },
2485 { 0x05, 0x8330 },
2486 { 0x06, 0x669a },
2487 { 0x1f, 0x0002 }
2488 };
2489 int val;
2490
4da19633 2491 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2492
4da19633 2493 val = rtl_readphy(tp, 0x0d);
daf9df6d 2494
2495 if ((val & 0x00ff) != 0x006c) {
350f7596 2496 static const u32 set[] = {
daf9df6d 2497 0x0065, 0x0066, 0x0067, 0x0068,
2498 0x0069, 0x006a, 0x006b, 0x006c
2499 };
2500 int i;
2501
4da19633 2502 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2503
2504 val &= 0xff00;
2505 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2506 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2507 }
2508 } else {
350f7596 2509 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2510 { 0x1f, 0x0002 },
2511 { 0x05, 0x6662 },
2512 { 0x1f, 0x0005 },
2513 { 0x05, 0x8330 },
2514 { 0x06, 0x6662 }
2515 };
2516
4da19633 2517 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2518 }
2519
bca03d5f 2520 /* RSET couple improve */
4da19633 2521 rtl_writephy(tp, 0x1f, 0x0002);
2522 rtl_patchphy(tp, 0x0d, 0x0300);
2523 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2524
bca03d5f 2525 /* Fine tune PLL performance */
4da19633 2526 rtl_writephy(tp, 0x1f, 0x0002);
2527 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2528 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2529
4da19633 2530 rtl_writephy(tp, 0x1f, 0x0005);
2531 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2532
2533 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2534
4da19633 2535 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2536}
2537
bca03d5f 2538static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2539{
350f7596 2540 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2541 /* Channel Estimation */
daf9df6d 2542 { 0x1f, 0x0001 },
2543 { 0x06, 0x4064 },
2544 { 0x07, 0x2863 },
2545 { 0x08, 0x059c },
2546 { 0x09, 0x26b4 },
2547 { 0x0a, 0x6a19 },
2548 { 0x0b, 0xdcc8 },
2549 { 0x10, 0xf06d },
2550 { 0x14, 0x7f68 },
2551 { 0x18, 0x7fd9 },
2552 { 0x1c, 0xf0ff },
2553 { 0x1d, 0x3d9c },
2554 { 0x1f, 0x0003 },
2555 { 0x12, 0xf49f },
2556 { 0x13, 0x070b },
2557 { 0x1a, 0x05ad },
2558 { 0x14, 0x94c0 },
2559
bca03d5f 2560 /*
2561 * Tx Error Issue
cecb5fd7 2562 * Enhance line driver power
bca03d5f 2563 */
daf9df6d 2564 { 0x1f, 0x0002 },
2565 { 0x06, 0x5561 },
2566 { 0x1f, 0x0005 },
2567 { 0x05, 0x8332 },
bca03d5f 2568 { 0x06, 0x5561 },
2569
2570 /*
2571 * Can not link to 1Gbps with bad cable
2572 * Decrease SNR threshold form 21.07dB to 19.04dB
2573 */
2574 { 0x1f, 0x0001 },
2575 { 0x17, 0x0cc0 },
daf9df6d 2576
2577 { 0x1f, 0x0000 },
bca03d5f 2578 { 0x0d, 0xf880 }
5b538df9 2579 };
bca03d5f 2580 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2581
4da19633 2582 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2583
daf9df6d 2584 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2585 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2586 { 0x1f, 0x0002 },
2587 { 0x05, 0x669a },
5b538df9 2588 { 0x1f, 0x0005 },
daf9df6d 2589 { 0x05, 0x8330 },
2590 { 0x06, 0x669a },
2591
2592 { 0x1f, 0x0002 }
2593 };
2594 int val;
2595
4da19633 2596 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2597
4da19633 2598 val = rtl_readphy(tp, 0x0d);
daf9df6d 2599 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2600 static const u32 set[] = {
daf9df6d 2601 0x0065, 0x0066, 0x0067, 0x0068,
2602 0x0069, 0x006a, 0x006b, 0x006c
2603 };
2604 int i;
2605
4da19633 2606 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2607
2608 val &= 0xff00;
2609 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2610 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2611 }
2612 } else {
350f7596 2613 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2614 { 0x1f, 0x0002 },
2615 { 0x05, 0x2642 },
5b538df9 2616 { 0x1f, 0x0005 },
daf9df6d 2617 { 0x05, 0x8330 },
2618 { 0x06, 0x2642 }
5b538df9
FR		 2619 };
2620
4da19633 2621 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2622 }
2623
bca03d5f 2624 /* Fine tune PLL performance */
4da19633 2625 rtl_writephy(tp, 0x1f, 0x0002);
2626 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2627 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2628
bca03d5f 2629 /* Switching regulator Slew rate */
4da19633 2630 rtl_writephy(tp, 0x1f, 0x0002);
2631 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2632
4da19633 2633 rtl_writephy(tp, 0x1f, 0x0005);
2634 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2635
2636 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2637
4da19633 2638 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2639}
2640
4da19633 2641static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2642{
350f7596 2643 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2644 { 0x1f, 0x0002 },
2645 { 0x10, 0x0008 },
2646 { 0x0d, 0x006c },
2647
2648 { 0x1f, 0x0000 },
2649 { 0x0d, 0xf880 },
2650
2651 { 0x1f, 0x0001 },
2652 { 0x17, 0x0cc0 },
2653
2654 { 0x1f, 0x0001 },
2655 { 0x0b, 0xa4d8 },
2656 { 0x09, 0x281c },
2657 { 0x07, 0x2883 },
2658 { 0x0a, 0x6b35 },
2659 { 0x1d, 0x3da4 },
2660 { 0x1c, 0xeffd },
2661 { 0x14, 0x7f52 },
2662 { 0x18, 0x7fc6 },
2663 { 0x08, 0x0601 },
2664 { 0x06, 0x4063 },
2665 { 0x10, 0xf074 },
2666 { 0x1f, 0x0003 },
2667 { 0x13, 0x0789 },
2668 { 0x12, 0xf4bd },
2669 { 0x1a, 0x04fd },
2670 { 0x14, 0x84b0 },
2671 { 0x1f, 0x0000 },
2672 { 0x00, 0x9200 },
2673
2674 { 0x1f, 0x0005 },
2675 { 0x01, 0x0340 },
2676 { 0x1f, 0x0001 },
2677 { 0x04, 0x4000 },
2678 { 0x03, 0x1d21 },
2679 { 0x02, 0x0c32 },
2680 { 0x01, 0x0200 },
2681 { 0x00, 0x5554 },
2682 { 0x04, 0x4800 },
2683 { 0x04, 0x4000 },
2684 { 0x04, 0xf000 },
2685 { 0x03, 0xdf01 },
2686 { 0x02, 0xdf20 },
2687 { 0x01, 0x101a },
2688 { 0x00, 0xa0ff },
2689 { 0x04, 0xf800 },
2690 { 0x04, 0xf000 },
2691 { 0x1f, 0x0000 },
2692
2693 { 0x1f, 0x0007 },
2694 { 0x1e, 0x0023 },
2695 { 0x16, 0x0000 },
2696 { 0x1f, 0x0000 }
2697 };
2698
4da19633 2699 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2700}
2701
e6de30d6 2702static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2703{
2704 static const struct phy_reg phy_reg_init[] = {
2705 { 0x1f, 0x0001 },
2706 { 0x17, 0x0cc0 },
2707
2708 { 0x1f, 0x0007 },
2709 { 0x1e, 0x002d },
2710 { 0x18, 0x0040 },
2711 { 0x1f, 0x0000 }
2712 };
2713
2714 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2715 rtl_patchphy(tp, 0x0d, 1 << 5);
2716}
2717
70090424 2718static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
01dc7fec 2719{
2720 static const struct phy_reg phy_reg_init[] = {
2721 /* Enable Delay cap */
2722 { 0x1f, 0x0005 },
2723 { 0x05, 0x8b80 },
2724 { 0x06, 0xc896 },
2725 { 0x1f, 0x0000 },
2726
2727 /* Channel estimation fine tune */
2728 { 0x1f, 0x0001 },
2729 { 0x0b, 0x6c20 },
2730 { 0x07, 0x2872 },
2731 { 0x1c, 0xefff },
2732 { 0x1f, 0x0003 },
2733 { 0x14, 0x6420 },
2734 { 0x1f, 0x0000 },
2735
2736 /* Update PFM & 10M TX idle timer */
2737 { 0x1f, 0x0007 },
2738 { 0x1e, 0x002f },
2739 { 0x15, 0x1919 },
2740 { 0x1f, 0x0000 },
2741
2742 { 0x1f, 0x0007 },
2743 { 0x1e, 0x00ac },
2744 { 0x18, 0x0006 },
2745 { 0x1f, 0x0000 }
2746 };
2747
15ecd039
FR		 2748 rtl_apply_firmware(tp);
2749
01dc7fec 2750 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2751
2752 /* DCO enable for 10M IDLE Power */
2753 rtl_writephy(tp, 0x1f, 0x0007);
2754 rtl_writephy(tp, 0x1e, 0x0023);
2755 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2756 rtl_writephy(tp, 0x1f, 0x0000);
2757
2758 /* For impedance matching */
2759 rtl_writephy(tp, 0x1f, 0x0002);
2760 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2761 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2762
2763 /* PHY auto speed down */
2764 rtl_writephy(tp, 0x1f, 0x0007);
2765 rtl_writephy(tp, 0x1e, 0x002d);
2766 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2767 rtl_writephy(tp, 0x1f, 0x0000);
2768 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2769
2770 rtl_writephy(tp, 0x1f, 0x0005);
2771 rtl_writephy(tp, 0x05, 0x8b86);
2772 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2773 rtl_writephy(tp, 0x1f, 0x0000);
2774
2775 rtl_writephy(tp, 0x1f, 0x0005);
2776 rtl_writephy(tp, 0x05, 0x8b85);
2777 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2778 rtl_writephy(tp, 0x1f, 0x0007);
2779 rtl_writephy(tp, 0x1e, 0x0020);
2780 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2781 rtl_writephy(tp, 0x1f, 0x0006);
2782 rtl_writephy(tp, 0x00, 0x5a00);
2783 rtl_writephy(tp, 0x1f, 0x0000);
2784 rtl_writephy(tp, 0x0d, 0x0007);
2785 rtl_writephy(tp, 0x0e, 0x003c);
2786 rtl_writephy(tp, 0x0d, 0x4007);
2787 rtl_writephy(tp, 0x0e, 0x0000);
2788 rtl_writephy(tp, 0x0d, 0x0000);
2789}
2790
70090424
HW		 2791static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
2792{
2793 static const struct phy_reg phy_reg_init[] = {
2794 /* Enable Delay cap */
2795 { 0x1f, 0x0004 },
2796 { 0x1f, 0x0007 },
2797 { 0x1e, 0x00ac },
2798 { 0x18, 0x0006 },
2799 { 0x1f, 0x0002 },
2800 { 0x1f, 0x0000 },
2801 { 0x1f, 0x0000 },
2802
2803 /* Channel estimation fine tune */
2804 { 0x1f, 0x0003 },
2805 { 0x09, 0xa20f },
2806 { 0x1f, 0x0000 },
2807 { 0x1f, 0x0000 },
2808
2809 /* Green Setting */
2810 { 0x1f, 0x0005 },
2811 { 0x05, 0x8b5b },
2812 { 0x06, 0x9222 },
2813 { 0x05, 0x8b6d },
2814 { 0x06, 0x8000 },
2815 { 0x05, 0x8b76 },
2816 { 0x06, 0x8000 },
2817 { 0x1f, 0x0000 }
2818 };
2819
2820 rtl_apply_firmware(tp);
2821
2822 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2823
2824 /* For 4-corner performance improve */
2825 rtl_writephy(tp, 0x1f, 0x0005);
2826 rtl_writephy(tp, 0x05, 0x8b80);
2827 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2828 rtl_writephy(tp, 0x1f, 0x0000);
2829
2830 /* PHY auto speed down */
2831 rtl_writephy(tp, 0x1f, 0x0004);
2832 rtl_writephy(tp, 0x1f, 0x0007);
2833 rtl_writephy(tp, 0x1e, 0x002d);
2834 rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000);
2835 rtl_writephy(tp, 0x1f, 0x0002);
2836 rtl_writephy(tp, 0x1f, 0x0000);
2837 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2838
2839 /* improve 10M EEE waveform */
2840 rtl_writephy(tp, 0x1f, 0x0005);
2841 rtl_writephy(tp, 0x05, 0x8b86);
2842 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2843 rtl_writephy(tp, 0x1f, 0x0000);
2844
2845 /* Improve 2-pair detection performance */
2846 rtl_writephy(tp, 0x1f, 0x0005);
2847 rtl_writephy(tp, 0x05, 0x8b85);
2848 rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000);
2849 rtl_writephy(tp, 0x1f, 0x0000);
2850
2851 /* EEE setting */
2852 rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003,
2853 ERIAR_EXGMAC);
2854 rtl_writephy(tp, 0x1f, 0x0005);
2855 rtl_writephy(tp, 0x05, 0x8b85);
2856 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2857 rtl_writephy(tp, 0x1f, 0x0004);
2858 rtl_writephy(tp, 0x1f, 0x0007);
2859 rtl_writephy(tp, 0x1e, 0x0020);
2860 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100);
2861 rtl_writephy(tp, 0x1f, 0x0002);
2862 rtl_writephy(tp, 0x1f, 0x0000);
2863 rtl_writephy(tp, 0x0d, 0x0007);
2864 rtl_writephy(tp, 0x0e, 0x003c);
2865 rtl_writephy(tp, 0x0d, 0x4007);
2866 rtl_writephy(tp, 0x0e, 0x0000);
2867 rtl_writephy(tp, 0x0d, 0x0000);
2868
2869 /* Green feature */
2870 rtl_writephy(tp, 0x1f, 0x0003);
2871 rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001);
2872 rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400);
2873 rtl_writephy(tp, 0x1f, 0x0000);
2874}
2875
4da19633 2876static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2877{
350f7596 2878 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2879 { 0x1f, 0x0003 },
2880 { 0x08, 0x441d },
2881 { 0x01, 0x9100 },
2882 { 0x1f, 0x0000 }
2883 };
2884
4da19633 2885 rtl_writephy(tp, 0x1f, 0x0000);
2886 rtl_patchphy(tp, 0x11, 1 << 12);
2887 rtl_patchphy(tp, 0x19, 1 << 13);
2888 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2889
4da19633 2890 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2891}
2892
5a5e4443
HW		 2893static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2894{
2895 static const struct phy_reg phy_reg_init[] = {
2896 { 0x1f, 0x0005 },
2897 { 0x1a, 0x0000 },
2898 { 0x1f, 0x0000 },
2899
2900 { 0x1f, 0x0004 },
2901 { 0x1c, 0x0000 },
2902 { 0x1f, 0x0000 },
2903
2904 { 0x1f, 0x0001 },
2905 { 0x15, 0x7701 },
2906 { 0x1f, 0x0000 }
2907 };
2908
2909 /* Disable ALDPS before ram code */
2910 rtl_writephy(tp, 0x1f, 0x0000);
2911 rtl_writephy(tp, 0x18, 0x0310);
2912 msleep(100);
2913
953a12cc 2914 rtl_apply_firmware(tp);
5a5e4443
HW		 2915
2916 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2917}
2918
5615d9f1
FR		 2919static void rtl_hw_phy_config(struct net_device *dev)
2920{
2921 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2922
2923 rtl8169_print_mac_version(tp);
2924
2925 switch (tp->mac_version) {
2926 case RTL_GIGA_MAC_VER_01:
2927 break;
2928 case RTL_GIGA_MAC_VER_02:
2929 case RTL_GIGA_MAC_VER_03:
4da19633 2930 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2931 break;
2932 case RTL_GIGA_MAC_VER_04:
4da19633 2933 rtl8169sb_hw_phy_config(tp);
5615d9f1 2934 break;
2e955856 2935 case RTL_GIGA_MAC_VER_05:
4da19633 2936 rtl8169scd_hw_phy_config(tp);
2e955856 2937 break;
8c7006aa 2938 case RTL_GIGA_MAC_VER_06:
4da19633 2939 rtl8169sce_hw_phy_config(tp);
8c7006aa 2940 break;
2857ffb7
FR		 2941 case RTL_GIGA_MAC_VER_07:
2942 case RTL_GIGA_MAC_VER_08:
2943 case RTL_GIGA_MAC_VER_09:
4da19633 2944 rtl8102e_hw_phy_config(tp);
2857ffb7 2945 break;
236b8082 2946 case RTL_GIGA_MAC_VER_11:
4da19633 2947 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2948 break;
2949 case RTL_GIGA_MAC_VER_12:
4da19633 2950 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2951 break;
2952 case RTL_GIGA_MAC_VER_17:
4da19633 2953 rtl8168bef_hw_phy_config(tp);
236b8082 2954 break;
867763c1 2955 case RTL_GIGA_MAC_VER_18:
4da19633 2956 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2957 break;
2958 case RTL_GIGA_MAC_VER_19:
4da19633 2959 rtl8168c_1_hw_phy_config(tp);
867763c1 2960 break;
7da97ec9 2961 case RTL_GIGA_MAC_VER_20:
4da19633 2962 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2963 break;
197ff761 2964 case RTL_GIGA_MAC_VER_21:
4da19633 2965 rtl8168c_3_hw_phy_config(tp);
197ff761 2966 break;
6fb07058 2967 case RTL_GIGA_MAC_VER_22:
4da19633 2968 rtl8168c_4_hw_phy_config(tp);
6fb07058 2969 break;
ef3386f0 2970 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2971 case RTL_GIGA_MAC_VER_24:
4da19633 2972 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2973 break;
5b538df9 2974 case RTL_GIGA_MAC_VER_25:
bca03d5f 2975 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2976 break;
2977 case RTL_GIGA_MAC_VER_26:
bca03d5f 2978 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2979 break;
2980 case RTL_GIGA_MAC_VER_27:
4da19633 2981 rtl8168d_3_hw_phy_config(tp);
5b538df9 2982 break;
e6de30d6 2983 case RTL_GIGA_MAC_VER_28:
2984 rtl8168d_4_hw_phy_config(tp);
2985 break;
5a5e4443
HW		 2986 case RTL_GIGA_MAC_VER_29:
2987 case RTL_GIGA_MAC_VER_30:
2988 rtl8105e_hw_phy_config(tp);
2989 break;
cecb5fd7
FR		 2990 case RTL_GIGA_MAC_VER_31:
2991 /* None. */
2992 break;
01dc7fec 2993 case RTL_GIGA_MAC_VER_32:
01dc7fec 2994 case RTL_GIGA_MAC_VER_33:
70090424
HW		 2995 rtl8168e_1_hw_phy_config(tp);
2996 break;
2997 case RTL_GIGA_MAC_VER_34:
2998 rtl8168e_2_hw_phy_config(tp);
01dc7fec 2999 break;
ef3386f0 3000
5615d9f1
FR		 3001 default:
3002 break;
3003 }
3004}
3005
1da177e4
LT		 3006static void rtl8169_phy_timer(unsigned long __opaque)
3007{
3008 struct net_device *dev = (struct net_device *)__opaque;
3009 struct rtl8169_private *tp = netdev_priv(dev);
3010 struct timer_list *timer = &tp->timer;
3011 void __iomem *ioaddr = tp->mmio_addr;
3012 unsigned long timeout = RTL8169_PHY_TIMEOUT;
3013
bcf0bf90 3014 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 3015
1da177e4
LT		 3016 spin_lock_irq(&tp->lock);
3017
4da19633 3018 if (tp->phy_reset_pending(tp)) {
5b0384f4 3019 /*
1da177e4
LT		 3020 * A busy loop could burn quite a few cycles on nowadays CPU.
3021 * Let's delay the execution of the timer for a few ticks.
3022 */
3023 timeout = HZ/10;
3024 goto out_mod_timer;
3025 }
3026
3027 if (tp->link_ok(ioaddr))
3028 goto out_unlock;
3029
bf82c189 3030 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 3031
4da19633 3032 tp->phy_reset_enable(tp);
1da177e4
LT		 3033
3034out_mod_timer:
3035 mod_timer(timer, jiffies + timeout);
3036out_unlock:
3037 spin_unlock_irq(&tp->lock);
3038}
3039
1da177e4
LT		 3040#ifdef CONFIG_NET_POLL_CONTROLLER
3041/*
3042 * Polling 'interrupt' - used by things like netconsole to send skbs
3043 * without having to re-enable interrupts. It's not called while
3044 * the interrupt routine is executing.
3045 */
3046static void rtl8169_netpoll(struct net_device *dev)
3047{
3048 struct rtl8169_private *tp = netdev_priv(dev);
3049 struct pci_dev *pdev = tp->pci_dev;
3050
3051 disable_irq(pdev->irq);
7d12e780 3052 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 3053 enable_irq(pdev->irq);
3054}
3055#endif
3056
3057static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
3058 void __iomem *ioaddr)
3059{
3060 iounmap(ioaddr);
3061 pci_release_regions(pdev);
87aeec76 3062 pci_clear_mwi(pdev);
1da177e4
LT		 3063 pci_disable_device(pdev);
3064 free_netdev(dev);
3065}
3066
bf793295
FR		 3067static void rtl8169_phy_reset(struct net_device *dev,
3068 struct rtl8169_private *tp)
3069{
07d3f51f 3070 unsigned int i;
bf793295 3071
4da19633 3072 tp->phy_reset_enable(tp);
bf793295 3073 for (i = 0; i < 100; i++) {
4da19633 3074 if (!tp->phy_reset_pending(tp))
bf793295
FR		 3075 return;
3076 msleep(1);
3077 }
bf82c189 3078 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 3079}
3080
4ff96fa6
FR		 3081static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
3082{
3083 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 3084
5615d9f1 3085 rtl_hw_phy_config(dev);
4ff96fa6 3086
77332894
MS		 3087 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
3088 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3089 RTL_W8(0x82, 0x01);
3090 }
4ff96fa6 3091
6dccd16b
FR		 3092 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
3093
3094 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3095 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 3096
bcf0bf90 3097 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 3098 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
3099 RTL_W8(0x82, 0x01);
3100 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 3101 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 3102 }
3103
bf793295
FR		 3104 rtl8169_phy_reset(dev, tp);
3105
54405cde 3106 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 3107 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3108 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3109 (tp->mii.supports_gmii ?
3110 ADVERTISED_1000baseT_Half |
3111 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 3112
bf82c189
JP		 3113 if (RTL_R8(PHYstatus) & TBI_Enable)
3114 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 3115}
3116
773d2021
FR		 3117static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
3118{
3119 void __iomem *ioaddr = tp->mmio_addr;
3120 u32 high;
3121 u32 low;
3122
3123 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
3124 high = addr[4] | (addr[5] << 8);
3125
3126 spin_lock_irq(&tp->lock);
3127
3128 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 3129
773d2021 3130 RTL_W32(MAC4, high);
908ba2bf 3131 RTL_R32(MAC4);
3132
78f1cd02 3133 RTL_W32(MAC0, low);
908ba2bf 3134 RTL_R32(MAC0);
3135
c28aa385 3136 if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
3137 const struct exgmac_reg e[] = {
3138 { .addr = 0xe0, ERIAR_MASK_1111, .val = low },
3139 { .addr = 0xe4, ERIAR_MASK_1111, .val = high },
3140 { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 },
3141 { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 |
3142 low >> 16 },
3143 };
3144
3145 rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e));
3146 }
3147
773d2021
FR		 3148 RTL_W8(Cfg9346, Cfg9346_Lock);
3149
3150 spin_unlock_irq(&tp->lock);
3151}
3152
3153static int rtl_set_mac_address(struct net_device *dev, void *p)
3154{
3155 struct rtl8169_private *tp = netdev_priv(dev);
3156 struct sockaddr *addr = p;
3157
3158 if (!is_valid_ether_addr(addr->sa_data))
3159 return -EADDRNOTAVAIL;
3160
3161 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3162
3163 rtl_rar_set(tp, dev->dev_addr);
3164
3165 return 0;
3166}
3167
5f787a1a
FR		 3168static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3169{
3170 struct rtl8169_private *tp = netdev_priv(dev);
3171 struct mii_ioctl_data *data = if_mii(ifr);
3172
8b4ab28d
FR		 3173 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
3174}
5f787a1a 3175
cecb5fd7
FR		 3176static int rtl_xmii_ioctl(struct rtl8169_private *tp,
3177 struct mii_ioctl_data *data, int cmd)
8b4ab28d 3178{
5f787a1a
FR		 3179 switch (cmd) {
3180 case SIOCGMIIPHY:
3181 data->phy_id = 32; /* Internal PHY */
3182 return 0;
3183
3184 case SIOCGMIIREG:
4da19633 3185 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 3186 return 0;
3187
3188 case SIOCSMIIREG:
4da19633 3189 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 3190 return 0;
3191 }
3192 return -EOPNOTSUPP;
3193}
3194
8b4ab28d
FR		 3195static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
3196{
3197 return -EOPNOTSUPP;
3198}
3199
0e485150
FR		 3200static const struct rtl_cfg_info {
3201 void (*hw_start)(struct net_device *);
3202 unsigned int region;
3203 unsigned int align;
3204 u16 intr_event;
3205 u16 napi_event;
ccdffb9a 3206 unsigned features;
f21b75e9 3207 u8 default_ver;
0e485150
FR		 3208} rtl_cfg_infos [] = {
3209 [RTL_CFG_0] = {
3210 .hw_start = rtl_hw_start_8169,
3211 .region = 1,
e9f63f30 3212 .align = 0,
0e485150
FR		 3213 .intr_event = SYSErr | LinkChg | RxOverflow |
3214 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3215 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3216 .features = RTL_FEATURE_GMII,
3217 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 3218 },
3219 [RTL_CFG_1] = {
3220 .hw_start = rtl_hw_start_8168,
3221 .region = 2,
3222 .align = 8,
53f57357 3223 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 3224 TxErr | TxOK | RxOK | RxErr,
fbac58fc 3225 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3226 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3227 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 3228 },
3229 [RTL_CFG_2] = {
3230 .hw_start = rtl_hw_start_8101,
3231 .region = 2,
3232 .align = 8,
3233 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3234 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 3235 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 3236 .features = RTL_FEATURE_MSI,
3237 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 3238 }
3239};
3240
fbac58fc
FR		 3241/* Cfg9346_Unlock assumed. */
3242static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3243 const struct rtl_cfg_info *cfg)
3244{
3245 unsigned msi = 0;
3246 u8 cfg2;
3247
3248 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 3249 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 3250 if (pci_enable_msi(pdev)) {
3251 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3252 } else {
3253 cfg2 |= MSIEnable;
3254 msi = RTL_FEATURE_MSI;
3255 }
3256 }
3257 RTL_W8(Config2, cfg2);
3258 return msi;
3259}
3260
3261static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3262{
3263 if (tp->features & RTL_FEATURE_MSI) {
3264 pci_disable_msi(pdev);
3265 tp->features &= ~RTL_FEATURE_MSI;
3266 }
3267}
3268
8b4ab28d
FR		 3269static const struct net_device_ops rtl8169_netdev_ops = {
3270 .ndo_open = rtl8169_open,
3271 .ndo_stop = rtl8169_close,
3272 .ndo_get_stats = rtl8169_get_stats,
00829823 3273 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 3274 .ndo_tx_timeout = rtl8169_tx_timeout,
3275 .ndo_validate_addr = eth_validate_addr,
3276 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 3277 .ndo_fix_features = rtl8169_fix_features,
3278 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 3279 .ndo_set_mac_address = rtl_set_mac_address,
3280 .ndo_do_ioctl = rtl8169_ioctl,
3281 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 3282#ifdef CONFIG_NET_POLL_CONTROLLER
3283 .ndo_poll_controller = rtl8169_netpoll,
3284#endif
3285
3286};
3287
c0e45c1c 3288static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3289{
3290 struct mdio_ops *ops = &tp->mdio_ops;
3291
3292 switch (tp->mac_version) {
3293 case RTL_GIGA_MAC_VER_27:
3294 ops->write = r8168dp_1_mdio_write;
3295 ops->read = r8168dp_1_mdio_read;
3296 break;
e6de30d6 3297 case RTL_GIGA_MAC_VER_28:
4804b3b3 3298 case RTL_GIGA_MAC_VER_31:
e6de30d6 3299 ops->write = r8168dp_2_mdio_write;
3300 ops->read = r8168dp_2_mdio_read;
3301 break;
c0e45c1c 3302 default:
3303 ops->write = r8169_mdio_write;
3304 ops->read = r8169_mdio_read;
3305 break;
3306 }
3307}
3308
065c27c1 3309static void r810x_phy_power_down(struct rtl8169_private *tp)
3310{
3311 rtl_writephy(tp, 0x1f, 0x0000);
3312 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3313}
3314
3315static void r810x_phy_power_up(struct rtl8169_private *tp)
3316{
3317 rtl_writephy(tp, 0x1f, 0x0000);
3318 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3319}
3320
3321static void r810x_pll_power_down(struct rtl8169_private *tp)
3322{
10663389
HW		 3323 void __iomem *ioaddr = tp->mmio_addr;
3324
065c27c1 3325 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3326 rtl_writephy(tp, 0x1f, 0x0000);
3327 rtl_writephy(tp, MII_BMCR, 0x0000);
10663389
HW		 3328
3329 if (tp->mac_version == RTL_GIGA_MAC_VER_29 ||
3330 tp->mac_version == RTL_GIGA_MAC_VER_30)
3331 RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3332 AcceptMulticast | AcceptMyPhys);
065c27c1 3333 return;
3334 }
3335
3336 r810x_phy_power_down(tp);
3337}
3338
3339static void r810x_pll_power_up(struct rtl8169_private *tp)
3340{
3341 r810x_phy_power_up(tp);
3342}
3343
3344static void r8168_phy_power_up(struct rtl8169_private *tp)
3345{
3346 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3347 switch (tp->mac_version) {
3348 case RTL_GIGA_MAC_VER_11:
3349 case RTL_GIGA_MAC_VER_12:
3350 case RTL_GIGA_MAC_VER_17:
3351 case RTL_GIGA_MAC_VER_18:
3352 case RTL_GIGA_MAC_VER_19:
3353 case RTL_GIGA_MAC_VER_20:
3354 case RTL_GIGA_MAC_VER_21:
3355 case RTL_GIGA_MAC_VER_22:
3356 case RTL_GIGA_MAC_VER_23:
3357 case RTL_GIGA_MAC_VER_24:
3358 case RTL_GIGA_MAC_VER_25:
3359 case RTL_GIGA_MAC_VER_26:
3360 case RTL_GIGA_MAC_VER_27:
3361 case RTL_GIGA_MAC_VER_28:
3362 case RTL_GIGA_MAC_VER_31:
3363 rtl_writephy(tp, 0x0e, 0x0000);
3364 break;
3365 default:
3366 break;
3367 }
065c27c1 3368 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3369}
3370
3371static void r8168_phy_power_down(struct rtl8169_private *tp)
3372{
3373 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3374 switch (tp->mac_version) {
3375 case RTL_GIGA_MAC_VER_32:
3376 case RTL_GIGA_MAC_VER_33:
3377 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3378 break;
3379
3380 case RTL_GIGA_MAC_VER_11:
3381 case RTL_GIGA_MAC_VER_12:
3382 case RTL_GIGA_MAC_VER_17:
3383 case RTL_GIGA_MAC_VER_18:
3384 case RTL_GIGA_MAC_VER_19:
3385 case RTL_GIGA_MAC_VER_20:
3386 case RTL_GIGA_MAC_VER_21:
3387 case RTL_GIGA_MAC_VER_22:
3388 case RTL_GIGA_MAC_VER_23:
3389 case RTL_GIGA_MAC_VER_24:
3390 case RTL_GIGA_MAC_VER_25:
3391 case RTL_GIGA_MAC_VER_26:
3392 case RTL_GIGA_MAC_VER_27:
3393 case RTL_GIGA_MAC_VER_28:
3394 case RTL_GIGA_MAC_VER_31:
3395 rtl_writephy(tp, 0x0e, 0x0200);
3396 default:
3397 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3398 break;
3399 }
065c27c1 3400}
3401
3402static void r8168_pll_power_down(struct rtl8169_private *tp)
3403{
3404 void __iomem *ioaddr = tp->mmio_addr;
3405
cecb5fd7
FR		 3406 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3407 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3408 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3409 r8168dp_check_dash(tp)) {
065c27c1 3410 return;
5d2e1957 3411 }
065c27c1 3412
cecb5fd7
FR		 3413 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3414 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3415 (RTL_R16(CPlusCmd) & ASF)) {
3416 return;
3417 }
3418
01dc7fec 3419 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3420 tp->mac_version == RTL_GIGA_MAC_VER_33)
3421 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3422
065c27c1 3423 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3424 rtl_writephy(tp, 0x1f, 0x0000);
3425 rtl_writephy(tp, MII_BMCR, 0x0000);
3426
d4ed95d7 3427 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
10663389
HW		 3428 tp->mac_version == RTL_GIGA_MAC_VER_33 ||
3429 tp->mac_version == RTL_GIGA_MAC_VER_34)
d4ed95d7
HW		 3430 RTL_W32(RxConfig, RTL_R32(RxConfig) | AcceptBroadcast |
3431 AcceptMulticast | AcceptMyPhys);
065c27c1 3432 return;
3433 }
3434
3435 r8168_phy_power_down(tp);
3436
3437 switch (tp->mac_version) {
3438 case RTL_GIGA_MAC_VER_25:
3439 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3440 case RTL_GIGA_MAC_VER_27:
3441 case RTL_GIGA_MAC_VER_28:
4804b3b3 3442 case RTL_GIGA_MAC_VER_31:
01dc7fec 3443 case RTL_GIGA_MAC_VER_32:
3444 case RTL_GIGA_MAC_VER_33:
065c27c1 3445 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3446 break;
3447 }
3448}
3449
3450static void r8168_pll_power_up(struct rtl8169_private *tp)
3451{
3452 void __iomem *ioaddr = tp->mmio_addr;
3453
cecb5fd7
FR		 3454 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3455 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3456 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3457 r8168dp_check_dash(tp)) {
065c27c1 3458 return;
5d2e1957 3459 }
065c27c1 3460
3461 switch (tp->mac_version) {
3462 case RTL_GIGA_MAC_VER_25:
3463 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3464 case RTL_GIGA_MAC_VER_27:
3465 case RTL_GIGA_MAC_VER_28:
4804b3b3 3466 case RTL_GIGA_MAC_VER_31:
01dc7fec 3467 case RTL_GIGA_MAC_VER_32:
3468 case RTL_GIGA_MAC_VER_33:
065c27c1 3469 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3470 break;
3471 }
3472
3473 r8168_phy_power_up(tp);
3474}
3475
3476static void rtl_pll_power_op(struct rtl8169_private *tp,
3477 void (*op)(struct rtl8169_private *))
3478{
3479 if (op)
3480 op(tp);
3481}
3482
3483static void rtl_pll_power_down(struct rtl8169_private *tp)
3484{
3485 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3486}
3487
3488static void rtl_pll_power_up(struct rtl8169_private *tp)
3489{
3490 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3491}
3492
3493static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3494{
3495 struct pll_power_ops *ops = &tp->pll_power_ops;
3496
3497 switch (tp->mac_version) {
3498 case RTL_GIGA_MAC_VER_07:
3499 case RTL_GIGA_MAC_VER_08:
3500 case RTL_GIGA_MAC_VER_09:
3501 case RTL_GIGA_MAC_VER_10:
3502 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3503 case RTL_GIGA_MAC_VER_29:
3504 case RTL_GIGA_MAC_VER_30:
065c27c1 3505 ops->down = r810x_pll_power_down;
3506 ops->up = r810x_pll_power_up;
3507 break;
3508
3509 case RTL_GIGA_MAC_VER_11:
3510 case RTL_GIGA_MAC_VER_12:
3511 case RTL_GIGA_MAC_VER_17:
3512 case RTL_GIGA_MAC_VER_18:
3513 case RTL_GIGA_MAC_VER_19:
3514 case RTL_GIGA_MAC_VER_20:
3515 case RTL_GIGA_MAC_VER_21:
3516 case RTL_GIGA_MAC_VER_22:
3517 case RTL_GIGA_MAC_VER_23:
3518 case RTL_GIGA_MAC_VER_24:
3519 case RTL_GIGA_MAC_VER_25:
3520 case RTL_GIGA_MAC_VER_26:
3521 case RTL_GIGA_MAC_VER_27:
e6de30d6 3522 case RTL_GIGA_MAC_VER_28:
4804b3b3 3523 case RTL_GIGA_MAC_VER_31:
01dc7fec 3524 case RTL_GIGA_MAC_VER_32:
3525 case RTL_GIGA_MAC_VER_33:
70090424 3526 case RTL_GIGA_MAC_VER_34:
065c27c1 3527 ops->down = r8168_pll_power_down;
3528 ops->up = r8168_pll_power_up;
3529 break;
3530
3531 default:
3532 ops->down = NULL;
3533 ops->up = NULL;
3534 break;
3535 }
3536}
3537
e542a226
HW		 3538static void rtl_init_rxcfg(struct rtl8169_private *tp)
3539{
3540 void __iomem *ioaddr = tp->mmio_addr;
3541
3542 switch (tp->mac_version) {
3543 case RTL_GIGA_MAC_VER_01:
3544 case RTL_GIGA_MAC_VER_02:
3545 case RTL_GIGA_MAC_VER_03:
3546 case RTL_GIGA_MAC_VER_04:
3547 case RTL_GIGA_MAC_VER_05:
3548 case RTL_GIGA_MAC_VER_06:
3549 case RTL_GIGA_MAC_VER_10:
3550 case RTL_GIGA_MAC_VER_11:
3551 case RTL_GIGA_MAC_VER_12:
3552 case RTL_GIGA_MAC_VER_13:
3553 case RTL_GIGA_MAC_VER_14:
3554 case RTL_GIGA_MAC_VER_15:
3555 case RTL_GIGA_MAC_VER_16:
3556 case RTL_GIGA_MAC_VER_17:
3557 RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
3558 break;
3559 case RTL_GIGA_MAC_VER_18:
3560 case RTL_GIGA_MAC_VER_19:
3561 case RTL_GIGA_MAC_VER_20:
3562 case RTL_GIGA_MAC_VER_21:
3563 case RTL_GIGA_MAC_VER_22:
3564 case RTL_GIGA_MAC_VER_23:
3565 case RTL_GIGA_MAC_VER_24:
3566 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
3567 break;
3568 default:
3569 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
3570 break;
3571 }
3572}
3573
92fc43b4
HW		 3574static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3575{
3576 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3577}
3578
6f43adc8
FR		 3579static void rtl_hw_reset(struct rtl8169_private *tp)
3580{
3581 void __iomem *ioaddr = tp->mmio_addr;
3582 int i;
3583
3584 /* Soft reset the chip. */
3585 RTL_W8(ChipCmd, CmdReset);
3586
3587 /* Check that the chip has finished the reset. */
3588 for (i = 0; i < 100; i++) {
3589 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3590 break;
92fc43b4 3591 udelay(100);
6f43adc8 3592 }
92fc43b4
HW		 3593
3594 rtl8169_init_ring_indexes(tp);
6f43adc8
FR		 3595}
3596
1da177e4 3597static int __devinit
4ff96fa6 3598rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3599{
0e485150
FR		 3600 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3601 const unsigned int region = cfg->region;
1da177e4 3602 struct rtl8169_private *tp;
ccdffb9a 3603 struct mii_if_info *mii;
4ff96fa6
FR		 3604 struct net_device *dev;
3605 void __iomem *ioaddr;
2b7b4318 3606 int chipset, i;
07d3f51f 3607 int rc;
1da177e4 3608
4ff96fa6
FR		 3609 if (netif_msg_drv(&debug)) {
3610 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3611 MODULENAME, RTL8169_VERSION);
3612 }
1da177e4 3613
1da177e4 3614 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3615 if (!dev) {
b57b7e5a 3616 if (netif_msg_drv(&debug))
9b91cf9d 3617 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3618 rc = -ENOMEM;
3619 goto out;
1da177e4
LT		 3620 }
3621
1da177e4 3622 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3623 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3624 tp = netdev_priv(dev);
c4028958 3625 tp->dev = dev;
21e197f2 3626 tp->pci_dev = pdev;
b57b7e5a 3627 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3628
ccdffb9a
FR		 3629 mii = &tp->mii;
3630 mii->dev = dev;
3631 mii->mdio_read = rtl_mdio_read;
3632 mii->mdio_write = rtl_mdio_write;
3633 mii->phy_id_mask = 0x1f;
3634 mii->reg_num_mask = 0x1f;
3635 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3636
ba04c7c9
SG		 3637 /* disable ASPM completely as that cause random device stop working
3638 * problems as well as full system hangs for some PCIe devices users */
3639 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3640 PCIE_LINK_STATE_CLKPM);
3641
1da177e4
LT		 3642 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3643 rc = pci_enable_device(pdev);
b57b7e5a 3644 if (rc < 0) {
bf82c189 3645 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3646 goto err_out_free_dev_1;
1da177e4
LT		 3647 }
3648
87aeec76 3649 if (pci_set_mwi(pdev) < 0)
3650 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3651
1da177e4 3652 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3653 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3654 netif_err(tp, probe, dev,
3655 "region #%d not an MMIO resource, aborting\n",
3656 region);
1da177e4 3657 rc = -ENODEV;
87aeec76 3658 goto err_out_mwi_2;
1da177e4 3659 }
4ff96fa6 3660
1da177e4 3661 /* check for weird/broken PCI region reporting */
bcf0bf90 3662 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3663 netif_err(tp, probe, dev,
3664 "Invalid PCI region size(s), aborting\n");
1da177e4 3665 rc = -ENODEV;
87aeec76 3666 goto err_out_mwi_2;
1da177e4
LT		 3667 }
3668
3669 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3670 if (rc < 0) {
bf82c189 3671 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3672 goto err_out_mwi_2;
1da177e4
LT		 3673 }
3674
d24e9aaf 3675 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3676
3677 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3678 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3679 tp->cp_cmd |= PCIDAC;
3680 dev->features |= NETIF_F_HIGHDMA;
3681 } else {
284901a9 3682 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3683 if (rc < 0) {
bf82c189 3684 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3685 goto err_out_free_res_3;
1da177e4
LT		 3686 }
3687 }
3688
1da177e4 3689 /* ioremap MMIO region */
bcf0bf90 3690 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3691 if (!ioaddr) {
bf82c189 3692 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3693 rc = -EIO;
87aeec76 3694 goto err_out_free_res_3;
1da177e4 3695 }
6f43adc8 3696 tp->mmio_addr = ioaddr;
1da177e4 3697
e44daade
JM		 3698 if (!pci_is_pcie(pdev))
3699 netif_info(tp, probe, dev, "not PCI Express\n");
4300e8c7 3700
e542a226
HW		 3701 /* Identify chip attached to board */
3702 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3703
3704 rtl_init_rxcfg(tp);
3705
d78ad8cb 3706 RTL_W16(IntrMask, 0x0000);
1da177e4 3707
6f43adc8 3708 rtl_hw_reset(tp);
1da177e4 3709
d78ad8cb
KW		 3710 RTL_W16(IntrStatus, 0xffff);
3711
ca52efd5 3712 pci_set_master(pdev);
3713
7a8fc77b
FR		 3714 /*
3715 * Pretend we are using VLANs; This bypasses a nasty bug where
3716 * Interrupts stop flowing on high load on 8110SCd controllers.
3717 */
3718 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3719 tp->cp_cmd |= RxVlan;
3720
c0e45c1c 3721 rtl_init_mdio_ops(tp);
065c27c1 3722 rtl_init_pll_power_ops(tp);
c0e45c1c 3723
1da177e4 3724 rtl8169_print_mac_version(tp);
1da177e4 3725
85bffe6c
FR		 3726 chipset = tp->mac_version;
3727 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 3728
5d06a99f
FR		 3729 RTL_W8(Cfg9346, Cfg9346_Unlock);
3730 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3731 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3732 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3733 tp->features |= RTL_FEATURE_WOL;
3734 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3735 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3736 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3737 RTL_W8(Cfg9346, Cfg9346_Lock);
3738
66ec5d4f
FR		 3739 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3740 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3741 tp->set_speed = rtl8169_set_speed_tbi;
3742 tp->get_settings = rtl8169_gset_tbi;
3743 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3744 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3745 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3746 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 3747 } else {
3748 tp->set_speed = rtl8169_set_speed_xmii;
3749 tp->get_settings = rtl8169_gset_xmii;
3750 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3751 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3752 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3753 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3754 }
3755
df58ef51
FR		 3756 spin_lock_init(&tp->lock);
3757
7bf6bf48 3758 /* Get MAC address */
1da177e4
LT		 3759 for (i = 0; i < MAC_ADDR_LEN; i++)
3760 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3761 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3762
1da177e4 3763 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3764 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3765 dev->irq = pdev->irq;
3766 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3767
bea3348e 3768 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3769
350fb32a
MM		 3770 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3771 * properly for all devices */
3772 dev->features |= NETIF_F_RXCSUM |
3773 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3774
3775 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3776 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3777 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3778 NETIF_F_HIGHDMA;
3779
3780 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3781 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3782 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3783
3784 tp->intr_mask = 0xffff;
0e485150
FR		 3785 tp->hw_start = cfg->hw_start;
3786 tp->intr_event = cfg->intr_event;
3787 tp->napi_event = cfg->napi_event;
1da177e4 3788
2efa53f3
FR		 3789 init_timer(&tp->timer);
3790 tp->timer.data = (unsigned long) dev;
3791 tp->timer.function = rtl8169_phy_timer;
3792
b6ffd97f 3793 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
953a12cc 3794
1da177e4 3795 rc = register_netdev(dev);
4ff96fa6 3796 if (rc < 0)
87aeec76 3797 goto err_out_msi_4;
1da177e4
LT		 3798
3799 pci_set_drvdata(pdev, dev);
3800
bf82c189 3801 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 3802 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3803 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3804
cecb5fd7
FR		 3805 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3806 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3807 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3808 rtl8168_driver_start(tp);
e6de30d6 3809 }
b646d900 3810
8b76ab39 3811 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3812
f3ec4f87
AS		 3813 if (pci_dev_run_wake(pdev))
3814 pm_runtime_put_noidle(&pdev->dev);
e1759441 3815
0d672e9f
IV		 3816 netif_carrier_off(dev);
3817
4ff96fa6
FR		 3818out:
3819 return rc;
1da177e4 3820
87aeec76 3821err_out_msi_4:
fbac58fc 3822 rtl_disable_msi(pdev, tp);
4ff96fa6 3823 iounmap(ioaddr);
87aeec76 3824err_out_free_res_3:
4ff96fa6 3825 pci_release_regions(pdev);
87aeec76 3826err_out_mwi_2:
4ff96fa6 3827 pci_clear_mwi(pdev);
4ff96fa6
FR		 3828 pci_disable_device(pdev);
3829err_out_free_dev_1:
3830 free_netdev(dev);
3831 goto out;
1da177e4
LT		 3832}
3833
07d3f51f 3834static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3835{
3836 struct net_device *dev = pci_get_drvdata(pdev);
3837 struct rtl8169_private *tp = netdev_priv(dev);
3838
cecb5fd7
FR		 3839 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3840 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3841 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3842 rtl8168_driver_stop(tp);
e6de30d6 3843 }
b646d900 3844
23f333a2 3845 cancel_delayed_work_sync(&tp->task);
eb2a021c 3846
1da177e4 3847 unregister_netdev(dev);
cc098dc7 3848
953a12cc
FR		 3849 rtl_release_firmware(tp);
3850
f3ec4f87
AS		 3851 if (pci_dev_run_wake(pdev))
3852 pm_runtime_get_noresume(&pdev->dev);
e1759441 3853
cc098dc7
IV		 3854 /* restore original MAC address */
3855 rtl_rar_set(tp, dev->perm_addr);
3856
fbac58fc 3857 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3858 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3859 pci_set_drvdata(pdev, NULL);
3860}
3861
b6ffd97f 3862static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 3863{
b6ffd97f
FR		 3864 struct rtl_fw *rtl_fw;
3865 const char *name;
3866 int rc = -ENOMEM;
953a12cc 3867
b6ffd97f
FR		 3868 name = rtl_lookup_firmware_name(tp);
3869 if (!name)
3870 goto out_no_firmware;
953a12cc 3871
b6ffd97f
FR		 3872 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3873 if (!rtl_fw)
3874 goto err_warn;
31bd204f 3875
b6ffd97f
FR		 3876 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3877 if (rc < 0)
3878 goto err_free;
3879
fd112f2e
FR		 3880 rc = rtl_check_firmware(tp, rtl_fw);
3881 if (rc < 0)
3882 goto err_release_firmware;
3883
b6ffd97f
FR		 3884 tp->rtl_fw = rtl_fw;
3885out:
3886 return;
3887
fd112f2e
FR		 3888err_release_firmware:
3889 release_firmware(rtl_fw->fw);
b6ffd97f
FR		 3890err_free:
3891 kfree(rtl_fw);
3892err_warn:
3893 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3894 name, rc);
3895out_no_firmware:
3896 tp->rtl_fw = NULL;
3897 goto out;
3898}
3899
3900static void rtl_request_firmware(struct rtl8169_private *tp)
3901{
3902 if (IS_ERR(tp->rtl_fw))
3903 rtl_request_uncached_firmware(tp);
953a12cc
FR		 3904}
3905
1da177e4
LT		 3906static int rtl8169_open(struct net_device *dev)
3907{
3908 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3909 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3910 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3911 int retval = -ENOMEM;
1da177e4 3912
e1759441 3913 pm_runtime_get_sync(&pdev->dev);
1da177e4 3914
1da177e4
LT		 3915 /*
3916 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3917 * dma_alloc_coherent provides more.
1da177e4 3918 */
82553bb6
SG		 3919 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3920 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3921 if (!tp->TxDescArray)
e1759441 3922 goto err_pm_runtime_put;
1da177e4 3923
82553bb6
SG		 3924 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3925 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3926 if (!tp->RxDescArray)
99f252b0 3927 goto err_free_tx_0;
1da177e4
LT		 3928
3929 retval = rtl8169_init_ring(dev);
3930 if (retval < 0)
99f252b0 3931 goto err_free_rx_1;
1da177e4 3932
c4028958 3933 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3934
99f252b0
FR		 3935 smp_mb();
3936
953a12cc
FR		 3937 rtl_request_firmware(tp);
3938
fbac58fc
FR		 3939 retval = request_irq(dev->irq, rtl8169_interrupt,
3940 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3941 dev->name, dev);
3942 if (retval < 0)
953a12cc 3943 goto err_release_fw_2;
99f252b0 3944
bea3348e 3945 napi_enable(&tp->napi);
bea3348e 3946
eee3a96c 3947 rtl8169_init_phy(dev, tp);
3948
350fb32a 3949 rtl8169_set_features(dev, dev->features);
eee3a96c 3950
065c27c1 3951 rtl_pll_power_up(tp);
3952
07ce4064 3953 rtl_hw_start(dev);
1da177e4 3954
e1759441
RW		 3955 tp->saved_wolopts = 0;
3956 pm_runtime_put_noidle(&pdev->dev);
3957
eee3a96c 3958 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3959out:
3960 return retval;
3961
953a12cc
FR		 3962err_release_fw_2:
3963 rtl_release_firmware(tp);
99f252b0
FR		 3964 rtl8169_rx_clear(tp);
3965err_free_rx_1:
82553bb6
SG		 3966 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3967 tp->RxPhyAddr);
e1759441 3968 tp->RxDescArray = NULL;
99f252b0 3969err_free_tx_0:
82553bb6
SG		 3970 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3971 tp->TxPhyAddr);
e1759441
RW		 3972 tp->TxDescArray = NULL;
3973err_pm_runtime_put:
3974 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3975 goto out;
3976}
3977
92fc43b4
HW		 3978static void rtl_rx_close(struct rtl8169_private *tp)
3979{
3980 void __iomem *ioaddr = tp->mmio_addr;
92fc43b4 3981
1687b566 3982 RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
92fc43b4
HW		 3983}
3984
e6de30d6 3985static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3986{
e6de30d6 3987 void __iomem *ioaddr = tp->mmio_addr;
3988
1da177e4
LT		 3989 /* Disable interrupts */
3990 rtl8169_irq_mask_and_ack(ioaddr);
3991
92fc43b4
HW		 3992 rtl_rx_close(tp);
3993
5d2e1957 3994 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3995 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3996 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3997 while (RTL_R8(TxPoll) & NPQ)
3998 udelay(20);
70090424 3999 } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) {
c2b0c1e7 4000 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
70090424
HW		 4001 while (!(RTL_R32(TxConfig) & TXCFG_EMPTY))
4002 udelay(100);
92fc43b4
HW		 4003 } else {
4004 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
4005 udelay(100);
e6de30d6 4006 }
4007
92fc43b4 4008 rtl_hw_reset(tp);
1da177e4
LT		 4009}
4010
7f796d83 4011static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 4012{
4013 void __iomem *ioaddr = tp->mmio_addr;
9cb427b6
FR		 4014
4015 /* Set DMA burst size and Interframe Gap Time */
4016 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4017 (InterFrameGap << TxInterFrameGapShift));
4018}
4019
07ce4064 4020static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 4021{
4022 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4023
07ce4064
FR		 4024 tp->hw_start(dev);
4025
07ce4064
FR		 4026 netif_start_queue(dev);
4027}
4028
7f796d83
FR		 4029static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
4030 void __iomem *ioaddr)
4031{
4032 /*
4033 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4034 * register to be written before TxDescAddrLow to work.
4035 * Switching from MMIO to I/O access fixes the issue as well.
4036 */
4037 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 4038 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 4039 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 4040 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 4041}
4042
4043static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
4044{
4045 u16 cmd;
4046
4047 cmd = RTL_R16(CPlusCmd);
4048 RTL_W16(CPlusCmd, cmd);
4049 return cmd;
4050}
4051
fdd7b4c3 4052static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 4053{
4054 /* Low hurts. Let's disable the filtering. */
207d6e87 4055 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 4056}
4057
6dccd16b
FR		 4058static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
4059{
3744100e 4060 static const struct rtl_cfg2_info {
6dccd16b
FR		 4061 u32 mac_version;
4062 u32 clk;
4063 u32 val;
4064 } cfg2_info [] = {
4065 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4066 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4067 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4068 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3744100e
FR		 4069 };
4070 const struct rtl_cfg2_info *p = cfg2_info;
6dccd16b
FR		 4071 unsigned int i;
4072 u32 clk;
4073
4074 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 4075 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 4076 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4077 RTL_W32(0x7c, p->val);
4078 break;
4079 }
4080 }
4081}
4082
07ce4064
FR		 4083static void rtl_hw_start_8169(struct net_device *dev)
4084{
4085 struct rtl8169_private *tp = netdev_priv(dev);
4086 void __iomem *ioaddr = tp->mmio_addr;
4087 struct pci_dev *pdev = tp->pci_dev;
07ce4064 4088
9cb427b6
FR		 4089 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
4090 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
4091 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
4092 }
4093
1da177e4 4094 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 4095 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4096 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4097 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4098 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 4099 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4100
e542a226
HW		 4101 rtl_init_rxcfg(tp);
4102
f0298f81 4103 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 4104
6f0333b8 4105 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 4106
cecb5fd7
FR		 4107 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
4108 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4109 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
4110 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 4111 rtl_set_rx_tx_config_registers(tp);
1da177e4 4112
7f796d83 4113 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 4114
cecb5fd7
FR		 4115 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4116 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 4117 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 4118 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 4119 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 4120 }
4121
bcf0bf90
FR		 4122 RTL_W16(CPlusCmd, tp->cp_cmd);
4123
6dccd16b
FR		 4124 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
4125
1da177e4
LT		 4126 /*
4127 * Undocumented corner. Supposedly:
4128 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4129 */
4130 RTL_W16(IntrMitigate, 0x0000);
4131
7f796d83 4132 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 4133
cecb5fd7
FR		 4134 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
4135 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
4136 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
4137 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 4138 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4139 rtl_set_rx_tx_config_registers(tp);
4140 }
4141
1da177e4 4142 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 4143
4144 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4145 RTL_R8(IntrMask);
1da177e4
LT		 4146
4147 RTL_W32(RxMissed, 0);
4148
07ce4064 4149 rtl_set_rx_mode(dev);
1da177e4
LT		 4150
4151 /* no early-rx interrupts */
4152 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 4153
4154 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 4155 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4156}
1da177e4 4157
9c14ceaf 4158static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 4159{
e44daade 4160 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 4161
4162 if (cap) {
4163 u16 ctl;
458a9f61 4164
9c14ceaf
FR		 4165 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
4166 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
4167 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
4168 }
458a9f61
FR		 4169}
4170
650e8d5d 4171static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 4172{
4173 u32 csi;
4174
4175 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 4176 rtl_csi_write(ioaddr, 0x070c, csi | bits);
4177}
4178
e6de30d6 4179static void rtl_csi_access_enable_1(void __iomem *ioaddr)
4180{
4181 rtl_csi_access_enable(ioaddr, 0x17000000);
4182}
4183
650e8d5d 4184static void rtl_csi_access_enable_2(void __iomem *ioaddr)
4185{
4186 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 4187}
4188
4189struct ephy_info {
4190 unsigned int offset;
4191 u16 mask;
4192 u16 bits;
4193};
4194
350f7596 4195static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 4196{
4197 u16 w;
4198
4199 while (len-- > 0) {
4200 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
4201 rtl_ephy_write(ioaddr, e->offset, w);
4202 e++;
4203 }
4204}
4205
b726e493
FR		 4206static void rtl_disable_clock_request(struct pci_dev *pdev)
4207{
e44daade 4208 int cap = pci_pcie_cap(pdev);
b726e493
FR		 4209
4210 if (cap) {
4211 u16 ctl;
4212
4213 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4214 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
4215 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4216 }
4217}
4218
e6de30d6 4219static void rtl_enable_clock_request(struct pci_dev *pdev)
4220{
e44daade 4221 int cap = pci_pcie_cap(pdev);
e6de30d6 4222
4223 if (cap) {
4224 u16 ctl;
4225
4226 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
4227 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
4228 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
4229 }
4230}
4231
b726e493
FR		 4232#define R8168_CPCMD_QUIRK_MASK (\
4233 EnableBist | \
4234 Mac_dbgo_oe | \
4235 Force_half_dup | \
4236 Force_rxflow_en | \
4237 Force_txflow_en | \
4238 Cxpl_dbg_sel | \
4239 ASF | \
4240 PktCntrDisable | \
4241 Mac_dbgo_sel)
4242
219a1e9d
FR		 4243static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
4244{
b726e493
FR		 4245 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4246
4247 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4248
2e68ae44
FR		 4249 rtl_tx_performance_tweak(pdev,
4250 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 4251}
4252
4253static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4254{
4255 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 4256
f0298f81 4257 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 4258
4259 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 4260}
4261
4262static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4263{
b726e493
FR		 4264 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4265
4266 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4267
219a1e9d 4268 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 4269
4270 rtl_disable_clock_request(pdev);
4271
4272 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 4273}
4274
ef3386f0 4275static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 4276{
350f7596 4277 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 4278 { 0x01, 0, 0x0001 },
4279 { 0x02, 0x0800, 0x1000 },
4280 { 0x03, 0, 0x0042 },
4281 { 0x06, 0x0080, 0x0000 },
4282 { 0x07, 0, 0x2000 }
4283 };
4284
650e8d5d 4285 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4286
4287 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4288
219a1e9d
FR		 4289 __rtl_hw_start_8168cp(ioaddr, pdev);
4290}
4291
ef3386f0
FR		 4292static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4293{
650e8d5d 4294 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 4295
4296 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4297
4298 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4299
4300 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4301}
4302
7f3e3d3a
FR		 4303static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4304{
650e8d5d 4305 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 4306
4307 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4308
4309 /* Magic. */
4310 RTL_W8(DBG_REG, 0x20);
4311
f0298f81 4312 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 4313
4314 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4315
4316 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4317}
4318
219a1e9d
FR		 4319static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4320{
350f7596 4321 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 4322 { 0x02, 0x0800, 0x1000 },
4323 { 0x03, 0, 0x0002 },
4324 { 0x06, 0x0080, 0x0000 }
4325 };
4326
650e8d5d 4327 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4328
4329 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4330
4331 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4332
219a1e9d
FR		 4333 __rtl_hw_start_8168cp(ioaddr, pdev);
4334}
4335
4336static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4337{
350f7596 4338 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 4339 { 0x01, 0, 0x0001 },
4340 { 0x03, 0x0400, 0x0220 }
4341 };
4342
650e8d5d 4343 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 4344
4345 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4346
219a1e9d
FR		 4347 __rtl_hw_start_8168cp(ioaddr, pdev);
4348}
4349
197ff761
FR		 4350static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4351{
4352 rtl_hw_start_8168c_2(ioaddr, pdev);
4353}
4354
6fb07058
FR		 4355static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4356{
650e8d5d 4357 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4358
4359 __rtl_hw_start_8168cp(ioaddr, pdev);
4360}
4361
5b538df9
FR		 4362static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4363{
650e8d5d 4364 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4365
4366 rtl_disable_clock_request(pdev);
4367
f0298f81 4368 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4369
4370 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4371
4372 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4373}
4374
4804b3b3 4375static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4376{
4377 rtl_csi_access_enable_1(ioaddr);
4378
4379 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4380
4381 RTL_W8(MaxTxPacketSize, TxPacketMax);
4382
4383 rtl_disable_clock_request(pdev);
4384}
4385
e6de30d6 4386static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4387{
4388 static const struct ephy_info e_info_8168d_4[] = {
4389 { 0x0b, ~0, 0x48 },
4390 { 0x19, 0x20, 0x50 },
4391 { 0x0c, ~0, 0x20 }
4392 };
4393 int i;
4394
4395 rtl_csi_access_enable_1(ioaddr);
4396
4397 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4398
4399 RTL_W8(MaxTxPacketSize, TxPacketMax);
4400
4401 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4402 const struct ephy_info *e = e_info_8168d_4 + i;
4403 u16 w;
4404
4405 w = rtl_ephy_read(ioaddr, e->offset);
4406 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4407 }
4408
4409 rtl_enable_clock_request(pdev);
4410}
4411
70090424 4412static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev)
01dc7fec 4413{
70090424 4414 static const struct ephy_info e_info_8168e_1[] = {
01dc7fec 4415 { 0x00, 0x0200, 0x0100 },
4416 { 0x00, 0x0000, 0x0004 },
4417 { 0x06, 0x0002, 0x0001 },
4418 { 0x06, 0x0000, 0x0030 },
4419 { 0x07, 0x0000, 0x2000 },
4420 { 0x00, 0x0000, 0x0020 },
4421 { 0x03, 0x5800, 0x2000 },
4422 { 0x03, 0x0000, 0x0001 },
4423 { 0x01, 0x0800, 0x1000 },
4424 { 0x07, 0x0000, 0x4000 },
4425 { 0x1e, 0x0000, 0x2000 },
4426 { 0x19, 0xffff, 0xfe6c },
4427 { 0x0a, 0x0000, 0x0040 }
4428 };
4429
4430 rtl_csi_access_enable_2(ioaddr);
4431
70090424 4432 rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
01dc7fec 4433
4434 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4435
4436 RTL_W8(MaxTxPacketSize, TxPacketMax);
4437
4438 rtl_disable_clock_request(pdev);
4439
4440 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4441 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4442 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4443
cecb5fd7 4444 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4445}
4446
70090424
HW		 4447static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4448{
4449 static const struct ephy_info e_info_8168e_2[] = {
4450 { 0x09, 0x0000, 0x0080 },
4451 { 0x19, 0x0000, 0x0224 }
4452 };
4453
4454 rtl_csi_access_enable_1(ioaddr);
4455
4456 rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
4457
4458 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4459
4460 rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4461 rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
4462 rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
4463 rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
4464 rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
4465 rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
4466 rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
4467 rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00,
4468 ERIAR_EXGMAC);
4469
4470 RTL_W8(MaxTxPacketSize, 0x27);
4471
4472 rtl_disable_clock_request(pdev);
4473
4474 RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
4475 RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB);
4476
4477 /* Adjust EEE LED frequency */
4478 RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
4479
4480 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
4481 RTL_W32(MISC, RTL_R32(MISC) | PWM_EN);
4482 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4483}
4484
07ce4064
FR		 4485static void rtl_hw_start_8168(struct net_device *dev)
4486{
2dd99530
FR		 4487 struct rtl8169_private *tp = netdev_priv(dev);
4488 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4489 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4490
4491 RTL_W8(Cfg9346, Cfg9346_Unlock);
4492
f0298f81 4493 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4494
6f0333b8 4495 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4496
0e485150 4497 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4498
4499 RTL_W16(CPlusCmd, tp->cp_cmd);
4500
0e485150 4501 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4502
0e485150 4503 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4504 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4505 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4506 tp->intr_event |= RxFIFOOver | PCSTimeout;
4507 tp->intr_event &= ~RxOverflow;
4508 }
4509
4510 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4511
b8363901
FR		 4512 rtl_set_rx_mode(dev);
4513
4514 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4515 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4516
4517 RTL_R8(IntrMask);
4518
219a1e9d
FR		 4519 switch (tp->mac_version) {
4520 case RTL_GIGA_MAC_VER_11:
4521 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4522 break;
219a1e9d
FR		 4523
4524 case RTL_GIGA_MAC_VER_12:
4525 case RTL_GIGA_MAC_VER_17:
4526 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4527 break;
219a1e9d
FR		 4528
4529 case RTL_GIGA_MAC_VER_18:
ef3386f0 4530 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4531 break;
219a1e9d
FR		 4532
4533 case RTL_GIGA_MAC_VER_19:
4534 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4535 break;
219a1e9d
FR		 4536
4537 case RTL_GIGA_MAC_VER_20:
4538 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4539 break;
219a1e9d 4540
197ff761
FR		 4541 case RTL_GIGA_MAC_VER_21:
4542 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4543 break;
197ff761 4544
6fb07058
FR		 4545 case RTL_GIGA_MAC_VER_22:
4546 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4547 break;
6fb07058 4548
ef3386f0
FR		 4549 case RTL_GIGA_MAC_VER_23:
4550 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4551 break;
ef3386f0 4552
7f3e3d3a
FR		 4553 case RTL_GIGA_MAC_VER_24:
4554 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4555 break;
7f3e3d3a 4556
5b538df9 4557 case RTL_GIGA_MAC_VER_25:
daf9df6d 4558 case RTL_GIGA_MAC_VER_26:
4559 case RTL_GIGA_MAC_VER_27:
5b538df9 4560 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4561 break;
5b538df9 4562
e6de30d6 4563 case RTL_GIGA_MAC_VER_28:
4564 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4565 break;
cecb5fd7 4566
4804b3b3 4567 case RTL_GIGA_MAC_VER_31:
4568 rtl_hw_start_8168dp(ioaddr, pdev);
4569 break;
4570
01dc7fec 4571 case RTL_GIGA_MAC_VER_32:
4572 case RTL_GIGA_MAC_VER_33:
70090424
HW		 4573 rtl_hw_start_8168e_1(ioaddr, pdev);
4574 break;
4575 case RTL_GIGA_MAC_VER_34:
4576 rtl_hw_start_8168e_2(ioaddr, pdev);
01dc7fec 4577 break;
e6de30d6 4578
219a1e9d
FR		 4579 default:
4580 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4581 dev->name, tp->mac_version);
4804b3b3 4582 break;
219a1e9d 4583 }
2dd99530 4584
0e485150
FR		 4585 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4586
b8363901
FR		 4587 RTL_W8(Cfg9346, Cfg9346_Lock);
4588
2dd99530 4589 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4590
0e485150 4591 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4592}
1da177e4 4593
2857ffb7
FR		 4594#define R810X_CPCMD_QUIRK_MASK (\
4595 EnableBist | \
4596 Mac_dbgo_oe | \
4597 Force_half_dup | \
5edcc537 4598 Force_rxflow_en | \
2857ffb7
FR		 4599 Force_txflow_en | \
4600 Cxpl_dbg_sel | \
4601 ASF | \
4602 PktCntrDisable | \
d24e9aaf 4603 Mac_dbgo_sel)
2857ffb7
FR		 4604
4605static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4606{
350f7596 4607 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4608 { 0x01, 0, 0x6e65 },
4609 { 0x02, 0, 0x091f },
4610 { 0x03, 0, 0xc2f9 },
4611 { 0x06, 0, 0xafb5 },
4612 { 0x07, 0, 0x0e00 },
4613 { 0x19, 0, 0xec80 },
4614 { 0x01, 0, 0x2e65 },
4615 { 0x01, 0, 0x6e65 }
4616 };
4617 u8 cfg1;
4618
650e8d5d 4619 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4620
4621 RTL_W8(DBG_REG, FIX_NAK_1);
4622
4623 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4624
4625 RTL_W8(Config1,
4626 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4627 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4628
4629 cfg1 = RTL_R8(Config1);
4630 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4631 RTL_W8(Config1, cfg1 & ~LEDS0);
4632
2857ffb7
FR		 4633 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4634}
4635
4636static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4637{
650e8d5d 4638 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4639
4640 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4641
4642 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4643 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4644}
4645
4646static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4647{
4648 rtl_hw_start_8102e_2(ioaddr, pdev);
4649
4650 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4651}
4652
5a5e4443
HW		 4653static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4654{
4655 static const struct ephy_info e_info_8105e_1[] = {
4656 { 0x07, 0, 0x4000 },
4657 { 0x19, 0, 0x0200 },
4658 { 0x19, 0, 0x0020 },
4659 { 0x1e, 0, 0x2000 },
4660 { 0x03, 0, 0x0001 },
4661 { 0x19, 0, 0x0100 },
4662 { 0x19, 0, 0x0004 },
4663 { 0x0a, 0, 0x0020 }
4664 };
4665
cecb5fd7 4666 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 4667 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4668
cecb5fd7 4669 /* Disable Early Tally Counter */
5a5e4443
HW		 4670 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4671
4672 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4f6b00e5 4673 RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN);
5a5e4443
HW		 4674
4675 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4676}
4677
4678static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4679{
4680 rtl_hw_start_8105e_1(ioaddr, pdev);
4681 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4682}
4683
07ce4064
FR		 4684static void rtl_hw_start_8101(struct net_device *dev)
4685{
cdf1a608
FR		 4686 struct rtl8169_private *tp = netdev_priv(dev);
4687 void __iomem *ioaddr = tp->mmio_addr;
4688 struct pci_dev *pdev = tp->pci_dev;
4689
cecb5fd7
FR		 4690 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4691 tp->mac_version == RTL_GIGA_MAC_VER_16) {
e44daade 4692 int cap = pci_pcie_cap(pdev);
9c14ceaf
FR		 4693
4694 if (cap) {
4695 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4696 PCI_EXP_DEVCTL_NOSNOOP_EN);
4697 }
cdf1a608
FR		 4698 }
4699
d24e9aaf
HW		 4700 RTL_W8(Cfg9346, Cfg9346_Unlock);
4701
2857ffb7
FR		 4702 switch (tp->mac_version) {
4703 case RTL_GIGA_MAC_VER_07:
4704 rtl_hw_start_8102e_1(ioaddr, pdev);
4705 break;
4706
4707 case RTL_GIGA_MAC_VER_08:
4708 rtl_hw_start_8102e_3(ioaddr, pdev);
4709 break;
4710
4711 case RTL_GIGA_MAC_VER_09:
4712 rtl_hw_start_8102e_2(ioaddr, pdev);
4713 break;
5a5e4443
HW		 4714
4715 case RTL_GIGA_MAC_VER_29:
4716 rtl_hw_start_8105e_1(ioaddr, pdev);
4717 break;
4718 case RTL_GIGA_MAC_VER_30:
4719 rtl_hw_start_8105e_2(ioaddr, pdev);
4720 break;
cdf1a608
FR		 4721 }
4722
d24e9aaf 4723 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4724
f0298f81 4725 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4726
6f0333b8 4727 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4728
d24e9aaf 4729 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4730 RTL_W16(CPlusCmd, tp->cp_cmd);
4731
4732 RTL_W16(IntrMitigate, 0x0000);
4733
4734 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4735
4736 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4737 rtl_set_rx_tx_config_registers(tp);
4738
cdf1a608
FR		 4739 RTL_R8(IntrMask);
4740
cdf1a608
FR		 4741 rtl_set_rx_mode(dev);
4742
4743 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4744
0e485150 4745 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4746}
4747
4748static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4749{
1da177e4
LT		 4750 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4751 return -EINVAL;
4752
4753 dev->mtu = new_mtu;
350fb32a
MM		 4754 netdev_update_features(dev);
4755
323bb685 4756 return 0;
1da177e4
LT		 4757}
4758
4759static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4760{
95e0918d 4761 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4762 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4763}
4764
6f0333b8
ED		 4765static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4766 void **data_buff, struct RxDesc *desc)
1da177e4 4767{
48addcc9 4768 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4769 DMA_FROM_DEVICE);
48addcc9 4770
6f0333b8
ED		 4771 kfree(*data_buff);
4772 *data_buff = NULL;
1da177e4
LT		 4773 rtl8169_make_unusable_by_asic(desc);
4774}
4775
4776static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4777{
4778 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4779
4780 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4781}
4782
4783static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4784 u32 rx_buf_sz)
4785{
4786 desc->addr = cpu_to_le64(mapping);
4787 wmb();
4788 rtl8169_mark_to_asic(desc, rx_buf_sz);
4789}
4790
6f0333b8
ED		 4791static inline void *rtl8169_align(void *data)
4792{
4793 return (void *)ALIGN((long)data, 16);
4794}
4795
0ecbe1ca
SG		 4796static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4797 struct RxDesc *desc)
1da177e4 4798{
6f0333b8 4799 void *data;
1da177e4 4800 dma_addr_t mapping;
48addcc9 4801 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4802 struct net_device *dev = tp->dev;
6f0333b8 4803 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4804
6f0333b8
ED		 4805 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4806 if (!data)
4807 return NULL;
e9f63f30 4808
6f0333b8
ED		 4809 if (rtl8169_align(data) != data) {
4810 kfree(data);
4811 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4812 if (!data)
4813 return NULL;
4814 }
3eafe507 4815
48addcc9 4816 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4817 DMA_FROM_DEVICE);
d827d86b
SG		 4818 if (unlikely(dma_mapping_error(d, mapping))) {
4819 if (net_ratelimit())
4820 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4821 goto err_out;
d827d86b 4822 }
1da177e4
LT		 4823
4824 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4825 return data;
3eafe507
SG		 4826
4827err_out:
4828 kfree(data);
4829 return NULL;
1da177e4
LT		 4830}
4831
4832static void rtl8169_rx_clear(struct rtl8169_private *tp)
4833{
07d3f51f 4834 unsigned int i;
1da177e4
LT		 4835
4836 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4837 if (tp->Rx_databuff[i]) {
4838 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4839 tp->RxDescArray + i);
4840 }
4841 }
4842}
4843
0ecbe1ca 4844static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4845{
0ecbe1ca
SG		 4846 desc->opts1 |= cpu_to_le32(RingEnd);
4847}
5b0384f4 4848
0ecbe1ca
SG		 4849static int rtl8169_rx_fill(struct rtl8169_private *tp)
4850{
4851 unsigned int i;
1da177e4 4852
0ecbe1ca
SG		 4853 for (i = 0; i < NUM_RX_DESC; i++) {
4854 void *data;
4ae47c2d 4855
6f0333b8 4856 if (tp->Rx_databuff[i])
1da177e4 4857 continue;
bcf0bf90 4858
0ecbe1ca 4859 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4860 if (!data) {
4861 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4862 goto err_out;
6f0333b8
ED		 4863 }
4864 tp->Rx_databuff[i] = data;
1da177e4 4865 }
1da177e4 4866
0ecbe1ca
SG		 4867 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4868 return 0;
4869
4870err_out:
4871 rtl8169_rx_clear(tp);
4872 return -ENOMEM;
1da177e4
LT		 4873}
4874
1da177e4
LT		 4875static int rtl8169_init_ring(struct net_device *dev)
4876{
4877 struct rtl8169_private *tp = netdev_priv(dev);
4878
4879 rtl8169_init_ring_indexes(tp);
4880
4881 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4882 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4883
0ecbe1ca 4884 return rtl8169_rx_fill(tp);
1da177e4
LT		 4885}
4886
48addcc9 4887static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4888 struct TxDesc *desc)
4889{
4890 unsigned int len = tx_skb->len;
4891
48addcc9
SG		 4892 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4893
1da177e4
LT		 4894 desc->opts1 = 0x00;
4895 desc->opts2 = 0x00;
4896 desc->addr = 0x00;
4897 tx_skb->len = 0;
4898}
4899
3eafe507
SG		 4900static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4901 unsigned int n)
1da177e4
LT		 4902{
4903 unsigned int i;
4904
3eafe507
SG		 4905 for (i = 0; i < n; i++) {
4906 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4907 struct ring_info *tx_skb = tp->tx_skb + entry;
4908 unsigned int len = tx_skb->len;
4909
4910 if (len) {
4911 struct sk_buff *skb = tx_skb->skb;
4912
48addcc9 4913 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4914 tp->TxDescArray + entry);
4915 if (skb) {
cac4b22f 4916 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4917 dev_kfree_skb(skb);
4918 tx_skb->skb = NULL;
4919 }
1da177e4
LT		 4920 }
4921 }
3eafe507
SG		 4922}
4923
4924static void rtl8169_tx_clear(struct rtl8169_private *tp)
4925{
4926 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4927 tp->cur_tx = tp->dirty_tx = 0;
4928}
4929
c4028958 4930static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4931{
4932 struct rtl8169_private *tp = netdev_priv(dev);
4933
c4028958 4934 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4935 schedule_delayed_work(&tp->task, 4);
4936}
4937
4938static void rtl8169_wait_for_quiescence(struct net_device *dev)
4939{
4940 struct rtl8169_private *tp = netdev_priv(dev);
4941 void __iomem *ioaddr = tp->mmio_addr;
4942
4943 synchronize_irq(dev->irq);
4944
4945 /* Wait for any pending NAPI task to complete */
bea3348e 4946 napi_disable(&tp->napi);
1da177e4
LT		 4947
4948 rtl8169_irq_mask_and_ack(ioaddr);
4949
d1d08d12
DM		 4950 tp->intr_mask = 0xffff;
4951 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4952 napi_enable(&tp->napi);
1da177e4
LT		 4953}
4954
c4028958 4955static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4956{
c4028958
DH		 4957 struct rtl8169_private *tp =
4958 container_of(work, struct rtl8169_private, task.work);
4959 struct net_device *dev = tp->dev;
1da177e4
LT		 4960 int ret;
4961
eb2a021c
FR		 4962 rtnl_lock();
4963
4964 if (!netif_running(dev))
4965 goto out_unlock;
4966
4967 rtl8169_wait_for_quiescence(dev);
4968 rtl8169_close(dev);
1da177e4
LT		 4969
4970 ret = rtl8169_open(dev);
4971 if (unlikely(ret < 0)) {
bf82c189
JP		 4972 if (net_ratelimit())
4973 netif_err(tp, drv, dev,
4974 "reinit failure (status = %d). Rescheduling\n",
4975 ret);
1da177e4
LT		 4976 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4977 }
eb2a021c
FR		 4978
4979out_unlock:
4980 rtnl_unlock();
1da177e4
LT		 4981}
4982
c4028958 4983static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4984{
c4028958
DH		 4985 struct rtl8169_private *tp =
4986 container_of(work, struct rtl8169_private, task.work);
4987 struct net_device *dev = tp->dev;
56de414c 4988 int i;
1da177e4 4989
eb2a021c
FR		 4990 rtnl_lock();
4991
1da177e4 4992 if (!netif_running(dev))
eb2a021c 4993 goto out_unlock;
1da177e4
LT		 4994
4995 rtl8169_wait_for_quiescence(dev);
4996
56de414c
FR		 4997 for (i = 0; i < NUM_RX_DESC; i++)
4998 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4999
1da177e4
LT		 5000 rtl8169_tx_clear(tp);
5001
92fc43b4 5002 rtl8169_hw_reset(tp);
56de414c
FR		 5003 rtl_hw_start(dev);
5004 netif_wake_queue(dev);
5005 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 5006
5007out_unlock:
5008 rtnl_unlock();
1da177e4
LT		 5009}
5010
5011static void rtl8169_tx_timeout(struct net_device *dev)
5012{
5013 struct rtl8169_private *tp = netdev_priv(dev);
5014
e6de30d6 5015 rtl8169_hw_reset(tp);
1da177e4
LT		 5016
5017 /* Let's wait a bit while any (async) irq lands on */
5018 rtl8169_schedule_work(dev, rtl8169_reset_task);
5019}
5020
5021static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 5022 u32 *opts)
1da177e4
LT		 5023{
5024 struct skb_shared_info *info = skb_shinfo(skb);
5025 unsigned int cur_frag, entry;
a6343afb 5026 struct TxDesc * uninitialized_var(txd);
48addcc9 5027 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5028
5029 entry = tp->cur_tx;
5030 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
5031 skb_frag_t *frag = info->frags + cur_frag;
5032 dma_addr_t mapping;
5033 u32 status, len;
5034 void *addr;
5035
5036 entry = (entry + 1) % NUM_TX_DESC;
5037
5038 txd = tp->TxDescArray + entry;
5039 len = frag->size;
5040 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 5041 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 5042 if (unlikely(dma_mapping_error(d, mapping))) {
5043 if (net_ratelimit())
5044 netif_err(tp, drv, tp->dev,
5045 "Failed to map TX fragments DMA!\n");
3eafe507 5046 goto err_out;
d827d86b 5047 }
1da177e4 5048
cecb5fd7 5049 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 5050 status = opts[0] | len |
5051 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5052
5053 txd->opts1 = cpu_to_le32(status);
2b7b4318 5054 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 5055 txd->addr = cpu_to_le64(mapping);
5056
5057 tp->tx_skb[entry].len = len;
5058 }
5059
5060 if (cur_frag) {
5061 tp->tx_skb[entry].skb = skb;
5062 txd->opts1 |= cpu_to_le32(LastFrag);
5063 }
5064
5065 return cur_frag;
3eafe507
SG		 5066
5067err_out:
5068 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
5069 return -EIO;
1da177e4
LT		 5070}
5071
2b7b4318
FR		 5072static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
5073 struct sk_buff *skb, u32 *opts)
1da177e4 5074{
2b7b4318 5075 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 5076 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 5077 int offset = info->opts_offset;
350fb32a 5078
2b7b4318
FR		 5079 if (mss) {
5080 opts[0] |= TD_LSO;
5081 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
5082 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 5083 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 5084
5085 if (ip->protocol == IPPROTO_TCP)
2b7b4318 5086 opts[offset] |= info->checksum.tcp;
1da177e4 5087 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 5088 opts[offset] |= info->checksum.udp;
5089 else
5090 WARN_ON_ONCE(1);
1da177e4 5091 }
1da177e4
LT		 5092}
5093
61357325
SH		 5094static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
5095 struct net_device *dev)
1da177e4
LT		 5096{
5097 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 5098 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 5099 struct TxDesc *txd = tp->TxDescArray + entry;
5100 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 5101 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 5102 dma_addr_t mapping;
5103 u32 status, len;
2b7b4318 5104 u32 opts[2];
3eafe507 5105 int frags;
5b0384f4 5106
1da177e4 5107 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 5108 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 5109 goto err_stop_0;
1da177e4
LT		 5110 }
5111
5112 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 5113 goto err_stop_0;
5114
5115 len = skb_headlen(skb);
48addcc9 5116 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 5117 if (unlikely(dma_mapping_error(d, mapping))) {
5118 if (net_ratelimit())
5119 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 5120 goto err_dma_0;
d827d86b 5121 }
3eafe507
SG		 5122
5123 tp->tx_skb[entry].len = len;
5124 txd->addr = cpu_to_le64(mapping);
1da177e4 5125
2b7b4318
FR		 5126 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
5127 opts[0] = DescOwn;
1da177e4 5128
2b7b4318
FR		 5129 rtl8169_tso_csum(tp, skb, opts);
5130
5131 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 5132 if (frags < 0)
5133 goto err_dma_1;
5134 else if (frags)
2b7b4318 5135 opts[0] |= FirstFrag;
3eafe507 5136 else {
2b7b4318 5137 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 5138 tp->tx_skb[entry].skb = skb;
5139 }
5140
2b7b4318
FR		 5141 txd->opts2 = cpu_to_le32(opts[1]);
5142
1da177e4
LT		 5143 wmb();
5144
cecb5fd7 5145 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 5146 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 5147 txd->opts1 = cpu_to_le32(status);
5148
1da177e4
LT		 5149 tp->cur_tx += frags + 1;
5150
4c020a96 5151 wmb();
1da177e4 5152
cecb5fd7 5153 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5154
5155 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
5156 netif_stop_queue(dev);
5157 smp_rmb();
5158 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
5159 netif_wake_queue(dev);
5160 }
5161
61357325 5162 return NETDEV_TX_OK;
1da177e4 5163
3eafe507 5164err_dma_1:
48addcc9 5165 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 5166err_dma_0:
5167 dev_kfree_skb(skb);
5168 dev->stats.tx_dropped++;
5169 return NETDEV_TX_OK;
5170
5171err_stop_0:
1da177e4 5172 netif_stop_queue(dev);
cebf8cc7 5173 dev->stats.tx_dropped++;
61357325 5174 return NETDEV_TX_BUSY;
1da177e4
LT		 5175}
5176
5177static void rtl8169_pcierr_interrupt(struct net_device *dev)
5178{
5179 struct rtl8169_private *tp = netdev_priv(dev);
5180 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 5181 u16 pci_status, pci_cmd;
5182
5183 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
5184 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
5185
bf82c189
JP		 5186 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
5187 pci_cmd, pci_status);
1da177e4
LT		 5188
5189 /*
5190 * The recovery sequence below admits a very elaborated explanation:
5191 * - it seems to work;
d03902b8
FR		 5192 * - I did not see what else could be done;
5193 * - it makes iop3xx happy.
1da177e4
LT		 5194 *
5195 * Feel free to adjust to your needs.
5196 */
a27993f3 5197 if (pdev->broken_parity_status)
d03902b8
FR		 5198 pci_cmd &= ~PCI_COMMAND_PARITY;
5199 else
5200 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
5201
5202 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 5203
5204 pci_write_config_word(pdev, PCI_STATUS,
5205 pci_status & (PCI_STATUS_DETECTED_PARITY |
5206 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
5207 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
5208
5209 /* The infamous DAC f*ckup only happens at boot time */
5210 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 5211 void __iomem *ioaddr = tp->mmio_addr;
5212
bf82c189 5213 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 5214 tp->cp_cmd &= ~PCIDAC;
5215 RTL_W16(CPlusCmd, tp->cp_cmd);
5216 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 5217 }
5218
e6de30d6 5219 rtl8169_hw_reset(tp);
d03902b8
FR		 5220
5221 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 5222}
5223
07d3f51f
FR		 5224static void rtl8169_tx_interrupt(struct net_device *dev,
5225 struct rtl8169_private *tp,
5226 void __iomem *ioaddr)
1da177e4
LT		 5227{
5228 unsigned int dirty_tx, tx_left;
5229
1da177e4
LT		 5230 dirty_tx = tp->dirty_tx;
5231 smp_rmb();
5232 tx_left = tp->cur_tx - dirty_tx;
5233
5234 while (tx_left > 0) {
5235 unsigned int entry = dirty_tx % NUM_TX_DESC;
5236 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 5237 u32 status;
5238
5239 rmb();
5240 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
5241 if (status & DescOwn)
5242 break;
5243
48addcc9
SG		 5244 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
5245 tp->TxDescArray + entry);
1da177e4 5246 if (status & LastFrag) {
cac4b22f
SG		 5247 dev->stats.tx_packets++;
5248 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 5249 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 5250 tx_skb->skb = NULL;
5251 }
5252 dirty_tx++;
5253 tx_left--;
5254 }
5255
5256 if (tp->dirty_tx != dirty_tx) {
5257 tp->dirty_tx = dirty_tx;
5258 smp_wmb();
5259 if (netif_queue_stopped(dev) &&
5260 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
5261 netif_wake_queue(dev);
5262 }
d78ae2dc
FR		 5263 /*
5264 * 8168 hack: TxPoll requests are lost when the Tx packets are
5265 * too close. Let's kick an extra TxPoll request when a burst
5266 * of start_xmit activity is detected (if it is not detected,
5267 * it is slow enough). -- FR
5268 */
5269 smp_rmb();
5270 if (tp->cur_tx != dirty_tx)
5271 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 5272 }
5273}
5274
126fa4b9
FR		 5275static inline int rtl8169_fragmented_frame(u32 status)
5276{
5277 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
5278}
5279
adea1ac7 5280static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 5281{
1da177e4
LT		 5282 u32 status = opts1 & RxProtoMask;
5283
5284 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 5285 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 5286 skb->ip_summed = CHECKSUM_UNNECESSARY;
5287 else
bc8acf2c 5288 skb_checksum_none_assert(skb);
1da177e4
LT		 5289}
5290
6f0333b8
ED		 5291static struct sk_buff *rtl8169_try_rx_copy(void *data,
5292 struct rtl8169_private *tp,
5293 int pkt_size,
5294 dma_addr_t addr)
1da177e4 5295{
b449655f 5296 struct sk_buff *skb;
48addcc9 5297 struct device *d = &tp->pci_dev->dev;
b449655f 5298
6f0333b8 5299 data = rtl8169_align(data);
48addcc9 5300 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 5301 prefetch(data);
5302 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5303 if (skb)
5304 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 5305 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5306
6f0333b8 5307 return skb;
1da177e4
LT		 5308}
5309
07d3f51f
FR		 5310static int rtl8169_rx_interrupt(struct net_device *dev,
5311 struct rtl8169_private *tp,
bea3348e 5312 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 5313{
5314 unsigned int cur_rx, rx_left;
6f0333b8 5315 unsigned int count;
1da177e4 5316
1da177e4
LT		 5317 cur_rx = tp->cur_rx;
5318 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 5319 rx_left = min(rx_left, budget);
1da177e4 5320
4dcb7d33 5321 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 5322 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 5323 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 5324 u32 status;
5325
5326 rmb();
126fa4b9 5327 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 5328
5329 if (status & DescOwn)
5330 break;
4dcb7d33 5331 if (unlikely(status & RxRES)) {
bf82c189
JP		 5332 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5333 status);
cebf8cc7 5334 dev->stats.rx_errors++;
1da177e4 5335 if (status & (RxRWT | RxRUNT))
cebf8cc7 5336 dev->stats.rx_length_errors++;
1da177e4 5337 if (status & RxCRC)
cebf8cc7 5338 dev->stats.rx_crc_errors++;
9dccf611
FR		 5339 if (status & RxFOVF) {
5340 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 5341 dev->stats.rx_fifo_errors++;
9dccf611 5342 }
6f0333b8 5343 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 5344 } else {
6f0333b8 5345 struct sk_buff *skb;
b449655f 5346 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 5347 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 5348
126fa4b9
FR		 5349 /*
5350 * The driver does not support incoming fragmented
5351 * frames. They are seen as a symptom of over-mtu
5352 * sized frames.
5353 */
5354 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 5355 dev->stats.rx_dropped++;
5356 dev->stats.rx_length_errors++;
6f0333b8 5357 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 5358 continue;
126fa4b9
FR		 5359 }
5360
6f0333b8
ED		 5361 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5362 tp, pkt_size, addr);
5363 rtl8169_mark_to_asic(desc, rx_buf_sz);
5364 if (!skb) {
5365 dev->stats.rx_dropped++;
5366 continue;
1da177e4
LT		 5367 }
5368
adea1ac7 5369 rtl8169_rx_csum(skb, status);
1da177e4
LT		 5370 skb_put(skb, pkt_size);
5371 skb->protocol = eth_type_trans(skb, dev);
5372
7a8fc77b
FR		 5373 rtl8169_rx_vlan_tag(desc, skb);
5374
56de414c 5375 napi_gro_receive(&tp->napi, skb);
1da177e4 5376
cebf8cc7
FR		 5377 dev->stats.rx_bytes += pkt_size;
5378 dev->stats.rx_packets++;
1da177e4 5379 }
6dccd16b
FR		 5380
5381 /* Work around for AMD plateform. */
95e0918d 5382 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 5383 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5384 desc->opts2 = 0;
5385 cur_rx++;
5386 }
1da177e4
LT		 5387 }
5388
5389 count = cur_rx - tp->cur_rx;
5390 tp->cur_rx = cur_rx;
5391
6f0333b8 5392 tp->dirty_rx += count;
1da177e4
LT		 5393
5394 return count;
5395}
5396
07d3f51f 5397static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5398{
07d3f51f 5399 struct net_device *dev = dev_instance;
1da177e4 5400 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5401 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5402 int handled = 0;
865c652d 5403 int status;
1da177e4 5404
f11a377b
DD		 5405 /* loop handling interrupts until we have no new ones or
5406 * we hit a invalid/hotplug case.
5407 */
865c652d 5408 status = RTL_R16(IntrStatus);
f11a377b
DD		 5409 while (status && status != 0xffff) {
5410 handled = 1;
1da177e4 5411
f11a377b
DD		 5412 /* Handle all of the error cases first. These will reset
5413 * the chip, so just exit the loop.
5414 */
5415 if (unlikely(!netif_running(dev))) {
92fc43b4 5416 rtl8169_hw_reset(tp);
f11a377b
DD		 5417 break;
5418 }
1da177e4 5419
1519e57f
FR		 5420 if (unlikely(status & RxFIFOOver)) {
5421 switch (tp->mac_version) {
5422 /* Work around for rx fifo overflow */
5423 case RTL_GIGA_MAC_VER_11:
5424 case RTL_GIGA_MAC_VER_22:
5425 case RTL_GIGA_MAC_VER_26:
5426 netif_stop_queue(dev);
5427 rtl8169_tx_timeout(dev);
5428 goto done;
f60ac8e7
FR		 5429 /* Testers needed. */
5430 case RTL_GIGA_MAC_VER_17:
5431 case RTL_GIGA_MAC_VER_19:
5432 case RTL_GIGA_MAC_VER_20:
5433 case RTL_GIGA_MAC_VER_21:
5434 case RTL_GIGA_MAC_VER_23:
5435 case RTL_GIGA_MAC_VER_24:
5436 case RTL_GIGA_MAC_VER_27:
5437 case RTL_GIGA_MAC_VER_28:
4804b3b3 5438 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5439 /* Experimental science. Pktgen proof. */
5440 case RTL_GIGA_MAC_VER_12:
5441 case RTL_GIGA_MAC_VER_25:
5442 if (status == RxFIFOOver)
5443 goto done;
5444 break;
5445 default:
5446 break;
5447 }
f11a377b 5448 }
1da177e4 5449
f11a377b
DD		 5450 if (unlikely(status & SYSErr)) {
5451 rtl8169_pcierr_interrupt(dev);
5452 break;
5453 }
1da177e4 5454
f11a377b 5455 if (status & LinkChg)
e4fbce74 5456 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5457
f11a377b
DD		 5458 /* We need to see the lastest version of tp->intr_mask to
5459 * avoid ignoring an MSI interrupt and having to wait for
5460 * another event which may never come.
5461 */
5462 smp_rmb();
5463 if (status & tp->intr_mask & tp->napi_event) {
5464 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5465 tp->intr_mask = ~tp->napi_event;
5466
5467 if (likely(napi_schedule_prep(&tp->napi)))
5468 __napi_schedule(&tp->napi);
bf82c189
JP		 5469 else
5470 netif_info(tp, intr, dev,
5471 "interrupt %04x in poll\n", status);
f11a377b 5472 }
1da177e4 5473
f11a377b
DD		 5474 /* We only get a new MSI interrupt when all active irq
5475 * sources on the chip have been acknowledged. So, ack
5476 * everything we've seen and check if new sources have become
5477 * active to avoid blocking all interrupts from the chip.
5478 */
5479 RTL_W16(IntrStatus,
5480 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5481 status = RTL_R16(IntrStatus);
865c652d 5482 }
1519e57f 5483done:
1da177e4
LT		 5484 return IRQ_RETVAL(handled);
5485}
5486
bea3348e 5487static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5488{
bea3348e
SH		 5489 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5490 struct net_device *dev = tp->dev;
1da177e4 5491 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5492 int work_done;
1da177e4 5493
bea3348e 5494 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5495 rtl8169_tx_interrupt(dev, tp, ioaddr);
5496
bea3348e 5497 if (work_done < budget) {
288379f0 5498 napi_complete(napi);
f11a377b
DD		 5499
5500 /* We need for force the visibility of tp->intr_mask
5501 * for other CPUs, as we can loose an MSI interrupt
5502 * and potentially wait for a retransmit timeout if we don't.
5503 * The posted write to IntrMask is safe, as it will
5504 * eventually make it to the chip and we won't loose anything
5505 * until it does.
1da177e4 5506 */
f11a377b 5507 tp->intr_mask = 0xffff;
4c020a96 5508 wmb();
0e485150 5509 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5510 }
5511
bea3348e 5512 return work_done;
1da177e4 5513}
1da177e4 5514
523a6094
FR		 5515static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5516{
5517 struct rtl8169_private *tp = netdev_priv(dev);
5518
5519 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5520 return;
5521
5522 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5523 RTL_W32(RxMissed, 0);
5524}
5525
1da177e4
LT		 5526static void rtl8169_down(struct net_device *dev)
5527{
5528 struct rtl8169_private *tp = netdev_priv(dev);
5529 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5530
4876cc1e 5531 del_timer_sync(&tp->timer);
1da177e4
LT		 5532
5533 netif_stop_queue(dev);
5534
93dd79e8 5535 napi_disable(&tp->napi);
93dd79e8 5536
1da177e4
LT		 5537 spin_lock_irq(&tp->lock);
5538
92fc43b4 5539 rtl8169_hw_reset(tp);
323bb685
SG		 5540 /*
5541 * At this point device interrupts can not be enabled in any function,
5542 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5543 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5544 */
523a6094 5545 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5546
5547 spin_unlock_irq(&tp->lock);
5548
5549 synchronize_irq(dev->irq);
5550
1da177e4 5551 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5552 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5553
1da177e4
LT		 5554 rtl8169_tx_clear(tp);
5555
5556 rtl8169_rx_clear(tp);
065c27c1 5557
5558 rtl_pll_power_down(tp);
1da177e4
LT		 5559}
5560
5561static int rtl8169_close(struct net_device *dev)
5562{
5563 struct rtl8169_private *tp = netdev_priv(dev);
5564 struct pci_dev *pdev = tp->pci_dev;
5565
e1759441
RW		 5566 pm_runtime_get_sync(&pdev->dev);
5567
cecb5fd7 5568 /* Update counters before going down */
355423d0
IV		 5569 rtl8169_update_counters(dev);
5570
1da177e4
LT		 5571 rtl8169_down(dev);
5572
5573 free_irq(dev->irq, dev);
5574
82553bb6
SG		 5575 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5576 tp->RxPhyAddr);
5577 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5578 tp->TxPhyAddr);
1da177e4
LT		 5579 tp->TxDescArray = NULL;
5580 tp->RxDescArray = NULL;
5581
e1759441
RW		 5582 pm_runtime_put_sync(&pdev->dev);
5583
1da177e4
LT		 5584 return 0;
5585}
5586
07ce4064 5587static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5588{
5589 struct rtl8169_private *tp = netdev_priv(dev);
5590 void __iomem *ioaddr = tp->mmio_addr;
5591 unsigned long flags;
5592 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5593 int rx_mode;
1da177e4
LT		 5594 u32 tmp = 0;
5595
5596 if (dev->flags & IFF_PROMISC) {
5597 /* Unconditionally log net taps. */
bf82c189 5598 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5599 rx_mode =
5600 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5601 AcceptAllPhys;
5602 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5603 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5604 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5605 /* Too many to filter perfectly -- accept all multicasts. */
5606 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5607 mc_filter[1] = mc_filter[0] = 0xffffffff;
5608 } else {
22bedad3 5609 struct netdev_hw_addr *ha;
07d3f51f 5610
1da177e4
LT		 5611 rx_mode = AcceptBroadcast | AcceptMyPhys;
5612 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5613 netdev_for_each_mc_addr(ha, dev) {
5614 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5615 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5616 rx_mode |= AcceptMulticast;
5617 }
5618 }
5619
5620 spin_lock_irqsave(&tp->lock, flags);
5621
1687b566 5622 tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
1da177e4 5623
f887cce8 5624 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5625 u32 data = mc_filter[0];
5626
5627 mc_filter[0] = swab32(mc_filter[1]);
5628 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5629 }
5630
1da177e4 5631 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5632 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5633
57a9f236
FR		 5634 RTL_W32(RxConfig, tmp);
5635
1da177e4
LT		 5636 spin_unlock_irqrestore(&tp->lock, flags);
5637}
5638
5639/**
5640 * rtl8169_get_stats - Get rtl8169 read/write statistics
5641 * @dev: The Ethernet Device to get statistics for
5642 *
5643 * Get TX/RX statistics for rtl8169
5644 */
5645static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5646{
5647 struct rtl8169_private *tp = netdev_priv(dev);
5648 void __iomem *ioaddr = tp->mmio_addr;
5649 unsigned long flags;
5650
5651 if (netif_running(dev)) {
5652 spin_lock_irqsave(&tp->lock, flags);
523a6094 5653 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5654 spin_unlock_irqrestore(&tp->lock, flags);
5655 }
5b0384f4 5656
cebf8cc7 5657 return &dev->stats;
1da177e4
LT		 5658}
5659
861ab440 5660static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5661{
065c27c1 5662 struct rtl8169_private *tp = netdev_priv(dev);
5663
5d06a99f 5664 if (!netif_running(dev))
861ab440 5665 return;
5d06a99f 5666
065c27c1 5667 rtl_pll_power_down(tp);
5668
5d06a99f
FR		 5669 netif_device_detach(dev);
5670 netif_stop_queue(dev);
861ab440
RW		 5671}
5672
5673#ifdef CONFIG_PM
5674
5675static int rtl8169_suspend(struct device *device)
5676{
5677 struct pci_dev *pdev = to_pci_dev(device);
5678 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5679
861ab440 5680 rtl8169_net_suspend(dev);
1371fa6d 5681
5d06a99f
FR		 5682 return 0;
5683}
5684
e1759441
RW		 5685static void __rtl8169_resume(struct net_device *dev)
5686{
065c27c1 5687 struct rtl8169_private *tp = netdev_priv(dev);
5688
e1759441 5689 netif_device_attach(dev);
065c27c1 5690
5691 rtl_pll_power_up(tp);
5692
e1759441
RW		 5693 rtl8169_schedule_work(dev, rtl8169_reset_task);
5694}
5695
861ab440 5696static int rtl8169_resume(struct device *device)
5d06a99f 5697{
861ab440 5698 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5699 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5700 struct rtl8169_private *tp = netdev_priv(dev);
5701
5702 rtl8169_init_phy(dev, tp);
5d06a99f 5703
e1759441
RW		 5704 if (netif_running(dev))
5705 __rtl8169_resume(dev);
5d06a99f 5706
e1759441
RW		 5707 return 0;
5708}
5709
5710static int rtl8169_runtime_suspend(struct device *device)
5711{
5712 struct pci_dev *pdev = to_pci_dev(device);
5713 struct net_device *dev = pci_get_drvdata(pdev);
5714 struct rtl8169_private *tp = netdev_priv(dev);
5715
5716 if (!tp->TxDescArray)
5717 return 0;
5718
5719 spin_lock_irq(&tp->lock);
5720 tp->saved_wolopts = __rtl8169_get_wol(tp);
5721 __rtl8169_set_wol(tp, WAKE_ANY);
5722 spin_unlock_irq(&tp->lock);
5723
5724 rtl8169_net_suspend(dev);
5725
5726 return 0;
5727}
5728
5729static int rtl8169_runtime_resume(struct device *device)
5730{
5731 struct pci_dev *pdev = to_pci_dev(device);
5732 struct net_device *dev = pci_get_drvdata(pdev);
5733 struct rtl8169_private *tp = netdev_priv(dev);
5734
5735 if (!tp->TxDescArray)
5736 return 0;
5737
5738 spin_lock_irq(&tp->lock);
5739 __rtl8169_set_wol(tp, tp->saved_wolopts);
5740 tp->saved_wolopts = 0;
5741 spin_unlock_irq(&tp->lock);
5742
fccec10b
SG		 5743 rtl8169_init_phy(dev, tp);
5744
e1759441 5745 __rtl8169_resume(dev);
5d06a99f 5746
5d06a99f
FR		 5747 return 0;
5748}
5749
e1759441
RW		 5750static int rtl8169_runtime_idle(struct device *device)
5751{
5752 struct pci_dev *pdev = to_pci_dev(device);
5753 struct net_device *dev = pci_get_drvdata(pdev);
5754 struct rtl8169_private *tp = netdev_priv(dev);
5755
e4fbce74 5756 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5757}
5758
47145210 5759static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 5760 .suspend = rtl8169_suspend,
5761 .resume = rtl8169_resume,
5762 .freeze = rtl8169_suspend,
5763 .thaw = rtl8169_resume,
5764 .poweroff = rtl8169_suspend,
5765 .restore = rtl8169_resume,
5766 .runtime_suspend = rtl8169_runtime_suspend,
5767 .runtime_resume = rtl8169_runtime_resume,
5768 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5769};
5770
5771#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5772
5773#else /* !CONFIG_PM */
5774
5775#define RTL8169_PM_OPS NULL
5776
5777#endif /* !CONFIG_PM */
5778
1765f95d
FR		 5779static void rtl_shutdown(struct pci_dev *pdev)
5780{
861ab440 5781 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5782 struct rtl8169_private *tp = netdev_priv(dev);
5783 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5784
5785 rtl8169_net_suspend(dev);
1765f95d 5786
cecb5fd7 5787 /* Restore original MAC address */
cc098dc7
IV		 5788 rtl_rar_set(tp, dev->perm_addr);
5789
4bb3f522 5790 spin_lock_irq(&tp->lock);
5791
92fc43b4 5792 rtl8169_hw_reset(tp);
4bb3f522 5793
5794 spin_unlock_irq(&tp->lock);
5795
861ab440 5796 if (system_state == SYSTEM_POWER_OFF) {
aaa89c08
HW		 5797 /* WoL fails with 8168b when the receiver is disabled. */
5798 if ((tp->mac_version == RTL_GIGA_MAC_VER_11 ||
5799 tp->mac_version == RTL_GIGA_MAC_VER_12 ||
5800 tp->mac_version == RTL_GIGA_MAC_VER_17) &&
5801 (tp->features & RTL_FEATURE_WOL)) {
ca52efd5 5802 pci_clear_master(pdev);
5803
5804 RTL_W8(ChipCmd, CmdRxEnb);
5805 /* PCI commit */
5806 RTL_R8(ChipCmd);
5807 }
5808
861ab440
RW		 5809 pci_wake_from_d3(pdev, true);
5810 pci_set_power_state(pdev, PCI_D3hot);
5811 }
5812}
5d06a99f 5813
1da177e4
LT		 5814static struct pci_driver rtl8169_pci_driver = {
5815 .name = MODULENAME,
5816 .id_table = rtl8169_pci_tbl,
5817 .probe = rtl8169_init_one,
5818 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5819 .shutdown = rtl_shutdown,
861ab440 5820 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5821};
5822
07d3f51f 5823static int __init rtl8169_init_module(void)
1da177e4 5824{
29917620 5825 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5826}
5827
07d3f51f 5828static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5829{
5830 pci_unregister_driver(&rtl8169_pci_driver);
5831}
5832
5833module_init(rtl8169_init_module);
5834module_exit(rtl8169_cleanup_module);
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