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net/r8169: add a new chip for RTL8105
[mirror_ubuntu-eoan-kernel.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
1da177e4 29
99f252b0 30#include <asm/system.h>
1da177e4
LT		 31#include <asm/io.h>
32#include <asm/irq.h>
33
865c652d 34#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 35#define MODULENAME "r8169"
36#define PFX MODULENAME ": "
37
bca03d5f 38#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
39#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
5a5e4443 40#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 41
1da177e4
LT		 42#ifdef RTL8169_DEBUG
43#define assert(expr) \
5b0384f4
FR		 44 if (!(expr)) { \
45 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 46 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 47 }
06fa7358
JP		 48#define dprintk(fmt, args...) \
49 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 50#else
51#define assert(expr) do {} while (0)
52#define dprintk(fmt, args...) do {} while (0)
53#endif /* RTL8169_DEBUG */
54
b57b7e5a 55#define R8169_MSG_DEFAULT \
f0e837d9 56 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 57
1da177e4
LT		 58#define TX_BUFFS_AVAIL(tp) \
59 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
60
1da177e4
LT		 61/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
62 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 63static const int multicast_filter_limit = 32;
1da177e4
LT		 64
65/* MAC address length */
66#define MAC_ADDR_LEN 6
67
9c14ceaf 68#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 69#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
70#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
71#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 72#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
73#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
74
75#define R8169_REGS_SIZE 256
76#define R8169_NAPI_WEIGHT 64
77#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
78#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
79#define RX_BUF_SIZE 1536 /* Rx Buffer size */
80#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
81#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
82
83#define RTL8169_TX_TIMEOUT (6*HZ)
84#define RTL8169_PHY_TIMEOUT (10*HZ)
85
ea8dbdd1 86#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
87#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 88#define RTL_EEPROM_SIG_ADDR 0x0000
89
1da177e4
LT		 90/* write/read MMIO register */
91#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
92#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
93#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
94#define RTL_R8(reg) readb (ioaddr + (reg))
95#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 96#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 97
98enum mac_version {
f21b75e9 99 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 100 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
101 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
102 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
103 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
104 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 105 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 106 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
107 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
108 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
109 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 110 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 111 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
112 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
113 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
114 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
115 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
116 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
117 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
118 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 119 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 120 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 121 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 122 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 123 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 124 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
125 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
e6de30d6 126 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
127 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
5a5e4443
HW		 128 RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E
129 RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E
1da177e4
LT		 130};
131
1da177e4
LT		 132#define _R(NAME,MAC,MASK) \
133 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
134
3c6bee1d 135static const struct {
1da177e4
LT		 136 const char *name;
137 u8 mac_version;
138 u32 RxConfigMask; /* Clears the bits supported by this chip */
139} rtl_chip_info[] = {
ba6eb6ee
FR		 140 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
141 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
142 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
143 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
144 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 145 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 146 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
147 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
148 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
149 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 150 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
153 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 154 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
155 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
156 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
157 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
158 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 159 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 160 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 161 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 162 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 163 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 164 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
165 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
e6de30d6 166 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
5a5e4443
HW		 167 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E
168 _R("RTL8105e", RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E
169 _R("RTL8105e", RTL_GIGA_MAC_VER_30, 0xff7e1880) // PCI-E
1da177e4
LT		 170};
171#undef _R
172
bcf0bf90
FR		 173enum cfg_version {
174 RTL_CFG_0 = 0x00,
175 RTL_CFG_1,
176 RTL_CFG_2
177};
178
07ce4064
FR		 179static void rtl_hw_start_8169(struct net_device *);
180static void rtl_hw_start_8168(struct net_device *);
181static void rtl_hw_start_8101(struct net_device *);
182
a3aa1884 183static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 184 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 185 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 186 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 187 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 188 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
189 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 190 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 191 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
192 { PCI_VENDOR_ID_LINKSYS, 0x1032,
193 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 194 { 0x0001, 0x8168,
195 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 196 {0,},
197};
198
199MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
200
6f0333b8 201static int rx_buf_sz = 16383;
4300e8c7 202static int use_dac;
b57b7e5a
SH		 203static struct {
204 u32 msg_enable;
205} debug = { -1 };
1da177e4 206
07d3f51f
FR		 207enum rtl_registers {
208 MAC0 = 0, /* Ethernet hardware address. */
773d2021 209 MAC4 = 4,
07d3f51f
FR		 210 MAR0 = 8, /* Multicast filter. */
211 CounterAddrLow = 0x10,
212 CounterAddrHigh = 0x14,
213 TxDescStartAddrLow = 0x20,
214 TxDescStartAddrHigh = 0x24,
215 TxHDescStartAddrLow = 0x28,
216 TxHDescStartAddrHigh = 0x2c,
217 FLASH = 0x30,
218 ERSR = 0x36,
219 ChipCmd = 0x37,
220 TxPoll = 0x38,
221 IntrMask = 0x3c,
222 IntrStatus = 0x3e,
223 TxConfig = 0x40,
224 RxConfig = 0x44,
225 RxMissed = 0x4c,
226 Cfg9346 = 0x50,
227 Config0 = 0x51,
228 Config1 = 0x52,
229 Config2 = 0x53,
230 Config3 = 0x54,
231 Config4 = 0x55,
232 Config5 = 0x56,
233 MultiIntr = 0x5c,
234 PHYAR = 0x60,
07d3f51f
FR		 235 PHYstatus = 0x6c,
236 RxMaxSize = 0xda,
237 CPlusCmd = 0xe0,
238 IntrMitigate = 0xe2,
239 RxDescAddrLow = 0xe4,
240 RxDescAddrHigh = 0xe8,
f0298f81 241 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
242
243#define NoEarlyTx 0x3f /* Max value : no early transmit. */
244
245 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
246
247#define TxPacketMax (8064 >> 7)
248
07d3f51f
FR		 249 FuncEvent = 0xf0,
250 FuncEventMask = 0xf4,
251 FuncPresetState = 0xf8,
252 FuncForceEvent = 0xfc,
1da177e4
LT		 253};
254
f162a5d1
FR		 255enum rtl8110_registers {
256 TBICSR = 0x64,
257 TBI_ANAR = 0x68,
258 TBI_LPAR = 0x6a,
259};
260
261enum rtl8168_8101_registers {
262 CSIDR = 0x64,
263 CSIAR = 0x68,
264#define CSIAR_FLAG 0x80000000
265#define CSIAR_WRITE_CMD 0x80000000
266#define CSIAR_BYTE_ENABLE 0x0f
267#define CSIAR_BYTE_ENABLE_SHIFT 12
268#define CSIAR_ADDR_MASK 0x0fff
065c27c1 269 PMCH = 0x6f,
f162a5d1
FR		 270 EPHYAR = 0x80,
271#define EPHYAR_FLAG 0x80000000
272#define EPHYAR_WRITE_CMD 0x80000000
273#define EPHYAR_REG_MASK 0x1f
274#define EPHYAR_REG_SHIFT 16
275#define EPHYAR_DATA_MASK 0xffff
5a5e4443
HW		 276 DLLPR = 0xd0,
277#define PM_SWITCH (1 << 6)
f162a5d1
FR		 278 DBG_REG = 0xd1,
279#define FIX_NAK_1 (1 << 4)
280#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 281 TWSI = 0xd2,
282 MCU = 0xd3,
283#define EN_NDP (1 << 3)
284#define EN_OOB_RESET (1 << 2)
daf9df6d 285 EFUSEAR = 0xdc,
286#define EFUSEAR_FLAG 0x80000000
287#define EFUSEAR_WRITE_CMD 0x80000000
288#define EFUSEAR_READ_CMD 0x00000000
289#define EFUSEAR_REG_MASK 0x03ff
290#define EFUSEAR_REG_SHIFT 8
291#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 292};
293
c0e45c1c 294enum rtl8168_registers {
b646d900 295 ERIDR = 0x70,
296 ERIAR = 0x74,
297#define ERIAR_FLAG 0x80000000
298#define ERIAR_WRITE_CMD 0x80000000
299#define ERIAR_READ_CMD 0x00000000
300#define ERIAR_ADDR_BYTE_ALIGN 4
301#define ERIAR_EXGMAC 0
302#define ERIAR_MSIX 1
303#define ERIAR_ASF 2
304#define ERIAR_TYPE_SHIFT 16
305#define ERIAR_BYTEEN 0x0f
306#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 307 EPHY_RXER_NUM = 0x7c,
308 OCPDR = 0xb0, /* OCP GPHY access */
309#define OCPDR_WRITE_CMD 0x80000000
310#define OCPDR_READ_CMD 0x00000000
311#define OCPDR_REG_MASK 0x7f
312#define OCPDR_GPHY_REG_SHIFT 16
313#define OCPDR_DATA_MASK 0xffff
314 OCPAR = 0xb4,
315#define OCPAR_FLAG 0x80000000
316#define OCPAR_GPHY_WRITE_CMD 0x8000f060
317#define OCPAR_GPHY_READ_CMD 0x0000f060
e6de30d6 318 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
c0e45c1c 319};
320
07d3f51f 321enum rtl_register_content {
1da177e4 322 /* InterruptStatusBits */
07d3f51f
FR		 323 SYSErr = 0x8000,
324 PCSTimeout = 0x4000,
325 SWInt = 0x0100,
326 TxDescUnavail = 0x0080,
327 RxFIFOOver = 0x0040,
328 LinkChg = 0x0020,
329 RxOverflow = 0x0010,
330 TxErr = 0x0008,
331 TxOK = 0x0004,
332 RxErr = 0x0002,
333 RxOK = 0x0001,
1da177e4
LT		 334
335 /* RxStatusDesc */
9dccf611
FR		 336 RxFOVF = (1 << 23),
337 RxRWT = (1 << 22),
338 RxRES = (1 << 21),
339 RxRUNT = (1 << 20),
340 RxCRC = (1 << 19),
1da177e4
LT		 341
342 /* ChipCmdBits */
07d3f51f
FR		 343 CmdReset = 0x10,
344 CmdRxEnb = 0x08,
345 CmdTxEnb = 0x04,
346 RxBufEmpty = 0x01,
1da177e4 347
275391a4
FR		 348 /* TXPoll register p.5 */
349 HPQ = 0x80, /* Poll cmd on the high prio queue */
350 NPQ = 0x40, /* Poll cmd on the low prio queue */
351 FSWInt = 0x01, /* Forced software interrupt */
352
1da177e4 353 /* Cfg9346Bits */
07d3f51f
FR		 354 Cfg9346_Lock = 0x00,
355 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 356
357 /* rx_mode_bits */
07d3f51f
FR		 358 AcceptErr = 0x20,
359 AcceptRunt = 0x10,
360 AcceptBroadcast = 0x08,
361 AcceptMulticast = 0x04,
362 AcceptMyPhys = 0x02,
363 AcceptAllPhys = 0x01,
1da177e4
LT		 364
365 /* RxConfigBits */
07d3f51f
FR		 366 RxCfgFIFOShift = 13,
367 RxCfgDMAShift = 8,
1da177e4
LT		 368
369 /* TxConfigBits */
370 TxInterFrameGapShift = 24,
371 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
372
5d06a99f 373 /* Config1 register p.24 */
f162a5d1
FR		 374 LEDS1 = (1 << 7),
375 LEDS0 = (1 << 6),
fbac58fc 376 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 377 Speed_down = (1 << 4),
378 MEMMAP = (1 << 3),
379 IOMAP = (1 << 2),
380 VPD = (1 << 1),
5d06a99f
FR		 381 PMEnable = (1 << 0), /* Power Management Enable */
382
6dccd16b
FR		 383 /* Config2 register p. 25 */
384 PCI_Clock_66MHz = 0x01,
385 PCI_Clock_33MHz = 0x00,
386
61a4dcc2
FR		 387 /* Config3 register p.25 */
388 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
389 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 390 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 391
5d06a99f 392 /* Config5 register p.27 */
61a4dcc2
FR		 393 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
394 MWF = (1 << 5), /* Accept Multicast wakeup frame */
395 UWF = (1 << 4), /* Accept Unicast wakeup frame */
396 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 397 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
398
1da177e4
LT		 399 /* TBICSR p.28 */
400 TBIReset = 0x80000000,
401 TBILoopback = 0x40000000,
402 TBINwEnable = 0x20000000,
403 TBINwRestart = 0x10000000,
404 TBILinkOk = 0x02000000,
405 TBINwComplete = 0x01000000,
406
407 /* CPlusCmd p.31 */
f162a5d1
FR		 408 EnableBist = (1 << 15), // 8168 8101
409 Mac_dbgo_oe = (1 << 14), // 8168 8101
410 Normal_mode = (1 << 13), // unused
411 Force_half_dup = (1 << 12), // 8168 8101
412 Force_rxflow_en = (1 << 11), // 8168 8101
413 Force_txflow_en = (1 << 10), // 8168 8101
414 Cxpl_dbg_sel = (1 << 9), // 8168 8101
415 ASF = (1 << 8), // 8168 8101
416 PktCntrDisable = (1 << 7), // 8168 8101
417 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 418 RxVlan = (1 << 6),
419 RxChkSum = (1 << 5),
420 PCIDAC = (1 << 4),
421 PCIMulRW = (1 << 3),
0e485150
FR		 422 INTT_0 = 0x0000, // 8168
423 INTT_1 = 0x0001, // 8168
424 INTT_2 = 0x0002, // 8168
425 INTT_3 = 0x0003, // 8168
1da177e4
LT		 426
427 /* rtl8169_PHYstatus */
07d3f51f
FR		 428 TBI_Enable = 0x80,
429 TxFlowCtrl = 0x40,
430 RxFlowCtrl = 0x20,
431 _1000bpsF = 0x10,
432 _100bps = 0x08,
433 _10bps = 0x04,
434 LinkStatus = 0x02,
435 FullDup = 0x01,
1da177e4 436
1da177e4 437 /* _TBICSRBit */
07d3f51f 438 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 439
440 /* DumpCounterCommand */
07d3f51f 441 CounterDump = 0x8,
1da177e4
LT		 442};
443
07d3f51f 444enum desc_status_bit {
1da177e4
LT		 445 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
446 RingEnd = (1 << 30), /* End of descriptor ring */
447 FirstFrag = (1 << 29), /* First segment of a packet */
448 LastFrag = (1 << 28), /* Final segment of a packet */
449
450 /* Tx private */
451 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
452 MSSShift = 16, /* MSS value position */
453 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
454 IPCS = (1 << 18), /* Calculate IP checksum */
455 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
456 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
457 TxVlanTag = (1 << 17), /* Add VLAN tag */
458
459 /* Rx private */
460 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
461 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
462
463#define RxProtoUDP (PID1)
464#define RxProtoTCP (PID0)
465#define RxProtoIP (PID1 | PID0)
466#define RxProtoMask RxProtoIP
467
468 IPFail = (1 << 16), /* IP checksum failed */
469 UDPFail = (1 << 15), /* UDP/IP checksum failed */
470 TCPFail = (1 << 14), /* TCP/IP checksum failed */
471 RxVlanTag = (1 << 16), /* VLAN tag available */
472};
473
474#define RsvdMask 0x3fffc000
475
476struct TxDesc {
6cccd6e7
REB		 477 __le32 opts1;
478 __le32 opts2;
479 __le64 addr;
1da177e4
LT		 480};
481
482struct RxDesc {
6cccd6e7
REB		 483 __le32 opts1;
484 __le32 opts2;
485 __le64 addr;
1da177e4
LT		 486};
487
488struct ring_info {
489 struct sk_buff *skb;
490 u32 len;
491 u8 __pad[sizeof(void *) - sizeof(u32)];
492};
493
f23e7fda 494enum features {
ccdffb9a
FR		 495 RTL_FEATURE_WOL = (1 << 0),
496 RTL_FEATURE_MSI = (1 << 1),
497 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 498};
499
355423d0
IV		 500struct rtl8169_counters {
501 __le64 tx_packets;
502 __le64 rx_packets;
503 __le64 tx_errors;
504 __le32 rx_errors;
505 __le16 rx_missed;
506 __le16 align_errors;
507 __le32 tx_one_collision;
508 __le32 tx_multi_collision;
509 __le64 rx_unicast;
510 __le64 rx_broadcast;
511 __le32 rx_multicast;
512 __le16 tx_aborted;
513 __le16 tx_underun;
514};
515
1da177e4
LT		 516struct rtl8169_private {
517 void __iomem *mmio_addr; /* memory map physical address */
518 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 519 struct net_device *dev;
bea3348e 520 struct napi_struct napi;
1da177e4 521 spinlock_t lock; /* spin lock flag */
b57b7e5a 522 u32 msg_enable;
1da177e4
LT		 523 int chipset;
524 int mac_version;
1da177e4
LT		 525 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
526 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
527 u32 dirty_rx;
528 u32 dirty_tx;
529 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
530 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
531 dma_addr_t TxPhyAddr;
532 dma_addr_t RxPhyAddr;
6f0333b8 533 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 534 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 535 struct timer_list timer;
536 u16 cp_cmd;
0e485150
FR		 537 u16 intr_event;
538 u16 napi_event;
1da177e4 539 u16 intr_mask;
1da177e4 540 int phy_1000_ctrl_reg;
c0e45c1c 541
542 struct mdio_ops {
543 void (*write)(void __iomem *, int, int);
544 int (*read)(void __iomem *, int);
545 } mdio_ops;
546
065c27c1 547 struct pll_power_ops {
548 void (*down)(struct rtl8169_private *);
549 void (*up)(struct rtl8169_private *);
550 } pll_power_ops;
551
54405cde 552 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 553 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 554 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 555 void (*hw_start)(struct net_device *);
4da19633 556 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 557 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 558 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 559 int pcie_cap;
c4028958 560 struct delayed_work task;
f23e7fda 561 unsigned features;
ccdffb9a
FR		 562
563 struct mii_if_info mii;
355423d0 564 struct rtl8169_counters counters;
e1759441 565 u32 saved_wolopts;
f1e02ed1 566
567 const struct firmware *fw;
1da177e4
LT		 568};
569
979b6c13 570MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 571MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 572module_param(use_dac, int, 0);
4300e8c7 573MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 574module_param_named(debug, debug.msg_enable, int, 0);
575MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 576MODULE_LICENSE("GPL");
577MODULE_VERSION(RTL8169_VERSION);
bca03d5f 578MODULE_FIRMWARE(FIRMWARE_8168D_1);
579MODULE_FIRMWARE(FIRMWARE_8168D_2);
5a5e4443 580MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 581
582static int rtl8169_open(struct net_device *dev);
61357325
SH		 583static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
584 struct net_device *dev);
7d12e780 585static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 586static int rtl8169_init_ring(struct net_device *dev);
07ce4064 587static void rtl_hw_start(struct net_device *dev);
1da177e4 588static int rtl8169_close(struct net_device *dev);
07ce4064 589static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 590static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 591static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 592static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 593 void __iomem *, u32 budget);
4dcb7d33 594static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 595static void rtl8169_down(struct net_device *dev);
99f252b0 596static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 597static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 598
1da177e4 599static const unsigned int rtl8169_rx_config =
5b0384f4 600 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 601
b646d900 602static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
603{
604 void __iomem *ioaddr = tp->mmio_addr;
605 int i;
606
607 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
608 for (i = 0; i < 20; i++) {
609 udelay(100);
610 if (RTL_R32(OCPAR) & OCPAR_FLAG)
611 break;
612 }
613 return RTL_R32(OCPDR);
614}
615
616static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
617{
618 void __iomem *ioaddr = tp->mmio_addr;
619 int i;
620
621 RTL_W32(OCPDR, data);
622 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
623 for (i = 0; i < 20; i++) {
624 udelay(100);
625 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
626 break;
627 }
628}
629
fac5b3ca 630static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 631{
fac5b3ca 632 void __iomem *ioaddr = tp->mmio_addr;
b646d900 633 int i;
634
635 RTL_W8(ERIDR, cmd);
636 RTL_W32(ERIAR, 0x800010e8);
637 msleep(2);
638 for (i = 0; i < 5; i++) {
639 udelay(100);
640 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
641 break;
642 }
643
fac5b3ca 644 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 645}
646
647#define OOB_CMD_RESET 0x00
648#define OOB_CMD_DRIVER_START 0x05
649#define OOB_CMD_DRIVER_STOP 0x06
650
651static void rtl8168_driver_start(struct rtl8169_private *tp)
652{
653 int i;
654
655 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
656
657 for (i = 0; i < 10; i++) {
658 msleep(10);
659 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
660 break;
661 }
662}
663
664static void rtl8168_driver_stop(struct rtl8169_private *tp)
665{
666 int i;
667
668 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
669
670 for (i = 0; i < 10; i++) {
671 msleep(10);
672 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
673 break;
674 }
675}
676
677
4da19633 678static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 679{
680 int i;
681
a6baf3af 682 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 683
2371408c 684 for (i = 20; i > 0; i--) {
07d3f51f
FR		 685 /*
686 * Check if the RTL8169 has completed writing to the specified
687 * MII register.
688 */
5b0384f4 689 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 690 break;
2371408c 691 udelay(25);
1da177e4 692 }
024a07ba 693 /*
81a95f04
TT		 694 * According to hardware specs a 20us delay is required after write
695 * complete indication, but before sending next command.
024a07ba 696 */
81a95f04 697 udelay(20);
1da177e4
LT		 698}
699
4da19633 700static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 701{
702 int i, value = -1;
703
a6baf3af 704 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 705
2371408c 706 for (i = 20; i > 0; i--) {
07d3f51f
FR		 707 /*
708 * Check if the RTL8169 has completed retrieving data from
709 * the specified MII register.
710 */
1da177e4 711 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 712 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 713 break;
714 }
2371408c 715 udelay(25);
1da177e4 716 }
81a95f04
TT		 717 /*
718 * According to hardware specs a 20us delay is required after read
719 * complete indication, but before sending next command.
720 */
721 udelay(20);
722
1da177e4
LT		 723 return value;
724}
725
c0e45c1c 726static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
727{
728 int i;
729
730 RTL_W32(OCPDR, data |
731 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
732 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
733 RTL_W32(EPHY_RXER_NUM, 0);
734
735 for (i = 0; i < 100; i++) {
736 mdelay(1);
737 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
738 break;
739 }
740}
741
742static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
743{
744 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
745 (value & OCPDR_DATA_MASK));
746}
747
748static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
749{
750 int i;
751
752 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
753
754 mdelay(1);
755 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
756 RTL_W32(EPHY_RXER_NUM, 0);
757
758 for (i = 0; i < 100; i++) {
759 mdelay(1);
760 if (RTL_R32(OCPAR) & OCPAR_FLAG)
761 break;
762 }
763
764 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
765}
766
e6de30d6 767#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
768
769static void r8168dp_2_mdio_start(void __iomem *ioaddr)
770{
771 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
772}
773
774static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
775{
776 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
777}
778
779static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
780{
781 r8168dp_2_mdio_start(ioaddr);
782
783 r8169_mdio_write(ioaddr, reg_addr, value);
784
785 r8168dp_2_mdio_stop(ioaddr);
786}
787
788static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
789{
790 int value;
791
792 r8168dp_2_mdio_start(ioaddr);
793
794 value = r8169_mdio_read(ioaddr, reg_addr);
795
796 r8168dp_2_mdio_stop(ioaddr);
797
798 return value;
799}
800
4da19633 801static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 802{
c0e45c1c 803 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 804}
805
4da19633 806static int rtl_readphy(struct rtl8169_private *tp, int location)
807{
c0e45c1c 808 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 809}
810
811static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
812{
813 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
814}
815
816static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 817{
818 int val;
819
4da19633 820 val = rtl_readphy(tp, reg_addr);
821 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 822}
823
ccdffb9a
FR		 824static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
825 int val)
826{
827 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 828
4da19633 829 rtl_writephy(tp, location, val);
ccdffb9a
FR		 830}
831
832static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
833{
834 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 835
4da19633 836 return rtl_readphy(tp, location);
ccdffb9a
FR		 837}
838
dacf8154
FR		 839static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
840{
841 unsigned int i;
842
843 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
844 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
845
846 for (i = 0; i < 100; i++) {
847 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
848 break;
849 udelay(10);
850 }
851}
852
853static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
854{
855 u16 value = 0xffff;
856 unsigned int i;
857
858 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
859
860 for (i = 0; i < 100; i++) {
861 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
862 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
863 break;
864 }
865 udelay(10);
866 }
867
868 return value;
869}
870
871static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
872{
873 unsigned int i;
874
875 RTL_W32(CSIDR, value);
876 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
877 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
878
879 for (i = 0; i < 100; i++) {
880 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
881 break;
882 udelay(10);
883 }
884}
885
886static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
887{
888 u32 value = ~0x00;
889 unsigned int i;
890
891 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
892 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
893
894 for (i = 0; i < 100; i++) {
895 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
896 value = RTL_R32(CSIDR);
897 break;
898 }
899 udelay(10);
900 }
901
902 return value;
903}
904
daf9df6d 905static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
906{
907 u8 value = 0xff;
908 unsigned int i;
909
910 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
911
912 for (i = 0; i < 300; i++) {
913 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
914 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
915 break;
916 }
917 udelay(100);
918 }
919
920 return value;
921}
922
1da177e4
LT		 923static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
924{
925 RTL_W16(IntrMask, 0x0000);
926
927 RTL_W16(IntrStatus, 0xffff);
928}
929
930static void rtl8169_asic_down(void __iomem *ioaddr)
931{
932 RTL_W8(ChipCmd, 0x00);
933 rtl8169_irq_mask_and_ack(ioaddr);
934 RTL_R16(CPlusCmd);
935}
936
4da19633 937static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 938{
4da19633 939 void __iomem *ioaddr = tp->mmio_addr;
940
1da177e4
LT		 941 return RTL_R32(TBICSR) & TBIReset;
942}
943
4da19633 944static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 945{
4da19633 946 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 947}
948
949static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
950{
951 return RTL_R32(TBICSR) & TBILinkOk;
952}
953
954static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
955{
956 return RTL_R8(PHYstatus) & LinkStatus;
957}
958
4da19633 959static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 960{
4da19633 961 void __iomem *ioaddr = tp->mmio_addr;
962
1da177e4
LT		 963 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
964}
965
4da19633 966static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 967{
968 unsigned int val;
969
4da19633 970 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
971 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 972}
973
e4fbce74 974static void __rtl8169_check_link_status(struct net_device *dev,
07d3f51f 975 struct rtl8169_private *tp,
e4fbce74
RW		 976 void __iomem *ioaddr,
977 bool pm)
1da177e4
LT		 978{
979 unsigned long flags;
980
981 spin_lock_irqsave(&tp->lock, flags);
982 if (tp->link_ok(ioaddr)) {
e1759441 983 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 984 if (pm)
985 pm_request_resume(&tp->pci_dev->dev);
1da177e4 986 netif_carrier_on(dev);
1519e57f
FR		 987 if (net_ratelimit())
988 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 989 } else {
1da177e4 990 netif_carrier_off(dev);
bf82c189 991 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 992 if (pm)
993 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 994 }
1da177e4
LT		 995 spin_unlock_irqrestore(&tp->lock, flags);
996}
997
e4fbce74
RW		 998static void rtl8169_check_link_status(struct net_device *dev,
999 struct rtl8169_private *tp,
1000 void __iomem *ioaddr)
1001{
1002 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1003}
1004
e1759441
RW		 1005#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1006
1007static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1008{
61a4dcc2
FR		 1009 void __iomem *ioaddr = tp->mmio_addr;
1010 u8 options;
e1759441 1011 u32 wolopts = 0;
61a4dcc2
FR		 1012
1013 options = RTL_R8(Config1);
1014 if (!(options & PMEnable))
e1759441 1015 return 0;
61a4dcc2
FR		 1016
1017 options = RTL_R8(Config3);
1018 if (options & LinkUp)
e1759441 1019 wolopts |= WAKE_PHY;
61a4dcc2 1020 if (options & MagicPacket)
e1759441 1021 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1022
1023 options = RTL_R8(Config5);
1024 if (options & UWF)
e1759441 1025 wolopts |= WAKE_UCAST;
61a4dcc2 1026 if (options & BWF)
e1759441 1027 wolopts |= WAKE_BCAST;
61a4dcc2 1028 if (options & MWF)
e1759441 1029 wolopts |= WAKE_MCAST;
61a4dcc2 1030
e1759441 1031 return wolopts;
61a4dcc2
FR		 1032}
1033
e1759441 1034static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1035{
1036 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1037
1038 spin_lock_irq(&tp->lock);
1039
1040 wol->supported = WAKE_ANY;
1041 wol->wolopts = __rtl8169_get_wol(tp);
1042
1043 spin_unlock_irq(&tp->lock);
1044}
1045
1046static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1047{
61a4dcc2 1048 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1049 unsigned int i;
350f7596 1050 static const struct {
61a4dcc2
FR		 1051 u32 opt;
1052 u16 reg;
1053 u8 mask;
1054 } cfg[] = {
1055 { WAKE_ANY, Config1, PMEnable },
1056 { WAKE_PHY, Config3, LinkUp },
1057 { WAKE_MAGIC, Config3, MagicPacket },
1058 { WAKE_UCAST, Config5, UWF },
1059 { WAKE_BCAST, Config5, BWF },
1060 { WAKE_MCAST, Config5, MWF },
1061 { WAKE_ANY, Config5, LanWake }
1062 };
1063
61a4dcc2
FR		 1064 RTL_W8(Cfg9346, Cfg9346_Unlock);
1065
1066 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1067 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1068 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1069 options |= cfg[i].mask;
1070 RTL_W8(cfg[i].reg, options);
1071 }
1072
1073 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1074}
1075
1076static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1077{
1078 struct rtl8169_private *tp = netdev_priv(dev);
1079
1080 spin_lock_irq(&tp->lock);
61a4dcc2 1081
f23e7fda
FR		 1082 if (wol->wolopts)
1083 tp->features |= RTL_FEATURE_WOL;
1084 else
1085 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1086 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1087 spin_unlock_irq(&tp->lock);
1088
ea80907f 1089 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1090
61a4dcc2
FR		 1091 return 0;
1092}
1093
1da177e4
LT		 1094static void rtl8169_get_drvinfo(struct net_device *dev,
1095 struct ethtool_drvinfo *info)
1096{
1097 struct rtl8169_private *tp = netdev_priv(dev);
1098
1099 strcpy(info->driver, MODULENAME);
1100 strcpy(info->version, RTL8169_VERSION);
1101 strcpy(info->bus_info, pci_name(tp->pci_dev));
1102}
1103
1104static int rtl8169_get_regs_len(struct net_device *dev)
1105{
1106 return R8169_REGS_SIZE;
1107}
1108
1109static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1110 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1111{
1112 struct rtl8169_private *tp = netdev_priv(dev);
1113 void __iomem *ioaddr = tp->mmio_addr;
1114 int ret = 0;
1115 u32 reg;
1116
1117 reg = RTL_R32(TBICSR);
1118 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1119 (duplex == DUPLEX_FULL)) {
1120 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1121 } else if (autoneg == AUTONEG_ENABLE)
1122 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1123 else {
bf82c189
JP		 1124 netif_warn(tp, link, dev,
1125 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1126 ret = -EOPNOTSUPP;
1127 }
1128
1129 return ret;
1130}
1131
1132static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1133 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1134{
1135 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1136 int giga_ctrl, bmcr;
54405cde 1137 int rc = -EINVAL;
1da177e4 1138
716b50a3 1139 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1140
1141 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1142 int auto_nego;
1143
4da19633 1144 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1145 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1146 ADVERTISE_100HALF | ADVERTISE_100FULL);
1147
1148 if (adv & ADVERTISED_10baseT_Half)
1149 auto_nego |= ADVERTISE_10HALF;
1150 if (adv & ADVERTISED_10baseT_Full)
1151 auto_nego |= ADVERTISE_10FULL;
1152 if (adv & ADVERTISED_100baseT_Half)
1153 auto_nego |= ADVERTISE_100HALF;
1154 if (adv & ADVERTISED_100baseT_Full)
1155 auto_nego |= ADVERTISE_100FULL;
1156
3577aa1b 1157 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1158
4da19633 1159 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1160 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1161
3577aa1b 1162 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1163 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1164 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1165 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1166 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1167 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1168 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1169 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
5a5e4443
HW		 1170 (tp->mac_version != RTL_GIGA_MAC_VER_16) &&
1171 (tp->mac_version != RTL_GIGA_MAC_VER_29) &&
1172 (tp->mac_version != RTL_GIGA_MAC_VER_30)) {
54405cde
ON		 1173 if (adv & ADVERTISED_1000baseT_Half)
1174 giga_ctrl |= ADVERTISE_1000HALF;
1175 if (adv & ADVERTISED_1000baseT_Full)
1176 giga_ctrl |= ADVERTISE_1000FULL;
1177 } else if (adv & (ADVERTISED_1000baseT_Half |
1178 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1179 netif_info(tp, link, dev,
1180 "PHY does not support 1000Mbps\n");
54405cde 1181 goto out;
bcf0bf90 1182 }
1da177e4 1183
3577aa1b 1184 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1185
4da19633 1186 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1187 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1188 } else {
1189 giga_ctrl = 0;
1190
1191 if (speed == SPEED_10)
1192 bmcr = 0;
1193 else if (speed == SPEED_100)
1194 bmcr = BMCR_SPEED100;
1195 else
54405cde 1196 goto out;
3577aa1b 1197
1198 if (duplex == DUPLEX_FULL)
1199 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1200 }
1201
1da177e4
LT		 1202 tp->phy_1000_ctrl_reg = giga_ctrl;
1203
4da19633 1204 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1205
1206 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1207 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1208 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1209 rtl_writephy(tp, 0x17, 0x2138);
1210 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1211 } else {
4da19633 1212 rtl_writephy(tp, 0x17, 0x2108);
1213 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1214 }
1215 }
1216
54405cde
ON		 1217 rc = 0;
1218out:
1219 return rc;
1da177e4
LT		 1220}
1221
1222static int rtl8169_set_speed(struct net_device *dev,
54405cde 1223 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1224{
1225 struct rtl8169_private *tp = netdev_priv(dev);
1226 int ret;
1227
54405cde 1228 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1da177e4 1229
64e4bfb4 1230 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1231 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1232
1233 return ret;
1234}
1235
1236static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1237{
1238 struct rtl8169_private *tp = netdev_priv(dev);
1239 unsigned long flags;
1240 int ret;
1241
1242 spin_lock_irqsave(&tp->lock, flags);
54405cde
ON		 1243 ret = rtl8169_set_speed(dev,
1244 cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising);
1da177e4 1245 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1246
1da177e4
LT		 1247 return ret;
1248}
1249
1250static u32 rtl8169_get_rx_csum(struct net_device *dev)
1251{
1252 struct rtl8169_private *tp = netdev_priv(dev);
1253
1254 return tp->cp_cmd & RxChkSum;
1255}
1256
1257static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1258{
1259 struct rtl8169_private *tp = netdev_priv(dev);
1260 void __iomem *ioaddr = tp->mmio_addr;
1261 unsigned long flags;
1262
1263 spin_lock_irqsave(&tp->lock, flags);
1264
1265 if (data)
1266 tp->cp_cmd |= RxChkSum;
1267 else
1268 tp->cp_cmd &= ~RxChkSum;
1269
1270 RTL_W16(CPlusCmd, tp->cp_cmd);
1271 RTL_R16(CPlusCmd);
1272
1273 spin_unlock_irqrestore(&tp->lock, flags);
1274
1275 return 0;
1276}
1277
1da177e4
LT		 1278static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1279 struct sk_buff *skb)
1280{
eab6d18d 1281 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1282 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1283}
1284
7a8fc77b
FR		 1285#define NETIF_F_HW_VLAN_TX_RX (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX)
1286
1287static void rtl8169_vlan_mode(struct net_device *dev)
1da177e4
LT		 1288{
1289 struct rtl8169_private *tp = netdev_priv(dev);
1290 void __iomem *ioaddr = tp->mmio_addr;
1291 unsigned long flags;
1292
1293 spin_lock_irqsave(&tp->lock, flags);
7a8fc77b 1294 if (dev->features & NETIF_F_HW_VLAN_RX)
1da177e4
LT		 1295 tp->cp_cmd |= RxVlan;
1296 else
1297 tp->cp_cmd &= ~RxVlan;
1298 RTL_W16(CPlusCmd, tp->cp_cmd);
7a8fc77b 1299 /* PCI commit */
1da177e4
LT		 1300 RTL_R16(CPlusCmd);
1301 spin_unlock_irqrestore(&tp->lock, flags);
7a8fc77b
FR		 1302
1303 dev->vlan_features = dev->features &~ NETIF_F_HW_VLAN_TX_RX;
1da177e4
LT		 1304}
1305
7a8fc77b 1306static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1307{
1308 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1309
7a8fc77b
FR		 1310 if (opts2 & RxVlanTag)
1311 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1312
1da177e4 1313 desc->opts2 = 0;
1da177e4
LT		 1314}
1315
ccdffb9a 1316static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1317{
1318 struct rtl8169_private *tp = netdev_priv(dev);
1319 void __iomem *ioaddr = tp->mmio_addr;
1320 u32 status;
1321
1322 cmd->supported =
1323 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1324 cmd->port = PORT_FIBRE;
1325 cmd->transceiver = XCVR_INTERNAL;
1326
1327 status = RTL_R32(TBICSR);
1328 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1329 cmd->autoneg = !!(status & TBINwEnable);
1330
1331 cmd->speed = SPEED_1000;
1332 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1333
1334 return 0;
1da177e4
LT		 1335}
1336
ccdffb9a 1337static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1338{
1339 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1340
1341 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1342}
1343
1344static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1345{
1346 struct rtl8169_private *tp = netdev_priv(dev);
1347 unsigned long flags;
ccdffb9a 1348 int rc;
1da177e4
LT		 1349
1350 spin_lock_irqsave(&tp->lock, flags);
1351
ccdffb9a 1352 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1353
1354 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1355 return rc;
1da177e4
LT		 1356}
1357
1358static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1359 void *p)
1360{
5b0384f4
FR		 1361 struct rtl8169_private *tp = netdev_priv(dev);
1362 unsigned long flags;
1da177e4 1363
5b0384f4
FR		 1364 if (regs->len > R8169_REGS_SIZE)
1365 regs->len = R8169_REGS_SIZE;
1da177e4 1366
5b0384f4
FR		 1367 spin_lock_irqsave(&tp->lock, flags);
1368 memcpy_fromio(p, tp->mmio_addr, regs->len);
1369 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1370}
1371
b57b7e5a
SH		 1372static u32 rtl8169_get_msglevel(struct net_device *dev)
1373{
1374 struct rtl8169_private *tp = netdev_priv(dev);
1375
1376 return tp->msg_enable;
1377}
1378
1379static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1380{
1381 struct rtl8169_private *tp = netdev_priv(dev);
1382
1383 tp->msg_enable = value;
1384}
1385
d4a3a0fc
SH		 1386static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1387 "tx_packets",
1388 "rx_packets",
1389 "tx_errors",
1390 "rx_errors",
1391 "rx_missed",
1392 "align_errors",
1393 "tx_single_collisions",
1394 "tx_multi_collisions",
1395 "unicast",
1396 "broadcast",
1397 "multicast",
1398 "tx_aborted",
1399 "tx_underrun",
1400};
1401
b9f2c044 1402static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1403{
b9f2c044
JG		 1404 switch (sset) {
1405 case ETH_SS_STATS:
1406 return ARRAY_SIZE(rtl8169_gstrings);
1407 default:
1408 return -EOPNOTSUPP;
1409 }
d4a3a0fc
SH		 1410}
1411
355423d0 1412static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1413{
1414 struct rtl8169_private *tp = netdev_priv(dev);
1415 void __iomem *ioaddr = tp->mmio_addr;
1416 struct rtl8169_counters *counters;
1417 dma_addr_t paddr;
1418 u32 cmd;
355423d0 1419 int wait = 1000;
48addcc9 1420 struct device *d = &tp->pci_dev->dev;
d4a3a0fc 1421
355423d0
IV		 1422 /*
1423 * Some chips are unable to dump tally counters when the receiver
1424 * is disabled.
1425 */
1426 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1427 return;
d4a3a0fc 1428
48addcc9 1429 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1430 if (!counters)
1431 return;
1432
1433 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1434 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1435 RTL_W32(CounterAddrLow, cmd);
1436 RTL_W32(CounterAddrLow, cmd | CounterDump);
1437
355423d0
IV		 1438 while (wait--) {
1439 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1440 /* copy updated counters */
1441 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1442 break;
355423d0
IV		 1443 }
1444 udelay(10);
d4a3a0fc
SH		 1445 }
1446
1447 RTL_W32(CounterAddrLow, 0);
1448 RTL_W32(CounterAddrHigh, 0);
1449
48addcc9 1450 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1451}
1452
355423d0
IV		 1453static void rtl8169_get_ethtool_stats(struct net_device *dev,
1454 struct ethtool_stats *stats, u64 *data)
1455{
1456 struct rtl8169_private *tp = netdev_priv(dev);
1457
1458 ASSERT_RTNL();
1459
1460 rtl8169_update_counters(dev);
1461
1462 data[0] = le64_to_cpu(tp->counters.tx_packets);
1463 data[1] = le64_to_cpu(tp->counters.rx_packets);
1464 data[2] = le64_to_cpu(tp->counters.tx_errors);
1465 data[3] = le32_to_cpu(tp->counters.rx_errors);
1466 data[4] = le16_to_cpu(tp->counters.rx_missed);
1467 data[5] = le16_to_cpu(tp->counters.align_errors);
1468 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1469 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1470 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1471 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1472 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1473 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1474 data[12] = le16_to_cpu(tp->counters.tx_underun);
1475}
1476
d4a3a0fc
SH		 1477static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1478{
1479 switch(stringset) {
1480 case ETH_SS_STATS:
1481 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1482 break;
1483 }
1484}
1485
7a8fc77b
FR		 1486static int rtl8169_set_flags(struct net_device *dev, u32 data)
1487{
1488 struct rtl8169_private *tp = netdev_priv(dev);
1489 unsigned long old_feat = dev->features;
1490 int rc;
1491
1492 if ((tp->mac_version == RTL_GIGA_MAC_VER_05) &&
1493 !(data & ETH_FLAG_RXVLAN)) {
1494 netif_info(tp, drv, dev, "8110SCd requires hardware Rx VLAN\n");
1495 return -EINVAL;
1496 }
1497
1498 rc = ethtool_op_set_flags(dev, data, ETH_FLAG_TXVLAN | ETH_FLAG_RXVLAN);
1499 if (rc)
1500 return rc;
1501
1502 if ((old_feat ^ dev->features) & NETIF_F_HW_VLAN_RX)
1503 rtl8169_vlan_mode(dev);
1504
1505 return 0;
1506}
1507
7282d491 1508static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1509 .get_drvinfo = rtl8169_get_drvinfo,
1510 .get_regs_len = rtl8169_get_regs_len,
1511 .get_link = ethtool_op_get_link,
1512 .get_settings = rtl8169_get_settings,
1513 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1514 .get_msglevel = rtl8169_get_msglevel,
1515 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1516 .get_rx_csum = rtl8169_get_rx_csum,
1517 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1518 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1519 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1520 .set_tso = ethtool_op_set_tso,
1521 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1522 .get_wol = rtl8169_get_wol,
1523 .set_wol = rtl8169_set_wol,
d4a3a0fc 1524 .get_strings = rtl8169_get_strings,
b9f2c044 1525 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1526 .get_ethtool_stats = rtl8169_get_ethtool_stats,
7a8fc77b
FR		 1527 .set_flags = rtl8169_set_flags,
1528 .get_flags = ethtool_op_get_flags,
1da177e4
LT		 1529};
1530
07d3f51f
FR		 1531static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1532 void __iomem *ioaddr)
1da177e4 1533{
0e485150
FR		 1534 /*
1535 * The driver currently handles the 8168Bf and the 8168Be identically
1536 * but they can be identified more specifically through the test below
1537 * if needed:
1538 *
1539 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1540 *
1541 * Same thing for the 8101Eb and the 8101Ec:
1542 *
1543 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1544 */
350f7596 1545 static const struct {
1da177e4 1546 u32 mask;
e3cf0cc0 1547 u32 val;
1da177e4
LT		 1548 int mac_version;
1549 } mac_info[] = {
5b538df9 1550 /* 8168D family. */
daf9df6d 1551 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1552 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1553 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1554
e6de30d6 1555 /* 8168DP family. */
1556 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1557 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1558
ef808d50 1559 /* 8168C family. */
17c99297 1560 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1561 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1562 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1563 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1564 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1565 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1566 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1567 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1568 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1569
1570 /* 8168B family. */
1571 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1572 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1573 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1574 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1575
1576 /* 8101 family. */
36a0e6c2 1577 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1578 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1579 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1580 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1581 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1582 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1583 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1584 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1585 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1586 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1587 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1588 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1589 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1590 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1591 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1592 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1593 /* FIXME: where did these entries come from ? -- FR */
1594 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1595 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1596
1597 /* 8110 family. */
1598 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1599 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1600 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1601 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1602 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1603 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1604
f21b75e9
JD		 1605 /* Catch-all */
1606 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1607 }, *p = mac_info;
1608 u32 reg;
1609
e3cf0cc0
FR		 1610 reg = RTL_R32(TxConfig);
1611 while ((reg & p->mask) != p->val)
1da177e4
LT		 1612 p++;
1613 tp->mac_version = p->mac_version;
1614}
1615
1616static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1617{
bcf0bf90 1618 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1619}
1620
867763c1
FR		 1621struct phy_reg {
1622 u16 reg;
1623 u16 val;
1624};
1625
4da19633 1626static void rtl_writephy_batch(struct rtl8169_private *tp,
1627 const struct phy_reg *regs, int len)
867763c1
FR		 1628{
1629 while (len-- > 0) {
4da19633 1630 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1631 regs++;
1632 }
1633}
1634
bca03d5f 1635#define PHY_READ 0x00000000
1636#define PHY_DATA_OR 0x10000000
1637#define PHY_DATA_AND 0x20000000
1638#define PHY_BJMPN 0x30000000
1639#define PHY_READ_EFUSE 0x40000000
1640#define PHY_READ_MAC_BYTE 0x50000000
1641#define PHY_WRITE_MAC_BYTE 0x60000000
1642#define PHY_CLEAR_READCOUNT 0x70000000
1643#define PHY_WRITE 0x80000000
1644#define PHY_READCOUNT_EQ_SKIP 0x90000000
1645#define PHY_COMP_EQ_SKIPN 0xa0000000
1646#define PHY_COMP_NEQ_SKIPN 0xb0000000
1647#define PHY_WRITE_PREVIOUS 0xc0000000
1648#define PHY_SKIPN 0xd0000000
1649#define PHY_DELAY_MS 0xe0000000
1650#define PHY_WRITE_ERI_WORD 0xf0000000
1651
1652static void
1653rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1654{
bca03d5f 1655 __le32 *phytable = (__le32 *)fw->data;
1656 struct net_device *dev = tp->dev;
42b82dc1 1657 size_t index, fw_size = fw->size / sizeof(*phytable);
1658 u32 predata, count;
bca03d5f 1659
1660 if (fw->size % sizeof(*phytable)) {
1661 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1662 return;
1663 }
1664
42b82dc1 1665 for (index = 0; index < fw_size; index++) {
1666 u32 action = le32_to_cpu(phytable[index]);
1667 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1668
42b82dc1 1669 switch(action & 0xf0000000) {
1670 case PHY_READ:
1671 case PHY_DATA_OR:
1672 case PHY_DATA_AND:
1673 case PHY_READ_EFUSE:
1674 case PHY_CLEAR_READCOUNT:
1675 case PHY_WRITE:
1676 case PHY_WRITE_PREVIOUS:
1677 case PHY_DELAY_MS:
1678 break;
1679
1680 case PHY_BJMPN:
1681 if (regno > index) {
1682 netif_err(tp, probe, tp->dev,
1683 "Out of range of firmware\n");
1684 return;
1685 }
1686 break;
1687 case PHY_READCOUNT_EQ_SKIP:
1688 if (index + 2 >= fw_size) {
1689 netif_err(tp, probe, tp->dev,
1690 "Out of range of firmware\n");
1691 return;
1692 }
1693 break;
1694 case PHY_COMP_EQ_SKIPN:
1695 case PHY_COMP_NEQ_SKIPN:
1696 case PHY_SKIPN:
1697 if (index + 1 + regno >= fw_size) {
1698 netif_err(tp, probe, tp->dev,
1699 "Out of range of firmware\n");
1700 return;
1701 }
bca03d5f 1702 break;
1703
42b82dc1 1704 case PHY_READ_MAC_BYTE:
1705 case PHY_WRITE_MAC_BYTE:
1706 case PHY_WRITE_ERI_WORD:
1707 default:
1708 netif_err(tp, probe, tp->dev,
1709 "Invalid action 0x%08x\n", action);
bca03d5f 1710 return;
1711 }
1712 }
1713
42b82dc1 1714 predata = 0;
1715 count = 0;
1716
1717 for (index = 0; index < fw_size; ) {
1718 u32 action = le32_to_cpu(phytable[index]);
bca03d5f 1719 u32 data = action & 0x0000ffff;
42b82dc1 1720 u32 regno = (action & 0x0fff0000) >> 16;
1721
1722 if (!action)
1723 break;
bca03d5f 1724
1725 switch(action & 0xf0000000) {
42b82dc1 1726 case PHY_READ:
1727 predata = rtl_readphy(tp, regno);
1728 count++;
1729 index++;
1730 break;
1731 case PHY_DATA_OR:
1732 predata |= data;
1733 index++;
1734 break;
1735 case PHY_DATA_AND:
1736 predata &= data;
1737 index++;
1738 break;
1739 case PHY_BJMPN:
1740 index -= regno;
1741 break;
1742 case PHY_READ_EFUSE:
1743 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1744 index++;
1745 break;
1746 case PHY_CLEAR_READCOUNT:
1747 count = 0;
1748 index++;
1749 break;
bca03d5f 1750 case PHY_WRITE:
42b82dc1 1751 rtl_writephy(tp, regno, data);
1752 index++;
1753 break;
1754 case PHY_READCOUNT_EQ_SKIP:
1755 if (count == data)
1756 index += 2;
1757 else
1758 index += 1;
bca03d5f 1759 break;
42b82dc1 1760 case PHY_COMP_EQ_SKIPN:
1761 if (predata == data)
1762 index += regno;
1763 index++;
1764 break;
1765 case PHY_COMP_NEQ_SKIPN:
1766 if (predata != data)
1767 index += regno;
1768 index++;
1769 break;
1770 case PHY_WRITE_PREVIOUS:
1771 rtl_writephy(tp, regno, predata);
1772 index++;
1773 break;
1774 case PHY_SKIPN:
1775 index += regno + 1;
1776 break;
1777 case PHY_DELAY_MS:
1778 mdelay(data);
1779 index++;
1780 break;
1781
1782 case PHY_READ_MAC_BYTE:
1783 case PHY_WRITE_MAC_BYTE:
1784 case PHY_WRITE_ERI_WORD:
bca03d5f 1785 default:
1786 BUG();
1787 }
1788 }
1789}
1790
f1e02ed1 1791static void rtl_release_firmware(struct rtl8169_private *tp)
1792{
1793 release_firmware(tp->fw);
1794 tp->fw = NULL;
1795}
1796
1797static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1798{
1799 const struct firmware **fw = &tp->fw;
1800 int rc = !*fw;
1801
1802 if (rc) {
1803 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1804 if (rc < 0)
1805 goto out;
1806 }
1807
1808 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1809 rtl_phy_write_fw(tp, *fw);
1810out:
1811 return rc;
1812}
1813
4da19633 1814static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1815{
350f7596 1816 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1817 { 0x1f, 0x0001 },
1818 { 0x06, 0x006e },
1819 { 0x08, 0x0708 },
1820 { 0x15, 0x4000 },
1821 { 0x18, 0x65c7 },
1da177e4 1822
0b9b571d 1823 { 0x1f, 0x0001 },
1824 { 0x03, 0x00a1 },
1825 { 0x02, 0x0008 },
1826 { 0x01, 0x0120 },
1827 { 0x00, 0x1000 },
1828 { 0x04, 0x0800 },
1829 { 0x04, 0x0000 },
1da177e4 1830
0b9b571d 1831 { 0x03, 0xff41 },
1832 { 0x02, 0xdf60 },
1833 { 0x01, 0x0140 },
1834 { 0x00, 0x0077 },
1835 { 0x04, 0x7800 },
1836 { 0x04, 0x7000 },
1837
1838 { 0x03, 0x802f },
1839 { 0x02, 0x4f02 },
1840 { 0x01, 0x0409 },
1841 { 0x00, 0xf0f9 },
1842 { 0x04, 0x9800 },
1843 { 0x04, 0x9000 },
1844
1845 { 0x03, 0xdf01 },
1846 { 0x02, 0xdf20 },
1847 { 0x01, 0xff95 },
1848 { 0x00, 0xba00 },
1849 { 0x04, 0xa800 },
1850 { 0x04, 0xa000 },
1851
1852 { 0x03, 0xff41 },
1853 { 0x02, 0xdf20 },
1854 { 0x01, 0x0140 },
1855 { 0x00, 0x00bb },
1856 { 0x04, 0xb800 },
1857 { 0x04, 0xb000 },
1858
1859 { 0x03, 0xdf41 },
1860 { 0x02, 0xdc60 },
1861 { 0x01, 0x6340 },
1862 { 0x00, 0x007d },
1863 { 0x04, 0xd800 },
1864 { 0x04, 0xd000 },
1865
1866 { 0x03, 0xdf01 },
1867 { 0x02, 0xdf20 },
1868 { 0x01, 0x100a },
1869 { 0x00, 0xa0ff },
1870 { 0x04, 0xf800 },
1871 { 0x04, 0xf000 },
1872
1873 { 0x1f, 0x0000 },
1874 { 0x0b, 0x0000 },
1875 { 0x00, 0x9200 }
1876 };
1da177e4 1877
4da19633 1878 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1879}
1880
4da19633 1881static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1882{
350f7596 1883 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1884 { 0x1f, 0x0002 },
1885 { 0x01, 0x90d0 },
1886 { 0x1f, 0x0000 }
1887 };
1888
4da19633 1889 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1890}
1891
4da19633 1892static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1893{
1894 struct pci_dev *pdev = tp->pci_dev;
1895 u16 vendor_id, device_id;
1896
1897 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1898 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1899
1900 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1901 return;
1902
4da19633 1903 rtl_writephy(tp, 0x1f, 0x0001);
1904 rtl_writephy(tp, 0x10, 0xf01b);
1905 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1906}
1907
4da19633 1908static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1909{
350f7596 1910 static const struct phy_reg phy_reg_init[] = {
2e955856 1911 { 0x1f, 0x0001 },
1912 { 0x04, 0x0000 },
1913 { 0x03, 0x00a1 },
1914 { 0x02, 0x0008 },
1915 { 0x01, 0x0120 },
1916 { 0x00, 0x1000 },
1917 { 0x04, 0x0800 },
1918 { 0x04, 0x9000 },
1919 { 0x03, 0x802f },
1920 { 0x02, 0x4f02 },
1921 { 0x01, 0x0409 },
1922 { 0x00, 0xf099 },
1923 { 0x04, 0x9800 },
1924 { 0x04, 0xa000 },
1925 { 0x03, 0xdf01 },
1926 { 0x02, 0xdf20 },
1927 { 0x01, 0xff95 },
1928 { 0x00, 0xba00 },
1929 { 0x04, 0xa800 },
1930 { 0x04, 0xf000 },
1931 { 0x03, 0xdf01 },
1932 { 0x02, 0xdf20 },
1933 { 0x01, 0x101a },
1934 { 0x00, 0xa0ff },
1935 { 0x04, 0xf800 },
1936 { 0x04, 0x0000 },
1937 { 0x1f, 0x0000 },
1938
1939 { 0x1f, 0x0001 },
1940 { 0x10, 0xf41b },
1941 { 0x14, 0xfb54 },
1942 { 0x18, 0xf5c7 },
1943 { 0x1f, 0x0000 },
1944
1945 { 0x1f, 0x0001 },
1946 { 0x17, 0x0cc0 },
1947 { 0x1f, 0x0000 }
1948 };
1949
4da19633 1950 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 1951
4da19633 1952 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 1953}
1954
4da19633 1955static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 1956{
350f7596 1957 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1958 { 0x1f, 0x0001 },
1959 { 0x04, 0x0000 },
1960 { 0x03, 0x00a1 },
1961 { 0x02, 0x0008 },
1962 { 0x01, 0x0120 },
1963 { 0x00, 0x1000 },
1964 { 0x04, 0x0800 },
1965 { 0x04, 0x9000 },
1966 { 0x03, 0x802f },
1967 { 0x02, 0x4f02 },
1968 { 0x01, 0x0409 },
1969 { 0x00, 0xf099 },
1970 { 0x04, 0x9800 },
1971 { 0x04, 0xa000 },
1972 { 0x03, 0xdf01 },
1973 { 0x02, 0xdf20 },
1974 { 0x01, 0xff95 },
1975 { 0x00, 0xba00 },
1976 { 0x04, 0xa800 },
1977 { 0x04, 0xf000 },
1978 { 0x03, 0xdf01 },
1979 { 0x02, 0xdf20 },
1980 { 0x01, 0x101a },
1981 { 0x00, 0xa0ff },
1982 { 0x04, 0xf800 },
1983 { 0x04, 0x0000 },
1984 { 0x1f, 0x0000 },
1985
1986 { 0x1f, 0x0001 },
1987 { 0x0b, 0x8480 },
1988 { 0x1f, 0x0000 },
1989
1990 { 0x1f, 0x0001 },
1991 { 0x18, 0x67c7 },
1992 { 0x04, 0x2000 },
1993 { 0x03, 0x002f },
1994 { 0x02, 0x4360 },
1995 { 0x01, 0x0109 },
1996 { 0x00, 0x3022 },
1997 { 0x04, 0x2800 },
1998 { 0x1f, 0x0000 },
1999
2000 { 0x1f, 0x0001 },
2001 { 0x17, 0x0cc0 },
2002 { 0x1f, 0x0000 }
2003 };
2004
4da19633 2005 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2006}
2007
4da19633 2008static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2009{
350f7596 2010 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2011 { 0x10, 0xf41b },
2012 { 0x1f, 0x0000 }
2013 };
2014
4da19633 2015 rtl_writephy(tp, 0x1f, 0x0001);
2016 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2017
4da19633 2018 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2019}
2020
4da19633 2021static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2022{
350f7596 2023 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2024 { 0x1f, 0x0001 },
2025 { 0x10, 0xf41b },
2026 { 0x1f, 0x0000 }
2027 };
2028
4da19633 2029 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2030}
2031
4da19633 2032static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2033{
350f7596 2034 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2035 { 0x1f, 0x0000 },
2036 { 0x1d, 0x0f00 },
2037 { 0x1f, 0x0002 },
2038 { 0x0c, 0x1ec8 },
2039 { 0x1f, 0x0000 }
2040 };
2041
4da19633 2042 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2043}
2044
4da19633 2045static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2046{
350f7596 2047 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2048 { 0x1f, 0x0001 },
2049 { 0x1d, 0x3d98 },
2050 { 0x1f, 0x0000 }
2051 };
2052
4da19633 2053 rtl_writephy(tp, 0x1f, 0x0000);
2054 rtl_patchphy(tp, 0x14, 1 << 5);
2055 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2056
4da19633 2057 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2058}
2059
4da19633 2060static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2061{
350f7596 2062 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2063 { 0x1f, 0x0001 },
2064 { 0x12, 0x2300 },
867763c1
FR		 2065 { 0x1f, 0x0002 },
2066 { 0x00, 0x88d4 },
2067 { 0x01, 0x82b1 },
2068 { 0x03, 0x7002 },
2069 { 0x08, 0x9e30 },
2070 { 0x09, 0x01f0 },
2071 { 0x0a, 0x5500 },
2072 { 0x0c, 0x00c8 },
2073 { 0x1f, 0x0003 },
2074 { 0x12, 0xc096 },
2075 { 0x16, 0x000a },
f50d4275
FR		 2076 { 0x1f, 0x0000 },
2077 { 0x1f, 0x0000 },
2078 { 0x09, 0x2000 },
2079 { 0x09, 0x0000 }
867763c1
FR		 2080 };
2081
4da19633 2082 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2083
4da19633 2084 rtl_patchphy(tp, 0x14, 1 << 5);
2085 rtl_patchphy(tp, 0x0d, 1 << 5);
2086 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2087}
2088
4da19633 2089static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2090{
350f7596 2091 static const struct phy_reg phy_reg_init[] = {
f50d4275 2092 { 0x1f, 0x0001 },
7da97ec9 2093 { 0x12, 0x2300 },
f50d4275
FR		 2094 { 0x03, 0x802f },
2095 { 0x02, 0x4f02 },
2096 { 0x01, 0x0409 },
2097 { 0x00, 0xf099 },
2098 { 0x04, 0x9800 },
2099 { 0x04, 0x9000 },
2100 { 0x1d, 0x3d98 },
7da97ec9
FR		 2101 { 0x1f, 0x0002 },
2102 { 0x0c, 0x7eb8 },
f50d4275
FR		 2103 { 0x06, 0x0761 },
2104 { 0x1f, 0x0003 },
2105 { 0x16, 0x0f0a },
7da97ec9
FR		 2106 { 0x1f, 0x0000 }
2107 };
2108
4da19633 2109 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2110
4da19633 2111 rtl_patchphy(tp, 0x16, 1 << 0);
2112 rtl_patchphy(tp, 0x14, 1 << 5);
2113 rtl_patchphy(tp, 0x0d, 1 << 5);
2114 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2115}
2116
4da19633 2117static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2118{
350f7596 2119 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2120 { 0x1f, 0x0001 },
2121 { 0x12, 0x2300 },
2122 { 0x1d, 0x3d98 },
2123 { 0x1f, 0x0002 },
2124 { 0x0c, 0x7eb8 },
2125 { 0x06, 0x5461 },
2126 { 0x1f, 0x0003 },
2127 { 0x16, 0x0f0a },
2128 { 0x1f, 0x0000 }
2129 };
2130
4da19633 2131 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2132
4da19633 2133 rtl_patchphy(tp, 0x16, 1 << 0);
2134 rtl_patchphy(tp, 0x14, 1 << 5);
2135 rtl_patchphy(tp, 0x0d, 1 << 5);
2136 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2137}
2138
4da19633 2139static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2140{
4da19633 2141 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2142}
2143
bca03d5f 2144static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2145{
350f7596 2146 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2147 /* Channel Estimation */
5b538df9 2148 { 0x1f, 0x0001 },
daf9df6d 2149 { 0x06, 0x4064 },
2150 { 0x07, 0x2863 },
2151 { 0x08, 0x059c },
2152 { 0x09, 0x26b4 },
2153 { 0x0a, 0x6a19 },
2154 { 0x0b, 0xdcc8 },
2155 { 0x10, 0xf06d },
2156 { 0x14, 0x7f68 },
2157 { 0x18, 0x7fd9 },
2158 { 0x1c, 0xf0ff },
2159 { 0x1d, 0x3d9c },
5b538df9 2160 { 0x1f, 0x0003 },
daf9df6d 2161 { 0x12, 0xf49f },
2162 { 0x13, 0x070b },
2163 { 0x1a, 0x05ad },
bca03d5f 2164 { 0x14, 0x94c0 },
2165
2166 /*
2167 * Tx Error Issue
2168 * enhance line driver power
2169 */
5b538df9 2170 { 0x1f, 0x0002 },
daf9df6d 2171 { 0x06, 0x5561 },
2172 { 0x1f, 0x0005 },
2173 { 0x05, 0x8332 },
bca03d5f 2174 { 0x06, 0x5561 },
2175
2176 /*
2177 * Can not link to 1Gbps with bad cable
2178 * Decrease SNR threshold form 21.07dB to 19.04dB
2179 */
2180 { 0x1f, 0x0001 },
2181 { 0x17, 0x0cc0 },
daf9df6d 2182
5b538df9 2183 { 0x1f, 0x0000 },
bca03d5f 2184 { 0x0d, 0xf880 }
daf9df6d 2185 };
bca03d5f 2186 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2187
4da19633 2188 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2189
bca03d5f 2190 /*
2191 * Rx Error Issue
2192 * Fine Tune Switching regulator parameter
2193 */
4da19633 2194 rtl_writephy(tp, 0x1f, 0x0002);
2195 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2196 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2197
daf9df6d 2198 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2199 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2200 { 0x1f, 0x0002 },
2201 { 0x05, 0x669a },
2202 { 0x1f, 0x0005 },
2203 { 0x05, 0x8330 },
2204 { 0x06, 0x669a },
2205 { 0x1f, 0x0002 }
2206 };
2207 int val;
2208
4da19633 2209 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2210
4da19633 2211 val = rtl_readphy(tp, 0x0d);
daf9df6d 2212
2213 if ((val & 0x00ff) != 0x006c) {
350f7596 2214 static const u32 set[] = {
daf9df6d 2215 0x0065, 0x0066, 0x0067, 0x0068,
2216 0x0069, 0x006a, 0x006b, 0x006c
2217 };
2218 int i;
2219
4da19633 2220 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2221
2222 val &= 0xff00;
2223 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2224 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2225 }
2226 } else {
350f7596 2227 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2228 { 0x1f, 0x0002 },
2229 { 0x05, 0x6662 },
2230 { 0x1f, 0x0005 },
2231 { 0x05, 0x8330 },
2232 { 0x06, 0x6662 }
2233 };
2234
4da19633 2235 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2236 }
2237
bca03d5f 2238 /* RSET couple improve */
4da19633 2239 rtl_writephy(tp, 0x1f, 0x0002);
2240 rtl_patchphy(tp, 0x0d, 0x0300);
2241 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2242
bca03d5f 2243 /* Fine tune PLL performance */
4da19633 2244 rtl_writephy(tp, 0x1f, 0x0002);
2245 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2246 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2247
4da19633 2248 rtl_writephy(tp, 0x1f, 0x0005);
2249 rtl_writephy(tp, 0x05, 0x001b);
f1e02ed1 2250 if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2251 (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
bca03d5f 2252 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2253 }
2254
4da19633 2255 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2256}
2257
bca03d5f 2258static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2259{
350f7596 2260 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2261 /* Channel Estimation */
daf9df6d 2262 { 0x1f, 0x0001 },
2263 { 0x06, 0x4064 },
2264 { 0x07, 0x2863 },
2265 { 0x08, 0x059c },
2266 { 0x09, 0x26b4 },
2267 { 0x0a, 0x6a19 },
2268 { 0x0b, 0xdcc8 },
2269 { 0x10, 0xf06d },
2270 { 0x14, 0x7f68 },
2271 { 0x18, 0x7fd9 },
2272 { 0x1c, 0xf0ff },
2273 { 0x1d, 0x3d9c },
2274 { 0x1f, 0x0003 },
2275 { 0x12, 0xf49f },
2276 { 0x13, 0x070b },
2277 { 0x1a, 0x05ad },
2278 { 0x14, 0x94c0 },
2279
bca03d5f 2280 /*
2281 * Tx Error Issue
2282 * enhance line driver power
2283 */
daf9df6d 2284 { 0x1f, 0x0002 },
2285 { 0x06, 0x5561 },
2286 { 0x1f, 0x0005 },
2287 { 0x05, 0x8332 },
bca03d5f 2288 { 0x06, 0x5561 },
2289
2290 /*
2291 * Can not link to 1Gbps with bad cable
2292 * Decrease SNR threshold form 21.07dB to 19.04dB
2293 */
2294 { 0x1f, 0x0001 },
2295 { 0x17, 0x0cc0 },
daf9df6d 2296
2297 { 0x1f, 0x0000 },
bca03d5f 2298 { 0x0d, 0xf880 }
5b538df9 2299 };
bca03d5f 2300 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2301
4da19633 2302 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2303
daf9df6d 2304 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2305 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2306 { 0x1f, 0x0002 },
2307 { 0x05, 0x669a },
5b538df9 2308 { 0x1f, 0x0005 },
daf9df6d 2309 { 0x05, 0x8330 },
2310 { 0x06, 0x669a },
2311
2312 { 0x1f, 0x0002 }
2313 };
2314 int val;
2315
4da19633 2316 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2317
4da19633 2318 val = rtl_readphy(tp, 0x0d);
daf9df6d 2319 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2320 static const u32 set[] = {
daf9df6d 2321 0x0065, 0x0066, 0x0067, 0x0068,
2322 0x0069, 0x006a, 0x006b, 0x006c
2323 };
2324 int i;
2325
4da19633 2326 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2327
2328 val &= 0xff00;
2329 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2330 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2331 }
2332 } else {
350f7596 2333 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2334 { 0x1f, 0x0002 },
2335 { 0x05, 0x2642 },
5b538df9 2336 { 0x1f, 0x0005 },
daf9df6d 2337 { 0x05, 0x8330 },
2338 { 0x06, 0x2642 }
5b538df9
FR		 2339 };
2340
4da19633 2341 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2342 }
2343
bca03d5f 2344 /* Fine tune PLL performance */
4da19633 2345 rtl_writephy(tp, 0x1f, 0x0002);
2346 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2347 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2348
bca03d5f 2349 /* Switching regulator Slew rate */
4da19633 2350 rtl_writephy(tp, 0x1f, 0x0002);
2351 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2352
4da19633 2353 rtl_writephy(tp, 0x1f, 0x0005);
2354 rtl_writephy(tp, 0x05, 0x001b);
f1e02ed1 2355 if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2356 (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
bca03d5f 2357 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2358 }
2359
4da19633 2360 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2361}
2362
4da19633 2363static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2364{
350f7596 2365 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2366 { 0x1f, 0x0002 },
2367 { 0x10, 0x0008 },
2368 { 0x0d, 0x006c },
2369
2370 { 0x1f, 0x0000 },
2371 { 0x0d, 0xf880 },
2372
2373 { 0x1f, 0x0001 },
2374 { 0x17, 0x0cc0 },
2375
2376 { 0x1f, 0x0001 },
2377 { 0x0b, 0xa4d8 },
2378 { 0x09, 0x281c },
2379 { 0x07, 0x2883 },
2380 { 0x0a, 0x6b35 },
2381 { 0x1d, 0x3da4 },
2382 { 0x1c, 0xeffd },
2383 { 0x14, 0x7f52 },
2384 { 0x18, 0x7fc6 },
2385 { 0x08, 0x0601 },
2386 { 0x06, 0x4063 },
2387 { 0x10, 0xf074 },
2388 { 0x1f, 0x0003 },
2389 { 0x13, 0x0789 },
2390 { 0x12, 0xf4bd },
2391 { 0x1a, 0x04fd },
2392 { 0x14, 0x84b0 },
2393 { 0x1f, 0x0000 },
2394 { 0x00, 0x9200 },
2395
2396 { 0x1f, 0x0005 },
2397 { 0x01, 0x0340 },
2398 { 0x1f, 0x0001 },
2399 { 0x04, 0x4000 },
2400 { 0x03, 0x1d21 },
2401 { 0x02, 0x0c32 },
2402 { 0x01, 0x0200 },
2403 { 0x00, 0x5554 },
2404 { 0x04, 0x4800 },
2405 { 0x04, 0x4000 },
2406 { 0x04, 0xf000 },
2407 { 0x03, 0xdf01 },
2408 { 0x02, 0xdf20 },
2409 { 0x01, 0x101a },
2410 { 0x00, 0xa0ff },
2411 { 0x04, 0xf800 },
2412 { 0x04, 0xf000 },
2413 { 0x1f, 0x0000 },
2414
2415 { 0x1f, 0x0007 },
2416 { 0x1e, 0x0023 },
2417 { 0x16, 0x0000 },
2418 { 0x1f, 0x0000 }
2419 };
2420
4da19633 2421 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2422}
2423
e6de30d6 2424static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2425{
2426 static const struct phy_reg phy_reg_init[] = {
2427 { 0x1f, 0x0001 },
2428 { 0x17, 0x0cc0 },
2429
2430 { 0x1f, 0x0007 },
2431 { 0x1e, 0x002d },
2432 { 0x18, 0x0040 },
2433 { 0x1f, 0x0000 }
2434 };
2435
2436 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2437 rtl_patchphy(tp, 0x0d, 1 << 5);
2438}
2439
4da19633 2440static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2441{
350f7596 2442 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2443 { 0x1f, 0x0003 },
2444 { 0x08, 0x441d },
2445 { 0x01, 0x9100 },
2446 { 0x1f, 0x0000 }
2447 };
2448
4da19633 2449 rtl_writephy(tp, 0x1f, 0x0000);
2450 rtl_patchphy(tp, 0x11, 1 << 12);
2451 rtl_patchphy(tp, 0x19, 1 << 13);
2452 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2453
4da19633 2454 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2455}
2456
5a5e4443
HW		 2457static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2458{
2459 static const struct phy_reg phy_reg_init[] = {
2460 { 0x1f, 0x0005 },
2461 { 0x1a, 0x0000 },
2462 { 0x1f, 0x0000 },
2463
2464 { 0x1f, 0x0004 },
2465 { 0x1c, 0x0000 },
2466 { 0x1f, 0x0000 },
2467
2468 { 0x1f, 0x0001 },
2469 { 0x15, 0x7701 },
2470 { 0x1f, 0x0000 }
2471 };
2472
2473 /* Disable ALDPS before ram code */
2474 rtl_writephy(tp, 0x1f, 0x0000);
2475 rtl_writephy(tp, 0x18, 0x0310);
2476 msleep(100);
2477
2478 if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0)
2479 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2480
2481 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2482}
2483
5615d9f1
FR		 2484static void rtl_hw_phy_config(struct net_device *dev)
2485{
2486 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2487
2488 rtl8169_print_mac_version(tp);
2489
2490 switch (tp->mac_version) {
2491 case RTL_GIGA_MAC_VER_01:
2492 break;
2493 case RTL_GIGA_MAC_VER_02:
2494 case RTL_GIGA_MAC_VER_03:
4da19633 2495 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2496 break;
2497 case RTL_GIGA_MAC_VER_04:
4da19633 2498 rtl8169sb_hw_phy_config(tp);
5615d9f1 2499 break;
2e955856 2500 case RTL_GIGA_MAC_VER_05:
4da19633 2501 rtl8169scd_hw_phy_config(tp);
2e955856 2502 break;
8c7006aa 2503 case RTL_GIGA_MAC_VER_06:
4da19633 2504 rtl8169sce_hw_phy_config(tp);
8c7006aa 2505 break;
2857ffb7
FR		 2506 case RTL_GIGA_MAC_VER_07:
2507 case RTL_GIGA_MAC_VER_08:
2508 case RTL_GIGA_MAC_VER_09:
4da19633 2509 rtl8102e_hw_phy_config(tp);
2857ffb7 2510 break;
236b8082 2511 case RTL_GIGA_MAC_VER_11:
4da19633 2512 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2513 break;
2514 case RTL_GIGA_MAC_VER_12:
4da19633 2515 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2516 break;
2517 case RTL_GIGA_MAC_VER_17:
4da19633 2518 rtl8168bef_hw_phy_config(tp);
236b8082 2519 break;
867763c1 2520 case RTL_GIGA_MAC_VER_18:
4da19633 2521 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2522 break;
2523 case RTL_GIGA_MAC_VER_19:
4da19633 2524 rtl8168c_1_hw_phy_config(tp);
867763c1 2525 break;
7da97ec9 2526 case RTL_GIGA_MAC_VER_20:
4da19633 2527 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2528 break;
197ff761 2529 case RTL_GIGA_MAC_VER_21:
4da19633 2530 rtl8168c_3_hw_phy_config(tp);
197ff761 2531 break;
6fb07058 2532 case RTL_GIGA_MAC_VER_22:
4da19633 2533 rtl8168c_4_hw_phy_config(tp);
6fb07058 2534 break;
ef3386f0 2535 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2536 case RTL_GIGA_MAC_VER_24:
4da19633 2537 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2538 break;
5b538df9 2539 case RTL_GIGA_MAC_VER_25:
bca03d5f 2540 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2541 break;
2542 case RTL_GIGA_MAC_VER_26:
bca03d5f 2543 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2544 break;
2545 case RTL_GIGA_MAC_VER_27:
4da19633 2546 rtl8168d_3_hw_phy_config(tp);
5b538df9 2547 break;
e6de30d6 2548 case RTL_GIGA_MAC_VER_28:
2549 rtl8168d_4_hw_phy_config(tp);
2550 break;
5a5e4443
HW		 2551 case RTL_GIGA_MAC_VER_29:
2552 case RTL_GIGA_MAC_VER_30:
2553 rtl8105e_hw_phy_config(tp);
2554 break;
ef3386f0 2555
5615d9f1
FR		 2556 default:
2557 break;
2558 }
2559}
2560
1da177e4
LT		 2561static void rtl8169_phy_timer(unsigned long __opaque)
2562{
2563 struct net_device *dev = (struct net_device *)__opaque;
2564 struct rtl8169_private *tp = netdev_priv(dev);
2565 struct timer_list *timer = &tp->timer;
2566 void __iomem *ioaddr = tp->mmio_addr;
2567 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2568
bcf0bf90 2569 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2570
64e4bfb4 2571 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2572 return;
2573
2574 spin_lock_irq(&tp->lock);
2575
4da19633 2576 if (tp->phy_reset_pending(tp)) {
5b0384f4 2577 /*
1da177e4
LT		 2578 * A busy loop could burn quite a few cycles on nowadays CPU.
2579 * Let's delay the execution of the timer for a few ticks.
2580 */
2581 timeout = HZ/10;
2582 goto out_mod_timer;
2583 }
2584
2585 if (tp->link_ok(ioaddr))
2586 goto out_unlock;
2587
bf82c189 2588 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2589
4da19633 2590 tp->phy_reset_enable(tp);
1da177e4
LT		 2591
2592out_mod_timer:
2593 mod_timer(timer, jiffies + timeout);
2594out_unlock:
2595 spin_unlock_irq(&tp->lock);
2596}
2597
2598static inline void rtl8169_delete_timer(struct net_device *dev)
2599{
2600 struct rtl8169_private *tp = netdev_priv(dev);
2601 struct timer_list *timer = &tp->timer;
2602
e179bb7b 2603 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2604 return;
2605
2606 del_timer_sync(timer);
2607}
2608
2609static inline void rtl8169_request_timer(struct net_device *dev)
2610{
2611 struct rtl8169_private *tp = netdev_priv(dev);
2612 struct timer_list *timer = &tp->timer;
2613
e179bb7b 2614 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2615 return;
2616
2efa53f3 2617 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2618}
2619
2620#ifdef CONFIG_NET_POLL_CONTROLLER
2621/*
2622 * Polling 'interrupt' - used by things like netconsole to send skbs
2623 * without having to re-enable interrupts. It's not called while
2624 * the interrupt routine is executing.
2625 */
2626static void rtl8169_netpoll(struct net_device *dev)
2627{
2628 struct rtl8169_private *tp = netdev_priv(dev);
2629 struct pci_dev *pdev = tp->pci_dev;
2630
2631 disable_irq(pdev->irq);
7d12e780 2632 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2633 enable_irq(pdev->irq);
2634}
2635#endif
2636
2637static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2638 void __iomem *ioaddr)
2639{
2640 iounmap(ioaddr);
2641 pci_release_regions(pdev);
87aeec76 2642 pci_clear_mwi(pdev);
1da177e4
LT		 2643 pci_disable_device(pdev);
2644 free_netdev(dev);
2645}
2646
bf793295
FR		 2647static void rtl8169_phy_reset(struct net_device *dev,
2648 struct rtl8169_private *tp)
2649{
07d3f51f 2650 unsigned int i;
bf793295 2651
4da19633 2652 tp->phy_reset_enable(tp);
bf793295 2653 for (i = 0; i < 100; i++) {
4da19633 2654 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2655 return;
2656 msleep(1);
2657 }
bf82c189 2658 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2659}
2660
4ff96fa6
FR		 2661static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2662{
2663 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2664
5615d9f1 2665 rtl_hw_phy_config(dev);
4ff96fa6 2666
77332894
MS		 2667 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2668 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2669 RTL_W8(0x82, 0x01);
2670 }
4ff96fa6 2671
6dccd16b
FR		 2672 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2673
2674 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2675 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2676
bcf0bf90 2677 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2678 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2679 RTL_W8(0x82, 0x01);
2680 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2681 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2682 }
2683
bf793295
FR		 2684 rtl8169_phy_reset(dev, tp);
2685
54405cde
ON		 2686 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2687 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2688 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
db552b33 2689 (tp->mii.supports_gmii ?
54405cde 2690 ADVERTISED_1000baseT_Half |
db552b33 2691 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 2692
bf82c189
JP		 2693 if (RTL_R8(PHYstatus) & TBI_Enable)
2694 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2695}
2696
773d2021
FR		 2697static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2698{
2699 void __iomem *ioaddr = tp->mmio_addr;
2700 u32 high;
2701 u32 low;
2702
2703 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2704 high = addr[4] | (addr[5] << 8);
2705
2706 spin_lock_irq(&tp->lock);
2707
2708 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2709
773d2021 2710 RTL_W32(MAC4, high);
908ba2bf 2711 RTL_R32(MAC4);
2712
78f1cd02 2713 RTL_W32(MAC0, low);
908ba2bf 2714 RTL_R32(MAC0);
2715
773d2021
FR		 2716 RTL_W8(Cfg9346, Cfg9346_Lock);
2717
2718 spin_unlock_irq(&tp->lock);
2719}
2720
2721static int rtl_set_mac_address(struct net_device *dev, void *p)
2722{
2723 struct rtl8169_private *tp = netdev_priv(dev);
2724 struct sockaddr *addr = p;
2725
2726 if (!is_valid_ether_addr(addr->sa_data))
2727 return -EADDRNOTAVAIL;
2728
2729 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2730
2731 rtl_rar_set(tp, dev->dev_addr);
2732
2733 return 0;
2734}
2735
5f787a1a
FR		 2736static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2737{
2738 struct rtl8169_private *tp = netdev_priv(dev);
2739 struct mii_ioctl_data *data = if_mii(ifr);
2740
8b4ab28d
FR		 2741 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2742}
5f787a1a 2743
8b4ab28d
FR		 2744static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2745{
5f787a1a
FR		 2746 switch (cmd) {
2747 case SIOCGMIIPHY:
2748 data->phy_id = 32; /* Internal PHY */
2749 return 0;
2750
2751 case SIOCGMIIREG:
4da19633 2752 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2753 return 0;
2754
2755 case SIOCSMIIREG:
4da19633 2756 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2757 return 0;
2758 }
2759 return -EOPNOTSUPP;
2760}
2761
8b4ab28d
FR		 2762static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2763{
2764 return -EOPNOTSUPP;
2765}
2766
0e485150
FR		 2767static const struct rtl_cfg_info {
2768 void (*hw_start)(struct net_device *);
2769 unsigned int region;
2770 unsigned int align;
2771 u16 intr_event;
2772 u16 napi_event;
ccdffb9a 2773 unsigned features;
f21b75e9 2774 u8 default_ver;
0e485150
FR		 2775} rtl_cfg_infos [] = {
2776 [RTL_CFG_0] = {
2777 .hw_start = rtl_hw_start_8169,
2778 .region = 1,
e9f63f30 2779 .align = 0,
0e485150
FR		 2780 .intr_event = SYSErr | LinkChg | RxOverflow |
2781 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2782 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2783 .features = RTL_FEATURE_GMII,
2784 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2785 },
2786 [RTL_CFG_1] = {
2787 .hw_start = rtl_hw_start_8168,
2788 .region = 2,
2789 .align = 8,
53f57357 2790 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2791 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2792 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2793 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2794 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2795 },
2796 [RTL_CFG_2] = {
2797 .hw_start = rtl_hw_start_8101,
2798 .region = 2,
2799 .align = 8,
2800 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2801 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2802 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2803 .features = RTL_FEATURE_MSI,
2804 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2805 }
2806};
2807
fbac58fc
FR		 2808/* Cfg9346_Unlock assumed. */
2809static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2810 const struct rtl_cfg_info *cfg)
2811{
2812 unsigned msi = 0;
2813 u8 cfg2;
2814
2815 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2816 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2817 if (pci_enable_msi(pdev)) {
2818 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2819 } else {
2820 cfg2 |= MSIEnable;
2821 msi = RTL_FEATURE_MSI;
2822 }
2823 }
2824 RTL_W8(Config2, cfg2);
2825 return msi;
2826}
2827
2828static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2829{
2830 if (tp->features & RTL_FEATURE_MSI) {
2831 pci_disable_msi(pdev);
2832 tp->features &= ~RTL_FEATURE_MSI;
2833 }
2834}
2835
8b4ab28d
FR		 2836static const struct net_device_ops rtl8169_netdev_ops = {
2837 .ndo_open = rtl8169_open,
2838 .ndo_stop = rtl8169_close,
2839 .ndo_get_stats = rtl8169_get_stats,
00829823 2840 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2841 .ndo_tx_timeout = rtl8169_tx_timeout,
2842 .ndo_validate_addr = eth_validate_addr,
2843 .ndo_change_mtu = rtl8169_change_mtu,
2844 .ndo_set_mac_address = rtl_set_mac_address,
2845 .ndo_do_ioctl = rtl8169_ioctl,
2846 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 2847#ifdef CONFIG_NET_POLL_CONTROLLER
2848 .ndo_poll_controller = rtl8169_netpoll,
2849#endif
2850
2851};
2852
c0e45c1c 2853static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2854{
2855 struct mdio_ops *ops = &tp->mdio_ops;
2856
2857 switch (tp->mac_version) {
2858 case RTL_GIGA_MAC_VER_27:
2859 ops->write = r8168dp_1_mdio_write;
2860 ops->read = r8168dp_1_mdio_read;
2861 break;
e6de30d6 2862 case RTL_GIGA_MAC_VER_28:
2863 ops->write = r8168dp_2_mdio_write;
2864 ops->read = r8168dp_2_mdio_read;
2865 break;
c0e45c1c 2866 default:
2867 ops->write = r8169_mdio_write;
2868 ops->read = r8169_mdio_read;
2869 break;
2870 }
2871}
2872
065c27c1 2873static void r810x_phy_power_down(struct rtl8169_private *tp)
2874{
2875 rtl_writephy(tp, 0x1f, 0x0000);
2876 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2877}
2878
2879static void r810x_phy_power_up(struct rtl8169_private *tp)
2880{
2881 rtl_writephy(tp, 0x1f, 0x0000);
2882 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2883}
2884
2885static void r810x_pll_power_down(struct rtl8169_private *tp)
2886{
2887 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2888 rtl_writephy(tp, 0x1f, 0x0000);
2889 rtl_writephy(tp, MII_BMCR, 0x0000);
2890 return;
2891 }
2892
2893 r810x_phy_power_down(tp);
2894}
2895
2896static void r810x_pll_power_up(struct rtl8169_private *tp)
2897{
2898 r810x_phy_power_up(tp);
2899}
2900
2901static void r8168_phy_power_up(struct rtl8169_private *tp)
2902{
2903 rtl_writephy(tp, 0x1f, 0x0000);
2904 rtl_writephy(tp, 0x0e, 0x0000);
2905 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2906}
2907
2908static void r8168_phy_power_down(struct rtl8169_private *tp)
2909{
2910 rtl_writephy(tp, 0x1f, 0x0000);
2911 rtl_writephy(tp, 0x0e, 0x0200);
2912 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2913}
2914
2915static void r8168_pll_power_down(struct rtl8169_private *tp)
2916{
2917 void __iomem *ioaddr = tp->mmio_addr;
2918
5d2e1957
HW		 2919 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
2920 (tp->mac_version == RTL_GIGA_MAC_VER_28)) &&
2921 (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) {
065c27c1 2922 return;
5d2e1957 2923 }
065c27c1 2924
2925 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2926 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2927 (RTL_R16(CPlusCmd) & ASF)) {
2928 return;
2929 }
2930
2931 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2932 rtl_writephy(tp, 0x1f, 0x0000);
2933 rtl_writephy(tp, MII_BMCR, 0x0000);
2934
2935 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2936 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2937 return;
2938 }
2939
2940 r8168_phy_power_down(tp);
2941
2942 switch (tp->mac_version) {
2943 case RTL_GIGA_MAC_VER_25:
2944 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 2945 case RTL_GIGA_MAC_VER_27:
2946 case RTL_GIGA_MAC_VER_28:
065c27c1 2947 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2948 break;
2949 }
2950}
2951
2952static void r8168_pll_power_up(struct rtl8169_private *tp)
2953{
2954 void __iomem *ioaddr = tp->mmio_addr;
2955
5d2e1957
HW		 2956 if (((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
2957 (tp->mac_version == RTL_GIGA_MAC_VER_28)) &&
2958 (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) {
065c27c1 2959 return;
5d2e1957 2960 }
065c27c1 2961
2962 switch (tp->mac_version) {
2963 case RTL_GIGA_MAC_VER_25:
2964 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 2965 case RTL_GIGA_MAC_VER_27:
2966 case RTL_GIGA_MAC_VER_28:
065c27c1 2967 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2968 break;
2969 }
2970
2971 r8168_phy_power_up(tp);
2972}
2973
2974static void rtl_pll_power_op(struct rtl8169_private *tp,
2975 void (*op)(struct rtl8169_private *))
2976{
2977 if (op)
2978 op(tp);
2979}
2980
2981static void rtl_pll_power_down(struct rtl8169_private *tp)
2982{
2983 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2984}
2985
2986static void rtl_pll_power_up(struct rtl8169_private *tp)
2987{
2988 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2989}
2990
2991static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2992{
2993 struct pll_power_ops *ops = &tp->pll_power_ops;
2994
2995 switch (tp->mac_version) {
2996 case RTL_GIGA_MAC_VER_07:
2997 case RTL_GIGA_MAC_VER_08:
2998 case RTL_GIGA_MAC_VER_09:
2999 case RTL_GIGA_MAC_VER_10:
3000 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3001 case RTL_GIGA_MAC_VER_29:
3002 case RTL_GIGA_MAC_VER_30:
065c27c1 3003 ops->down = r810x_pll_power_down;
3004 ops->up = r810x_pll_power_up;
3005 break;
3006
3007 case RTL_GIGA_MAC_VER_11:
3008 case RTL_GIGA_MAC_VER_12:
3009 case RTL_GIGA_MAC_VER_17:
3010 case RTL_GIGA_MAC_VER_18:
3011 case RTL_GIGA_MAC_VER_19:
3012 case RTL_GIGA_MAC_VER_20:
3013 case RTL_GIGA_MAC_VER_21:
3014 case RTL_GIGA_MAC_VER_22:
3015 case RTL_GIGA_MAC_VER_23:
3016 case RTL_GIGA_MAC_VER_24:
3017 case RTL_GIGA_MAC_VER_25:
3018 case RTL_GIGA_MAC_VER_26:
3019 case RTL_GIGA_MAC_VER_27:
e6de30d6 3020 case RTL_GIGA_MAC_VER_28:
065c27c1 3021 ops->down = r8168_pll_power_down;
3022 ops->up = r8168_pll_power_up;
3023 break;
3024
3025 default:
3026 ops->down = NULL;
3027 ops->up = NULL;
3028 break;
3029 }
3030}
3031
1da177e4 3032static int __devinit
4ff96fa6 3033rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3034{
0e485150
FR		 3035 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3036 const unsigned int region = cfg->region;
1da177e4 3037 struct rtl8169_private *tp;
ccdffb9a 3038 struct mii_if_info *mii;
4ff96fa6
FR		 3039 struct net_device *dev;
3040 void __iomem *ioaddr;
07d3f51f
FR		 3041 unsigned int i;
3042 int rc;
1da177e4 3043
4ff96fa6
FR		 3044 if (netif_msg_drv(&debug)) {
3045 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3046 MODULENAME, RTL8169_VERSION);
3047 }
1da177e4 3048
1da177e4 3049 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3050 if (!dev) {
b57b7e5a 3051 if (netif_msg_drv(&debug))
9b91cf9d 3052 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3053 rc = -ENOMEM;
3054 goto out;
1da177e4
LT		 3055 }
3056
1da177e4 3057 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3058 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3059 tp = netdev_priv(dev);
c4028958 3060 tp->dev = dev;
21e197f2 3061 tp->pci_dev = pdev;
b57b7e5a 3062 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3063
ccdffb9a
FR		 3064 mii = &tp->mii;
3065 mii->dev = dev;
3066 mii->mdio_read = rtl_mdio_read;
3067 mii->mdio_write = rtl_mdio_write;
3068 mii->phy_id_mask = 0x1f;
3069 mii->reg_num_mask = 0x1f;
3070 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3071
ba04c7c9
SG		 3072 /* disable ASPM completely as that cause random device stop working
3073 * problems as well as full system hangs for some PCIe devices users */
3074 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3075 PCIE_LINK_STATE_CLKPM);
3076
1da177e4
LT		 3077 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3078 rc = pci_enable_device(pdev);
b57b7e5a 3079 if (rc < 0) {
bf82c189 3080 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3081 goto err_out_free_dev_1;
1da177e4
LT		 3082 }
3083
87aeec76 3084 if (pci_set_mwi(pdev) < 0)
3085 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3086
1da177e4 3087 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3088 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3089 netif_err(tp, probe, dev,
3090 "region #%d not an MMIO resource, aborting\n",
3091 region);
1da177e4 3092 rc = -ENODEV;
87aeec76 3093 goto err_out_mwi_2;
1da177e4 3094 }
4ff96fa6 3095
1da177e4 3096 /* check for weird/broken PCI region reporting */
bcf0bf90 3097 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3098 netif_err(tp, probe, dev,
3099 "Invalid PCI region size(s), aborting\n");
1da177e4 3100 rc = -ENODEV;
87aeec76 3101 goto err_out_mwi_2;
1da177e4
LT		 3102 }
3103
3104 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3105 if (rc < 0) {
bf82c189 3106 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3107 goto err_out_mwi_2;
1da177e4
LT		 3108 }
3109
d24e9aaf 3110 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3111
3112 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3113 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3114 tp->cp_cmd |= PCIDAC;
3115 dev->features |= NETIF_F_HIGHDMA;
3116 } else {
284901a9 3117 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3118 if (rc < 0) {
bf82c189 3119 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3120 goto err_out_free_res_3;
1da177e4
LT		 3121 }
3122 }
3123
1da177e4 3124 /* ioremap MMIO region */
bcf0bf90 3125 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3126 if (!ioaddr) {
bf82c189 3127 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3128 rc = -EIO;
87aeec76 3129 goto err_out_free_res_3;
1da177e4
LT		 3130 }
3131
4300e8c7
DM		 3132 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3133 if (!tp->pcie_cap)
3134 netif_info(tp, probe, dev, "no PCI Express capability\n");
3135
d78ad8cb 3136 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3137
3138 /* Soft reset the chip. */
3139 RTL_W8(ChipCmd, CmdReset);
3140
3141 /* Check that the chip has finished the reset. */
07d3f51f 3142 for (i = 0; i < 100; i++) {
1da177e4
LT		 3143 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3144 break;
b518fa8e 3145 msleep_interruptible(1);
1da177e4
LT		 3146 }
3147
d78ad8cb
KW		 3148 RTL_W16(IntrStatus, 0xffff);
3149
ca52efd5 3150 pci_set_master(pdev);
3151
1da177e4
LT		 3152 /* Identify chip attached to board */
3153 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3154
7a8fc77b
FR		 3155 /*
3156 * Pretend we are using VLANs; This bypasses a nasty bug where
3157 * Interrupts stop flowing on high load on 8110SCd controllers.
3158 */
3159 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3160 tp->cp_cmd |= RxVlan;
3161
c0e45c1c 3162 rtl_init_mdio_ops(tp);
065c27c1 3163 rtl_init_pll_power_ops(tp);
c0e45c1c 3164
f21b75e9
JD		 3165 /* Use appropriate default if unknown */
3166 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3167 netif_notice(tp, probe, dev,
3168 "unknown MAC, using family default\n");
f21b75e9
JD		 3169 tp->mac_version = cfg->default_ver;
3170 }
3171
1da177e4 3172 rtl8169_print_mac_version(tp);
1da177e4 3173
cee60c37 3174 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3175 if (tp->mac_version == rtl_chip_info[i].mac_version)
3176 break;
3177 }
cee60c37 3178 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3179 dev_err(&pdev->dev,
3180 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3181 goto err_out_msi_4;
1da177e4
LT		 3182 }
3183 tp->chipset = i;
3184
5d06a99f
FR		 3185 RTL_W8(Cfg9346, Cfg9346_Unlock);
3186 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3187 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3188 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3189 tp->features |= RTL_FEATURE_WOL;
3190 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3191 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3192 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3193 RTL_W8(Cfg9346, Cfg9346_Lock);
3194
66ec5d4f
FR		 3195 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3196 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3197 tp->set_speed = rtl8169_set_speed_tbi;
3198 tp->get_settings = rtl8169_gset_tbi;
3199 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3200 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3201 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3202 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3203
64e4bfb4 3204 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3205 } else {
3206 tp->set_speed = rtl8169_set_speed_xmii;
3207 tp->get_settings = rtl8169_gset_xmii;
3208 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3209 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3210 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3211 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3212 }
3213
df58ef51
FR		 3214 spin_lock_init(&tp->lock);
3215
738e1e69
PV		 3216 tp->mmio_addr = ioaddr;
3217
7bf6bf48 3218 /* Get MAC address */
1da177e4
LT		 3219 for (i = 0; i < MAC_ADDR_LEN; i++)
3220 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3221 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3222
1da177e4 3223 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3224 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3225 dev->irq = pdev->irq;
3226 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3227
bea3348e 3228 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3229
7a8fc77b 3230 dev->features |= NETIF_F_HW_VLAN_TX_RX | NETIF_F_GRO;
1da177e4
LT		 3231
3232 tp->intr_mask = 0xffff;
0e485150
FR		 3233 tp->hw_start = cfg->hw_start;
3234 tp->intr_event = cfg->intr_event;
3235 tp->napi_event = cfg->napi_event;
1da177e4 3236
2efa53f3
FR		 3237 init_timer(&tp->timer);
3238 tp->timer.data = (unsigned long) dev;
3239 tp->timer.function = rtl8169_phy_timer;
3240
1da177e4 3241 rc = register_netdev(dev);
4ff96fa6 3242 if (rc < 0)
87aeec76 3243 goto err_out_msi_4;
1da177e4
LT		 3244
3245 pci_set_drvdata(pdev, dev);
3246
bf82c189
JP		 3247 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3248 rtl_chip_info[tp->chipset].name,
3249 dev->base_addr, dev->dev_addr,
3250 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3251
e6de30d6 3252 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3253 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
b646d900 3254 rtl8168_driver_start(tp);
e6de30d6 3255 }
b646d900 3256
8b76ab39 3257 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3258
f3ec4f87
AS		 3259 if (pci_dev_run_wake(pdev))
3260 pm_runtime_put_noidle(&pdev->dev);
e1759441 3261
0d672e9f
IV		 3262 netif_carrier_off(dev);
3263
4ff96fa6
FR		 3264out:
3265 return rc;
1da177e4 3266
87aeec76 3267err_out_msi_4:
fbac58fc 3268 rtl_disable_msi(pdev, tp);
4ff96fa6 3269 iounmap(ioaddr);
87aeec76 3270err_out_free_res_3:
4ff96fa6 3271 pci_release_regions(pdev);
87aeec76 3272err_out_mwi_2:
4ff96fa6 3273 pci_clear_mwi(pdev);
4ff96fa6
FR		 3274 pci_disable_device(pdev);
3275err_out_free_dev_1:
3276 free_netdev(dev);
3277 goto out;
1da177e4
LT		 3278}
3279
07d3f51f 3280static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3281{
3282 struct net_device *dev = pci_get_drvdata(pdev);
3283 struct rtl8169_private *tp = netdev_priv(dev);
3284
e6de30d6 3285 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3286 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
b646d900 3287 rtl8168_driver_stop(tp);
e6de30d6 3288 }
b646d900 3289
23f333a2 3290 cancel_delayed_work_sync(&tp->task);
eb2a021c 3291
f1e02ed1 3292 rtl_release_firmware(tp);
3293
1da177e4 3294 unregister_netdev(dev);
cc098dc7 3295
f3ec4f87
AS		 3296 if (pci_dev_run_wake(pdev))
3297 pm_runtime_get_noresume(&pdev->dev);
e1759441 3298
cc098dc7
IV		 3299 /* restore original MAC address */
3300 rtl_rar_set(tp, dev->perm_addr);
3301
fbac58fc 3302 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3303 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3304 pci_set_drvdata(pdev, NULL);
3305}
3306
1da177e4
LT		 3307static int rtl8169_open(struct net_device *dev)
3308{
3309 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3310 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3311 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3312 int retval = -ENOMEM;
1da177e4 3313
e1759441 3314 pm_runtime_get_sync(&pdev->dev);
1da177e4 3315
1da177e4
LT		 3316 /*
3317 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3318 * dma_alloc_coherent provides more.
1da177e4 3319 */
82553bb6
SG		 3320 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3321 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3322 if (!tp->TxDescArray)
e1759441 3323 goto err_pm_runtime_put;
1da177e4 3324
82553bb6
SG		 3325 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3326 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3327 if (!tp->RxDescArray)
99f252b0 3328 goto err_free_tx_0;
1da177e4
LT		 3329
3330 retval = rtl8169_init_ring(dev);
3331 if (retval < 0)
99f252b0 3332 goto err_free_rx_1;
1da177e4 3333
c4028958 3334 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3335
99f252b0
FR		 3336 smp_mb();
3337
fbac58fc
FR		 3338 retval = request_irq(dev->irq, rtl8169_interrupt,
3339 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3340 dev->name, dev);
3341 if (retval < 0)
3342 goto err_release_ring_2;
3343
bea3348e 3344 napi_enable(&tp->napi);
bea3348e 3345
eee3a96c 3346 rtl8169_init_phy(dev, tp);
3347
7a8fc77b 3348 rtl8169_vlan_mode(dev);
eee3a96c 3349
065c27c1 3350 rtl_pll_power_up(tp);
3351
07ce4064 3352 rtl_hw_start(dev);
1da177e4
LT		 3353
3354 rtl8169_request_timer(dev);
3355
e1759441
RW		 3356 tp->saved_wolopts = 0;
3357 pm_runtime_put_noidle(&pdev->dev);
3358
eee3a96c 3359 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3360out:
3361 return retval;
3362
99f252b0
FR		 3363err_release_ring_2:
3364 rtl8169_rx_clear(tp);
3365err_free_rx_1:
82553bb6
SG		 3366 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3367 tp->RxPhyAddr);
e1759441 3368 tp->RxDescArray = NULL;
99f252b0 3369err_free_tx_0:
82553bb6
SG		 3370 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3371 tp->TxPhyAddr);
e1759441
RW		 3372 tp->TxDescArray = NULL;
3373err_pm_runtime_put:
3374 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3375 goto out;
3376}
3377
e6de30d6 3378static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3379{
e6de30d6 3380 void __iomem *ioaddr = tp->mmio_addr;
3381
1da177e4
LT		 3382 /* Disable interrupts */
3383 rtl8169_irq_mask_and_ack(ioaddr);
3384
5d2e1957
HW		 3385 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3386 tp->mac_version == RTL_GIGA_MAC_VER_28) {
e6de30d6 3387 while (RTL_R8(TxPoll) & NPQ)
3388 udelay(20);
3389
3390 }
3391
1da177e4
LT		 3392 /* Reset the chipset */
3393 RTL_W8(ChipCmd, CmdReset);
3394
3395 /* PCI commit */
3396 RTL_R8(ChipCmd);
3397}
3398
7f796d83 3399static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3400{
3401 void __iomem *ioaddr = tp->mmio_addr;
3402 u32 cfg = rtl8169_rx_config;
3403
3404 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3405 RTL_W32(RxConfig, cfg);
3406
3407 /* Set DMA burst size and Interframe Gap Time */
3408 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3409 (InterFrameGap << TxInterFrameGapShift));
3410}
3411
07ce4064 3412static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3413{
3414 struct rtl8169_private *tp = netdev_priv(dev);
3415 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3416 unsigned int i;
1da177e4
LT		 3417
3418 /* Soft reset the chip. */
3419 RTL_W8(ChipCmd, CmdReset);
3420
3421 /* Check that the chip has finished the reset. */
07d3f51f 3422 for (i = 0; i < 100; i++) {
1da177e4
LT		 3423 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3424 break;
b518fa8e 3425 msleep_interruptible(1);
1da177e4
LT		 3426 }
3427
07ce4064
FR		 3428 tp->hw_start(dev);
3429
07ce4064
FR		 3430 netif_start_queue(dev);
3431}
3432
3433
7f796d83
FR		 3434static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3435 void __iomem *ioaddr)
3436{
3437 /*
3438 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3439 * register to be written before TxDescAddrLow to work.
3440 * Switching from MMIO to I/O access fixes the issue as well.
3441 */
3442 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3443 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3444 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3445 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3446}
3447
3448static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3449{
3450 u16 cmd;
3451
3452 cmd = RTL_R16(CPlusCmd);
3453 RTL_W16(CPlusCmd, cmd);
3454 return cmd;
3455}
3456
fdd7b4c3 3457static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3458{
3459 /* Low hurts. Let's disable the filtering. */
207d6e87 3460 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3461}
3462
6dccd16b
FR		 3463static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3464{
350f7596 3465 static const struct {
6dccd16b
FR		 3466 u32 mac_version;
3467 u32 clk;
3468 u32 val;
3469 } cfg2_info [] = {
3470 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3471 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3472 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3473 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3474 }, *p = cfg2_info;
3475 unsigned int i;
3476 u32 clk;
3477
3478 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3479 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3480 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3481 RTL_W32(0x7c, p->val);
3482 break;
3483 }
3484 }
3485}
3486
07ce4064
FR		 3487static void rtl_hw_start_8169(struct net_device *dev)
3488{
3489 struct rtl8169_private *tp = netdev_priv(dev);
3490 void __iomem *ioaddr = tp->mmio_addr;
3491 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3492
9cb427b6
FR		 3493 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3494 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3495 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3496 }
3497
1da177e4 3498 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3499 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3500 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3501 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3502 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3503 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3504
f0298f81 3505 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3506
6f0333b8 3507 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3508
c946b304
FR		 3509 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3510 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3511 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3512 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3513 rtl_set_rx_tx_config_registers(tp);
1da177e4 3514
7f796d83 3515 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3516
bcf0bf90
FR		 3517 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3518 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3519 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3520 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3521 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3522 }
3523
bcf0bf90
FR		 3524 RTL_W16(CPlusCmd, tp->cp_cmd);
3525
6dccd16b
FR		 3526 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3527
1da177e4
LT		 3528 /*
3529 * Undocumented corner. Supposedly:
3530 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3531 */
3532 RTL_W16(IntrMitigate, 0x0000);
3533
7f796d83 3534 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3535
c946b304
FR		 3536 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3537 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3538 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3539 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3540 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3541 rtl_set_rx_tx_config_registers(tp);
3542 }
3543
1da177e4 3544 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3545
3546 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3547 RTL_R8(IntrMask);
1da177e4
LT		 3548
3549 RTL_W32(RxMissed, 0);
3550
07ce4064 3551 rtl_set_rx_mode(dev);
1da177e4
LT		 3552
3553 /* no early-rx interrupts */
3554 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3555
3556 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3557 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3558}
1da177e4 3559
9c14ceaf 3560static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3561{
9c14ceaf
FR		 3562 struct net_device *dev = pci_get_drvdata(pdev);
3563 struct rtl8169_private *tp = netdev_priv(dev);
3564 int cap = tp->pcie_cap;
3565
3566 if (cap) {
3567 u16 ctl;
458a9f61 3568
9c14ceaf
FR		 3569 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3570 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3571 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3572 }
458a9f61
FR		 3573}
3574
650e8d5d 3575static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3576{
3577 u32 csi;
3578
3579 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3580 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3581}
3582
e6de30d6 3583static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3584{
3585 rtl_csi_access_enable(ioaddr, 0x17000000);
3586}
3587
650e8d5d 3588static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3589{
3590 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3591}
3592
3593struct ephy_info {
3594 unsigned int offset;
3595 u16 mask;
3596 u16 bits;
3597};
3598
350f7596 3599static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3600{
3601 u16 w;
3602
3603 while (len-- > 0) {
3604 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3605 rtl_ephy_write(ioaddr, e->offset, w);
3606 e++;
3607 }
3608}
3609
b726e493
FR		 3610static void rtl_disable_clock_request(struct pci_dev *pdev)
3611{
3612 struct net_device *dev = pci_get_drvdata(pdev);
3613 struct rtl8169_private *tp = netdev_priv(dev);
3614 int cap = tp->pcie_cap;
3615
3616 if (cap) {
3617 u16 ctl;
3618
3619 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3620 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3621 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3622 }
3623}
3624
e6de30d6 3625static void rtl_enable_clock_request(struct pci_dev *pdev)
3626{
3627 struct net_device *dev = pci_get_drvdata(pdev);
3628 struct rtl8169_private *tp = netdev_priv(dev);
3629 int cap = tp->pcie_cap;
3630
3631 if (cap) {
3632 u16 ctl;
3633
3634 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3635 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3636 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3637 }
3638}
3639
b726e493
FR		 3640#define R8168_CPCMD_QUIRK_MASK (\
3641 EnableBist | \
3642 Mac_dbgo_oe | \
3643 Force_half_dup | \
3644 Force_rxflow_en | \
3645 Force_txflow_en | \
3646 Cxpl_dbg_sel | \
3647 ASF | \
3648 PktCntrDisable | \
3649 Mac_dbgo_sel)
3650
219a1e9d
FR		 3651static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3652{
b726e493
FR		 3653 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3654
3655 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3656
2e68ae44
FR		 3657 rtl_tx_performance_tweak(pdev,
3658 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3659}
3660
3661static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3662{
3663 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3664
f0298f81 3665 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3666
3667 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3668}
3669
3670static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3671{
b726e493
FR		 3672 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3673
3674 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3675
219a1e9d 3676 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3677
3678 rtl_disable_clock_request(pdev);
3679
3680 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3681}
3682
ef3386f0 3683static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3684{
350f7596 3685 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3686 { 0x01, 0, 0x0001 },
3687 { 0x02, 0x0800, 0x1000 },
3688 { 0x03, 0, 0x0042 },
3689 { 0x06, 0x0080, 0x0000 },
3690 { 0x07, 0, 0x2000 }
3691 };
3692
650e8d5d 3693 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3694
3695 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3696
219a1e9d
FR		 3697 __rtl_hw_start_8168cp(ioaddr, pdev);
3698}
3699
ef3386f0
FR		 3700static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3701{
650e8d5d 3702 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3703
3704 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3705
3706 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3707
3708 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3709}
3710
7f3e3d3a
FR		 3711static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3712{
650e8d5d 3713 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3714
3715 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3716
3717 /* Magic. */
3718 RTL_W8(DBG_REG, 0x20);
3719
f0298f81 3720 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3721
3722 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3723
3724 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3725}
3726
219a1e9d
FR		 3727static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3728{
350f7596 3729 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3730 { 0x02, 0x0800, 0x1000 },
3731 { 0x03, 0, 0x0002 },
3732 { 0x06, 0x0080, 0x0000 }
3733 };
3734
650e8d5d 3735 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3736
3737 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3738
3739 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3740
219a1e9d
FR		 3741 __rtl_hw_start_8168cp(ioaddr, pdev);
3742}
3743
3744static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3745{
350f7596 3746 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3747 { 0x01, 0, 0x0001 },
3748 { 0x03, 0x0400, 0x0220 }
3749 };
3750
650e8d5d 3751 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3752
3753 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3754
219a1e9d
FR		 3755 __rtl_hw_start_8168cp(ioaddr, pdev);
3756}
3757
197ff761
FR		 3758static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3759{
3760 rtl_hw_start_8168c_2(ioaddr, pdev);
3761}
3762
6fb07058
FR		 3763static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3764{
650e8d5d 3765 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 3766
3767 __rtl_hw_start_8168cp(ioaddr, pdev);
3768}
3769
5b538df9
FR		 3770static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3771{
650e8d5d 3772 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 3773
3774 rtl_disable_clock_request(pdev);
3775
f0298f81 3776 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 3777
3778 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3779
3780 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3781}
3782
e6de30d6 3783static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3784{
3785 static const struct ephy_info e_info_8168d_4[] = {
3786 { 0x0b, ~0, 0x48 },
3787 { 0x19, 0x20, 0x50 },
3788 { 0x0c, ~0, 0x20 }
3789 };
3790 int i;
3791
3792 rtl_csi_access_enable_1(ioaddr);
3793
3794 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3795
3796 RTL_W8(MaxTxPacketSize, TxPacketMax);
3797
3798 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3799 const struct ephy_info *e = e_info_8168d_4 + i;
3800 u16 w;
3801
3802 w = rtl_ephy_read(ioaddr, e->offset);
3803 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3804 }
3805
3806 rtl_enable_clock_request(pdev);
3807}
3808
07ce4064
FR		 3809static void rtl_hw_start_8168(struct net_device *dev)
3810{
2dd99530
FR		 3811 struct rtl8169_private *tp = netdev_priv(dev);
3812 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3813 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3814
3815 RTL_W8(Cfg9346, Cfg9346_Unlock);
3816
f0298f81 3817 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 3818
6f0333b8 3819 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 3820
0e485150 3821 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3822
3823 RTL_W16(CPlusCmd, tp->cp_cmd);
3824
0e485150 3825 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3826
0e485150 3827 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 3828 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3829 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 3830 tp->intr_event |= RxFIFOOver | PCSTimeout;
3831 tp->intr_event &= ~RxOverflow;
3832 }
3833
3834 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3835
b8363901
FR		 3836 rtl_set_rx_mode(dev);
3837
3838 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3839 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3840
3841 RTL_R8(IntrMask);
3842
219a1e9d
FR		 3843 switch (tp->mac_version) {
3844 case RTL_GIGA_MAC_VER_11:
3845 rtl_hw_start_8168bb(ioaddr, pdev);
3846 break;
3847
3848 case RTL_GIGA_MAC_VER_12:
3849 case RTL_GIGA_MAC_VER_17:
3850 rtl_hw_start_8168bef(ioaddr, pdev);
3851 break;
3852
3853 case RTL_GIGA_MAC_VER_18:
ef3386f0 3854 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3855 break;
3856
3857 case RTL_GIGA_MAC_VER_19:
3858 rtl_hw_start_8168c_1(ioaddr, pdev);
3859 break;
3860
3861 case RTL_GIGA_MAC_VER_20:
3862 rtl_hw_start_8168c_2(ioaddr, pdev);
3863 break;
3864
197ff761
FR		 3865 case RTL_GIGA_MAC_VER_21:
3866 rtl_hw_start_8168c_3(ioaddr, pdev);
3867 break;
3868
6fb07058
FR		 3869 case RTL_GIGA_MAC_VER_22:
3870 rtl_hw_start_8168c_4(ioaddr, pdev);
3871 break;
3872
ef3386f0
FR		 3873 case RTL_GIGA_MAC_VER_23:
3874 rtl_hw_start_8168cp_2(ioaddr, pdev);
3875 break;
3876
7f3e3d3a
FR		 3877 case RTL_GIGA_MAC_VER_24:
3878 rtl_hw_start_8168cp_3(ioaddr, pdev);
3879 break;
3880
5b538df9 3881 case RTL_GIGA_MAC_VER_25:
daf9df6d 3882 case RTL_GIGA_MAC_VER_26:
3883 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3884 rtl_hw_start_8168d(ioaddr, pdev);
3885 break;
3886
e6de30d6 3887 case RTL_GIGA_MAC_VER_28:
3888 rtl_hw_start_8168d_4(ioaddr, pdev);
3889 break;
3890
219a1e9d
FR		 3891 default:
3892 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3893 dev->name, tp->mac_version);
3894 break;
3895 }
2dd99530 3896
0e485150
FR		 3897 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3898
b8363901
FR		 3899 RTL_W8(Cfg9346, Cfg9346_Lock);
3900
2dd99530 3901 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3902
0e485150 3903 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3904}
1da177e4 3905
2857ffb7
FR		 3906#define R810X_CPCMD_QUIRK_MASK (\
3907 EnableBist | \
3908 Mac_dbgo_oe | \
3909 Force_half_dup | \
5edcc537 3910 Force_rxflow_en | \
2857ffb7
FR		 3911 Force_txflow_en | \
3912 Cxpl_dbg_sel | \
3913 ASF | \
3914 PktCntrDisable | \
d24e9aaf 3915 Mac_dbgo_sel)
2857ffb7
FR		 3916
3917static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3918{
350f7596 3919 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3920 { 0x01, 0, 0x6e65 },
3921 { 0x02, 0, 0x091f },
3922 { 0x03, 0, 0xc2f9 },
3923 { 0x06, 0, 0xafb5 },
3924 { 0x07, 0, 0x0e00 },
3925 { 0x19, 0, 0xec80 },
3926 { 0x01, 0, 0x2e65 },
3927 { 0x01, 0, 0x6e65 }
3928 };
3929 u8 cfg1;
3930
650e8d5d 3931 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 3932
3933 RTL_W8(DBG_REG, FIX_NAK_1);
3934
3935 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3936
3937 RTL_W8(Config1,
3938 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3939 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3940
3941 cfg1 = RTL_R8(Config1);
3942 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3943 RTL_W8(Config1, cfg1 & ~LEDS0);
3944
2857ffb7
FR		 3945 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3946}
3947
3948static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3949{
650e8d5d 3950 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 3951
3952 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3953
3954 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3955 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 3956}
3957
3958static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3959{
3960 rtl_hw_start_8102e_2(ioaddr, pdev);
3961
3962 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3963}
3964
5a5e4443
HW		 3965static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3966{
3967 static const struct ephy_info e_info_8105e_1[] = {
3968 { 0x07, 0, 0x4000 },
3969 { 0x19, 0, 0x0200 },
3970 { 0x19, 0, 0x0020 },
3971 { 0x1e, 0, 0x2000 },
3972 { 0x03, 0, 0x0001 },
3973 { 0x19, 0, 0x0100 },
3974 { 0x19, 0, 0x0004 },
3975 { 0x0a, 0, 0x0020 }
3976 };
3977
3978 /* Force LAN exit from ASPM if Rx/Tx are not idel */
3979 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
3980
3981 /* disable Early Tally Counter */
3982 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
3983
3984 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
3985 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
3986
3987 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
3988}
3989
3990static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3991{
3992 rtl_hw_start_8105e_1(ioaddr, pdev);
3993 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
3994}
3995
07ce4064
FR		 3996static void rtl_hw_start_8101(struct net_device *dev)
3997{
cdf1a608
FR		 3998 struct rtl8169_private *tp = netdev_priv(dev);
3999 void __iomem *ioaddr = tp->mmio_addr;
4000 struct pci_dev *pdev = tp->pci_dev;
4001
e3cf0cc0
FR		 4002 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
4003 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 4004 int cap = tp->pcie_cap;
4005
4006 if (cap) {
4007 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4008 PCI_EXP_DEVCTL_NOSNOOP_EN);
4009 }
cdf1a608
FR		 4010 }
4011
d24e9aaf
HW		 4012 RTL_W8(Cfg9346, Cfg9346_Unlock);
4013
2857ffb7
FR		 4014 switch (tp->mac_version) {
4015 case RTL_GIGA_MAC_VER_07:
4016 rtl_hw_start_8102e_1(ioaddr, pdev);
4017 break;
4018
4019 case RTL_GIGA_MAC_VER_08:
4020 rtl_hw_start_8102e_3(ioaddr, pdev);
4021 break;
4022
4023 case RTL_GIGA_MAC_VER_09:
4024 rtl_hw_start_8102e_2(ioaddr, pdev);
4025 break;
5a5e4443
HW		 4026
4027 case RTL_GIGA_MAC_VER_29:
4028 rtl_hw_start_8105e_1(ioaddr, pdev);
4029 break;
4030 case RTL_GIGA_MAC_VER_30:
4031 rtl_hw_start_8105e_2(ioaddr, pdev);
4032 break;
cdf1a608
FR		 4033 }
4034
d24e9aaf 4035 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4036
f0298f81 4037 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4038
6f0333b8 4039 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4040
d24e9aaf 4041 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4042 RTL_W16(CPlusCmd, tp->cp_cmd);
4043
4044 RTL_W16(IntrMitigate, 0x0000);
4045
4046 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4047
4048 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4049 rtl_set_rx_tx_config_registers(tp);
4050
cdf1a608
FR		 4051 RTL_R8(IntrMask);
4052
cdf1a608
FR		 4053 rtl_set_rx_mode(dev);
4054
4055 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4056
0e485150 4057 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4058}
4059
4060static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4061{
1da177e4
LT		 4062 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4063 return -EINVAL;
4064
4065 dev->mtu = new_mtu;
323bb685 4066 return 0;
1da177e4
LT		 4067}
4068
4069static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4070{
95e0918d 4071 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4072 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4073}
4074
6f0333b8
ED		 4075static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4076 void **data_buff, struct RxDesc *desc)
1da177e4 4077{
48addcc9 4078 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4079 DMA_FROM_DEVICE);
48addcc9 4080
6f0333b8
ED		 4081 kfree(*data_buff);
4082 *data_buff = NULL;
1da177e4
LT		 4083 rtl8169_make_unusable_by_asic(desc);
4084}
4085
4086static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4087{
4088 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4089
4090 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4091}
4092
4093static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4094 u32 rx_buf_sz)
4095{
4096 desc->addr = cpu_to_le64(mapping);
4097 wmb();
4098 rtl8169_mark_to_asic(desc, rx_buf_sz);
4099}
4100
6f0333b8
ED		 4101static inline void *rtl8169_align(void *data)
4102{
4103 return (void *)ALIGN((long)data, 16);
4104}
4105
0ecbe1ca
SG		 4106static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4107 struct RxDesc *desc)
1da177e4 4108{
6f0333b8 4109 void *data;
1da177e4 4110 dma_addr_t mapping;
48addcc9 4111 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4112 struct net_device *dev = tp->dev;
6f0333b8 4113 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4114
6f0333b8
ED		 4115 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4116 if (!data)
4117 return NULL;
e9f63f30 4118
6f0333b8
ED		 4119 if (rtl8169_align(data) != data) {
4120 kfree(data);
4121 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4122 if (!data)
4123 return NULL;
4124 }
3eafe507 4125
48addcc9 4126 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4127 DMA_FROM_DEVICE);
d827d86b
SG		 4128 if (unlikely(dma_mapping_error(d, mapping))) {
4129 if (net_ratelimit())
4130 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4131 goto err_out;
d827d86b 4132 }
1da177e4
LT		 4133
4134 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4135 return data;
3eafe507
SG		 4136
4137err_out:
4138 kfree(data);
4139 return NULL;
1da177e4
LT		 4140}
4141
4142static void rtl8169_rx_clear(struct rtl8169_private *tp)
4143{
07d3f51f 4144 unsigned int i;
1da177e4
LT		 4145
4146 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4147 if (tp->Rx_databuff[i]) {
4148 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4149 tp->RxDescArray + i);
4150 }
4151 }
4152}
4153
0ecbe1ca 4154static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4155{
0ecbe1ca
SG		 4156 desc->opts1 |= cpu_to_le32(RingEnd);
4157}
5b0384f4 4158
0ecbe1ca
SG		 4159static int rtl8169_rx_fill(struct rtl8169_private *tp)
4160{
4161 unsigned int i;
1da177e4 4162
0ecbe1ca
SG		 4163 for (i = 0; i < NUM_RX_DESC; i++) {
4164 void *data;
4ae47c2d 4165
6f0333b8 4166 if (tp->Rx_databuff[i])
1da177e4 4167 continue;
bcf0bf90 4168
0ecbe1ca 4169 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4170 if (!data) {
4171 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4172 goto err_out;
6f0333b8
ED		 4173 }
4174 tp->Rx_databuff[i] = data;
1da177e4 4175 }
1da177e4 4176
0ecbe1ca
SG		 4177 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4178 return 0;
4179
4180err_out:
4181 rtl8169_rx_clear(tp);
4182 return -ENOMEM;
1da177e4
LT		 4183}
4184
4185static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4186{
4187 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4188}
4189
4190static int rtl8169_init_ring(struct net_device *dev)
4191{
4192 struct rtl8169_private *tp = netdev_priv(dev);
4193
4194 rtl8169_init_ring_indexes(tp);
4195
4196 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4197 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4198
0ecbe1ca 4199 return rtl8169_rx_fill(tp);
1da177e4
LT		 4200}
4201
48addcc9 4202static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4203 struct TxDesc *desc)
4204{
4205 unsigned int len = tx_skb->len;
4206
48addcc9
SG		 4207 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4208
1da177e4
LT		 4209 desc->opts1 = 0x00;
4210 desc->opts2 = 0x00;
4211 desc->addr = 0x00;
4212 tx_skb->len = 0;
4213}
4214
3eafe507
SG		 4215static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4216 unsigned int n)
1da177e4
LT		 4217{
4218 unsigned int i;
4219
3eafe507
SG		 4220 for (i = 0; i < n; i++) {
4221 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4222 struct ring_info *tx_skb = tp->tx_skb + entry;
4223 unsigned int len = tx_skb->len;
4224
4225 if (len) {
4226 struct sk_buff *skb = tx_skb->skb;
4227
48addcc9 4228 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4229 tp->TxDescArray + entry);
4230 if (skb) {
cac4b22f 4231 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4232 dev_kfree_skb(skb);
4233 tx_skb->skb = NULL;
4234 }
1da177e4
LT		 4235 }
4236 }
3eafe507
SG		 4237}
4238
4239static void rtl8169_tx_clear(struct rtl8169_private *tp)
4240{
4241 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4242 tp->cur_tx = tp->dirty_tx = 0;
4243}
4244
c4028958 4245static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4246{
4247 struct rtl8169_private *tp = netdev_priv(dev);
4248
c4028958 4249 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4250 schedule_delayed_work(&tp->task, 4);
4251}
4252
4253static void rtl8169_wait_for_quiescence(struct net_device *dev)
4254{
4255 struct rtl8169_private *tp = netdev_priv(dev);
4256 void __iomem *ioaddr = tp->mmio_addr;
4257
4258 synchronize_irq(dev->irq);
4259
4260 /* Wait for any pending NAPI task to complete */
bea3348e 4261 napi_disable(&tp->napi);
1da177e4
LT		 4262
4263 rtl8169_irq_mask_and_ack(ioaddr);
4264
d1d08d12
DM		 4265 tp->intr_mask = 0xffff;
4266 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4267 napi_enable(&tp->napi);
1da177e4
LT		 4268}
4269
c4028958 4270static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4271{
c4028958
DH		 4272 struct rtl8169_private *tp =
4273 container_of(work, struct rtl8169_private, task.work);
4274 struct net_device *dev = tp->dev;
1da177e4
LT		 4275 int ret;
4276
eb2a021c
FR		 4277 rtnl_lock();
4278
4279 if (!netif_running(dev))
4280 goto out_unlock;
4281
4282 rtl8169_wait_for_quiescence(dev);
4283 rtl8169_close(dev);
1da177e4
LT		 4284
4285 ret = rtl8169_open(dev);
4286 if (unlikely(ret < 0)) {
bf82c189
JP		 4287 if (net_ratelimit())
4288 netif_err(tp, drv, dev,
4289 "reinit failure (status = %d). Rescheduling\n",
4290 ret);
1da177e4
LT		 4291 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4292 }
eb2a021c
FR		 4293
4294out_unlock:
4295 rtnl_unlock();
1da177e4
LT		 4296}
4297
c4028958 4298static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4299{
c4028958
DH		 4300 struct rtl8169_private *tp =
4301 container_of(work, struct rtl8169_private, task.work);
4302 struct net_device *dev = tp->dev;
1da177e4 4303
eb2a021c
FR		 4304 rtnl_lock();
4305
1da177e4 4306 if (!netif_running(dev))
eb2a021c 4307 goto out_unlock;
1da177e4
LT		 4308
4309 rtl8169_wait_for_quiescence(dev);
4310
bea3348e 4311 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4312 rtl8169_tx_clear(tp);
4313
4314 if (tp->dirty_rx == tp->cur_rx) {
4315 rtl8169_init_ring_indexes(tp);
07ce4064 4316 rtl_hw_start(dev);
1da177e4 4317 netif_wake_queue(dev);
cebf8cc7 4318 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4319 } else {
bf82c189
JP		 4320 if (net_ratelimit())
4321 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4322 rtl8169_schedule_work(dev, rtl8169_reset_task);
4323 }
eb2a021c
FR		 4324
4325out_unlock:
4326 rtnl_unlock();
1da177e4
LT		 4327}
4328
4329static void rtl8169_tx_timeout(struct net_device *dev)
4330{
4331 struct rtl8169_private *tp = netdev_priv(dev);
4332
e6de30d6 4333 rtl8169_hw_reset(tp);
1da177e4
LT		 4334
4335 /* Let's wait a bit while any (async) irq lands on */
4336 rtl8169_schedule_work(dev, rtl8169_reset_task);
4337}
4338
4339static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4340 u32 opts1)
4341{
4342 struct skb_shared_info *info = skb_shinfo(skb);
4343 unsigned int cur_frag, entry;
a6343afb 4344 struct TxDesc * uninitialized_var(txd);
48addcc9 4345 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4346
4347 entry = tp->cur_tx;
4348 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4349 skb_frag_t *frag = info->frags + cur_frag;
4350 dma_addr_t mapping;
4351 u32 status, len;
4352 void *addr;
4353
4354 entry = (entry + 1) % NUM_TX_DESC;
4355
4356 txd = tp->TxDescArray + entry;
4357 len = frag->size;
4358 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4359 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4360 if (unlikely(dma_mapping_error(d, mapping))) {
4361 if (net_ratelimit())
4362 netif_err(tp, drv, tp->dev,
4363 "Failed to map TX fragments DMA!\n");
3eafe507 4364 goto err_out;
d827d86b 4365 }
1da177e4
LT		 4366
4367 /* anti gcc 2.95.3 bugware (sic) */
4368 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4369
4370 txd->opts1 = cpu_to_le32(status);
4371 txd->addr = cpu_to_le64(mapping);
4372
4373 tp->tx_skb[entry].len = len;
4374 }
4375
4376 if (cur_frag) {
4377 tp->tx_skb[entry].skb = skb;
4378 txd->opts1 |= cpu_to_le32(LastFrag);
4379 }
4380
4381 return cur_frag;
3eafe507
SG		 4382
4383err_out:
4384 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4385 return -EIO;
1da177e4
LT		 4386}
4387
4388static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4389{
4390 if (dev->features & NETIF_F_TSO) {
7967168c 4391 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4392
4393 if (mss)
4394 return LargeSend | ((mss & MSSMask) << MSSShift);
4395 }
84fa7933 4396 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4397 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4398
4399 if (ip->protocol == IPPROTO_TCP)
4400 return IPCS | TCPCS;
4401 else if (ip->protocol == IPPROTO_UDP)
4402 return IPCS | UDPCS;
4403 WARN_ON(1); /* we need a WARN() */
4404 }
4405 return 0;
4406}
4407
61357325
SH		 4408static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4409 struct net_device *dev)
1da177e4
LT		 4410{
4411 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4412 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4413 struct TxDesc *txd = tp->TxDescArray + entry;
4414 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4415 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4416 dma_addr_t mapping;
4417 u32 status, len;
4418 u32 opts1;
3eafe507 4419 int frags;
5b0384f4 4420
1da177e4 4421 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4422 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4423 goto err_stop_0;
1da177e4
LT		 4424 }
4425
4426 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4427 goto err_stop_0;
4428
4429 len = skb_headlen(skb);
48addcc9 4430 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4431 if (unlikely(dma_mapping_error(d, mapping))) {
4432 if (net_ratelimit())
4433 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4434 goto err_dma_0;
d827d86b 4435 }
3eafe507
SG		 4436
4437 tp->tx_skb[entry].len = len;
4438 txd->addr = cpu_to_le64(mapping);
4439 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
1da177e4
LT		 4440
4441 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4442
4443 frags = rtl8169_xmit_frags(tp, skb, opts1);
3eafe507
SG		 4444 if (frags < 0)
4445 goto err_dma_1;
4446 else if (frags)
1da177e4 4447 opts1 |= FirstFrag;
3eafe507 4448 else {
1da177e4
LT		 4449 opts1 |= FirstFrag | LastFrag;
4450 tp->tx_skb[entry].skb = skb;
4451 }
4452
1da177e4
LT		 4453 wmb();
4454
4455 /* anti gcc 2.95.3 bugware (sic) */
4456 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4457 txd->opts1 = cpu_to_le32(status);
4458
1da177e4
LT		 4459 tp->cur_tx += frags + 1;
4460
4c020a96 4461 wmb();
1da177e4 4462
275391a4 4463 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4464
4465 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4466 netif_stop_queue(dev);
4467 smp_rmb();
4468 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4469 netif_wake_queue(dev);
4470 }
4471
61357325 4472 return NETDEV_TX_OK;
1da177e4 4473
3eafe507 4474err_dma_1:
48addcc9 4475 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4476err_dma_0:
4477 dev_kfree_skb(skb);
4478 dev->stats.tx_dropped++;
4479 return NETDEV_TX_OK;
4480
4481err_stop_0:
1da177e4 4482 netif_stop_queue(dev);
cebf8cc7 4483 dev->stats.tx_dropped++;
61357325 4484 return NETDEV_TX_BUSY;
1da177e4
LT		 4485}
4486
4487static void rtl8169_pcierr_interrupt(struct net_device *dev)
4488{
4489 struct rtl8169_private *tp = netdev_priv(dev);
4490 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4491 u16 pci_status, pci_cmd;
4492
4493 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4494 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4495
bf82c189
JP		 4496 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4497 pci_cmd, pci_status);
1da177e4
LT		 4498
4499 /*
4500 * The recovery sequence below admits a very elaborated explanation:
4501 * - it seems to work;
d03902b8
FR		 4502 * - I did not see what else could be done;
4503 * - it makes iop3xx happy.
1da177e4
LT		 4504 *
4505 * Feel free to adjust to your needs.
4506 */
a27993f3 4507 if (pdev->broken_parity_status)
d03902b8
FR		 4508 pci_cmd &= ~PCI_COMMAND_PARITY;
4509 else
4510 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4511
4512 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4513
4514 pci_write_config_word(pdev, PCI_STATUS,
4515 pci_status & (PCI_STATUS_DETECTED_PARITY |
4516 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4517 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4518
4519 /* The infamous DAC f*ckup only happens at boot time */
4520 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4521 void __iomem *ioaddr = tp->mmio_addr;
4522
bf82c189 4523 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4524 tp->cp_cmd &= ~PCIDAC;
4525 RTL_W16(CPlusCmd, tp->cp_cmd);
4526 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4527 }
4528
e6de30d6 4529 rtl8169_hw_reset(tp);
d03902b8
FR		 4530
4531 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4532}
4533
07d3f51f
FR		 4534static void rtl8169_tx_interrupt(struct net_device *dev,
4535 struct rtl8169_private *tp,
4536 void __iomem *ioaddr)
1da177e4
LT		 4537{
4538 unsigned int dirty_tx, tx_left;
4539
1da177e4
LT		 4540 dirty_tx = tp->dirty_tx;
4541 smp_rmb();
4542 tx_left = tp->cur_tx - dirty_tx;
4543
4544 while (tx_left > 0) {
4545 unsigned int entry = dirty_tx % NUM_TX_DESC;
4546 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4547 u32 status;
4548
4549 rmb();
4550 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4551 if (status & DescOwn)
4552 break;
4553
48addcc9
SG		 4554 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4555 tp->TxDescArray + entry);
1da177e4 4556 if (status & LastFrag) {
cac4b22f
SG		 4557 dev->stats.tx_packets++;
4558 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4559 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4560 tx_skb->skb = NULL;
4561 }
4562 dirty_tx++;
4563 tx_left--;
4564 }
4565
4566 if (tp->dirty_tx != dirty_tx) {
4567 tp->dirty_tx = dirty_tx;
4568 smp_wmb();
4569 if (netif_queue_stopped(dev) &&
4570 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4571 netif_wake_queue(dev);
4572 }
d78ae2dc
FR		 4573 /*
4574 * 8168 hack: TxPoll requests are lost when the Tx packets are
4575 * too close. Let's kick an extra TxPoll request when a burst
4576 * of start_xmit activity is detected (if it is not detected,
4577 * it is slow enough). -- FR
4578 */
4579 smp_rmb();
4580 if (tp->cur_tx != dirty_tx)
4581 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4582 }
4583}
4584
126fa4b9
FR		 4585static inline int rtl8169_fragmented_frame(u32 status)
4586{
4587 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4588}
4589
adea1ac7 4590static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4591{
1da177e4
LT		 4592 u32 status = opts1 & RxProtoMask;
4593
4594 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4595 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4596 skb->ip_summed = CHECKSUM_UNNECESSARY;
4597 else
bc8acf2c 4598 skb_checksum_none_assert(skb);
1da177e4
LT		 4599}
4600
6f0333b8
ED		 4601static struct sk_buff *rtl8169_try_rx_copy(void *data,
4602 struct rtl8169_private *tp,
4603 int pkt_size,
4604 dma_addr_t addr)
1da177e4 4605{
b449655f 4606 struct sk_buff *skb;
48addcc9 4607 struct device *d = &tp->pci_dev->dev;
b449655f 4608
6f0333b8 4609 data = rtl8169_align(data);
48addcc9 4610 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4611 prefetch(data);
4612 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4613 if (skb)
4614 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4615 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4616
6f0333b8 4617 return skb;
1da177e4
LT		 4618}
4619
630b943c
ED		 4620/*
4621 * Warning : rtl8169_rx_interrupt() might be called :
4622 * 1) from NAPI (softirq) context
4623 * (polling = 1 : we should call netif_receive_skb())
4624 * 2) from process context (rtl8169_reset_task())
4625 * (polling = 0 : we must call netif_rx() instead)
4626 */
07d3f51f
FR		 4627static int rtl8169_rx_interrupt(struct net_device *dev,
4628 struct rtl8169_private *tp,
bea3348e 4629 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4630{
4631 unsigned int cur_rx, rx_left;
6f0333b8 4632 unsigned int count;
630b943c 4633 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4634
1da177e4
LT		 4635 cur_rx = tp->cur_rx;
4636 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4637 rx_left = min(rx_left, budget);
1da177e4 4638
4dcb7d33 4639 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4640 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4641 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4642 u32 status;
4643
4644 rmb();
126fa4b9 4645 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4646
4647 if (status & DescOwn)
4648 break;
4dcb7d33 4649 if (unlikely(status & RxRES)) {
bf82c189
JP		 4650 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4651 status);
cebf8cc7 4652 dev->stats.rx_errors++;
1da177e4 4653 if (status & (RxRWT | RxRUNT))
cebf8cc7 4654 dev->stats.rx_length_errors++;
1da177e4 4655 if (status & RxCRC)
cebf8cc7 4656 dev->stats.rx_crc_errors++;
9dccf611
FR		 4657 if (status & RxFOVF) {
4658 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4659 dev->stats.rx_fifo_errors++;
9dccf611 4660 }
6f0333b8 4661 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4662 } else {
6f0333b8 4663 struct sk_buff *skb;
b449655f 4664 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4665 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4666
126fa4b9
FR		 4667 /*
4668 * The driver does not support incoming fragmented
4669 * frames. They are seen as a symptom of over-mtu
4670 * sized frames.
4671 */
4672 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4673 dev->stats.rx_dropped++;
4674 dev->stats.rx_length_errors++;
6f0333b8 4675 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4676 continue;
126fa4b9
FR		 4677 }
4678
6f0333b8
ED		 4679 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4680 tp, pkt_size, addr);
4681 rtl8169_mark_to_asic(desc, rx_buf_sz);
4682 if (!skb) {
4683 dev->stats.rx_dropped++;
4684 continue;
1da177e4
LT		 4685 }
4686
adea1ac7 4687 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4688 skb_put(skb, pkt_size);
4689 skb->protocol = eth_type_trans(skb, dev);
4690
7a8fc77b
FR		 4691 rtl8169_rx_vlan_tag(desc, skb);
4692
4693 if (likely(polling))
4694 napi_gro_receive(&tp->napi, skb);
4695 else
4696 netif_rx(skb);
1da177e4 4697
cebf8cc7
FR		 4698 dev->stats.rx_bytes += pkt_size;
4699 dev->stats.rx_packets++;
1da177e4 4700 }
6dccd16b
FR		 4701
4702 /* Work around for AMD plateform. */
95e0918d 4703 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4704 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4705 desc->opts2 = 0;
4706 cur_rx++;
4707 }
1da177e4
LT		 4708 }
4709
4710 count = cur_rx - tp->cur_rx;
4711 tp->cur_rx = cur_rx;
4712
6f0333b8 4713 tp->dirty_rx += count;
1da177e4
LT		 4714
4715 return count;
4716}
4717
07d3f51f 4718static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4719{
07d3f51f 4720 struct net_device *dev = dev_instance;
1da177e4 4721 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4722 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4723 int handled = 0;
865c652d 4724 int status;
1da177e4 4725
f11a377b
DD		 4726 /* loop handling interrupts until we have no new ones or
4727 * we hit a invalid/hotplug case.
4728 */
865c652d 4729 status = RTL_R16(IntrStatus);
f11a377b
DD		 4730 while (status && status != 0xffff) {
4731 handled = 1;
1da177e4 4732
f11a377b
DD		 4733 /* Handle all of the error cases first. These will reset
4734 * the chip, so just exit the loop.
4735 */
4736 if (unlikely(!netif_running(dev))) {
4737 rtl8169_asic_down(ioaddr);
4738 break;
4739 }
1da177e4 4740
1519e57f
FR		 4741 if (unlikely(status & RxFIFOOver)) {
4742 switch (tp->mac_version) {
4743 /* Work around for rx fifo overflow */
4744 case RTL_GIGA_MAC_VER_11:
4745 case RTL_GIGA_MAC_VER_22:
4746 case RTL_GIGA_MAC_VER_26:
4747 netif_stop_queue(dev);
4748 rtl8169_tx_timeout(dev);
4749 goto done;
f60ac8e7
FR		 4750 /* Testers needed. */
4751 case RTL_GIGA_MAC_VER_17:
4752 case RTL_GIGA_MAC_VER_19:
4753 case RTL_GIGA_MAC_VER_20:
4754 case RTL_GIGA_MAC_VER_21:
4755 case RTL_GIGA_MAC_VER_23:
4756 case RTL_GIGA_MAC_VER_24:
4757 case RTL_GIGA_MAC_VER_27:
4758 case RTL_GIGA_MAC_VER_28:
1519e57f
FR		 4759 /* Experimental science. Pktgen proof. */
4760 case RTL_GIGA_MAC_VER_12:
4761 case RTL_GIGA_MAC_VER_25:
4762 if (status == RxFIFOOver)
4763 goto done;
4764 break;
4765 default:
4766 break;
4767 }
f11a377b 4768 }
1da177e4 4769
f11a377b
DD		 4770 if (unlikely(status & SYSErr)) {
4771 rtl8169_pcierr_interrupt(dev);
4772 break;
4773 }
1da177e4 4774
f11a377b 4775 if (status & LinkChg)
e4fbce74 4776 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 4777
f11a377b
DD		 4778 /* We need to see the lastest version of tp->intr_mask to
4779 * avoid ignoring an MSI interrupt and having to wait for
4780 * another event which may never come.
4781 */
4782 smp_rmb();
4783 if (status & tp->intr_mask & tp->napi_event) {
4784 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4785 tp->intr_mask = ~tp->napi_event;
4786
4787 if (likely(napi_schedule_prep(&tp->napi)))
4788 __napi_schedule(&tp->napi);
bf82c189
JP		 4789 else
4790 netif_info(tp, intr, dev,
4791 "interrupt %04x in poll\n", status);
f11a377b 4792 }
1da177e4 4793
f11a377b
DD		 4794 /* We only get a new MSI interrupt when all active irq
4795 * sources on the chip have been acknowledged. So, ack
4796 * everything we've seen and check if new sources have become
4797 * active to avoid blocking all interrupts from the chip.
4798 */
4799 RTL_W16(IntrStatus,
4800 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4801 status = RTL_R16(IntrStatus);
865c652d 4802 }
1519e57f 4803done:
1da177e4
LT		 4804 return IRQ_RETVAL(handled);
4805}
4806
bea3348e 4807static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4808{
bea3348e
SH		 4809 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4810 struct net_device *dev = tp->dev;
1da177e4 4811 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4812 int work_done;
1da177e4 4813
bea3348e 4814 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4815 rtl8169_tx_interrupt(dev, tp, ioaddr);
4816
bea3348e 4817 if (work_done < budget) {
288379f0 4818 napi_complete(napi);
f11a377b
DD		 4819
4820 /* We need for force the visibility of tp->intr_mask
4821 * for other CPUs, as we can loose an MSI interrupt
4822 * and potentially wait for a retransmit timeout if we don't.
4823 * The posted write to IntrMask is safe, as it will
4824 * eventually make it to the chip and we won't loose anything
4825 * until it does.
1da177e4 4826 */
f11a377b 4827 tp->intr_mask = 0xffff;
4c020a96 4828 wmb();
0e485150 4829 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4830 }
4831
bea3348e 4832 return work_done;
1da177e4 4833}
1da177e4 4834
523a6094
FR		 4835static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4836{
4837 struct rtl8169_private *tp = netdev_priv(dev);
4838
4839 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4840 return;
4841
4842 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4843 RTL_W32(RxMissed, 0);
4844}
4845
1da177e4
LT		 4846static void rtl8169_down(struct net_device *dev)
4847{
4848 struct rtl8169_private *tp = netdev_priv(dev);
4849 void __iomem *ioaddr = tp->mmio_addr;
1da177e4
LT		 4850
4851 rtl8169_delete_timer(dev);
4852
4853 netif_stop_queue(dev);
4854
93dd79e8 4855 napi_disable(&tp->napi);
93dd79e8 4856
1da177e4
LT		 4857 spin_lock_irq(&tp->lock);
4858
4859 rtl8169_asic_down(ioaddr);
323bb685
SG		 4860 /*
4861 * At this point device interrupts can not be enabled in any function,
4862 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4863 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4864 */
523a6094 4865 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4866
4867 spin_unlock_irq(&tp->lock);
4868
4869 synchronize_irq(dev->irq);
4870
1da177e4 4871 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4872 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 4873
1da177e4
LT		 4874 rtl8169_tx_clear(tp);
4875
4876 rtl8169_rx_clear(tp);
065c27c1 4877
4878 rtl_pll_power_down(tp);
1da177e4
LT		 4879}
4880
4881static int rtl8169_close(struct net_device *dev)
4882{
4883 struct rtl8169_private *tp = netdev_priv(dev);
4884 struct pci_dev *pdev = tp->pci_dev;
4885
e1759441
RW		 4886 pm_runtime_get_sync(&pdev->dev);
4887
355423d0
IV		 4888 /* update counters before going down */
4889 rtl8169_update_counters(dev);
4890
1da177e4
LT		 4891 rtl8169_down(dev);
4892
4893 free_irq(dev->irq, dev);
4894
82553bb6
SG		 4895 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4896 tp->RxPhyAddr);
4897 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4898 tp->TxPhyAddr);
1da177e4
LT		 4899 tp->TxDescArray = NULL;
4900 tp->RxDescArray = NULL;
4901
e1759441
RW		 4902 pm_runtime_put_sync(&pdev->dev);
4903
1da177e4
LT		 4904 return 0;
4905}
4906
07ce4064 4907static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4908{
4909 struct rtl8169_private *tp = netdev_priv(dev);
4910 void __iomem *ioaddr = tp->mmio_addr;
4911 unsigned long flags;
4912 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4913 int rx_mode;
1da177e4
LT		 4914 u32 tmp = 0;
4915
4916 if (dev->flags & IFF_PROMISC) {
4917 /* Unconditionally log net taps. */
bf82c189 4918 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4919 rx_mode =
4920 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4921 AcceptAllPhys;
4922 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4923 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4924 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4925 /* Too many to filter perfectly -- accept all multicasts. */
4926 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4927 mc_filter[1] = mc_filter[0] = 0xffffffff;
4928 } else {
22bedad3 4929 struct netdev_hw_addr *ha;
07d3f51f 4930
1da177e4
LT		 4931 rx_mode = AcceptBroadcast | AcceptMyPhys;
4932 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 4933 netdev_for_each_mc_addr(ha, dev) {
4934 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 4935 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4936 rx_mode |= AcceptMulticast;
4937 }
4938 }
4939
4940 spin_lock_irqsave(&tp->lock, flags);
4941
4942 tmp = rtl8169_rx_config | rx_mode |
4943 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4944
f887cce8 4945 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4946 u32 data = mc_filter[0];
4947
4948 mc_filter[0] = swab32(mc_filter[1]);
4949 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4950 }
4951
1da177e4 4952 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4953 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4954
57a9f236
FR		 4955 RTL_W32(RxConfig, tmp);
4956
1da177e4
LT		 4957 spin_unlock_irqrestore(&tp->lock, flags);
4958}
4959
4960/**
4961 * rtl8169_get_stats - Get rtl8169 read/write statistics
4962 * @dev: The Ethernet Device to get statistics for
4963 *
4964 * Get TX/RX statistics for rtl8169
4965 */
4966static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4967{
4968 struct rtl8169_private *tp = netdev_priv(dev);
4969 void __iomem *ioaddr = tp->mmio_addr;
4970 unsigned long flags;
4971
4972 if (netif_running(dev)) {
4973 spin_lock_irqsave(&tp->lock, flags);
523a6094 4974 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4975 spin_unlock_irqrestore(&tp->lock, flags);
4976 }
5b0384f4 4977
cebf8cc7 4978 return &dev->stats;
1da177e4
LT		 4979}
4980
861ab440 4981static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4982{
065c27c1 4983 struct rtl8169_private *tp = netdev_priv(dev);
4984
5d06a99f 4985 if (!netif_running(dev))
861ab440 4986 return;
5d06a99f 4987
065c27c1 4988 rtl_pll_power_down(tp);
4989
5d06a99f
FR		 4990 netif_device_detach(dev);
4991 netif_stop_queue(dev);
861ab440
RW		 4992}
4993
4994#ifdef CONFIG_PM
4995
4996static int rtl8169_suspend(struct device *device)
4997{
4998 struct pci_dev *pdev = to_pci_dev(device);
4999 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5000
861ab440 5001 rtl8169_net_suspend(dev);
1371fa6d 5002
5d06a99f
FR		 5003 return 0;
5004}
5005
e1759441
RW		 5006static void __rtl8169_resume(struct net_device *dev)
5007{
065c27c1 5008 struct rtl8169_private *tp = netdev_priv(dev);
5009
e1759441 5010 netif_device_attach(dev);
065c27c1 5011
5012 rtl_pll_power_up(tp);
5013
e1759441
RW		 5014 rtl8169_schedule_work(dev, rtl8169_reset_task);
5015}
5016
861ab440 5017static int rtl8169_resume(struct device *device)
5d06a99f 5018{
861ab440 5019 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5020 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5021 struct rtl8169_private *tp = netdev_priv(dev);
5022
5023 rtl8169_init_phy(dev, tp);
5d06a99f 5024
e1759441
RW		 5025 if (netif_running(dev))
5026 __rtl8169_resume(dev);
5d06a99f 5027
e1759441
RW		 5028 return 0;
5029}
5030
5031static int rtl8169_runtime_suspend(struct device *device)
5032{
5033 struct pci_dev *pdev = to_pci_dev(device);
5034 struct net_device *dev = pci_get_drvdata(pdev);
5035 struct rtl8169_private *tp = netdev_priv(dev);
5036
5037 if (!tp->TxDescArray)
5038 return 0;
5039
5040 spin_lock_irq(&tp->lock);
5041 tp->saved_wolopts = __rtl8169_get_wol(tp);
5042 __rtl8169_set_wol(tp, WAKE_ANY);
5043 spin_unlock_irq(&tp->lock);
5044
5045 rtl8169_net_suspend(dev);
5046
5047 return 0;
5048}
5049
5050static int rtl8169_runtime_resume(struct device *device)
5051{
5052 struct pci_dev *pdev = to_pci_dev(device);
5053 struct net_device *dev = pci_get_drvdata(pdev);
5054 struct rtl8169_private *tp = netdev_priv(dev);
5055
5056 if (!tp->TxDescArray)
5057 return 0;
5058
5059 spin_lock_irq(&tp->lock);
5060 __rtl8169_set_wol(tp, tp->saved_wolopts);
5061 tp->saved_wolopts = 0;
5062 spin_unlock_irq(&tp->lock);
5063
fccec10b
SG		 5064 rtl8169_init_phy(dev, tp);
5065
e1759441 5066 __rtl8169_resume(dev);
5d06a99f 5067
5d06a99f
FR		 5068 return 0;
5069}
5070
e1759441
RW		 5071static int rtl8169_runtime_idle(struct device *device)
5072{
5073 struct pci_dev *pdev = to_pci_dev(device);
5074 struct net_device *dev = pci_get_drvdata(pdev);
5075 struct rtl8169_private *tp = netdev_priv(dev);
5076
e4fbce74 5077 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5078}
5079
47145210 5080static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 5081 .suspend = rtl8169_suspend,
5082 .resume = rtl8169_resume,
5083 .freeze = rtl8169_suspend,
5084 .thaw = rtl8169_resume,
5085 .poweroff = rtl8169_suspend,
5086 .restore = rtl8169_resume,
e1759441
RW		 5087 .runtime_suspend = rtl8169_runtime_suspend,
5088 .runtime_resume = rtl8169_runtime_resume,
5089 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5090};
5091
5092#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5093
5094#else /* !CONFIG_PM */
5095
5096#define RTL8169_PM_OPS NULL
5097
5098#endif /* !CONFIG_PM */
5099
1765f95d
FR		 5100static void rtl_shutdown(struct pci_dev *pdev)
5101{
861ab440 5102 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5103 struct rtl8169_private *tp = netdev_priv(dev);
5104 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5105
5106 rtl8169_net_suspend(dev);
1765f95d 5107
cc098dc7
IV		 5108 /* restore original MAC address */
5109 rtl_rar_set(tp, dev->perm_addr);
5110
4bb3f522 5111 spin_lock_irq(&tp->lock);
5112
5113 rtl8169_asic_down(ioaddr);
5114
5115 spin_unlock_irq(&tp->lock);
5116
861ab440 5117 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 5118 /* WoL fails with some 8168 when the receiver is disabled. */
5119 if (tp->features & RTL_FEATURE_WOL) {
5120 pci_clear_master(pdev);
5121
5122 RTL_W8(ChipCmd, CmdRxEnb);
5123 /* PCI commit */
5124 RTL_R8(ChipCmd);
5125 }
5126
861ab440
RW		 5127 pci_wake_from_d3(pdev, true);
5128 pci_set_power_state(pdev, PCI_D3hot);
5129 }
5130}
5d06a99f 5131
1da177e4
LT		 5132static struct pci_driver rtl8169_pci_driver = {
5133 .name = MODULENAME,
5134 .id_table = rtl8169_pci_tbl,
5135 .probe = rtl8169_init_one,
5136 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5137 .shutdown = rtl_shutdown,
861ab440 5138 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5139};
5140
07d3f51f 5141static int __init rtl8169_init_module(void)
1da177e4 5142{
29917620 5143 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5144}
5145
07d3f51f 5146static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5147{
5148 pci_unregister_driver(&rtl8169_pci_driver);
5149}
5150
5151module_init(rtl8169_init_module);
5152module_exit(rtl8169_cleanup_module);
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