]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/dma-mapping.h> | |
e1759441 | 26 | #include <linux/pm_runtime.h> |
bca03d5f | 27 | #include <linux/firmware.h> |
ba04c7c9 | 28 | #include <linux/pci-aspm.h> |
1da177e4 | 29 | |
99f252b0 | 30 | #include <asm/system.h> |
1da177e4 LT |
31 | #include <asm/io.h> |
32 | #include <asm/irq.h> | |
33 | ||
865c652d | 34 | #define RTL8169_VERSION "2.3LK-NAPI" |
1da177e4 LT |
35 | #define MODULENAME "r8169" |
36 | #define PFX MODULENAME ": " | |
37 | ||
bca03d5f | 38 | #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
39 | #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" | |
5a5e4443 | 40 | #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
bca03d5f | 41 | |
1da177e4 LT |
42 | #ifdef RTL8169_DEBUG |
43 | #define assert(expr) \ | |
5b0384f4 FR |
44 | if (!(expr)) { \ |
45 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
b39d66a8 | 46 | #expr,__FILE__,__func__,__LINE__); \ |
5b0384f4 | 47 | } |
06fa7358 JP |
48 | #define dprintk(fmt, args...) \ |
49 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
50 | #else |
51 | #define assert(expr) do {} while (0) | |
52 | #define dprintk(fmt, args...) do {} while (0) | |
53 | #endif /* RTL8169_DEBUG */ | |
54 | ||
b57b7e5a | 55 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 56 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 57 | |
1da177e4 LT |
58 | #define TX_BUFFS_AVAIL(tp) \ |
59 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) | |
60 | ||
1da177e4 LT |
61 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
62 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 63 | static const int multicast_filter_limit = 32; |
1da177e4 LT |
64 | |
65 | /* MAC address length */ | |
66 | #define MAC_ADDR_LEN 6 | |
67 | ||
9c14ceaf | 68 | #define MAX_READ_REQUEST_SHIFT 12 |
1da177e4 LT |
69 | #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ |
70 | #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
71 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
1da177e4 LT |
72 | #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
73 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
74 | ||
75 | #define R8169_REGS_SIZE 256 | |
76 | #define R8169_NAPI_WEIGHT 64 | |
77 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
78 | #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ | |
79 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ | |
80 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) | |
81 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
82 | ||
83 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
84 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
85 | ||
ea8dbdd1 | 86 | #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
87 | #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) | |
e1564ec9 FR |
88 | #define RTL_EEPROM_SIG_ADDR 0x0000 |
89 | ||
1da177e4 LT |
90 | /* write/read MMIO register */ |
91 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
92 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
93 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
94 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
95 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
06f555f3 | 96 | #define RTL_R32(reg) readl (ioaddr + (reg)) |
1da177e4 LT |
97 | |
98 | enum mac_version { | |
f21b75e9 | 99 | RTL_GIGA_MAC_NONE = 0x00, |
ba6eb6ee FR |
100 | RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
101 | RTL_GIGA_MAC_VER_02 = 0x02, // 8169S | |
102 | RTL_GIGA_MAC_VER_03 = 0x03, // 8110S | |
103 | RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB | |
104 | RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd | |
6dccd16b | 105 | RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
2857ffb7 FR |
106 | RTL_GIGA_MAC_VER_07 = 0x07, // 8102e |
107 | RTL_GIGA_MAC_VER_08 = 0x08, // 8102e | |
108 | RTL_GIGA_MAC_VER_09 = 0x09, // 8102e | |
109 | RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e | |
2dd99530 | 110 | RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
e3cf0cc0 FR |
111 | RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be |
112 | RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb | |
113 | RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? | |
114 | RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? | |
115 | RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec | |
116 | RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf | |
117 | RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP | |
118 | RTL_GIGA_MAC_VER_19 = 0x13, // 8168C | |
197ff761 | 119 | RTL_GIGA_MAC_VER_20 = 0x14, // 8168C |
6fb07058 | 120 | RTL_GIGA_MAC_VER_21 = 0x15, // 8168C |
ef3386f0 | 121 | RTL_GIGA_MAC_VER_22 = 0x16, // 8168C |
7f3e3d3a | 122 | RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP |
5b538df9 | 123 | RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP |
daf9df6d | 124 | RTL_GIGA_MAC_VER_25 = 0x19, // 8168D |
125 | RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D | |
e6de30d6 | 126 | RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP |
127 | RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP | |
5a5e4443 HW |
128 | RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E |
129 | RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E | |
1da177e4 LT |
130 | }; |
131 | ||
1da177e4 LT |
132 | #define _R(NAME,MAC,MASK) \ |
133 | { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } | |
134 | ||
3c6bee1d | 135 | static const struct { |
1da177e4 LT |
136 | const char *name; |
137 | u8 mac_version; | |
138 | u32 RxConfigMask; /* Clears the bits supported by this chip */ | |
139 | } rtl_chip_info[] = { | |
ba6eb6ee FR |
140 | _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 |
141 | _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S | |
142 | _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S | |
143 | _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB | |
144 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd | |
6dccd16b | 145 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe |
2857ffb7 FR |
146 | _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E |
147 | _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E | |
148 | _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E | |
149 | _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E | |
bcf0bf90 FR |
150 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
151 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E | |
152 | _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 | |
153 | _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 | |
e3cf0cc0 FR |
154 | _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 |
155 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E | |
156 | _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E | |
157 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E | |
158 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E | |
197ff761 | 159 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E |
6fb07058 | 160 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E |
ef3386f0 | 161 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E |
7f3e3d3a | 162 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E |
5b538df9 | 163 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E |
daf9df6d | 164 | _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E |
165 | _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E | |
e6de30d6 | 166 | _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E |
5a5e4443 HW |
167 | _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E |
168 | _R("RTL8105e", RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E | |
169 | _R("RTL8105e", RTL_GIGA_MAC_VER_30, 0xff7e1880) // PCI-E | |
1da177e4 LT |
170 | }; |
171 | #undef _R | |
172 | ||
bcf0bf90 FR |
173 | enum cfg_version { |
174 | RTL_CFG_0 = 0x00, | |
175 | RTL_CFG_1, | |
176 | RTL_CFG_2 | |
177 | }; | |
178 | ||
07ce4064 FR |
179 | static void rtl_hw_start_8169(struct net_device *); |
180 | static void rtl_hw_start_8168(struct net_device *); | |
181 | static void rtl_hw_start_8101(struct net_device *); | |
182 | ||
a3aa1884 | 183 | static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { |
bcf0bf90 | 184 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 185 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 186 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 187 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 FR |
188 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
189 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, | |
bc1660b5 | 190 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
191 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
192 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
193 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
194 | { 0x0001, 0x8168, |
195 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
196 | {0,}, |
197 | }; | |
198 | ||
199 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
200 | ||
6f0333b8 | 201 | static int rx_buf_sz = 16383; |
4300e8c7 | 202 | static int use_dac; |
b57b7e5a SH |
203 | static struct { |
204 | u32 msg_enable; | |
205 | } debug = { -1 }; | |
1da177e4 | 206 | |
07d3f51f FR |
207 | enum rtl_registers { |
208 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 209 | MAC4 = 4, |
07d3f51f FR |
210 | MAR0 = 8, /* Multicast filter. */ |
211 | CounterAddrLow = 0x10, | |
212 | CounterAddrHigh = 0x14, | |
213 | TxDescStartAddrLow = 0x20, | |
214 | TxDescStartAddrHigh = 0x24, | |
215 | TxHDescStartAddrLow = 0x28, | |
216 | TxHDescStartAddrHigh = 0x2c, | |
217 | FLASH = 0x30, | |
218 | ERSR = 0x36, | |
219 | ChipCmd = 0x37, | |
220 | TxPoll = 0x38, | |
221 | IntrMask = 0x3c, | |
222 | IntrStatus = 0x3e, | |
223 | TxConfig = 0x40, | |
224 | RxConfig = 0x44, | |
225 | RxMissed = 0x4c, | |
226 | Cfg9346 = 0x50, | |
227 | Config0 = 0x51, | |
228 | Config1 = 0x52, | |
229 | Config2 = 0x53, | |
230 | Config3 = 0x54, | |
231 | Config4 = 0x55, | |
232 | Config5 = 0x56, | |
233 | MultiIntr = 0x5c, | |
234 | PHYAR = 0x60, | |
07d3f51f FR |
235 | PHYstatus = 0x6c, |
236 | RxMaxSize = 0xda, | |
237 | CPlusCmd = 0xe0, | |
238 | IntrMitigate = 0xe2, | |
239 | RxDescAddrLow = 0xe4, | |
240 | RxDescAddrHigh = 0xe8, | |
f0298f81 | 241 | EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
242 | ||
243 | #define NoEarlyTx 0x3f /* Max value : no early transmit. */ | |
244 | ||
245 | MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ | |
246 | ||
247 | #define TxPacketMax (8064 >> 7) | |
248 | ||
07d3f51f FR |
249 | FuncEvent = 0xf0, |
250 | FuncEventMask = 0xf4, | |
251 | FuncPresetState = 0xf8, | |
252 | FuncForceEvent = 0xfc, | |
1da177e4 LT |
253 | }; |
254 | ||
f162a5d1 FR |
255 | enum rtl8110_registers { |
256 | TBICSR = 0x64, | |
257 | TBI_ANAR = 0x68, | |
258 | TBI_LPAR = 0x6a, | |
259 | }; | |
260 | ||
261 | enum rtl8168_8101_registers { | |
262 | CSIDR = 0x64, | |
263 | CSIAR = 0x68, | |
264 | #define CSIAR_FLAG 0x80000000 | |
265 | #define CSIAR_WRITE_CMD 0x80000000 | |
266 | #define CSIAR_BYTE_ENABLE 0x0f | |
267 | #define CSIAR_BYTE_ENABLE_SHIFT 12 | |
268 | #define CSIAR_ADDR_MASK 0x0fff | |
065c27c1 | 269 | PMCH = 0x6f, |
f162a5d1 FR |
270 | EPHYAR = 0x80, |
271 | #define EPHYAR_FLAG 0x80000000 | |
272 | #define EPHYAR_WRITE_CMD 0x80000000 | |
273 | #define EPHYAR_REG_MASK 0x1f | |
274 | #define EPHYAR_REG_SHIFT 16 | |
275 | #define EPHYAR_DATA_MASK 0xffff | |
5a5e4443 HW |
276 | DLLPR = 0xd0, |
277 | #define PM_SWITCH (1 << 6) | |
f162a5d1 FR |
278 | DBG_REG = 0xd1, |
279 | #define FIX_NAK_1 (1 << 4) | |
280 | #define FIX_NAK_2 (1 << 3) | |
5a5e4443 HW |
281 | TWSI = 0xd2, |
282 | MCU = 0xd3, | |
283 | #define EN_NDP (1 << 3) | |
284 | #define EN_OOB_RESET (1 << 2) | |
daf9df6d | 285 | EFUSEAR = 0xdc, |
286 | #define EFUSEAR_FLAG 0x80000000 | |
287 | #define EFUSEAR_WRITE_CMD 0x80000000 | |
288 | #define EFUSEAR_READ_CMD 0x00000000 | |
289 | #define EFUSEAR_REG_MASK 0x03ff | |
290 | #define EFUSEAR_REG_SHIFT 8 | |
291 | #define EFUSEAR_DATA_MASK 0xff | |
f162a5d1 FR |
292 | }; |
293 | ||
c0e45c1c | 294 | enum rtl8168_registers { |
b646d900 | 295 | ERIDR = 0x70, |
296 | ERIAR = 0x74, | |
297 | #define ERIAR_FLAG 0x80000000 | |
298 | #define ERIAR_WRITE_CMD 0x80000000 | |
299 | #define ERIAR_READ_CMD 0x00000000 | |
300 | #define ERIAR_ADDR_BYTE_ALIGN 4 | |
301 | #define ERIAR_EXGMAC 0 | |
302 | #define ERIAR_MSIX 1 | |
303 | #define ERIAR_ASF 2 | |
304 | #define ERIAR_TYPE_SHIFT 16 | |
305 | #define ERIAR_BYTEEN 0x0f | |
306 | #define ERIAR_BYTEEN_SHIFT 12 | |
c0e45c1c | 307 | EPHY_RXER_NUM = 0x7c, |
308 | OCPDR = 0xb0, /* OCP GPHY access */ | |
309 | #define OCPDR_WRITE_CMD 0x80000000 | |
310 | #define OCPDR_READ_CMD 0x00000000 | |
311 | #define OCPDR_REG_MASK 0x7f | |
312 | #define OCPDR_GPHY_REG_SHIFT 16 | |
313 | #define OCPDR_DATA_MASK 0xffff | |
314 | OCPAR = 0xb4, | |
315 | #define OCPAR_FLAG 0x80000000 | |
316 | #define OCPAR_GPHY_WRITE_CMD 0x8000f060 | |
317 | #define OCPAR_GPHY_READ_CMD 0x0000f060 | |
e6de30d6 | 318 | RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */ |
c0e45c1c | 319 | }; |
320 | ||
07d3f51f | 321 | enum rtl_register_content { |
1da177e4 | 322 | /* InterruptStatusBits */ |
07d3f51f FR |
323 | SYSErr = 0x8000, |
324 | PCSTimeout = 0x4000, | |
325 | SWInt = 0x0100, | |
326 | TxDescUnavail = 0x0080, | |
327 | RxFIFOOver = 0x0040, | |
328 | LinkChg = 0x0020, | |
329 | RxOverflow = 0x0010, | |
330 | TxErr = 0x0008, | |
331 | TxOK = 0x0004, | |
332 | RxErr = 0x0002, | |
333 | RxOK = 0x0001, | |
1da177e4 LT |
334 | |
335 | /* RxStatusDesc */ | |
9dccf611 FR |
336 | RxFOVF = (1 << 23), |
337 | RxRWT = (1 << 22), | |
338 | RxRES = (1 << 21), | |
339 | RxRUNT = (1 << 20), | |
340 | RxCRC = (1 << 19), | |
1da177e4 LT |
341 | |
342 | /* ChipCmdBits */ | |
07d3f51f FR |
343 | CmdReset = 0x10, |
344 | CmdRxEnb = 0x08, | |
345 | CmdTxEnb = 0x04, | |
346 | RxBufEmpty = 0x01, | |
1da177e4 | 347 | |
275391a4 FR |
348 | /* TXPoll register p.5 */ |
349 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
350 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
351 | FSWInt = 0x01, /* Forced software interrupt */ | |
352 | ||
1da177e4 | 353 | /* Cfg9346Bits */ |
07d3f51f FR |
354 | Cfg9346_Lock = 0x00, |
355 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
356 | |
357 | /* rx_mode_bits */ | |
07d3f51f FR |
358 | AcceptErr = 0x20, |
359 | AcceptRunt = 0x10, | |
360 | AcceptBroadcast = 0x08, | |
361 | AcceptMulticast = 0x04, | |
362 | AcceptMyPhys = 0x02, | |
363 | AcceptAllPhys = 0x01, | |
1da177e4 LT |
364 | |
365 | /* RxConfigBits */ | |
07d3f51f FR |
366 | RxCfgFIFOShift = 13, |
367 | RxCfgDMAShift = 8, | |
1da177e4 LT |
368 | |
369 | /* TxConfigBits */ | |
370 | TxInterFrameGapShift = 24, | |
371 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
372 | ||
5d06a99f | 373 | /* Config1 register p.24 */ |
f162a5d1 FR |
374 | LEDS1 = (1 << 7), |
375 | LEDS0 = (1 << 6), | |
fbac58fc | 376 | MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
f162a5d1 FR |
377 | Speed_down = (1 << 4), |
378 | MEMMAP = (1 << 3), | |
379 | IOMAP = (1 << 2), | |
380 | VPD = (1 << 1), | |
5d06a99f FR |
381 | PMEnable = (1 << 0), /* Power Management Enable */ |
382 | ||
6dccd16b FR |
383 | /* Config2 register p. 25 */ |
384 | PCI_Clock_66MHz = 0x01, | |
385 | PCI_Clock_33MHz = 0x00, | |
386 | ||
61a4dcc2 FR |
387 | /* Config3 register p.25 */ |
388 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
389 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
f162a5d1 | 390 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 391 | |
5d06a99f | 392 | /* Config5 register p.27 */ |
61a4dcc2 FR |
393 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
394 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
395 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
396 | LanWake = (1 << 1), /* LanWake enable/disable */ | |
5d06a99f FR |
397 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
398 | ||
1da177e4 LT |
399 | /* TBICSR p.28 */ |
400 | TBIReset = 0x80000000, | |
401 | TBILoopback = 0x40000000, | |
402 | TBINwEnable = 0x20000000, | |
403 | TBINwRestart = 0x10000000, | |
404 | TBILinkOk = 0x02000000, | |
405 | TBINwComplete = 0x01000000, | |
406 | ||
407 | /* CPlusCmd p.31 */ | |
f162a5d1 FR |
408 | EnableBist = (1 << 15), // 8168 8101 |
409 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
410 | Normal_mode = (1 << 13), // unused | |
411 | Force_half_dup = (1 << 12), // 8168 8101 | |
412 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
413 | Force_txflow_en = (1 << 10), // 8168 8101 | |
414 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
415 | ASF = (1 << 8), // 8168 8101 | |
416 | PktCntrDisable = (1 << 7), // 8168 8101 | |
417 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
418 | RxVlan = (1 << 6), |
419 | RxChkSum = (1 << 5), | |
420 | PCIDAC = (1 << 4), | |
421 | PCIMulRW = (1 << 3), | |
0e485150 FR |
422 | INTT_0 = 0x0000, // 8168 |
423 | INTT_1 = 0x0001, // 8168 | |
424 | INTT_2 = 0x0002, // 8168 | |
425 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
426 | |
427 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
428 | TBI_Enable = 0x80, |
429 | TxFlowCtrl = 0x40, | |
430 | RxFlowCtrl = 0x20, | |
431 | _1000bpsF = 0x10, | |
432 | _100bps = 0x08, | |
433 | _10bps = 0x04, | |
434 | LinkStatus = 0x02, | |
435 | FullDup = 0x01, | |
1da177e4 | 436 | |
1da177e4 | 437 | /* _TBICSRBit */ |
07d3f51f | 438 | TBILinkOK = 0x02000000, |
d4a3a0fc SH |
439 | |
440 | /* DumpCounterCommand */ | |
07d3f51f | 441 | CounterDump = 0x8, |
1da177e4 LT |
442 | }; |
443 | ||
07d3f51f | 444 | enum desc_status_bit { |
1da177e4 LT |
445 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
446 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
447 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
448 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
449 | ||
450 | /* Tx private */ | |
451 | LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ | |
452 | MSSShift = 16, /* MSS value position */ | |
453 | MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ | |
454 | IPCS = (1 << 18), /* Calculate IP checksum */ | |
455 | UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ | |
456 | TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ | |
457 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
458 | ||
459 | /* Rx private */ | |
460 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
461 | PID0 = (1 << 17), /* Protocol ID bit 2/2 */ | |
462 | ||
463 | #define RxProtoUDP (PID1) | |
464 | #define RxProtoTCP (PID0) | |
465 | #define RxProtoIP (PID1 | PID0) | |
466 | #define RxProtoMask RxProtoIP | |
467 | ||
468 | IPFail = (1 << 16), /* IP checksum failed */ | |
469 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
470 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
471 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
472 | }; | |
473 | ||
474 | #define RsvdMask 0x3fffc000 | |
475 | ||
476 | struct TxDesc { | |
6cccd6e7 REB |
477 | __le32 opts1; |
478 | __le32 opts2; | |
479 | __le64 addr; | |
1da177e4 LT |
480 | }; |
481 | ||
482 | struct RxDesc { | |
6cccd6e7 REB |
483 | __le32 opts1; |
484 | __le32 opts2; | |
485 | __le64 addr; | |
1da177e4 LT |
486 | }; |
487 | ||
488 | struct ring_info { | |
489 | struct sk_buff *skb; | |
490 | u32 len; | |
491 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
492 | }; | |
493 | ||
f23e7fda | 494 | enum features { |
ccdffb9a FR |
495 | RTL_FEATURE_WOL = (1 << 0), |
496 | RTL_FEATURE_MSI = (1 << 1), | |
497 | RTL_FEATURE_GMII = (1 << 2), | |
f23e7fda FR |
498 | }; |
499 | ||
355423d0 IV |
500 | struct rtl8169_counters { |
501 | __le64 tx_packets; | |
502 | __le64 rx_packets; | |
503 | __le64 tx_errors; | |
504 | __le32 rx_errors; | |
505 | __le16 rx_missed; | |
506 | __le16 align_errors; | |
507 | __le32 tx_one_collision; | |
508 | __le32 tx_multi_collision; | |
509 | __le64 rx_unicast; | |
510 | __le64 rx_broadcast; | |
511 | __le32 rx_multicast; | |
512 | __le16 tx_aborted; | |
513 | __le16 tx_underun; | |
514 | }; | |
515 | ||
1da177e4 LT |
516 | struct rtl8169_private { |
517 | void __iomem *mmio_addr; /* memory map physical address */ | |
518 | struct pci_dev *pci_dev; /* Index of PCI device */ | |
c4028958 | 519 | struct net_device *dev; |
bea3348e | 520 | struct napi_struct napi; |
1da177e4 | 521 | spinlock_t lock; /* spin lock flag */ |
b57b7e5a | 522 | u32 msg_enable; |
1da177e4 LT |
523 | int chipset; |
524 | int mac_version; | |
1da177e4 LT |
525 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
526 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
527 | u32 dirty_rx; | |
528 | u32 dirty_tx; | |
529 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ | |
530 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
531 | dma_addr_t TxPhyAddr; | |
532 | dma_addr_t RxPhyAddr; | |
6f0333b8 | 533 | void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
1da177e4 | 534 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
1da177e4 LT |
535 | struct timer_list timer; |
536 | u16 cp_cmd; | |
0e485150 FR |
537 | u16 intr_event; |
538 | u16 napi_event; | |
1da177e4 | 539 | u16 intr_mask; |
1da177e4 | 540 | int phy_1000_ctrl_reg; |
c0e45c1c | 541 | |
542 | struct mdio_ops { | |
543 | void (*write)(void __iomem *, int, int); | |
544 | int (*read)(void __iomem *, int); | |
545 | } mdio_ops; | |
546 | ||
065c27c1 | 547 | struct pll_power_ops { |
548 | void (*down)(struct rtl8169_private *); | |
549 | void (*up)(struct rtl8169_private *); | |
550 | } pll_power_ops; | |
551 | ||
54405cde | 552 | int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
ccdffb9a | 553 | int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
4da19633 | 554 | void (*phy_reset_enable)(struct rtl8169_private *tp); |
07ce4064 | 555 | void (*hw_start)(struct net_device *); |
4da19633 | 556 | unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
1da177e4 | 557 | unsigned int (*link_ok)(void __iomem *); |
8b4ab28d | 558 | int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
9c14ceaf | 559 | int pcie_cap; |
c4028958 | 560 | struct delayed_work task; |
f23e7fda | 561 | unsigned features; |
ccdffb9a FR |
562 | |
563 | struct mii_if_info mii; | |
355423d0 | 564 | struct rtl8169_counters counters; |
e1759441 | 565 | u32 saved_wolopts; |
f1e02ed1 | 566 | |
567 | const struct firmware *fw; | |
1da177e4 LT |
568 | }; |
569 | ||
979b6c13 | 570 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 571 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 572 | module_param(use_dac, int, 0); |
4300e8c7 | 573 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
b57b7e5a SH |
574 | module_param_named(debug, debug.msg_enable, int, 0); |
575 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
576 | MODULE_LICENSE("GPL"); |
577 | MODULE_VERSION(RTL8169_VERSION); | |
bca03d5f | 578 | MODULE_FIRMWARE(FIRMWARE_8168D_1); |
579 | MODULE_FIRMWARE(FIRMWARE_8168D_2); | |
5a5e4443 | 580 | MODULE_FIRMWARE(FIRMWARE_8105E_1); |
1da177e4 LT |
581 | |
582 | static int rtl8169_open(struct net_device *dev); | |
61357325 SH |
583 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
584 | struct net_device *dev); | |
7d12e780 | 585 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
1da177e4 | 586 | static int rtl8169_init_ring(struct net_device *dev); |
07ce4064 | 587 | static void rtl_hw_start(struct net_device *dev); |
1da177e4 | 588 | static int rtl8169_close(struct net_device *dev); |
07ce4064 | 589 | static void rtl_set_rx_mode(struct net_device *dev); |
1da177e4 | 590 | static void rtl8169_tx_timeout(struct net_device *dev); |
4dcb7d33 | 591 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
1da177e4 | 592 | static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
bea3348e | 593 | void __iomem *, u32 budget); |
4dcb7d33 | 594 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
1da177e4 | 595 | static void rtl8169_down(struct net_device *dev); |
99f252b0 | 596 | static void rtl8169_rx_clear(struct rtl8169_private *tp); |
bea3348e | 597 | static int rtl8169_poll(struct napi_struct *napi, int budget); |
1da177e4 | 598 | |
1da177e4 | 599 | static const unsigned int rtl8169_rx_config = |
5b0384f4 | 600 | (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
1da177e4 | 601 | |
b646d900 | 602 | static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
603 | { | |
604 | void __iomem *ioaddr = tp->mmio_addr; | |
605 | int i; | |
606 | ||
607 | RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
608 | for (i = 0; i < 20; i++) { | |
609 | udelay(100); | |
610 | if (RTL_R32(OCPAR) & OCPAR_FLAG) | |
611 | break; | |
612 | } | |
613 | return RTL_R32(OCPDR); | |
614 | } | |
615 | ||
616 | static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) | |
617 | { | |
618 | void __iomem *ioaddr = tp->mmio_addr; | |
619 | int i; | |
620 | ||
621 | RTL_W32(OCPDR, data); | |
622 | RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
623 | for (i = 0; i < 20; i++) { | |
624 | udelay(100); | |
625 | if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0) | |
626 | break; | |
627 | } | |
628 | } | |
629 | ||
fac5b3ca | 630 | static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
b646d900 | 631 | { |
fac5b3ca | 632 | void __iomem *ioaddr = tp->mmio_addr; |
b646d900 | 633 | int i; |
634 | ||
635 | RTL_W8(ERIDR, cmd); | |
636 | RTL_W32(ERIAR, 0x800010e8); | |
637 | msleep(2); | |
638 | for (i = 0; i < 5; i++) { | |
639 | udelay(100); | |
640 | if (!(RTL_R32(ERIDR) & ERIAR_FLAG)) | |
641 | break; | |
642 | } | |
643 | ||
fac5b3ca | 644 | ocp_write(tp, 0x1, 0x30, 0x00000001); |
b646d900 | 645 | } |
646 | ||
647 | #define OOB_CMD_RESET 0x00 | |
648 | #define OOB_CMD_DRIVER_START 0x05 | |
649 | #define OOB_CMD_DRIVER_STOP 0x06 | |
650 | ||
651 | static void rtl8168_driver_start(struct rtl8169_private *tp) | |
652 | { | |
653 | int i; | |
654 | ||
655 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); | |
656 | ||
657 | for (i = 0; i < 10; i++) { | |
658 | msleep(10); | |
659 | if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800) | |
660 | break; | |
661 | } | |
662 | } | |
663 | ||
664 | static void rtl8168_driver_stop(struct rtl8169_private *tp) | |
665 | { | |
666 | int i; | |
667 | ||
668 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); | |
669 | ||
670 | for (i = 0; i < 10; i++) { | |
671 | msleep(10); | |
672 | if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0) | |
673 | break; | |
674 | } | |
675 | } | |
676 | ||
677 | ||
4da19633 | 678 | static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
1da177e4 LT |
679 | { |
680 | int i; | |
681 | ||
a6baf3af | 682 | RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 683 | |
2371408c | 684 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
685 | /* |
686 | * Check if the RTL8169 has completed writing to the specified | |
687 | * MII register. | |
688 | */ | |
5b0384f4 | 689 | if (!(RTL_R32(PHYAR) & 0x80000000)) |
1da177e4 | 690 | break; |
2371408c | 691 | udelay(25); |
1da177e4 | 692 | } |
024a07ba | 693 | /* |
81a95f04 TT |
694 | * According to hardware specs a 20us delay is required after write |
695 | * complete indication, but before sending next command. | |
024a07ba | 696 | */ |
81a95f04 | 697 | udelay(20); |
1da177e4 LT |
698 | } |
699 | ||
4da19633 | 700 | static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr) |
1da177e4 LT |
701 | { |
702 | int i, value = -1; | |
703 | ||
a6baf3af | 704 | RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
1da177e4 | 705 | |
2371408c | 706 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
707 | /* |
708 | * Check if the RTL8169 has completed retrieving data from | |
709 | * the specified MII register. | |
710 | */ | |
1da177e4 | 711 | if (RTL_R32(PHYAR) & 0x80000000) { |
a6baf3af | 712 | value = RTL_R32(PHYAR) & 0xffff; |
1da177e4 LT |
713 | break; |
714 | } | |
2371408c | 715 | udelay(25); |
1da177e4 | 716 | } |
81a95f04 TT |
717 | /* |
718 | * According to hardware specs a 20us delay is required after read | |
719 | * complete indication, but before sending next command. | |
720 | */ | |
721 | udelay(20); | |
722 | ||
1da177e4 LT |
723 | return value; |
724 | } | |
725 | ||
c0e45c1c | 726 | static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data) |
727 | { | |
728 | int i; | |
729 | ||
730 | RTL_W32(OCPDR, data | | |
731 | ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); | |
732 | RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); | |
733 | RTL_W32(EPHY_RXER_NUM, 0); | |
734 | ||
735 | for (i = 0; i < 100; i++) { | |
736 | mdelay(1); | |
737 | if (!(RTL_R32(OCPAR) & OCPAR_FLAG)) | |
738 | break; | |
739 | } | |
740 | } | |
741 | ||
742 | static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value) | |
743 | { | |
744 | r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD | | |
745 | (value & OCPDR_DATA_MASK)); | |
746 | } | |
747 | ||
748 | static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr) | |
749 | { | |
750 | int i; | |
751 | ||
752 | r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD); | |
753 | ||
754 | mdelay(1); | |
755 | RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); | |
756 | RTL_W32(EPHY_RXER_NUM, 0); | |
757 | ||
758 | for (i = 0; i < 100; i++) { | |
759 | mdelay(1); | |
760 | if (RTL_R32(OCPAR) & OCPAR_FLAG) | |
761 | break; | |
762 | } | |
763 | ||
764 | return RTL_R32(OCPDR) & OCPDR_DATA_MASK; | |
765 | } | |
766 | ||
e6de30d6 | 767 | #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
768 | ||
769 | static void r8168dp_2_mdio_start(void __iomem *ioaddr) | |
770 | { | |
771 | RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); | |
772 | } | |
773 | ||
774 | static void r8168dp_2_mdio_stop(void __iomem *ioaddr) | |
775 | { | |
776 | RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); | |
777 | } | |
778 | ||
779 | static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value) | |
780 | { | |
781 | r8168dp_2_mdio_start(ioaddr); | |
782 | ||
783 | r8169_mdio_write(ioaddr, reg_addr, value); | |
784 | ||
785 | r8168dp_2_mdio_stop(ioaddr); | |
786 | } | |
787 | ||
788 | static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr) | |
789 | { | |
790 | int value; | |
791 | ||
792 | r8168dp_2_mdio_start(ioaddr); | |
793 | ||
794 | value = r8169_mdio_read(ioaddr, reg_addr); | |
795 | ||
796 | r8168dp_2_mdio_stop(ioaddr); | |
797 | ||
798 | return value; | |
799 | } | |
800 | ||
4da19633 | 801 | static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
dacf8154 | 802 | { |
c0e45c1c | 803 | tp->mdio_ops.write(tp->mmio_addr, location, val); |
dacf8154 FR |
804 | } |
805 | ||
4da19633 | 806 | static int rtl_readphy(struct rtl8169_private *tp, int location) |
807 | { | |
c0e45c1c | 808 | return tp->mdio_ops.read(tp->mmio_addr, location); |
4da19633 | 809 | } |
810 | ||
811 | static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) | |
812 | { | |
813 | rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); | |
814 | } | |
815 | ||
816 | static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) | |
daf9df6d | 817 | { |
818 | int val; | |
819 | ||
4da19633 | 820 | val = rtl_readphy(tp, reg_addr); |
821 | rtl_writephy(tp, reg_addr, (val | p) & ~m); | |
daf9df6d | 822 | } |
823 | ||
ccdffb9a FR |
824 | static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
825 | int val) | |
826 | { | |
827 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 828 | |
4da19633 | 829 | rtl_writephy(tp, location, val); |
ccdffb9a FR |
830 | } |
831 | ||
832 | static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) | |
833 | { | |
834 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 835 | |
4da19633 | 836 | return rtl_readphy(tp, location); |
ccdffb9a FR |
837 | } |
838 | ||
dacf8154 FR |
839 | static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
840 | { | |
841 | unsigned int i; | |
842 | ||
843 | RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | | |
844 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
845 | ||
846 | for (i = 0; i < 100; i++) { | |
847 | if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) | |
848 | break; | |
849 | udelay(10); | |
850 | } | |
851 | } | |
852 | ||
853 | static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) | |
854 | { | |
855 | u16 value = 0xffff; | |
856 | unsigned int i; | |
857 | ||
858 | RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
859 | ||
860 | for (i = 0; i < 100; i++) { | |
861 | if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { | |
862 | value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; | |
863 | break; | |
864 | } | |
865 | udelay(10); | |
866 | } | |
867 | ||
868 | return value; | |
869 | } | |
870 | ||
871 | static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) | |
872 | { | |
873 | unsigned int i; | |
874 | ||
875 | RTL_W32(CSIDR, value); | |
876 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
877 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
878 | ||
879 | for (i = 0; i < 100; i++) { | |
880 | if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) | |
881 | break; | |
882 | udelay(10); | |
883 | } | |
884 | } | |
885 | ||
886 | static u32 rtl_csi_read(void __iomem *ioaddr, int addr) | |
887 | { | |
888 | u32 value = ~0x00; | |
889 | unsigned int i; | |
890 | ||
891 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | | |
892 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
893 | ||
894 | for (i = 0; i < 100; i++) { | |
895 | if (RTL_R32(CSIAR) & CSIAR_FLAG) { | |
896 | value = RTL_R32(CSIDR); | |
897 | break; | |
898 | } | |
899 | udelay(10); | |
900 | } | |
901 | ||
902 | return value; | |
903 | } | |
904 | ||
daf9df6d | 905 | static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) |
906 | { | |
907 | u8 value = 0xff; | |
908 | unsigned int i; | |
909 | ||
910 | RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); | |
911 | ||
912 | for (i = 0; i < 300; i++) { | |
913 | if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) { | |
914 | value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK; | |
915 | break; | |
916 | } | |
917 | udelay(100); | |
918 | } | |
919 | ||
920 | return value; | |
921 | } | |
922 | ||
1da177e4 LT |
923 | static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
924 | { | |
925 | RTL_W16(IntrMask, 0x0000); | |
926 | ||
927 | RTL_W16(IntrStatus, 0xffff); | |
928 | } | |
929 | ||
930 | static void rtl8169_asic_down(void __iomem *ioaddr) | |
931 | { | |
932 | RTL_W8(ChipCmd, 0x00); | |
933 | rtl8169_irq_mask_and_ack(ioaddr); | |
934 | RTL_R16(CPlusCmd); | |
935 | } | |
936 | ||
4da19633 | 937 | static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 938 | { |
4da19633 | 939 | void __iomem *ioaddr = tp->mmio_addr; |
940 | ||
1da177e4 LT |
941 | return RTL_R32(TBICSR) & TBIReset; |
942 | } | |
943 | ||
4da19633 | 944 | static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 945 | { |
4da19633 | 946 | return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
947 | } |
948 | ||
949 | static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) | |
950 | { | |
951 | return RTL_R32(TBICSR) & TBILinkOk; | |
952 | } | |
953 | ||
954 | static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) | |
955 | { | |
956 | return RTL_R8(PHYstatus) & LinkStatus; | |
957 | } | |
958 | ||
4da19633 | 959 | static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
1da177e4 | 960 | { |
4da19633 | 961 | void __iomem *ioaddr = tp->mmio_addr; |
962 | ||
1da177e4 LT |
963 | RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
964 | } | |
965 | ||
4da19633 | 966 | static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
1da177e4 LT |
967 | { |
968 | unsigned int val; | |
969 | ||
4da19633 | 970 | val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
971 | rtl_writephy(tp, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
972 | } |
973 | ||
e4fbce74 | 974 | static void __rtl8169_check_link_status(struct net_device *dev, |
07d3f51f | 975 | struct rtl8169_private *tp, |
e4fbce74 RW |
976 | void __iomem *ioaddr, |
977 | bool pm) | |
1da177e4 LT |
978 | { |
979 | unsigned long flags; | |
980 | ||
981 | spin_lock_irqsave(&tp->lock, flags); | |
982 | if (tp->link_ok(ioaddr)) { | |
e1759441 | 983 | /* This is to cancel a scheduled suspend if there's one. */ |
e4fbce74 RW |
984 | if (pm) |
985 | pm_request_resume(&tp->pci_dev->dev); | |
1da177e4 | 986 | netif_carrier_on(dev); |
1519e57f FR |
987 | if (net_ratelimit()) |
988 | netif_info(tp, ifup, dev, "link up\n"); | |
b57b7e5a | 989 | } else { |
1da177e4 | 990 | netif_carrier_off(dev); |
bf82c189 | 991 | netif_info(tp, ifdown, dev, "link down\n"); |
e4fbce74 RW |
992 | if (pm) |
993 | pm_schedule_suspend(&tp->pci_dev->dev, 100); | |
b57b7e5a | 994 | } |
1da177e4 LT |
995 | spin_unlock_irqrestore(&tp->lock, flags); |
996 | } | |
997 | ||
e4fbce74 RW |
998 | static void rtl8169_check_link_status(struct net_device *dev, |
999 | struct rtl8169_private *tp, | |
1000 | void __iomem *ioaddr) | |
1001 | { | |
1002 | __rtl8169_check_link_status(dev, tp, ioaddr, false); | |
1003 | } | |
1004 | ||
e1759441 RW |
1005 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1006 | ||
1007 | static u32 __rtl8169_get_wol(struct rtl8169_private *tp) | |
61a4dcc2 | 1008 | { |
61a4dcc2 FR |
1009 | void __iomem *ioaddr = tp->mmio_addr; |
1010 | u8 options; | |
e1759441 | 1011 | u32 wolopts = 0; |
61a4dcc2 FR |
1012 | |
1013 | options = RTL_R8(Config1); | |
1014 | if (!(options & PMEnable)) | |
e1759441 | 1015 | return 0; |
61a4dcc2 FR |
1016 | |
1017 | options = RTL_R8(Config3); | |
1018 | if (options & LinkUp) | |
e1759441 | 1019 | wolopts |= WAKE_PHY; |
61a4dcc2 | 1020 | if (options & MagicPacket) |
e1759441 | 1021 | wolopts |= WAKE_MAGIC; |
61a4dcc2 FR |
1022 | |
1023 | options = RTL_R8(Config5); | |
1024 | if (options & UWF) | |
e1759441 | 1025 | wolopts |= WAKE_UCAST; |
61a4dcc2 | 1026 | if (options & BWF) |
e1759441 | 1027 | wolopts |= WAKE_BCAST; |
61a4dcc2 | 1028 | if (options & MWF) |
e1759441 | 1029 | wolopts |= WAKE_MCAST; |
61a4dcc2 | 1030 | |
e1759441 | 1031 | return wolopts; |
61a4dcc2 FR |
1032 | } |
1033 | ||
e1759441 | 1034 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
61a4dcc2 FR |
1035 | { |
1036 | struct rtl8169_private *tp = netdev_priv(dev); | |
e1759441 RW |
1037 | |
1038 | spin_lock_irq(&tp->lock); | |
1039 | ||
1040 | wol->supported = WAKE_ANY; | |
1041 | wol->wolopts = __rtl8169_get_wol(tp); | |
1042 | ||
1043 | spin_unlock_irq(&tp->lock); | |
1044 | } | |
1045 | ||
1046 | static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) | |
1047 | { | |
61a4dcc2 | 1048 | void __iomem *ioaddr = tp->mmio_addr; |
07d3f51f | 1049 | unsigned int i; |
350f7596 | 1050 | static const struct { |
61a4dcc2 FR |
1051 | u32 opt; |
1052 | u16 reg; | |
1053 | u8 mask; | |
1054 | } cfg[] = { | |
1055 | { WAKE_ANY, Config1, PMEnable }, | |
1056 | { WAKE_PHY, Config3, LinkUp }, | |
1057 | { WAKE_MAGIC, Config3, MagicPacket }, | |
1058 | { WAKE_UCAST, Config5, UWF }, | |
1059 | { WAKE_BCAST, Config5, BWF }, | |
1060 | { WAKE_MCAST, Config5, MWF }, | |
1061 | { WAKE_ANY, Config5, LanWake } | |
1062 | }; | |
1063 | ||
61a4dcc2 FR |
1064 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
1065 | ||
1066 | for (i = 0; i < ARRAY_SIZE(cfg); i++) { | |
1067 | u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; | |
e1759441 | 1068 | if (wolopts & cfg[i].opt) |
61a4dcc2 FR |
1069 | options |= cfg[i].mask; |
1070 | RTL_W8(cfg[i].reg, options); | |
1071 | } | |
1072 | ||
1073 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
e1759441 RW |
1074 | } |
1075 | ||
1076 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1077 | { | |
1078 | struct rtl8169_private *tp = netdev_priv(dev); | |
1079 | ||
1080 | spin_lock_irq(&tp->lock); | |
61a4dcc2 | 1081 | |
f23e7fda FR |
1082 | if (wol->wolopts) |
1083 | tp->features |= RTL_FEATURE_WOL; | |
1084 | else | |
1085 | tp->features &= ~RTL_FEATURE_WOL; | |
e1759441 | 1086 | __rtl8169_set_wol(tp, wol->wolopts); |
61a4dcc2 FR |
1087 | spin_unlock_irq(&tp->lock); |
1088 | ||
ea80907f | 1089 | device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
1090 | ||
61a4dcc2 FR |
1091 | return 0; |
1092 | } | |
1093 | ||
1da177e4 LT |
1094 | static void rtl8169_get_drvinfo(struct net_device *dev, |
1095 | struct ethtool_drvinfo *info) | |
1096 | { | |
1097 | struct rtl8169_private *tp = netdev_priv(dev); | |
1098 | ||
1099 | strcpy(info->driver, MODULENAME); | |
1100 | strcpy(info->version, RTL8169_VERSION); | |
1101 | strcpy(info->bus_info, pci_name(tp->pci_dev)); | |
1102 | } | |
1103 | ||
1104 | static int rtl8169_get_regs_len(struct net_device *dev) | |
1105 | { | |
1106 | return R8169_REGS_SIZE; | |
1107 | } | |
1108 | ||
1109 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
54405cde | 1110 | u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
1da177e4 LT |
1111 | { |
1112 | struct rtl8169_private *tp = netdev_priv(dev); | |
1113 | void __iomem *ioaddr = tp->mmio_addr; | |
1114 | int ret = 0; | |
1115 | u32 reg; | |
1116 | ||
1117 | reg = RTL_R32(TBICSR); | |
1118 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && | |
1119 | (duplex == DUPLEX_FULL)) { | |
1120 | RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); | |
1121 | } else if (autoneg == AUTONEG_ENABLE) | |
1122 | RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); | |
1123 | else { | |
bf82c189 JP |
1124 | netif_warn(tp, link, dev, |
1125 | "incorrect speed setting refused in TBI mode\n"); | |
1da177e4 LT |
1126 | ret = -EOPNOTSUPP; |
1127 | } | |
1128 | ||
1129 | return ret; | |
1130 | } | |
1131 | ||
1132 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
54405cde | 1133 | u8 autoneg, u16 speed, u8 duplex, u32 adv) |
1da177e4 LT |
1134 | { |
1135 | struct rtl8169_private *tp = netdev_priv(dev); | |
3577aa1b | 1136 | int giga_ctrl, bmcr; |
54405cde | 1137 | int rc = -EINVAL; |
1da177e4 | 1138 | |
716b50a3 | 1139 | rtl_writephy(tp, 0x1f, 0x0000); |
1da177e4 LT |
1140 | |
1141 | if (autoneg == AUTONEG_ENABLE) { | |
3577aa1b | 1142 | int auto_nego; |
1143 | ||
4da19633 | 1144 | auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
54405cde ON |
1145 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
1146 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
1147 | ||
1148 | if (adv & ADVERTISED_10baseT_Half) | |
1149 | auto_nego |= ADVERTISE_10HALF; | |
1150 | if (adv & ADVERTISED_10baseT_Full) | |
1151 | auto_nego |= ADVERTISE_10FULL; | |
1152 | if (adv & ADVERTISED_100baseT_Half) | |
1153 | auto_nego |= ADVERTISE_100HALF; | |
1154 | if (adv & ADVERTISED_100baseT_Full) | |
1155 | auto_nego |= ADVERTISE_100FULL; | |
1156 | ||
3577aa1b | 1157 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1da177e4 | 1158 | |
4da19633 | 1159 | giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
3577aa1b | 1160 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
bcf0bf90 | 1161 | |
3577aa1b | 1162 | /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
1163 | if ((tp->mac_version != RTL_GIGA_MAC_VER_07) && | |
1164 | (tp->mac_version != RTL_GIGA_MAC_VER_08) && | |
1165 | (tp->mac_version != RTL_GIGA_MAC_VER_09) && | |
1166 | (tp->mac_version != RTL_GIGA_MAC_VER_10) && | |
1167 | (tp->mac_version != RTL_GIGA_MAC_VER_13) && | |
1168 | (tp->mac_version != RTL_GIGA_MAC_VER_14) && | |
1169 | (tp->mac_version != RTL_GIGA_MAC_VER_15) && | |
5a5e4443 HW |
1170 | (tp->mac_version != RTL_GIGA_MAC_VER_16) && |
1171 | (tp->mac_version != RTL_GIGA_MAC_VER_29) && | |
1172 | (tp->mac_version != RTL_GIGA_MAC_VER_30)) { | |
54405cde ON |
1173 | if (adv & ADVERTISED_1000baseT_Half) |
1174 | giga_ctrl |= ADVERTISE_1000HALF; | |
1175 | if (adv & ADVERTISED_1000baseT_Full) | |
1176 | giga_ctrl |= ADVERTISE_1000FULL; | |
1177 | } else if (adv & (ADVERTISED_1000baseT_Half | | |
1178 | ADVERTISED_1000baseT_Full)) { | |
bf82c189 JP |
1179 | netif_info(tp, link, dev, |
1180 | "PHY does not support 1000Mbps\n"); | |
54405cde | 1181 | goto out; |
bcf0bf90 | 1182 | } |
1da177e4 | 1183 | |
3577aa1b | 1184 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
1185 | ||
4da19633 | 1186 | rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
1187 | rtl_writephy(tp, MII_CTRL1000, giga_ctrl); | |
3577aa1b | 1188 | } else { |
1189 | giga_ctrl = 0; | |
1190 | ||
1191 | if (speed == SPEED_10) | |
1192 | bmcr = 0; | |
1193 | else if (speed == SPEED_100) | |
1194 | bmcr = BMCR_SPEED100; | |
1195 | else | |
54405cde | 1196 | goto out; |
3577aa1b | 1197 | |
1198 | if (duplex == DUPLEX_FULL) | |
1199 | bmcr |= BMCR_FULLDPLX; | |
2584fbc3 RS |
1200 | } |
1201 | ||
1da177e4 LT |
1202 | tp->phy_1000_ctrl_reg = giga_ctrl; |
1203 | ||
4da19633 | 1204 | rtl_writephy(tp, MII_BMCR, bmcr); |
3577aa1b | 1205 | |
1206 | if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
1207 | (tp->mac_version == RTL_GIGA_MAC_VER_03)) { | |
1208 | if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { | |
4da19633 | 1209 | rtl_writephy(tp, 0x17, 0x2138); |
1210 | rtl_writephy(tp, 0x0e, 0x0260); | |
3577aa1b | 1211 | } else { |
4da19633 | 1212 | rtl_writephy(tp, 0x17, 0x2108); |
1213 | rtl_writephy(tp, 0x0e, 0x0000); | |
3577aa1b | 1214 | } |
1215 | } | |
1216 | ||
54405cde ON |
1217 | rc = 0; |
1218 | out: | |
1219 | return rc; | |
1da177e4 LT |
1220 | } |
1221 | ||
1222 | static int rtl8169_set_speed(struct net_device *dev, | |
54405cde | 1223 | u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
1da177e4 LT |
1224 | { |
1225 | struct rtl8169_private *tp = netdev_priv(dev); | |
1226 | int ret; | |
1227 | ||
54405cde | 1228 | ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
1da177e4 | 1229 | |
64e4bfb4 | 1230 | if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
1da177e4 LT |
1231 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
1232 | ||
1233 | return ret; | |
1234 | } | |
1235 | ||
1236 | static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1237 | { | |
1238 | struct rtl8169_private *tp = netdev_priv(dev); | |
1239 | unsigned long flags; | |
1240 | int ret; | |
1241 | ||
1242 | spin_lock_irqsave(&tp->lock, flags); | |
54405cde ON |
1243 | ret = rtl8169_set_speed(dev, |
1244 | cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising); | |
1da177e4 | 1245 | spin_unlock_irqrestore(&tp->lock, flags); |
5b0384f4 | 1246 | |
1da177e4 LT |
1247 | return ret; |
1248 | } | |
1249 | ||
1250 | static u32 rtl8169_get_rx_csum(struct net_device *dev) | |
1251 | { | |
1252 | struct rtl8169_private *tp = netdev_priv(dev); | |
1253 | ||
1254 | return tp->cp_cmd & RxChkSum; | |
1255 | } | |
1256 | ||
1257 | static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) | |
1258 | { | |
1259 | struct rtl8169_private *tp = netdev_priv(dev); | |
1260 | void __iomem *ioaddr = tp->mmio_addr; | |
1261 | unsigned long flags; | |
1262 | ||
1263 | spin_lock_irqsave(&tp->lock, flags); | |
1264 | ||
1265 | if (data) | |
1266 | tp->cp_cmd |= RxChkSum; | |
1267 | else | |
1268 | tp->cp_cmd &= ~RxChkSum; | |
1269 | ||
1270 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
1271 | RTL_R16(CPlusCmd); | |
1272 | ||
1273 | spin_unlock_irqrestore(&tp->lock, flags); | |
1274 | ||
1275 | return 0; | |
1276 | } | |
1277 | ||
1da177e4 LT |
1278 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
1279 | struct sk_buff *skb) | |
1280 | { | |
eab6d18d | 1281 | return (vlan_tx_tag_present(skb)) ? |
1da177e4 LT |
1282 | TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
1283 | } | |
1284 | ||
7a8fc77b FR |
1285 | #define NETIF_F_HW_VLAN_TX_RX (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX) |
1286 | ||
1287 | static void rtl8169_vlan_mode(struct net_device *dev) | |
1da177e4 LT |
1288 | { |
1289 | struct rtl8169_private *tp = netdev_priv(dev); | |
1290 | void __iomem *ioaddr = tp->mmio_addr; | |
1291 | unsigned long flags; | |
1292 | ||
1293 | spin_lock_irqsave(&tp->lock, flags); | |
7a8fc77b | 1294 | if (dev->features & NETIF_F_HW_VLAN_RX) |
1da177e4 LT |
1295 | tp->cp_cmd |= RxVlan; |
1296 | else | |
1297 | tp->cp_cmd &= ~RxVlan; | |
1298 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
7a8fc77b | 1299 | /* PCI commit */ |
1da177e4 LT |
1300 | RTL_R16(CPlusCmd); |
1301 | spin_unlock_irqrestore(&tp->lock, flags); | |
7a8fc77b FR |
1302 | |
1303 | dev->vlan_features = dev->features &~ NETIF_F_HW_VLAN_TX_RX; | |
1da177e4 LT |
1304 | } |
1305 | ||
7a8fc77b | 1306 | static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
1da177e4 LT |
1307 | { |
1308 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1da177e4 | 1309 | |
7a8fc77b FR |
1310 | if (opts2 & RxVlanTag) |
1311 | __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); | |
2edae08e | 1312 | |
1da177e4 | 1313 | desc->opts2 = 0; |
1da177e4 LT |
1314 | } |
1315 | ||
ccdffb9a | 1316 | static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1317 | { |
1318 | struct rtl8169_private *tp = netdev_priv(dev); | |
1319 | void __iomem *ioaddr = tp->mmio_addr; | |
1320 | u32 status; | |
1321 | ||
1322 | cmd->supported = | |
1323 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; | |
1324 | cmd->port = PORT_FIBRE; | |
1325 | cmd->transceiver = XCVR_INTERNAL; | |
1326 | ||
1327 | status = RTL_R32(TBICSR); | |
1328 | cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; | |
1329 | cmd->autoneg = !!(status & TBINwEnable); | |
1330 | ||
1331 | cmd->speed = SPEED_1000; | |
1332 | cmd->duplex = DUPLEX_FULL; /* Always set */ | |
ccdffb9a FR |
1333 | |
1334 | return 0; | |
1da177e4 LT |
1335 | } |
1336 | ||
ccdffb9a | 1337 | static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1338 | { |
1339 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a FR |
1340 | |
1341 | return mii_ethtool_gset(&tp->mii, cmd); | |
1da177e4 LT |
1342 | } |
1343 | ||
1344 | static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1345 | { | |
1346 | struct rtl8169_private *tp = netdev_priv(dev); | |
1347 | unsigned long flags; | |
ccdffb9a | 1348 | int rc; |
1da177e4 LT |
1349 | |
1350 | spin_lock_irqsave(&tp->lock, flags); | |
1351 | ||
ccdffb9a | 1352 | rc = tp->get_settings(dev, cmd); |
1da177e4 LT |
1353 | |
1354 | spin_unlock_irqrestore(&tp->lock, flags); | |
ccdffb9a | 1355 | return rc; |
1da177e4 LT |
1356 | } |
1357 | ||
1358 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1359 | void *p) | |
1360 | { | |
5b0384f4 FR |
1361 | struct rtl8169_private *tp = netdev_priv(dev); |
1362 | unsigned long flags; | |
1da177e4 | 1363 | |
5b0384f4 FR |
1364 | if (regs->len > R8169_REGS_SIZE) |
1365 | regs->len = R8169_REGS_SIZE; | |
1da177e4 | 1366 | |
5b0384f4 FR |
1367 | spin_lock_irqsave(&tp->lock, flags); |
1368 | memcpy_fromio(p, tp->mmio_addr, regs->len); | |
1369 | spin_unlock_irqrestore(&tp->lock, flags); | |
1da177e4 LT |
1370 | } |
1371 | ||
b57b7e5a SH |
1372 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
1373 | { | |
1374 | struct rtl8169_private *tp = netdev_priv(dev); | |
1375 | ||
1376 | return tp->msg_enable; | |
1377 | } | |
1378 | ||
1379 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
1380 | { | |
1381 | struct rtl8169_private *tp = netdev_priv(dev); | |
1382 | ||
1383 | tp->msg_enable = value; | |
1384 | } | |
1385 | ||
d4a3a0fc SH |
1386 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
1387 | "tx_packets", | |
1388 | "rx_packets", | |
1389 | "tx_errors", | |
1390 | "rx_errors", | |
1391 | "rx_missed", | |
1392 | "align_errors", | |
1393 | "tx_single_collisions", | |
1394 | "tx_multi_collisions", | |
1395 | "unicast", | |
1396 | "broadcast", | |
1397 | "multicast", | |
1398 | "tx_aborted", | |
1399 | "tx_underrun", | |
1400 | }; | |
1401 | ||
b9f2c044 | 1402 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 1403 | { |
b9f2c044 JG |
1404 | switch (sset) { |
1405 | case ETH_SS_STATS: | |
1406 | return ARRAY_SIZE(rtl8169_gstrings); | |
1407 | default: | |
1408 | return -EOPNOTSUPP; | |
1409 | } | |
d4a3a0fc SH |
1410 | } |
1411 | ||
355423d0 | 1412 | static void rtl8169_update_counters(struct net_device *dev) |
d4a3a0fc SH |
1413 | { |
1414 | struct rtl8169_private *tp = netdev_priv(dev); | |
1415 | void __iomem *ioaddr = tp->mmio_addr; | |
1416 | struct rtl8169_counters *counters; | |
1417 | dma_addr_t paddr; | |
1418 | u32 cmd; | |
355423d0 | 1419 | int wait = 1000; |
48addcc9 | 1420 | struct device *d = &tp->pci_dev->dev; |
d4a3a0fc | 1421 | |
355423d0 IV |
1422 | /* |
1423 | * Some chips are unable to dump tally counters when the receiver | |
1424 | * is disabled. | |
1425 | */ | |
1426 | if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) | |
1427 | return; | |
d4a3a0fc | 1428 | |
48addcc9 | 1429 | counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); |
d4a3a0fc SH |
1430 | if (!counters) |
1431 | return; | |
1432 | ||
1433 | RTL_W32(CounterAddrHigh, (u64)paddr >> 32); | |
284901a9 | 1434 | cmd = (u64)paddr & DMA_BIT_MASK(32); |
d4a3a0fc SH |
1435 | RTL_W32(CounterAddrLow, cmd); |
1436 | RTL_W32(CounterAddrLow, cmd | CounterDump); | |
1437 | ||
355423d0 IV |
1438 | while (wait--) { |
1439 | if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { | |
1440 | /* copy updated counters */ | |
1441 | memcpy(&tp->counters, counters, sizeof(*counters)); | |
d4a3a0fc | 1442 | break; |
355423d0 IV |
1443 | } |
1444 | udelay(10); | |
d4a3a0fc SH |
1445 | } |
1446 | ||
1447 | RTL_W32(CounterAddrLow, 0); | |
1448 | RTL_W32(CounterAddrHigh, 0); | |
1449 | ||
48addcc9 | 1450 | dma_free_coherent(d, sizeof(*counters), counters, paddr); |
d4a3a0fc SH |
1451 | } |
1452 | ||
355423d0 IV |
1453 | static void rtl8169_get_ethtool_stats(struct net_device *dev, |
1454 | struct ethtool_stats *stats, u64 *data) | |
1455 | { | |
1456 | struct rtl8169_private *tp = netdev_priv(dev); | |
1457 | ||
1458 | ASSERT_RTNL(); | |
1459 | ||
1460 | rtl8169_update_counters(dev); | |
1461 | ||
1462 | data[0] = le64_to_cpu(tp->counters.tx_packets); | |
1463 | data[1] = le64_to_cpu(tp->counters.rx_packets); | |
1464 | data[2] = le64_to_cpu(tp->counters.tx_errors); | |
1465 | data[3] = le32_to_cpu(tp->counters.rx_errors); | |
1466 | data[4] = le16_to_cpu(tp->counters.rx_missed); | |
1467 | data[5] = le16_to_cpu(tp->counters.align_errors); | |
1468 | data[6] = le32_to_cpu(tp->counters.tx_one_collision); | |
1469 | data[7] = le32_to_cpu(tp->counters.tx_multi_collision); | |
1470 | data[8] = le64_to_cpu(tp->counters.rx_unicast); | |
1471 | data[9] = le64_to_cpu(tp->counters.rx_broadcast); | |
1472 | data[10] = le32_to_cpu(tp->counters.rx_multicast); | |
1473 | data[11] = le16_to_cpu(tp->counters.tx_aborted); | |
1474 | data[12] = le16_to_cpu(tp->counters.tx_underun); | |
1475 | } | |
1476 | ||
d4a3a0fc SH |
1477 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
1478 | { | |
1479 | switch(stringset) { | |
1480 | case ETH_SS_STATS: | |
1481 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
1482 | break; | |
1483 | } | |
1484 | } | |
1485 | ||
7a8fc77b FR |
1486 | static int rtl8169_set_flags(struct net_device *dev, u32 data) |
1487 | { | |
1488 | struct rtl8169_private *tp = netdev_priv(dev); | |
1489 | unsigned long old_feat = dev->features; | |
1490 | int rc; | |
1491 | ||
1492 | if ((tp->mac_version == RTL_GIGA_MAC_VER_05) && | |
1493 | !(data & ETH_FLAG_RXVLAN)) { | |
1494 | netif_info(tp, drv, dev, "8110SCd requires hardware Rx VLAN\n"); | |
1495 | return -EINVAL; | |
1496 | } | |
1497 | ||
1498 | rc = ethtool_op_set_flags(dev, data, ETH_FLAG_TXVLAN | ETH_FLAG_RXVLAN); | |
1499 | if (rc) | |
1500 | return rc; | |
1501 | ||
1502 | if ((old_feat ^ dev->features) & NETIF_F_HW_VLAN_RX) | |
1503 | rtl8169_vlan_mode(dev); | |
1504 | ||
1505 | return 0; | |
1506 | } | |
1507 | ||
7282d491 | 1508 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
1509 | .get_drvinfo = rtl8169_get_drvinfo, |
1510 | .get_regs_len = rtl8169_get_regs_len, | |
1511 | .get_link = ethtool_op_get_link, | |
1512 | .get_settings = rtl8169_get_settings, | |
1513 | .set_settings = rtl8169_set_settings, | |
b57b7e5a SH |
1514 | .get_msglevel = rtl8169_get_msglevel, |
1515 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 LT |
1516 | .get_rx_csum = rtl8169_get_rx_csum, |
1517 | .set_rx_csum = rtl8169_set_rx_csum, | |
1da177e4 | 1518 | .set_tx_csum = ethtool_op_set_tx_csum, |
1da177e4 | 1519 | .set_sg = ethtool_op_set_sg, |
1da177e4 LT |
1520 | .set_tso = ethtool_op_set_tso, |
1521 | .get_regs = rtl8169_get_regs, | |
61a4dcc2 FR |
1522 | .get_wol = rtl8169_get_wol, |
1523 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 1524 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 1525 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 1526 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
7a8fc77b FR |
1527 | .set_flags = rtl8169_set_flags, |
1528 | .get_flags = ethtool_op_get_flags, | |
1da177e4 LT |
1529 | }; |
1530 | ||
07d3f51f FR |
1531 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
1532 | void __iomem *ioaddr) | |
1da177e4 | 1533 | { |
0e485150 FR |
1534 | /* |
1535 | * The driver currently handles the 8168Bf and the 8168Be identically | |
1536 | * but they can be identified more specifically through the test below | |
1537 | * if needed: | |
1538 | * | |
1539 | * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be | |
0127215c FR |
1540 | * |
1541 | * Same thing for the 8101Eb and the 8101Ec: | |
1542 | * | |
1543 | * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec | |
0e485150 | 1544 | */ |
350f7596 | 1545 | static const struct { |
1da177e4 | 1546 | u32 mask; |
e3cf0cc0 | 1547 | u32 val; |
1da177e4 LT |
1548 | int mac_version; |
1549 | } mac_info[] = { | |
5b538df9 | 1550 | /* 8168D family. */ |
daf9df6d | 1551 | { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
1552 | { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, | |
daf9df6d | 1553 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
5b538df9 | 1554 | |
e6de30d6 | 1555 | /* 8168DP family. */ |
1556 | { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, | |
1557 | { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, | |
1558 | ||
ef808d50 | 1559 | /* 8168C family. */ |
17c99297 | 1560 | { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
ef3386f0 | 1561 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
ef808d50 | 1562 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
7f3e3d3a | 1563 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
e3cf0cc0 FR |
1564 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
1565 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
197ff761 | 1566 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
6fb07058 | 1567 | { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
ef808d50 | 1568 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
e3cf0cc0 FR |
1569 | |
1570 | /* 8168B family. */ | |
1571 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
1572 | { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, | |
1573 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, | |
1574 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
1575 | ||
1576 | /* 8101 family. */ | |
5a5e4443 HW |
1577 | { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, |
1578 | { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, | |
1579 | { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, | |
2857ffb7 FR |
1580 | { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
1581 | { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, | |
1582 | { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, | |
1583 | { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, | |
1584 | { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, | |
1585 | { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, | |
e3cf0cc0 | 1586 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
2857ffb7 | 1587 | { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
e3cf0cc0 | 1588 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
2857ffb7 FR |
1589 | { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
1590 | { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, | |
e3cf0cc0 FR |
1591 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
1592 | /* FIXME: where did these entries come from ? -- FR */ | |
1593 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
1594 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
1595 | ||
1596 | /* 8110 family. */ | |
1597 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
1598 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
1599 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
1600 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
1601 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
1602 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
1603 | ||
f21b75e9 JD |
1604 | /* Catch-all */ |
1605 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } | |
1da177e4 LT |
1606 | }, *p = mac_info; |
1607 | u32 reg; | |
1608 | ||
e3cf0cc0 FR |
1609 | reg = RTL_R32(TxConfig); |
1610 | while ((reg & p->mask) != p->val) | |
1da177e4 LT |
1611 | p++; |
1612 | tp->mac_version = p->mac_version; | |
1613 | } | |
1614 | ||
1615 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
1616 | { | |
bcf0bf90 | 1617 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
1618 | } |
1619 | ||
867763c1 FR |
1620 | struct phy_reg { |
1621 | u16 reg; | |
1622 | u16 val; | |
1623 | }; | |
1624 | ||
4da19633 | 1625 | static void rtl_writephy_batch(struct rtl8169_private *tp, |
1626 | const struct phy_reg *regs, int len) | |
867763c1 FR |
1627 | { |
1628 | while (len-- > 0) { | |
4da19633 | 1629 | rtl_writephy(tp, regs->reg, regs->val); |
867763c1 FR |
1630 | regs++; |
1631 | } | |
1632 | } | |
1633 | ||
bca03d5f | 1634 | #define PHY_READ 0x00000000 |
1635 | #define PHY_DATA_OR 0x10000000 | |
1636 | #define PHY_DATA_AND 0x20000000 | |
1637 | #define PHY_BJMPN 0x30000000 | |
1638 | #define PHY_READ_EFUSE 0x40000000 | |
1639 | #define PHY_READ_MAC_BYTE 0x50000000 | |
1640 | #define PHY_WRITE_MAC_BYTE 0x60000000 | |
1641 | #define PHY_CLEAR_READCOUNT 0x70000000 | |
1642 | #define PHY_WRITE 0x80000000 | |
1643 | #define PHY_READCOUNT_EQ_SKIP 0x90000000 | |
1644 | #define PHY_COMP_EQ_SKIPN 0xa0000000 | |
1645 | #define PHY_COMP_NEQ_SKIPN 0xb0000000 | |
1646 | #define PHY_WRITE_PREVIOUS 0xc0000000 | |
1647 | #define PHY_SKIPN 0xd0000000 | |
1648 | #define PHY_DELAY_MS 0xe0000000 | |
1649 | #define PHY_WRITE_ERI_WORD 0xf0000000 | |
1650 | ||
1651 | static void | |
1652 | rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw) | |
1653 | { | |
bca03d5f | 1654 | __le32 *phytable = (__le32 *)fw->data; |
1655 | struct net_device *dev = tp->dev; | |
42b82dc1 | 1656 | size_t index, fw_size = fw->size / sizeof(*phytable); |
1657 | u32 predata, count; | |
bca03d5f | 1658 | |
1659 | if (fw->size % sizeof(*phytable)) { | |
1660 | netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size); | |
1661 | return; | |
1662 | } | |
1663 | ||
42b82dc1 | 1664 | for (index = 0; index < fw_size; index++) { |
1665 | u32 action = le32_to_cpu(phytable[index]); | |
1666 | u32 regno = (action & 0x0fff0000) >> 16; | |
bca03d5f | 1667 | |
42b82dc1 | 1668 | switch(action & 0xf0000000) { |
1669 | case PHY_READ: | |
1670 | case PHY_DATA_OR: | |
1671 | case PHY_DATA_AND: | |
1672 | case PHY_READ_EFUSE: | |
1673 | case PHY_CLEAR_READCOUNT: | |
1674 | case PHY_WRITE: | |
1675 | case PHY_WRITE_PREVIOUS: | |
1676 | case PHY_DELAY_MS: | |
1677 | break; | |
1678 | ||
1679 | case PHY_BJMPN: | |
1680 | if (regno > index) { | |
1681 | netif_err(tp, probe, tp->dev, | |
1682 | "Out of range of firmware\n"); | |
1683 | return; | |
1684 | } | |
1685 | break; | |
1686 | case PHY_READCOUNT_EQ_SKIP: | |
1687 | if (index + 2 >= fw_size) { | |
1688 | netif_err(tp, probe, tp->dev, | |
1689 | "Out of range of firmware\n"); | |
1690 | return; | |
1691 | } | |
1692 | break; | |
1693 | case PHY_COMP_EQ_SKIPN: | |
1694 | case PHY_COMP_NEQ_SKIPN: | |
1695 | case PHY_SKIPN: | |
1696 | if (index + 1 + regno >= fw_size) { | |
1697 | netif_err(tp, probe, tp->dev, | |
1698 | "Out of range of firmware\n"); | |
1699 | return; | |
1700 | } | |
bca03d5f | 1701 | break; |
1702 | ||
42b82dc1 | 1703 | case PHY_READ_MAC_BYTE: |
1704 | case PHY_WRITE_MAC_BYTE: | |
1705 | case PHY_WRITE_ERI_WORD: | |
1706 | default: | |
1707 | netif_err(tp, probe, tp->dev, | |
1708 | "Invalid action 0x%08x\n", action); | |
bca03d5f | 1709 | return; |
1710 | } | |
1711 | } | |
1712 | ||
42b82dc1 | 1713 | predata = 0; |
1714 | count = 0; | |
1715 | ||
1716 | for (index = 0; index < fw_size; ) { | |
1717 | u32 action = le32_to_cpu(phytable[index]); | |
bca03d5f | 1718 | u32 data = action & 0x0000ffff; |
42b82dc1 | 1719 | u32 regno = (action & 0x0fff0000) >> 16; |
1720 | ||
1721 | if (!action) | |
1722 | break; | |
bca03d5f | 1723 | |
1724 | switch(action & 0xf0000000) { | |
42b82dc1 | 1725 | case PHY_READ: |
1726 | predata = rtl_readphy(tp, regno); | |
1727 | count++; | |
1728 | index++; | |
1729 | break; | |
1730 | case PHY_DATA_OR: | |
1731 | predata |= data; | |
1732 | index++; | |
1733 | break; | |
1734 | case PHY_DATA_AND: | |
1735 | predata &= data; | |
1736 | index++; | |
1737 | break; | |
1738 | case PHY_BJMPN: | |
1739 | index -= regno; | |
1740 | break; | |
1741 | case PHY_READ_EFUSE: | |
1742 | predata = rtl8168d_efuse_read(tp->mmio_addr, regno); | |
1743 | index++; | |
1744 | break; | |
1745 | case PHY_CLEAR_READCOUNT: | |
1746 | count = 0; | |
1747 | index++; | |
1748 | break; | |
bca03d5f | 1749 | case PHY_WRITE: |
42b82dc1 | 1750 | rtl_writephy(tp, regno, data); |
1751 | index++; | |
1752 | break; | |
1753 | case PHY_READCOUNT_EQ_SKIP: | |
1754 | if (count == data) | |
1755 | index += 2; | |
1756 | else | |
1757 | index += 1; | |
bca03d5f | 1758 | break; |
42b82dc1 | 1759 | case PHY_COMP_EQ_SKIPN: |
1760 | if (predata == data) | |
1761 | index += regno; | |
1762 | index++; | |
1763 | break; | |
1764 | case PHY_COMP_NEQ_SKIPN: | |
1765 | if (predata != data) | |
1766 | index += regno; | |
1767 | index++; | |
1768 | break; | |
1769 | case PHY_WRITE_PREVIOUS: | |
1770 | rtl_writephy(tp, regno, predata); | |
1771 | index++; | |
1772 | break; | |
1773 | case PHY_SKIPN: | |
1774 | index += regno + 1; | |
1775 | break; | |
1776 | case PHY_DELAY_MS: | |
1777 | mdelay(data); | |
1778 | index++; | |
1779 | break; | |
1780 | ||
1781 | case PHY_READ_MAC_BYTE: | |
1782 | case PHY_WRITE_MAC_BYTE: | |
1783 | case PHY_WRITE_ERI_WORD: | |
bca03d5f | 1784 | default: |
1785 | BUG(); | |
1786 | } | |
1787 | } | |
1788 | } | |
1789 | ||
f1e02ed1 | 1790 | static void rtl_release_firmware(struct rtl8169_private *tp) |
1791 | { | |
1792 | release_firmware(tp->fw); | |
1793 | tp->fw = NULL; | |
1794 | } | |
1795 | ||
1796 | static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name) | |
1797 | { | |
1798 | const struct firmware **fw = &tp->fw; | |
1799 | int rc = !*fw; | |
1800 | ||
1801 | if (rc) { | |
1802 | rc = request_firmware(fw, fw_name, &tp->pci_dev->dev); | |
1803 | if (rc < 0) | |
1804 | goto out; | |
1805 | } | |
1806 | ||
1807 | /* TODO: release firmware once rtl_phy_write_fw signals failures. */ | |
1808 | rtl_phy_write_fw(tp, *fw); | |
1809 | out: | |
1810 | return rc; | |
1811 | } | |
1812 | ||
4da19633 | 1813 | static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
1da177e4 | 1814 | { |
350f7596 | 1815 | static const struct phy_reg phy_reg_init[] = { |
0b9b571d | 1816 | { 0x1f, 0x0001 }, |
1817 | { 0x06, 0x006e }, | |
1818 | { 0x08, 0x0708 }, | |
1819 | { 0x15, 0x4000 }, | |
1820 | { 0x18, 0x65c7 }, | |
1da177e4 | 1821 | |
0b9b571d | 1822 | { 0x1f, 0x0001 }, |
1823 | { 0x03, 0x00a1 }, | |
1824 | { 0x02, 0x0008 }, | |
1825 | { 0x01, 0x0120 }, | |
1826 | { 0x00, 0x1000 }, | |
1827 | { 0x04, 0x0800 }, | |
1828 | { 0x04, 0x0000 }, | |
1da177e4 | 1829 | |
0b9b571d | 1830 | { 0x03, 0xff41 }, |
1831 | { 0x02, 0xdf60 }, | |
1832 | { 0x01, 0x0140 }, | |
1833 | { 0x00, 0x0077 }, | |
1834 | { 0x04, 0x7800 }, | |
1835 | { 0x04, 0x7000 }, | |
1836 | ||
1837 | { 0x03, 0x802f }, | |
1838 | { 0x02, 0x4f02 }, | |
1839 | { 0x01, 0x0409 }, | |
1840 | { 0x00, 0xf0f9 }, | |
1841 | { 0x04, 0x9800 }, | |
1842 | { 0x04, 0x9000 }, | |
1843 | ||
1844 | { 0x03, 0xdf01 }, | |
1845 | { 0x02, 0xdf20 }, | |
1846 | { 0x01, 0xff95 }, | |
1847 | { 0x00, 0xba00 }, | |
1848 | { 0x04, 0xa800 }, | |
1849 | { 0x04, 0xa000 }, | |
1850 | ||
1851 | { 0x03, 0xff41 }, | |
1852 | { 0x02, 0xdf20 }, | |
1853 | { 0x01, 0x0140 }, | |
1854 | { 0x00, 0x00bb }, | |
1855 | { 0x04, 0xb800 }, | |
1856 | { 0x04, 0xb000 }, | |
1857 | ||
1858 | { 0x03, 0xdf41 }, | |
1859 | { 0x02, 0xdc60 }, | |
1860 | { 0x01, 0x6340 }, | |
1861 | { 0x00, 0x007d }, | |
1862 | { 0x04, 0xd800 }, | |
1863 | { 0x04, 0xd000 }, | |
1864 | ||
1865 | { 0x03, 0xdf01 }, | |
1866 | { 0x02, 0xdf20 }, | |
1867 | { 0x01, 0x100a }, | |
1868 | { 0x00, 0xa0ff }, | |
1869 | { 0x04, 0xf800 }, | |
1870 | { 0x04, 0xf000 }, | |
1871 | ||
1872 | { 0x1f, 0x0000 }, | |
1873 | { 0x0b, 0x0000 }, | |
1874 | { 0x00, 0x9200 } | |
1875 | }; | |
1da177e4 | 1876 | |
4da19633 | 1877 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1da177e4 LT |
1878 | } |
1879 | ||
4da19633 | 1880 | static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
5615d9f1 | 1881 | { |
350f7596 | 1882 | static const struct phy_reg phy_reg_init[] = { |
a441d7b6 FR |
1883 | { 0x1f, 0x0002 }, |
1884 | { 0x01, 0x90d0 }, | |
1885 | { 0x1f, 0x0000 } | |
1886 | }; | |
1887 | ||
4da19633 | 1888 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5615d9f1 FR |
1889 | } |
1890 | ||
4da19633 | 1891 | static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
2e955856 | 1892 | { |
1893 | struct pci_dev *pdev = tp->pci_dev; | |
1894 | u16 vendor_id, device_id; | |
1895 | ||
1896 | pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id); | |
1897 | pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id); | |
1898 | ||
1899 | if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000)) | |
1900 | return; | |
1901 | ||
4da19633 | 1902 | rtl_writephy(tp, 0x1f, 0x0001); |
1903 | rtl_writephy(tp, 0x10, 0xf01b); | |
1904 | rtl_writephy(tp, 0x1f, 0x0000); | |
2e955856 | 1905 | } |
1906 | ||
4da19633 | 1907 | static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
2e955856 | 1908 | { |
350f7596 | 1909 | static const struct phy_reg phy_reg_init[] = { |
2e955856 | 1910 | { 0x1f, 0x0001 }, |
1911 | { 0x04, 0x0000 }, | |
1912 | { 0x03, 0x00a1 }, | |
1913 | { 0x02, 0x0008 }, | |
1914 | { 0x01, 0x0120 }, | |
1915 | { 0x00, 0x1000 }, | |
1916 | { 0x04, 0x0800 }, | |
1917 | { 0x04, 0x9000 }, | |
1918 | { 0x03, 0x802f }, | |
1919 | { 0x02, 0x4f02 }, | |
1920 | { 0x01, 0x0409 }, | |
1921 | { 0x00, 0xf099 }, | |
1922 | { 0x04, 0x9800 }, | |
1923 | { 0x04, 0xa000 }, | |
1924 | { 0x03, 0xdf01 }, | |
1925 | { 0x02, 0xdf20 }, | |
1926 | { 0x01, 0xff95 }, | |
1927 | { 0x00, 0xba00 }, | |
1928 | { 0x04, 0xa800 }, | |
1929 | { 0x04, 0xf000 }, | |
1930 | { 0x03, 0xdf01 }, | |
1931 | { 0x02, 0xdf20 }, | |
1932 | { 0x01, 0x101a }, | |
1933 | { 0x00, 0xa0ff }, | |
1934 | { 0x04, 0xf800 }, | |
1935 | { 0x04, 0x0000 }, | |
1936 | { 0x1f, 0x0000 }, | |
1937 | ||
1938 | { 0x1f, 0x0001 }, | |
1939 | { 0x10, 0xf41b }, | |
1940 | { 0x14, 0xfb54 }, | |
1941 | { 0x18, 0xf5c7 }, | |
1942 | { 0x1f, 0x0000 }, | |
1943 | ||
1944 | { 0x1f, 0x0001 }, | |
1945 | { 0x17, 0x0cc0 }, | |
1946 | { 0x1f, 0x0000 } | |
1947 | }; | |
1948 | ||
4da19633 | 1949 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2e955856 | 1950 | |
4da19633 | 1951 | rtl8169scd_hw_phy_config_quirk(tp); |
2e955856 | 1952 | } |
1953 | ||
4da19633 | 1954 | static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
8c7006aa | 1955 | { |
350f7596 | 1956 | static const struct phy_reg phy_reg_init[] = { |
8c7006aa | 1957 | { 0x1f, 0x0001 }, |
1958 | { 0x04, 0x0000 }, | |
1959 | { 0x03, 0x00a1 }, | |
1960 | { 0x02, 0x0008 }, | |
1961 | { 0x01, 0x0120 }, | |
1962 | { 0x00, 0x1000 }, | |
1963 | { 0x04, 0x0800 }, | |
1964 | { 0x04, 0x9000 }, | |
1965 | { 0x03, 0x802f }, | |
1966 | { 0x02, 0x4f02 }, | |
1967 | { 0x01, 0x0409 }, | |
1968 | { 0x00, 0xf099 }, | |
1969 | { 0x04, 0x9800 }, | |
1970 | { 0x04, 0xa000 }, | |
1971 | { 0x03, 0xdf01 }, | |
1972 | { 0x02, 0xdf20 }, | |
1973 | { 0x01, 0xff95 }, | |
1974 | { 0x00, 0xba00 }, | |
1975 | { 0x04, 0xa800 }, | |
1976 | { 0x04, 0xf000 }, | |
1977 | { 0x03, 0xdf01 }, | |
1978 | { 0x02, 0xdf20 }, | |
1979 | { 0x01, 0x101a }, | |
1980 | { 0x00, 0xa0ff }, | |
1981 | { 0x04, 0xf800 }, | |
1982 | { 0x04, 0x0000 }, | |
1983 | { 0x1f, 0x0000 }, | |
1984 | ||
1985 | { 0x1f, 0x0001 }, | |
1986 | { 0x0b, 0x8480 }, | |
1987 | { 0x1f, 0x0000 }, | |
1988 | ||
1989 | { 0x1f, 0x0001 }, | |
1990 | { 0x18, 0x67c7 }, | |
1991 | { 0x04, 0x2000 }, | |
1992 | { 0x03, 0x002f }, | |
1993 | { 0x02, 0x4360 }, | |
1994 | { 0x01, 0x0109 }, | |
1995 | { 0x00, 0x3022 }, | |
1996 | { 0x04, 0x2800 }, | |
1997 | { 0x1f, 0x0000 }, | |
1998 | ||
1999 | { 0x1f, 0x0001 }, | |
2000 | { 0x17, 0x0cc0 }, | |
2001 | { 0x1f, 0x0000 } | |
2002 | }; | |
2003 | ||
4da19633 | 2004 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
8c7006aa | 2005 | } |
2006 | ||
4da19633 | 2007 | static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2008 | { |
350f7596 | 2009 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2010 | { 0x10, 0xf41b }, |
2011 | { 0x1f, 0x0000 } | |
2012 | }; | |
2013 | ||
4da19633 | 2014 | rtl_writephy(tp, 0x1f, 0x0001); |
2015 | rtl_patchphy(tp, 0x16, 1 << 0); | |
236b8082 | 2016 | |
4da19633 | 2017 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2018 | } |
2019 | ||
4da19633 | 2020 | static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2021 | { |
350f7596 | 2022 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2023 | { 0x1f, 0x0001 }, |
2024 | { 0x10, 0xf41b }, | |
2025 | { 0x1f, 0x0000 } | |
2026 | }; | |
2027 | ||
4da19633 | 2028 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2029 | } |
2030 | ||
4da19633 | 2031 | static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2032 | { |
350f7596 | 2033 | static const struct phy_reg phy_reg_init[] = { |
867763c1 FR |
2034 | { 0x1f, 0x0000 }, |
2035 | { 0x1d, 0x0f00 }, | |
2036 | { 0x1f, 0x0002 }, | |
2037 | { 0x0c, 0x1ec8 }, | |
2038 | { 0x1f, 0x0000 } | |
2039 | }; | |
2040 | ||
4da19633 | 2041 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
867763c1 FR |
2042 | } |
2043 | ||
4da19633 | 2044 | static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
ef3386f0 | 2045 | { |
350f7596 | 2046 | static const struct phy_reg phy_reg_init[] = { |
ef3386f0 FR |
2047 | { 0x1f, 0x0001 }, |
2048 | { 0x1d, 0x3d98 }, | |
2049 | { 0x1f, 0x0000 } | |
2050 | }; | |
2051 | ||
4da19633 | 2052 | rtl_writephy(tp, 0x1f, 0x0000); |
2053 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2054 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
ef3386f0 | 2055 | |
4da19633 | 2056 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
ef3386f0 FR |
2057 | } |
2058 | ||
4da19633 | 2059 | static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2060 | { |
350f7596 | 2061 | static const struct phy_reg phy_reg_init[] = { |
a3f80671 FR |
2062 | { 0x1f, 0x0001 }, |
2063 | { 0x12, 0x2300 }, | |
867763c1 FR |
2064 | { 0x1f, 0x0002 }, |
2065 | { 0x00, 0x88d4 }, | |
2066 | { 0x01, 0x82b1 }, | |
2067 | { 0x03, 0x7002 }, | |
2068 | { 0x08, 0x9e30 }, | |
2069 | { 0x09, 0x01f0 }, | |
2070 | { 0x0a, 0x5500 }, | |
2071 | { 0x0c, 0x00c8 }, | |
2072 | { 0x1f, 0x0003 }, | |
2073 | { 0x12, 0xc096 }, | |
2074 | { 0x16, 0x000a }, | |
f50d4275 FR |
2075 | { 0x1f, 0x0000 }, |
2076 | { 0x1f, 0x0000 }, | |
2077 | { 0x09, 0x2000 }, | |
2078 | { 0x09, 0x0000 } | |
867763c1 FR |
2079 | }; |
2080 | ||
4da19633 | 2081 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2082 | |
4da19633 | 2083 | rtl_patchphy(tp, 0x14, 1 << 5); |
2084 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2085 | rtl_writephy(tp, 0x1f, 0x0000); | |
867763c1 FR |
2086 | } |
2087 | ||
4da19633 | 2088 | static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
7da97ec9 | 2089 | { |
350f7596 | 2090 | static const struct phy_reg phy_reg_init[] = { |
f50d4275 | 2091 | { 0x1f, 0x0001 }, |
7da97ec9 | 2092 | { 0x12, 0x2300 }, |
f50d4275 FR |
2093 | { 0x03, 0x802f }, |
2094 | { 0x02, 0x4f02 }, | |
2095 | { 0x01, 0x0409 }, | |
2096 | { 0x00, 0xf099 }, | |
2097 | { 0x04, 0x9800 }, | |
2098 | { 0x04, 0x9000 }, | |
2099 | { 0x1d, 0x3d98 }, | |
7da97ec9 FR |
2100 | { 0x1f, 0x0002 }, |
2101 | { 0x0c, 0x7eb8 }, | |
f50d4275 FR |
2102 | { 0x06, 0x0761 }, |
2103 | { 0x1f, 0x0003 }, | |
2104 | { 0x16, 0x0f0a }, | |
7da97ec9 FR |
2105 | { 0x1f, 0x0000 } |
2106 | }; | |
2107 | ||
4da19633 | 2108 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2109 | |
4da19633 | 2110 | rtl_patchphy(tp, 0x16, 1 << 0); |
2111 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2112 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2113 | rtl_writephy(tp, 0x1f, 0x0000); | |
7da97ec9 FR |
2114 | } |
2115 | ||
4da19633 | 2116 | static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
197ff761 | 2117 | { |
350f7596 | 2118 | static const struct phy_reg phy_reg_init[] = { |
197ff761 FR |
2119 | { 0x1f, 0x0001 }, |
2120 | { 0x12, 0x2300 }, | |
2121 | { 0x1d, 0x3d98 }, | |
2122 | { 0x1f, 0x0002 }, | |
2123 | { 0x0c, 0x7eb8 }, | |
2124 | { 0x06, 0x5461 }, | |
2125 | { 0x1f, 0x0003 }, | |
2126 | { 0x16, 0x0f0a }, | |
2127 | { 0x1f, 0x0000 } | |
2128 | }; | |
2129 | ||
4da19633 | 2130 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
197ff761 | 2131 | |
4da19633 | 2132 | rtl_patchphy(tp, 0x16, 1 << 0); |
2133 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2134 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2135 | rtl_writephy(tp, 0x1f, 0x0000); | |
197ff761 FR |
2136 | } |
2137 | ||
4da19633 | 2138 | static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
6fb07058 | 2139 | { |
4da19633 | 2140 | rtl8168c_3_hw_phy_config(tp); |
6fb07058 FR |
2141 | } |
2142 | ||
bca03d5f | 2143 | static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
5b538df9 | 2144 | { |
350f7596 | 2145 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 2146 | /* Channel Estimation */ |
5b538df9 | 2147 | { 0x1f, 0x0001 }, |
daf9df6d | 2148 | { 0x06, 0x4064 }, |
2149 | { 0x07, 0x2863 }, | |
2150 | { 0x08, 0x059c }, | |
2151 | { 0x09, 0x26b4 }, | |
2152 | { 0x0a, 0x6a19 }, | |
2153 | { 0x0b, 0xdcc8 }, | |
2154 | { 0x10, 0xf06d }, | |
2155 | { 0x14, 0x7f68 }, | |
2156 | { 0x18, 0x7fd9 }, | |
2157 | { 0x1c, 0xf0ff }, | |
2158 | { 0x1d, 0x3d9c }, | |
5b538df9 | 2159 | { 0x1f, 0x0003 }, |
daf9df6d | 2160 | { 0x12, 0xf49f }, |
2161 | { 0x13, 0x070b }, | |
2162 | { 0x1a, 0x05ad }, | |
bca03d5f | 2163 | { 0x14, 0x94c0 }, |
2164 | ||
2165 | /* | |
2166 | * Tx Error Issue | |
2167 | * enhance line driver power | |
2168 | */ | |
5b538df9 | 2169 | { 0x1f, 0x0002 }, |
daf9df6d | 2170 | { 0x06, 0x5561 }, |
2171 | { 0x1f, 0x0005 }, | |
2172 | { 0x05, 0x8332 }, | |
bca03d5f | 2173 | { 0x06, 0x5561 }, |
2174 | ||
2175 | /* | |
2176 | * Can not link to 1Gbps with bad cable | |
2177 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
2178 | */ | |
2179 | { 0x1f, 0x0001 }, | |
2180 | { 0x17, 0x0cc0 }, | |
daf9df6d | 2181 | |
5b538df9 | 2182 | { 0x1f, 0x0000 }, |
bca03d5f | 2183 | { 0x0d, 0xf880 } |
daf9df6d | 2184 | }; |
bca03d5f | 2185 | void __iomem *ioaddr = tp->mmio_addr; |
daf9df6d | 2186 | |
4da19633 | 2187 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
daf9df6d | 2188 | |
bca03d5f | 2189 | /* |
2190 | * Rx Error Issue | |
2191 | * Fine Tune Switching regulator parameter | |
2192 | */ | |
4da19633 | 2193 | rtl_writephy(tp, 0x1f, 0x0002); |
2194 | rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); | |
2195 | rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); | |
daf9df6d | 2196 | |
daf9df6d | 2197 | if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
350f7596 | 2198 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2199 | { 0x1f, 0x0002 }, |
2200 | { 0x05, 0x669a }, | |
2201 | { 0x1f, 0x0005 }, | |
2202 | { 0x05, 0x8330 }, | |
2203 | { 0x06, 0x669a }, | |
2204 | { 0x1f, 0x0002 } | |
2205 | }; | |
2206 | int val; | |
2207 | ||
4da19633 | 2208 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2209 | |
4da19633 | 2210 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 2211 | |
2212 | if ((val & 0x00ff) != 0x006c) { | |
350f7596 | 2213 | static const u32 set[] = { |
daf9df6d | 2214 | 0x0065, 0x0066, 0x0067, 0x0068, |
2215 | 0x0069, 0x006a, 0x006b, 0x006c | |
2216 | }; | |
2217 | int i; | |
2218 | ||
4da19633 | 2219 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 2220 | |
2221 | val &= 0xff00; | |
2222 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 2223 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 2224 | } |
2225 | } else { | |
350f7596 | 2226 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2227 | { 0x1f, 0x0002 }, |
2228 | { 0x05, 0x6662 }, | |
2229 | { 0x1f, 0x0005 }, | |
2230 | { 0x05, 0x8330 }, | |
2231 | { 0x06, 0x6662 } | |
2232 | }; | |
2233 | ||
4da19633 | 2234 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2235 | } |
2236 | ||
bca03d5f | 2237 | /* RSET couple improve */ |
4da19633 | 2238 | rtl_writephy(tp, 0x1f, 0x0002); |
2239 | rtl_patchphy(tp, 0x0d, 0x0300); | |
2240 | rtl_patchphy(tp, 0x0f, 0x0010); | |
daf9df6d | 2241 | |
bca03d5f | 2242 | /* Fine tune PLL performance */ |
4da19633 | 2243 | rtl_writephy(tp, 0x1f, 0x0002); |
2244 | rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); | |
2245 | rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 2246 | |
4da19633 | 2247 | rtl_writephy(tp, 0x1f, 0x0005); |
2248 | rtl_writephy(tp, 0x05, 0x001b); | |
f1e02ed1 | 2249 | if ((rtl_readphy(tp, 0x06) != 0xbf00) || |
2250 | (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) { | |
bca03d5f | 2251 | netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n"); |
2252 | } | |
2253 | ||
4da19633 | 2254 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 2255 | } |
2256 | ||
bca03d5f | 2257 | static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 2258 | { |
350f7596 | 2259 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 2260 | /* Channel Estimation */ |
daf9df6d | 2261 | { 0x1f, 0x0001 }, |
2262 | { 0x06, 0x4064 }, | |
2263 | { 0x07, 0x2863 }, | |
2264 | { 0x08, 0x059c }, | |
2265 | { 0x09, 0x26b4 }, | |
2266 | { 0x0a, 0x6a19 }, | |
2267 | { 0x0b, 0xdcc8 }, | |
2268 | { 0x10, 0xf06d }, | |
2269 | { 0x14, 0x7f68 }, | |
2270 | { 0x18, 0x7fd9 }, | |
2271 | { 0x1c, 0xf0ff }, | |
2272 | { 0x1d, 0x3d9c }, | |
2273 | { 0x1f, 0x0003 }, | |
2274 | { 0x12, 0xf49f }, | |
2275 | { 0x13, 0x070b }, | |
2276 | { 0x1a, 0x05ad }, | |
2277 | { 0x14, 0x94c0 }, | |
2278 | ||
bca03d5f | 2279 | /* |
2280 | * Tx Error Issue | |
2281 | * enhance line driver power | |
2282 | */ | |
daf9df6d | 2283 | { 0x1f, 0x0002 }, |
2284 | { 0x06, 0x5561 }, | |
2285 | { 0x1f, 0x0005 }, | |
2286 | { 0x05, 0x8332 }, | |
bca03d5f | 2287 | { 0x06, 0x5561 }, |
2288 | ||
2289 | /* | |
2290 | * Can not link to 1Gbps with bad cable | |
2291 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
2292 | */ | |
2293 | { 0x1f, 0x0001 }, | |
2294 | { 0x17, 0x0cc0 }, | |
daf9df6d | 2295 | |
2296 | { 0x1f, 0x0000 }, | |
bca03d5f | 2297 | { 0x0d, 0xf880 } |
5b538df9 | 2298 | }; |
bca03d5f | 2299 | void __iomem *ioaddr = tp->mmio_addr; |
5b538df9 | 2300 | |
4da19633 | 2301 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
5b538df9 | 2302 | |
daf9df6d | 2303 | if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
350f7596 | 2304 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2305 | { 0x1f, 0x0002 }, |
2306 | { 0x05, 0x669a }, | |
5b538df9 | 2307 | { 0x1f, 0x0005 }, |
daf9df6d | 2308 | { 0x05, 0x8330 }, |
2309 | { 0x06, 0x669a }, | |
2310 | ||
2311 | { 0x1f, 0x0002 } | |
2312 | }; | |
2313 | int val; | |
2314 | ||
4da19633 | 2315 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2316 | |
4da19633 | 2317 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 2318 | if ((val & 0x00ff) != 0x006c) { |
b6bc7650 | 2319 | static const u32 set[] = { |
daf9df6d | 2320 | 0x0065, 0x0066, 0x0067, 0x0068, |
2321 | 0x0069, 0x006a, 0x006b, 0x006c | |
2322 | }; | |
2323 | int i; | |
2324 | ||
4da19633 | 2325 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 2326 | |
2327 | val &= 0xff00; | |
2328 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 2329 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 2330 | } |
2331 | } else { | |
350f7596 | 2332 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2333 | { 0x1f, 0x0002 }, |
2334 | { 0x05, 0x2642 }, | |
5b538df9 | 2335 | { 0x1f, 0x0005 }, |
daf9df6d | 2336 | { 0x05, 0x8330 }, |
2337 | { 0x06, 0x2642 } | |
5b538df9 FR |
2338 | }; |
2339 | ||
4da19633 | 2340 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
2341 | } |
2342 | ||
bca03d5f | 2343 | /* Fine tune PLL performance */ |
4da19633 | 2344 | rtl_writephy(tp, 0x1f, 0x0002); |
2345 | rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); | |
2346 | rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 2347 | |
bca03d5f | 2348 | /* Switching regulator Slew rate */ |
4da19633 | 2349 | rtl_writephy(tp, 0x1f, 0x0002); |
2350 | rtl_patchphy(tp, 0x0f, 0x0017); | |
daf9df6d | 2351 | |
4da19633 | 2352 | rtl_writephy(tp, 0x1f, 0x0005); |
2353 | rtl_writephy(tp, 0x05, 0x001b); | |
f1e02ed1 | 2354 | if ((rtl_readphy(tp, 0x06) != 0xb300) || |
2355 | (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) { | |
bca03d5f | 2356 | netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n"); |
2357 | } | |
2358 | ||
4da19633 | 2359 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 2360 | } |
2361 | ||
4da19633 | 2362 | static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 2363 | { |
350f7596 | 2364 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2365 | { 0x1f, 0x0002 }, |
2366 | { 0x10, 0x0008 }, | |
2367 | { 0x0d, 0x006c }, | |
2368 | ||
2369 | { 0x1f, 0x0000 }, | |
2370 | { 0x0d, 0xf880 }, | |
2371 | ||
2372 | { 0x1f, 0x0001 }, | |
2373 | { 0x17, 0x0cc0 }, | |
2374 | ||
2375 | { 0x1f, 0x0001 }, | |
2376 | { 0x0b, 0xa4d8 }, | |
2377 | { 0x09, 0x281c }, | |
2378 | { 0x07, 0x2883 }, | |
2379 | { 0x0a, 0x6b35 }, | |
2380 | { 0x1d, 0x3da4 }, | |
2381 | { 0x1c, 0xeffd }, | |
2382 | { 0x14, 0x7f52 }, | |
2383 | { 0x18, 0x7fc6 }, | |
2384 | { 0x08, 0x0601 }, | |
2385 | { 0x06, 0x4063 }, | |
2386 | { 0x10, 0xf074 }, | |
2387 | { 0x1f, 0x0003 }, | |
2388 | { 0x13, 0x0789 }, | |
2389 | { 0x12, 0xf4bd }, | |
2390 | { 0x1a, 0x04fd }, | |
2391 | { 0x14, 0x84b0 }, | |
2392 | { 0x1f, 0x0000 }, | |
2393 | { 0x00, 0x9200 }, | |
2394 | ||
2395 | { 0x1f, 0x0005 }, | |
2396 | { 0x01, 0x0340 }, | |
2397 | { 0x1f, 0x0001 }, | |
2398 | { 0x04, 0x4000 }, | |
2399 | { 0x03, 0x1d21 }, | |
2400 | { 0x02, 0x0c32 }, | |
2401 | { 0x01, 0x0200 }, | |
2402 | { 0x00, 0x5554 }, | |
2403 | { 0x04, 0x4800 }, | |
2404 | { 0x04, 0x4000 }, | |
2405 | { 0x04, 0xf000 }, | |
2406 | { 0x03, 0xdf01 }, | |
2407 | { 0x02, 0xdf20 }, | |
2408 | { 0x01, 0x101a }, | |
2409 | { 0x00, 0xa0ff }, | |
2410 | { 0x04, 0xf800 }, | |
2411 | { 0x04, 0xf000 }, | |
2412 | { 0x1f, 0x0000 }, | |
2413 | ||
2414 | { 0x1f, 0x0007 }, | |
2415 | { 0x1e, 0x0023 }, | |
2416 | { 0x16, 0x0000 }, | |
2417 | { 0x1f, 0x0000 } | |
2418 | }; | |
2419 | ||
4da19633 | 2420 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
2421 | } |
2422 | ||
e6de30d6 | 2423 | static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
2424 | { | |
2425 | static const struct phy_reg phy_reg_init[] = { | |
2426 | { 0x1f, 0x0001 }, | |
2427 | { 0x17, 0x0cc0 }, | |
2428 | ||
2429 | { 0x1f, 0x0007 }, | |
2430 | { 0x1e, 0x002d }, | |
2431 | { 0x18, 0x0040 }, | |
2432 | { 0x1f, 0x0000 } | |
2433 | }; | |
2434 | ||
2435 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
2436 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2437 | } | |
2438 | ||
4da19633 | 2439 | static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
2857ffb7 | 2440 | { |
350f7596 | 2441 | static const struct phy_reg phy_reg_init[] = { |
2857ffb7 FR |
2442 | { 0x1f, 0x0003 }, |
2443 | { 0x08, 0x441d }, | |
2444 | { 0x01, 0x9100 }, | |
2445 | { 0x1f, 0x0000 } | |
2446 | }; | |
2447 | ||
4da19633 | 2448 | rtl_writephy(tp, 0x1f, 0x0000); |
2449 | rtl_patchphy(tp, 0x11, 1 << 12); | |
2450 | rtl_patchphy(tp, 0x19, 1 << 13); | |
2451 | rtl_patchphy(tp, 0x10, 1 << 15); | |
2857ffb7 | 2452 | |
4da19633 | 2453 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2857ffb7 FR |
2454 | } |
2455 | ||
5a5e4443 HW |
2456 | static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
2457 | { | |
2458 | static const struct phy_reg phy_reg_init[] = { | |
2459 | { 0x1f, 0x0005 }, | |
2460 | { 0x1a, 0x0000 }, | |
2461 | { 0x1f, 0x0000 }, | |
2462 | ||
2463 | { 0x1f, 0x0004 }, | |
2464 | { 0x1c, 0x0000 }, | |
2465 | { 0x1f, 0x0000 }, | |
2466 | ||
2467 | { 0x1f, 0x0001 }, | |
2468 | { 0x15, 0x7701 }, | |
2469 | { 0x1f, 0x0000 } | |
2470 | }; | |
2471 | ||
2472 | /* Disable ALDPS before ram code */ | |
2473 | rtl_writephy(tp, 0x1f, 0x0000); | |
2474 | rtl_writephy(tp, 0x18, 0x0310); | |
2475 | msleep(100); | |
2476 | ||
2477 | if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0) | |
2478 | netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n"); | |
2479 | ||
2480 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
2481 | } | |
2482 | ||
5615d9f1 FR |
2483 | static void rtl_hw_phy_config(struct net_device *dev) |
2484 | { | |
2485 | struct rtl8169_private *tp = netdev_priv(dev); | |
5615d9f1 FR |
2486 | |
2487 | rtl8169_print_mac_version(tp); | |
2488 | ||
2489 | switch (tp->mac_version) { | |
2490 | case RTL_GIGA_MAC_VER_01: | |
2491 | break; | |
2492 | case RTL_GIGA_MAC_VER_02: | |
2493 | case RTL_GIGA_MAC_VER_03: | |
4da19633 | 2494 | rtl8169s_hw_phy_config(tp); |
5615d9f1 FR |
2495 | break; |
2496 | case RTL_GIGA_MAC_VER_04: | |
4da19633 | 2497 | rtl8169sb_hw_phy_config(tp); |
5615d9f1 | 2498 | break; |
2e955856 | 2499 | case RTL_GIGA_MAC_VER_05: |
4da19633 | 2500 | rtl8169scd_hw_phy_config(tp); |
2e955856 | 2501 | break; |
8c7006aa | 2502 | case RTL_GIGA_MAC_VER_06: |
4da19633 | 2503 | rtl8169sce_hw_phy_config(tp); |
8c7006aa | 2504 | break; |
2857ffb7 FR |
2505 | case RTL_GIGA_MAC_VER_07: |
2506 | case RTL_GIGA_MAC_VER_08: | |
2507 | case RTL_GIGA_MAC_VER_09: | |
4da19633 | 2508 | rtl8102e_hw_phy_config(tp); |
2857ffb7 | 2509 | break; |
236b8082 | 2510 | case RTL_GIGA_MAC_VER_11: |
4da19633 | 2511 | rtl8168bb_hw_phy_config(tp); |
236b8082 FR |
2512 | break; |
2513 | case RTL_GIGA_MAC_VER_12: | |
4da19633 | 2514 | rtl8168bef_hw_phy_config(tp); |
236b8082 FR |
2515 | break; |
2516 | case RTL_GIGA_MAC_VER_17: | |
4da19633 | 2517 | rtl8168bef_hw_phy_config(tp); |
236b8082 | 2518 | break; |
867763c1 | 2519 | case RTL_GIGA_MAC_VER_18: |
4da19633 | 2520 | rtl8168cp_1_hw_phy_config(tp); |
867763c1 FR |
2521 | break; |
2522 | case RTL_GIGA_MAC_VER_19: | |
4da19633 | 2523 | rtl8168c_1_hw_phy_config(tp); |
867763c1 | 2524 | break; |
7da97ec9 | 2525 | case RTL_GIGA_MAC_VER_20: |
4da19633 | 2526 | rtl8168c_2_hw_phy_config(tp); |
7da97ec9 | 2527 | break; |
197ff761 | 2528 | case RTL_GIGA_MAC_VER_21: |
4da19633 | 2529 | rtl8168c_3_hw_phy_config(tp); |
197ff761 | 2530 | break; |
6fb07058 | 2531 | case RTL_GIGA_MAC_VER_22: |
4da19633 | 2532 | rtl8168c_4_hw_phy_config(tp); |
6fb07058 | 2533 | break; |
ef3386f0 | 2534 | case RTL_GIGA_MAC_VER_23: |
7f3e3d3a | 2535 | case RTL_GIGA_MAC_VER_24: |
4da19633 | 2536 | rtl8168cp_2_hw_phy_config(tp); |
ef3386f0 | 2537 | break; |
5b538df9 | 2538 | case RTL_GIGA_MAC_VER_25: |
bca03d5f | 2539 | rtl8168d_1_hw_phy_config(tp); |
daf9df6d | 2540 | break; |
2541 | case RTL_GIGA_MAC_VER_26: | |
bca03d5f | 2542 | rtl8168d_2_hw_phy_config(tp); |
daf9df6d | 2543 | break; |
2544 | case RTL_GIGA_MAC_VER_27: | |
4da19633 | 2545 | rtl8168d_3_hw_phy_config(tp); |
5b538df9 | 2546 | break; |
e6de30d6 | 2547 | case RTL_GIGA_MAC_VER_28: |
2548 | rtl8168d_4_hw_phy_config(tp); | |
2549 | break; | |
5a5e4443 HW |
2550 | case RTL_GIGA_MAC_VER_29: |
2551 | case RTL_GIGA_MAC_VER_30: | |
2552 | rtl8105e_hw_phy_config(tp); | |
2553 | break; | |
ef3386f0 | 2554 | |
5615d9f1 FR |
2555 | default: |
2556 | break; | |
2557 | } | |
2558 | } | |
2559 | ||
1da177e4 LT |
2560 | static void rtl8169_phy_timer(unsigned long __opaque) |
2561 | { | |
2562 | struct net_device *dev = (struct net_device *)__opaque; | |
2563 | struct rtl8169_private *tp = netdev_priv(dev); | |
2564 | struct timer_list *timer = &tp->timer; | |
2565 | void __iomem *ioaddr = tp->mmio_addr; | |
2566 | unsigned long timeout = RTL8169_PHY_TIMEOUT; | |
2567 | ||
bcf0bf90 | 2568 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 2569 | |
64e4bfb4 | 2570 | if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
1da177e4 LT |
2571 | return; |
2572 | ||
2573 | spin_lock_irq(&tp->lock); | |
2574 | ||
4da19633 | 2575 | if (tp->phy_reset_pending(tp)) { |
5b0384f4 | 2576 | /* |
1da177e4 LT |
2577 | * A busy loop could burn quite a few cycles on nowadays CPU. |
2578 | * Let's delay the execution of the timer for a few ticks. | |
2579 | */ | |
2580 | timeout = HZ/10; | |
2581 | goto out_mod_timer; | |
2582 | } | |
2583 | ||
2584 | if (tp->link_ok(ioaddr)) | |
2585 | goto out_unlock; | |
2586 | ||
bf82c189 | 2587 | netif_warn(tp, link, dev, "PHY reset until link up\n"); |
1da177e4 | 2588 | |
4da19633 | 2589 | tp->phy_reset_enable(tp); |
1da177e4 LT |
2590 | |
2591 | out_mod_timer: | |
2592 | mod_timer(timer, jiffies + timeout); | |
2593 | out_unlock: | |
2594 | spin_unlock_irq(&tp->lock); | |
2595 | } | |
2596 | ||
2597 | static inline void rtl8169_delete_timer(struct net_device *dev) | |
2598 | { | |
2599 | struct rtl8169_private *tp = netdev_priv(dev); | |
2600 | struct timer_list *timer = &tp->timer; | |
2601 | ||
e179bb7b | 2602 | if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
1da177e4 LT |
2603 | return; |
2604 | ||
2605 | del_timer_sync(timer); | |
2606 | } | |
2607 | ||
2608 | static inline void rtl8169_request_timer(struct net_device *dev) | |
2609 | { | |
2610 | struct rtl8169_private *tp = netdev_priv(dev); | |
2611 | struct timer_list *timer = &tp->timer; | |
2612 | ||
e179bb7b | 2613 | if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
1da177e4 LT |
2614 | return; |
2615 | ||
2efa53f3 | 2616 | mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); |
1da177e4 LT |
2617 | } |
2618 | ||
2619 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2620 | /* | |
2621 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
2622 | * without having to re-enable interrupts. It's not called while | |
2623 | * the interrupt routine is executing. | |
2624 | */ | |
2625 | static void rtl8169_netpoll(struct net_device *dev) | |
2626 | { | |
2627 | struct rtl8169_private *tp = netdev_priv(dev); | |
2628 | struct pci_dev *pdev = tp->pci_dev; | |
2629 | ||
2630 | disable_irq(pdev->irq); | |
7d12e780 | 2631 | rtl8169_interrupt(pdev->irq, dev); |
1da177e4 LT |
2632 | enable_irq(pdev->irq); |
2633 | } | |
2634 | #endif | |
2635 | ||
2636 | static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, | |
2637 | void __iomem *ioaddr) | |
2638 | { | |
2639 | iounmap(ioaddr); | |
2640 | pci_release_regions(pdev); | |
87aeec76 | 2641 | pci_clear_mwi(pdev); |
1da177e4 LT |
2642 | pci_disable_device(pdev); |
2643 | free_netdev(dev); | |
2644 | } | |
2645 | ||
bf793295 FR |
2646 | static void rtl8169_phy_reset(struct net_device *dev, |
2647 | struct rtl8169_private *tp) | |
2648 | { | |
07d3f51f | 2649 | unsigned int i; |
bf793295 | 2650 | |
4da19633 | 2651 | tp->phy_reset_enable(tp); |
bf793295 | 2652 | for (i = 0; i < 100; i++) { |
4da19633 | 2653 | if (!tp->phy_reset_pending(tp)) |
bf793295 FR |
2654 | return; |
2655 | msleep(1); | |
2656 | } | |
bf82c189 | 2657 | netif_err(tp, link, dev, "PHY reset failed\n"); |
bf793295 FR |
2658 | } |
2659 | ||
4ff96fa6 FR |
2660 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
2661 | { | |
2662 | void __iomem *ioaddr = tp->mmio_addr; | |
4ff96fa6 | 2663 | |
5615d9f1 | 2664 | rtl_hw_phy_config(dev); |
4ff96fa6 | 2665 | |
77332894 MS |
2666 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
2667 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
2668 | RTL_W8(0x82, 0x01); | |
2669 | } | |
4ff96fa6 | 2670 | |
6dccd16b FR |
2671 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
2672 | ||
2673 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
2674 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 2675 | |
bcf0bf90 | 2676 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 FR |
2677 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
2678 | RTL_W8(0x82, 0x01); | |
2679 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); | |
4da19633 | 2680 | rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
4ff96fa6 FR |
2681 | } |
2682 | ||
bf793295 FR |
2683 | rtl8169_phy_reset(dev, tp); |
2684 | ||
54405cde ON |
2685 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
2686 | ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
2687 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
db552b33 | 2688 | (tp->mii.supports_gmii ? |
54405cde | 2689 | ADVERTISED_1000baseT_Half | |
db552b33 | 2690 | ADVERTISED_1000baseT_Full : 0)); |
4ff96fa6 | 2691 | |
bf82c189 JP |
2692 | if (RTL_R8(PHYstatus) & TBI_Enable) |
2693 | netif_info(tp, link, dev, "TBI auto-negotiating\n"); | |
4ff96fa6 FR |
2694 | } |
2695 | ||
773d2021 FR |
2696 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
2697 | { | |
2698 | void __iomem *ioaddr = tp->mmio_addr; | |
2699 | u32 high; | |
2700 | u32 low; | |
2701 | ||
2702 | low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); | |
2703 | high = addr[4] | (addr[5] << 8); | |
2704 | ||
2705 | spin_lock_irq(&tp->lock); | |
2706 | ||
2707 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
908ba2bf | 2708 | |
773d2021 | 2709 | RTL_W32(MAC4, high); |
908ba2bf | 2710 | RTL_R32(MAC4); |
2711 | ||
78f1cd02 | 2712 | RTL_W32(MAC0, low); |
908ba2bf | 2713 | RTL_R32(MAC0); |
2714 | ||
773d2021 FR |
2715 | RTL_W8(Cfg9346, Cfg9346_Lock); |
2716 | ||
2717 | spin_unlock_irq(&tp->lock); | |
2718 | } | |
2719 | ||
2720 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
2721 | { | |
2722 | struct rtl8169_private *tp = netdev_priv(dev); | |
2723 | struct sockaddr *addr = p; | |
2724 | ||
2725 | if (!is_valid_ether_addr(addr->sa_data)) | |
2726 | return -EADDRNOTAVAIL; | |
2727 | ||
2728 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
2729 | ||
2730 | rtl_rar_set(tp, dev->dev_addr); | |
2731 | ||
2732 | return 0; | |
2733 | } | |
2734 | ||
5f787a1a FR |
2735 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
2736 | { | |
2737 | struct rtl8169_private *tp = netdev_priv(dev); | |
2738 | struct mii_ioctl_data *data = if_mii(ifr); | |
2739 | ||
8b4ab28d FR |
2740 | return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
2741 | } | |
5f787a1a | 2742 | |
8b4ab28d FR |
2743 | static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
2744 | { | |
5f787a1a FR |
2745 | switch (cmd) { |
2746 | case SIOCGMIIPHY: | |
2747 | data->phy_id = 32; /* Internal PHY */ | |
2748 | return 0; | |
2749 | ||
2750 | case SIOCGMIIREG: | |
4da19633 | 2751 | data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
5f787a1a FR |
2752 | return 0; |
2753 | ||
2754 | case SIOCSMIIREG: | |
4da19633 | 2755 | rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
5f787a1a FR |
2756 | return 0; |
2757 | } | |
2758 | return -EOPNOTSUPP; | |
2759 | } | |
2760 | ||
8b4ab28d FR |
2761 | static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
2762 | { | |
2763 | return -EOPNOTSUPP; | |
2764 | } | |
2765 | ||
0e485150 FR |
2766 | static const struct rtl_cfg_info { |
2767 | void (*hw_start)(struct net_device *); | |
2768 | unsigned int region; | |
2769 | unsigned int align; | |
2770 | u16 intr_event; | |
2771 | u16 napi_event; | |
ccdffb9a | 2772 | unsigned features; |
f21b75e9 | 2773 | u8 default_ver; |
0e485150 FR |
2774 | } rtl_cfg_infos [] = { |
2775 | [RTL_CFG_0] = { | |
2776 | .hw_start = rtl_hw_start_8169, | |
2777 | .region = 1, | |
e9f63f30 | 2778 | .align = 0, |
0e485150 FR |
2779 | .intr_event = SYSErr | LinkChg | RxOverflow | |
2780 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 2781 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
2782 | .features = RTL_FEATURE_GMII, |
2783 | .default_ver = RTL_GIGA_MAC_VER_01, | |
0e485150 FR |
2784 | }, |
2785 | [RTL_CFG_1] = { | |
2786 | .hw_start = rtl_hw_start_8168, | |
2787 | .region = 2, | |
2788 | .align = 8, | |
53f57357 | 2789 | .intr_event = SYSErr | LinkChg | RxOverflow | |
0e485150 | 2790 | TxErr | TxOK | RxOK | RxErr, |
fbac58fc | 2791 | .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
2792 | .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, |
2793 | .default_ver = RTL_GIGA_MAC_VER_11, | |
0e485150 FR |
2794 | }, |
2795 | [RTL_CFG_2] = { | |
2796 | .hw_start = rtl_hw_start_8101, | |
2797 | .region = 2, | |
2798 | .align = 8, | |
2799 | .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | | |
2800 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 2801 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
2802 | .features = RTL_FEATURE_MSI, |
2803 | .default_ver = RTL_GIGA_MAC_VER_13, | |
0e485150 FR |
2804 | } |
2805 | }; | |
2806 | ||
fbac58fc FR |
2807 | /* Cfg9346_Unlock assumed. */ |
2808 | static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, | |
2809 | const struct rtl_cfg_info *cfg) | |
2810 | { | |
2811 | unsigned msi = 0; | |
2812 | u8 cfg2; | |
2813 | ||
2814 | cfg2 = RTL_R8(Config2) & ~MSIEnable; | |
ccdffb9a | 2815 | if (cfg->features & RTL_FEATURE_MSI) { |
fbac58fc FR |
2816 | if (pci_enable_msi(pdev)) { |
2817 | dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); | |
2818 | } else { | |
2819 | cfg2 |= MSIEnable; | |
2820 | msi = RTL_FEATURE_MSI; | |
2821 | } | |
2822 | } | |
2823 | RTL_W8(Config2, cfg2); | |
2824 | return msi; | |
2825 | } | |
2826 | ||
2827 | static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) | |
2828 | { | |
2829 | if (tp->features & RTL_FEATURE_MSI) { | |
2830 | pci_disable_msi(pdev); | |
2831 | tp->features &= ~RTL_FEATURE_MSI; | |
2832 | } | |
2833 | } | |
2834 | ||
8b4ab28d FR |
2835 | static const struct net_device_ops rtl8169_netdev_ops = { |
2836 | .ndo_open = rtl8169_open, | |
2837 | .ndo_stop = rtl8169_close, | |
2838 | .ndo_get_stats = rtl8169_get_stats, | |
00829823 | 2839 | .ndo_start_xmit = rtl8169_start_xmit, |
8b4ab28d FR |
2840 | .ndo_tx_timeout = rtl8169_tx_timeout, |
2841 | .ndo_validate_addr = eth_validate_addr, | |
2842 | .ndo_change_mtu = rtl8169_change_mtu, | |
2843 | .ndo_set_mac_address = rtl_set_mac_address, | |
2844 | .ndo_do_ioctl = rtl8169_ioctl, | |
2845 | .ndo_set_multicast_list = rtl_set_rx_mode, | |
8b4ab28d FR |
2846 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2847 | .ndo_poll_controller = rtl8169_netpoll, | |
2848 | #endif | |
2849 | ||
2850 | }; | |
2851 | ||
c0e45c1c | 2852 | static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp) |
2853 | { | |
2854 | struct mdio_ops *ops = &tp->mdio_ops; | |
2855 | ||
2856 | switch (tp->mac_version) { | |
2857 | case RTL_GIGA_MAC_VER_27: | |
2858 | ops->write = r8168dp_1_mdio_write; | |
2859 | ops->read = r8168dp_1_mdio_read; | |
2860 | break; | |
e6de30d6 | 2861 | case RTL_GIGA_MAC_VER_28: |
2862 | ops->write = r8168dp_2_mdio_write; | |
2863 | ops->read = r8168dp_2_mdio_read; | |
2864 | break; | |
c0e45c1c | 2865 | default: |
2866 | ops->write = r8169_mdio_write; | |
2867 | ops->read = r8169_mdio_read; | |
2868 | break; | |
2869 | } | |
2870 | } | |
2871 | ||
065c27c1 | 2872 | static void r810x_phy_power_down(struct rtl8169_private *tp) |
2873 | { | |
2874 | rtl_writephy(tp, 0x1f, 0x0000); | |
2875 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
2876 | } | |
2877 | ||
2878 | static void r810x_phy_power_up(struct rtl8169_private *tp) | |
2879 | { | |
2880 | rtl_writephy(tp, 0x1f, 0x0000); | |
2881 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); | |
2882 | } | |
2883 | ||
2884 | static void r810x_pll_power_down(struct rtl8169_private *tp) | |
2885 | { | |
2886 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { | |
2887 | rtl_writephy(tp, 0x1f, 0x0000); | |
2888 | rtl_writephy(tp, MII_BMCR, 0x0000); | |
2889 | return; | |
2890 | } | |
2891 | ||
2892 | r810x_phy_power_down(tp); | |
2893 | } | |
2894 | ||
2895 | static void r810x_pll_power_up(struct rtl8169_private *tp) | |
2896 | { | |
2897 | r810x_phy_power_up(tp); | |
2898 | } | |
2899 | ||
2900 | static void r8168_phy_power_up(struct rtl8169_private *tp) | |
2901 | { | |
2902 | rtl_writephy(tp, 0x1f, 0x0000); | |
2903 | rtl_writephy(tp, 0x0e, 0x0000); | |
2904 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); | |
2905 | } | |
2906 | ||
2907 | static void r8168_phy_power_down(struct rtl8169_private *tp) | |
2908 | { | |
2909 | rtl_writephy(tp, 0x1f, 0x0000); | |
2910 | rtl_writephy(tp, 0x0e, 0x0200); | |
2911 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
2912 | } | |
2913 | ||
2914 | static void r8168_pll_power_down(struct rtl8169_private *tp) | |
2915 | { | |
2916 | void __iomem *ioaddr = tp->mmio_addr; | |
2917 | ||
5d2e1957 HW |
2918 | if (((tp->mac_version == RTL_GIGA_MAC_VER_27) || |
2919 | (tp->mac_version == RTL_GIGA_MAC_VER_28)) && | |
2920 | (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) { | |
065c27c1 | 2921 | return; |
5d2e1957 | 2922 | } |
065c27c1 | 2923 | |
2924 | if (((tp->mac_version == RTL_GIGA_MAC_VER_23) || | |
2925 | (tp->mac_version == RTL_GIGA_MAC_VER_24)) && | |
2926 | (RTL_R16(CPlusCmd) & ASF)) { | |
2927 | return; | |
2928 | } | |
2929 | ||
2930 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { | |
2931 | rtl_writephy(tp, 0x1f, 0x0000); | |
2932 | rtl_writephy(tp, MII_BMCR, 0x0000); | |
2933 | ||
2934 | RTL_W32(RxConfig, RTL_R32(RxConfig) | | |
2935 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); | |
2936 | return; | |
2937 | } | |
2938 | ||
2939 | r8168_phy_power_down(tp); | |
2940 | ||
2941 | switch (tp->mac_version) { | |
2942 | case RTL_GIGA_MAC_VER_25: | |
2943 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
2944 | case RTL_GIGA_MAC_VER_27: |
2945 | case RTL_GIGA_MAC_VER_28: | |
065c27c1 | 2946 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
2947 | break; | |
2948 | } | |
2949 | } | |
2950 | ||
2951 | static void r8168_pll_power_up(struct rtl8169_private *tp) | |
2952 | { | |
2953 | void __iomem *ioaddr = tp->mmio_addr; | |
2954 | ||
5d2e1957 HW |
2955 | if (((tp->mac_version == RTL_GIGA_MAC_VER_27) || |
2956 | (tp->mac_version == RTL_GIGA_MAC_VER_28)) && | |
2957 | (ocp_read(tp, 0x0f, 0x0010) & 0x00008000)) { | |
065c27c1 | 2958 | return; |
5d2e1957 | 2959 | } |
065c27c1 | 2960 | |
2961 | switch (tp->mac_version) { | |
2962 | case RTL_GIGA_MAC_VER_25: | |
2963 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
2964 | case RTL_GIGA_MAC_VER_27: |
2965 | case RTL_GIGA_MAC_VER_28: | |
065c27c1 | 2966 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
2967 | break; | |
2968 | } | |
2969 | ||
2970 | r8168_phy_power_up(tp); | |
2971 | } | |
2972 | ||
2973 | static void rtl_pll_power_op(struct rtl8169_private *tp, | |
2974 | void (*op)(struct rtl8169_private *)) | |
2975 | { | |
2976 | if (op) | |
2977 | op(tp); | |
2978 | } | |
2979 | ||
2980 | static void rtl_pll_power_down(struct rtl8169_private *tp) | |
2981 | { | |
2982 | rtl_pll_power_op(tp, tp->pll_power_ops.down); | |
2983 | } | |
2984 | ||
2985 | static void rtl_pll_power_up(struct rtl8169_private *tp) | |
2986 | { | |
2987 | rtl_pll_power_op(tp, tp->pll_power_ops.up); | |
2988 | } | |
2989 | ||
2990 | static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) | |
2991 | { | |
2992 | struct pll_power_ops *ops = &tp->pll_power_ops; | |
2993 | ||
2994 | switch (tp->mac_version) { | |
2995 | case RTL_GIGA_MAC_VER_07: | |
2996 | case RTL_GIGA_MAC_VER_08: | |
2997 | case RTL_GIGA_MAC_VER_09: | |
2998 | case RTL_GIGA_MAC_VER_10: | |
2999 | case RTL_GIGA_MAC_VER_16: | |
5a5e4443 HW |
3000 | case RTL_GIGA_MAC_VER_29: |
3001 | case RTL_GIGA_MAC_VER_30: | |
065c27c1 | 3002 | ops->down = r810x_pll_power_down; |
3003 | ops->up = r810x_pll_power_up; | |
3004 | break; | |
3005 | ||
3006 | case RTL_GIGA_MAC_VER_11: | |
3007 | case RTL_GIGA_MAC_VER_12: | |
3008 | case RTL_GIGA_MAC_VER_17: | |
3009 | case RTL_GIGA_MAC_VER_18: | |
3010 | case RTL_GIGA_MAC_VER_19: | |
3011 | case RTL_GIGA_MAC_VER_20: | |
3012 | case RTL_GIGA_MAC_VER_21: | |
3013 | case RTL_GIGA_MAC_VER_22: | |
3014 | case RTL_GIGA_MAC_VER_23: | |
3015 | case RTL_GIGA_MAC_VER_24: | |
3016 | case RTL_GIGA_MAC_VER_25: | |
3017 | case RTL_GIGA_MAC_VER_26: | |
3018 | case RTL_GIGA_MAC_VER_27: | |
e6de30d6 | 3019 | case RTL_GIGA_MAC_VER_28: |
065c27c1 | 3020 | ops->down = r8168_pll_power_down; |
3021 | ops->up = r8168_pll_power_up; | |
3022 | break; | |
3023 | ||
3024 | default: | |
3025 | ops->down = NULL; | |
3026 | ops->up = NULL; | |
3027 | break; | |
3028 | } | |
3029 | } | |
3030 | ||
1da177e4 | 3031 | static int __devinit |
4ff96fa6 | 3032 | rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 3033 | { |
0e485150 FR |
3034 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
3035 | const unsigned int region = cfg->region; | |
1da177e4 | 3036 | struct rtl8169_private *tp; |
ccdffb9a | 3037 | struct mii_if_info *mii; |
4ff96fa6 FR |
3038 | struct net_device *dev; |
3039 | void __iomem *ioaddr; | |
07d3f51f FR |
3040 | unsigned int i; |
3041 | int rc; | |
1da177e4 | 3042 | |
4ff96fa6 FR |
3043 | if (netif_msg_drv(&debug)) { |
3044 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
3045 | MODULENAME, RTL8169_VERSION); | |
3046 | } | |
1da177e4 | 3047 | |
1da177e4 | 3048 | dev = alloc_etherdev(sizeof (*tp)); |
4ff96fa6 | 3049 | if (!dev) { |
b57b7e5a | 3050 | if (netif_msg_drv(&debug)) |
9b91cf9d | 3051 | dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
4ff96fa6 FR |
3052 | rc = -ENOMEM; |
3053 | goto out; | |
1da177e4 LT |
3054 | } |
3055 | ||
1da177e4 | 3056 | SET_NETDEV_DEV(dev, &pdev->dev); |
8b4ab28d | 3057 | dev->netdev_ops = &rtl8169_netdev_ops; |
1da177e4 | 3058 | tp = netdev_priv(dev); |
c4028958 | 3059 | tp->dev = dev; |
21e197f2 | 3060 | tp->pci_dev = pdev; |
b57b7e5a | 3061 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
1da177e4 | 3062 | |
ccdffb9a FR |
3063 | mii = &tp->mii; |
3064 | mii->dev = dev; | |
3065 | mii->mdio_read = rtl_mdio_read; | |
3066 | mii->mdio_write = rtl_mdio_write; | |
3067 | mii->phy_id_mask = 0x1f; | |
3068 | mii->reg_num_mask = 0x1f; | |
3069 | mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); | |
3070 | ||
ba04c7c9 SG |
3071 | /* disable ASPM completely as that cause random device stop working |
3072 | * problems as well as full system hangs for some PCIe devices users */ | |
3073 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
3074 | PCIE_LINK_STATE_CLKPM); | |
3075 | ||
1da177e4 LT |
3076 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
3077 | rc = pci_enable_device(pdev); | |
b57b7e5a | 3078 | if (rc < 0) { |
bf82c189 | 3079 | netif_err(tp, probe, dev, "enable failure\n"); |
4ff96fa6 | 3080 | goto err_out_free_dev_1; |
1da177e4 LT |
3081 | } |
3082 | ||
87aeec76 | 3083 | if (pci_set_mwi(pdev) < 0) |
3084 | netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); | |
1da177e4 | 3085 | |
1da177e4 | 3086 | /* make sure PCI base addr 1 is MMIO */ |
bcf0bf90 | 3087 | if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
bf82c189 JP |
3088 | netif_err(tp, probe, dev, |
3089 | "region #%d not an MMIO resource, aborting\n", | |
3090 | region); | |
1da177e4 | 3091 | rc = -ENODEV; |
87aeec76 | 3092 | goto err_out_mwi_2; |
1da177e4 | 3093 | } |
4ff96fa6 | 3094 | |
1da177e4 | 3095 | /* check for weird/broken PCI region reporting */ |
bcf0bf90 | 3096 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
bf82c189 JP |
3097 | netif_err(tp, probe, dev, |
3098 | "Invalid PCI region size(s), aborting\n"); | |
1da177e4 | 3099 | rc = -ENODEV; |
87aeec76 | 3100 | goto err_out_mwi_2; |
1da177e4 LT |
3101 | } |
3102 | ||
3103 | rc = pci_request_regions(pdev, MODULENAME); | |
b57b7e5a | 3104 | if (rc < 0) { |
bf82c189 | 3105 | netif_err(tp, probe, dev, "could not request regions\n"); |
87aeec76 | 3106 | goto err_out_mwi_2; |
1da177e4 LT |
3107 | } |
3108 | ||
d24e9aaf | 3109 | tp->cp_cmd = RxChkSum; |
1da177e4 LT |
3110 | |
3111 | if ((sizeof(dma_addr_t) > 4) && | |
4300e8c7 | 3112 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { |
1da177e4 LT |
3113 | tp->cp_cmd |= PCIDAC; |
3114 | dev->features |= NETIF_F_HIGHDMA; | |
3115 | } else { | |
284901a9 | 3116 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 3117 | if (rc < 0) { |
bf82c189 | 3118 | netif_err(tp, probe, dev, "DMA configuration failed\n"); |
87aeec76 | 3119 | goto err_out_free_res_3; |
1da177e4 LT |
3120 | } |
3121 | } | |
3122 | ||
1da177e4 | 3123 | /* ioremap MMIO region */ |
bcf0bf90 | 3124 | ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
4ff96fa6 | 3125 | if (!ioaddr) { |
bf82c189 | 3126 | netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); |
1da177e4 | 3127 | rc = -EIO; |
87aeec76 | 3128 | goto err_out_free_res_3; |
1da177e4 LT |
3129 | } |
3130 | ||
4300e8c7 DM |
3131 | tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
3132 | if (!tp->pcie_cap) | |
3133 | netif_info(tp, probe, dev, "no PCI Express capability\n"); | |
3134 | ||
d78ad8cb | 3135 | RTL_W16(IntrMask, 0x0000); |
1da177e4 LT |
3136 | |
3137 | /* Soft reset the chip. */ | |
3138 | RTL_W8(ChipCmd, CmdReset); | |
3139 | ||
3140 | /* Check that the chip has finished the reset. */ | |
07d3f51f | 3141 | for (i = 0; i < 100; i++) { |
1da177e4 LT |
3142 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
3143 | break; | |
b518fa8e | 3144 | msleep_interruptible(1); |
1da177e4 LT |
3145 | } |
3146 | ||
d78ad8cb KW |
3147 | RTL_W16(IntrStatus, 0xffff); |
3148 | ||
ca52efd5 | 3149 | pci_set_master(pdev); |
3150 | ||
1da177e4 LT |
3151 | /* Identify chip attached to board */ |
3152 | rtl8169_get_mac_version(tp, ioaddr); | |
1da177e4 | 3153 | |
7a8fc77b FR |
3154 | /* |
3155 | * Pretend we are using VLANs; This bypasses a nasty bug where | |
3156 | * Interrupts stop flowing on high load on 8110SCd controllers. | |
3157 | */ | |
3158 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) | |
3159 | tp->cp_cmd |= RxVlan; | |
3160 | ||
c0e45c1c | 3161 | rtl_init_mdio_ops(tp); |
065c27c1 | 3162 | rtl_init_pll_power_ops(tp); |
c0e45c1c | 3163 | |
f21b75e9 JD |
3164 | /* Use appropriate default if unknown */ |
3165 | if (tp->mac_version == RTL_GIGA_MAC_NONE) { | |
bf82c189 JP |
3166 | netif_notice(tp, probe, dev, |
3167 | "unknown MAC, using family default\n"); | |
f21b75e9 JD |
3168 | tp->mac_version = cfg->default_ver; |
3169 | } | |
3170 | ||
1da177e4 | 3171 | rtl8169_print_mac_version(tp); |
1da177e4 | 3172 | |
cee60c37 | 3173 | for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { |
1da177e4 LT |
3174 | if (tp->mac_version == rtl_chip_info[i].mac_version) |
3175 | break; | |
3176 | } | |
cee60c37 | 3177 | if (i == ARRAY_SIZE(rtl_chip_info)) { |
f21b75e9 JD |
3178 | dev_err(&pdev->dev, |
3179 | "driver bug, MAC version not found in rtl_chip_info\n"); | |
87aeec76 | 3180 | goto err_out_msi_4; |
1da177e4 LT |
3181 | } |
3182 | tp->chipset = i; | |
3183 | ||
5d06a99f FR |
3184 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
3185 | RTL_W8(Config1, RTL_R8(Config1) | PMEnable); | |
3186 | RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); | |
20037fa4 BP |
3187 | if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
3188 | tp->features |= RTL_FEATURE_WOL; | |
3189 | if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) | |
3190 | tp->features |= RTL_FEATURE_WOL; | |
fbac58fc | 3191 | tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
5d06a99f FR |
3192 | RTL_W8(Cfg9346, Cfg9346_Lock); |
3193 | ||
66ec5d4f FR |
3194 | if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && |
3195 | (RTL_R8(PHYstatus) & TBI_Enable)) { | |
1da177e4 LT |
3196 | tp->set_speed = rtl8169_set_speed_tbi; |
3197 | tp->get_settings = rtl8169_gset_tbi; | |
3198 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; | |
3199 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
3200 | tp->link_ok = rtl8169_tbi_link_ok; | |
8b4ab28d | 3201 | tp->do_ioctl = rtl_tbi_ioctl; |
1da177e4 | 3202 | |
64e4bfb4 | 3203 | tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ |
1da177e4 LT |
3204 | } else { |
3205 | tp->set_speed = rtl8169_set_speed_xmii; | |
3206 | tp->get_settings = rtl8169_gset_xmii; | |
3207 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; | |
3208 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
3209 | tp->link_ok = rtl8169_xmii_link_ok; | |
8b4ab28d | 3210 | tp->do_ioctl = rtl_xmii_ioctl; |
1da177e4 LT |
3211 | } |
3212 | ||
df58ef51 FR |
3213 | spin_lock_init(&tp->lock); |
3214 | ||
738e1e69 PV |
3215 | tp->mmio_addr = ioaddr; |
3216 | ||
7bf6bf48 | 3217 | /* Get MAC address */ |
1da177e4 LT |
3218 | for (i = 0; i < MAC_ADDR_LEN; i++) |
3219 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | |
6d6525b7 | 3220 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 3221 | |
1da177e4 | 3222 | SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
1da177e4 LT |
3223 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
3224 | dev->irq = pdev->irq; | |
3225 | dev->base_addr = (unsigned long) ioaddr; | |
1da177e4 | 3226 | |
bea3348e | 3227 | netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
1da177e4 | 3228 | |
7a8fc77b | 3229 | dev->features |= NETIF_F_HW_VLAN_TX_RX | NETIF_F_GRO; |
1da177e4 LT |
3230 | |
3231 | tp->intr_mask = 0xffff; | |
0e485150 FR |
3232 | tp->hw_start = cfg->hw_start; |
3233 | tp->intr_event = cfg->intr_event; | |
3234 | tp->napi_event = cfg->napi_event; | |
1da177e4 | 3235 | |
2efa53f3 FR |
3236 | init_timer(&tp->timer); |
3237 | tp->timer.data = (unsigned long) dev; | |
3238 | tp->timer.function = rtl8169_phy_timer; | |
3239 | ||
1da177e4 | 3240 | rc = register_netdev(dev); |
4ff96fa6 | 3241 | if (rc < 0) |
87aeec76 | 3242 | goto err_out_msi_4; |
1da177e4 LT |
3243 | |
3244 | pci_set_drvdata(pdev, dev); | |
3245 | ||
bf82c189 JP |
3246 | netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n", |
3247 | rtl_chip_info[tp->chipset].name, | |
3248 | dev->base_addr, dev->dev_addr, | |
3249 | (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq); | |
1da177e4 | 3250 | |
e6de30d6 | 3251 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27) || |
3252 | (tp->mac_version == RTL_GIGA_MAC_VER_28)) { | |
b646d900 | 3253 | rtl8168_driver_start(tp); |
e6de30d6 | 3254 | } |
b646d900 | 3255 | |
8b76ab39 | 3256 | device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
1da177e4 | 3257 | |
f3ec4f87 AS |
3258 | if (pci_dev_run_wake(pdev)) |
3259 | pm_runtime_put_noidle(&pdev->dev); | |
e1759441 | 3260 | |
0d672e9f IV |
3261 | netif_carrier_off(dev); |
3262 | ||
4ff96fa6 FR |
3263 | out: |
3264 | return rc; | |
1da177e4 | 3265 | |
87aeec76 | 3266 | err_out_msi_4: |
fbac58fc | 3267 | rtl_disable_msi(pdev, tp); |
4ff96fa6 | 3268 | iounmap(ioaddr); |
87aeec76 | 3269 | err_out_free_res_3: |
4ff96fa6 | 3270 | pci_release_regions(pdev); |
87aeec76 | 3271 | err_out_mwi_2: |
4ff96fa6 | 3272 | pci_clear_mwi(pdev); |
4ff96fa6 FR |
3273 | pci_disable_device(pdev); |
3274 | err_out_free_dev_1: | |
3275 | free_netdev(dev); | |
3276 | goto out; | |
1da177e4 LT |
3277 | } |
3278 | ||
07d3f51f | 3279 | static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
3280 | { |
3281 | struct net_device *dev = pci_get_drvdata(pdev); | |
3282 | struct rtl8169_private *tp = netdev_priv(dev); | |
3283 | ||
e6de30d6 | 3284 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27) || |
3285 | (tp->mac_version == RTL_GIGA_MAC_VER_28)) { | |
b646d900 | 3286 | rtl8168_driver_stop(tp); |
e6de30d6 | 3287 | } |
b646d900 | 3288 | |
23f333a2 | 3289 | cancel_delayed_work_sync(&tp->task); |
eb2a021c | 3290 | |
f1e02ed1 | 3291 | rtl_release_firmware(tp); |
3292 | ||
1da177e4 | 3293 | unregister_netdev(dev); |
cc098dc7 | 3294 | |
f3ec4f87 AS |
3295 | if (pci_dev_run_wake(pdev)) |
3296 | pm_runtime_get_noresume(&pdev->dev); | |
e1759441 | 3297 | |
cc098dc7 IV |
3298 | /* restore original MAC address */ |
3299 | rtl_rar_set(tp, dev->perm_addr); | |
3300 | ||
fbac58fc | 3301 | rtl_disable_msi(pdev, tp); |
1da177e4 LT |
3302 | rtl8169_release_board(pdev, dev, tp->mmio_addr); |
3303 | pci_set_drvdata(pdev, NULL); | |
3304 | } | |
3305 | ||
1da177e4 LT |
3306 | static int rtl8169_open(struct net_device *dev) |
3307 | { | |
3308 | struct rtl8169_private *tp = netdev_priv(dev); | |
eee3a96c | 3309 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 3310 | struct pci_dev *pdev = tp->pci_dev; |
99f252b0 | 3311 | int retval = -ENOMEM; |
1da177e4 | 3312 | |
e1759441 | 3313 | pm_runtime_get_sync(&pdev->dev); |
1da177e4 | 3314 | |
1da177e4 LT |
3315 | /* |
3316 | * Rx and Tx desscriptors needs 256 bytes alignment. | |
82553bb6 | 3317 | * dma_alloc_coherent provides more. |
1da177e4 | 3318 | */ |
82553bb6 SG |
3319 | tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, |
3320 | &tp->TxPhyAddr, GFP_KERNEL); | |
1da177e4 | 3321 | if (!tp->TxDescArray) |
e1759441 | 3322 | goto err_pm_runtime_put; |
1da177e4 | 3323 | |
82553bb6 SG |
3324 | tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, |
3325 | &tp->RxPhyAddr, GFP_KERNEL); | |
1da177e4 | 3326 | if (!tp->RxDescArray) |
99f252b0 | 3327 | goto err_free_tx_0; |
1da177e4 LT |
3328 | |
3329 | retval = rtl8169_init_ring(dev); | |
3330 | if (retval < 0) | |
99f252b0 | 3331 | goto err_free_rx_1; |
1da177e4 | 3332 | |
c4028958 | 3333 | INIT_DELAYED_WORK(&tp->task, NULL); |
1da177e4 | 3334 | |
99f252b0 FR |
3335 | smp_mb(); |
3336 | ||
fbac58fc FR |
3337 | retval = request_irq(dev->irq, rtl8169_interrupt, |
3338 | (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, | |
99f252b0 FR |
3339 | dev->name, dev); |
3340 | if (retval < 0) | |
3341 | goto err_release_ring_2; | |
3342 | ||
bea3348e | 3343 | napi_enable(&tp->napi); |
bea3348e | 3344 | |
eee3a96c | 3345 | rtl8169_init_phy(dev, tp); |
3346 | ||
7a8fc77b | 3347 | rtl8169_vlan_mode(dev); |
eee3a96c | 3348 | |
065c27c1 | 3349 | rtl_pll_power_up(tp); |
3350 | ||
07ce4064 | 3351 | rtl_hw_start(dev); |
1da177e4 LT |
3352 | |
3353 | rtl8169_request_timer(dev); | |
3354 | ||
e1759441 RW |
3355 | tp->saved_wolopts = 0; |
3356 | pm_runtime_put_noidle(&pdev->dev); | |
3357 | ||
eee3a96c | 3358 | rtl8169_check_link_status(dev, tp, ioaddr); |
1da177e4 LT |
3359 | out: |
3360 | return retval; | |
3361 | ||
99f252b0 FR |
3362 | err_release_ring_2: |
3363 | rtl8169_rx_clear(tp); | |
3364 | err_free_rx_1: | |
82553bb6 SG |
3365 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
3366 | tp->RxPhyAddr); | |
e1759441 | 3367 | tp->RxDescArray = NULL; |
99f252b0 | 3368 | err_free_tx_0: |
82553bb6 SG |
3369 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
3370 | tp->TxPhyAddr); | |
e1759441 RW |
3371 | tp->TxDescArray = NULL; |
3372 | err_pm_runtime_put: | |
3373 | pm_runtime_put_noidle(&pdev->dev); | |
1da177e4 LT |
3374 | goto out; |
3375 | } | |
3376 | ||
e6de30d6 | 3377 | static void rtl8169_hw_reset(struct rtl8169_private *tp) |
1da177e4 | 3378 | { |
e6de30d6 | 3379 | void __iomem *ioaddr = tp->mmio_addr; |
3380 | ||
1da177e4 LT |
3381 | /* Disable interrupts */ |
3382 | rtl8169_irq_mask_and_ack(ioaddr); | |
3383 | ||
5d2e1957 HW |
3384 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
3385 | tp->mac_version == RTL_GIGA_MAC_VER_28) { | |
e6de30d6 | 3386 | while (RTL_R8(TxPoll) & NPQ) |
3387 | udelay(20); | |
3388 | ||
3389 | } | |
3390 | ||
1da177e4 LT |
3391 | /* Reset the chipset */ |
3392 | RTL_W8(ChipCmd, CmdReset); | |
3393 | ||
3394 | /* PCI commit */ | |
3395 | RTL_R8(ChipCmd); | |
3396 | } | |
3397 | ||
7f796d83 | 3398 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 FR |
3399 | { |
3400 | void __iomem *ioaddr = tp->mmio_addr; | |
3401 | u32 cfg = rtl8169_rx_config; | |
3402 | ||
3403 | cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); | |
3404 | RTL_W32(RxConfig, cfg); | |
3405 | ||
3406 | /* Set DMA burst size and Interframe Gap Time */ | |
3407 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
3408 | (InterFrameGap << TxInterFrameGapShift)); | |
3409 | } | |
3410 | ||
07ce4064 | 3411 | static void rtl_hw_start(struct net_device *dev) |
1da177e4 LT |
3412 | { |
3413 | struct rtl8169_private *tp = netdev_priv(dev); | |
3414 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 3415 | unsigned int i; |
1da177e4 LT |
3416 | |
3417 | /* Soft reset the chip. */ | |
3418 | RTL_W8(ChipCmd, CmdReset); | |
3419 | ||
3420 | /* Check that the chip has finished the reset. */ | |
07d3f51f | 3421 | for (i = 0; i < 100; i++) { |
1da177e4 LT |
3422 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
3423 | break; | |
b518fa8e | 3424 | msleep_interruptible(1); |
1da177e4 LT |
3425 | } |
3426 | ||
07ce4064 FR |
3427 | tp->hw_start(dev); |
3428 | ||
07ce4064 FR |
3429 | netif_start_queue(dev); |
3430 | } | |
3431 | ||
3432 | ||
7f796d83 FR |
3433 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
3434 | void __iomem *ioaddr) | |
3435 | { | |
3436 | /* | |
3437 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
3438 | * register to be written before TxDescAddrLow to work. | |
3439 | * Switching from MMIO to I/O access fixes the issue as well. | |
3440 | */ | |
3441 | RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); | |
284901a9 | 3442 | RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 | 3443 | RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
284901a9 | 3444 | RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 FR |
3445 | } |
3446 | ||
3447 | static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) | |
3448 | { | |
3449 | u16 cmd; | |
3450 | ||
3451 | cmd = RTL_R16(CPlusCmd); | |
3452 | RTL_W16(CPlusCmd, cmd); | |
3453 | return cmd; | |
3454 | } | |
3455 | ||
fdd7b4c3 | 3456 | static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
7f796d83 FR |
3457 | { |
3458 | /* Low hurts. Let's disable the filtering. */ | |
207d6e87 | 3459 | RTL_W16(RxMaxSize, rx_buf_sz + 1); |
7f796d83 FR |
3460 | } |
3461 | ||
6dccd16b FR |
3462 | static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
3463 | { | |
350f7596 | 3464 | static const struct { |
6dccd16b FR |
3465 | u32 mac_version; |
3466 | u32 clk; | |
3467 | u32 val; | |
3468 | } cfg2_info [] = { | |
3469 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
3470 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
3471 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
3472 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
3473 | }, *p = cfg2_info; | |
3474 | unsigned int i; | |
3475 | u32 clk; | |
3476 | ||
3477 | clk = RTL_R8(Config2) & PCI_Clock_66MHz; | |
cadf1855 | 3478 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
6dccd16b FR |
3479 | if ((p->mac_version == mac_version) && (p->clk == clk)) { |
3480 | RTL_W32(0x7c, p->val); | |
3481 | break; | |
3482 | } | |
3483 | } | |
3484 | } | |
3485 | ||
07ce4064 FR |
3486 | static void rtl_hw_start_8169(struct net_device *dev) |
3487 | { | |
3488 | struct rtl8169_private *tp = netdev_priv(dev); | |
3489 | void __iomem *ioaddr = tp->mmio_addr; | |
3490 | struct pci_dev *pdev = tp->pci_dev; | |
07ce4064 | 3491 | |
9cb427b6 FR |
3492 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
3493 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); | |
3494 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
3495 | } | |
3496 | ||
1da177e4 | 3497 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
9cb427b6 FR |
3498 | if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
3499 | (tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
3500 | (tp->mac_version == RTL_GIGA_MAC_VER_03) || | |
3501 | (tp->mac_version == RTL_GIGA_MAC_VER_04)) | |
3502 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
3503 | ||
f0298f81 | 3504 | RTL_W8(EarlyTxThres, NoEarlyTx); |
1da177e4 | 3505 | |
6f0333b8 | 3506 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
1da177e4 | 3507 | |
c946b304 FR |
3508 | if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
3509 | (tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
3510 | (tp->mac_version == RTL_GIGA_MAC_VER_03) || | |
3511 | (tp->mac_version == RTL_GIGA_MAC_VER_04)) | |
3512 | rtl_set_rx_tx_config_registers(tp); | |
1da177e4 | 3513 | |
7f796d83 | 3514 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
1da177e4 | 3515 | |
bcf0bf90 FR |
3516 | if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
3517 | (tp->mac_version == RTL_GIGA_MAC_VER_03)) { | |
06fa7358 | 3518 | dprintk("Set MAC Reg C+CR Offset 0xE0. " |
1da177e4 | 3519 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 3520 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
3521 | } |
3522 | ||
bcf0bf90 FR |
3523 | RTL_W16(CPlusCmd, tp->cp_cmd); |
3524 | ||
6dccd16b FR |
3525 | rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
3526 | ||
1da177e4 LT |
3527 | /* |
3528 | * Undocumented corner. Supposedly: | |
3529 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
3530 | */ | |
3531 | RTL_W16(IntrMitigate, 0x0000); | |
3532 | ||
7f796d83 | 3533 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
9cb427b6 | 3534 | |
c946b304 FR |
3535 | if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && |
3536 | (tp->mac_version != RTL_GIGA_MAC_VER_02) && | |
3537 | (tp->mac_version != RTL_GIGA_MAC_VER_03) && | |
3538 | (tp->mac_version != RTL_GIGA_MAC_VER_04)) { | |
3539 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
3540 | rtl_set_rx_tx_config_registers(tp); | |
3541 | } | |
3542 | ||
1da177e4 | 3543 | RTL_W8(Cfg9346, Cfg9346_Lock); |
b518fa8e FR |
3544 | |
3545 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
3546 | RTL_R8(IntrMask); | |
1da177e4 LT |
3547 | |
3548 | RTL_W32(RxMissed, 0); | |
3549 | ||
07ce4064 | 3550 | rtl_set_rx_mode(dev); |
1da177e4 LT |
3551 | |
3552 | /* no early-rx interrupts */ | |
3553 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | |
6dccd16b FR |
3554 | |
3555 | /* Enable all known interrupts by setting the interrupt mask. */ | |
0e485150 | 3556 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 3557 | } |
1da177e4 | 3558 | |
9c14ceaf | 3559 | static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
458a9f61 | 3560 | { |
9c14ceaf FR |
3561 | struct net_device *dev = pci_get_drvdata(pdev); |
3562 | struct rtl8169_private *tp = netdev_priv(dev); | |
3563 | int cap = tp->pcie_cap; | |
3564 | ||
3565 | if (cap) { | |
3566 | u16 ctl; | |
458a9f61 | 3567 | |
9c14ceaf FR |
3568 | pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
3569 | ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; | |
3570 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); | |
3571 | } | |
458a9f61 FR |
3572 | } |
3573 | ||
650e8d5d | 3574 | static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits) |
dacf8154 FR |
3575 | { |
3576 | u32 csi; | |
3577 | ||
3578 | csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; | |
650e8d5d | 3579 | rtl_csi_write(ioaddr, 0x070c, csi | bits); |
3580 | } | |
3581 | ||
e6de30d6 | 3582 | static void rtl_csi_access_enable_1(void __iomem *ioaddr) |
3583 | { | |
3584 | rtl_csi_access_enable(ioaddr, 0x17000000); | |
3585 | } | |
3586 | ||
650e8d5d | 3587 | static void rtl_csi_access_enable_2(void __iomem *ioaddr) |
3588 | { | |
3589 | rtl_csi_access_enable(ioaddr, 0x27000000); | |
dacf8154 FR |
3590 | } |
3591 | ||
3592 | struct ephy_info { | |
3593 | unsigned int offset; | |
3594 | u16 mask; | |
3595 | u16 bits; | |
3596 | }; | |
3597 | ||
350f7596 | 3598 | static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len) |
dacf8154 FR |
3599 | { |
3600 | u16 w; | |
3601 | ||
3602 | while (len-- > 0) { | |
3603 | w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; | |
3604 | rtl_ephy_write(ioaddr, e->offset, w); | |
3605 | e++; | |
3606 | } | |
3607 | } | |
3608 | ||
b726e493 FR |
3609 | static void rtl_disable_clock_request(struct pci_dev *pdev) |
3610 | { | |
3611 | struct net_device *dev = pci_get_drvdata(pdev); | |
3612 | struct rtl8169_private *tp = netdev_priv(dev); | |
3613 | int cap = tp->pcie_cap; | |
3614 | ||
3615 | if (cap) { | |
3616 | u16 ctl; | |
3617 | ||
3618 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
3619 | ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3620 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
3621 | } | |
3622 | } | |
3623 | ||
e6de30d6 | 3624 | static void rtl_enable_clock_request(struct pci_dev *pdev) |
3625 | { | |
3626 | struct net_device *dev = pci_get_drvdata(pdev); | |
3627 | struct rtl8169_private *tp = netdev_priv(dev); | |
3628 | int cap = tp->pcie_cap; | |
3629 | ||
3630 | if (cap) { | |
3631 | u16 ctl; | |
3632 | ||
3633 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
3634 | ctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
3635 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
3636 | } | |
3637 | } | |
3638 | ||
b726e493 FR |
3639 | #define R8168_CPCMD_QUIRK_MASK (\ |
3640 | EnableBist | \ | |
3641 | Mac_dbgo_oe | \ | |
3642 | Force_half_dup | \ | |
3643 | Force_rxflow_en | \ | |
3644 | Force_txflow_en | \ | |
3645 | Cxpl_dbg_sel | \ | |
3646 | ASF | \ | |
3647 | PktCntrDisable | \ | |
3648 | Mac_dbgo_sel) | |
3649 | ||
219a1e9d FR |
3650 | static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
3651 | { | |
b726e493 FR |
3652 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
3653 | ||
3654 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
3655 | ||
2e68ae44 FR |
3656 | rtl_tx_performance_tweak(pdev, |
3657 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
219a1e9d FR |
3658 | } |
3659 | ||
3660 | static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) | |
3661 | { | |
3662 | rtl_hw_start_8168bb(ioaddr, pdev); | |
b726e493 | 3663 | |
f0298f81 | 3664 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
b726e493 FR |
3665 | |
3666 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
219a1e9d FR |
3667 | } |
3668 | ||
3669 | static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) | |
3670 | { | |
b726e493 FR |
3671 | RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
3672 | ||
3673 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
3674 | ||
219a1e9d | 3675 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
b726e493 FR |
3676 | |
3677 | rtl_disable_clock_request(pdev); | |
3678 | ||
3679 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
219a1e9d FR |
3680 | } |
3681 | ||
ef3386f0 | 3682 | static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
219a1e9d | 3683 | { |
350f7596 | 3684 | static const struct ephy_info e_info_8168cp[] = { |
b726e493 FR |
3685 | { 0x01, 0, 0x0001 }, |
3686 | { 0x02, 0x0800, 0x1000 }, | |
3687 | { 0x03, 0, 0x0042 }, | |
3688 | { 0x06, 0x0080, 0x0000 }, | |
3689 | { 0x07, 0, 0x2000 } | |
3690 | }; | |
3691 | ||
650e8d5d | 3692 | rtl_csi_access_enable_2(ioaddr); |
b726e493 FR |
3693 | |
3694 | rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); | |
3695 | ||
219a1e9d FR |
3696 | __rtl_hw_start_8168cp(ioaddr, pdev); |
3697 | } | |
3698 | ||
ef3386f0 FR |
3699 | static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
3700 | { | |
650e8d5d | 3701 | rtl_csi_access_enable_2(ioaddr); |
ef3386f0 FR |
3702 | |
3703 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
3704 | ||
3705 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
3706 | ||
3707 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
3708 | } | |
3709 | ||
7f3e3d3a FR |
3710 | static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
3711 | { | |
650e8d5d | 3712 | rtl_csi_access_enable_2(ioaddr); |
7f3e3d3a FR |
3713 | |
3714 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
3715 | ||
3716 | /* Magic. */ | |
3717 | RTL_W8(DBG_REG, 0x20); | |
3718 | ||
f0298f81 | 3719 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
7f3e3d3a FR |
3720 | |
3721 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
3722 | ||
3723 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
3724 | } | |
3725 | ||
219a1e9d FR |
3726 | static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
3727 | { | |
350f7596 | 3728 | static const struct ephy_info e_info_8168c_1[] = { |
b726e493 FR |
3729 | { 0x02, 0x0800, 0x1000 }, |
3730 | { 0x03, 0, 0x0002 }, | |
3731 | { 0x06, 0x0080, 0x0000 } | |
3732 | }; | |
3733 | ||
650e8d5d | 3734 | rtl_csi_access_enable_2(ioaddr); |
b726e493 FR |
3735 | |
3736 | RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); | |
3737 | ||
3738 | rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); | |
3739 | ||
219a1e9d FR |
3740 | __rtl_hw_start_8168cp(ioaddr, pdev); |
3741 | } | |
3742 | ||
3743 | static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
3744 | { | |
350f7596 | 3745 | static const struct ephy_info e_info_8168c_2[] = { |
b726e493 FR |
3746 | { 0x01, 0, 0x0001 }, |
3747 | { 0x03, 0x0400, 0x0220 } | |
3748 | }; | |
3749 | ||
650e8d5d | 3750 | rtl_csi_access_enable_2(ioaddr); |
b726e493 FR |
3751 | |
3752 | rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); | |
3753 | ||
219a1e9d FR |
3754 | __rtl_hw_start_8168cp(ioaddr, pdev); |
3755 | } | |
3756 | ||
197ff761 FR |
3757 | static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
3758 | { | |
3759 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
3760 | } | |
3761 | ||
6fb07058 FR |
3762 | static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
3763 | { | |
650e8d5d | 3764 | rtl_csi_access_enable_2(ioaddr); |
6fb07058 FR |
3765 | |
3766 | __rtl_hw_start_8168cp(ioaddr, pdev); | |
3767 | } | |
3768 | ||
5b538df9 FR |
3769 | static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
3770 | { | |
650e8d5d | 3771 | rtl_csi_access_enable_2(ioaddr); |
5b538df9 FR |
3772 | |
3773 | rtl_disable_clock_request(pdev); | |
3774 | ||
f0298f81 | 3775 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
5b538df9 FR |
3776 | |
3777 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
3778 | ||
3779 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
3780 | } | |
3781 | ||
e6de30d6 | 3782 | static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev) |
3783 | { | |
3784 | static const struct ephy_info e_info_8168d_4[] = { | |
3785 | { 0x0b, ~0, 0x48 }, | |
3786 | { 0x19, 0x20, 0x50 }, | |
3787 | { 0x0c, ~0, 0x20 } | |
3788 | }; | |
3789 | int i; | |
3790 | ||
3791 | rtl_csi_access_enable_1(ioaddr); | |
3792 | ||
3793 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
3794 | ||
3795 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
3796 | ||
3797 | for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { | |
3798 | const struct ephy_info *e = e_info_8168d_4 + i; | |
3799 | u16 w; | |
3800 | ||
3801 | w = rtl_ephy_read(ioaddr, e->offset); | |
3802 | rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits); | |
3803 | } | |
3804 | ||
3805 | rtl_enable_clock_request(pdev); | |
3806 | } | |
3807 | ||
07ce4064 FR |
3808 | static void rtl_hw_start_8168(struct net_device *dev) |
3809 | { | |
2dd99530 FR |
3810 | struct rtl8169_private *tp = netdev_priv(dev); |
3811 | void __iomem *ioaddr = tp->mmio_addr; | |
0e485150 | 3812 | struct pci_dev *pdev = tp->pci_dev; |
2dd99530 FR |
3813 | |
3814 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
3815 | ||
f0298f81 | 3816 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
2dd99530 | 3817 | |
6f0333b8 | 3818 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
2dd99530 | 3819 | |
0e485150 | 3820 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
2dd99530 FR |
3821 | |
3822 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
3823 | ||
0e485150 | 3824 | RTL_W16(IntrMitigate, 0x5151); |
2dd99530 | 3825 | |
0e485150 | 3826 | /* Work around for RxFIFO overflow. */ |
b5ba6d12 IV |
3827 | if (tp->mac_version == RTL_GIGA_MAC_VER_11 || |
3828 | tp->mac_version == RTL_GIGA_MAC_VER_22) { | |
0e485150 FR |
3829 | tp->intr_event |= RxFIFOOver | PCSTimeout; |
3830 | tp->intr_event &= ~RxOverflow; | |
3831 | } | |
3832 | ||
3833 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2dd99530 | 3834 | |
b8363901 FR |
3835 | rtl_set_rx_mode(dev); |
3836 | ||
3837 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
3838 | (InterFrameGap << TxInterFrameGapShift)); | |
2dd99530 FR |
3839 | |
3840 | RTL_R8(IntrMask); | |
3841 | ||
219a1e9d FR |
3842 | switch (tp->mac_version) { |
3843 | case RTL_GIGA_MAC_VER_11: | |
3844 | rtl_hw_start_8168bb(ioaddr, pdev); | |
3845 | break; | |
3846 | ||
3847 | case RTL_GIGA_MAC_VER_12: | |
3848 | case RTL_GIGA_MAC_VER_17: | |
3849 | rtl_hw_start_8168bef(ioaddr, pdev); | |
3850 | break; | |
3851 | ||
3852 | case RTL_GIGA_MAC_VER_18: | |
ef3386f0 | 3853 | rtl_hw_start_8168cp_1(ioaddr, pdev); |
219a1e9d FR |
3854 | break; |
3855 | ||
3856 | case RTL_GIGA_MAC_VER_19: | |
3857 | rtl_hw_start_8168c_1(ioaddr, pdev); | |
3858 | break; | |
3859 | ||
3860 | case RTL_GIGA_MAC_VER_20: | |
3861 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
3862 | break; | |
3863 | ||
197ff761 FR |
3864 | case RTL_GIGA_MAC_VER_21: |
3865 | rtl_hw_start_8168c_3(ioaddr, pdev); | |
3866 | break; | |
3867 | ||
6fb07058 FR |
3868 | case RTL_GIGA_MAC_VER_22: |
3869 | rtl_hw_start_8168c_4(ioaddr, pdev); | |
3870 | break; | |
3871 | ||
ef3386f0 FR |
3872 | case RTL_GIGA_MAC_VER_23: |
3873 | rtl_hw_start_8168cp_2(ioaddr, pdev); | |
3874 | break; | |
3875 | ||
7f3e3d3a FR |
3876 | case RTL_GIGA_MAC_VER_24: |
3877 | rtl_hw_start_8168cp_3(ioaddr, pdev); | |
3878 | break; | |
3879 | ||
5b538df9 | 3880 | case RTL_GIGA_MAC_VER_25: |
daf9df6d | 3881 | case RTL_GIGA_MAC_VER_26: |
3882 | case RTL_GIGA_MAC_VER_27: | |
5b538df9 FR |
3883 | rtl_hw_start_8168d(ioaddr, pdev); |
3884 | break; | |
3885 | ||
e6de30d6 | 3886 | case RTL_GIGA_MAC_VER_28: |
3887 | rtl_hw_start_8168d_4(ioaddr, pdev); | |
3888 | break; | |
3889 | ||
219a1e9d FR |
3890 | default: |
3891 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | |
3892 | dev->name, tp->mac_version); | |
3893 | break; | |
3894 | } | |
2dd99530 | 3895 | |
0e485150 FR |
3896 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
3897 | ||
b8363901 FR |
3898 | RTL_W8(Cfg9346, Cfg9346_Lock); |
3899 | ||
2dd99530 | 3900 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
6dccd16b | 3901 | |
0e485150 | 3902 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 3903 | } |
1da177e4 | 3904 | |
2857ffb7 FR |
3905 | #define R810X_CPCMD_QUIRK_MASK (\ |
3906 | EnableBist | \ | |
3907 | Mac_dbgo_oe | \ | |
3908 | Force_half_dup | \ | |
5edcc537 | 3909 | Force_rxflow_en | \ |
2857ffb7 FR |
3910 | Force_txflow_en | \ |
3911 | Cxpl_dbg_sel | \ | |
3912 | ASF | \ | |
3913 | PktCntrDisable | \ | |
d24e9aaf | 3914 | Mac_dbgo_sel) |
2857ffb7 FR |
3915 | |
3916 | static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) | |
3917 | { | |
350f7596 | 3918 | static const struct ephy_info e_info_8102e_1[] = { |
2857ffb7 FR |
3919 | { 0x01, 0, 0x6e65 }, |
3920 | { 0x02, 0, 0x091f }, | |
3921 | { 0x03, 0, 0xc2f9 }, | |
3922 | { 0x06, 0, 0xafb5 }, | |
3923 | { 0x07, 0, 0x0e00 }, | |
3924 | { 0x19, 0, 0xec80 }, | |
3925 | { 0x01, 0, 0x2e65 }, | |
3926 | { 0x01, 0, 0x6e65 } | |
3927 | }; | |
3928 | u8 cfg1; | |
3929 | ||
650e8d5d | 3930 | rtl_csi_access_enable_2(ioaddr); |
2857ffb7 FR |
3931 | |
3932 | RTL_W8(DBG_REG, FIX_NAK_1); | |
3933 | ||
3934 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
3935 | ||
3936 | RTL_W8(Config1, | |
3937 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); | |
3938 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
3939 | ||
3940 | cfg1 = RTL_R8(Config1); | |
3941 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) | |
3942 | RTL_W8(Config1, cfg1 & ~LEDS0); | |
3943 | ||
2857ffb7 FR |
3944 | rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
3945 | } | |
3946 | ||
3947 | static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
3948 | { | |
650e8d5d | 3949 | rtl_csi_access_enable_2(ioaddr); |
2857ffb7 FR |
3950 | |
3951 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
3952 | ||
3953 | RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); | |
3954 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2857ffb7 FR |
3955 | } |
3956 | ||
3957 | static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) | |
3958 | { | |
3959 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
3960 | ||
3961 | rtl_ephy_write(ioaddr, 0x03, 0xc2f9); | |
3962 | } | |
3963 | ||
5a5e4443 HW |
3964 | static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
3965 | { | |
3966 | static const struct ephy_info e_info_8105e_1[] = { | |
3967 | { 0x07, 0, 0x4000 }, | |
3968 | { 0x19, 0, 0x0200 }, | |
3969 | { 0x19, 0, 0x0020 }, | |
3970 | { 0x1e, 0, 0x2000 }, | |
3971 | { 0x03, 0, 0x0001 }, | |
3972 | { 0x19, 0, 0x0100 }, | |
3973 | { 0x19, 0, 0x0004 }, | |
3974 | { 0x0a, 0, 0x0020 } | |
3975 | }; | |
3976 | ||
3977 | /* Force LAN exit from ASPM if Rx/Tx are not idel */ | |
3978 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); | |
3979 | ||
3980 | /* disable Early Tally Counter */ | |
3981 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); | |
3982 | ||
3983 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); | |
3984 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH); | |
3985 | ||
3986 | rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); | |
3987 | } | |
3988 | ||
3989 | static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
3990 | { | |
3991 | rtl_hw_start_8105e_1(ioaddr, pdev); | |
3992 | rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000); | |
3993 | } | |
3994 | ||
07ce4064 FR |
3995 | static void rtl_hw_start_8101(struct net_device *dev) |
3996 | { | |
cdf1a608 FR |
3997 | struct rtl8169_private *tp = netdev_priv(dev); |
3998 | void __iomem *ioaddr = tp->mmio_addr; | |
3999 | struct pci_dev *pdev = tp->pci_dev; | |
4000 | ||
e3cf0cc0 FR |
4001 | if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
4002 | (tp->mac_version == RTL_GIGA_MAC_VER_16)) { | |
9c14ceaf FR |
4003 | int cap = tp->pcie_cap; |
4004 | ||
4005 | if (cap) { | |
4006 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, | |
4007 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
4008 | } | |
cdf1a608 FR |
4009 | } |
4010 | ||
d24e9aaf HW |
4011 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
4012 | ||
2857ffb7 FR |
4013 | switch (tp->mac_version) { |
4014 | case RTL_GIGA_MAC_VER_07: | |
4015 | rtl_hw_start_8102e_1(ioaddr, pdev); | |
4016 | break; | |
4017 | ||
4018 | case RTL_GIGA_MAC_VER_08: | |
4019 | rtl_hw_start_8102e_3(ioaddr, pdev); | |
4020 | break; | |
4021 | ||
4022 | case RTL_GIGA_MAC_VER_09: | |
4023 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
4024 | break; | |
5a5e4443 HW |
4025 | |
4026 | case RTL_GIGA_MAC_VER_29: | |
4027 | rtl_hw_start_8105e_1(ioaddr, pdev); | |
4028 | break; | |
4029 | case RTL_GIGA_MAC_VER_30: | |
4030 | rtl_hw_start_8105e_2(ioaddr, pdev); | |
4031 | break; | |
cdf1a608 FR |
4032 | } |
4033 | ||
d24e9aaf | 4034 | RTL_W8(Cfg9346, Cfg9346_Lock); |
cdf1a608 | 4035 | |
f0298f81 | 4036 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
cdf1a608 | 4037 | |
6f0333b8 | 4038 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
cdf1a608 | 4039 | |
d24e9aaf | 4040 | tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; |
cdf1a608 FR |
4041 | RTL_W16(CPlusCmd, tp->cp_cmd); |
4042 | ||
4043 | RTL_W16(IntrMitigate, 0x0000); | |
4044 | ||
4045 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
4046 | ||
4047 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
4048 | rtl_set_rx_tx_config_registers(tp); | |
4049 | ||
cdf1a608 FR |
4050 | RTL_R8(IntrMask); |
4051 | ||
cdf1a608 FR |
4052 | rtl_set_rx_mode(dev); |
4053 | ||
4054 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); | |
6dccd16b | 4055 | |
0e485150 | 4056 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
4057 | } |
4058 | ||
4059 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
4060 | { | |
1da177e4 LT |
4061 | if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) |
4062 | return -EINVAL; | |
4063 | ||
4064 | dev->mtu = new_mtu; | |
323bb685 | 4065 | return 0; |
1da177e4 LT |
4066 | } |
4067 | ||
4068 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
4069 | { | |
95e0918d | 4070 | desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
1da177e4 LT |
4071 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
4072 | } | |
4073 | ||
6f0333b8 ED |
4074 | static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
4075 | void **data_buff, struct RxDesc *desc) | |
1da177e4 | 4076 | { |
48addcc9 | 4077 | dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
231aee63 | 4078 | DMA_FROM_DEVICE); |
48addcc9 | 4079 | |
6f0333b8 ED |
4080 | kfree(*data_buff); |
4081 | *data_buff = NULL; | |
1da177e4 LT |
4082 | rtl8169_make_unusable_by_asic(desc); |
4083 | } | |
4084 | ||
4085 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) | |
4086 | { | |
4087 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
4088 | ||
4089 | desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); | |
4090 | } | |
4091 | ||
4092 | static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, | |
4093 | u32 rx_buf_sz) | |
4094 | { | |
4095 | desc->addr = cpu_to_le64(mapping); | |
4096 | wmb(); | |
4097 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
4098 | } | |
4099 | ||
6f0333b8 ED |
4100 | static inline void *rtl8169_align(void *data) |
4101 | { | |
4102 | return (void *)ALIGN((long)data, 16); | |
4103 | } | |
4104 | ||
0ecbe1ca SG |
4105 | static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
4106 | struct RxDesc *desc) | |
1da177e4 | 4107 | { |
6f0333b8 | 4108 | void *data; |
1da177e4 | 4109 | dma_addr_t mapping; |
48addcc9 | 4110 | struct device *d = &tp->pci_dev->dev; |
0ecbe1ca | 4111 | struct net_device *dev = tp->dev; |
6f0333b8 | 4112 | int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
1da177e4 | 4113 | |
6f0333b8 ED |
4114 | data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
4115 | if (!data) | |
4116 | return NULL; | |
e9f63f30 | 4117 | |
6f0333b8 ED |
4118 | if (rtl8169_align(data) != data) { |
4119 | kfree(data); | |
4120 | data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); | |
4121 | if (!data) | |
4122 | return NULL; | |
4123 | } | |
3eafe507 | 4124 | |
48addcc9 | 4125 | mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
231aee63 | 4126 | DMA_FROM_DEVICE); |
d827d86b SG |
4127 | if (unlikely(dma_mapping_error(d, mapping))) { |
4128 | if (net_ratelimit()) | |
4129 | netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); | |
3eafe507 | 4130 | goto err_out; |
d827d86b | 4131 | } |
1da177e4 LT |
4132 | |
4133 | rtl8169_map_to_asic(desc, mapping, rx_buf_sz); | |
6f0333b8 | 4134 | return data; |
3eafe507 SG |
4135 | |
4136 | err_out: | |
4137 | kfree(data); | |
4138 | return NULL; | |
1da177e4 LT |
4139 | } |
4140 | ||
4141 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
4142 | { | |
07d3f51f | 4143 | unsigned int i; |
1da177e4 LT |
4144 | |
4145 | for (i = 0; i < NUM_RX_DESC; i++) { | |
6f0333b8 ED |
4146 | if (tp->Rx_databuff[i]) { |
4147 | rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, | |
1da177e4 LT |
4148 | tp->RxDescArray + i); |
4149 | } | |
4150 | } | |
4151 | } | |
4152 | ||
0ecbe1ca | 4153 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
1da177e4 | 4154 | { |
0ecbe1ca SG |
4155 | desc->opts1 |= cpu_to_le32(RingEnd); |
4156 | } | |
5b0384f4 | 4157 | |
0ecbe1ca SG |
4158 | static int rtl8169_rx_fill(struct rtl8169_private *tp) |
4159 | { | |
4160 | unsigned int i; | |
1da177e4 | 4161 | |
0ecbe1ca SG |
4162 | for (i = 0; i < NUM_RX_DESC; i++) { |
4163 | void *data; | |
4ae47c2d | 4164 | |
6f0333b8 | 4165 | if (tp->Rx_databuff[i]) |
1da177e4 | 4166 | continue; |
bcf0bf90 | 4167 | |
0ecbe1ca | 4168 | data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
6f0333b8 ED |
4169 | if (!data) { |
4170 | rtl8169_make_unusable_by_asic(tp->RxDescArray + i); | |
0ecbe1ca | 4171 | goto err_out; |
6f0333b8 ED |
4172 | } |
4173 | tp->Rx_databuff[i] = data; | |
1da177e4 | 4174 | } |
1da177e4 | 4175 | |
0ecbe1ca SG |
4176 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
4177 | return 0; | |
4178 | ||
4179 | err_out: | |
4180 | rtl8169_rx_clear(tp); | |
4181 | return -ENOMEM; | |
1da177e4 LT |
4182 | } |
4183 | ||
4184 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) | |
4185 | { | |
4186 | tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; | |
4187 | } | |
4188 | ||
4189 | static int rtl8169_init_ring(struct net_device *dev) | |
4190 | { | |
4191 | struct rtl8169_private *tp = netdev_priv(dev); | |
4192 | ||
4193 | rtl8169_init_ring_indexes(tp); | |
4194 | ||
4195 | memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); | |
6f0333b8 | 4196 | memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
1da177e4 | 4197 | |
0ecbe1ca | 4198 | return rtl8169_rx_fill(tp); |
1da177e4 LT |
4199 | } |
4200 | ||
48addcc9 | 4201 | static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
1da177e4 LT |
4202 | struct TxDesc *desc) |
4203 | { | |
4204 | unsigned int len = tx_skb->len; | |
4205 | ||
48addcc9 SG |
4206 | dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
4207 | ||
1da177e4 LT |
4208 | desc->opts1 = 0x00; |
4209 | desc->opts2 = 0x00; | |
4210 | desc->addr = 0x00; | |
4211 | tx_skb->len = 0; | |
4212 | } | |
4213 | ||
3eafe507 SG |
4214 | static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
4215 | unsigned int n) | |
1da177e4 LT |
4216 | { |
4217 | unsigned int i; | |
4218 | ||
3eafe507 SG |
4219 | for (i = 0; i < n; i++) { |
4220 | unsigned int entry = (start + i) % NUM_TX_DESC; | |
1da177e4 LT |
4221 | struct ring_info *tx_skb = tp->tx_skb + entry; |
4222 | unsigned int len = tx_skb->len; | |
4223 | ||
4224 | if (len) { | |
4225 | struct sk_buff *skb = tx_skb->skb; | |
4226 | ||
48addcc9 | 4227 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
1da177e4 LT |
4228 | tp->TxDescArray + entry); |
4229 | if (skb) { | |
cac4b22f | 4230 | tp->dev->stats.tx_dropped++; |
1da177e4 LT |
4231 | dev_kfree_skb(skb); |
4232 | tx_skb->skb = NULL; | |
4233 | } | |
1da177e4 LT |
4234 | } |
4235 | } | |
3eafe507 SG |
4236 | } |
4237 | ||
4238 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
4239 | { | |
4240 | rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); | |
1da177e4 LT |
4241 | tp->cur_tx = tp->dirty_tx = 0; |
4242 | } | |
4243 | ||
c4028958 | 4244 | static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
1da177e4 LT |
4245 | { |
4246 | struct rtl8169_private *tp = netdev_priv(dev); | |
4247 | ||
c4028958 | 4248 | PREPARE_DELAYED_WORK(&tp->task, task); |
1da177e4 LT |
4249 | schedule_delayed_work(&tp->task, 4); |
4250 | } | |
4251 | ||
4252 | static void rtl8169_wait_for_quiescence(struct net_device *dev) | |
4253 | { | |
4254 | struct rtl8169_private *tp = netdev_priv(dev); | |
4255 | void __iomem *ioaddr = tp->mmio_addr; | |
4256 | ||
4257 | synchronize_irq(dev->irq); | |
4258 | ||
4259 | /* Wait for any pending NAPI task to complete */ | |
bea3348e | 4260 | napi_disable(&tp->napi); |
1da177e4 LT |
4261 | |
4262 | rtl8169_irq_mask_and_ack(ioaddr); | |
4263 | ||
d1d08d12 DM |
4264 | tp->intr_mask = 0xffff; |
4265 | RTL_W16(IntrMask, tp->intr_event); | |
bea3348e | 4266 | napi_enable(&tp->napi); |
1da177e4 LT |
4267 | } |
4268 | ||
c4028958 | 4269 | static void rtl8169_reinit_task(struct work_struct *work) |
1da177e4 | 4270 | { |
c4028958 DH |
4271 | struct rtl8169_private *tp = |
4272 | container_of(work, struct rtl8169_private, task.work); | |
4273 | struct net_device *dev = tp->dev; | |
1da177e4 LT |
4274 | int ret; |
4275 | ||
eb2a021c FR |
4276 | rtnl_lock(); |
4277 | ||
4278 | if (!netif_running(dev)) | |
4279 | goto out_unlock; | |
4280 | ||
4281 | rtl8169_wait_for_quiescence(dev); | |
4282 | rtl8169_close(dev); | |
1da177e4 LT |
4283 | |
4284 | ret = rtl8169_open(dev); | |
4285 | if (unlikely(ret < 0)) { | |
bf82c189 JP |
4286 | if (net_ratelimit()) |
4287 | netif_err(tp, drv, dev, | |
4288 | "reinit failure (status = %d). Rescheduling\n", | |
4289 | ret); | |
1da177e4 LT |
4290 | rtl8169_schedule_work(dev, rtl8169_reinit_task); |
4291 | } | |
eb2a021c FR |
4292 | |
4293 | out_unlock: | |
4294 | rtnl_unlock(); | |
1da177e4 LT |
4295 | } |
4296 | ||
c4028958 | 4297 | static void rtl8169_reset_task(struct work_struct *work) |
1da177e4 | 4298 | { |
c4028958 DH |
4299 | struct rtl8169_private *tp = |
4300 | container_of(work, struct rtl8169_private, task.work); | |
4301 | struct net_device *dev = tp->dev; | |
1da177e4 | 4302 | |
eb2a021c FR |
4303 | rtnl_lock(); |
4304 | ||
1da177e4 | 4305 | if (!netif_running(dev)) |
eb2a021c | 4306 | goto out_unlock; |
1da177e4 LT |
4307 | |
4308 | rtl8169_wait_for_quiescence(dev); | |
4309 | ||
bea3348e | 4310 | rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); |
1da177e4 LT |
4311 | rtl8169_tx_clear(tp); |
4312 | ||
4313 | if (tp->dirty_rx == tp->cur_rx) { | |
4314 | rtl8169_init_ring_indexes(tp); | |
07ce4064 | 4315 | rtl_hw_start(dev); |
1da177e4 | 4316 | netif_wake_queue(dev); |
cebf8cc7 | 4317 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
1da177e4 | 4318 | } else { |
bf82c189 JP |
4319 | if (net_ratelimit()) |
4320 | netif_emerg(tp, intr, dev, "Rx buffers shortage\n"); | |
1da177e4 LT |
4321 | rtl8169_schedule_work(dev, rtl8169_reset_task); |
4322 | } | |
eb2a021c FR |
4323 | |
4324 | out_unlock: | |
4325 | rtnl_unlock(); | |
1da177e4 LT |
4326 | } |
4327 | ||
4328 | static void rtl8169_tx_timeout(struct net_device *dev) | |
4329 | { | |
4330 | struct rtl8169_private *tp = netdev_priv(dev); | |
4331 | ||
e6de30d6 | 4332 | rtl8169_hw_reset(tp); |
1da177e4 LT |
4333 | |
4334 | /* Let's wait a bit while any (async) irq lands on */ | |
4335 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
4336 | } | |
4337 | ||
4338 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
4339 | u32 opts1) | |
4340 | { | |
4341 | struct skb_shared_info *info = skb_shinfo(skb); | |
4342 | unsigned int cur_frag, entry; | |
a6343afb | 4343 | struct TxDesc * uninitialized_var(txd); |
48addcc9 | 4344 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
4345 | |
4346 | entry = tp->cur_tx; | |
4347 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
4348 | skb_frag_t *frag = info->frags + cur_frag; | |
4349 | dma_addr_t mapping; | |
4350 | u32 status, len; | |
4351 | void *addr; | |
4352 | ||
4353 | entry = (entry + 1) % NUM_TX_DESC; | |
4354 | ||
4355 | txd = tp->TxDescArray + entry; | |
4356 | len = frag->size; | |
4357 | addr = ((void *) page_address(frag->page)) + frag->page_offset; | |
48addcc9 | 4358 | mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
d827d86b SG |
4359 | if (unlikely(dma_mapping_error(d, mapping))) { |
4360 | if (net_ratelimit()) | |
4361 | netif_err(tp, drv, tp->dev, | |
4362 | "Failed to map TX fragments DMA!\n"); | |
3eafe507 | 4363 | goto err_out; |
d827d86b | 4364 | } |
1da177e4 LT |
4365 | |
4366 | /* anti gcc 2.95.3 bugware (sic) */ | |
4367 | status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
4368 | ||
4369 | txd->opts1 = cpu_to_le32(status); | |
4370 | txd->addr = cpu_to_le64(mapping); | |
4371 | ||
4372 | tp->tx_skb[entry].len = len; | |
4373 | } | |
4374 | ||
4375 | if (cur_frag) { | |
4376 | tp->tx_skb[entry].skb = skb; | |
4377 | txd->opts1 |= cpu_to_le32(LastFrag); | |
4378 | } | |
4379 | ||
4380 | return cur_frag; | |
3eafe507 SG |
4381 | |
4382 | err_out: | |
4383 | rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); | |
4384 | return -EIO; | |
1da177e4 LT |
4385 | } |
4386 | ||
4387 | static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) | |
4388 | { | |
4389 | if (dev->features & NETIF_F_TSO) { | |
7967168c | 4390 | u32 mss = skb_shinfo(skb)->gso_size; |
1da177e4 LT |
4391 | |
4392 | if (mss) | |
4393 | return LargeSend | ((mss & MSSMask) << MSSShift); | |
4394 | } | |
84fa7933 | 4395 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 | 4396 | const struct iphdr *ip = ip_hdr(skb); |
1da177e4 LT |
4397 | |
4398 | if (ip->protocol == IPPROTO_TCP) | |
4399 | return IPCS | TCPCS; | |
4400 | else if (ip->protocol == IPPROTO_UDP) | |
4401 | return IPCS | UDPCS; | |
4402 | WARN_ON(1); /* we need a WARN() */ | |
4403 | } | |
4404 | return 0; | |
4405 | } | |
4406 | ||
61357325 SH |
4407 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
4408 | struct net_device *dev) | |
1da177e4 LT |
4409 | { |
4410 | struct rtl8169_private *tp = netdev_priv(dev); | |
3eafe507 | 4411 | unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
1da177e4 LT |
4412 | struct TxDesc *txd = tp->TxDescArray + entry; |
4413 | void __iomem *ioaddr = tp->mmio_addr; | |
48addcc9 | 4414 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
4415 | dma_addr_t mapping; |
4416 | u32 status, len; | |
4417 | u32 opts1; | |
3eafe507 | 4418 | int frags; |
5b0384f4 | 4419 | |
1da177e4 | 4420 | if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
bf82c189 | 4421 | netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
3eafe507 | 4422 | goto err_stop_0; |
1da177e4 LT |
4423 | } |
4424 | ||
4425 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
3eafe507 SG |
4426 | goto err_stop_0; |
4427 | ||
4428 | len = skb_headlen(skb); | |
48addcc9 | 4429 | mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
d827d86b SG |
4430 | if (unlikely(dma_mapping_error(d, mapping))) { |
4431 | if (net_ratelimit()) | |
4432 | netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); | |
3eafe507 | 4433 | goto err_dma_0; |
d827d86b | 4434 | } |
3eafe507 SG |
4435 | |
4436 | tp->tx_skb[entry].len = len; | |
4437 | txd->addr = cpu_to_le64(mapping); | |
4438 | txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); | |
1da177e4 LT |
4439 | |
4440 | opts1 = DescOwn | rtl8169_tso_csum(skb, dev); | |
4441 | ||
4442 | frags = rtl8169_xmit_frags(tp, skb, opts1); | |
3eafe507 SG |
4443 | if (frags < 0) |
4444 | goto err_dma_1; | |
4445 | else if (frags) | |
1da177e4 | 4446 | opts1 |= FirstFrag; |
3eafe507 | 4447 | else { |
1da177e4 LT |
4448 | opts1 |= FirstFrag | LastFrag; |
4449 | tp->tx_skb[entry].skb = skb; | |
4450 | } | |
4451 | ||
1da177e4 LT |
4452 | wmb(); |
4453 | ||
4454 | /* anti gcc 2.95.3 bugware (sic) */ | |
4455 | status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
4456 | txd->opts1 = cpu_to_le32(status); | |
4457 | ||
1da177e4 LT |
4458 | tp->cur_tx += frags + 1; |
4459 | ||
4c020a96 | 4460 | wmb(); |
1da177e4 | 4461 | |
275391a4 | 4462 | RTL_W8(TxPoll, NPQ); /* set polling bit */ |
1da177e4 LT |
4463 | |
4464 | if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { | |
4465 | netif_stop_queue(dev); | |
4466 | smp_rmb(); | |
4467 | if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) | |
4468 | netif_wake_queue(dev); | |
4469 | } | |
4470 | ||
61357325 | 4471 | return NETDEV_TX_OK; |
1da177e4 | 4472 | |
3eafe507 | 4473 | err_dma_1: |
48addcc9 | 4474 | rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
3eafe507 SG |
4475 | err_dma_0: |
4476 | dev_kfree_skb(skb); | |
4477 | dev->stats.tx_dropped++; | |
4478 | return NETDEV_TX_OK; | |
4479 | ||
4480 | err_stop_0: | |
1da177e4 | 4481 | netif_stop_queue(dev); |
cebf8cc7 | 4482 | dev->stats.tx_dropped++; |
61357325 | 4483 | return NETDEV_TX_BUSY; |
1da177e4 LT |
4484 | } |
4485 | ||
4486 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
4487 | { | |
4488 | struct rtl8169_private *tp = netdev_priv(dev); | |
4489 | struct pci_dev *pdev = tp->pci_dev; | |
1da177e4 LT |
4490 | u16 pci_status, pci_cmd; |
4491 | ||
4492 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
4493 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
4494 | ||
bf82c189 JP |
4495 | netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
4496 | pci_cmd, pci_status); | |
1da177e4 LT |
4497 | |
4498 | /* | |
4499 | * The recovery sequence below admits a very elaborated explanation: | |
4500 | * - it seems to work; | |
d03902b8 FR |
4501 | * - I did not see what else could be done; |
4502 | * - it makes iop3xx happy. | |
1da177e4 LT |
4503 | * |
4504 | * Feel free to adjust to your needs. | |
4505 | */ | |
a27993f3 | 4506 | if (pdev->broken_parity_status) |
d03902b8 FR |
4507 | pci_cmd &= ~PCI_COMMAND_PARITY; |
4508 | else | |
4509 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
4510 | ||
4511 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
4512 | |
4513 | pci_write_config_word(pdev, PCI_STATUS, | |
4514 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
4515 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
4516 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
4517 | ||
4518 | /* The infamous DAC f*ckup only happens at boot time */ | |
4519 | if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { | |
e6de30d6 | 4520 | void __iomem *ioaddr = tp->mmio_addr; |
4521 | ||
bf82c189 | 4522 | netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
1da177e4 LT |
4523 | tp->cp_cmd &= ~PCIDAC; |
4524 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
4525 | dev->features &= ~NETIF_F_HIGHDMA; | |
1da177e4 LT |
4526 | } |
4527 | ||
e6de30d6 | 4528 | rtl8169_hw_reset(tp); |
d03902b8 FR |
4529 | |
4530 | rtl8169_schedule_work(dev, rtl8169_reinit_task); | |
1da177e4 LT |
4531 | } |
4532 | ||
07d3f51f FR |
4533 | static void rtl8169_tx_interrupt(struct net_device *dev, |
4534 | struct rtl8169_private *tp, | |
4535 | void __iomem *ioaddr) | |
1da177e4 LT |
4536 | { |
4537 | unsigned int dirty_tx, tx_left; | |
4538 | ||
1da177e4 LT |
4539 | dirty_tx = tp->dirty_tx; |
4540 | smp_rmb(); | |
4541 | tx_left = tp->cur_tx - dirty_tx; | |
4542 | ||
4543 | while (tx_left > 0) { | |
4544 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
4545 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
1da177e4 LT |
4546 | u32 status; |
4547 | ||
4548 | rmb(); | |
4549 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); | |
4550 | if (status & DescOwn) | |
4551 | break; | |
4552 | ||
48addcc9 SG |
4553 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
4554 | tp->TxDescArray + entry); | |
1da177e4 | 4555 | if (status & LastFrag) { |
cac4b22f SG |
4556 | dev->stats.tx_packets++; |
4557 | dev->stats.tx_bytes += tx_skb->skb->len; | |
87433bfc | 4558 | dev_kfree_skb(tx_skb->skb); |
1da177e4 LT |
4559 | tx_skb->skb = NULL; |
4560 | } | |
4561 | dirty_tx++; | |
4562 | tx_left--; | |
4563 | } | |
4564 | ||
4565 | if (tp->dirty_tx != dirty_tx) { | |
4566 | tp->dirty_tx = dirty_tx; | |
4567 | smp_wmb(); | |
4568 | if (netif_queue_stopped(dev) && | |
4569 | (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { | |
4570 | netif_wake_queue(dev); | |
4571 | } | |
d78ae2dc FR |
4572 | /* |
4573 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
4574 | * too close. Let's kick an extra TxPoll request when a burst | |
4575 | * of start_xmit activity is detected (if it is not detected, | |
4576 | * it is slow enough). -- FR | |
4577 | */ | |
4578 | smp_rmb(); | |
4579 | if (tp->cur_tx != dirty_tx) | |
4580 | RTL_W8(TxPoll, NPQ); | |
1da177e4 LT |
4581 | } |
4582 | } | |
4583 | ||
126fa4b9 FR |
4584 | static inline int rtl8169_fragmented_frame(u32 status) |
4585 | { | |
4586 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
4587 | } | |
4588 | ||
adea1ac7 | 4589 | static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
1da177e4 | 4590 | { |
1da177e4 LT |
4591 | u32 status = opts1 & RxProtoMask; |
4592 | ||
4593 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
d5d3ebe3 | 4594 | ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
1da177e4 LT |
4595 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
4596 | else | |
bc8acf2c | 4597 | skb_checksum_none_assert(skb); |
1da177e4 LT |
4598 | } |
4599 | ||
6f0333b8 ED |
4600 | static struct sk_buff *rtl8169_try_rx_copy(void *data, |
4601 | struct rtl8169_private *tp, | |
4602 | int pkt_size, | |
4603 | dma_addr_t addr) | |
1da177e4 | 4604 | { |
b449655f | 4605 | struct sk_buff *skb; |
48addcc9 | 4606 | struct device *d = &tp->pci_dev->dev; |
b449655f | 4607 | |
6f0333b8 | 4608 | data = rtl8169_align(data); |
48addcc9 | 4609 | dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
6f0333b8 ED |
4610 | prefetch(data); |
4611 | skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); | |
4612 | if (skb) | |
4613 | memcpy(skb->data, data, pkt_size); | |
48addcc9 SG |
4614 | dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
4615 | ||
6f0333b8 | 4616 | return skb; |
1da177e4 LT |
4617 | } |
4618 | ||
630b943c ED |
4619 | /* |
4620 | * Warning : rtl8169_rx_interrupt() might be called : | |
4621 | * 1) from NAPI (softirq) context | |
4622 | * (polling = 1 : we should call netif_receive_skb()) | |
4623 | * 2) from process context (rtl8169_reset_task()) | |
4624 | * (polling = 0 : we must call netif_rx() instead) | |
4625 | */ | |
07d3f51f FR |
4626 | static int rtl8169_rx_interrupt(struct net_device *dev, |
4627 | struct rtl8169_private *tp, | |
bea3348e | 4628 | void __iomem *ioaddr, u32 budget) |
1da177e4 LT |
4629 | { |
4630 | unsigned int cur_rx, rx_left; | |
6f0333b8 | 4631 | unsigned int count; |
630b943c | 4632 | int polling = (budget != ~(u32)0) ? 1 : 0; |
1da177e4 | 4633 | |
1da177e4 LT |
4634 | cur_rx = tp->cur_rx; |
4635 | rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; | |
865c652d | 4636 | rx_left = min(rx_left, budget); |
1da177e4 | 4637 | |
4dcb7d33 | 4638 | for (; rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 4639 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 4640 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
4641 | u32 status; |
4642 | ||
4643 | rmb(); | |
126fa4b9 | 4644 | status = le32_to_cpu(desc->opts1); |
1da177e4 LT |
4645 | |
4646 | if (status & DescOwn) | |
4647 | break; | |
4dcb7d33 | 4648 | if (unlikely(status & RxRES)) { |
bf82c189 JP |
4649 | netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
4650 | status); | |
cebf8cc7 | 4651 | dev->stats.rx_errors++; |
1da177e4 | 4652 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 4653 | dev->stats.rx_length_errors++; |
1da177e4 | 4654 | if (status & RxCRC) |
cebf8cc7 | 4655 | dev->stats.rx_crc_errors++; |
9dccf611 FR |
4656 | if (status & RxFOVF) { |
4657 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
cebf8cc7 | 4658 | dev->stats.rx_fifo_errors++; |
9dccf611 | 4659 | } |
6f0333b8 | 4660 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
1da177e4 | 4661 | } else { |
6f0333b8 | 4662 | struct sk_buff *skb; |
b449655f | 4663 | dma_addr_t addr = le64_to_cpu(desc->addr); |
1da177e4 | 4664 | int pkt_size = (status & 0x00001FFF) - 4; |
1da177e4 | 4665 | |
126fa4b9 FR |
4666 | /* |
4667 | * The driver does not support incoming fragmented | |
4668 | * frames. They are seen as a symptom of over-mtu | |
4669 | * sized frames. | |
4670 | */ | |
4671 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
4672 | dev->stats.rx_dropped++; |
4673 | dev->stats.rx_length_errors++; | |
6f0333b8 | 4674 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
4dcb7d33 | 4675 | continue; |
126fa4b9 FR |
4676 | } |
4677 | ||
6f0333b8 ED |
4678 | skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
4679 | tp, pkt_size, addr); | |
4680 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
4681 | if (!skb) { | |
4682 | dev->stats.rx_dropped++; | |
4683 | continue; | |
1da177e4 LT |
4684 | } |
4685 | ||
adea1ac7 | 4686 | rtl8169_rx_csum(skb, status); |
1da177e4 LT |
4687 | skb_put(skb, pkt_size); |
4688 | skb->protocol = eth_type_trans(skb, dev); | |
4689 | ||
7a8fc77b FR |
4690 | rtl8169_rx_vlan_tag(desc, skb); |
4691 | ||
4692 | if (likely(polling)) | |
4693 | napi_gro_receive(&tp->napi, skb); | |
4694 | else | |
4695 | netif_rx(skb); | |
1da177e4 | 4696 | |
cebf8cc7 FR |
4697 | dev->stats.rx_bytes += pkt_size; |
4698 | dev->stats.rx_packets++; | |
1da177e4 | 4699 | } |
6dccd16b FR |
4700 | |
4701 | /* Work around for AMD plateform. */ | |
95e0918d | 4702 | if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
6dccd16b FR |
4703 | (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
4704 | desc->opts2 = 0; | |
4705 | cur_rx++; | |
4706 | } | |
1da177e4 LT |
4707 | } |
4708 | ||
4709 | count = cur_rx - tp->cur_rx; | |
4710 | tp->cur_rx = cur_rx; | |
4711 | ||
6f0333b8 | 4712 | tp->dirty_rx += count; |
1da177e4 LT |
4713 | |
4714 | return count; | |
4715 | } | |
4716 | ||
07d3f51f | 4717 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 4718 | { |
07d3f51f | 4719 | struct net_device *dev = dev_instance; |
1da177e4 | 4720 | struct rtl8169_private *tp = netdev_priv(dev); |
1da177e4 | 4721 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 4722 | int handled = 0; |
865c652d | 4723 | int status; |
1da177e4 | 4724 | |
f11a377b DD |
4725 | /* loop handling interrupts until we have no new ones or |
4726 | * we hit a invalid/hotplug case. | |
4727 | */ | |
865c652d | 4728 | status = RTL_R16(IntrStatus); |
f11a377b DD |
4729 | while (status && status != 0xffff) { |
4730 | handled = 1; | |
1da177e4 | 4731 | |
f11a377b DD |
4732 | /* Handle all of the error cases first. These will reset |
4733 | * the chip, so just exit the loop. | |
4734 | */ | |
4735 | if (unlikely(!netif_running(dev))) { | |
4736 | rtl8169_asic_down(ioaddr); | |
4737 | break; | |
4738 | } | |
1da177e4 | 4739 | |
1519e57f FR |
4740 | if (unlikely(status & RxFIFOOver)) { |
4741 | switch (tp->mac_version) { | |
4742 | /* Work around for rx fifo overflow */ | |
4743 | case RTL_GIGA_MAC_VER_11: | |
4744 | case RTL_GIGA_MAC_VER_22: | |
4745 | case RTL_GIGA_MAC_VER_26: | |
4746 | netif_stop_queue(dev); | |
4747 | rtl8169_tx_timeout(dev); | |
4748 | goto done; | |
f60ac8e7 FR |
4749 | /* Testers needed. */ |
4750 | case RTL_GIGA_MAC_VER_17: | |
4751 | case RTL_GIGA_MAC_VER_19: | |
4752 | case RTL_GIGA_MAC_VER_20: | |
4753 | case RTL_GIGA_MAC_VER_21: | |
4754 | case RTL_GIGA_MAC_VER_23: | |
4755 | case RTL_GIGA_MAC_VER_24: | |
4756 | case RTL_GIGA_MAC_VER_27: | |
4757 | case RTL_GIGA_MAC_VER_28: | |
1519e57f FR |
4758 | /* Experimental science. Pktgen proof. */ |
4759 | case RTL_GIGA_MAC_VER_12: | |
4760 | case RTL_GIGA_MAC_VER_25: | |
4761 | if (status == RxFIFOOver) | |
4762 | goto done; | |
4763 | break; | |
4764 | default: | |
4765 | break; | |
4766 | } | |
f11a377b | 4767 | } |
1da177e4 | 4768 | |
f11a377b DD |
4769 | if (unlikely(status & SYSErr)) { |
4770 | rtl8169_pcierr_interrupt(dev); | |
4771 | break; | |
4772 | } | |
1da177e4 | 4773 | |
f11a377b | 4774 | if (status & LinkChg) |
e4fbce74 | 4775 | __rtl8169_check_link_status(dev, tp, ioaddr, true); |
0e485150 | 4776 | |
f11a377b DD |
4777 | /* We need to see the lastest version of tp->intr_mask to |
4778 | * avoid ignoring an MSI interrupt and having to wait for | |
4779 | * another event which may never come. | |
4780 | */ | |
4781 | smp_rmb(); | |
4782 | if (status & tp->intr_mask & tp->napi_event) { | |
4783 | RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); | |
4784 | tp->intr_mask = ~tp->napi_event; | |
4785 | ||
4786 | if (likely(napi_schedule_prep(&tp->napi))) | |
4787 | __napi_schedule(&tp->napi); | |
bf82c189 JP |
4788 | else |
4789 | netif_info(tp, intr, dev, | |
4790 | "interrupt %04x in poll\n", status); | |
f11a377b | 4791 | } |
1da177e4 | 4792 | |
f11a377b DD |
4793 | /* We only get a new MSI interrupt when all active irq |
4794 | * sources on the chip have been acknowledged. So, ack | |
4795 | * everything we've seen and check if new sources have become | |
4796 | * active to avoid blocking all interrupts from the chip. | |
4797 | */ | |
4798 | RTL_W16(IntrStatus, | |
4799 | (status & RxFIFOOver) ? (status | RxOverflow) : status); | |
4800 | status = RTL_R16(IntrStatus); | |
865c652d | 4801 | } |
1519e57f | 4802 | done: |
1da177e4 LT |
4803 | return IRQ_RETVAL(handled); |
4804 | } | |
4805 | ||
bea3348e | 4806 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 4807 | { |
bea3348e SH |
4808 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
4809 | struct net_device *dev = tp->dev; | |
1da177e4 | 4810 | void __iomem *ioaddr = tp->mmio_addr; |
bea3348e | 4811 | int work_done; |
1da177e4 | 4812 | |
bea3348e | 4813 | work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
1da177e4 LT |
4814 | rtl8169_tx_interrupt(dev, tp, ioaddr); |
4815 | ||
bea3348e | 4816 | if (work_done < budget) { |
288379f0 | 4817 | napi_complete(napi); |
f11a377b DD |
4818 | |
4819 | /* We need for force the visibility of tp->intr_mask | |
4820 | * for other CPUs, as we can loose an MSI interrupt | |
4821 | * and potentially wait for a retransmit timeout if we don't. | |
4822 | * The posted write to IntrMask is safe, as it will | |
4823 | * eventually make it to the chip and we won't loose anything | |
4824 | * until it does. | |
1da177e4 | 4825 | */ |
f11a377b | 4826 | tp->intr_mask = 0xffff; |
4c020a96 | 4827 | wmb(); |
0e485150 | 4828 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
4829 | } |
4830 | ||
bea3348e | 4831 | return work_done; |
1da177e4 | 4832 | } |
1da177e4 | 4833 | |
523a6094 FR |
4834 | static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
4835 | { | |
4836 | struct rtl8169_private *tp = netdev_priv(dev); | |
4837 | ||
4838 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) | |
4839 | return; | |
4840 | ||
4841 | dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); | |
4842 | RTL_W32(RxMissed, 0); | |
4843 | } | |
4844 | ||
1da177e4 LT |
4845 | static void rtl8169_down(struct net_device *dev) |
4846 | { | |
4847 | struct rtl8169_private *tp = netdev_priv(dev); | |
4848 | void __iomem *ioaddr = tp->mmio_addr; | |
1da177e4 LT |
4849 | |
4850 | rtl8169_delete_timer(dev); | |
4851 | ||
4852 | netif_stop_queue(dev); | |
4853 | ||
93dd79e8 | 4854 | napi_disable(&tp->napi); |
93dd79e8 | 4855 | |
1da177e4 LT |
4856 | spin_lock_irq(&tp->lock); |
4857 | ||
4858 | rtl8169_asic_down(ioaddr); | |
323bb685 SG |
4859 | /* |
4860 | * At this point device interrupts can not be enabled in any function, | |
4861 | * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task, | |
4862 | * rtl8169_reinit_task) and napi is disabled (rtl8169_poll). | |
4863 | */ | |
523a6094 | 4864 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
4865 | |
4866 | spin_unlock_irq(&tp->lock); | |
4867 | ||
4868 | synchronize_irq(dev->irq); | |
4869 | ||
1da177e4 | 4870 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
fbd568a3 | 4871 | synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
1da177e4 | 4872 | |
1da177e4 LT |
4873 | rtl8169_tx_clear(tp); |
4874 | ||
4875 | rtl8169_rx_clear(tp); | |
065c27c1 | 4876 | |
4877 | rtl_pll_power_down(tp); | |
1da177e4 LT |
4878 | } |
4879 | ||
4880 | static int rtl8169_close(struct net_device *dev) | |
4881 | { | |
4882 | struct rtl8169_private *tp = netdev_priv(dev); | |
4883 | struct pci_dev *pdev = tp->pci_dev; | |
4884 | ||
e1759441 RW |
4885 | pm_runtime_get_sync(&pdev->dev); |
4886 | ||
355423d0 IV |
4887 | /* update counters before going down */ |
4888 | rtl8169_update_counters(dev); | |
4889 | ||
1da177e4 LT |
4890 | rtl8169_down(dev); |
4891 | ||
4892 | free_irq(dev->irq, dev); | |
4893 | ||
82553bb6 SG |
4894 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
4895 | tp->RxPhyAddr); | |
4896 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
4897 | tp->TxPhyAddr); | |
1da177e4 LT |
4898 | tp->TxDescArray = NULL; |
4899 | tp->RxDescArray = NULL; | |
4900 | ||
e1759441 RW |
4901 | pm_runtime_put_sync(&pdev->dev); |
4902 | ||
1da177e4 LT |
4903 | return 0; |
4904 | } | |
4905 | ||
07ce4064 | 4906 | static void rtl_set_rx_mode(struct net_device *dev) |
1da177e4 LT |
4907 | { |
4908 | struct rtl8169_private *tp = netdev_priv(dev); | |
4909 | void __iomem *ioaddr = tp->mmio_addr; | |
4910 | unsigned long flags; | |
4911 | u32 mc_filter[2]; /* Multicast hash filter */ | |
07d3f51f | 4912 | int rx_mode; |
1da177e4 LT |
4913 | u32 tmp = 0; |
4914 | ||
4915 | if (dev->flags & IFF_PROMISC) { | |
4916 | /* Unconditionally log net taps. */ | |
bf82c189 | 4917 | netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); |
1da177e4 LT |
4918 | rx_mode = |
4919 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
4920 | AcceptAllPhys; | |
4921 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
4cd24eaf | 4922 | } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
8e95a202 | 4923 | (dev->flags & IFF_ALLMULTI)) { |
1da177e4 LT |
4924 | /* Too many to filter perfectly -- accept all multicasts. */ |
4925 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
4926 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
4927 | } else { | |
22bedad3 | 4928 | struct netdev_hw_addr *ha; |
07d3f51f | 4929 | |
1da177e4 LT |
4930 | rx_mode = AcceptBroadcast | AcceptMyPhys; |
4931 | mc_filter[1] = mc_filter[0] = 0; | |
22bedad3 JP |
4932 | netdev_for_each_mc_addr(ha, dev) { |
4933 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
1da177e4 LT |
4934 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
4935 | rx_mode |= AcceptMulticast; | |
4936 | } | |
4937 | } | |
4938 | ||
4939 | spin_lock_irqsave(&tp->lock, flags); | |
4940 | ||
4941 | tmp = rtl8169_rx_config | rx_mode | | |
4942 | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); | |
4943 | ||
f887cce8 | 4944 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
1087f4f4 FR |
4945 | u32 data = mc_filter[0]; |
4946 | ||
4947 | mc_filter[0] = swab32(mc_filter[1]); | |
4948 | mc_filter[1] = swab32(data); | |
bcf0bf90 FR |
4949 | } |
4950 | ||
1da177e4 | 4951 | RTL_W32(MAR0 + 4, mc_filter[1]); |
78f1cd02 | 4952 | RTL_W32(MAR0 + 0, mc_filter[0]); |
1da177e4 | 4953 | |
57a9f236 FR |
4954 | RTL_W32(RxConfig, tmp); |
4955 | ||
1da177e4 LT |
4956 | spin_unlock_irqrestore(&tp->lock, flags); |
4957 | } | |
4958 | ||
4959 | /** | |
4960 | * rtl8169_get_stats - Get rtl8169 read/write statistics | |
4961 | * @dev: The Ethernet Device to get statistics for | |
4962 | * | |
4963 | * Get TX/RX statistics for rtl8169 | |
4964 | */ | |
4965 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) | |
4966 | { | |
4967 | struct rtl8169_private *tp = netdev_priv(dev); | |
4968 | void __iomem *ioaddr = tp->mmio_addr; | |
4969 | unsigned long flags; | |
4970 | ||
4971 | if (netif_running(dev)) { | |
4972 | spin_lock_irqsave(&tp->lock, flags); | |
523a6094 | 4973 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
4974 | spin_unlock_irqrestore(&tp->lock, flags); |
4975 | } | |
5b0384f4 | 4976 | |
cebf8cc7 | 4977 | return &dev->stats; |
1da177e4 LT |
4978 | } |
4979 | ||
861ab440 | 4980 | static void rtl8169_net_suspend(struct net_device *dev) |
5d06a99f | 4981 | { |
065c27c1 | 4982 | struct rtl8169_private *tp = netdev_priv(dev); |
4983 | ||
5d06a99f | 4984 | if (!netif_running(dev)) |
861ab440 | 4985 | return; |
5d06a99f | 4986 | |
065c27c1 | 4987 | rtl_pll_power_down(tp); |
4988 | ||
5d06a99f FR |
4989 | netif_device_detach(dev); |
4990 | netif_stop_queue(dev); | |
861ab440 RW |
4991 | } |
4992 | ||
4993 | #ifdef CONFIG_PM | |
4994 | ||
4995 | static int rtl8169_suspend(struct device *device) | |
4996 | { | |
4997 | struct pci_dev *pdev = to_pci_dev(device); | |
4998 | struct net_device *dev = pci_get_drvdata(pdev); | |
5d06a99f | 4999 | |
861ab440 | 5000 | rtl8169_net_suspend(dev); |
1371fa6d | 5001 | |
5d06a99f FR |
5002 | return 0; |
5003 | } | |
5004 | ||
e1759441 RW |
5005 | static void __rtl8169_resume(struct net_device *dev) |
5006 | { | |
065c27c1 | 5007 | struct rtl8169_private *tp = netdev_priv(dev); |
5008 | ||
e1759441 | 5009 | netif_device_attach(dev); |
065c27c1 | 5010 | |
5011 | rtl_pll_power_up(tp); | |
5012 | ||
e1759441 RW |
5013 | rtl8169_schedule_work(dev, rtl8169_reset_task); |
5014 | } | |
5015 | ||
861ab440 | 5016 | static int rtl8169_resume(struct device *device) |
5d06a99f | 5017 | { |
861ab440 | 5018 | struct pci_dev *pdev = to_pci_dev(device); |
5d06a99f | 5019 | struct net_device *dev = pci_get_drvdata(pdev); |
fccec10b SG |
5020 | struct rtl8169_private *tp = netdev_priv(dev); |
5021 | ||
5022 | rtl8169_init_phy(dev, tp); | |
5d06a99f | 5023 | |
e1759441 RW |
5024 | if (netif_running(dev)) |
5025 | __rtl8169_resume(dev); | |
5d06a99f | 5026 | |
e1759441 RW |
5027 | return 0; |
5028 | } | |
5029 | ||
5030 | static int rtl8169_runtime_suspend(struct device *device) | |
5031 | { | |
5032 | struct pci_dev *pdev = to_pci_dev(device); | |
5033 | struct net_device *dev = pci_get_drvdata(pdev); | |
5034 | struct rtl8169_private *tp = netdev_priv(dev); | |
5035 | ||
5036 | if (!tp->TxDescArray) | |
5037 | return 0; | |
5038 | ||
5039 | spin_lock_irq(&tp->lock); | |
5040 | tp->saved_wolopts = __rtl8169_get_wol(tp); | |
5041 | __rtl8169_set_wol(tp, WAKE_ANY); | |
5042 | spin_unlock_irq(&tp->lock); | |
5043 | ||
5044 | rtl8169_net_suspend(dev); | |
5045 | ||
5046 | return 0; | |
5047 | } | |
5048 | ||
5049 | static int rtl8169_runtime_resume(struct device *device) | |
5050 | { | |
5051 | struct pci_dev *pdev = to_pci_dev(device); | |
5052 | struct net_device *dev = pci_get_drvdata(pdev); | |
5053 | struct rtl8169_private *tp = netdev_priv(dev); | |
5054 | ||
5055 | if (!tp->TxDescArray) | |
5056 | return 0; | |
5057 | ||
5058 | spin_lock_irq(&tp->lock); | |
5059 | __rtl8169_set_wol(tp, tp->saved_wolopts); | |
5060 | tp->saved_wolopts = 0; | |
5061 | spin_unlock_irq(&tp->lock); | |
5062 | ||
fccec10b SG |
5063 | rtl8169_init_phy(dev, tp); |
5064 | ||
e1759441 | 5065 | __rtl8169_resume(dev); |
5d06a99f | 5066 | |
5d06a99f FR |
5067 | return 0; |
5068 | } | |
5069 | ||
e1759441 RW |
5070 | static int rtl8169_runtime_idle(struct device *device) |
5071 | { | |
5072 | struct pci_dev *pdev = to_pci_dev(device); | |
5073 | struct net_device *dev = pci_get_drvdata(pdev); | |
5074 | struct rtl8169_private *tp = netdev_priv(dev); | |
5075 | ||
e4fbce74 | 5076 | return tp->TxDescArray ? -EBUSY : 0; |
e1759441 RW |
5077 | } |
5078 | ||
47145210 | 5079 | static const struct dev_pm_ops rtl8169_pm_ops = { |
861ab440 RW |
5080 | .suspend = rtl8169_suspend, |
5081 | .resume = rtl8169_resume, | |
5082 | .freeze = rtl8169_suspend, | |
5083 | .thaw = rtl8169_resume, | |
5084 | .poweroff = rtl8169_suspend, | |
5085 | .restore = rtl8169_resume, | |
e1759441 RW |
5086 | .runtime_suspend = rtl8169_runtime_suspend, |
5087 | .runtime_resume = rtl8169_runtime_resume, | |
5088 | .runtime_idle = rtl8169_runtime_idle, | |
861ab440 RW |
5089 | }; |
5090 | ||
5091 | #define RTL8169_PM_OPS (&rtl8169_pm_ops) | |
5092 | ||
5093 | #else /* !CONFIG_PM */ | |
5094 | ||
5095 | #define RTL8169_PM_OPS NULL | |
5096 | ||
5097 | #endif /* !CONFIG_PM */ | |
5098 | ||
1765f95d FR |
5099 | static void rtl_shutdown(struct pci_dev *pdev) |
5100 | { | |
861ab440 | 5101 | struct net_device *dev = pci_get_drvdata(pdev); |
4bb3f522 | 5102 | struct rtl8169_private *tp = netdev_priv(dev); |
5103 | void __iomem *ioaddr = tp->mmio_addr; | |
861ab440 RW |
5104 | |
5105 | rtl8169_net_suspend(dev); | |
1765f95d | 5106 | |
cc098dc7 IV |
5107 | /* restore original MAC address */ |
5108 | rtl_rar_set(tp, dev->perm_addr); | |
5109 | ||
4bb3f522 | 5110 | spin_lock_irq(&tp->lock); |
5111 | ||
5112 | rtl8169_asic_down(ioaddr); | |
5113 | ||
5114 | spin_unlock_irq(&tp->lock); | |
5115 | ||
861ab440 | 5116 | if (system_state == SYSTEM_POWER_OFF) { |
ca52efd5 | 5117 | /* WoL fails with some 8168 when the receiver is disabled. */ |
5118 | if (tp->features & RTL_FEATURE_WOL) { | |
5119 | pci_clear_master(pdev); | |
5120 | ||
5121 | RTL_W8(ChipCmd, CmdRxEnb); | |
5122 | /* PCI commit */ | |
5123 | RTL_R8(ChipCmd); | |
5124 | } | |
5125 | ||
861ab440 RW |
5126 | pci_wake_from_d3(pdev, true); |
5127 | pci_set_power_state(pdev, PCI_D3hot); | |
5128 | } | |
5129 | } | |
5d06a99f | 5130 | |
1da177e4 LT |
5131 | static struct pci_driver rtl8169_pci_driver = { |
5132 | .name = MODULENAME, | |
5133 | .id_table = rtl8169_pci_tbl, | |
5134 | .probe = rtl8169_init_one, | |
5135 | .remove = __devexit_p(rtl8169_remove_one), | |
1765f95d | 5136 | .shutdown = rtl_shutdown, |
861ab440 | 5137 | .driver.pm = RTL8169_PM_OPS, |
1da177e4 LT |
5138 | }; |
5139 | ||
07d3f51f | 5140 | static int __init rtl8169_init_module(void) |
1da177e4 | 5141 | { |
29917620 | 5142 | return pci_register_driver(&rtl8169_pci_driver); |
1da177e4 LT |
5143 | } |
5144 | ||
07d3f51f | 5145 | static void __exit rtl8169_cleanup_module(void) |
1da177e4 LT |
5146 | { |
5147 | pci_unregister_driver(&rtl8169_pci_driver); | |
5148 | } | |
5149 | ||
5150 | module_init(rtl8169_init_module); | |
5151 | module_exit(rtl8169_cleanup_module); |