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Commit | Line | Data |
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1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
24 | #include <linux/init.h> | |
a6b7a407 | 25 | #include <linux/interrupt.h> |
1da177e4 | 26 | #include <linux/dma-mapping.h> |
e1759441 | 27 | #include <linux/pm_runtime.h> |
bca03d5f | 28 | #include <linux/firmware.h> |
ba04c7c9 | 29 | #include <linux/pci-aspm.h> |
70c71606 | 30 | #include <linux/prefetch.h> |
1da177e4 | 31 | |
99f252b0 | 32 | #include <asm/system.h> |
1da177e4 LT |
33 | #include <asm/io.h> |
34 | #include <asm/irq.h> | |
35 | ||
865c652d | 36 | #define RTL8169_VERSION "2.3LK-NAPI" |
1da177e4 LT |
37 | #define MODULENAME "r8169" |
38 | #define PFX MODULENAME ": " | |
39 | ||
bca03d5f | 40 | #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
41 | #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" | |
01dc7fec | 42 | #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
43 | #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" | |
70090424 | 44 | #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw" |
5a5e4443 | 45 | #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
bca03d5f | 46 | |
1da177e4 LT |
47 | #ifdef RTL8169_DEBUG |
48 | #define assert(expr) \ | |
5b0384f4 FR |
49 | if (!(expr)) { \ |
50 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
b39d66a8 | 51 | #expr,__FILE__,__func__,__LINE__); \ |
5b0384f4 | 52 | } |
06fa7358 JP |
53 | #define dprintk(fmt, args...) \ |
54 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
55 | #else |
56 | #define assert(expr) do {} while (0) | |
57 | #define dprintk(fmt, args...) do {} while (0) | |
58 | #endif /* RTL8169_DEBUG */ | |
59 | ||
b57b7e5a | 60 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 61 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 62 | |
1da177e4 LT |
63 | #define TX_BUFFS_AVAIL(tp) \ |
64 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) | |
65 | ||
1da177e4 LT |
66 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
67 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 68 | static const int multicast_filter_limit = 32; |
1da177e4 LT |
69 | |
70 | /* MAC address length */ | |
71 | #define MAC_ADDR_LEN 6 | |
72 | ||
9c14ceaf | 73 | #define MAX_READ_REQUEST_SHIFT 12 |
1da177e4 | 74 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ |
1da177e4 LT |
75 | #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
76 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
77 | ||
78 | #define R8169_REGS_SIZE 256 | |
79 | #define R8169_NAPI_WEIGHT 64 | |
80 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
81 | #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ | |
82 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ | |
83 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) | |
84 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
85 | ||
86 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
87 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
88 | ||
ea8dbdd1 | 89 | #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
90 | #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) | |
e1564ec9 FR |
91 | #define RTL_EEPROM_SIG_ADDR 0x0000 |
92 | ||
1da177e4 LT |
93 | /* write/read MMIO register */ |
94 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
95 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
96 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
97 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
98 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
06f555f3 | 99 | #define RTL_R32(reg) readl (ioaddr + (reg)) |
1da177e4 LT |
100 | |
101 | enum mac_version { | |
85bffe6c FR |
102 | RTL_GIGA_MAC_VER_01 = 0, |
103 | RTL_GIGA_MAC_VER_02, | |
104 | RTL_GIGA_MAC_VER_03, | |
105 | RTL_GIGA_MAC_VER_04, | |
106 | RTL_GIGA_MAC_VER_05, | |
107 | RTL_GIGA_MAC_VER_06, | |
108 | RTL_GIGA_MAC_VER_07, | |
109 | RTL_GIGA_MAC_VER_08, | |
110 | RTL_GIGA_MAC_VER_09, | |
111 | RTL_GIGA_MAC_VER_10, | |
112 | RTL_GIGA_MAC_VER_11, | |
113 | RTL_GIGA_MAC_VER_12, | |
114 | RTL_GIGA_MAC_VER_13, | |
115 | RTL_GIGA_MAC_VER_14, | |
116 | RTL_GIGA_MAC_VER_15, | |
117 | RTL_GIGA_MAC_VER_16, | |
118 | RTL_GIGA_MAC_VER_17, | |
119 | RTL_GIGA_MAC_VER_18, | |
120 | RTL_GIGA_MAC_VER_19, | |
121 | RTL_GIGA_MAC_VER_20, | |
122 | RTL_GIGA_MAC_VER_21, | |
123 | RTL_GIGA_MAC_VER_22, | |
124 | RTL_GIGA_MAC_VER_23, | |
125 | RTL_GIGA_MAC_VER_24, | |
126 | RTL_GIGA_MAC_VER_25, | |
127 | RTL_GIGA_MAC_VER_26, | |
128 | RTL_GIGA_MAC_VER_27, | |
129 | RTL_GIGA_MAC_VER_28, | |
130 | RTL_GIGA_MAC_VER_29, | |
131 | RTL_GIGA_MAC_VER_30, | |
132 | RTL_GIGA_MAC_VER_31, | |
133 | RTL_GIGA_MAC_VER_32, | |
134 | RTL_GIGA_MAC_VER_33, | |
70090424 | 135 | RTL_GIGA_MAC_VER_34, |
85bffe6c | 136 | RTL_GIGA_MAC_NONE = 0xff, |
1da177e4 LT |
137 | }; |
138 | ||
2b7b4318 FR |
139 | enum rtl_tx_desc_version { |
140 | RTL_TD_0 = 0, | |
141 | RTL_TD_1 = 1, | |
142 | }; | |
143 | ||
85bffe6c FR |
144 | #define _R(NAME,TD,FW) \ |
145 | { .name = NAME, .txd_version = TD, .fw_name = FW } | |
1da177e4 | 146 | |
3c6bee1d | 147 | static const struct { |
1da177e4 | 148 | const char *name; |
2b7b4318 | 149 | enum rtl_tx_desc_version txd_version; |
953a12cc | 150 | const char *fw_name; |
85bffe6c FR |
151 | } rtl_chip_infos[] = { |
152 | /* PCI devices. */ | |
153 | [RTL_GIGA_MAC_VER_01] = | |
154 | _R("RTL8169", RTL_TD_0, NULL), | |
155 | [RTL_GIGA_MAC_VER_02] = | |
156 | _R("RTL8169s", RTL_TD_0, NULL), | |
157 | [RTL_GIGA_MAC_VER_03] = | |
158 | _R("RTL8110s", RTL_TD_0, NULL), | |
159 | [RTL_GIGA_MAC_VER_04] = | |
160 | _R("RTL8169sb/8110sb", RTL_TD_0, NULL), | |
161 | [RTL_GIGA_MAC_VER_05] = | |
162 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL), | |
163 | [RTL_GIGA_MAC_VER_06] = | |
164 | _R("RTL8169sc/8110sc", RTL_TD_0, NULL), | |
165 | /* PCI-E devices. */ | |
166 | [RTL_GIGA_MAC_VER_07] = | |
167 | _R("RTL8102e", RTL_TD_1, NULL), | |
168 | [RTL_GIGA_MAC_VER_08] = | |
169 | _R("RTL8102e", RTL_TD_1, NULL), | |
170 | [RTL_GIGA_MAC_VER_09] = | |
171 | _R("RTL8102e", RTL_TD_1, NULL), | |
172 | [RTL_GIGA_MAC_VER_10] = | |
173 | _R("RTL8101e", RTL_TD_0, NULL), | |
174 | [RTL_GIGA_MAC_VER_11] = | |
175 | _R("RTL8168b/8111b", RTL_TD_0, NULL), | |
176 | [RTL_GIGA_MAC_VER_12] = | |
177 | _R("RTL8168b/8111b", RTL_TD_0, NULL), | |
178 | [RTL_GIGA_MAC_VER_13] = | |
179 | _R("RTL8101e", RTL_TD_0, NULL), | |
180 | [RTL_GIGA_MAC_VER_14] = | |
181 | _R("RTL8100e", RTL_TD_0, NULL), | |
182 | [RTL_GIGA_MAC_VER_15] = | |
183 | _R("RTL8100e", RTL_TD_0, NULL), | |
184 | [RTL_GIGA_MAC_VER_16] = | |
185 | _R("RTL8101e", RTL_TD_0, NULL), | |
186 | [RTL_GIGA_MAC_VER_17] = | |
187 | _R("RTL8168b/8111b", RTL_TD_0, NULL), | |
188 | [RTL_GIGA_MAC_VER_18] = | |
189 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL), | |
190 | [RTL_GIGA_MAC_VER_19] = | |
191 | _R("RTL8168c/8111c", RTL_TD_1, NULL), | |
192 | [RTL_GIGA_MAC_VER_20] = | |
193 | _R("RTL8168c/8111c", RTL_TD_1, NULL), | |
194 | [RTL_GIGA_MAC_VER_21] = | |
195 | _R("RTL8168c/8111c", RTL_TD_1, NULL), | |
196 | [RTL_GIGA_MAC_VER_22] = | |
197 | _R("RTL8168c/8111c", RTL_TD_1, NULL), | |
198 | [RTL_GIGA_MAC_VER_23] = | |
199 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL), | |
200 | [RTL_GIGA_MAC_VER_24] = | |
201 | _R("RTL8168cp/8111cp", RTL_TD_1, NULL), | |
202 | [RTL_GIGA_MAC_VER_25] = | |
203 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1), | |
204 | [RTL_GIGA_MAC_VER_26] = | |
205 | _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2), | |
206 | [RTL_GIGA_MAC_VER_27] = | |
207 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL), | |
208 | [RTL_GIGA_MAC_VER_28] = | |
209 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL), | |
210 | [RTL_GIGA_MAC_VER_29] = | |
211 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1), | |
212 | [RTL_GIGA_MAC_VER_30] = | |
213 | _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1), | |
214 | [RTL_GIGA_MAC_VER_31] = | |
215 | _R("RTL8168dp/8111dp", RTL_TD_1, NULL), | |
216 | [RTL_GIGA_MAC_VER_32] = | |
217 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1), | |
218 | [RTL_GIGA_MAC_VER_33] = | |
70090424 HW |
219 | _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2), |
220 | [RTL_GIGA_MAC_VER_34] = | |
221 | _R("RTL8168evl/8111evl",RTL_TD_1, FIRMWARE_8168E_3) | |
953a12cc | 222 | }; |
85bffe6c | 223 | #undef _R |
953a12cc | 224 | |
bcf0bf90 FR |
225 | enum cfg_version { |
226 | RTL_CFG_0 = 0x00, | |
227 | RTL_CFG_1, | |
228 | RTL_CFG_2 | |
229 | }; | |
230 | ||
07ce4064 FR |
231 | static void rtl_hw_start_8169(struct net_device *); |
232 | static void rtl_hw_start_8168(struct net_device *); | |
233 | static void rtl_hw_start_8101(struct net_device *); | |
234 | ||
a3aa1884 | 235 | static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { |
bcf0bf90 | 236 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 237 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 238 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 239 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 FR |
240 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
241 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, | |
93a3aa25 | 242 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 }, |
bc1660b5 | 243 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
244 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
245 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
246 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
247 | { 0x0001, 0x8168, |
248 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
249 | {0,}, |
250 | }; | |
251 | ||
252 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
253 | ||
6f0333b8 | 254 | static int rx_buf_sz = 16383; |
4300e8c7 | 255 | static int use_dac; |
b57b7e5a SH |
256 | static struct { |
257 | u32 msg_enable; | |
258 | } debug = { -1 }; | |
1da177e4 | 259 | |
07d3f51f FR |
260 | enum rtl_registers { |
261 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 262 | MAC4 = 4, |
07d3f51f FR |
263 | MAR0 = 8, /* Multicast filter. */ |
264 | CounterAddrLow = 0x10, | |
265 | CounterAddrHigh = 0x14, | |
266 | TxDescStartAddrLow = 0x20, | |
267 | TxDescStartAddrHigh = 0x24, | |
268 | TxHDescStartAddrLow = 0x28, | |
269 | TxHDescStartAddrHigh = 0x2c, | |
270 | FLASH = 0x30, | |
271 | ERSR = 0x36, | |
272 | ChipCmd = 0x37, | |
273 | TxPoll = 0x38, | |
274 | IntrMask = 0x3c, | |
275 | IntrStatus = 0x3e, | |
4f6b00e5 | 276 | |
07d3f51f | 277 | TxConfig = 0x40, |
4f6b00e5 HW |
278 | #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */ |
279 | #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */ | |
2b7b4318 | 280 | |
4f6b00e5 HW |
281 | RxConfig = 0x44, |
282 | #define RX128_INT_EN (1 << 15) /* 8111c and later */ | |
283 | #define RX_MULTI_EN (1 << 14) /* 8111c only */ | |
284 | #define RXCFG_FIFO_SHIFT 13 | |
285 | /* No threshold before first PCI xfer */ | |
286 | #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT) | |
287 | #define RXCFG_DMA_SHIFT 8 | |
288 | /* Unlimited maximum PCI burst. */ | |
289 | #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT) | |
2b7b4318 | 290 | |
07d3f51f FR |
291 | RxMissed = 0x4c, |
292 | Cfg9346 = 0x50, | |
293 | Config0 = 0x51, | |
294 | Config1 = 0x52, | |
295 | Config2 = 0x53, | |
296 | Config3 = 0x54, | |
297 | Config4 = 0x55, | |
298 | Config5 = 0x56, | |
299 | MultiIntr = 0x5c, | |
300 | PHYAR = 0x60, | |
07d3f51f FR |
301 | PHYstatus = 0x6c, |
302 | RxMaxSize = 0xda, | |
303 | CPlusCmd = 0xe0, | |
304 | IntrMitigate = 0xe2, | |
305 | RxDescAddrLow = 0xe4, | |
306 | RxDescAddrHigh = 0xe8, | |
f0298f81 | 307 | EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
308 | ||
309 | #define NoEarlyTx 0x3f /* Max value : no early transmit. */ | |
310 | ||
311 | MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ | |
312 | ||
313 | #define TxPacketMax (8064 >> 7) | |
314 | ||
07d3f51f FR |
315 | FuncEvent = 0xf0, |
316 | FuncEventMask = 0xf4, | |
317 | FuncPresetState = 0xf8, | |
318 | FuncForceEvent = 0xfc, | |
1da177e4 LT |
319 | }; |
320 | ||
f162a5d1 FR |
321 | enum rtl8110_registers { |
322 | TBICSR = 0x64, | |
323 | TBI_ANAR = 0x68, | |
324 | TBI_LPAR = 0x6a, | |
325 | }; | |
326 | ||
327 | enum rtl8168_8101_registers { | |
328 | CSIDR = 0x64, | |
329 | CSIAR = 0x68, | |
330 | #define CSIAR_FLAG 0x80000000 | |
331 | #define CSIAR_WRITE_CMD 0x80000000 | |
332 | #define CSIAR_BYTE_ENABLE 0x0f | |
333 | #define CSIAR_BYTE_ENABLE_SHIFT 12 | |
334 | #define CSIAR_ADDR_MASK 0x0fff | |
065c27c1 | 335 | PMCH = 0x6f, |
f162a5d1 FR |
336 | EPHYAR = 0x80, |
337 | #define EPHYAR_FLAG 0x80000000 | |
338 | #define EPHYAR_WRITE_CMD 0x80000000 | |
339 | #define EPHYAR_REG_MASK 0x1f | |
340 | #define EPHYAR_REG_SHIFT 16 | |
341 | #define EPHYAR_DATA_MASK 0xffff | |
5a5e4443 | 342 | DLLPR = 0xd0, |
4f6b00e5 | 343 | #define PFM_EN (1 << 6) |
f162a5d1 FR |
344 | DBG_REG = 0xd1, |
345 | #define FIX_NAK_1 (1 << 4) | |
346 | #define FIX_NAK_2 (1 << 3) | |
5a5e4443 HW |
347 | TWSI = 0xd2, |
348 | MCU = 0xd3, | |
4f6b00e5 | 349 | #define NOW_IS_OOB (1 << 7) |
5a5e4443 HW |
350 | #define EN_NDP (1 << 3) |
351 | #define EN_OOB_RESET (1 << 2) | |
daf9df6d | 352 | EFUSEAR = 0xdc, |
353 | #define EFUSEAR_FLAG 0x80000000 | |
354 | #define EFUSEAR_WRITE_CMD 0x80000000 | |
355 | #define EFUSEAR_READ_CMD 0x00000000 | |
356 | #define EFUSEAR_REG_MASK 0x03ff | |
357 | #define EFUSEAR_REG_SHIFT 8 | |
358 | #define EFUSEAR_DATA_MASK 0xff | |
f162a5d1 FR |
359 | }; |
360 | ||
c0e45c1c | 361 | enum rtl8168_registers { |
4f6b00e5 HW |
362 | LED_FREQ = 0x1a, |
363 | EEE_LED = 0x1b, | |
b646d900 | 364 | ERIDR = 0x70, |
365 | ERIAR = 0x74, | |
366 | #define ERIAR_FLAG 0x80000000 | |
367 | #define ERIAR_WRITE_CMD 0x80000000 | |
368 | #define ERIAR_READ_CMD 0x00000000 | |
369 | #define ERIAR_ADDR_BYTE_ALIGN 4 | |
b646d900 | 370 | #define ERIAR_TYPE_SHIFT 16 |
4f6b00e5 HW |
371 | #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT) |
372 | #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT) | |
373 | #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT) | |
374 | #define ERIAR_MASK_SHIFT 12 | |
375 | #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT) | |
376 | #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT) | |
377 | #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT) | |
c0e45c1c | 378 | EPHY_RXER_NUM = 0x7c, |
379 | OCPDR = 0xb0, /* OCP GPHY access */ | |
380 | #define OCPDR_WRITE_CMD 0x80000000 | |
381 | #define OCPDR_READ_CMD 0x00000000 | |
382 | #define OCPDR_REG_MASK 0x7f | |
383 | #define OCPDR_GPHY_REG_SHIFT 16 | |
384 | #define OCPDR_DATA_MASK 0xffff | |
385 | OCPAR = 0xb4, | |
386 | #define OCPAR_FLAG 0x80000000 | |
387 | #define OCPAR_GPHY_WRITE_CMD 0x8000f060 | |
388 | #define OCPAR_GPHY_READ_CMD 0x0000f060 | |
01dc7fec | 389 | RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
390 | MISC = 0xf0, /* 8168e only. */ | |
cecb5fd7 | 391 | #define TXPLA_RST (1 << 29) |
4f6b00e5 | 392 | #define PWM_EN (1 << 22) |
c0e45c1c | 393 | }; |
394 | ||
07d3f51f | 395 | enum rtl_register_content { |
1da177e4 | 396 | /* InterruptStatusBits */ |
07d3f51f FR |
397 | SYSErr = 0x8000, |
398 | PCSTimeout = 0x4000, | |
399 | SWInt = 0x0100, | |
400 | TxDescUnavail = 0x0080, | |
401 | RxFIFOOver = 0x0040, | |
402 | LinkChg = 0x0020, | |
403 | RxOverflow = 0x0010, | |
404 | TxErr = 0x0008, | |
405 | TxOK = 0x0004, | |
406 | RxErr = 0x0002, | |
407 | RxOK = 0x0001, | |
1da177e4 LT |
408 | |
409 | /* RxStatusDesc */ | |
e03f33af | 410 | RxBOVF = (1 << 24), |
9dccf611 FR |
411 | RxFOVF = (1 << 23), |
412 | RxRWT = (1 << 22), | |
413 | RxRES = (1 << 21), | |
414 | RxRUNT = (1 << 20), | |
415 | RxCRC = (1 << 19), | |
1da177e4 LT |
416 | |
417 | /* ChipCmdBits */ | |
4f6b00e5 | 418 | StopReq = 0x80, |
07d3f51f FR |
419 | CmdReset = 0x10, |
420 | CmdRxEnb = 0x08, | |
421 | CmdTxEnb = 0x04, | |
422 | RxBufEmpty = 0x01, | |
1da177e4 | 423 | |
275391a4 FR |
424 | /* TXPoll register p.5 */ |
425 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
426 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
427 | FSWInt = 0x01, /* Forced software interrupt */ | |
428 | ||
1da177e4 | 429 | /* Cfg9346Bits */ |
07d3f51f FR |
430 | Cfg9346_Lock = 0x00, |
431 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
432 | |
433 | /* rx_mode_bits */ | |
07d3f51f FR |
434 | AcceptErr = 0x20, |
435 | AcceptRunt = 0x10, | |
436 | AcceptBroadcast = 0x08, | |
437 | AcceptMulticast = 0x04, | |
438 | AcceptMyPhys = 0x02, | |
439 | AcceptAllPhys = 0x01, | |
1687b566 | 440 | #define RX_CONFIG_ACCEPT_MASK 0x3f |
1da177e4 | 441 | |
1da177e4 LT |
442 | /* TxConfigBits */ |
443 | TxInterFrameGapShift = 24, | |
444 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
445 | ||
5d06a99f | 446 | /* Config1 register p.24 */ |
f162a5d1 FR |
447 | LEDS1 = (1 << 7), |
448 | LEDS0 = (1 << 6), | |
fbac58fc | 449 | MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
f162a5d1 FR |
450 | Speed_down = (1 << 4), |
451 | MEMMAP = (1 << 3), | |
452 | IOMAP = (1 << 2), | |
453 | VPD = (1 << 1), | |
5d06a99f FR |
454 | PMEnable = (1 << 0), /* Power Management Enable */ |
455 | ||
6dccd16b FR |
456 | /* Config2 register p. 25 */ |
457 | PCI_Clock_66MHz = 0x01, | |
458 | PCI_Clock_33MHz = 0x00, | |
459 | ||
61a4dcc2 FR |
460 | /* Config3 register p.25 */ |
461 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
462 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
f162a5d1 | 463 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 464 | |
5d06a99f | 465 | /* Config5 register p.27 */ |
61a4dcc2 FR |
466 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
467 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
468 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
cecb5fd7 | 469 | Spi_en = (1 << 3), |
61a4dcc2 | 470 | LanWake = (1 << 1), /* LanWake enable/disable */ |
5d06a99f FR |
471 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
472 | ||
1da177e4 LT |
473 | /* TBICSR p.28 */ |
474 | TBIReset = 0x80000000, | |
475 | TBILoopback = 0x40000000, | |
476 | TBINwEnable = 0x20000000, | |
477 | TBINwRestart = 0x10000000, | |
478 | TBILinkOk = 0x02000000, | |
479 | TBINwComplete = 0x01000000, | |
480 | ||
481 | /* CPlusCmd p.31 */ | |
f162a5d1 FR |
482 | EnableBist = (1 << 15), // 8168 8101 |
483 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
484 | Normal_mode = (1 << 13), // unused | |
485 | Force_half_dup = (1 << 12), // 8168 8101 | |
486 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
487 | Force_txflow_en = (1 << 10), // 8168 8101 | |
488 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
489 | ASF = (1 << 8), // 8168 8101 | |
490 | PktCntrDisable = (1 << 7), // 8168 8101 | |
491 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
492 | RxVlan = (1 << 6), |
493 | RxChkSum = (1 << 5), | |
494 | PCIDAC = (1 << 4), | |
495 | PCIMulRW = (1 << 3), | |
0e485150 FR |
496 | INTT_0 = 0x0000, // 8168 |
497 | INTT_1 = 0x0001, // 8168 | |
498 | INTT_2 = 0x0002, // 8168 | |
499 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
500 | |
501 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
502 | TBI_Enable = 0x80, |
503 | TxFlowCtrl = 0x40, | |
504 | RxFlowCtrl = 0x20, | |
505 | _1000bpsF = 0x10, | |
506 | _100bps = 0x08, | |
507 | _10bps = 0x04, | |
508 | LinkStatus = 0x02, | |
509 | FullDup = 0x01, | |
1da177e4 | 510 | |
1da177e4 | 511 | /* _TBICSRBit */ |
07d3f51f | 512 | TBILinkOK = 0x02000000, |
d4a3a0fc SH |
513 | |
514 | /* DumpCounterCommand */ | |
07d3f51f | 515 | CounterDump = 0x8, |
1da177e4 LT |
516 | }; |
517 | ||
2b7b4318 FR |
518 | enum rtl_desc_bit { |
519 | /* First doubleword. */ | |
1da177e4 LT |
520 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
521 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
522 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
523 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
2b7b4318 FR |
524 | }; |
525 | ||
526 | /* Generic case. */ | |
527 | enum rtl_tx_desc_bit { | |
528 | /* First doubleword. */ | |
529 | TD_LSO = (1 << 27), /* Large Send Offload */ | |
530 | #define TD_MSS_MAX 0x07ffu /* MSS value */ | |
1da177e4 | 531 | |
2b7b4318 FR |
532 | /* Second doubleword. */ |
533 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
534 | }; | |
535 | ||
536 | /* 8169, 8168b and 810x except 8102e. */ | |
537 | enum rtl_tx_desc_bit_0 { | |
538 | /* First doubleword. */ | |
539 | #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */ | |
540 | TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */ | |
541 | TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */ | |
542 | TD0_IP_CS = (1 << 18), /* Calculate IP checksum */ | |
543 | }; | |
544 | ||
545 | /* 8102e, 8168c and beyond. */ | |
546 | enum rtl_tx_desc_bit_1 { | |
547 | /* Second doubleword. */ | |
548 | #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */ | |
549 | TD1_IP_CS = (1 << 29), /* Calculate IP checksum */ | |
550 | TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */ | |
551 | TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */ | |
552 | }; | |
1da177e4 | 553 | |
2b7b4318 FR |
554 | static const struct rtl_tx_desc_info { |
555 | struct { | |
556 | u32 udp; | |
557 | u32 tcp; | |
558 | } checksum; | |
559 | u16 mss_shift; | |
560 | u16 opts_offset; | |
561 | } tx_desc_info [] = { | |
562 | [RTL_TD_0] = { | |
563 | .checksum = { | |
564 | .udp = TD0_IP_CS | TD0_UDP_CS, | |
565 | .tcp = TD0_IP_CS | TD0_TCP_CS | |
566 | }, | |
567 | .mss_shift = TD0_MSS_SHIFT, | |
568 | .opts_offset = 0 | |
569 | }, | |
570 | [RTL_TD_1] = { | |
571 | .checksum = { | |
572 | .udp = TD1_IP_CS | TD1_UDP_CS, | |
573 | .tcp = TD1_IP_CS | TD1_TCP_CS | |
574 | }, | |
575 | .mss_shift = TD1_MSS_SHIFT, | |
576 | .opts_offset = 1 | |
577 | } | |
578 | }; | |
579 | ||
580 | enum rtl_rx_desc_bit { | |
1da177e4 LT |
581 | /* Rx private */ |
582 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
583 | PID0 = (1 << 17), /* Protocol ID bit 2/2 */ | |
584 | ||
585 | #define RxProtoUDP (PID1) | |
586 | #define RxProtoTCP (PID0) | |
587 | #define RxProtoIP (PID1 | PID0) | |
588 | #define RxProtoMask RxProtoIP | |
589 | ||
590 | IPFail = (1 << 16), /* IP checksum failed */ | |
591 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
592 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
593 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
594 | }; | |
595 | ||
596 | #define RsvdMask 0x3fffc000 | |
597 | ||
598 | struct TxDesc { | |
6cccd6e7 REB |
599 | __le32 opts1; |
600 | __le32 opts2; | |
601 | __le64 addr; | |
1da177e4 LT |
602 | }; |
603 | ||
604 | struct RxDesc { | |
6cccd6e7 REB |
605 | __le32 opts1; |
606 | __le32 opts2; | |
607 | __le64 addr; | |
1da177e4 LT |
608 | }; |
609 | ||
610 | struct ring_info { | |
611 | struct sk_buff *skb; | |
612 | u32 len; | |
613 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
614 | }; | |
615 | ||
f23e7fda | 616 | enum features { |
ccdffb9a FR |
617 | RTL_FEATURE_WOL = (1 << 0), |
618 | RTL_FEATURE_MSI = (1 << 1), | |
619 | RTL_FEATURE_GMII = (1 << 2), | |
f23e7fda FR |
620 | }; |
621 | ||
355423d0 IV |
622 | struct rtl8169_counters { |
623 | __le64 tx_packets; | |
624 | __le64 rx_packets; | |
625 | __le64 tx_errors; | |
626 | __le32 rx_errors; | |
627 | __le16 rx_missed; | |
628 | __le16 align_errors; | |
629 | __le32 tx_one_collision; | |
630 | __le32 tx_multi_collision; | |
631 | __le64 rx_unicast; | |
632 | __le64 rx_broadcast; | |
633 | __le32 rx_multicast; | |
634 | __le16 tx_aborted; | |
635 | __le16 tx_underun; | |
636 | }; | |
637 | ||
1da177e4 LT |
638 | struct rtl8169_private { |
639 | void __iomem *mmio_addr; /* memory map physical address */ | |
cecb5fd7 | 640 | struct pci_dev *pci_dev; |
c4028958 | 641 | struct net_device *dev; |
bea3348e | 642 | struct napi_struct napi; |
cecb5fd7 | 643 | spinlock_t lock; |
b57b7e5a | 644 | u32 msg_enable; |
2b7b4318 FR |
645 | u16 txd_version; |
646 | u16 mac_version; | |
1da177e4 LT |
647 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
648 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
649 | u32 dirty_rx; | |
650 | u32 dirty_tx; | |
651 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ | |
652 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
653 | dma_addr_t TxPhyAddr; | |
654 | dma_addr_t RxPhyAddr; | |
6f0333b8 | 655 | void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
1da177e4 | 656 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
1da177e4 LT |
657 | struct timer_list timer; |
658 | u16 cp_cmd; | |
0e485150 FR |
659 | u16 intr_event; |
660 | u16 napi_event; | |
1da177e4 | 661 | u16 intr_mask; |
c0e45c1c | 662 | |
663 | struct mdio_ops { | |
664 | void (*write)(void __iomem *, int, int); | |
665 | int (*read)(void __iomem *, int); | |
666 | } mdio_ops; | |
667 | ||
065c27c1 | 668 | struct pll_power_ops { |
669 | void (*down)(struct rtl8169_private *); | |
670 | void (*up)(struct rtl8169_private *); | |
671 | } pll_power_ops; | |
672 | ||
54405cde | 673 | int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
ccdffb9a | 674 | int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
4da19633 | 675 | void (*phy_reset_enable)(struct rtl8169_private *tp); |
07ce4064 | 676 | void (*hw_start)(struct net_device *); |
4da19633 | 677 | unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
1da177e4 | 678 | unsigned int (*link_ok)(void __iomem *); |
8b4ab28d | 679 | int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
c4028958 | 680 | struct delayed_work task; |
f23e7fda | 681 | unsigned features; |
ccdffb9a FR |
682 | |
683 | struct mii_if_info mii; | |
355423d0 | 684 | struct rtl8169_counters counters; |
e1759441 | 685 | u32 saved_wolopts; |
e03f33af | 686 | u32 opts1_mask; |
f1e02ed1 | 687 | |
b6ffd97f FR |
688 | struct rtl_fw { |
689 | const struct firmware *fw; | |
1c361efb FR |
690 | |
691 | #define RTL_VER_SIZE 32 | |
692 | ||
693 | char version[RTL_VER_SIZE]; | |
694 | ||
695 | struct rtl_fw_phy_action { | |
696 | __le32 *code; | |
697 | size_t size; | |
698 | } phy_action; | |
b6ffd97f | 699 | } *rtl_fw; |
497888cf | 700 | #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN) |
1da177e4 LT |
701 | }; |
702 | ||
979b6c13 | 703 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 704 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 705 | module_param(use_dac, int, 0); |
4300e8c7 | 706 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
b57b7e5a SH |
707 | module_param_named(debug, debug.msg_enable, int, 0); |
708 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
709 | MODULE_LICENSE("GPL"); |
710 | MODULE_VERSION(RTL8169_VERSION); | |
bca03d5f | 711 | MODULE_FIRMWARE(FIRMWARE_8168D_1); |
712 | MODULE_FIRMWARE(FIRMWARE_8168D_2); | |
01dc7fec | 713 | MODULE_FIRMWARE(FIRMWARE_8168E_1); |
714 | MODULE_FIRMWARE(FIRMWARE_8168E_2); | |
bbb8af75 | 715 | MODULE_FIRMWARE(FIRMWARE_8168E_3); |
5a5e4443 | 716 | MODULE_FIRMWARE(FIRMWARE_8105E_1); |
1da177e4 LT |
717 | |
718 | static int rtl8169_open(struct net_device *dev); | |
61357325 SH |
719 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
720 | struct net_device *dev); | |
7d12e780 | 721 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
1da177e4 | 722 | static int rtl8169_init_ring(struct net_device *dev); |
07ce4064 | 723 | static void rtl_hw_start(struct net_device *dev); |
1da177e4 | 724 | static int rtl8169_close(struct net_device *dev); |
07ce4064 | 725 | static void rtl_set_rx_mode(struct net_device *dev); |
1da177e4 | 726 | static void rtl8169_tx_timeout(struct net_device *dev); |
4dcb7d33 | 727 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
1da177e4 | 728 | static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
bea3348e | 729 | void __iomem *, u32 budget); |
4dcb7d33 | 730 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
1da177e4 | 731 | static void rtl8169_down(struct net_device *dev); |
99f252b0 | 732 | static void rtl8169_rx_clear(struct rtl8169_private *tp); |
bea3348e | 733 | static int rtl8169_poll(struct napi_struct *napi, int budget); |
1da177e4 | 734 | |
b646d900 | 735 | static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
736 | { | |
737 | void __iomem *ioaddr = tp->mmio_addr; | |
738 | int i; | |
739 | ||
740 | RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
741 | for (i = 0; i < 20; i++) { | |
742 | udelay(100); | |
743 | if (RTL_R32(OCPAR) & OCPAR_FLAG) | |
744 | break; | |
745 | } | |
746 | return RTL_R32(OCPDR); | |
747 | } | |
748 | ||
749 | static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) | |
750 | { | |
751 | void __iomem *ioaddr = tp->mmio_addr; | |
752 | int i; | |
753 | ||
754 | RTL_W32(OCPDR, data); | |
755 | RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
756 | for (i = 0; i < 20; i++) { | |
757 | udelay(100); | |
758 | if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0) | |
759 | break; | |
760 | } | |
761 | } | |
762 | ||
fac5b3ca | 763 | static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
b646d900 | 764 | { |
fac5b3ca | 765 | void __iomem *ioaddr = tp->mmio_addr; |
b646d900 | 766 | int i; |
767 | ||
768 | RTL_W8(ERIDR, cmd); | |
769 | RTL_W32(ERIAR, 0x800010e8); | |
770 | msleep(2); | |
771 | for (i = 0; i < 5; i++) { | |
772 | udelay(100); | |
1e4e82ba | 773 | if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) |
b646d900 | 774 | break; |
775 | } | |
776 | ||
fac5b3ca | 777 | ocp_write(tp, 0x1, 0x30, 0x00000001); |
b646d900 | 778 | } |
779 | ||
780 | #define OOB_CMD_RESET 0x00 | |
781 | #define OOB_CMD_DRIVER_START 0x05 | |
782 | #define OOB_CMD_DRIVER_STOP 0x06 | |
783 | ||
cecb5fd7 FR |
784 | static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp) |
785 | { | |
786 | return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; | |
787 | } | |
788 | ||
b646d900 | 789 | static void rtl8168_driver_start(struct rtl8169_private *tp) |
790 | { | |
cecb5fd7 | 791 | u16 reg; |
b646d900 | 792 | int i; |
793 | ||
794 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); | |
795 | ||
cecb5fd7 | 796 | reg = rtl8168_get_ocp_reg(tp); |
4804b3b3 | 797 | |
b646d900 | 798 | for (i = 0; i < 10; i++) { |
799 | msleep(10); | |
4804b3b3 | 800 | if (ocp_read(tp, 0x0f, reg) & 0x00000800) |
b646d900 | 801 | break; |
802 | } | |
803 | } | |
804 | ||
805 | static void rtl8168_driver_stop(struct rtl8169_private *tp) | |
806 | { | |
cecb5fd7 | 807 | u16 reg; |
b646d900 | 808 | int i; |
809 | ||
810 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); | |
811 | ||
cecb5fd7 | 812 | reg = rtl8168_get_ocp_reg(tp); |
4804b3b3 | 813 | |
b646d900 | 814 | for (i = 0; i < 10; i++) { |
815 | msleep(10); | |
4804b3b3 | 816 | if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0) |
b646d900 | 817 | break; |
818 | } | |
819 | } | |
820 | ||
4804b3b3 | 821 | static int r8168dp_check_dash(struct rtl8169_private *tp) |
822 | { | |
cecb5fd7 | 823 | u16 reg = rtl8168_get_ocp_reg(tp); |
4804b3b3 | 824 | |
cecb5fd7 | 825 | return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0; |
4804b3b3 | 826 | } |
b646d900 | 827 | |
4da19633 | 828 | static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
1da177e4 LT |
829 | { |
830 | int i; | |
831 | ||
a6baf3af | 832 | RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 833 | |
2371408c | 834 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
835 | /* |
836 | * Check if the RTL8169 has completed writing to the specified | |
837 | * MII register. | |
838 | */ | |
5b0384f4 | 839 | if (!(RTL_R32(PHYAR) & 0x80000000)) |
1da177e4 | 840 | break; |
2371408c | 841 | udelay(25); |
1da177e4 | 842 | } |
024a07ba | 843 | /* |
81a95f04 TT |
844 | * According to hardware specs a 20us delay is required after write |
845 | * complete indication, but before sending next command. | |
024a07ba | 846 | */ |
81a95f04 | 847 | udelay(20); |
1da177e4 LT |
848 | } |
849 | ||
4da19633 | 850 | static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr) |
1da177e4 LT |
851 | { |
852 | int i, value = -1; | |
853 | ||
a6baf3af | 854 | RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
1da177e4 | 855 | |
2371408c | 856 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
857 | /* |
858 | * Check if the RTL8169 has completed retrieving data from | |
859 | * the specified MII register. | |
860 | */ | |
1da177e4 | 861 | if (RTL_R32(PHYAR) & 0x80000000) { |
a6baf3af | 862 | value = RTL_R32(PHYAR) & 0xffff; |
1da177e4 LT |
863 | break; |
864 | } | |
2371408c | 865 | udelay(25); |
1da177e4 | 866 | } |
81a95f04 TT |
867 | /* |
868 | * According to hardware specs a 20us delay is required after read | |
869 | * complete indication, but before sending next command. | |
870 | */ | |
871 | udelay(20); | |
872 | ||
1da177e4 LT |
873 | return value; |
874 | } | |
875 | ||
c0e45c1c | 876 | static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data) |
877 | { | |
878 | int i; | |
879 | ||
880 | RTL_W32(OCPDR, data | | |
881 | ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); | |
882 | RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); | |
883 | RTL_W32(EPHY_RXER_NUM, 0); | |
884 | ||
885 | for (i = 0; i < 100; i++) { | |
886 | mdelay(1); | |
887 | if (!(RTL_R32(OCPAR) & OCPAR_FLAG)) | |
888 | break; | |
889 | } | |
890 | } | |
891 | ||
892 | static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value) | |
893 | { | |
894 | r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD | | |
895 | (value & OCPDR_DATA_MASK)); | |
896 | } | |
897 | ||
898 | static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr) | |
899 | { | |
900 | int i; | |
901 | ||
902 | r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD); | |
903 | ||
904 | mdelay(1); | |
905 | RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); | |
906 | RTL_W32(EPHY_RXER_NUM, 0); | |
907 | ||
908 | for (i = 0; i < 100; i++) { | |
909 | mdelay(1); | |
910 | if (RTL_R32(OCPAR) & OCPAR_FLAG) | |
911 | break; | |
912 | } | |
913 | ||
914 | return RTL_R32(OCPDR) & OCPDR_DATA_MASK; | |
915 | } | |
916 | ||
e6de30d6 | 917 | #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
918 | ||
919 | static void r8168dp_2_mdio_start(void __iomem *ioaddr) | |
920 | { | |
921 | RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); | |
922 | } | |
923 | ||
924 | static void r8168dp_2_mdio_stop(void __iomem *ioaddr) | |
925 | { | |
926 | RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); | |
927 | } | |
928 | ||
929 | static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value) | |
930 | { | |
931 | r8168dp_2_mdio_start(ioaddr); | |
932 | ||
933 | r8169_mdio_write(ioaddr, reg_addr, value); | |
934 | ||
935 | r8168dp_2_mdio_stop(ioaddr); | |
936 | } | |
937 | ||
938 | static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr) | |
939 | { | |
940 | int value; | |
941 | ||
942 | r8168dp_2_mdio_start(ioaddr); | |
943 | ||
944 | value = r8169_mdio_read(ioaddr, reg_addr); | |
945 | ||
946 | r8168dp_2_mdio_stop(ioaddr); | |
947 | ||
948 | return value; | |
949 | } | |
950 | ||
4da19633 | 951 | static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
dacf8154 | 952 | { |
c0e45c1c | 953 | tp->mdio_ops.write(tp->mmio_addr, location, val); |
dacf8154 FR |
954 | } |
955 | ||
4da19633 | 956 | static int rtl_readphy(struct rtl8169_private *tp, int location) |
957 | { | |
c0e45c1c | 958 | return tp->mdio_ops.read(tp->mmio_addr, location); |
4da19633 | 959 | } |
960 | ||
961 | static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) | |
962 | { | |
963 | rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); | |
964 | } | |
965 | ||
966 | static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) | |
daf9df6d | 967 | { |
968 | int val; | |
969 | ||
4da19633 | 970 | val = rtl_readphy(tp, reg_addr); |
971 | rtl_writephy(tp, reg_addr, (val | p) & ~m); | |
daf9df6d | 972 | } |
973 | ||
ccdffb9a FR |
974 | static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
975 | int val) | |
976 | { | |
977 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 978 | |
4da19633 | 979 | rtl_writephy(tp, location, val); |
ccdffb9a FR |
980 | } |
981 | ||
982 | static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) | |
983 | { | |
984 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 985 | |
4da19633 | 986 | return rtl_readphy(tp, location); |
ccdffb9a FR |
987 | } |
988 | ||
dacf8154 FR |
989 | static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
990 | { | |
991 | unsigned int i; | |
992 | ||
993 | RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | | |
994 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
995 | ||
996 | for (i = 0; i < 100; i++) { | |
997 | if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) | |
998 | break; | |
999 | udelay(10); | |
1000 | } | |
1001 | } | |
1002 | ||
1003 | static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) | |
1004 | { | |
1005 | u16 value = 0xffff; | |
1006 | unsigned int i; | |
1007 | ||
1008 | RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
1009 | ||
1010 | for (i = 0; i < 100; i++) { | |
1011 | if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { | |
1012 | value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; | |
1013 | break; | |
1014 | } | |
1015 | udelay(10); | |
1016 | } | |
1017 | ||
1018 | return value; | |
1019 | } | |
1020 | ||
1021 | static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) | |
1022 | { | |
1023 | unsigned int i; | |
1024 | ||
1025 | RTL_W32(CSIDR, value); | |
1026 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
1027 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
1028 | ||
1029 | for (i = 0; i < 100; i++) { | |
1030 | if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) | |
1031 | break; | |
1032 | udelay(10); | |
1033 | } | |
1034 | } | |
1035 | ||
1036 | static u32 rtl_csi_read(void __iomem *ioaddr, int addr) | |
1037 | { | |
1038 | u32 value = ~0x00; | |
1039 | unsigned int i; | |
1040 | ||
1041 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | | |
1042 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
1043 | ||
1044 | for (i = 0; i < 100; i++) { | |
1045 | if (RTL_R32(CSIAR) & CSIAR_FLAG) { | |
1046 | value = RTL_R32(CSIDR); | |
1047 | break; | |
1048 | } | |
1049 | udelay(10); | |
1050 | } | |
1051 | ||
1052 | return value; | |
1053 | } | |
1054 | ||
133ac40a HW |
1055 | static |
1056 | void rtl_eri_write(void __iomem *ioaddr, int addr, u32 mask, u32 val, int type) | |
1057 | { | |
1058 | unsigned int i; | |
1059 | ||
1060 | BUG_ON((addr & 3) || (mask == 0)); | |
1061 | RTL_W32(ERIDR, val); | |
1062 | RTL_W32(ERIAR, ERIAR_WRITE_CMD | type | mask | addr); | |
1063 | ||
1064 | for (i = 0; i < 100; i++) { | |
1065 | if (!(RTL_R32(ERIAR) & ERIAR_FLAG)) | |
1066 | break; | |
1067 | udelay(100); | |
1068 | } | |
1069 | } | |
1070 | ||
1071 | static u32 rtl_eri_read(void __iomem *ioaddr, int addr, int type) | |
1072 | { | |
1073 | u32 value = ~0x00; | |
1074 | unsigned int i; | |
1075 | ||
1076 | RTL_W32(ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr); | |
1077 | ||
1078 | for (i = 0; i < 100; i++) { | |
1079 | if (RTL_R32(ERIAR) & ERIAR_FLAG) { | |
1080 | value = RTL_R32(ERIDR); | |
1081 | break; | |
1082 | } | |
1083 | udelay(100); | |
1084 | } | |
1085 | ||
1086 | return value; | |
1087 | } | |
1088 | ||
1089 | static void | |
1090 | rtl_w1w0_eri(void __iomem *ioaddr, int addr, u32 mask, u32 p, u32 m, int type) | |
1091 | { | |
1092 | u32 val; | |
1093 | ||
1094 | val = rtl_eri_read(ioaddr, addr, type); | |
1095 | rtl_eri_write(ioaddr, addr, mask, (val & ~m) | p, type); | |
1096 | } | |
1097 | ||
c28aa385 | 1098 | struct exgmac_reg { |
1099 | u16 addr; | |
1100 | u16 mask; | |
1101 | u32 val; | |
1102 | }; | |
1103 | ||
1104 | static void rtl_write_exgmac_batch(void __iomem *ioaddr, | |
1105 | const struct exgmac_reg *r, int len) | |
1106 | { | |
1107 | while (len-- > 0) { | |
1108 | rtl_eri_write(ioaddr, r->addr, r->mask, r->val, ERIAR_EXGMAC); | |
1109 | r++; | |
1110 | } | |
1111 | } | |
1112 | ||
daf9df6d | 1113 | static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) |
1114 | { | |
1115 | u8 value = 0xff; | |
1116 | unsigned int i; | |
1117 | ||
1118 | RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); | |
1119 | ||
1120 | for (i = 0; i < 300; i++) { | |
1121 | if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) { | |
1122 | value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK; | |
1123 | break; | |
1124 | } | |
1125 | udelay(100); | |
1126 | } | |
1127 | ||
1128 | return value; | |
1129 | } | |
1130 | ||
1da177e4 LT |
1131 | static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
1132 | { | |
1133 | RTL_W16(IntrMask, 0x0000); | |
1134 | ||
1135 | RTL_W16(IntrStatus, 0xffff); | |
1136 | } | |
1137 | ||
4da19633 | 1138 | static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1139 | { |
4da19633 | 1140 | void __iomem *ioaddr = tp->mmio_addr; |
1141 | ||
1da177e4 LT |
1142 | return RTL_R32(TBICSR) & TBIReset; |
1143 | } | |
1144 | ||
4da19633 | 1145 | static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 1146 | { |
4da19633 | 1147 | return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
1148 | } |
1149 | ||
1150 | static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) | |
1151 | { | |
1152 | return RTL_R32(TBICSR) & TBILinkOk; | |
1153 | } | |
1154 | ||
1155 | static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) | |
1156 | { | |
1157 | return RTL_R8(PHYstatus) & LinkStatus; | |
1158 | } | |
1159 | ||
4da19633 | 1160 | static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
1da177e4 | 1161 | { |
4da19633 | 1162 | void __iomem *ioaddr = tp->mmio_addr; |
1163 | ||
1da177e4 LT |
1164 | RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
1165 | } | |
1166 | ||
4da19633 | 1167 | static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
1da177e4 LT |
1168 | { |
1169 | unsigned int val; | |
1170 | ||
4da19633 | 1171 | val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
1172 | rtl_writephy(tp, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
1173 | } |
1174 | ||
70090424 HW |
1175 | static void rtl_link_chg_patch(struct rtl8169_private *tp) |
1176 | { | |
1177 | void __iomem *ioaddr = tp->mmio_addr; | |
1178 | struct net_device *dev = tp->dev; | |
1179 | ||
1180 | if (!netif_running(dev)) | |
1181 | return; | |
1182 | ||
1183 | if (tp->mac_version == RTL_GIGA_MAC_VER_34) { | |
1184 | if (RTL_R8(PHYstatus) & _1000bpsF) { | |
1185 | rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, | |
1186 | 0x00000011, ERIAR_EXGMAC); | |
1187 | rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, | |
1188 | 0x00000005, ERIAR_EXGMAC); | |
1189 | } else if (RTL_R8(PHYstatus) & _100bps) { | |
1190 | rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, | |
1191 | 0x0000001f, ERIAR_EXGMAC); | |
1192 | rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, | |
1193 | 0x00000005, ERIAR_EXGMAC); | |
1194 | } else { | |
1195 | rtl_eri_write(ioaddr, 0x1bc, ERIAR_MASK_1111, | |
1196 | 0x0000001f, ERIAR_EXGMAC); | |
1197 | rtl_eri_write(ioaddr, 0x1dc, ERIAR_MASK_1111, | |
1198 | 0x0000003f, ERIAR_EXGMAC); | |
1199 | } | |
1200 | /* Reset packet filter */ | |
1201 | rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, | |
1202 | ERIAR_EXGMAC); | |
1203 | rtl_w1w0_eri(ioaddr, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, | |
1204 | ERIAR_EXGMAC); | |
1205 | } | |
1206 | } | |
1207 | ||
e4fbce74 | 1208 | static void __rtl8169_check_link_status(struct net_device *dev, |
cecb5fd7 FR |
1209 | struct rtl8169_private *tp, |
1210 | void __iomem *ioaddr, bool pm) | |
1da177e4 LT |
1211 | { |
1212 | unsigned long flags; | |
1213 | ||
1214 | spin_lock_irqsave(&tp->lock, flags); | |
1215 | if (tp->link_ok(ioaddr)) { | |
70090424 | 1216 | rtl_link_chg_patch(tp); |
e1759441 | 1217 | /* This is to cancel a scheduled suspend if there's one. */ |
e4fbce74 RW |
1218 | if (pm) |
1219 | pm_request_resume(&tp->pci_dev->dev); | |
1da177e4 | 1220 | netif_carrier_on(dev); |
1519e57f FR |
1221 | if (net_ratelimit()) |
1222 | netif_info(tp, ifup, dev, "link up\n"); | |
b57b7e5a | 1223 | } else { |
1da177e4 | 1224 | netif_carrier_off(dev); |
bf82c189 | 1225 | netif_info(tp, ifdown, dev, "link down\n"); |
e4fbce74 RW |
1226 | if (pm) |
1227 | pm_schedule_suspend(&tp->pci_dev->dev, 100); | |
b57b7e5a | 1228 | } |
1da177e4 LT |
1229 | spin_unlock_irqrestore(&tp->lock, flags); |
1230 | } | |
1231 | ||
e4fbce74 RW |
1232 | static void rtl8169_check_link_status(struct net_device *dev, |
1233 | struct rtl8169_private *tp, | |
1234 | void __iomem *ioaddr) | |
1235 | { | |
1236 | __rtl8169_check_link_status(dev, tp, ioaddr, false); | |
1237 | } | |
1238 | ||
e1759441 RW |
1239 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1240 | ||
1241 | static u32 __rtl8169_get_wol(struct rtl8169_private *tp) | |
61a4dcc2 | 1242 | { |
61a4dcc2 FR |
1243 | void __iomem *ioaddr = tp->mmio_addr; |
1244 | u8 options; | |
e1759441 | 1245 | u32 wolopts = 0; |
61a4dcc2 FR |
1246 | |
1247 | options = RTL_R8(Config1); | |
1248 | if (!(options & PMEnable)) | |
e1759441 | 1249 | return 0; |
61a4dcc2 FR |
1250 | |
1251 | options = RTL_R8(Config3); | |
1252 | if (options & LinkUp) | |
e1759441 | 1253 | wolopts |= WAKE_PHY; |
61a4dcc2 | 1254 | if (options & MagicPacket) |
e1759441 | 1255 | wolopts |= WAKE_MAGIC; |
61a4dcc2 FR |
1256 | |
1257 | options = RTL_R8(Config5); | |
1258 | if (options & UWF) | |
e1759441 | 1259 | wolopts |= WAKE_UCAST; |
61a4dcc2 | 1260 | if (options & BWF) |
e1759441 | 1261 | wolopts |= WAKE_BCAST; |
61a4dcc2 | 1262 | if (options & MWF) |
e1759441 | 1263 | wolopts |= WAKE_MCAST; |
61a4dcc2 | 1264 | |
e1759441 | 1265 | return wolopts; |
61a4dcc2 FR |
1266 | } |
1267 | ||
e1759441 | 1268 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
61a4dcc2 FR |
1269 | { |
1270 | struct rtl8169_private *tp = netdev_priv(dev); | |
e1759441 RW |
1271 | |
1272 | spin_lock_irq(&tp->lock); | |
1273 | ||
1274 | wol->supported = WAKE_ANY; | |
1275 | wol->wolopts = __rtl8169_get_wol(tp); | |
1276 | ||
1277 | spin_unlock_irq(&tp->lock); | |
1278 | } | |
1279 | ||
1280 | static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) | |
1281 | { | |
61a4dcc2 | 1282 | void __iomem *ioaddr = tp->mmio_addr; |
07d3f51f | 1283 | unsigned int i; |
350f7596 | 1284 | static const struct { |
61a4dcc2 FR |
1285 | u32 opt; |
1286 | u16 reg; | |
1287 | u8 mask; | |
1288 | } cfg[] = { | |
1289 | { WAKE_ANY, Config1, PMEnable }, | |
1290 | { WAKE_PHY, Config3, LinkUp }, | |
1291 | { WAKE_MAGIC, Config3, MagicPacket }, | |
1292 | { WAKE_UCAST, Config5, UWF }, | |
1293 | { WAKE_BCAST, Config5, BWF }, | |
1294 | { WAKE_MCAST, Config5, MWF }, | |
1295 | { WAKE_ANY, Config5, LanWake } | |
1296 | }; | |
1297 | ||
61a4dcc2 FR |
1298 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
1299 | ||
1300 | for (i = 0; i < ARRAY_SIZE(cfg); i++) { | |
1301 | u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; | |
e1759441 | 1302 | if (wolopts & cfg[i].opt) |
61a4dcc2 FR |
1303 | options |= cfg[i].mask; |
1304 | RTL_W8(cfg[i].reg, options); | |
1305 | } | |
1306 | ||
1307 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
e1759441 RW |
1308 | } |
1309 | ||
1310 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1311 | { | |
1312 | struct rtl8169_private *tp = netdev_priv(dev); | |
1313 | ||
1314 | spin_lock_irq(&tp->lock); | |
61a4dcc2 | 1315 | |
f23e7fda FR |
1316 | if (wol->wolopts) |
1317 | tp->features |= RTL_FEATURE_WOL; | |
1318 | else | |
1319 | tp->features &= ~RTL_FEATURE_WOL; | |
e1759441 | 1320 | __rtl8169_set_wol(tp, wol->wolopts); |
61a4dcc2 FR |
1321 | spin_unlock_irq(&tp->lock); |
1322 | ||
ea80907f | 1323 | device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
1324 | ||
61a4dcc2 FR |
1325 | return 0; |
1326 | } | |
1327 | ||
31bd204f FR |
1328 | static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp) |
1329 | { | |
85bffe6c | 1330 | return rtl_chip_infos[tp->mac_version].fw_name; |
31bd204f FR |
1331 | } |
1332 | ||
1da177e4 LT |
1333 | static void rtl8169_get_drvinfo(struct net_device *dev, |
1334 | struct ethtool_drvinfo *info) | |
1335 | { | |
1336 | struct rtl8169_private *tp = netdev_priv(dev); | |
b6ffd97f | 1337 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
1da177e4 LT |
1338 | |
1339 | strcpy(info->driver, MODULENAME); | |
1340 | strcpy(info->version, RTL8169_VERSION); | |
1341 | strcpy(info->bus_info, pci_name(tp->pci_dev)); | |
1c361efb FR |
1342 | BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version)); |
1343 | strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" : | |
1344 | rtl_fw->version); | |
1da177e4 LT |
1345 | } |
1346 | ||
1347 | static int rtl8169_get_regs_len(struct net_device *dev) | |
1348 | { | |
1349 | return R8169_REGS_SIZE; | |
1350 | } | |
1351 | ||
1352 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
54405cde | 1353 | u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
1da177e4 LT |
1354 | { |
1355 | struct rtl8169_private *tp = netdev_priv(dev); | |
1356 | void __iomem *ioaddr = tp->mmio_addr; | |
1357 | int ret = 0; | |
1358 | u32 reg; | |
1359 | ||
1360 | reg = RTL_R32(TBICSR); | |
1361 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && | |
1362 | (duplex == DUPLEX_FULL)) { | |
1363 | RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); | |
1364 | } else if (autoneg == AUTONEG_ENABLE) | |
1365 | RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); | |
1366 | else { | |
bf82c189 JP |
1367 | netif_warn(tp, link, dev, |
1368 | "incorrect speed setting refused in TBI mode\n"); | |
1da177e4 LT |
1369 | ret = -EOPNOTSUPP; |
1370 | } | |
1371 | ||
1372 | return ret; | |
1373 | } | |
1374 | ||
1375 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
54405cde | 1376 | u8 autoneg, u16 speed, u8 duplex, u32 adv) |
1da177e4 LT |
1377 | { |
1378 | struct rtl8169_private *tp = netdev_priv(dev); | |
3577aa1b | 1379 | int giga_ctrl, bmcr; |
54405cde | 1380 | int rc = -EINVAL; |
1da177e4 | 1381 | |
716b50a3 | 1382 | rtl_writephy(tp, 0x1f, 0x0000); |
1da177e4 LT |
1383 | |
1384 | if (autoneg == AUTONEG_ENABLE) { | |
3577aa1b | 1385 | int auto_nego; |
1386 | ||
4da19633 | 1387 | auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
54405cde ON |
1388 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
1389 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
1390 | ||
1391 | if (adv & ADVERTISED_10baseT_Half) | |
1392 | auto_nego |= ADVERTISE_10HALF; | |
1393 | if (adv & ADVERTISED_10baseT_Full) | |
1394 | auto_nego |= ADVERTISE_10FULL; | |
1395 | if (adv & ADVERTISED_100baseT_Half) | |
1396 | auto_nego |= ADVERTISE_100HALF; | |
1397 | if (adv & ADVERTISED_100baseT_Full) | |
1398 | auto_nego |= ADVERTISE_100FULL; | |
1399 | ||
3577aa1b | 1400 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1da177e4 | 1401 | |
4da19633 | 1402 | giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
3577aa1b | 1403 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
bcf0bf90 | 1404 | |
3577aa1b | 1405 | /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
826e6cbd | 1406 | if (tp->mii.supports_gmii) { |
54405cde ON |
1407 | if (adv & ADVERTISED_1000baseT_Half) |
1408 | giga_ctrl |= ADVERTISE_1000HALF; | |
1409 | if (adv & ADVERTISED_1000baseT_Full) | |
1410 | giga_ctrl |= ADVERTISE_1000FULL; | |
1411 | } else if (adv & (ADVERTISED_1000baseT_Half | | |
1412 | ADVERTISED_1000baseT_Full)) { | |
bf82c189 JP |
1413 | netif_info(tp, link, dev, |
1414 | "PHY does not support 1000Mbps\n"); | |
54405cde | 1415 | goto out; |
bcf0bf90 | 1416 | } |
1da177e4 | 1417 | |
3577aa1b | 1418 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
1419 | ||
4da19633 | 1420 | rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
1421 | rtl_writephy(tp, MII_CTRL1000, giga_ctrl); | |
3577aa1b | 1422 | } else { |
1423 | giga_ctrl = 0; | |
1424 | ||
1425 | if (speed == SPEED_10) | |
1426 | bmcr = 0; | |
1427 | else if (speed == SPEED_100) | |
1428 | bmcr = BMCR_SPEED100; | |
1429 | else | |
54405cde | 1430 | goto out; |
3577aa1b | 1431 | |
1432 | if (duplex == DUPLEX_FULL) | |
1433 | bmcr |= BMCR_FULLDPLX; | |
2584fbc3 RS |
1434 | } |
1435 | ||
4da19633 | 1436 | rtl_writephy(tp, MII_BMCR, bmcr); |
3577aa1b | 1437 | |
cecb5fd7 FR |
1438 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
1439 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
3577aa1b | 1440 | if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { |
4da19633 | 1441 | rtl_writephy(tp, 0x17, 0x2138); |
1442 | rtl_writephy(tp, 0x0e, 0x0260); | |
3577aa1b | 1443 | } else { |
4da19633 | 1444 | rtl_writephy(tp, 0x17, 0x2108); |
1445 | rtl_writephy(tp, 0x0e, 0x0000); | |
3577aa1b | 1446 | } |
1447 | } | |
1448 | ||
54405cde ON |
1449 | rc = 0; |
1450 | out: | |
1451 | return rc; | |
1da177e4 LT |
1452 | } |
1453 | ||
1454 | static int rtl8169_set_speed(struct net_device *dev, | |
54405cde | 1455 | u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
1da177e4 LT |
1456 | { |
1457 | struct rtl8169_private *tp = netdev_priv(dev); | |
1458 | int ret; | |
1459 | ||
54405cde | 1460 | ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
4876cc1e FR |
1461 | if (ret < 0) |
1462 | goto out; | |
1da177e4 | 1463 | |
4876cc1e FR |
1464 | if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) && |
1465 | (advertising & ADVERTISED_1000baseT_Full)) { | |
1da177e4 | 1466 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
4876cc1e FR |
1467 | } |
1468 | out: | |
1da177e4 LT |
1469 | return ret; |
1470 | } | |
1471 | ||
1472 | static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1473 | { | |
1474 | struct rtl8169_private *tp = netdev_priv(dev); | |
1475 | unsigned long flags; | |
1476 | int ret; | |
1477 | ||
4876cc1e FR |
1478 | del_timer_sync(&tp->timer); |
1479 | ||
1da177e4 | 1480 | spin_lock_irqsave(&tp->lock, flags); |
cecb5fd7 | 1481 | ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd), |
25db0338 | 1482 | cmd->duplex, cmd->advertising); |
1da177e4 | 1483 | spin_unlock_irqrestore(&tp->lock, flags); |
5b0384f4 | 1484 | |
1da177e4 LT |
1485 | return ret; |
1486 | } | |
1487 | ||
350fb32a | 1488 | static u32 rtl8169_fix_features(struct net_device *dev, u32 features) |
1da177e4 | 1489 | { |
2b7b4318 | 1490 | if (dev->mtu > TD_MSS_MAX) |
350fb32a | 1491 | features &= ~NETIF_F_ALL_TSO; |
1da177e4 | 1492 | |
350fb32a | 1493 | return features; |
1da177e4 LT |
1494 | } |
1495 | ||
350fb32a | 1496 | static int rtl8169_set_features(struct net_device *dev, u32 features) |
1da177e4 LT |
1497 | { |
1498 | struct rtl8169_private *tp = netdev_priv(dev); | |
1499 | void __iomem *ioaddr = tp->mmio_addr; | |
1500 | unsigned long flags; | |
1501 | ||
1502 | spin_lock_irqsave(&tp->lock, flags); | |
1503 | ||
350fb32a | 1504 | if (features & NETIF_F_RXCSUM) |
1da177e4 LT |
1505 | tp->cp_cmd |= RxChkSum; |
1506 | else | |
1507 | tp->cp_cmd &= ~RxChkSum; | |
1508 | ||
350fb32a MM |
1509 | if (dev->features & NETIF_F_HW_VLAN_RX) |
1510 | tp->cp_cmd |= RxVlan; | |
1511 | else | |
1512 | tp->cp_cmd &= ~RxVlan; | |
1513 | ||
1da177e4 LT |
1514 | RTL_W16(CPlusCmd, tp->cp_cmd); |
1515 | RTL_R16(CPlusCmd); | |
1516 | ||
1517 | spin_unlock_irqrestore(&tp->lock, flags); | |
1518 | ||
1519 | return 0; | |
1520 | } | |
1521 | ||
1da177e4 LT |
1522 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
1523 | struct sk_buff *skb) | |
1524 | { | |
eab6d18d | 1525 | return (vlan_tx_tag_present(skb)) ? |
1da177e4 LT |
1526 | TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
1527 | } | |
1528 | ||
7a8fc77b | 1529 | static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
1da177e4 LT |
1530 | { |
1531 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1da177e4 | 1532 | |
7a8fc77b FR |
1533 | if (opts2 & RxVlanTag) |
1534 | __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); | |
2edae08e | 1535 | |
1da177e4 | 1536 | desc->opts2 = 0; |
1da177e4 LT |
1537 | } |
1538 | ||
ccdffb9a | 1539 | static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1540 | { |
1541 | struct rtl8169_private *tp = netdev_priv(dev); | |
1542 | void __iomem *ioaddr = tp->mmio_addr; | |
1543 | u32 status; | |
1544 | ||
1545 | cmd->supported = | |
1546 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; | |
1547 | cmd->port = PORT_FIBRE; | |
1548 | cmd->transceiver = XCVR_INTERNAL; | |
1549 | ||
1550 | status = RTL_R32(TBICSR); | |
1551 | cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; | |
1552 | cmd->autoneg = !!(status & TBINwEnable); | |
1553 | ||
70739497 | 1554 | ethtool_cmd_speed_set(cmd, SPEED_1000); |
1da177e4 | 1555 | cmd->duplex = DUPLEX_FULL; /* Always set */ |
ccdffb9a FR |
1556 | |
1557 | return 0; | |
1da177e4 LT |
1558 | } |
1559 | ||
ccdffb9a | 1560 | static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1561 | { |
1562 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a FR |
1563 | |
1564 | return mii_ethtool_gset(&tp->mii, cmd); | |
1da177e4 LT |
1565 | } |
1566 | ||
1567 | static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1568 | { | |
1569 | struct rtl8169_private *tp = netdev_priv(dev); | |
1570 | unsigned long flags; | |
ccdffb9a | 1571 | int rc; |
1da177e4 LT |
1572 | |
1573 | spin_lock_irqsave(&tp->lock, flags); | |
1574 | ||
ccdffb9a | 1575 | rc = tp->get_settings(dev, cmd); |
1da177e4 LT |
1576 | |
1577 | spin_unlock_irqrestore(&tp->lock, flags); | |
ccdffb9a | 1578 | return rc; |
1da177e4 LT |
1579 | } |
1580 | ||
1581 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1582 | void *p) | |
1583 | { | |
5b0384f4 FR |
1584 | struct rtl8169_private *tp = netdev_priv(dev); |
1585 | unsigned long flags; | |
1da177e4 | 1586 | |
5b0384f4 FR |
1587 | if (regs->len > R8169_REGS_SIZE) |
1588 | regs->len = R8169_REGS_SIZE; | |
1da177e4 | 1589 | |
5b0384f4 FR |
1590 | spin_lock_irqsave(&tp->lock, flags); |
1591 | memcpy_fromio(p, tp->mmio_addr, regs->len); | |
1592 | spin_unlock_irqrestore(&tp->lock, flags); | |
1da177e4 LT |
1593 | } |
1594 | ||
b57b7e5a SH |
1595 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
1596 | { | |
1597 | struct rtl8169_private *tp = netdev_priv(dev); | |
1598 | ||
1599 | return tp->msg_enable; | |
1600 | } | |
1601 | ||
1602 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
1603 | { | |
1604 | struct rtl8169_private *tp = netdev_priv(dev); | |
1605 | ||
1606 | tp->msg_enable = value; | |
1607 | } | |
1608 | ||
d4a3a0fc SH |
1609 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
1610 | "tx_packets", | |
1611 | "rx_packets", | |
1612 | "tx_errors", | |
1613 | "rx_errors", | |
1614 | "rx_missed", | |
1615 | "align_errors", | |
1616 | "tx_single_collisions", | |
1617 | "tx_multi_collisions", | |
1618 | "unicast", | |
1619 | "broadcast", | |
1620 | "multicast", | |
1621 | "tx_aborted", | |
1622 | "tx_underrun", | |
1623 | }; | |
1624 | ||
b9f2c044 | 1625 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 1626 | { |
b9f2c044 JG |
1627 | switch (sset) { |
1628 | case ETH_SS_STATS: | |
1629 | return ARRAY_SIZE(rtl8169_gstrings); | |
1630 | default: | |
1631 | return -EOPNOTSUPP; | |
1632 | } | |
d4a3a0fc SH |
1633 | } |
1634 | ||
355423d0 | 1635 | static void rtl8169_update_counters(struct net_device *dev) |
d4a3a0fc SH |
1636 | { |
1637 | struct rtl8169_private *tp = netdev_priv(dev); | |
1638 | void __iomem *ioaddr = tp->mmio_addr; | |
cecb5fd7 | 1639 | struct device *d = &tp->pci_dev->dev; |
d4a3a0fc SH |
1640 | struct rtl8169_counters *counters; |
1641 | dma_addr_t paddr; | |
1642 | u32 cmd; | |
355423d0 | 1643 | int wait = 1000; |
d4a3a0fc | 1644 | |
355423d0 IV |
1645 | /* |
1646 | * Some chips are unable to dump tally counters when the receiver | |
1647 | * is disabled. | |
1648 | */ | |
1649 | if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) | |
1650 | return; | |
d4a3a0fc | 1651 | |
48addcc9 | 1652 | counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); |
d4a3a0fc SH |
1653 | if (!counters) |
1654 | return; | |
1655 | ||
1656 | RTL_W32(CounterAddrHigh, (u64)paddr >> 32); | |
284901a9 | 1657 | cmd = (u64)paddr & DMA_BIT_MASK(32); |
d4a3a0fc SH |
1658 | RTL_W32(CounterAddrLow, cmd); |
1659 | RTL_W32(CounterAddrLow, cmd | CounterDump); | |
1660 | ||
355423d0 IV |
1661 | while (wait--) { |
1662 | if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { | |
355423d0 | 1663 | memcpy(&tp->counters, counters, sizeof(*counters)); |
d4a3a0fc | 1664 | break; |
355423d0 IV |
1665 | } |
1666 | udelay(10); | |
d4a3a0fc SH |
1667 | } |
1668 | ||
1669 | RTL_W32(CounterAddrLow, 0); | |
1670 | RTL_W32(CounterAddrHigh, 0); | |
1671 | ||
48addcc9 | 1672 | dma_free_coherent(d, sizeof(*counters), counters, paddr); |
d4a3a0fc SH |
1673 | } |
1674 | ||
355423d0 IV |
1675 | static void rtl8169_get_ethtool_stats(struct net_device *dev, |
1676 | struct ethtool_stats *stats, u64 *data) | |
1677 | { | |
1678 | struct rtl8169_private *tp = netdev_priv(dev); | |
1679 | ||
1680 | ASSERT_RTNL(); | |
1681 | ||
1682 | rtl8169_update_counters(dev); | |
1683 | ||
1684 | data[0] = le64_to_cpu(tp->counters.tx_packets); | |
1685 | data[1] = le64_to_cpu(tp->counters.rx_packets); | |
1686 | data[2] = le64_to_cpu(tp->counters.tx_errors); | |
1687 | data[3] = le32_to_cpu(tp->counters.rx_errors); | |
1688 | data[4] = le16_to_cpu(tp->counters.rx_missed); | |
1689 | data[5] = le16_to_cpu(tp->counters.align_errors); | |
1690 | data[6] = le32_to_cpu(tp->counters.tx_one_collision); | |
1691 | data[7] = le32_to_cpu(tp->counters.tx_multi_collision); | |
1692 | data[8] = le64_to_cpu(tp->counters.rx_unicast); | |
1693 | data[9] = le64_to_cpu(tp->counters.rx_broadcast); | |
1694 | data[10] = le32_to_cpu(tp->counters.rx_multicast); | |
1695 | data[11] = le16_to_cpu(tp->counters.tx_aborted); | |
1696 | data[12] = le16_to_cpu(tp->counters.tx_underun); | |
1697 | } | |
1698 | ||
d4a3a0fc SH |
1699 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
1700 | { | |
1701 | switch(stringset) { | |
1702 | case ETH_SS_STATS: | |
1703 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
1704 | break; | |
1705 | } | |
1706 | } | |
1707 | ||
7282d491 | 1708 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
1709 | .get_drvinfo = rtl8169_get_drvinfo, |
1710 | .get_regs_len = rtl8169_get_regs_len, | |
1711 | .get_link = ethtool_op_get_link, | |
1712 | .get_settings = rtl8169_get_settings, | |
1713 | .set_settings = rtl8169_set_settings, | |
b57b7e5a SH |
1714 | .get_msglevel = rtl8169_get_msglevel, |
1715 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 | 1716 | .get_regs = rtl8169_get_regs, |
61a4dcc2 FR |
1717 | .get_wol = rtl8169_get_wol, |
1718 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 1719 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 1720 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 1721 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
1da177e4 LT |
1722 | }; |
1723 | ||
07d3f51f | 1724 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
5d320a20 | 1725 | struct net_device *dev, u8 default_version) |
1da177e4 | 1726 | { |
5d320a20 | 1727 | void __iomem *ioaddr = tp->mmio_addr; |
0e485150 FR |
1728 | /* |
1729 | * The driver currently handles the 8168Bf and the 8168Be identically | |
1730 | * but they can be identified more specifically through the test below | |
1731 | * if needed: | |
1732 | * | |
1733 | * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be | |
0127215c FR |
1734 | * |
1735 | * Same thing for the 8101Eb and the 8101Ec: | |
1736 | * | |
1737 | * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec | |
0e485150 | 1738 | */ |
3744100e | 1739 | static const struct rtl_mac_info { |
1da177e4 | 1740 | u32 mask; |
e3cf0cc0 | 1741 | u32 val; |
1da177e4 LT |
1742 | int mac_version; |
1743 | } mac_info[] = { | |
01dc7fec | 1744 | /* 8168E family. */ |
70090424 | 1745 | { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 }, |
01dc7fec | 1746 | { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, |
1747 | { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, | |
1748 | { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, | |
1749 | ||
5b538df9 | 1750 | /* 8168D family. */ |
daf9df6d | 1751 | { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
1752 | { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, | |
daf9df6d | 1753 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
5b538df9 | 1754 | |
e6de30d6 | 1755 | /* 8168DP family. */ |
1756 | { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, | |
1757 | { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, | |
4804b3b3 | 1758 | { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, |
e6de30d6 | 1759 | |
ef808d50 | 1760 | /* 8168C family. */ |
17c99297 | 1761 | { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
ef3386f0 | 1762 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
ef808d50 | 1763 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
7f3e3d3a | 1764 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
e3cf0cc0 FR |
1765 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
1766 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
197ff761 | 1767 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
6fb07058 | 1768 | { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
ef808d50 | 1769 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
e3cf0cc0 FR |
1770 | |
1771 | /* 8168B family. */ | |
1772 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
1773 | { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, | |
1774 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, | |
1775 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
1776 | ||
1777 | /* 8101 family. */ | |
36a0e6c2 | 1778 | { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, |
5a5e4443 HW |
1779 | { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, |
1780 | { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, | |
1781 | { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, | |
2857ffb7 FR |
1782 | { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
1783 | { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, | |
1784 | { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, | |
1785 | { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, | |
1786 | { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, | |
1787 | { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, | |
e3cf0cc0 | 1788 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
2857ffb7 | 1789 | { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
e3cf0cc0 | 1790 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
2857ffb7 FR |
1791 | { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
1792 | { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, | |
e3cf0cc0 FR |
1793 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
1794 | /* FIXME: where did these entries come from ? -- FR */ | |
1795 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
1796 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
1797 | ||
1798 | /* 8110 family. */ | |
1799 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
1800 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
1801 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
1802 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
1803 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
1804 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
1805 | ||
f21b75e9 JD |
1806 | /* Catch-all */ |
1807 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } | |
3744100e FR |
1808 | }; |
1809 | const struct rtl_mac_info *p = mac_info; | |
1da177e4 LT |
1810 | u32 reg; |
1811 | ||
e3cf0cc0 FR |
1812 | reg = RTL_R32(TxConfig); |
1813 | while ((reg & p->mask) != p->val) | |
1da177e4 LT |
1814 | p++; |
1815 | tp->mac_version = p->mac_version; | |
5d320a20 FR |
1816 | |
1817 | if (tp->mac_version == RTL_GIGA_MAC_NONE) { | |
1818 | netif_notice(tp, probe, dev, | |
1819 | "unknown MAC, using family default\n"); | |
1820 | tp->mac_version = default_version; | |
1821 | } | |
1da177e4 LT |
1822 | } |
1823 | ||
1824 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
1825 | { | |
bcf0bf90 | 1826 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
1827 | } |
1828 | ||
867763c1 FR |
1829 | struct phy_reg { |
1830 | u16 reg; | |
1831 | u16 val; | |
1832 | }; | |
1833 | ||
4da19633 | 1834 | static void rtl_writephy_batch(struct rtl8169_private *tp, |
1835 | const struct phy_reg *regs, int len) | |
867763c1 FR |
1836 | { |
1837 | while (len-- > 0) { | |
4da19633 | 1838 | rtl_writephy(tp, regs->reg, regs->val); |
867763c1 FR |
1839 | regs++; |
1840 | } | |
1841 | } | |
1842 | ||
bca03d5f | 1843 | #define PHY_READ 0x00000000 |
1844 | #define PHY_DATA_OR 0x10000000 | |
1845 | #define PHY_DATA_AND 0x20000000 | |
1846 | #define PHY_BJMPN 0x30000000 | |
1847 | #define PHY_READ_EFUSE 0x40000000 | |
1848 | #define PHY_READ_MAC_BYTE 0x50000000 | |
1849 | #define PHY_WRITE_MAC_BYTE 0x60000000 | |
1850 | #define PHY_CLEAR_READCOUNT 0x70000000 | |
1851 | #define PHY_WRITE 0x80000000 | |
1852 | #define PHY_READCOUNT_EQ_SKIP 0x90000000 | |
1853 | #define PHY_COMP_EQ_SKIPN 0xa0000000 | |
1854 | #define PHY_COMP_NEQ_SKIPN 0xb0000000 | |
1855 | #define PHY_WRITE_PREVIOUS 0xc0000000 | |
1856 | #define PHY_SKIPN 0xd0000000 | |
1857 | #define PHY_DELAY_MS 0xe0000000 | |
1858 | #define PHY_WRITE_ERI_WORD 0xf0000000 | |
1859 | ||
960aee6c HW |
1860 | struct fw_info { |
1861 | u32 magic; | |
1862 | char version[RTL_VER_SIZE]; | |
1863 | __le32 fw_start; | |
1864 | __le32 fw_len; | |
1865 | u8 chksum; | |
1866 | } __packed; | |
1867 | ||
1c361efb FR |
1868 | #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code)) |
1869 | ||
1870 | static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
bca03d5f | 1871 | { |
b6ffd97f | 1872 | const struct firmware *fw = rtl_fw->fw; |
960aee6c | 1873 | struct fw_info *fw_info = (struct fw_info *)fw->data; |
1c361efb FR |
1874 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; |
1875 | char *version = rtl_fw->version; | |
1876 | bool rc = false; | |
1877 | ||
1878 | if (fw->size < FW_OPCODE_SIZE) | |
1879 | goto out; | |
960aee6c HW |
1880 | |
1881 | if (!fw_info->magic) { | |
1882 | size_t i, size, start; | |
1883 | u8 checksum = 0; | |
1884 | ||
1885 | if (fw->size < sizeof(*fw_info)) | |
1886 | goto out; | |
1887 | ||
1888 | for (i = 0; i < fw->size; i++) | |
1889 | checksum += fw->data[i]; | |
1890 | if (checksum != 0) | |
1891 | goto out; | |
1892 | ||
1893 | start = le32_to_cpu(fw_info->fw_start); | |
1894 | if (start > fw->size) | |
1895 | goto out; | |
1896 | ||
1897 | size = le32_to_cpu(fw_info->fw_len); | |
1898 | if (size > (fw->size - start) / FW_OPCODE_SIZE) | |
1899 | goto out; | |
1900 | ||
1901 | memcpy(version, fw_info->version, RTL_VER_SIZE); | |
1902 | ||
1903 | pa->code = (__le32 *)(fw->data + start); | |
1904 | pa->size = size; | |
1905 | } else { | |
1c361efb FR |
1906 | if (fw->size % FW_OPCODE_SIZE) |
1907 | goto out; | |
1908 | ||
1909 | strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE); | |
1910 | ||
1911 | pa->code = (__le32 *)fw->data; | |
1912 | pa->size = fw->size / FW_OPCODE_SIZE; | |
1913 | } | |
1914 | version[RTL_VER_SIZE - 1] = 0; | |
1915 | ||
1916 | rc = true; | |
1917 | out: | |
1918 | return rc; | |
1919 | } | |
1920 | ||
fd112f2e FR |
1921 | static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev, |
1922 | struct rtl_fw_phy_action *pa) | |
1c361efb | 1923 | { |
fd112f2e | 1924 | bool rc = false; |
1c361efb | 1925 | size_t index; |
bca03d5f | 1926 | |
1c361efb FR |
1927 | for (index = 0; index < pa->size; index++) { |
1928 | u32 action = le32_to_cpu(pa->code[index]); | |
42b82dc1 | 1929 | u32 regno = (action & 0x0fff0000) >> 16; |
bca03d5f | 1930 | |
42b82dc1 | 1931 | switch(action & 0xf0000000) { |
1932 | case PHY_READ: | |
1933 | case PHY_DATA_OR: | |
1934 | case PHY_DATA_AND: | |
1935 | case PHY_READ_EFUSE: | |
1936 | case PHY_CLEAR_READCOUNT: | |
1937 | case PHY_WRITE: | |
1938 | case PHY_WRITE_PREVIOUS: | |
1939 | case PHY_DELAY_MS: | |
1940 | break; | |
1941 | ||
1942 | case PHY_BJMPN: | |
1943 | if (regno > index) { | |
fd112f2e | 1944 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 1945 | "Out of range of firmware\n"); |
fd112f2e | 1946 | goto out; |
42b82dc1 | 1947 | } |
1948 | break; | |
1949 | case PHY_READCOUNT_EQ_SKIP: | |
1c361efb | 1950 | if (index + 2 >= pa->size) { |
fd112f2e | 1951 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 1952 | "Out of range of firmware\n"); |
fd112f2e | 1953 | goto out; |
42b82dc1 | 1954 | } |
1955 | break; | |
1956 | case PHY_COMP_EQ_SKIPN: | |
1957 | case PHY_COMP_NEQ_SKIPN: | |
1958 | case PHY_SKIPN: | |
1c361efb | 1959 | if (index + 1 + regno >= pa->size) { |
fd112f2e | 1960 | netif_err(tp, ifup, tp->dev, |
cecb5fd7 | 1961 | "Out of range of firmware\n"); |
fd112f2e | 1962 | goto out; |
42b82dc1 | 1963 | } |
bca03d5f | 1964 | break; |
1965 | ||
42b82dc1 | 1966 | case PHY_READ_MAC_BYTE: |
1967 | case PHY_WRITE_MAC_BYTE: | |
1968 | case PHY_WRITE_ERI_WORD: | |
1969 | default: | |
fd112f2e | 1970 | netif_err(tp, ifup, tp->dev, |
42b82dc1 | 1971 | "Invalid action 0x%08x\n", action); |
fd112f2e | 1972 | goto out; |
bca03d5f | 1973 | } |
1974 | } | |
fd112f2e FR |
1975 | rc = true; |
1976 | out: | |
1977 | return rc; | |
1978 | } | |
bca03d5f | 1979 | |
fd112f2e FR |
1980 | static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) |
1981 | { | |
1982 | struct net_device *dev = tp->dev; | |
1983 | int rc = -EINVAL; | |
1984 | ||
1985 | if (!rtl_fw_format_ok(tp, rtl_fw)) { | |
1986 | netif_err(tp, ifup, dev, "invalid firwmare\n"); | |
1987 | goto out; | |
1988 | } | |
1989 | ||
1990 | if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action)) | |
1991 | rc = 0; | |
1992 | out: | |
1993 | return rc; | |
1994 | } | |
1995 | ||
1996 | static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw) | |
1997 | { | |
1998 | struct rtl_fw_phy_action *pa = &rtl_fw->phy_action; | |
1999 | u32 predata, count; | |
2000 | size_t index; | |
2001 | ||
2002 | predata = count = 0; | |
42b82dc1 | 2003 | |
1c361efb FR |
2004 | for (index = 0; index < pa->size; ) { |
2005 | u32 action = le32_to_cpu(pa->code[index]); | |
bca03d5f | 2006 | u32 data = action & 0x0000ffff; |
42b82dc1 | 2007 | u32 regno = (action & 0x0fff0000) >> 16; |
2008 | ||
2009 | if (!action) | |
2010 | break; | |
bca03d5f | 2011 | |
2012 | switch(action & 0xf0000000) { | |
42b82dc1 | 2013 | case PHY_READ: |
2014 | predata = rtl_readphy(tp, regno); | |
2015 | count++; | |
2016 | index++; | |
2017 | break; | |
2018 | case PHY_DATA_OR: | |
2019 | predata |= data; | |
2020 | index++; | |
2021 | break; | |
2022 | case PHY_DATA_AND: | |
2023 | predata &= data; | |
2024 | index++; | |
2025 | break; | |
2026 | case PHY_BJMPN: | |
2027 | index -= regno; | |
2028 | break; | |
2029 | case PHY_READ_EFUSE: | |
2030 | predata = rtl8168d_efuse_read(tp->mmio_addr, regno); | |
2031 | index++; | |
2032 | break; | |
2033 | case PHY_CLEAR_READCOUNT: | |
2034 | count = 0; | |
2035 | index++; | |
2036 | break; | |
bca03d5f | 2037 | case PHY_WRITE: |
42b82dc1 | 2038 | rtl_writephy(tp, regno, data); |
2039 | index++; | |
2040 | break; | |
2041 | case PHY_READCOUNT_EQ_SKIP: | |
cecb5fd7 | 2042 | index += (count == data) ? 2 : 1; |
bca03d5f | 2043 | break; |
42b82dc1 | 2044 | case PHY_COMP_EQ_SKIPN: |
2045 | if (predata == data) | |
2046 | index += regno; | |
2047 | index++; | |
2048 | break; | |
2049 | case PHY_COMP_NEQ_SKIPN: | |
2050 | if (predata != data) | |
2051 | index += regno; | |
2052 | index++; | |
2053 | break; | |
2054 | case PHY_WRITE_PREVIOUS: | |
2055 | rtl_writephy(tp, regno, predata); | |
2056 | index++; | |
2057 | break; | |
2058 | case PHY_SKIPN: | |
2059 | index += regno + 1; | |
2060 | break; | |
2061 | case PHY_DELAY_MS: | |
2062 | mdelay(data); | |
2063 | index++; | |
2064 | break; | |
2065 | ||
2066 | case PHY_READ_MAC_BYTE: | |
2067 | case PHY_WRITE_MAC_BYTE: | |
2068 | case PHY_WRITE_ERI_WORD: | |
bca03d5f | 2069 | default: |
2070 | BUG(); | |
2071 | } | |
2072 | } | |
2073 | } | |
2074 | ||
f1e02ed1 | 2075 | static void rtl_release_firmware(struct rtl8169_private *tp) |
2076 | { | |
b6ffd97f FR |
2077 | if (!IS_ERR_OR_NULL(tp->rtl_fw)) { |
2078 | release_firmware(tp->rtl_fw->fw); | |
2079 | kfree(tp->rtl_fw); | |
2080 | } | |
2081 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; | |
f1e02ed1 | 2082 | } |
2083 | ||
953a12cc | 2084 | static void rtl_apply_firmware(struct rtl8169_private *tp) |
f1e02ed1 | 2085 | { |
b6ffd97f | 2086 | struct rtl_fw *rtl_fw = tp->rtl_fw; |
f1e02ed1 | 2087 | |
2088 | /* TODO: release firmware once rtl_phy_write_fw signals failures. */ | |
b6ffd97f FR |
2089 | if (!IS_ERR_OR_NULL(rtl_fw)) |
2090 | rtl_phy_write_fw(tp, rtl_fw); | |
953a12cc FR |
2091 | } |
2092 | ||
2093 | static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val) | |
2094 | { | |
2095 | if (rtl_readphy(tp, reg) != val) | |
2096 | netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n"); | |
2097 | else | |
2098 | rtl_apply_firmware(tp); | |
f1e02ed1 | 2099 | } |
2100 | ||
4da19633 | 2101 | static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
1da177e4 | 2102 | { |
350f7596 | 2103 | static const struct phy_reg phy_reg_init[] = { |
0b9b571d | 2104 | { 0x1f, 0x0001 }, |
2105 | { 0x06, 0x006e }, | |
2106 | { 0x08, 0x0708 }, | |
2107 | { 0x15, 0x4000 }, | |
2108 | { 0x18, 0x65c7 }, | |
1da177e4 | 2109 | |
0b9b571d | 2110 | { 0x1f, 0x0001 }, |
2111 | { 0x03, 0x00a1 }, | |
2112 | { 0x02, 0x0008 }, | |
2113 | { 0x01, 0x0120 }, | |
2114 | { 0x00, 0x1000 }, | |
2115 | { 0x04, 0x0800 }, | |
2116 | { 0x04, 0x0000 }, | |
1da177e4 | 2117 | |
0b9b571d | 2118 | { 0x03, 0xff41 }, |
2119 | { 0x02, 0xdf60 }, | |
2120 | { 0x01, 0x0140 }, | |
2121 | { 0x00, 0x0077 }, | |
2122 | { 0x04, 0x7800 }, | |
2123 | { 0x04, 0x7000 }, | |
2124 | ||
2125 | { 0x03, 0x802f }, | |
2126 | { 0x02, 0x4f02 }, | |
2127 | { 0x01, 0x0409 }, | |
2128 | { 0x00, 0xf0f9 }, | |
2129 | { 0x04, 0x9800 }, | |
2130 | { 0x04, 0x9000 }, | |
2131 | ||
2132 | { 0x03, 0xdf01 }, | |
2133 | { 0x02, 0xdf20 }, | |
2134 | { 0x01, 0xff95 }, | |
2135 | { 0x00, 0xba00 }, | |
2136 | { 0x04, 0xa800 }, | |
2137 | { 0x04, 0xa000 }, | |
2138 | ||
2139 | { 0x03, 0xff41 }, | |
2140 | { 0x02, 0xdf20 }, | |
2141 | { 0x01, 0x0140 }, | |
2142 | { 0x00, 0x00bb }, | |
2143 | { 0x04, 0xb800 }, | |
2144 | { 0x04, 0xb000 }, | |
2145 | ||
2146 | { 0x03, 0xdf41 }, | |
2147 | { 0x02, 0xdc60 }, | |
2148 | { 0x01, 0x6340 }, | |
2149 | { 0x00, 0x007d }, | |
2150 | { 0x04, 0xd800 }, | |
2151 | { 0x04, 0xd000 }, | |
2152 | ||
2153 | { 0x03, 0xdf01 }, | |
2154 | { 0x02, 0xdf20 }, | |
2155 | { 0x01, 0x100a }, | |
2156 | { 0x00, 0xa0ff }, | |
2157 | { 0x04, 0xf800 }, | |
2158 | { 0x04, 0xf000 }, | |
2159 | ||
2160 | { 0x1f, 0x0000 }, | |
2161 | { 0x0b, 0x0000 }, | |
2162 | { 0x00, 0x9200 } | |
2163 | }; | |
1da177e4 | 2164 | |
4da19633 | 2165 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1da177e4 LT |
2166 | } |
2167 | ||
4da19633 | 2168 | static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
5615d9f1 | 2169 | { |
350f7596 | 2170 | static const struct phy_reg phy_reg_init[] = { |
a441d7b6 FR |
2171 | { 0x1f, 0x0002 }, |
2172 | { 0x01, 0x90d0 }, | |
2173 | { 0x1f, 0x0000 } | |
2174 | }; | |
2175 | ||
4da19633 | 2176 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5615d9f1 FR |
2177 | } |
2178 | ||
4da19633 | 2179 | static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
2e955856 | 2180 | { |
2181 | struct pci_dev *pdev = tp->pci_dev; | |
2e955856 | 2182 | |
ccbae55e SS |
2183 | if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) || |
2184 | (pdev->subsystem_device != 0xe000)) | |
2e955856 | 2185 | return; |
2186 | ||
4da19633 | 2187 | rtl_writephy(tp, 0x1f, 0x0001); |
2188 | rtl_writephy(tp, 0x10, 0xf01b); | |
2189 | rtl_writephy(tp, 0x1f, 0x0000); | |
2e955856 | 2190 | } |
2191 | ||
4da19633 | 2192 | static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
2e955856 | 2193 | { |
350f7596 | 2194 | static const struct phy_reg phy_reg_init[] = { |
2e955856 | 2195 | { 0x1f, 0x0001 }, |
2196 | { 0x04, 0x0000 }, | |
2197 | { 0x03, 0x00a1 }, | |
2198 | { 0x02, 0x0008 }, | |
2199 | { 0x01, 0x0120 }, | |
2200 | { 0x00, 0x1000 }, | |
2201 | { 0x04, 0x0800 }, | |
2202 | { 0x04, 0x9000 }, | |
2203 | { 0x03, 0x802f }, | |
2204 | { 0x02, 0x4f02 }, | |
2205 | { 0x01, 0x0409 }, | |
2206 | { 0x00, 0xf099 }, | |
2207 | { 0x04, 0x9800 }, | |
2208 | { 0x04, 0xa000 }, | |
2209 | { 0x03, 0xdf01 }, | |
2210 | { 0x02, 0xdf20 }, | |
2211 | { 0x01, 0xff95 }, | |
2212 | { 0x00, 0xba00 }, | |
2213 | { 0x04, 0xa800 }, | |
2214 | { 0x04, 0xf000 }, | |
2215 | { 0x03, 0xdf01 }, | |
2216 | { 0x02, 0xdf20 }, | |
2217 | { 0x01, 0x101a }, | |
2218 | { 0x00, 0xa0ff }, | |
2219 | { 0x04, 0xf800 }, | |
2220 | { 0x04, 0x0000 }, | |
2221 | { 0x1f, 0x0000 }, | |
2222 | ||
2223 | { 0x1f, 0x0001 }, | |
2224 | { 0x10, 0xf41b }, | |
2225 | { 0x14, 0xfb54 }, | |
2226 | { 0x18, 0xf5c7 }, | |
2227 | { 0x1f, 0x0000 }, | |
2228 | ||
2229 | { 0x1f, 0x0001 }, | |
2230 | { 0x17, 0x0cc0 }, | |
2231 | { 0x1f, 0x0000 } | |
2232 | }; | |
2233 | ||
4da19633 | 2234 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2e955856 | 2235 | |
4da19633 | 2236 | rtl8169scd_hw_phy_config_quirk(tp); |
2e955856 | 2237 | } |
2238 | ||
4da19633 | 2239 | static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
8c7006aa | 2240 | { |
350f7596 | 2241 | static const struct phy_reg phy_reg_init[] = { |
8c7006aa | 2242 | { 0x1f, 0x0001 }, |
2243 | { 0x04, 0x0000 }, | |
2244 | { 0x03, 0x00a1 }, | |
2245 | { 0x02, 0x0008 }, | |
2246 | { 0x01, 0x0120 }, | |
2247 | { 0x00, 0x1000 }, | |
2248 | { 0x04, 0x0800 }, | |
2249 | { 0x04, 0x9000 }, | |
2250 | { 0x03, 0x802f }, | |
2251 | { 0x02, 0x4f02 }, | |
2252 | { 0x01, 0x0409 }, | |
2253 | { 0x00, 0xf099 }, | |
2254 | { 0x04, 0x9800 }, | |
2255 | { 0x04, 0xa000 }, | |
2256 | { 0x03, 0xdf01 }, | |
2257 | { 0x02, 0xdf20 }, | |
2258 | { 0x01, 0xff95 }, | |
2259 | { 0x00, 0xba00 }, | |
2260 | { 0x04, 0xa800 }, | |
2261 | { 0x04, 0xf000 }, | |
2262 | { 0x03, 0xdf01 }, | |
2263 | { 0x02, 0xdf20 }, | |
2264 | { 0x01, 0x101a }, | |
2265 | { 0x00, 0xa0ff }, | |
2266 | { 0x04, 0xf800 }, | |
2267 | { 0x04, 0x0000 }, | |
2268 | { 0x1f, 0x0000 }, | |
2269 | ||
2270 | { 0x1f, 0x0001 }, | |
2271 | { 0x0b, 0x8480 }, | |
2272 | { 0x1f, 0x0000 }, | |
2273 | ||
2274 | { 0x1f, 0x0001 }, | |
2275 | { 0x18, 0x67c7 }, | |
2276 | { 0x04, 0x2000 }, | |
2277 | { 0x03, 0x002f }, | |
2278 | { 0x02, 0x4360 }, | |
2279 | { 0x01, 0x0109 }, | |
2280 | { 0x00, 0x3022 }, | |
2281 | { 0x04, 0x2800 }, | |
2282 | { 0x1f, 0x0000 }, | |
2283 | ||
2284 | { 0x1f, 0x0001 }, | |
2285 | { 0x17, 0x0cc0 }, | |
2286 | { 0x1f, 0x0000 } | |
2287 | }; | |
2288 | ||
4da19633 | 2289 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
8c7006aa | 2290 | } |
2291 | ||
4da19633 | 2292 | static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2293 | { |
350f7596 | 2294 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2295 | { 0x10, 0xf41b }, |
2296 | { 0x1f, 0x0000 } | |
2297 | }; | |
2298 | ||
4da19633 | 2299 | rtl_writephy(tp, 0x1f, 0x0001); |
2300 | rtl_patchphy(tp, 0x16, 1 << 0); | |
236b8082 | 2301 | |
4da19633 | 2302 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2303 | } |
2304 | ||
4da19633 | 2305 | static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2306 | { |
350f7596 | 2307 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2308 | { 0x1f, 0x0001 }, |
2309 | { 0x10, 0xf41b }, | |
2310 | { 0x1f, 0x0000 } | |
2311 | }; | |
2312 | ||
4da19633 | 2313 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2314 | } |
2315 | ||
4da19633 | 2316 | static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2317 | { |
350f7596 | 2318 | static const struct phy_reg phy_reg_init[] = { |
867763c1 FR |
2319 | { 0x1f, 0x0000 }, |
2320 | { 0x1d, 0x0f00 }, | |
2321 | { 0x1f, 0x0002 }, | |
2322 | { 0x0c, 0x1ec8 }, | |
2323 | { 0x1f, 0x0000 } | |
2324 | }; | |
2325 | ||
4da19633 | 2326 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
867763c1 FR |
2327 | } |
2328 | ||
4da19633 | 2329 | static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
ef3386f0 | 2330 | { |
350f7596 | 2331 | static const struct phy_reg phy_reg_init[] = { |
ef3386f0 FR |
2332 | { 0x1f, 0x0001 }, |
2333 | { 0x1d, 0x3d98 }, | |
2334 | { 0x1f, 0x0000 } | |
2335 | }; | |
2336 | ||
4da19633 | 2337 | rtl_writephy(tp, 0x1f, 0x0000); |
2338 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2339 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
ef3386f0 | 2340 | |
4da19633 | 2341 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
ef3386f0 FR |
2342 | } |
2343 | ||
4da19633 | 2344 | static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2345 | { |
350f7596 | 2346 | static const struct phy_reg phy_reg_init[] = { |
a3f80671 FR |
2347 | { 0x1f, 0x0001 }, |
2348 | { 0x12, 0x2300 }, | |
867763c1 FR |
2349 | { 0x1f, 0x0002 }, |
2350 | { 0x00, 0x88d4 }, | |
2351 | { 0x01, 0x82b1 }, | |
2352 | { 0x03, 0x7002 }, | |
2353 | { 0x08, 0x9e30 }, | |
2354 | { 0x09, 0x01f0 }, | |
2355 | { 0x0a, 0x5500 }, | |
2356 | { 0x0c, 0x00c8 }, | |
2357 | { 0x1f, 0x0003 }, | |
2358 | { 0x12, 0xc096 }, | |
2359 | { 0x16, 0x000a }, | |
f50d4275 FR |
2360 | { 0x1f, 0x0000 }, |
2361 | { 0x1f, 0x0000 }, | |
2362 | { 0x09, 0x2000 }, | |
2363 | { 0x09, 0x0000 } | |
867763c1 FR |
2364 | }; |
2365 | ||
4da19633 | 2366 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2367 | |
4da19633 | 2368 | rtl_patchphy(tp, 0x14, 1 << 5); |
2369 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2370 | rtl_writephy(tp, 0x1f, 0x0000); | |
867763c1 FR |
2371 | } |
2372 | ||
4da19633 | 2373 | static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
7da97ec9 | 2374 | { |
350f7596 | 2375 | static const struct phy_reg phy_reg_init[] = { |
f50d4275 | 2376 | { 0x1f, 0x0001 }, |
7da97ec9 | 2377 | { 0x12, 0x2300 }, |
f50d4275 FR |
2378 | { 0x03, 0x802f }, |
2379 | { 0x02, 0x4f02 }, | |
2380 | { 0x01, 0x0409 }, | |
2381 | { 0x00, 0xf099 }, | |
2382 | { 0x04, 0x9800 }, | |
2383 | { 0x04, 0x9000 }, | |
2384 | { 0x1d, 0x3d98 }, | |
7da97ec9 FR |
2385 | { 0x1f, 0x0002 }, |
2386 | { 0x0c, 0x7eb8 }, | |
f50d4275 FR |
2387 | { 0x06, 0x0761 }, |
2388 | { 0x1f, 0x0003 }, | |
2389 | { 0x16, 0x0f0a }, | |
7da97ec9 FR |
2390 | { 0x1f, 0x0000 } |
2391 | }; | |
2392 | ||
4da19633 | 2393 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2394 | |
4da19633 | 2395 | rtl_patchphy(tp, 0x16, 1 << 0); |
2396 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2397 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2398 | rtl_writephy(tp, 0x1f, 0x0000); | |
7da97ec9 FR |
2399 | } |
2400 | ||
4da19633 | 2401 | static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
197ff761 | 2402 | { |
350f7596 | 2403 | static const struct phy_reg phy_reg_init[] = { |
197ff761 FR |
2404 | { 0x1f, 0x0001 }, |
2405 | { 0x12, 0x2300 }, | |
2406 | { 0x1d, 0x3d98 }, | |
2407 | { 0x1f, 0x0002 }, | |
2408 | { 0x0c, 0x7eb8 }, | |
2409 | { 0x06, 0x5461 }, | |
2410 | { 0x1f, 0x0003 }, | |
2411 | { 0x16, 0x0f0a }, | |
2412 | { 0x1f, 0x0000 } | |
2413 | }; | |
2414 | ||
4da19633 | 2415 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
197ff761 | 2416 | |
4da19633 | 2417 | rtl_patchphy(tp, 0x16, 1 << 0); |
2418 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2419 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2420 | rtl_writephy(tp, 0x1f, 0x0000); | |
197ff761 FR |
2421 | } |
2422 | ||
4da19633 | 2423 | static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
6fb07058 | 2424 | { |
4da19633 | 2425 | rtl8168c_3_hw_phy_config(tp); |
6fb07058 FR |
2426 | } |
2427 | ||
bca03d5f | 2428 | static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
5b538df9 | 2429 | { |
350f7596 | 2430 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 2431 | /* Channel Estimation */ |
5b538df9 | 2432 | { 0x1f, 0x0001 }, |
daf9df6d | 2433 | { 0x06, 0x4064 }, |
2434 | { 0x07, 0x2863 }, | |
2435 | { 0x08, 0x059c }, | |
2436 | { 0x09, 0x26b4 }, | |
2437 | { 0x0a, 0x6a19 }, | |
2438 | { 0x0b, 0xdcc8 }, | |
2439 | { 0x10, 0xf06d }, | |
2440 | { 0x14, 0x7f68 }, | |
2441 | { 0x18, 0x7fd9 }, | |
2442 | { 0x1c, 0xf0ff }, | |
2443 | { 0x1d, 0x3d9c }, | |
5b538df9 | 2444 | { 0x1f, 0x0003 }, |
daf9df6d | 2445 | { 0x12, 0xf49f }, |
2446 | { 0x13, 0x070b }, | |
2447 | { 0x1a, 0x05ad }, | |
bca03d5f | 2448 | { 0x14, 0x94c0 }, |
2449 | ||
2450 | /* | |
2451 | * Tx Error Issue | |
cecb5fd7 | 2452 | * Enhance line driver power |
bca03d5f | 2453 | */ |
5b538df9 | 2454 | { 0x1f, 0x0002 }, |
daf9df6d | 2455 | { 0x06, 0x5561 }, |
2456 | { 0x1f, 0x0005 }, | |
2457 | { 0x05, 0x8332 }, | |
bca03d5f | 2458 | { 0x06, 0x5561 }, |
2459 | ||
2460 | /* | |
2461 | * Can not link to 1Gbps with bad cable | |
2462 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
2463 | */ | |
2464 | { 0x1f, 0x0001 }, | |
2465 | { 0x17, 0x0cc0 }, | |
daf9df6d | 2466 | |
5b538df9 | 2467 | { 0x1f, 0x0000 }, |
bca03d5f | 2468 | { 0x0d, 0xf880 } |
daf9df6d | 2469 | }; |
bca03d5f | 2470 | void __iomem *ioaddr = tp->mmio_addr; |
daf9df6d | 2471 | |
4da19633 | 2472 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
daf9df6d | 2473 | |
bca03d5f | 2474 | /* |
2475 | * Rx Error Issue | |
2476 | * Fine Tune Switching regulator parameter | |
2477 | */ | |
4da19633 | 2478 | rtl_writephy(tp, 0x1f, 0x0002); |
2479 | rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); | |
2480 | rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); | |
daf9df6d | 2481 | |
daf9df6d | 2482 | if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
350f7596 | 2483 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2484 | { 0x1f, 0x0002 }, |
2485 | { 0x05, 0x669a }, | |
2486 | { 0x1f, 0x0005 }, | |
2487 | { 0x05, 0x8330 }, | |
2488 | { 0x06, 0x669a }, | |
2489 | { 0x1f, 0x0002 } | |
2490 | }; | |
2491 | int val; | |
2492 | ||
4da19633 | 2493 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2494 | |
4da19633 | 2495 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 2496 | |
2497 | if ((val & 0x00ff) != 0x006c) { | |
350f7596 | 2498 | static const u32 set[] = { |
daf9df6d | 2499 | 0x0065, 0x0066, 0x0067, 0x0068, |
2500 | 0x0069, 0x006a, 0x006b, 0x006c | |
2501 | }; | |
2502 | int i; | |
2503 | ||
4da19633 | 2504 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 2505 | |
2506 | val &= 0xff00; | |
2507 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 2508 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 2509 | } |
2510 | } else { | |
350f7596 | 2511 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2512 | { 0x1f, 0x0002 }, |
2513 | { 0x05, 0x6662 }, | |
2514 | { 0x1f, 0x0005 }, | |
2515 | { 0x05, 0x8330 }, | |
2516 | { 0x06, 0x6662 } | |
2517 | }; | |
2518 | ||
4da19633 | 2519 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2520 | } |
2521 | ||
bca03d5f | 2522 | /* RSET couple improve */ |
4da19633 | 2523 | rtl_writephy(tp, 0x1f, 0x0002); |
2524 | rtl_patchphy(tp, 0x0d, 0x0300); | |
2525 | rtl_patchphy(tp, 0x0f, 0x0010); | |
daf9df6d | 2526 | |
bca03d5f | 2527 | /* Fine tune PLL performance */ |
4da19633 | 2528 | rtl_writephy(tp, 0x1f, 0x0002); |
2529 | rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); | |
2530 | rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 2531 | |
4da19633 | 2532 | rtl_writephy(tp, 0x1f, 0x0005); |
2533 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
2534 | |
2535 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00); | |
bca03d5f | 2536 | |
4da19633 | 2537 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 2538 | } |
2539 | ||
bca03d5f | 2540 | static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 2541 | { |
350f7596 | 2542 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 2543 | /* Channel Estimation */ |
daf9df6d | 2544 | { 0x1f, 0x0001 }, |
2545 | { 0x06, 0x4064 }, | |
2546 | { 0x07, 0x2863 }, | |
2547 | { 0x08, 0x059c }, | |
2548 | { 0x09, 0x26b4 }, | |
2549 | { 0x0a, 0x6a19 }, | |
2550 | { 0x0b, 0xdcc8 }, | |
2551 | { 0x10, 0xf06d }, | |
2552 | { 0x14, 0x7f68 }, | |
2553 | { 0x18, 0x7fd9 }, | |
2554 | { 0x1c, 0xf0ff }, | |
2555 | { 0x1d, 0x3d9c }, | |
2556 | { 0x1f, 0x0003 }, | |
2557 | { 0x12, 0xf49f }, | |
2558 | { 0x13, 0x070b }, | |
2559 | { 0x1a, 0x05ad }, | |
2560 | { 0x14, 0x94c0 }, | |
2561 | ||
bca03d5f | 2562 | /* |
2563 | * Tx Error Issue | |
cecb5fd7 | 2564 | * Enhance line driver power |
bca03d5f | 2565 | */ |
daf9df6d | 2566 | { 0x1f, 0x0002 }, |
2567 | { 0x06, 0x5561 }, | |
2568 | { 0x1f, 0x0005 }, | |
2569 | { 0x05, 0x8332 }, | |
bca03d5f | 2570 | { 0x06, 0x5561 }, |
2571 | ||
2572 | /* | |
2573 | * Can not link to 1Gbps with bad cable | |
2574 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
2575 | */ | |
2576 | { 0x1f, 0x0001 }, | |
2577 | { 0x17, 0x0cc0 }, | |
daf9df6d | 2578 | |
2579 | { 0x1f, 0x0000 }, | |
bca03d5f | 2580 | { 0x0d, 0xf880 } |
5b538df9 | 2581 | }; |
bca03d5f | 2582 | void __iomem *ioaddr = tp->mmio_addr; |
5b538df9 | 2583 | |
4da19633 | 2584 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
5b538df9 | 2585 | |
daf9df6d | 2586 | if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
350f7596 | 2587 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2588 | { 0x1f, 0x0002 }, |
2589 | { 0x05, 0x669a }, | |
5b538df9 | 2590 | { 0x1f, 0x0005 }, |
daf9df6d | 2591 | { 0x05, 0x8330 }, |
2592 | { 0x06, 0x669a }, | |
2593 | ||
2594 | { 0x1f, 0x0002 } | |
2595 | }; | |
2596 | int val; | |
2597 | ||
4da19633 | 2598 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2599 | |
4da19633 | 2600 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 2601 | if ((val & 0x00ff) != 0x006c) { |
b6bc7650 | 2602 | static const u32 set[] = { |
daf9df6d | 2603 | 0x0065, 0x0066, 0x0067, 0x0068, |
2604 | 0x0069, 0x006a, 0x006b, 0x006c | |
2605 | }; | |
2606 | int i; | |
2607 | ||
4da19633 | 2608 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 2609 | |
2610 | val &= 0xff00; | |
2611 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 2612 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 2613 | } |
2614 | } else { | |
350f7596 | 2615 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2616 | { 0x1f, 0x0002 }, |
2617 | { 0x05, 0x2642 }, | |
5b538df9 | 2618 | { 0x1f, 0x0005 }, |
daf9df6d | 2619 | { 0x05, 0x8330 }, |
2620 | { 0x06, 0x2642 } | |
5b538df9 FR |
2621 | }; |
2622 | ||
4da19633 | 2623 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
2624 | } |
2625 | ||
bca03d5f | 2626 | /* Fine tune PLL performance */ |
4da19633 | 2627 | rtl_writephy(tp, 0x1f, 0x0002); |
2628 | rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); | |
2629 | rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 2630 | |
bca03d5f | 2631 | /* Switching regulator Slew rate */ |
4da19633 | 2632 | rtl_writephy(tp, 0x1f, 0x0002); |
2633 | rtl_patchphy(tp, 0x0f, 0x0017); | |
daf9df6d | 2634 | |
4da19633 | 2635 | rtl_writephy(tp, 0x1f, 0x0005); |
2636 | rtl_writephy(tp, 0x05, 0x001b); | |
953a12cc FR |
2637 | |
2638 | rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300); | |
bca03d5f | 2639 | |
4da19633 | 2640 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 2641 | } |
2642 | ||
4da19633 | 2643 | static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 2644 | { |
350f7596 | 2645 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2646 | { 0x1f, 0x0002 }, |
2647 | { 0x10, 0x0008 }, | |
2648 | { 0x0d, 0x006c }, | |
2649 | ||
2650 | { 0x1f, 0x0000 }, | |
2651 | { 0x0d, 0xf880 }, | |
2652 | ||
2653 | { 0x1f, 0x0001 }, | |
2654 | { 0x17, 0x0cc0 }, | |
2655 | ||
2656 | { 0x1f, 0x0001 }, | |
2657 | { 0x0b, 0xa4d8 }, | |
2658 | { 0x09, 0x281c }, | |
2659 | { 0x07, 0x2883 }, | |
2660 | { 0x0a, 0x6b35 }, | |
2661 | { 0x1d, 0x3da4 }, | |
2662 | { 0x1c, 0xeffd }, | |
2663 | { 0x14, 0x7f52 }, | |
2664 | { 0x18, 0x7fc6 }, | |
2665 | { 0x08, 0x0601 }, | |
2666 | { 0x06, 0x4063 }, | |
2667 | { 0x10, 0xf074 }, | |
2668 | { 0x1f, 0x0003 }, | |
2669 | { 0x13, 0x0789 }, | |
2670 | { 0x12, 0xf4bd }, | |
2671 | { 0x1a, 0x04fd }, | |
2672 | { 0x14, 0x84b0 }, | |
2673 | { 0x1f, 0x0000 }, | |
2674 | { 0x00, 0x9200 }, | |
2675 | ||
2676 | { 0x1f, 0x0005 }, | |
2677 | { 0x01, 0x0340 }, | |
2678 | { 0x1f, 0x0001 }, | |
2679 | { 0x04, 0x4000 }, | |
2680 | { 0x03, 0x1d21 }, | |
2681 | { 0x02, 0x0c32 }, | |
2682 | { 0x01, 0x0200 }, | |
2683 | { 0x00, 0x5554 }, | |
2684 | { 0x04, 0x4800 }, | |
2685 | { 0x04, 0x4000 }, | |
2686 | { 0x04, 0xf000 }, | |
2687 | { 0x03, 0xdf01 }, | |
2688 | { 0x02, 0xdf20 }, | |
2689 | { 0x01, 0x101a }, | |
2690 | { 0x00, 0xa0ff }, | |
2691 | { 0x04, 0xf800 }, | |
2692 | { 0x04, 0xf000 }, | |
2693 | { 0x1f, 0x0000 }, | |
2694 | ||
2695 | { 0x1f, 0x0007 }, | |
2696 | { 0x1e, 0x0023 }, | |
2697 | { 0x16, 0x0000 }, | |
2698 | { 0x1f, 0x0000 } | |
2699 | }; | |
2700 | ||
4da19633 | 2701 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
2702 | } |
2703 | ||
e6de30d6 | 2704 | static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
2705 | { | |
2706 | static const struct phy_reg phy_reg_init[] = { | |
2707 | { 0x1f, 0x0001 }, | |
2708 | { 0x17, 0x0cc0 }, | |
2709 | ||
2710 | { 0x1f, 0x0007 }, | |
2711 | { 0x1e, 0x002d }, | |
2712 | { 0x18, 0x0040 }, | |
2713 | { 0x1f, 0x0000 } | |
2714 | }; | |
2715 | ||
2716 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
2717 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2718 | } | |
2719 | ||
70090424 | 2720 | static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) |
01dc7fec | 2721 | { |
2722 | static const struct phy_reg phy_reg_init[] = { | |
2723 | /* Enable Delay cap */ | |
2724 | { 0x1f, 0x0005 }, | |
2725 | { 0x05, 0x8b80 }, | |
2726 | { 0x06, 0xc896 }, | |
2727 | { 0x1f, 0x0000 }, | |
2728 | ||
2729 | /* Channel estimation fine tune */ | |
2730 | { 0x1f, 0x0001 }, | |
2731 | { 0x0b, 0x6c20 }, | |
2732 | { 0x07, 0x2872 }, | |
2733 | { 0x1c, 0xefff }, | |
2734 | { 0x1f, 0x0003 }, | |
2735 | { 0x14, 0x6420 }, | |
2736 | { 0x1f, 0x0000 }, | |
2737 | ||
2738 | /* Update PFM & 10M TX idle timer */ | |
2739 | { 0x1f, 0x0007 }, | |
2740 | { 0x1e, 0x002f }, | |
2741 | { 0x15, 0x1919 }, | |
2742 | { 0x1f, 0x0000 }, | |
2743 | ||
2744 | { 0x1f, 0x0007 }, | |
2745 | { 0x1e, 0x00ac }, | |
2746 | { 0x18, 0x0006 }, | |
2747 | { 0x1f, 0x0000 } | |
2748 | }; | |
2749 | ||
15ecd039 FR |
2750 | rtl_apply_firmware(tp); |
2751 | ||
01dc7fec | 2752 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2753 | ||
2754 | /* DCO enable for 10M IDLE Power */ | |
2755 | rtl_writephy(tp, 0x1f, 0x0007); | |
2756 | rtl_writephy(tp, 0x1e, 0x0023); | |
2757 | rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); | |
2758 | rtl_writephy(tp, 0x1f, 0x0000); | |
2759 | ||
2760 | /* For impedance matching */ | |
2761 | rtl_writephy(tp, 0x1f, 0x0002); | |
2762 | rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); | |
cecb5fd7 | 2763 | rtl_writephy(tp, 0x1f, 0x0000); |
01dc7fec | 2764 | |
2765 | /* PHY auto speed down */ | |
2766 | rtl_writephy(tp, 0x1f, 0x0007); | |
2767 | rtl_writephy(tp, 0x1e, 0x002d); | |
2768 | rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); | |
2769 | rtl_writephy(tp, 0x1f, 0x0000); | |
2770 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
2771 | ||
2772 | rtl_writephy(tp, 0x1f, 0x0005); | |
2773 | rtl_writephy(tp, 0x05, 0x8b86); | |
2774 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
2775 | rtl_writephy(tp, 0x1f, 0x0000); | |
2776 | ||
2777 | rtl_writephy(tp, 0x1f, 0x0005); | |
2778 | rtl_writephy(tp, 0x05, 0x8b85); | |
2779 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); | |
2780 | rtl_writephy(tp, 0x1f, 0x0007); | |
2781 | rtl_writephy(tp, 0x1e, 0x0020); | |
2782 | rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); | |
2783 | rtl_writephy(tp, 0x1f, 0x0006); | |
2784 | rtl_writephy(tp, 0x00, 0x5a00); | |
2785 | rtl_writephy(tp, 0x1f, 0x0000); | |
2786 | rtl_writephy(tp, 0x0d, 0x0007); | |
2787 | rtl_writephy(tp, 0x0e, 0x003c); | |
2788 | rtl_writephy(tp, 0x0d, 0x4007); | |
2789 | rtl_writephy(tp, 0x0e, 0x0000); | |
2790 | rtl_writephy(tp, 0x0d, 0x0000); | |
2791 | } | |
2792 | ||
70090424 HW |
2793 | static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) |
2794 | { | |
2795 | static const struct phy_reg phy_reg_init[] = { | |
2796 | /* Enable Delay cap */ | |
2797 | { 0x1f, 0x0004 }, | |
2798 | { 0x1f, 0x0007 }, | |
2799 | { 0x1e, 0x00ac }, | |
2800 | { 0x18, 0x0006 }, | |
2801 | { 0x1f, 0x0002 }, | |
2802 | { 0x1f, 0x0000 }, | |
2803 | { 0x1f, 0x0000 }, | |
2804 | ||
2805 | /* Channel estimation fine tune */ | |
2806 | { 0x1f, 0x0003 }, | |
2807 | { 0x09, 0xa20f }, | |
2808 | { 0x1f, 0x0000 }, | |
2809 | { 0x1f, 0x0000 }, | |
2810 | ||
2811 | /* Green Setting */ | |
2812 | { 0x1f, 0x0005 }, | |
2813 | { 0x05, 0x8b5b }, | |
2814 | { 0x06, 0x9222 }, | |
2815 | { 0x05, 0x8b6d }, | |
2816 | { 0x06, 0x8000 }, | |
2817 | { 0x05, 0x8b76 }, | |
2818 | { 0x06, 0x8000 }, | |
2819 | { 0x1f, 0x0000 } | |
2820 | }; | |
2821 | ||
2822 | rtl_apply_firmware(tp); | |
2823 | ||
2824 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
2825 | ||
2826 | /* For 4-corner performance improve */ | |
2827 | rtl_writephy(tp, 0x1f, 0x0005); | |
2828 | rtl_writephy(tp, 0x05, 0x8b80); | |
2829 | rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); | |
2830 | rtl_writephy(tp, 0x1f, 0x0000); | |
2831 | ||
2832 | /* PHY auto speed down */ | |
2833 | rtl_writephy(tp, 0x1f, 0x0004); | |
2834 | rtl_writephy(tp, 0x1f, 0x0007); | |
2835 | rtl_writephy(tp, 0x1e, 0x002d); | |
2836 | rtl_w1w0_phy(tp, 0x18, 0x0010, 0x0000); | |
2837 | rtl_writephy(tp, 0x1f, 0x0002); | |
2838 | rtl_writephy(tp, 0x1f, 0x0000); | |
2839 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
2840 | ||
2841 | /* improve 10M EEE waveform */ | |
2842 | rtl_writephy(tp, 0x1f, 0x0005); | |
2843 | rtl_writephy(tp, 0x05, 0x8b86); | |
2844 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
2845 | rtl_writephy(tp, 0x1f, 0x0000); | |
2846 | ||
2847 | /* Improve 2-pair detection performance */ | |
2848 | rtl_writephy(tp, 0x1f, 0x0005); | |
2849 | rtl_writephy(tp, 0x05, 0x8b85); | |
2850 | rtl_w1w0_phy(tp, 0x06, 0x4000, 0x0000); | |
2851 | rtl_writephy(tp, 0x1f, 0x0000); | |
2852 | ||
2853 | /* EEE setting */ | |
2854 | rtl_w1w0_eri(tp->mmio_addr, 0x1b0, ERIAR_MASK_1111, 0x0000, 0x0003, | |
2855 | ERIAR_EXGMAC); | |
2856 | rtl_writephy(tp, 0x1f, 0x0005); | |
2857 | rtl_writephy(tp, 0x05, 0x8b85); | |
2858 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); | |
2859 | rtl_writephy(tp, 0x1f, 0x0004); | |
2860 | rtl_writephy(tp, 0x1f, 0x0007); | |
2861 | rtl_writephy(tp, 0x1e, 0x0020); | |
2862 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x0100); | |
2863 | rtl_writephy(tp, 0x1f, 0x0002); | |
2864 | rtl_writephy(tp, 0x1f, 0x0000); | |
2865 | rtl_writephy(tp, 0x0d, 0x0007); | |
2866 | rtl_writephy(tp, 0x0e, 0x003c); | |
2867 | rtl_writephy(tp, 0x0d, 0x4007); | |
2868 | rtl_writephy(tp, 0x0e, 0x0000); | |
2869 | rtl_writephy(tp, 0x0d, 0x0000); | |
2870 | ||
2871 | /* Green feature */ | |
2872 | rtl_writephy(tp, 0x1f, 0x0003); | |
2873 | rtl_w1w0_phy(tp, 0x19, 0x0000, 0x0001); | |
2874 | rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0400); | |
2875 | rtl_writephy(tp, 0x1f, 0x0000); | |
2876 | } | |
2877 | ||
4da19633 | 2878 | static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
2857ffb7 | 2879 | { |
350f7596 | 2880 | static const struct phy_reg phy_reg_init[] = { |
2857ffb7 FR |
2881 | { 0x1f, 0x0003 }, |
2882 | { 0x08, 0x441d }, | |
2883 | { 0x01, 0x9100 }, | |
2884 | { 0x1f, 0x0000 } | |
2885 | }; | |
2886 | ||
4da19633 | 2887 | rtl_writephy(tp, 0x1f, 0x0000); |
2888 | rtl_patchphy(tp, 0x11, 1 << 12); | |
2889 | rtl_patchphy(tp, 0x19, 1 << 13); | |
2890 | rtl_patchphy(tp, 0x10, 1 << 15); | |
2857ffb7 | 2891 | |
4da19633 | 2892 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2857ffb7 FR |
2893 | } |
2894 | ||
5a5e4443 HW |
2895 | static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
2896 | { | |
2897 | static const struct phy_reg phy_reg_init[] = { | |
2898 | { 0x1f, 0x0005 }, | |
2899 | { 0x1a, 0x0000 }, | |
2900 | { 0x1f, 0x0000 }, | |
2901 | ||
2902 | { 0x1f, 0x0004 }, | |
2903 | { 0x1c, 0x0000 }, | |
2904 | { 0x1f, 0x0000 }, | |
2905 | ||
2906 | { 0x1f, 0x0001 }, | |
2907 | { 0x15, 0x7701 }, | |
2908 | { 0x1f, 0x0000 } | |
2909 | }; | |
2910 | ||
2911 | /* Disable ALDPS before ram code */ | |
2912 | rtl_writephy(tp, 0x1f, 0x0000); | |
2913 | rtl_writephy(tp, 0x18, 0x0310); | |
2914 | msleep(100); | |
2915 | ||
953a12cc | 2916 | rtl_apply_firmware(tp); |
5a5e4443 HW |
2917 | |
2918 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
2919 | } | |
2920 | ||
5615d9f1 FR |
2921 | static void rtl_hw_phy_config(struct net_device *dev) |
2922 | { | |
2923 | struct rtl8169_private *tp = netdev_priv(dev); | |
5615d9f1 FR |
2924 | |
2925 | rtl8169_print_mac_version(tp); | |
2926 | ||
2927 | switch (tp->mac_version) { | |
2928 | case RTL_GIGA_MAC_VER_01: | |
2929 | break; | |
2930 | case RTL_GIGA_MAC_VER_02: | |
2931 | case RTL_GIGA_MAC_VER_03: | |
4da19633 | 2932 | rtl8169s_hw_phy_config(tp); |
5615d9f1 FR |
2933 | break; |
2934 | case RTL_GIGA_MAC_VER_04: | |
4da19633 | 2935 | rtl8169sb_hw_phy_config(tp); |
5615d9f1 | 2936 | break; |
2e955856 | 2937 | case RTL_GIGA_MAC_VER_05: |
4da19633 | 2938 | rtl8169scd_hw_phy_config(tp); |
2e955856 | 2939 | break; |
8c7006aa | 2940 | case RTL_GIGA_MAC_VER_06: |
4da19633 | 2941 | rtl8169sce_hw_phy_config(tp); |
8c7006aa | 2942 | break; |
2857ffb7 FR |
2943 | case RTL_GIGA_MAC_VER_07: |
2944 | case RTL_GIGA_MAC_VER_08: | |
2945 | case RTL_GIGA_MAC_VER_09: | |
4da19633 | 2946 | rtl8102e_hw_phy_config(tp); |
2857ffb7 | 2947 | break; |
236b8082 | 2948 | case RTL_GIGA_MAC_VER_11: |
4da19633 | 2949 | rtl8168bb_hw_phy_config(tp); |
236b8082 FR |
2950 | break; |
2951 | case RTL_GIGA_MAC_VER_12: | |
4da19633 | 2952 | rtl8168bef_hw_phy_config(tp); |
236b8082 FR |
2953 | break; |
2954 | case RTL_GIGA_MAC_VER_17: | |
4da19633 | 2955 | rtl8168bef_hw_phy_config(tp); |
236b8082 | 2956 | break; |
867763c1 | 2957 | case RTL_GIGA_MAC_VER_18: |
4da19633 | 2958 | rtl8168cp_1_hw_phy_config(tp); |
867763c1 FR |
2959 | break; |
2960 | case RTL_GIGA_MAC_VER_19: | |
4da19633 | 2961 | rtl8168c_1_hw_phy_config(tp); |
867763c1 | 2962 | break; |
7da97ec9 | 2963 | case RTL_GIGA_MAC_VER_20: |
4da19633 | 2964 | rtl8168c_2_hw_phy_config(tp); |
7da97ec9 | 2965 | break; |
197ff761 | 2966 | case RTL_GIGA_MAC_VER_21: |
4da19633 | 2967 | rtl8168c_3_hw_phy_config(tp); |
197ff761 | 2968 | break; |
6fb07058 | 2969 | case RTL_GIGA_MAC_VER_22: |
4da19633 | 2970 | rtl8168c_4_hw_phy_config(tp); |
6fb07058 | 2971 | break; |
ef3386f0 | 2972 | case RTL_GIGA_MAC_VER_23: |
7f3e3d3a | 2973 | case RTL_GIGA_MAC_VER_24: |
4da19633 | 2974 | rtl8168cp_2_hw_phy_config(tp); |
ef3386f0 | 2975 | break; |
5b538df9 | 2976 | case RTL_GIGA_MAC_VER_25: |
bca03d5f | 2977 | rtl8168d_1_hw_phy_config(tp); |
daf9df6d | 2978 | break; |
2979 | case RTL_GIGA_MAC_VER_26: | |
bca03d5f | 2980 | rtl8168d_2_hw_phy_config(tp); |
daf9df6d | 2981 | break; |
2982 | case RTL_GIGA_MAC_VER_27: | |
4da19633 | 2983 | rtl8168d_3_hw_phy_config(tp); |
5b538df9 | 2984 | break; |
e6de30d6 | 2985 | case RTL_GIGA_MAC_VER_28: |
2986 | rtl8168d_4_hw_phy_config(tp); | |
2987 | break; | |
5a5e4443 HW |
2988 | case RTL_GIGA_MAC_VER_29: |
2989 | case RTL_GIGA_MAC_VER_30: | |
2990 | rtl8105e_hw_phy_config(tp); | |
2991 | break; | |
cecb5fd7 FR |
2992 | case RTL_GIGA_MAC_VER_31: |
2993 | /* None. */ | |
2994 | break; | |
01dc7fec | 2995 | case RTL_GIGA_MAC_VER_32: |
01dc7fec | 2996 | case RTL_GIGA_MAC_VER_33: |
70090424 HW |
2997 | rtl8168e_1_hw_phy_config(tp); |
2998 | break; | |
2999 | case RTL_GIGA_MAC_VER_34: | |
3000 | rtl8168e_2_hw_phy_config(tp); | |
01dc7fec | 3001 | break; |
ef3386f0 | 3002 | |
5615d9f1 FR |
3003 | default: |
3004 | break; | |
3005 | } | |
3006 | } | |
3007 | ||
1da177e4 LT |
3008 | static void rtl8169_phy_timer(unsigned long __opaque) |
3009 | { | |
3010 | struct net_device *dev = (struct net_device *)__opaque; | |
3011 | struct rtl8169_private *tp = netdev_priv(dev); | |
3012 | struct timer_list *timer = &tp->timer; | |
3013 | void __iomem *ioaddr = tp->mmio_addr; | |
3014 | unsigned long timeout = RTL8169_PHY_TIMEOUT; | |
3015 | ||
bcf0bf90 | 3016 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 3017 | |
1da177e4 LT |
3018 | spin_lock_irq(&tp->lock); |
3019 | ||
4da19633 | 3020 | if (tp->phy_reset_pending(tp)) { |
5b0384f4 | 3021 | /* |
1da177e4 LT |
3022 | * A busy loop could burn quite a few cycles on nowadays CPU. |
3023 | * Let's delay the execution of the timer for a few ticks. | |
3024 | */ | |
3025 | timeout = HZ/10; | |
3026 | goto out_mod_timer; | |
3027 | } | |
3028 | ||
3029 | if (tp->link_ok(ioaddr)) | |
3030 | goto out_unlock; | |
3031 | ||
bf82c189 | 3032 | netif_warn(tp, link, dev, "PHY reset until link up\n"); |
1da177e4 | 3033 | |
4da19633 | 3034 | tp->phy_reset_enable(tp); |
1da177e4 LT |
3035 | |
3036 | out_mod_timer: | |
3037 | mod_timer(timer, jiffies + timeout); | |
3038 | out_unlock: | |
3039 | spin_unlock_irq(&tp->lock); | |
3040 | } | |
3041 | ||
1da177e4 LT |
3042 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3043 | /* | |
3044 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
3045 | * without having to re-enable interrupts. It's not called while | |
3046 | * the interrupt routine is executing. | |
3047 | */ | |
3048 | static void rtl8169_netpoll(struct net_device *dev) | |
3049 | { | |
3050 | struct rtl8169_private *tp = netdev_priv(dev); | |
3051 | struct pci_dev *pdev = tp->pci_dev; | |
3052 | ||
3053 | disable_irq(pdev->irq); | |
7d12e780 | 3054 | rtl8169_interrupt(pdev->irq, dev); |
1da177e4 LT |
3055 | enable_irq(pdev->irq); |
3056 | } | |
3057 | #endif | |
3058 | ||
3059 | static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, | |
3060 | void __iomem *ioaddr) | |
3061 | { | |
3062 | iounmap(ioaddr); | |
3063 | pci_release_regions(pdev); | |
87aeec76 | 3064 | pci_clear_mwi(pdev); |
1da177e4 LT |
3065 | pci_disable_device(pdev); |
3066 | free_netdev(dev); | |
3067 | } | |
3068 | ||
bf793295 FR |
3069 | static void rtl8169_phy_reset(struct net_device *dev, |
3070 | struct rtl8169_private *tp) | |
3071 | { | |
07d3f51f | 3072 | unsigned int i; |
bf793295 | 3073 | |
4da19633 | 3074 | tp->phy_reset_enable(tp); |
bf793295 | 3075 | for (i = 0; i < 100; i++) { |
4da19633 | 3076 | if (!tp->phy_reset_pending(tp)) |
bf793295 FR |
3077 | return; |
3078 | msleep(1); | |
3079 | } | |
bf82c189 | 3080 | netif_err(tp, link, dev, "PHY reset failed\n"); |
bf793295 FR |
3081 | } |
3082 | ||
2544bfc0 FR |
3083 | static bool rtl_tbi_enabled(struct rtl8169_private *tp) |
3084 | { | |
3085 | void __iomem *ioaddr = tp->mmio_addr; | |
3086 | ||
3087 | return (tp->mac_version == RTL_GIGA_MAC_VER_01) && | |
3088 | (RTL_R8(PHYstatus) & TBI_Enable); | |
3089 | } | |
3090 | ||
4ff96fa6 FR |
3091 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
3092 | { | |
3093 | void __iomem *ioaddr = tp->mmio_addr; | |
4ff96fa6 | 3094 | |
5615d9f1 | 3095 | rtl_hw_phy_config(dev); |
4ff96fa6 | 3096 | |
77332894 MS |
3097 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
3098 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
3099 | RTL_W8(0x82, 0x01); | |
3100 | } | |
4ff96fa6 | 3101 | |
6dccd16b FR |
3102 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
3103 | ||
3104 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
3105 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 3106 | |
bcf0bf90 | 3107 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 FR |
3108 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
3109 | RTL_W8(0x82, 0x01); | |
3110 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); | |
4da19633 | 3111 | rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
4ff96fa6 FR |
3112 | } |
3113 | ||
bf793295 FR |
3114 | rtl8169_phy_reset(dev, tp); |
3115 | ||
54405cde | 3116 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
cecb5fd7 FR |
3117 | ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | |
3118 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
3119 | (tp->mii.supports_gmii ? | |
3120 | ADVERTISED_1000baseT_Half | | |
3121 | ADVERTISED_1000baseT_Full : 0)); | |
4ff96fa6 | 3122 | |
2544bfc0 | 3123 | if (rtl_tbi_enabled(tp)) |
bf82c189 | 3124 | netif_info(tp, link, dev, "TBI auto-negotiating\n"); |
4ff96fa6 FR |
3125 | } |
3126 | ||
773d2021 FR |
3127 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
3128 | { | |
3129 | void __iomem *ioaddr = tp->mmio_addr; | |
3130 | u32 high; | |
3131 | u32 low; | |
3132 | ||
3133 | low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); | |
3134 | high = addr[4] | (addr[5] << 8); | |
3135 | ||
3136 | spin_lock_irq(&tp->lock); | |
3137 | ||
3138 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
908ba2bf | 3139 | |
773d2021 | 3140 | RTL_W32(MAC4, high); |
908ba2bf | 3141 | RTL_R32(MAC4); |
3142 | ||
78f1cd02 | 3143 | RTL_W32(MAC0, low); |
908ba2bf | 3144 | RTL_R32(MAC0); |
3145 | ||
c28aa385 | 3146 | if (tp->mac_version == RTL_GIGA_MAC_VER_34) { |
3147 | const struct exgmac_reg e[] = { | |
3148 | { .addr = 0xe0, ERIAR_MASK_1111, .val = low }, | |
3149 | { .addr = 0xe4, ERIAR_MASK_1111, .val = high }, | |
3150 | { .addr = 0xf0, ERIAR_MASK_1111, .val = low << 16 }, | |
3151 | { .addr = 0xf4, ERIAR_MASK_1111, .val = high << 16 | | |
3152 | low >> 16 }, | |
3153 | }; | |
3154 | ||
3155 | rtl_write_exgmac_batch(ioaddr, e, ARRAY_SIZE(e)); | |
3156 | } | |
3157 | ||
773d2021 FR |
3158 | RTL_W8(Cfg9346, Cfg9346_Lock); |
3159 | ||
3160 | spin_unlock_irq(&tp->lock); | |
3161 | } | |
3162 | ||
3163 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
3164 | { | |
3165 | struct rtl8169_private *tp = netdev_priv(dev); | |
3166 | struct sockaddr *addr = p; | |
3167 | ||
3168 | if (!is_valid_ether_addr(addr->sa_data)) | |
3169 | return -EADDRNOTAVAIL; | |
3170 | ||
3171 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
3172 | ||
3173 | rtl_rar_set(tp, dev->dev_addr); | |
3174 | ||
3175 | return 0; | |
3176 | } | |
3177 | ||
5f787a1a FR |
3178 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
3179 | { | |
3180 | struct rtl8169_private *tp = netdev_priv(dev); | |
3181 | struct mii_ioctl_data *data = if_mii(ifr); | |
3182 | ||
8b4ab28d FR |
3183 | return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
3184 | } | |
5f787a1a | 3185 | |
cecb5fd7 FR |
3186 | static int rtl_xmii_ioctl(struct rtl8169_private *tp, |
3187 | struct mii_ioctl_data *data, int cmd) | |
8b4ab28d | 3188 | { |
5f787a1a FR |
3189 | switch (cmd) { |
3190 | case SIOCGMIIPHY: | |
3191 | data->phy_id = 32; /* Internal PHY */ | |
3192 | return 0; | |
3193 | ||
3194 | case SIOCGMIIREG: | |
4da19633 | 3195 | data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
5f787a1a FR |
3196 | return 0; |
3197 | ||
3198 | case SIOCSMIIREG: | |
4da19633 | 3199 | rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
5f787a1a FR |
3200 | return 0; |
3201 | } | |
3202 | return -EOPNOTSUPP; | |
3203 | } | |
3204 | ||
8b4ab28d FR |
3205 | static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
3206 | { | |
3207 | return -EOPNOTSUPP; | |
3208 | } | |
3209 | ||
0e485150 FR |
3210 | static const struct rtl_cfg_info { |
3211 | void (*hw_start)(struct net_device *); | |
3212 | unsigned int region; | |
3213 | unsigned int align; | |
3214 | u16 intr_event; | |
3215 | u16 napi_event; | |
ccdffb9a | 3216 | unsigned features; |
f21b75e9 | 3217 | u8 default_ver; |
0e485150 FR |
3218 | } rtl_cfg_infos [] = { |
3219 | [RTL_CFG_0] = { | |
3220 | .hw_start = rtl_hw_start_8169, | |
3221 | .region = 1, | |
e9f63f30 | 3222 | .align = 0, |
0e485150 FR |
3223 | .intr_event = SYSErr | LinkChg | RxOverflow | |
3224 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 3225 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
3226 | .features = RTL_FEATURE_GMII, |
3227 | .default_ver = RTL_GIGA_MAC_VER_01, | |
0e485150 FR |
3228 | }, |
3229 | [RTL_CFG_1] = { | |
3230 | .hw_start = rtl_hw_start_8168, | |
3231 | .region = 2, | |
3232 | .align = 8, | |
53f57357 | 3233 | .intr_event = SYSErr | LinkChg | RxOverflow | |
0e485150 | 3234 | TxErr | TxOK | RxOK | RxErr, |
fbac58fc | 3235 | .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
3236 | .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, |
3237 | .default_ver = RTL_GIGA_MAC_VER_11, | |
0e485150 FR |
3238 | }, |
3239 | [RTL_CFG_2] = { | |
3240 | .hw_start = rtl_hw_start_8101, | |
3241 | .region = 2, | |
3242 | .align = 8, | |
3243 | .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | | |
3244 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 3245 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
3246 | .features = RTL_FEATURE_MSI, |
3247 | .default_ver = RTL_GIGA_MAC_VER_13, | |
0e485150 FR |
3248 | } |
3249 | }; | |
3250 | ||
fbac58fc FR |
3251 | /* Cfg9346_Unlock assumed. */ |
3252 | static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, | |
3253 | const struct rtl_cfg_info *cfg) | |
3254 | { | |
3255 | unsigned msi = 0; | |
3256 | u8 cfg2; | |
3257 | ||
3258 | cfg2 = RTL_R8(Config2) & ~MSIEnable; | |
ccdffb9a | 3259 | if (cfg->features & RTL_FEATURE_MSI) { |
fbac58fc FR |
3260 | if (pci_enable_msi(pdev)) { |
3261 | dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); | |
3262 | } else { | |
3263 | cfg2 |= MSIEnable; | |
3264 | msi = RTL_FEATURE_MSI; | |
3265 | } | |
3266 | } | |
3267 | RTL_W8(Config2, cfg2); | |
3268 | return msi; | |
3269 | } | |
3270 | ||
3271 | static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) | |
3272 | { | |
3273 | if (tp->features & RTL_FEATURE_MSI) { | |
3274 | pci_disable_msi(pdev); | |
3275 | tp->features &= ~RTL_FEATURE_MSI; | |
3276 | } | |
3277 | } | |
3278 | ||
8b4ab28d FR |
3279 | static const struct net_device_ops rtl8169_netdev_ops = { |
3280 | .ndo_open = rtl8169_open, | |
3281 | .ndo_stop = rtl8169_close, | |
3282 | .ndo_get_stats = rtl8169_get_stats, | |
00829823 | 3283 | .ndo_start_xmit = rtl8169_start_xmit, |
8b4ab28d FR |
3284 | .ndo_tx_timeout = rtl8169_tx_timeout, |
3285 | .ndo_validate_addr = eth_validate_addr, | |
3286 | .ndo_change_mtu = rtl8169_change_mtu, | |
350fb32a MM |
3287 | .ndo_fix_features = rtl8169_fix_features, |
3288 | .ndo_set_features = rtl8169_set_features, | |
8b4ab28d FR |
3289 | .ndo_set_mac_address = rtl_set_mac_address, |
3290 | .ndo_do_ioctl = rtl8169_ioctl, | |
3291 | .ndo_set_multicast_list = rtl_set_rx_mode, | |
8b4ab28d FR |
3292 | #ifdef CONFIG_NET_POLL_CONTROLLER |
3293 | .ndo_poll_controller = rtl8169_netpoll, | |
3294 | #endif | |
3295 | ||
3296 | }; | |
3297 | ||
c0e45c1c | 3298 | static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp) |
3299 | { | |
3300 | struct mdio_ops *ops = &tp->mdio_ops; | |
3301 | ||
3302 | switch (tp->mac_version) { | |
3303 | case RTL_GIGA_MAC_VER_27: | |
3304 | ops->write = r8168dp_1_mdio_write; | |
3305 | ops->read = r8168dp_1_mdio_read; | |
3306 | break; | |
e6de30d6 | 3307 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 3308 | case RTL_GIGA_MAC_VER_31: |
e6de30d6 | 3309 | ops->write = r8168dp_2_mdio_write; |
3310 | ops->read = r8168dp_2_mdio_read; | |
3311 | break; | |
c0e45c1c | 3312 | default: |
3313 | ops->write = r8169_mdio_write; | |
3314 | ops->read = r8169_mdio_read; | |
3315 | break; | |
3316 | } | |
3317 | } | |
3318 | ||
649b3b8c | 3319 | static void rtl_wol_suspend_quirk(struct rtl8169_private *tp) |
3320 | { | |
3321 | void __iomem *ioaddr = tp->mmio_addr; | |
3322 | ||
3323 | switch (tp->mac_version) { | |
3324 | case RTL_GIGA_MAC_VER_29: | |
3325 | case RTL_GIGA_MAC_VER_30: | |
3326 | case RTL_GIGA_MAC_VER_32: | |
3327 | case RTL_GIGA_MAC_VER_33: | |
3328 | case RTL_GIGA_MAC_VER_34: | |
3329 | RTL_W32(RxConfig, RTL_R32(RxConfig) | | |
3330 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); | |
3331 | break; | |
3332 | default: | |
3333 | break; | |
3334 | } | |
3335 | } | |
3336 | ||
3337 | static bool rtl_wol_pll_power_down(struct rtl8169_private *tp) | |
3338 | { | |
3339 | if (!(__rtl8169_get_wol(tp) & WAKE_ANY)) | |
3340 | return false; | |
3341 | ||
3342 | rtl_writephy(tp, 0x1f, 0x0000); | |
3343 | rtl_writephy(tp, MII_BMCR, 0x0000); | |
3344 | ||
3345 | rtl_wol_suspend_quirk(tp); | |
3346 | ||
3347 | return true; | |
3348 | } | |
3349 | ||
065c27c1 | 3350 | static void r810x_phy_power_down(struct rtl8169_private *tp) |
3351 | { | |
3352 | rtl_writephy(tp, 0x1f, 0x0000); | |
3353 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
3354 | } | |
3355 | ||
3356 | static void r810x_phy_power_up(struct rtl8169_private *tp) | |
3357 | { | |
3358 | rtl_writephy(tp, 0x1f, 0x0000); | |
3359 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); | |
3360 | } | |
3361 | ||
3362 | static void r810x_pll_power_down(struct rtl8169_private *tp) | |
3363 | { | |
649b3b8c | 3364 | if (rtl_wol_pll_power_down(tp)) |
065c27c1 | 3365 | return; |
065c27c1 | 3366 | |
3367 | r810x_phy_power_down(tp); | |
3368 | } | |
3369 | ||
3370 | static void r810x_pll_power_up(struct rtl8169_private *tp) | |
3371 | { | |
3372 | r810x_phy_power_up(tp); | |
3373 | } | |
3374 | ||
3375 | static void r8168_phy_power_up(struct rtl8169_private *tp) | |
3376 | { | |
3377 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 3378 | switch (tp->mac_version) { |
3379 | case RTL_GIGA_MAC_VER_11: | |
3380 | case RTL_GIGA_MAC_VER_12: | |
3381 | case RTL_GIGA_MAC_VER_17: | |
3382 | case RTL_GIGA_MAC_VER_18: | |
3383 | case RTL_GIGA_MAC_VER_19: | |
3384 | case RTL_GIGA_MAC_VER_20: | |
3385 | case RTL_GIGA_MAC_VER_21: | |
3386 | case RTL_GIGA_MAC_VER_22: | |
3387 | case RTL_GIGA_MAC_VER_23: | |
3388 | case RTL_GIGA_MAC_VER_24: | |
3389 | case RTL_GIGA_MAC_VER_25: | |
3390 | case RTL_GIGA_MAC_VER_26: | |
3391 | case RTL_GIGA_MAC_VER_27: | |
3392 | case RTL_GIGA_MAC_VER_28: | |
3393 | case RTL_GIGA_MAC_VER_31: | |
3394 | rtl_writephy(tp, 0x0e, 0x0000); | |
3395 | break; | |
3396 | default: | |
3397 | break; | |
3398 | } | |
065c27c1 | 3399 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
3400 | } | |
3401 | ||
3402 | static void r8168_phy_power_down(struct rtl8169_private *tp) | |
3403 | { | |
3404 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 3405 | switch (tp->mac_version) { |
3406 | case RTL_GIGA_MAC_VER_32: | |
3407 | case RTL_GIGA_MAC_VER_33: | |
3408 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); | |
3409 | break; | |
3410 | ||
3411 | case RTL_GIGA_MAC_VER_11: | |
3412 | case RTL_GIGA_MAC_VER_12: | |
3413 | case RTL_GIGA_MAC_VER_17: | |
3414 | case RTL_GIGA_MAC_VER_18: | |
3415 | case RTL_GIGA_MAC_VER_19: | |
3416 | case RTL_GIGA_MAC_VER_20: | |
3417 | case RTL_GIGA_MAC_VER_21: | |
3418 | case RTL_GIGA_MAC_VER_22: | |
3419 | case RTL_GIGA_MAC_VER_23: | |
3420 | case RTL_GIGA_MAC_VER_24: | |
3421 | case RTL_GIGA_MAC_VER_25: | |
3422 | case RTL_GIGA_MAC_VER_26: | |
3423 | case RTL_GIGA_MAC_VER_27: | |
3424 | case RTL_GIGA_MAC_VER_28: | |
3425 | case RTL_GIGA_MAC_VER_31: | |
3426 | rtl_writephy(tp, 0x0e, 0x0200); | |
3427 | default: | |
3428 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
3429 | break; | |
3430 | } | |
065c27c1 | 3431 | } |
3432 | ||
3433 | static void r8168_pll_power_down(struct rtl8169_private *tp) | |
3434 | { | |
3435 | void __iomem *ioaddr = tp->mmio_addr; | |
3436 | ||
cecb5fd7 FR |
3437 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
3438 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
3439 | tp->mac_version == RTL_GIGA_MAC_VER_31) && | |
4804b3b3 | 3440 | r8168dp_check_dash(tp)) { |
065c27c1 | 3441 | return; |
5d2e1957 | 3442 | } |
065c27c1 | 3443 | |
cecb5fd7 FR |
3444 | if ((tp->mac_version == RTL_GIGA_MAC_VER_23 || |
3445 | tp->mac_version == RTL_GIGA_MAC_VER_24) && | |
065c27c1 | 3446 | (RTL_R16(CPlusCmd) & ASF)) { |
3447 | return; | |
3448 | } | |
3449 | ||
01dc7fec | 3450 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
3451 | tp->mac_version == RTL_GIGA_MAC_VER_33) | |
3452 | rtl_ephy_write(ioaddr, 0x19, 0xff64); | |
3453 | ||
649b3b8c | 3454 | if (rtl_wol_pll_power_down(tp)) |
065c27c1 | 3455 | return; |
065c27c1 | 3456 | |
3457 | r8168_phy_power_down(tp); | |
3458 | ||
3459 | switch (tp->mac_version) { | |
3460 | case RTL_GIGA_MAC_VER_25: | |
3461 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
3462 | case RTL_GIGA_MAC_VER_27: |
3463 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 3464 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 3465 | case RTL_GIGA_MAC_VER_32: |
3466 | case RTL_GIGA_MAC_VER_33: | |
065c27c1 | 3467 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
3468 | break; | |
3469 | } | |
3470 | } | |
3471 | ||
3472 | static void r8168_pll_power_up(struct rtl8169_private *tp) | |
3473 | { | |
3474 | void __iomem *ioaddr = tp->mmio_addr; | |
3475 | ||
cecb5fd7 FR |
3476 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27 || |
3477 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
3478 | tp->mac_version == RTL_GIGA_MAC_VER_31) && | |
4804b3b3 | 3479 | r8168dp_check_dash(tp)) { |
065c27c1 | 3480 | return; |
5d2e1957 | 3481 | } |
065c27c1 | 3482 | |
3483 | switch (tp->mac_version) { | |
3484 | case RTL_GIGA_MAC_VER_25: | |
3485 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
3486 | case RTL_GIGA_MAC_VER_27: |
3487 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 3488 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 3489 | case RTL_GIGA_MAC_VER_32: |
3490 | case RTL_GIGA_MAC_VER_33: | |
065c27c1 | 3491 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
3492 | break; | |
3493 | } | |
3494 | ||
3495 | r8168_phy_power_up(tp); | |
3496 | } | |
3497 | ||
3498 | static void rtl_pll_power_op(struct rtl8169_private *tp, | |
3499 | void (*op)(struct rtl8169_private *)) | |
3500 | { | |
3501 | if (op) | |
3502 | op(tp); | |
3503 | } | |
3504 | ||
3505 | static void rtl_pll_power_down(struct rtl8169_private *tp) | |
3506 | { | |
3507 | rtl_pll_power_op(tp, tp->pll_power_ops.down); | |
3508 | } | |
3509 | ||
3510 | static void rtl_pll_power_up(struct rtl8169_private *tp) | |
3511 | { | |
3512 | rtl_pll_power_op(tp, tp->pll_power_ops.up); | |
3513 | } | |
3514 | ||
3515 | static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) | |
3516 | { | |
3517 | struct pll_power_ops *ops = &tp->pll_power_ops; | |
3518 | ||
3519 | switch (tp->mac_version) { | |
3520 | case RTL_GIGA_MAC_VER_07: | |
3521 | case RTL_GIGA_MAC_VER_08: | |
3522 | case RTL_GIGA_MAC_VER_09: | |
3523 | case RTL_GIGA_MAC_VER_10: | |
3524 | case RTL_GIGA_MAC_VER_16: | |
5a5e4443 HW |
3525 | case RTL_GIGA_MAC_VER_29: |
3526 | case RTL_GIGA_MAC_VER_30: | |
065c27c1 | 3527 | ops->down = r810x_pll_power_down; |
3528 | ops->up = r810x_pll_power_up; | |
3529 | break; | |
3530 | ||
3531 | case RTL_GIGA_MAC_VER_11: | |
3532 | case RTL_GIGA_MAC_VER_12: | |
3533 | case RTL_GIGA_MAC_VER_17: | |
3534 | case RTL_GIGA_MAC_VER_18: | |
3535 | case RTL_GIGA_MAC_VER_19: | |
3536 | case RTL_GIGA_MAC_VER_20: | |
3537 | case RTL_GIGA_MAC_VER_21: | |
3538 | case RTL_GIGA_MAC_VER_22: | |
3539 | case RTL_GIGA_MAC_VER_23: | |
3540 | case RTL_GIGA_MAC_VER_24: | |
3541 | case RTL_GIGA_MAC_VER_25: | |
3542 | case RTL_GIGA_MAC_VER_26: | |
3543 | case RTL_GIGA_MAC_VER_27: | |
e6de30d6 | 3544 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 3545 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 3546 | case RTL_GIGA_MAC_VER_32: |
3547 | case RTL_GIGA_MAC_VER_33: | |
70090424 | 3548 | case RTL_GIGA_MAC_VER_34: |
065c27c1 | 3549 | ops->down = r8168_pll_power_down; |
3550 | ops->up = r8168_pll_power_up; | |
3551 | break; | |
3552 | ||
3553 | default: | |
3554 | ops->down = NULL; | |
3555 | ops->up = NULL; | |
3556 | break; | |
3557 | } | |
3558 | } | |
3559 | ||
e542a226 HW |
3560 | static void rtl_init_rxcfg(struct rtl8169_private *tp) |
3561 | { | |
3562 | void __iomem *ioaddr = tp->mmio_addr; | |
3563 | ||
3564 | switch (tp->mac_version) { | |
3565 | case RTL_GIGA_MAC_VER_01: | |
3566 | case RTL_GIGA_MAC_VER_02: | |
3567 | case RTL_GIGA_MAC_VER_03: | |
3568 | case RTL_GIGA_MAC_VER_04: | |
3569 | case RTL_GIGA_MAC_VER_05: | |
3570 | case RTL_GIGA_MAC_VER_06: | |
3571 | case RTL_GIGA_MAC_VER_10: | |
3572 | case RTL_GIGA_MAC_VER_11: | |
3573 | case RTL_GIGA_MAC_VER_12: | |
3574 | case RTL_GIGA_MAC_VER_13: | |
3575 | case RTL_GIGA_MAC_VER_14: | |
3576 | case RTL_GIGA_MAC_VER_15: | |
3577 | case RTL_GIGA_MAC_VER_16: | |
3578 | case RTL_GIGA_MAC_VER_17: | |
3579 | RTL_W32(RxConfig, RX_FIFO_THRESH | RX_DMA_BURST); | |
3580 | break; | |
3581 | case RTL_GIGA_MAC_VER_18: | |
3582 | case RTL_GIGA_MAC_VER_19: | |
3583 | case RTL_GIGA_MAC_VER_20: | |
3584 | case RTL_GIGA_MAC_VER_21: | |
3585 | case RTL_GIGA_MAC_VER_22: | |
3586 | case RTL_GIGA_MAC_VER_23: | |
3587 | case RTL_GIGA_MAC_VER_24: | |
3588 | RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST); | |
3589 | break; | |
3590 | default: | |
3591 | RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST); | |
3592 | break; | |
3593 | } | |
3594 | } | |
3595 | ||
92fc43b4 HW |
3596 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) |
3597 | { | |
3598 | tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; | |
3599 | } | |
3600 | ||
6f43adc8 FR |
3601 | static void rtl_hw_reset(struct rtl8169_private *tp) |
3602 | { | |
3603 | void __iomem *ioaddr = tp->mmio_addr; | |
3604 | int i; | |
3605 | ||
3606 | /* Soft reset the chip. */ | |
3607 | RTL_W8(ChipCmd, CmdReset); | |
3608 | ||
3609 | /* Check that the chip has finished the reset. */ | |
3610 | for (i = 0; i < 100; i++) { | |
3611 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) | |
3612 | break; | |
92fc43b4 | 3613 | udelay(100); |
6f43adc8 | 3614 | } |
92fc43b4 HW |
3615 | |
3616 | rtl8169_init_ring_indexes(tp); | |
6f43adc8 FR |
3617 | } |
3618 | ||
1da177e4 | 3619 | static int __devinit |
4ff96fa6 | 3620 | rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 3621 | { |
0e485150 FR |
3622 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
3623 | const unsigned int region = cfg->region; | |
1da177e4 | 3624 | struct rtl8169_private *tp; |
ccdffb9a | 3625 | struct mii_if_info *mii; |
4ff96fa6 FR |
3626 | struct net_device *dev; |
3627 | void __iomem *ioaddr; | |
2b7b4318 | 3628 | int chipset, i; |
07d3f51f | 3629 | int rc; |
1da177e4 | 3630 | |
4ff96fa6 FR |
3631 | if (netif_msg_drv(&debug)) { |
3632 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
3633 | MODULENAME, RTL8169_VERSION); | |
3634 | } | |
1da177e4 | 3635 | |
1da177e4 | 3636 | dev = alloc_etherdev(sizeof (*tp)); |
4ff96fa6 | 3637 | if (!dev) { |
b57b7e5a | 3638 | if (netif_msg_drv(&debug)) |
9b91cf9d | 3639 | dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
4ff96fa6 FR |
3640 | rc = -ENOMEM; |
3641 | goto out; | |
1da177e4 LT |
3642 | } |
3643 | ||
1da177e4 | 3644 | SET_NETDEV_DEV(dev, &pdev->dev); |
8b4ab28d | 3645 | dev->netdev_ops = &rtl8169_netdev_ops; |
1da177e4 | 3646 | tp = netdev_priv(dev); |
c4028958 | 3647 | tp->dev = dev; |
21e197f2 | 3648 | tp->pci_dev = pdev; |
b57b7e5a | 3649 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
1da177e4 | 3650 | |
ccdffb9a FR |
3651 | mii = &tp->mii; |
3652 | mii->dev = dev; | |
3653 | mii->mdio_read = rtl_mdio_read; | |
3654 | mii->mdio_write = rtl_mdio_write; | |
3655 | mii->phy_id_mask = 0x1f; | |
3656 | mii->reg_num_mask = 0x1f; | |
3657 | mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); | |
3658 | ||
ba04c7c9 SG |
3659 | /* disable ASPM completely as that cause random device stop working |
3660 | * problems as well as full system hangs for some PCIe devices users */ | |
3661 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
3662 | PCIE_LINK_STATE_CLKPM); | |
3663 | ||
1da177e4 LT |
3664 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
3665 | rc = pci_enable_device(pdev); | |
b57b7e5a | 3666 | if (rc < 0) { |
bf82c189 | 3667 | netif_err(tp, probe, dev, "enable failure\n"); |
4ff96fa6 | 3668 | goto err_out_free_dev_1; |
1da177e4 LT |
3669 | } |
3670 | ||
87aeec76 | 3671 | if (pci_set_mwi(pdev) < 0) |
3672 | netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); | |
1da177e4 | 3673 | |
1da177e4 | 3674 | /* make sure PCI base addr 1 is MMIO */ |
bcf0bf90 | 3675 | if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
bf82c189 JP |
3676 | netif_err(tp, probe, dev, |
3677 | "region #%d not an MMIO resource, aborting\n", | |
3678 | region); | |
1da177e4 | 3679 | rc = -ENODEV; |
87aeec76 | 3680 | goto err_out_mwi_2; |
1da177e4 | 3681 | } |
4ff96fa6 | 3682 | |
1da177e4 | 3683 | /* check for weird/broken PCI region reporting */ |
bcf0bf90 | 3684 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
bf82c189 JP |
3685 | netif_err(tp, probe, dev, |
3686 | "Invalid PCI region size(s), aborting\n"); | |
1da177e4 | 3687 | rc = -ENODEV; |
87aeec76 | 3688 | goto err_out_mwi_2; |
1da177e4 LT |
3689 | } |
3690 | ||
3691 | rc = pci_request_regions(pdev, MODULENAME); | |
b57b7e5a | 3692 | if (rc < 0) { |
bf82c189 | 3693 | netif_err(tp, probe, dev, "could not request regions\n"); |
87aeec76 | 3694 | goto err_out_mwi_2; |
1da177e4 LT |
3695 | } |
3696 | ||
d24e9aaf | 3697 | tp->cp_cmd = RxChkSum; |
1da177e4 LT |
3698 | |
3699 | if ((sizeof(dma_addr_t) > 4) && | |
4300e8c7 | 3700 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { |
1da177e4 LT |
3701 | tp->cp_cmd |= PCIDAC; |
3702 | dev->features |= NETIF_F_HIGHDMA; | |
3703 | } else { | |
284901a9 | 3704 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 3705 | if (rc < 0) { |
bf82c189 | 3706 | netif_err(tp, probe, dev, "DMA configuration failed\n"); |
87aeec76 | 3707 | goto err_out_free_res_3; |
1da177e4 LT |
3708 | } |
3709 | } | |
3710 | ||
1da177e4 | 3711 | /* ioremap MMIO region */ |
bcf0bf90 | 3712 | ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
4ff96fa6 | 3713 | if (!ioaddr) { |
bf82c189 | 3714 | netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); |
1da177e4 | 3715 | rc = -EIO; |
87aeec76 | 3716 | goto err_out_free_res_3; |
1da177e4 | 3717 | } |
6f43adc8 | 3718 | tp->mmio_addr = ioaddr; |
1da177e4 | 3719 | |
e44daade JM |
3720 | if (!pci_is_pcie(pdev)) |
3721 | netif_info(tp, probe, dev, "not PCI Express\n"); | |
4300e8c7 | 3722 | |
e542a226 HW |
3723 | /* Identify chip attached to board */ |
3724 | rtl8169_get_mac_version(tp, dev, cfg->default_ver); | |
3725 | ||
3726 | rtl_init_rxcfg(tp); | |
3727 | ||
d78ad8cb | 3728 | RTL_W16(IntrMask, 0x0000); |
1da177e4 | 3729 | |
6f43adc8 | 3730 | rtl_hw_reset(tp); |
1da177e4 | 3731 | |
d78ad8cb KW |
3732 | RTL_W16(IntrStatus, 0xffff); |
3733 | ||
ca52efd5 | 3734 | pci_set_master(pdev); |
3735 | ||
7a8fc77b FR |
3736 | /* |
3737 | * Pretend we are using VLANs; This bypasses a nasty bug where | |
3738 | * Interrupts stop flowing on high load on 8110SCd controllers. | |
3739 | */ | |
3740 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) | |
3741 | tp->cp_cmd |= RxVlan; | |
3742 | ||
c0e45c1c | 3743 | rtl_init_mdio_ops(tp); |
065c27c1 | 3744 | rtl_init_pll_power_ops(tp); |
c0e45c1c | 3745 | |
1da177e4 | 3746 | rtl8169_print_mac_version(tp); |
1da177e4 | 3747 | |
85bffe6c FR |
3748 | chipset = tp->mac_version; |
3749 | tp->txd_version = rtl_chip_infos[chipset].txd_version; | |
1da177e4 | 3750 | |
5d06a99f FR |
3751 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
3752 | RTL_W8(Config1, RTL_R8(Config1) | PMEnable); | |
3753 | RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); | |
20037fa4 BP |
3754 | if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
3755 | tp->features |= RTL_FEATURE_WOL; | |
3756 | if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) | |
3757 | tp->features |= RTL_FEATURE_WOL; | |
fbac58fc | 3758 | tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
5d06a99f FR |
3759 | RTL_W8(Cfg9346, Cfg9346_Lock); |
3760 | ||
2544bfc0 | 3761 | if (rtl_tbi_enabled(tp)) { |
1da177e4 LT |
3762 | tp->set_speed = rtl8169_set_speed_tbi; |
3763 | tp->get_settings = rtl8169_gset_tbi; | |
3764 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; | |
3765 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
3766 | tp->link_ok = rtl8169_tbi_link_ok; | |
8b4ab28d | 3767 | tp->do_ioctl = rtl_tbi_ioctl; |
1da177e4 LT |
3768 | } else { |
3769 | tp->set_speed = rtl8169_set_speed_xmii; | |
3770 | tp->get_settings = rtl8169_gset_xmii; | |
3771 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; | |
3772 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
3773 | tp->link_ok = rtl8169_xmii_link_ok; | |
8b4ab28d | 3774 | tp->do_ioctl = rtl_xmii_ioctl; |
1da177e4 LT |
3775 | } |
3776 | ||
df58ef51 FR |
3777 | spin_lock_init(&tp->lock); |
3778 | ||
7bf6bf48 | 3779 | /* Get MAC address */ |
1da177e4 LT |
3780 | for (i = 0; i < MAC_ADDR_LEN; i++) |
3781 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | |
6d6525b7 | 3782 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 3783 | |
1da177e4 | 3784 | SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
1da177e4 LT |
3785 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
3786 | dev->irq = pdev->irq; | |
3787 | dev->base_addr = (unsigned long) ioaddr; | |
1da177e4 | 3788 | |
bea3348e | 3789 | netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
1da177e4 | 3790 | |
350fb32a MM |
3791 | /* don't enable SG, IP_CSUM and TSO by default - it might not work |
3792 | * properly for all devices */ | |
3793 | dev->features |= NETIF_F_RXCSUM | | |
3794 | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
3795 | ||
3796 | dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | |
3797 | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
3798 | dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | | |
3799 | NETIF_F_HIGHDMA; | |
3800 | ||
3801 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) | |
3802 | /* 8110SCd requires hardware Rx VLAN - disallow toggling */ | |
3803 | dev->hw_features &= ~NETIF_F_HW_VLAN_RX; | |
1da177e4 LT |
3804 | |
3805 | tp->intr_mask = 0xffff; | |
0e485150 FR |
3806 | tp->hw_start = cfg->hw_start; |
3807 | tp->intr_event = cfg->intr_event; | |
3808 | tp->napi_event = cfg->napi_event; | |
1da177e4 | 3809 | |
e03f33af FR |
3810 | tp->opts1_mask = (tp->mac_version != RTL_GIGA_MAC_VER_01) ? |
3811 | ~(RxBOVF | RxFOVF) : ~0; | |
3812 | ||
2efa53f3 FR |
3813 | init_timer(&tp->timer); |
3814 | tp->timer.data = (unsigned long) dev; | |
3815 | tp->timer.function = rtl8169_phy_timer; | |
3816 | ||
b6ffd97f | 3817 | tp->rtl_fw = RTL_FIRMWARE_UNKNOWN; |
953a12cc | 3818 | |
1da177e4 | 3819 | rc = register_netdev(dev); |
4ff96fa6 | 3820 | if (rc < 0) |
87aeec76 | 3821 | goto err_out_msi_4; |
1da177e4 LT |
3822 | |
3823 | pci_set_drvdata(pdev, dev); | |
3824 | ||
bf82c189 | 3825 | netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n", |
85bffe6c | 3826 | rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr, |
bf82c189 | 3827 | (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq); |
1da177e4 | 3828 | |
cecb5fd7 FR |
3829 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
3830 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
3831 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
b646d900 | 3832 | rtl8168_driver_start(tp); |
e6de30d6 | 3833 | } |
b646d900 | 3834 | |
8b76ab39 | 3835 | device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
1da177e4 | 3836 | |
f3ec4f87 AS |
3837 | if (pci_dev_run_wake(pdev)) |
3838 | pm_runtime_put_noidle(&pdev->dev); | |
e1759441 | 3839 | |
0d672e9f IV |
3840 | netif_carrier_off(dev); |
3841 | ||
4ff96fa6 FR |
3842 | out: |
3843 | return rc; | |
1da177e4 | 3844 | |
87aeec76 | 3845 | err_out_msi_4: |
fbac58fc | 3846 | rtl_disable_msi(pdev, tp); |
4ff96fa6 | 3847 | iounmap(ioaddr); |
87aeec76 | 3848 | err_out_free_res_3: |
4ff96fa6 | 3849 | pci_release_regions(pdev); |
87aeec76 | 3850 | err_out_mwi_2: |
4ff96fa6 | 3851 | pci_clear_mwi(pdev); |
4ff96fa6 FR |
3852 | pci_disable_device(pdev); |
3853 | err_out_free_dev_1: | |
3854 | free_netdev(dev); | |
3855 | goto out; | |
1da177e4 LT |
3856 | } |
3857 | ||
07d3f51f | 3858 | static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
3859 | { |
3860 | struct net_device *dev = pci_get_drvdata(pdev); | |
3861 | struct rtl8169_private *tp = netdev_priv(dev); | |
3862 | ||
cecb5fd7 FR |
3863 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
3864 | tp->mac_version == RTL_GIGA_MAC_VER_28 || | |
3865 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
b646d900 | 3866 | rtl8168_driver_stop(tp); |
e6de30d6 | 3867 | } |
b646d900 | 3868 | |
23f333a2 | 3869 | cancel_delayed_work_sync(&tp->task); |
eb2a021c | 3870 | |
1da177e4 | 3871 | unregister_netdev(dev); |
cc098dc7 | 3872 | |
953a12cc FR |
3873 | rtl_release_firmware(tp); |
3874 | ||
f3ec4f87 AS |
3875 | if (pci_dev_run_wake(pdev)) |
3876 | pm_runtime_get_noresume(&pdev->dev); | |
e1759441 | 3877 | |
cc098dc7 IV |
3878 | /* restore original MAC address */ |
3879 | rtl_rar_set(tp, dev->perm_addr); | |
3880 | ||
fbac58fc | 3881 | rtl_disable_msi(pdev, tp); |
1da177e4 LT |
3882 | rtl8169_release_board(pdev, dev, tp->mmio_addr); |
3883 | pci_set_drvdata(pdev, NULL); | |
3884 | } | |
3885 | ||
b6ffd97f | 3886 | static void rtl_request_uncached_firmware(struct rtl8169_private *tp) |
953a12cc | 3887 | { |
b6ffd97f FR |
3888 | struct rtl_fw *rtl_fw; |
3889 | const char *name; | |
3890 | int rc = -ENOMEM; | |
953a12cc | 3891 | |
b6ffd97f FR |
3892 | name = rtl_lookup_firmware_name(tp); |
3893 | if (!name) | |
3894 | goto out_no_firmware; | |
953a12cc | 3895 | |
b6ffd97f FR |
3896 | rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL); |
3897 | if (!rtl_fw) | |
3898 | goto err_warn; | |
31bd204f | 3899 | |
b6ffd97f FR |
3900 | rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev); |
3901 | if (rc < 0) | |
3902 | goto err_free; | |
3903 | ||
fd112f2e FR |
3904 | rc = rtl_check_firmware(tp, rtl_fw); |
3905 | if (rc < 0) | |
3906 | goto err_release_firmware; | |
3907 | ||
b6ffd97f FR |
3908 | tp->rtl_fw = rtl_fw; |
3909 | out: | |
3910 | return; | |
3911 | ||
fd112f2e FR |
3912 | err_release_firmware: |
3913 | release_firmware(rtl_fw->fw); | |
b6ffd97f FR |
3914 | err_free: |
3915 | kfree(rtl_fw); | |
3916 | err_warn: | |
3917 | netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n", | |
3918 | name, rc); | |
3919 | out_no_firmware: | |
3920 | tp->rtl_fw = NULL; | |
3921 | goto out; | |
3922 | } | |
3923 | ||
3924 | static void rtl_request_firmware(struct rtl8169_private *tp) | |
3925 | { | |
3926 | if (IS_ERR(tp->rtl_fw)) | |
3927 | rtl_request_uncached_firmware(tp); | |
953a12cc FR |
3928 | } |
3929 | ||
1da177e4 LT |
3930 | static int rtl8169_open(struct net_device *dev) |
3931 | { | |
3932 | struct rtl8169_private *tp = netdev_priv(dev); | |
eee3a96c | 3933 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 3934 | struct pci_dev *pdev = tp->pci_dev; |
99f252b0 | 3935 | int retval = -ENOMEM; |
1da177e4 | 3936 | |
e1759441 | 3937 | pm_runtime_get_sync(&pdev->dev); |
1da177e4 | 3938 | |
1da177e4 LT |
3939 | /* |
3940 | * Rx and Tx desscriptors needs 256 bytes alignment. | |
82553bb6 | 3941 | * dma_alloc_coherent provides more. |
1da177e4 | 3942 | */ |
82553bb6 SG |
3943 | tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, |
3944 | &tp->TxPhyAddr, GFP_KERNEL); | |
1da177e4 | 3945 | if (!tp->TxDescArray) |
e1759441 | 3946 | goto err_pm_runtime_put; |
1da177e4 | 3947 | |
82553bb6 SG |
3948 | tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, |
3949 | &tp->RxPhyAddr, GFP_KERNEL); | |
1da177e4 | 3950 | if (!tp->RxDescArray) |
99f252b0 | 3951 | goto err_free_tx_0; |
1da177e4 LT |
3952 | |
3953 | retval = rtl8169_init_ring(dev); | |
3954 | if (retval < 0) | |
99f252b0 | 3955 | goto err_free_rx_1; |
1da177e4 | 3956 | |
c4028958 | 3957 | INIT_DELAYED_WORK(&tp->task, NULL); |
1da177e4 | 3958 | |
99f252b0 FR |
3959 | smp_mb(); |
3960 | ||
953a12cc FR |
3961 | rtl_request_firmware(tp); |
3962 | ||
fbac58fc FR |
3963 | retval = request_irq(dev->irq, rtl8169_interrupt, |
3964 | (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, | |
99f252b0 FR |
3965 | dev->name, dev); |
3966 | if (retval < 0) | |
953a12cc | 3967 | goto err_release_fw_2; |
99f252b0 | 3968 | |
bea3348e | 3969 | napi_enable(&tp->napi); |
bea3348e | 3970 | |
eee3a96c | 3971 | rtl8169_init_phy(dev, tp); |
3972 | ||
350fb32a | 3973 | rtl8169_set_features(dev, dev->features); |
eee3a96c | 3974 | |
065c27c1 | 3975 | rtl_pll_power_up(tp); |
3976 | ||
07ce4064 | 3977 | rtl_hw_start(dev); |
1da177e4 | 3978 | |
e1759441 RW |
3979 | tp->saved_wolopts = 0; |
3980 | pm_runtime_put_noidle(&pdev->dev); | |
3981 | ||
eee3a96c | 3982 | rtl8169_check_link_status(dev, tp, ioaddr); |
1da177e4 LT |
3983 | out: |
3984 | return retval; | |
3985 | ||
953a12cc FR |
3986 | err_release_fw_2: |
3987 | rtl_release_firmware(tp); | |
99f252b0 FR |
3988 | rtl8169_rx_clear(tp); |
3989 | err_free_rx_1: | |
82553bb6 SG |
3990 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
3991 | tp->RxPhyAddr); | |
e1759441 | 3992 | tp->RxDescArray = NULL; |
99f252b0 | 3993 | err_free_tx_0: |
82553bb6 SG |
3994 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
3995 | tp->TxPhyAddr); | |
e1759441 RW |
3996 | tp->TxDescArray = NULL; |
3997 | err_pm_runtime_put: | |
3998 | pm_runtime_put_noidle(&pdev->dev); | |
1da177e4 LT |
3999 | goto out; |
4000 | } | |
4001 | ||
92fc43b4 HW |
4002 | static void rtl_rx_close(struct rtl8169_private *tp) |
4003 | { | |
4004 | void __iomem *ioaddr = tp->mmio_addr; | |
92fc43b4 | 4005 | |
1687b566 | 4006 | RTL_W32(RxConfig, RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK); |
92fc43b4 HW |
4007 | } |
4008 | ||
e6de30d6 | 4009 | static void rtl8169_hw_reset(struct rtl8169_private *tp) |
1da177e4 | 4010 | { |
e6de30d6 | 4011 | void __iomem *ioaddr = tp->mmio_addr; |
4012 | ||
1da177e4 LT |
4013 | /* Disable interrupts */ |
4014 | rtl8169_irq_mask_and_ack(ioaddr); | |
4015 | ||
92fc43b4 HW |
4016 | rtl_rx_close(tp); |
4017 | ||
5d2e1957 | 4018 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
4804b3b3 | 4019 | tp->mac_version == RTL_GIGA_MAC_VER_28 || |
4020 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
e6de30d6 | 4021 | while (RTL_R8(TxPoll) & NPQ) |
4022 | udelay(20); | |
70090424 | 4023 | } else if (tp->mac_version == RTL_GIGA_MAC_VER_34) { |
c2b0c1e7 | 4024 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); |
70090424 HW |
4025 | while (!(RTL_R32(TxConfig) & TXCFG_EMPTY)) |
4026 | udelay(100); | |
92fc43b4 HW |
4027 | } else { |
4028 | RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq); | |
4029 | udelay(100); | |
e6de30d6 | 4030 | } |
4031 | ||
92fc43b4 | 4032 | rtl_hw_reset(tp); |
1da177e4 LT |
4033 | } |
4034 | ||
7f796d83 | 4035 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 FR |
4036 | { |
4037 | void __iomem *ioaddr = tp->mmio_addr; | |
9cb427b6 FR |
4038 | |
4039 | /* Set DMA burst size and Interframe Gap Time */ | |
4040 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
4041 | (InterFrameGap << TxInterFrameGapShift)); | |
4042 | } | |
4043 | ||
07ce4064 | 4044 | static void rtl_hw_start(struct net_device *dev) |
1da177e4 LT |
4045 | { |
4046 | struct rtl8169_private *tp = netdev_priv(dev); | |
1da177e4 | 4047 | |
07ce4064 FR |
4048 | tp->hw_start(dev); |
4049 | ||
07ce4064 FR |
4050 | netif_start_queue(dev); |
4051 | } | |
4052 | ||
7f796d83 FR |
4053 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
4054 | void __iomem *ioaddr) | |
4055 | { | |
4056 | /* | |
4057 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
4058 | * register to be written before TxDescAddrLow to work. | |
4059 | * Switching from MMIO to I/O access fixes the issue as well. | |
4060 | */ | |
4061 | RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); | |
284901a9 | 4062 | RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 | 4063 | RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
284901a9 | 4064 | RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 FR |
4065 | } |
4066 | ||
4067 | static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) | |
4068 | { | |
4069 | u16 cmd; | |
4070 | ||
4071 | cmd = RTL_R16(CPlusCmd); | |
4072 | RTL_W16(CPlusCmd, cmd); | |
4073 | return cmd; | |
4074 | } | |
4075 | ||
fdd7b4c3 | 4076 | static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
7f796d83 FR |
4077 | { |
4078 | /* Low hurts. Let's disable the filtering. */ | |
207d6e87 | 4079 | RTL_W16(RxMaxSize, rx_buf_sz + 1); |
7f796d83 FR |
4080 | } |
4081 | ||
6dccd16b FR |
4082 | static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
4083 | { | |
3744100e | 4084 | static const struct rtl_cfg2_info { |
6dccd16b FR |
4085 | u32 mac_version; |
4086 | u32 clk; | |
4087 | u32 val; | |
4088 | } cfg2_info [] = { | |
4089 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
4090 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
4091 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
4092 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
3744100e FR |
4093 | }; |
4094 | const struct rtl_cfg2_info *p = cfg2_info; | |
6dccd16b FR |
4095 | unsigned int i; |
4096 | u32 clk; | |
4097 | ||
4098 | clk = RTL_R8(Config2) & PCI_Clock_66MHz; | |
cadf1855 | 4099 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
6dccd16b FR |
4100 | if ((p->mac_version == mac_version) && (p->clk == clk)) { |
4101 | RTL_W32(0x7c, p->val); | |
4102 | break; | |
4103 | } | |
4104 | } | |
4105 | } | |
4106 | ||
07ce4064 FR |
4107 | static void rtl_hw_start_8169(struct net_device *dev) |
4108 | { | |
4109 | struct rtl8169_private *tp = netdev_priv(dev); | |
4110 | void __iomem *ioaddr = tp->mmio_addr; | |
4111 | struct pci_dev *pdev = tp->pci_dev; | |
07ce4064 | 4112 | |
9cb427b6 FR |
4113 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
4114 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); | |
4115 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
4116 | } | |
4117 | ||
1da177e4 | 4118 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
cecb5fd7 FR |
4119 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
4120 | tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
4121 | tp->mac_version == RTL_GIGA_MAC_VER_03 || | |
4122 | tp->mac_version == RTL_GIGA_MAC_VER_04) | |
9cb427b6 FR |
4123 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
4124 | ||
e542a226 HW |
4125 | rtl_init_rxcfg(tp); |
4126 | ||
f0298f81 | 4127 | RTL_W8(EarlyTxThres, NoEarlyTx); |
1da177e4 | 4128 | |
6f0333b8 | 4129 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
1da177e4 | 4130 | |
cecb5fd7 FR |
4131 | if (tp->mac_version == RTL_GIGA_MAC_VER_01 || |
4132 | tp->mac_version == RTL_GIGA_MAC_VER_02 || | |
4133 | tp->mac_version == RTL_GIGA_MAC_VER_03 || | |
4134 | tp->mac_version == RTL_GIGA_MAC_VER_04) | |
c946b304 | 4135 | rtl_set_rx_tx_config_registers(tp); |
1da177e4 | 4136 | |
7f796d83 | 4137 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
1da177e4 | 4138 | |
cecb5fd7 FR |
4139 | if (tp->mac_version == RTL_GIGA_MAC_VER_02 || |
4140 | tp->mac_version == RTL_GIGA_MAC_VER_03) { | |
06fa7358 | 4141 | dprintk("Set MAC Reg C+CR Offset 0xE0. " |
1da177e4 | 4142 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 4143 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
4144 | } |
4145 | ||
bcf0bf90 FR |
4146 | RTL_W16(CPlusCmd, tp->cp_cmd); |
4147 | ||
6dccd16b FR |
4148 | rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
4149 | ||
1da177e4 LT |
4150 | /* |
4151 | * Undocumented corner. Supposedly: | |
4152 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
4153 | */ | |
4154 | RTL_W16(IntrMitigate, 0x0000); | |
4155 | ||
7f796d83 | 4156 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
9cb427b6 | 4157 | |
cecb5fd7 FR |
4158 | if (tp->mac_version != RTL_GIGA_MAC_VER_01 && |
4159 | tp->mac_version != RTL_GIGA_MAC_VER_02 && | |
4160 | tp->mac_version != RTL_GIGA_MAC_VER_03 && | |
4161 | tp->mac_version != RTL_GIGA_MAC_VER_04) { | |
c946b304 FR |
4162 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
4163 | rtl_set_rx_tx_config_registers(tp); | |
4164 | } | |
4165 | ||
1da177e4 | 4166 | RTL_W8(Cfg9346, Cfg9346_Lock); |
b518fa8e FR |
4167 | |
4168 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
4169 | RTL_R8(IntrMask); | |
1da177e4 LT |
4170 | |
4171 | RTL_W32(RxMissed, 0); | |
4172 | ||
07ce4064 | 4173 | rtl_set_rx_mode(dev); |
1da177e4 LT |
4174 | |
4175 | /* no early-rx interrupts */ | |
4176 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | |
6dccd16b FR |
4177 | |
4178 | /* Enable all known interrupts by setting the interrupt mask. */ | |
0e485150 | 4179 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 4180 | } |
1da177e4 | 4181 | |
9c14ceaf | 4182 | static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
458a9f61 | 4183 | { |
e44daade | 4184 | int cap = pci_pcie_cap(pdev); |
9c14ceaf FR |
4185 | |
4186 | if (cap) { | |
4187 | u16 ctl; | |
458a9f61 | 4188 | |
9c14ceaf FR |
4189 | pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
4190 | ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; | |
4191 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); | |
4192 | } | |
458a9f61 FR |
4193 | } |
4194 | ||
650e8d5d | 4195 | static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits) |
dacf8154 FR |
4196 | { |
4197 | u32 csi; | |
4198 | ||
4199 | csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; | |
650e8d5d | 4200 | rtl_csi_write(ioaddr, 0x070c, csi | bits); |
4201 | } | |
4202 | ||
e6de30d6 | 4203 | static void rtl_csi_access_enable_1(void __iomem *ioaddr) |
4204 | { | |
4205 | rtl_csi_access_enable(ioaddr, 0x17000000); | |
4206 | } | |
4207 | ||
650e8d5d | 4208 | static void rtl_csi_access_enable_2(void __iomem *ioaddr) |
4209 | { | |
4210 | rtl_csi_access_enable(ioaddr, 0x27000000); | |
dacf8154 FR |
4211 | } |
4212 | ||
4213 | struct ephy_info { | |
4214 | unsigned int offset; | |
4215 | u16 mask; | |
4216 | u16 bits; | |
4217 | }; | |
4218 | ||
350f7596 | 4219 | static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len) |
dacf8154 FR |
4220 | { |
4221 | u16 w; | |
4222 | ||
4223 | while (len-- > 0) { | |
4224 | w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; | |
4225 | rtl_ephy_write(ioaddr, e->offset, w); | |
4226 | e++; | |
4227 | } | |
4228 | } | |
4229 | ||
b726e493 FR |
4230 | static void rtl_disable_clock_request(struct pci_dev *pdev) |
4231 | { | |
e44daade | 4232 | int cap = pci_pcie_cap(pdev); |
b726e493 FR |
4233 | |
4234 | if (cap) { | |
4235 | u16 ctl; | |
4236 | ||
4237 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
4238 | ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
4239 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
4240 | } | |
4241 | } | |
4242 | ||
e6de30d6 | 4243 | static void rtl_enable_clock_request(struct pci_dev *pdev) |
4244 | { | |
e44daade | 4245 | int cap = pci_pcie_cap(pdev); |
e6de30d6 | 4246 | |
4247 | if (cap) { | |
4248 | u16 ctl; | |
4249 | ||
4250 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
4251 | ctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
4252 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
4253 | } | |
4254 | } | |
4255 | ||
b726e493 FR |
4256 | #define R8168_CPCMD_QUIRK_MASK (\ |
4257 | EnableBist | \ | |
4258 | Mac_dbgo_oe | \ | |
4259 | Force_half_dup | \ | |
4260 | Force_rxflow_en | \ | |
4261 | Force_txflow_en | \ | |
4262 | Cxpl_dbg_sel | \ | |
4263 | ASF | \ | |
4264 | PktCntrDisable | \ | |
4265 | Mac_dbgo_sel) | |
4266 | ||
219a1e9d FR |
4267 | static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
4268 | { | |
b726e493 FR |
4269 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
4270 | ||
4271 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
4272 | ||
2e68ae44 FR |
4273 | rtl_tx_performance_tweak(pdev, |
4274 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
219a1e9d FR |
4275 | } |
4276 | ||
4277 | static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) | |
4278 | { | |
4279 | rtl_hw_start_8168bb(ioaddr, pdev); | |
b726e493 | 4280 | |
f0298f81 | 4281 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
b726e493 FR |
4282 | |
4283 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
219a1e9d FR |
4284 | } |
4285 | ||
4286 | static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) | |
4287 | { | |
b726e493 FR |
4288 | RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
4289 | ||
4290 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
4291 | ||
219a1e9d | 4292 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
b726e493 FR |
4293 | |
4294 | rtl_disable_clock_request(pdev); | |
4295 | ||
4296 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
219a1e9d FR |
4297 | } |
4298 | ||
ef3386f0 | 4299 | static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
219a1e9d | 4300 | { |
350f7596 | 4301 | static const struct ephy_info e_info_8168cp[] = { |
b726e493 FR |
4302 | { 0x01, 0, 0x0001 }, |
4303 | { 0x02, 0x0800, 0x1000 }, | |
4304 | { 0x03, 0, 0x0042 }, | |
4305 | { 0x06, 0x0080, 0x0000 }, | |
4306 | { 0x07, 0, 0x2000 } | |
4307 | }; | |
4308 | ||
650e8d5d | 4309 | rtl_csi_access_enable_2(ioaddr); |
b726e493 FR |
4310 | |
4311 | rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); | |
4312 | ||
219a1e9d FR |
4313 | __rtl_hw_start_8168cp(ioaddr, pdev); |
4314 | } | |
4315 | ||
ef3386f0 FR |
4316 | static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
4317 | { | |
650e8d5d | 4318 | rtl_csi_access_enable_2(ioaddr); |
ef3386f0 FR |
4319 | |
4320 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
4321 | ||
4322 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4323 | ||
4324 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
4325 | } | |
4326 | ||
7f3e3d3a FR |
4327 | static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
4328 | { | |
650e8d5d | 4329 | rtl_csi_access_enable_2(ioaddr); |
7f3e3d3a FR |
4330 | |
4331 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
4332 | ||
4333 | /* Magic. */ | |
4334 | RTL_W8(DBG_REG, 0x20); | |
4335 | ||
f0298f81 | 4336 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
7f3e3d3a FR |
4337 | |
4338 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4339 | ||
4340 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
4341 | } | |
4342 | ||
219a1e9d FR |
4343 | static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
4344 | { | |
350f7596 | 4345 | static const struct ephy_info e_info_8168c_1[] = { |
b726e493 FR |
4346 | { 0x02, 0x0800, 0x1000 }, |
4347 | { 0x03, 0, 0x0002 }, | |
4348 | { 0x06, 0x0080, 0x0000 } | |
4349 | }; | |
4350 | ||
650e8d5d | 4351 | rtl_csi_access_enable_2(ioaddr); |
b726e493 FR |
4352 | |
4353 | RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); | |
4354 | ||
4355 | rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); | |
4356 | ||
219a1e9d FR |
4357 | __rtl_hw_start_8168cp(ioaddr, pdev); |
4358 | } | |
4359 | ||
4360 | static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
4361 | { | |
350f7596 | 4362 | static const struct ephy_info e_info_8168c_2[] = { |
b726e493 FR |
4363 | { 0x01, 0, 0x0001 }, |
4364 | { 0x03, 0x0400, 0x0220 } | |
4365 | }; | |
4366 | ||
650e8d5d | 4367 | rtl_csi_access_enable_2(ioaddr); |
b726e493 FR |
4368 | |
4369 | rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); | |
4370 | ||
219a1e9d FR |
4371 | __rtl_hw_start_8168cp(ioaddr, pdev); |
4372 | } | |
4373 | ||
197ff761 FR |
4374 | static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
4375 | { | |
4376 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
4377 | } | |
4378 | ||
6fb07058 FR |
4379 | static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
4380 | { | |
650e8d5d | 4381 | rtl_csi_access_enable_2(ioaddr); |
6fb07058 FR |
4382 | |
4383 | __rtl_hw_start_8168cp(ioaddr, pdev); | |
4384 | } | |
4385 | ||
5b538df9 FR |
4386 | static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
4387 | { | |
650e8d5d | 4388 | rtl_csi_access_enable_2(ioaddr); |
5b538df9 FR |
4389 | |
4390 | rtl_disable_clock_request(pdev); | |
4391 | ||
f0298f81 | 4392 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
5b538df9 FR |
4393 | |
4394 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4395 | ||
4396 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
4397 | } | |
4398 | ||
4804b3b3 | 4399 | static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev) |
4400 | { | |
4401 | rtl_csi_access_enable_1(ioaddr); | |
4402 | ||
4403 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4404 | ||
4405 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
4406 | ||
4407 | rtl_disable_clock_request(pdev); | |
4408 | } | |
4409 | ||
e6de30d6 | 4410 | static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev) |
4411 | { | |
4412 | static const struct ephy_info e_info_8168d_4[] = { | |
4413 | { 0x0b, ~0, 0x48 }, | |
4414 | { 0x19, 0x20, 0x50 }, | |
4415 | { 0x0c, ~0, 0x20 } | |
4416 | }; | |
4417 | int i; | |
4418 | ||
4419 | rtl_csi_access_enable_1(ioaddr); | |
4420 | ||
4421 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4422 | ||
4423 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
4424 | ||
4425 | for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { | |
4426 | const struct ephy_info *e = e_info_8168d_4 + i; | |
4427 | u16 w; | |
4428 | ||
4429 | w = rtl_ephy_read(ioaddr, e->offset); | |
4430 | rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits); | |
4431 | } | |
4432 | ||
4433 | rtl_enable_clock_request(pdev); | |
4434 | } | |
4435 | ||
70090424 | 4436 | static void rtl_hw_start_8168e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
01dc7fec | 4437 | { |
70090424 | 4438 | static const struct ephy_info e_info_8168e_1[] = { |
01dc7fec | 4439 | { 0x00, 0x0200, 0x0100 }, |
4440 | { 0x00, 0x0000, 0x0004 }, | |
4441 | { 0x06, 0x0002, 0x0001 }, | |
4442 | { 0x06, 0x0000, 0x0030 }, | |
4443 | { 0x07, 0x0000, 0x2000 }, | |
4444 | { 0x00, 0x0000, 0x0020 }, | |
4445 | { 0x03, 0x5800, 0x2000 }, | |
4446 | { 0x03, 0x0000, 0x0001 }, | |
4447 | { 0x01, 0x0800, 0x1000 }, | |
4448 | { 0x07, 0x0000, 0x4000 }, | |
4449 | { 0x1e, 0x0000, 0x2000 }, | |
4450 | { 0x19, 0xffff, 0xfe6c }, | |
4451 | { 0x0a, 0x0000, 0x0040 } | |
4452 | }; | |
4453 | ||
4454 | rtl_csi_access_enable_2(ioaddr); | |
4455 | ||
70090424 | 4456 | rtl_ephy_init(ioaddr, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1)); |
01dc7fec | 4457 | |
4458 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4459 | ||
4460 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
4461 | ||
4462 | rtl_disable_clock_request(pdev); | |
4463 | ||
4464 | /* Reset tx FIFO pointer */ | |
cecb5fd7 FR |
4465 | RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST); |
4466 | RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST); | |
01dc7fec | 4467 | |
cecb5fd7 | 4468 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); |
01dc7fec | 4469 | } |
4470 | ||
70090424 HW |
4471 | static void rtl_hw_start_8168e_2(void __iomem *ioaddr, struct pci_dev *pdev) |
4472 | { | |
4473 | static const struct ephy_info e_info_8168e_2[] = { | |
4474 | { 0x09, 0x0000, 0x0080 }, | |
4475 | { 0x19, 0x0000, 0x0224 } | |
4476 | }; | |
4477 | ||
4478 | rtl_csi_access_enable_1(ioaddr); | |
4479 | ||
4480 | rtl_ephy_init(ioaddr, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2)); | |
4481 | ||
4482 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4483 | ||
4484 | rtl_eri_write(ioaddr, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
4485 | rtl_eri_write(ioaddr, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC); | |
4486 | rtl_eri_write(ioaddr, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC); | |
4487 | rtl_eri_write(ioaddr, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC); | |
4488 | rtl_eri_write(ioaddr, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC); | |
4489 | rtl_eri_write(ioaddr, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC); | |
4490 | rtl_w1w0_eri(ioaddr, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC); | |
4491 | rtl_w1w0_eri(ioaddr, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, | |
4492 | ERIAR_EXGMAC); | |
4493 | ||
4494 | RTL_W8(MaxTxPacketSize, 0x27); | |
4495 | ||
4496 | rtl_disable_clock_request(pdev); | |
4497 | ||
4498 | RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO); | |
4499 | RTL_W8(MCU, RTL_R8(MCU) & ~NOW_IS_OOB); | |
4500 | ||
4501 | /* Adjust EEE LED frequency */ | |
4502 | RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07); | |
4503 | ||
4504 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); | |
4505 | RTL_W32(MISC, RTL_R32(MISC) | PWM_EN); | |
4506 | RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en); | |
4507 | } | |
4508 | ||
07ce4064 FR |
4509 | static void rtl_hw_start_8168(struct net_device *dev) |
4510 | { | |
2dd99530 FR |
4511 | struct rtl8169_private *tp = netdev_priv(dev); |
4512 | void __iomem *ioaddr = tp->mmio_addr; | |
0e485150 | 4513 | struct pci_dev *pdev = tp->pci_dev; |
2dd99530 FR |
4514 | |
4515 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
4516 | ||
f0298f81 | 4517 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
2dd99530 | 4518 | |
6f0333b8 | 4519 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
2dd99530 | 4520 | |
0e485150 | 4521 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
2dd99530 FR |
4522 | |
4523 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
4524 | ||
0e485150 | 4525 | RTL_W16(IntrMitigate, 0x5151); |
2dd99530 | 4526 | |
0e485150 | 4527 | /* Work around for RxFIFO overflow. */ |
b5ba6d12 IV |
4528 | if (tp->mac_version == RTL_GIGA_MAC_VER_11 || |
4529 | tp->mac_version == RTL_GIGA_MAC_VER_22) { | |
0e485150 FR |
4530 | tp->intr_event |= RxFIFOOver | PCSTimeout; |
4531 | tp->intr_event &= ~RxOverflow; | |
4532 | } | |
4533 | ||
4534 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2dd99530 | 4535 | |
b8363901 FR |
4536 | rtl_set_rx_mode(dev); |
4537 | ||
4538 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
4539 | (InterFrameGap << TxInterFrameGapShift)); | |
2dd99530 FR |
4540 | |
4541 | RTL_R8(IntrMask); | |
4542 | ||
219a1e9d FR |
4543 | switch (tp->mac_version) { |
4544 | case RTL_GIGA_MAC_VER_11: | |
4545 | rtl_hw_start_8168bb(ioaddr, pdev); | |
4804b3b3 | 4546 | break; |
219a1e9d FR |
4547 | |
4548 | case RTL_GIGA_MAC_VER_12: | |
4549 | case RTL_GIGA_MAC_VER_17: | |
4550 | rtl_hw_start_8168bef(ioaddr, pdev); | |
4804b3b3 | 4551 | break; |
219a1e9d FR |
4552 | |
4553 | case RTL_GIGA_MAC_VER_18: | |
ef3386f0 | 4554 | rtl_hw_start_8168cp_1(ioaddr, pdev); |
4804b3b3 | 4555 | break; |
219a1e9d FR |
4556 | |
4557 | case RTL_GIGA_MAC_VER_19: | |
4558 | rtl_hw_start_8168c_1(ioaddr, pdev); | |
4804b3b3 | 4559 | break; |
219a1e9d FR |
4560 | |
4561 | case RTL_GIGA_MAC_VER_20: | |
4562 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
4804b3b3 | 4563 | break; |
219a1e9d | 4564 | |
197ff761 FR |
4565 | case RTL_GIGA_MAC_VER_21: |
4566 | rtl_hw_start_8168c_3(ioaddr, pdev); | |
4804b3b3 | 4567 | break; |
197ff761 | 4568 | |
6fb07058 FR |
4569 | case RTL_GIGA_MAC_VER_22: |
4570 | rtl_hw_start_8168c_4(ioaddr, pdev); | |
4804b3b3 | 4571 | break; |
6fb07058 | 4572 | |
ef3386f0 FR |
4573 | case RTL_GIGA_MAC_VER_23: |
4574 | rtl_hw_start_8168cp_2(ioaddr, pdev); | |
4804b3b3 | 4575 | break; |
ef3386f0 | 4576 | |
7f3e3d3a FR |
4577 | case RTL_GIGA_MAC_VER_24: |
4578 | rtl_hw_start_8168cp_3(ioaddr, pdev); | |
4804b3b3 | 4579 | break; |
7f3e3d3a | 4580 | |
5b538df9 | 4581 | case RTL_GIGA_MAC_VER_25: |
daf9df6d | 4582 | case RTL_GIGA_MAC_VER_26: |
4583 | case RTL_GIGA_MAC_VER_27: | |
5b538df9 | 4584 | rtl_hw_start_8168d(ioaddr, pdev); |
4804b3b3 | 4585 | break; |
5b538df9 | 4586 | |
e6de30d6 | 4587 | case RTL_GIGA_MAC_VER_28: |
4588 | rtl_hw_start_8168d_4(ioaddr, pdev); | |
4804b3b3 | 4589 | break; |
cecb5fd7 | 4590 | |
4804b3b3 | 4591 | case RTL_GIGA_MAC_VER_31: |
4592 | rtl_hw_start_8168dp(ioaddr, pdev); | |
4593 | break; | |
4594 | ||
01dc7fec | 4595 | case RTL_GIGA_MAC_VER_32: |
4596 | case RTL_GIGA_MAC_VER_33: | |
70090424 HW |
4597 | rtl_hw_start_8168e_1(ioaddr, pdev); |
4598 | break; | |
4599 | case RTL_GIGA_MAC_VER_34: | |
4600 | rtl_hw_start_8168e_2(ioaddr, pdev); | |
01dc7fec | 4601 | break; |
e6de30d6 | 4602 | |
219a1e9d FR |
4603 | default: |
4604 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | |
4605 | dev->name, tp->mac_version); | |
4804b3b3 | 4606 | break; |
219a1e9d | 4607 | } |
2dd99530 | 4608 | |
0e485150 FR |
4609 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
4610 | ||
b8363901 FR |
4611 | RTL_W8(Cfg9346, Cfg9346_Lock); |
4612 | ||
2dd99530 | 4613 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
6dccd16b | 4614 | |
0e485150 | 4615 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 4616 | } |
1da177e4 | 4617 | |
2857ffb7 FR |
4618 | #define R810X_CPCMD_QUIRK_MASK (\ |
4619 | EnableBist | \ | |
4620 | Mac_dbgo_oe | \ | |
4621 | Force_half_dup | \ | |
5edcc537 | 4622 | Force_rxflow_en | \ |
2857ffb7 FR |
4623 | Force_txflow_en | \ |
4624 | Cxpl_dbg_sel | \ | |
4625 | ASF | \ | |
4626 | PktCntrDisable | \ | |
d24e9aaf | 4627 | Mac_dbgo_sel) |
2857ffb7 FR |
4628 | |
4629 | static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) | |
4630 | { | |
350f7596 | 4631 | static const struct ephy_info e_info_8102e_1[] = { |
2857ffb7 FR |
4632 | { 0x01, 0, 0x6e65 }, |
4633 | { 0x02, 0, 0x091f }, | |
4634 | { 0x03, 0, 0xc2f9 }, | |
4635 | { 0x06, 0, 0xafb5 }, | |
4636 | { 0x07, 0, 0x0e00 }, | |
4637 | { 0x19, 0, 0xec80 }, | |
4638 | { 0x01, 0, 0x2e65 }, | |
4639 | { 0x01, 0, 0x6e65 } | |
4640 | }; | |
4641 | u8 cfg1; | |
4642 | ||
650e8d5d | 4643 | rtl_csi_access_enable_2(ioaddr); |
2857ffb7 FR |
4644 | |
4645 | RTL_W8(DBG_REG, FIX_NAK_1); | |
4646 | ||
4647 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4648 | ||
4649 | RTL_W8(Config1, | |
4650 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); | |
4651 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
4652 | ||
4653 | cfg1 = RTL_R8(Config1); | |
4654 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) | |
4655 | RTL_W8(Config1, cfg1 & ~LEDS0); | |
4656 | ||
2857ffb7 FR |
4657 | rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
4658 | } | |
4659 | ||
4660 | static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
4661 | { | |
650e8d5d | 4662 | rtl_csi_access_enable_2(ioaddr); |
2857ffb7 FR |
4663 | |
4664 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4665 | ||
4666 | RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); | |
4667 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2857ffb7 FR |
4668 | } |
4669 | ||
4670 | static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) | |
4671 | { | |
4672 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
4673 | ||
4674 | rtl_ephy_write(ioaddr, 0x03, 0xc2f9); | |
4675 | } | |
4676 | ||
5a5e4443 HW |
4677 | static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
4678 | { | |
4679 | static const struct ephy_info e_info_8105e_1[] = { | |
4680 | { 0x07, 0, 0x4000 }, | |
4681 | { 0x19, 0, 0x0200 }, | |
4682 | { 0x19, 0, 0x0020 }, | |
4683 | { 0x1e, 0, 0x2000 }, | |
4684 | { 0x03, 0, 0x0001 }, | |
4685 | { 0x19, 0, 0x0100 }, | |
4686 | { 0x19, 0, 0x0004 }, | |
4687 | { 0x0a, 0, 0x0020 } | |
4688 | }; | |
4689 | ||
cecb5fd7 | 4690 | /* Force LAN exit from ASPM if Rx/Tx are not idle */ |
5a5e4443 HW |
4691 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); |
4692 | ||
cecb5fd7 | 4693 | /* Disable Early Tally Counter */ |
5a5e4443 HW |
4694 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); |
4695 | ||
4696 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); | |
4f6b00e5 | 4697 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PFM_EN); |
5a5e4443 HW |
4698 | |
4699 | rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); | |
4700 | } | |
4701 | ||
4702 | static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
4703 | { | |
4704 | rtl_hw_start_8105e_1(ioaddr, pdev); | |
4705 | rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000); | |
4706 | } | |
4707 | ||
07ce4064 FR |
4708 | static void rtl_hw_start_8101(struct net_device *dev) |
4709 | { | |
cdf1a608 FR |
4710 | struct rtl8169_private *tp = netdev_priv(dev); |
4711 | void __iomem *ioaddr = tp->mmio_addr; | |
4712 | struct pci_dev *pdev = tp->pci_dev; | |
4713 | ||
cecb5fd7 FR |
4714 | if (tp->mac_version == RTL_GIGA_MAC_VER_13 || |
4715 | tp->mac_version == RTL_GIGA_MAC_VER_16) { | |
e44daade | 4716 | int cap = pci_pcie_cap(pdev); |
9c14ceaf FR |
4717 | |
4718 | if (cap) { | |
4719 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, | |
4720 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
4721 | } | |
cdf1a608 FR |
4722 | } |
4723 | ||
d24e9aaf HW |
4724 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
4725 | ||
2857ffb7 FR |
4726 | switch (tp->mac_version) { |
4727 | case RTL_GIGA_MAC_VER_07: | |
4728 | rtl_hw_start_8102e_1(ioaddr, pdev); | |
4729 | break; | |
4730 | ||
4731 | case RTL_GIGA_MAC_VER_08: | |
4732 | rtl_hw_start_8102e_3(ioaddr, pdev); | |
4733 | break; | |
4734 | ||
4735 | case RTL_GIGA_MAC_VER_09: | |
4736 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
4737 | break; | |
5a5e4443 HW |
4738 | |
4739 | case RTL_GIGA_MAC_VER_29: | |
4740 | rtl_hw_start_8105e_1(ioaddr, pdev); | |
4741 | break; | |
4742 | case RTL_GIGA_MAC_VER_30: | |
4743 | rtl_hw_start_8105e_2(ioaddr, pdev); | |
4744 | break; | |
cdf1a608 FR |
4745 | } |
4746 | ||
d24e9aaf | 4747 | RTL_W8(Cfg9346, Cfg9346_Lock); |
cdf1a608 | 4748 | |
f0298f81 | 4749 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
cdf1a608 | 4750 | |
6f0333b8 | 4751 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
cdf1a608 | 4752 | |
d24e9aaf | 4753 | tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; |
cdf1a608 FR |
4754 | RTL_W16(CPlusCmd, tp->cp_cmd); |
4755 | ||
4756 | RTL_W16(IntrMitigate, 0x0000); | |
4757 | ||
4758 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
4759 | ||
4760 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
4761 | rtl_set_rx_tx_config_registers(tp); | |
4762 | ||
cdf1a608 FR |
4763 | RTL_R8(IntrMask); |
4764 | ||
cdf1a608 FR |
4765 | rtl_set_rx_mode(dev); |
4766 | ||
4767 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); | |
6dccd16b | 4768 | |
0e485150 | 4769 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
4770 | } |
4771 | ||
4772 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
4773 | { | |
1da177e4 LT |
4774 | if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) |
4775 | return -EINVAL; | |
4776 | ||
4777 | dev->mtu = new_mtu; | |
350fb32a MM |
4778 | netdev_update_features(dev); |
4779 | ||
323bb685 | 4780 | return 0; |
1da177e4 LT |
4781 | } |
4782 | ||
4783 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
4784 | { | |
95e0918d | 4785 | desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
1da177e4 LT |
4786 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
4787 | } | |
4788 | ||
6f0333b8 ED |
4789 | static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
4790 | void **data_buff, struct RxDesc *desc) | |
1da177e4 | 4791 | { |
48addcc9 | 4792 | dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
231aee63 | 4793 | DMA_FROM_DEVICE); |
48addcc9 | 4794 | |
6f0333b8 ED |
4795 | kfree(*data_buff); |
4796 | *data_buff = NULL; | |
1da177e4 LT |
4797 | rtl8169_make_unusable_by_asic(desc); |
4798 | } | |
4799 | ||
4800 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) | |
4801 | { | |
4802 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
4803 | ||
4804 | desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); | |
4805 | } | |
4806 | ||
4807 | static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, | |
4808 | u32 rx_buf_sz) | |
4809 | { | |
4810 | desc->addr = cpu_to_le64(mapping); | |
4811 | wmb(); | |
4812 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
4813 | } | |
4814 | ||
6f0333b8 ED |
4815 | static inline void *rtl8169_align(void *data) |
4816 | { | |
4817 | return (void *)ALIGN((long)data, 16); | |
4818 | } | |
4819 | ||
0ecbe1ca SG |
4820 | static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
4821 | struct RxDesc *desc) | |
1da177e4 | 4822 | { |
6f0333b8 | 4823 | void *data; |
1da177e4 | 4824 | dma_addr_t mapping; |
48addcc9 | 4825 | struct device *d = &tp->pci_dev->dev; |
0ecbe1ca | 4826 | struct net_device *dev = tp->dev; |
6f0333b8 | 4827 | int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
1da177e4 | 4828 | |
6f0333b8 ED |
4829 | data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
4830 | if (!data) | |
4831 | return NULL; | |
e9f63f30 | 4832 | |
6f0333b8 ED |
4833 | if (rtl8169_align(data) != data) { |
4834 | kfree(data); | |
4835 | data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); | |
4836 | if (!data) | |
4837 | return NULL; | |
4838 | } | |
3eafe507 | 4839 | |
48addcc9 | 4840 | mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
231aee63 | 4841 | DMA_FROM_DEVICE); |
d827d86b SG |
4842 | if (unlikely(dma_mapping_error(d, mapping))) { |
4843 | if (net_ratelimit()) | |
4844 | netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); | |
3eafe507 | 4845 | goto err_out; |
d827d86b | 4846 | } |
1da177e4 LT |
4847 | |
4848 | rtl8169_map_to_asic(desc, mapping, rx_buf_sz); | |
6f0333b8 | 4849 | return data; |
3eafe507 SG |
4850 | |
4851 | err_out: | |
4852 | kfree(data); | |
4853 | return NULL; | |
1da177e4 LT |
4854 | } |
4855 | ||
4856 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
4857 | { | |
07d3f51f | 4858 | unsigned int i; |
1da177e4 LT |
4859 | |
4860 | for (i = 0; i < NUM_RX_DESC; i++) { | |
6f0333b8 ED |
4861 | if (tp->Rx_databuff[i]) { |
4862 | rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, | |
1da177e4 LT |
4863 | tp->RxDescArray + i); |
4864 | } | |
4865 | } | |
4866 | } | |
4867 | ||
0ecbe1ca | 4868 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
1da177e4 | 4869 | { |
0ecbe1ca SG |
4870 | desc->opts1 |= cpu_to_le32(RingEnd); |
4871 | } | |
5b0384f4 | 4872 | |
0ecbe1ca SG |
4873 | static int rtl8169_rx_fill(struct rtl8169_private *tp) |
4874 | { | |
4875 | unsigned int i; | |
1da177e4 | 4876 | |
0ecbe1ca SG |
4877 | for (i = 0; i < NUM_RX_DESC; i++) { |
4878 | void *data; | |
4ae47c2d | 4879 | |
6f0333b8 | 4880 | if (tp->Rx_databuff[i]) |
1da177e4 | 4881 | continue; |
bcf0bf90 | 4882 | |
0ecbe1ca | 4883 | data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
6f0333b8 ED |
4884 | if (!data) { |
4885 | rtl8169_make_unusable_by_asic(tp->RxDescArray + i); | |
0ecbe1ca | 4886 | goto err_out; |
6f0333b8 ED |
4887 | } |
4888 | tp->Rx_databuff[i] = data; | |
1da177e4 | 4889 | } |
1da177e4 | 4890 | |
0ecbe1ca SG |
4891 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
4892 | return 0; | |
4893 | ||
4894 | err_out: | |
4895 | rtl8169_rx_clear(tp); | |
4896 | return -ENOMEM; | |
1da177e4 LT |
4897 | } |
4898 | ||
1da177e4 LT |
4899 | static int rtl8169_init_ring(struct net_device *dev) |
4900 | { | |
4901 | struct rtl8169_private *tp = netdev_priv(dev); | |
4902 | ||
4903 | rtl8169_init_ring_indexes(tp); | |
4904 | ||
4905 | memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); | |
6f0333b8 | 4906 | memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
1da177e4 | 4907 | |
0ecbe1ca | 4908 | return rtl8169_rx_fill(tp); |
1da177e4 LT |
4909 | } |
4910 | ||
48addcc9 | 4911 | static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
1da177e4 LT |
4912 | struct TxDesc *desc) |
4913 | { | |
4914 | unsigned int len = tx_skb->len; | |
4915 | ||
48addcc9 SG |
4916 | dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
4917 | ||
1da177e4 LT |
4918 | desc->opts1 = 0x00; |
4919 | desc->opts2 = 0x00; | |
4920 | desc->addr = 0x00; | |
4921 | tx_skb->len = 0; | |
4922 | } | |
4923 | ||
3eafe507 SG |
4924 | static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
4925 | unsigned int n) | |
1da177e4 LT |
4926 | { |
4927 | unsigned int i; | |
4928 | ||
3eafe507 SG |
4929 | for (i = 0; i < n; i++) { |
4930 | unsigned int entry = (start + i) % NUM_TX_DESC; | |
1da177e4 LT |
4931 | struct ring_info *tx_skb = tp->tx_skb + entry; |
4932 | unsigned int len = tx_skb->len; | |
4933 | ||
4934 | if (len) { | |
4935 | struct sk_buff *skb = tx_skb->skb; | |
4936 | ||
48addcc9 | 4937 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
1da177e4 LT |
4938 | tp->TxDescArray + entry); |
4939 | if (skb) { | |
cac4b22f | 4940 | tp->dev->stats.tx_dropped++; |
1da177e4 LT |
4941 | dev_kfree_skb(skb); |
4942 | tx_skb->skb = NULL; | |
4943 | } | |
1da177e4 LT |
4944 | } |
4945 | } | |
3eafe507 SG |
4946 | } |
4947 | ||
4948 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
4949 | { | |
4950 | rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); | |
1da177e4 LT |
4951 | tp->cur_tx = tp->dirty_tx = 0; |
4952 | } | |
4953 | ||
c4028958 | 4954 | static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
1da177e4 LT |
4955 | { |
4956 | struct rtl8169_private *tp = netdev_priv(dev); | |
4957 | ||
c4028958 | 4958 | PREPARE_DELAYED_WORK(&tp->task, task); |
1da177e4 LT |
4959 | schedule_delayed_work(&tp->task, 4); |
4960 | } | |
4961 | ||
4962 | static void rtl8169_wait_for_quiescence(struct net_device *dev) | |
4963 | { | |
4964 | struct rtl8169_private *tp = netdev_priv(dev); | |
4965 | void __iomem *ioaddr = tp->mmio_addr; | |
4966 | ||
4967 | synchronize_irq(dev->irq); | |
4968 | ||
4969 | /* Wait for any pending NAPI task to complete */ | |
bea3348e | 4970 | napi_disable(&tp->napi); |
1da177e4 LT |
4971 | |
4972 | rtl8169_irq_mask_and_ack(ioaddr); | |
4973 | ||
d1d08d12 DM |
4974 | tp->intr_mask = 0xffff; |
4975 | RTL_W16(IntrMask, tp->intr_event); | |
bea3348e | 4976 | napi_enable(&tp->napi); |
1da177e4 LT |
4977 | } |
4978 | ||
c4028958 | 4979 | static void rtl8169_reinit_task(struct work_struct *work) |
1da177e4 | 4980 | { |
c4028958 DH |
4981 | struct rtl8169_private *tp = |
4982 | container_of(work, struct rtl8169_private, task.work); | |
4983 | struct net_device *dev = tp->dev; | |
1da177e4 LT |
4984 | int ret; |
4985 | ||
eb2a021c FR |
4986 | rtnl_lock(); |
4987 | ||
4988 | if (!netif_running(dev)) | |
4989 | goto out_unlock; | |
4990 | ||
4991 | rtl8169_wait_for_quiescence(dev); | |
4992 | rtl8169_close(dev); | |
1da177e4 LT |
4993 | |
4994 | ret = rtl8169_open(dev); | |
4995 | if (unlikely(ret < 0)) { | |
bf82c189 JP |
4996 | if (net_ratelimit()) |
4997 | netif_err(tp, drv, dev, | |
4998 | "reinit failure (status = %d). Rescheduling\n", | |
4999 | ret); | |
1da177e4 LT |
5000 | rtl8169_schedule_work(dev, rtl8169_reinit_task); |
5001 | } | |
eb2a021c FR |
5002 | |
5003 | out_unlock: | |
5004 | rtnl_unlock(); | |
1da177e4 LT |
5005 | } |
5006 | ||
c4028958 | 5007 | static void rtl8169_reset_task(struct work_struct *work) |
1da177e4 | 5008 | { |
c4028958 DH |
5009 | struct rtl8169_private *tp = |
5010 | container_of(work, struct rtl8169_private, task.work); | |
5011 | struct net_device *dev = tp->dev; | |
56de414c | 5012 | int i; |
1da177e4 | 5013 | |
eb2a021c FR |
5014 | rtnl_lock(); |
5015 | ||
1da177e4 | 5016 | if (!netif_running(dev)) |
eb2a021c | 5017 | goto out_unlock; |
1da177e4 LT |
5018 | |
5019 | rtl8169_wait_for_quiescence(dev); | |
5020 | ||
56de414c FR |
5021 | for (i = 0; i < NUM_RX_DESC; i++) |
5022 | rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz); | |
5023 | ||
1da177e4 LT |
5024 | rtl8169_tx_clear(tp); |
5025 | ||
92fc43b4 | 5026 | rtl8169_hw_reset(tp); |
56de414c FR |
5027 | rtl_hw_start(dev); |
5028 | netif_wake_queue(dev); | |
5029 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); | |
eb2a021c FR |
5030 | |
5031 | out_unlock: | |
5032 | rtnl_unlock(); | |
1da177e4 LT |
5033 | } |
5034 | ||
5035 | static void rtl8169_tx_timeout(struct net_device *dev) | |
5036 | { | |
5037 | struct rtl8169_private *tp = netdev_priv(dev); | |
5038 | ||
e6de30d6 | 5039 | rtl8169_hw_reset(tp); |
1da177e4 LT |
5040 | |
5041 | /* Let's wait a bit while any (async) irq lands on */ | |
5042 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
5043 | } | |
5044 | ||
5045 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
2b7b4318 | 5046 | u32 *opts) |
1da177e4 LT |
5047 | { |
5048 | struct skb_shared_info *info = skb_shinfo(skb); | |
5049 | unsigned int cur_frag, entry; | |
a6343afb | 5050 | struct TxDesc * uninitialized_var(txd); |
48addcc9 | 5051 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
5052 | |
5053 | entry = tp->cur_tx; | |
5054 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
5055 | skb_frag_t *frag = info->frags + cur_frag; | |
5056 | dma_addr_t mapping; | |
5057 | u32 status, len; | |
5058 | void *addr; | |
5059 | ||
5060 | entry = (entry + 1) % NUM_TX_DESC; | |
5061 | ||
5062 | txd = tp->TxDescArray + entry; | |
5063 | len = frag->size; | |
5064 | addr = ((void *) page_address(frag->page)) + frag->page_offset; | |
48addcc9 | 5065 | mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
d827d86b SG |
5066 | if (unlikely(dma_mapping_error(d, mapping))) { |
5067 | if (net_ratelimit()) | |
5068 | netif_err(tp, drv, tp->dev, | |
5069 | "Failed to map TX fragments DMA!\n"); | |
3eafe507 | 5070 | goto err_out; |
d827d86b | 5071 | } |
1da177e4 | 5072 | |
cecb5fd7 | 5073 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 FR |
5074 | status = opts[0] | len | |
5075 | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
1da177e4 LT |
5076 | |
5077 | txd->opts1 = cpu_to_le32(status); | |
2b7b4318 | 5078 | txd->opts2 = cpu_to_le32(opts[1]); |
1da177e4 LT |
5079 | txd->addr = cpu_to_le64(mapping); |
5080 | ||
5081 | tp->tx_skb[entry].len = len; | |
5082 | } | |
5083 | ||
5084 | if (cur_frag) { | |
5085 | tp->tx_skb[entry].skb = skb; | |
5086 | txd->opts1 |= cpu_to_le32(LastFrag); | |
5087 | } | |
5088 | ||
5089 | return cur_frag; | |
3eafe507 SG |
5090 | |
5091 | err_out: | |
5092 | rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); | |
5093 | return -EIO; | |
1da177e4 LT |
5094 | } |
5095 | ||
2b7b4318 FR |
5096 | static inline void rtl8169_tso_csum(struct rtl8169_private *tp, |
5097 | struct sk_buff *skb, u32 *opts) | |
1da177e4 | 5098 | { |
2b7b4318 | 5099 | const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version; |
350fb32a | 5100 | u32 mss = skb_shinfo(skb)->gso_size; |
2b7b4318 | 5101 | int offset = info->opts_offset; |
350fb32a | 5102 | |
2b7b4318 FR |
5103 | if (mss) { |
5104 | opts[0] |= TD_LSO; | |
5105 | opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift; | |
5106 | } else if (skb->ip_summed == CHECKSUM_PARTIAL) { | |
eddc9ec5 | 5107 | const struct iphdr *ip = ip_hdr(skb); |
1da177e4 LT |
5108 | |
5109 | if (ip->protocol == IPPROTO_TCP) | |
2b7b4318 | 5110 | opts[offset] |= info->checksum.tcp; |
1da177e4 | 5111 | else if (ip->protocol == IPPROTO_UDP) |
2b7b4318 FR |
5112 | opts[offset] |= info->checksum.udp; |
5113 | else | |
5114 | WARN_ON_ONCE(1); | |
1da177e4 | 5115 | } |
1da177e4 LT |
5116 | } |
5117 | ||
61357325 SH |
5118 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
5119 | struct net_device *dev) | |
1da177e4 LT |
5120 | { |
5121 | struct rtl8169_private *tp = netdev_priv(dev); | |
3eafe507 | 5122 | unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
1da177e4 LT |
5123 | struct TxDesc *txd = tp->TxDescArray + entry; |
5124 | void __iomem *ioaddr = tp->mmio_addr; | |
48addcc9 | 5125 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
5126 | dma_addr_t mapping; |
5127 | u32 status, len; | |
2b7b4318 | 5128 | u32 opts[2]; |
3eafe507 | 5129 | int frags; |
5b0384f4 | 5130 | |
1da177e4 | 5131 | if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
bf82c189 | 5132 | netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
3eafe507 | 5133 | goto err_stop_0; |
1da177e4 LT |
5134 | } |
5135 | ||
5136 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
3eafe507 SG |
5137 | goto err_stop_0; |
5138 | ||
5139 | len = skb_headlen(skb); | |
48addcc9 | 5140 | mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
d827d86b SG |
5141 | if (unlikely(dma_mapping_error(d, mapping))) { |
5142 | if (net_ratelimit()) | |
5143 | netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); | |
3eafe507 | 5144 | goto err_dma_0; |
d827d86b | 5145 | } |
3eafe507 SG |
5146 | |
5147 | tp->tx_skb[entry].len = len; | |
5148 | txd->addr = cpu_to_le64(mapping); | |
1da177e4 | 5149 | |
2b7b4318 FR |
5150 | opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); |
5151 | opts[0] = DescOwn; | |
1da177e4 | 5152 | |
2b7b4318 FR |
5153 | rtl8169_tso_csum(tp, skb, opts); |
5154 | ||
5155 | frags = rtl8169_xmit_frags(tp, skb, opts); | |
3eafe507 SG |
5156 | if (frags < 0) |
5157 | goto err_dma_1; | |
5158 | else if (frags) | |
2b7b4318 | 5159 | opts[0] |= FirstFrag; |
3eafe507 | 5160 | else { |
2b7b4318 | 5161 | opts[0] |= FirstFrag | LastFrag; |
1da177e4 LT |
5162 | tp->tx_skb[entry].skb = skb; |
5163 | } | |
5164 | ||
2b7b4318 FR |
5165 | txd->opts2 = cpu_to_le32(opts[1]); |
5166 | ||
1da177e4 LT |
5167 | wmb(); |
5168 | ||
cecb5fd7 | 5169 | /* Anti gcc 2.95.3 bugware (sic) */ |
2b7b4318 | 5170 | status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); |
1da177e4 LT |
5171 | txd->opts1 = cpu_to_le32(status); |
5172 | ||
1da177e4 LT |
5173 | tp->cur_tx += frags + 1; |
5174 | ||
4c020a96 | 5175 | wmb(); |
1da177e4 | 5176 | |
cecb5fd7 | 5177 | RTL_W8(TxPoll, NPQ); |
1da177e4 LT |
5178 | |
5179 | if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { | |
5180 | netif_stop_queue(dev); | |
5181 | smp_rmb(); | |
5182 | if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) | |
5183 | netif_wake_queue(dev); | |
5184 | } | |
5185 | ||
61357325 | 5186 | return NETDEV_TX_OK; |
1da177e4 | 5187 | |
3eafe507 | 5188 | err_dma_1: |
48addcc9 | 5189 | rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
3eafe507 SG |
5190 | err_dma_0: |
5191 | dev_kfree_skb(skb); | |
5192 | dev->stats.tx_dropped++; | |
5193 | return NETDEV_TX_OK; | |
5194 | ||
5195 | err_stop_0: | |
1da177e4 | 5196 | netif_stop_queue(dev); |
cebf8cc7 | 5197 | dev->stats.tx_dropped++; |
61357325 | 5198 | return NETDEV_TX_BUSY; |
1da177e4 LT |
5199 | } |
5200 | ||
5201 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
5202 | { | |
5203 | struct rtl8169_private *tp = netdev_priv(dev); | |
5204 | struct pci_dev *pdev = tp->pci_dev; | |
1da177e4 LT |
5205 | u16 pci_status, pci_cmd; |
5206 | ||
5207 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
5208 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
5209 | ||
bf82c189 JP |
5210 | netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
5211 | pci_cmd, pci_status); | |
1da177e4 LT |
5212 | |
5213 | /* | |
5214 | * The recovery sequence below admits a very elaborated explanation: | |
5215 | * - it seems to work; | |
d03902b8 FR |
5216 | * - I did not see what else could be done; |
5217 | * - it makes iop3xx happy. | |
1da177e4 LT |
5218 | * |
5219 | * Feel free to adjust to your needs. | |
5220 | */ | |
a27993f3 | 5221 | if (pdev->broken_parity_status) |
d03902b8 FR |
5222 | pci_cmd &= ~PCI_COMMAND_PARITY; |
5223 | else | |
5224 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
5225 | ||
5226 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
5227 | |
5228 | pci_write_config_word(pdev, PCI_STATUS, | |
5229 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
5230 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
5231 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
5232 | ||
5233 | /* The infamous DAC f*ckup only happens at boot time */ | |
5234 | if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { | |
e6de30d6 | 5235 | void __iomem *ioaddr = tp->mmio_addr; |
5236 | ||
bf82c189 | 5237 | netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
1da177e4 LT |
5238 | tp->cp_cmd &= ~PCIDAC; |
5239 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
5240 | dev->features &= ~NETIF_F_HIGHDMA; | |
1da177e4 LT |
5241 | } |
5242 | ||
e6de30d6 | 5243 | rtl8169_hw_reset(tp); |
d03902b8 FR |
5244 | |
5245 | rtl8169_schedule_work(dev, rtl8169_reinit_task); | |
1da177e4 LT |
5246 | } |
5247 | ||
07d3f51f FR |
5248 | static void rtl8169_tx_interrupt(struct net_device *dev, |
5249 | struct rtl8169_private *tp, | |
5250 | void __iomem *ioaddr) | |
1da177e4 LT |
5251 | { |
5252 | unsigned int dirty_tx, tx_left; | |
5253 | ||
1da177e4 LT |
5254 | dirty_tx = tp->dirty_tx; |
5255 | smp_rmb(); | |
5256 | tx_left = tp->cur_tx - dirty_tx; | |
5257 | ||
5258 | while (tx_left > 0) { | |
5259 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
5260 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
1da177e4 LT |
5261 | u32 status; |
5262 | ||
5263 | rmb(); | |
5264 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); | |
5265 | if (status & DescOwn) | |
5266 | break; | |
5267 | ||
48addcc9 SG |
5268 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
5269 | tp->TxDescArray + entry); | |
1da177e4 | 5270 | if (status & LastFrag) { |
cac4b22f SG |
5271 | dev->stats.tx_packets++; |
5272 | dev->stats.tx_bytes += tx_skb->skb->len; | |
87433bfc | 5273 | dev_kfree_skb(tx_skb->skb); |
1da177e4 LT |
5274 | tx_skb->skb = NULL; |
5275 | } | |
5276 | dirty_tx++; | |
5277 | tx_left--; | |
5278 | } | |
5279 | ||
5280 | if (tp->dirty_tx != dirty_tx) { | |
5281 | tp->dirty_tx = dirty_tx; | |
5282 | smp_wmb(); | |
5283 | if (netif_queue_stopped(dev) && | |
5284 | (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { | |
5285 | netif_wake_queue(dev); | |
5286 | } | |
d78ae2dc FR |
5287 | /* |
5288 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
5289 | * too close. Let's kick an extra TxPoll request when a burst | |
5290 | * of start_xmit activity is detected (if it is not detected, | |
5291 | * it is slow enough). -- FR | |
5292 | */ | |
5293 | smp_rmb(); | |
5294 | if (tp->cur_tx != dirty_tx) | |
5295 | RTL_W8(TxPoll, NPQ); | |
1da177e4 LT |
5296 | } |
5297 | } | |
5298 | ||
126fa4b9 FR |
5299 | static inline int rtl8169_fragmented_frame(u32 status) |
5300 | { | |
5301 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
5302 | } | |
5303 | ||
adea1ac7 | 5304 | static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
1da177e4 | 5305 | { |
1da177e4 LT |
5306 | u32 status = opts1 & RxProtoMask; |
5307 | ||
5308 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
d5d3ebe3 | 5309 | ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
1da177e4 LT |
5310 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
5311 | else | |
bc8acf2c | 5312 | skb_checksum_none_assert(skb); |
1da177e4 LT |
5313 | } |
5314 | ||
6f0333b8 ED |
5315 | static struct sk_buff *rtl8169_try_rx_copy(void *data, |
5316 | struct rtl8169_private *tp, | |
5317 | int pkt_size, | |
5318 | dma_addr_t addr) | |
1da177e4 | 5319 | { |
b449655f | 5320 | struct sk_buff *skb; |
48addcc9 | 5321 | struct device *d = &tp->pci_dev->dev; |
b449655f | 5322 | |
6f0333b8 | 5323 | data = rtl8169_align(data); |
48addcc9 | 5324 | dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
6f0333b8 ED |
5325 | prefetch(data); |
5326 | skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); | |
5327 | if (skb) | |
5328 | memcpy(skb->data, data, pkt_size); | |
48addcc9 SG |
5329 | dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
5330 | ||
6f0333b8 | 5331 | return skb; |
1da177e4 LT |
5332 | } |
5333 | ||
07d3f51f FR |
5334 | static int rtl8169_rx_interrupt(struct net_device *dev, |
5335 | struct rtl8169_private *tp, | |
bea3348e | 5336 | void __iomem *ioaddr, u32 budget) |
1da177e4 LT |
5337 | { |
5338 | unsigned int cur_rx, rx_left; | |
6f0333b8 | 5339 | unsigned int count; |
1da177e4 | 5340 | |
1da177e4 LT |
5341 | cur_rx = tp->cur_rx; |
5342 | rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; | |
865c652d | 5343 | rx_left = min(rx_left, budget); |
1da177e4 | 5344 | |
4dcb7d33 | 5345 | for (; rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 5346 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 5347 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
5348 | u32 status; |
5349 | ||
5350 | rmb(); | |
e03f33af | 5351 | status = le32_to_cpu(desc->opts1) & tp->opts1_mask; |
1da177e4 LT |
5352 | |
5353 | if (status & DescOwn) | |
5354 | break; | |
4dcb7d33 | 5355 | if (unlikely(status & RxRES)) { |
bf82c189 JP |
5356 | netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
5357 | status); | |
cebf8cc7 | 5358 | dev->stats.rx_errors++; |
1da177e4 | 5359 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 5360 | dev->stats.rx_length_errors++; |
1da177e4 | 5361 | if (status & RxCRC) |
cebf8cc7 | 5362 | dev->stats.rx_crc_errors++; |
9dccf611 FR |
5363 | if (status & RxFOVF) { |
5364 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
cebf8cc7 | 5365 | dev->stats.rx_fifo_errors++; |
9dccf611 | 5366 | } |
6f0333b8 | 5367 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
1da177e4 | 5368 | } else { |
6f0333b8 | 5369 | struct sk_buff *skb; |
b449655f | 5370 | dma_addr_t addr = le64_to_cpu(desc->addr); |
1da177e4 | 5371 | int pkt_size = (status & 0x00001FFF) - 4; |
1da177e4 | 5372 | |
126fa4b9 FR |
5373 | /* |
5374 | * The driver does not support incoming fragmented | |
5375 | * frames. They are seen as a symptom of over-mtu | |
5376 | * sized frames. | |
5377 | */ | |
5378 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
5379 | dev->stats.rx_dropped++; |
5380 | dev->stats.rx_length_errors++; | |
6f0333b8 | 5381 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
4dcb7d33 | 5382 | continue; |
126fa4b9 FR |
5383 | } |
5384 | ||
6f0333b8 ED |
5385 | skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
5386 | tp, pkt_size, addr); | |
5387 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
5388 | if (!skb) { | |
5389 | dev->stats.rx_dropped++; | |
5390 | continue; | |
1da177e4 LT |
5391 | } |
5392 | ||
adea1ac7 | 5393 | rtl8169_rx_csum(skb, status); |
1da177e4 LT |
5394 | skb_put(skb, pkt_size); |
5395 | skb->protocol = eth_type_trans(skb, dev); | |
5396 | ||
7a8fc77b FR |
5397 | rtl8169_rx_vlan_tag(desc, skb); |
5398 | ||
56de414c | 5399 | napi_gro_receive(&tp->napi, skb); |
1da177e4 | 5400 | |
cebf8cc7 FR |
5401 | dev->stats.rx_bytes += pkt_size; |
5402 | dev->stats.rx_packets++; | |
1da177e4 | 5403 | } |
6dccd16b FR |
5404 | |
5405 | /* Work around for AMD plateform. */ | |
95e0918d | 5406 | if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
6dccd16b FR |
5407 | (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
5408 | desc->opts2 = 0; | |
5409 | cur_rx++; | |
5410 | } | |
1da177e4 LT |
5411 | } |
5412 | ||
5413 | count = cur_rx - tp->cur_rx; | |
5414 | tp->cur_rx = cur_rx; | |
5415 | ||
6f0333b8 | 5416 | tp->dirty_rx += count; |
1da177e4 LT |
5417 | |
5418 | return count; | |
5419 | } | |
5420 | ||
07d3f51f | 5421 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 5422 | { |
07d3f51f | 5423 | struct net_device *dev = dev_instance; |
1da177e4 | 5424 | struct rtl8169_private *tp = netdev_priv(dev); |
1da177e4 | 5425 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 5426 | int handled = 0; |
865c652d | 5427 | int status; |
1da177e4 | 5428 | |
f11a377b DD |
5429 | /* loop handling interrupts until we have no new ones or |
5430 | * we hit a invalid/hotplug case. | |
5431 | */ | |
865c652d | 5432 | status = RTL_R16(IntrStatus); |
f11a377b DD |
5433 | while (status && status != 0xffff) { |
5434 | handled = 1; | |
1da177e4 | 5435 | |
f11a377b DD |
5436 | /* Handle all of the error cases first. These will reset |
5437 | * the chip, so just exit the loop. | |
5438 | */ | |
5439 | if (unlikely(!netif_running(dev))) { | |
92fc43b4 | 5440 | rtl8169_hw_reset(tp); |
f11a377b DD |
5441 | break; |
5442 | } | |
1da177e4 | 5443 | |
1519e57f FR |
5444 | if (unlikely(status & RxFIFOOver)) { |
5445 | switch (tp->mac_version) { | |
5446 | /* Work around for rx fifo overflow */ | |
5447 | case RTL_GIGA_MAC_VER_11: | |
5448 | case RTL_GIGA_MAC_VER_22: | |
5449 | case RTL_GIGA_MAC_VER_26: | |
5450 | netif_stop_queue(dev); | |
5451 | rtl8169_tx_timeout(dev); | |
5452 | goto done; | |
f60ac8e7 FR |
5453 | /* Testers needed. */ |
5454 | case RTL_GIGA_MAC_VER_17: | |
5455 | case RTL_GIGA_MAC_VER_19: | |
5456 | case RTL_GIGA_MAC_VER_20: | |
5457 | case RTL_GIGA_MAC_VER_21: | |
5458 | case RTL_GIGA_MAC_VER_23: | |
5459 | case RTL_GIGA_MAC_VER_24: | |
5460 | case RTL_GIGA_MAC_VER_27: | |
5461 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 5462 | case RTL_GIGA_MAC_VER_31: |
1519e57f FR |
5463 | /* Experimental science. Pktgen proof. */ |
5464 | case RTL_GIGA_MAC_VER_12: | |
5465 | case RTL_GIGA_MAC_VER_25: | |
5466 | if (status == RxFIFOOver) | |
5467 | goto done; | |
5468 | break; | |
5469 | default: | |
5470 | break; | |
5471 | } | |
f11a377b | 5472 | } |
1da177e4 | 5473 | |
f11a377b DD |
5474 | if (unlikely(status & SYSErr)) { |
5475 | rtl8169_pcierr_interrupt(dev); | |
5476 | break; | |
5477 | } | |
1da177e4 | 5478 | |
f11a377b | 5479 | if (status & LinkChg) |
e4fbce74 | 5480 | __rtl8169_check_link_status(dev, tp, ioaddr, true); |
0e485150 | 5481 | |
f11a377b DD |
5482 | /* We need to see the lastest version of tp->intr_mask to |
5483 | * avoid ignoring an MSI interrupt and having to wait for | |
5484 | * another event which may never come. | |
5485 | */ | |
5486 | smp_rmb(); | |
5487 | if (status & tp->intr_mask & tp->napi_event) { | |
5488 | RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); | |
5489 | tp->intr_mask = ~tp->napi_event; | |
5490 | ||
5491 | if (likely(napi_schedule_prep(&tp->napi))) | |
5492 | __napi_schedule(&tp->napi); | |
bf82c189 JP |
5493 | else |
5494 | netif_info(tp, intr, dev, | |
5495 | "interrupt %04x in poll\n", status); | |
f11a377b | 5496 | } |
1da177e4 | 5497 | |
f11a377b DD |
5498 | /* We only get a new MSI interrupt when all active irq |
5499 | * sources on the chip have been acknowledged. So, ack | |
5500 | * everything we've seen and check if new sources have become | |
5501 | * active to avoid blocking all interrupts from the chip. | |
5502 | */ | |
5503 | RTL_W16(IntrStatus, | |
5504 | (status & RxFIFOOver) ? (status | RxOverflow) : status); | |
5505 | status = RTL_R16(IntrStatus); | |
865c652d | 5506 | } |
1519e57f | 5507 | done: |
1da177e4 LT |
5508 | return IRQ_RETVAL(handled); |
5509 | } | |
5510 | ||
bea3348e | 5511 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 5512 | { |
bea3348e SH |
5513 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
5514 | struct net_device *dev = tp->dev; | |
1da177e4 | 5515 | void __iomem *ioaddr = tp->mmio_addr; |
bea3348e | 5516 | int work_done; |
1da177e4 | 5517 | |
bea3348e | 5518 | work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
1da177e4 LT |
5519 | rtl8169_tx_interrupt(dev, tp, ioaddr); |
5520 | ||
bea3348e | 5521 | if (work_done < budget) { |
288379f0 | 5522 | napi_complete(napi); |
f11a377b DD |
5523 | |
5524 | /* We need for force the visibility of tp->intr_mask | |
5525 | * for other CPUs, as we can loose an MSI interrupt | |
5526 | * and potentially wait for a retransmit timeout if we don't. | |
5527 | * The posted write to IntrMask is safe, as it will | |
5528 | * eventually make it to the chip and we won't loose anything | |
5529 | * until it does. | |
1da177e4 | 5530 | */ |
f11a377b | 5531 | tp->intr_mask = 0xffff; |
4c020a96 | 5532 | wmb(); |
0e485150 | 5533 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
5534 | } |
5535 | ||
bea3348e | 5536 | return work_done; |
1da177e4 | 5537 | } |
1da177e4 | 5538 | |
523a6094 FR |
5539 | static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
5540 | { | |
5541 | struct rtl8169_private *tp = netdev_priv(dev); | |
5542 | ||
5543 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) | |
5544 | return; | |
5545 | ||
5546 | dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); | |
5547 | RTL_W32(RxMissed, 0); | |
5548 | } | |
5549 | ||
1da177e4 LT |
5550 | static void rtl8169_down(struct net_device *dev) |
5551 | { | |
5552 | struct rtl8169_private *tp = netdev_priv(dev); | |
5553 | void __iomem *ioaddr = tp->mmio_addr; | |
1da177e4 | 5554 | |
4876cc1e | 5555 | del_timer_sync(&tp->timer); |
1da177e4 LT |
5556 | |
5557 | netif_stop_queue(dev); | |
5558 | ||
93dd79e8 | 5559 | napi_disable(&tp->napi); |
93dd79e8 | 5560 | |
1da177e4 LT |
5561 | spin_lock_irq(&tp->lock); |
5562 | ||
92fc43b4 | 5563 | rtl8169_hw_reset(tp); |
323bb685 SG |
5564 | /* |
5565 | * At this point device interrupts can not be enabled in any function, | |
5566 | * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task, | |
5567 | * rtl8169_reinit_task) and napi is disabled (rtl8169_poll). | |
5568 | */ | |
523a6094 | 5569 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
5570 | |
5571 | spin_unlock_irq(&tp->lock); | |
5572 | ||
5573 | synchronize_irq(dev->irq); | |
5574 | ||
1da177e4 | 5575 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
fbd568a3 | 5576 | synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
1da177e4 | 5577 | |
1da177e4 LT |
5578 | rtl8169_tx_clear(tp); |
5579 | ||
5580 | rtl8169_rx_clear(tp); | |
065c27c1 | 5581 | |
5582 | rtl_pll_power_down(tp); | |
1da177e4 LT |
5583 | } |
5584 | ||
5585 | static int rtl8169_close(struct net_device *dev) | |
5586 | { | |
5587 | struct rtl8169_private *tp = netdev_priv(dev); | |
5588 | struct pci_dev *pdev = tp->pci_dev; | |
5589 | ||
e1759441 RW |
5590 | pm_runtime_get_sync(&pdev->dev); |
5591 | ||
cecb5fd7 | 5592 | /* Update counters before going down */ |
355423d0 IV |
5593 | rtl8169_update_counters(dev); |
5594 | ||
1da177e4 LT |
5595 | rtl8169_down(dev); |
5596 | ||
5597 | free_irq(dev->irq, dev); | |
5598 | ||
82553bb6 SG |
5599 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
5600 | tp->RxPhyAddr); | |
5601 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
5602 | tp->TxPhyAddr); | |
1da177e4 LT |
5603 | tp->TxDescArray = NULL; |
5604 | tp->RxDescArray = NULL; | |
5605 | ||
e1759441 RW |
5606 | pm_runtime_put_sync(&pdev->dev); |
5607 | ||
1da177e4 LT |
5608 | return 0; |
5609 | } | |
5610 | ||
07ce4064 | 5611 | static void rtl_set_rx_mode(struct net_device *dev) |
1da177e4 LT |
5612 | { |
5613 | struct rtl8169_private *tp = netdev_priv(dev); | |
5614 | void __iomem *ioaddr = tp->mmio_addr; | |
5615 | unsigned long flags; | |
5616 | u32 mc_filter[2]; /* Multicast hash filter */ | |
07d3f51f | 5617 | int rx_mode; |
1da177e4 LT |
5618 | u32 tmp = 0; |
5619 | ||
5620 | if (dev->flags & IFF_PROMISC) { | |
5621 | /* Unconditionally log net taps. */ | |
bf82c189 | 5622 | netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); |
1da177e4 LT |
5623 | rx_mode = |
5624 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
5625 | AcceptAllPhys; | |
5626 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
4cd24eaf | 5627 | } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
8e95a202 | 5628 | (dev->flags & IFF_ALLMULTI)) { |
1da177e4 LT |
5629 | /* Too many to filter perfectly -- accept all multicasts. */ |
5630 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
5631 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
5632 | } else { | |
22bedad3 | 5633 | struct netdev_hw_addr *ha; |
07d3f51f | 5634 | |
1da177e4 LT |
5635 | rx_mode = AcceptBroadcast | AcceptMyPhys; |
5636 | mc_filter[1] = mc_filter[0] = 0; | |
22bedad3 JP |
5637 | netdev_for_each_mc_addr(ha, dev) { |
5638 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
1da177e4 LT |
5639 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
5640 | rx_mode |= AcceptMulticast; | |
5641 | } | |
5642 | } | |
5643 | ||
5644 | spin_lock_irqsave(&tp->lock, flags); | |
5645 | ||
1687b566 | 5646 | tmp = (RTL_R32(RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode; |
1da177e4 | 5647 | |
f887cce8 | 5648 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
1087f4f4 FR |
5649 | u32 data = mc_filter[0]; |
5650 | ||
5651 | mc_filter[0] = swab32(mc_filter[1]); | |
5652 | mc_filter[1] = swab32(data); | |
bcf0bf90 FR |
5653 | } |
5654 | ||
1da177e4 | 5655 | RTL_W32(MAR0 + 4, mc_filter[1]); |
78f1cd02 | 5656 | RTL_W32(MAR0 + 0, mc_filter[0]); |
1da177e4 | 5657 | |
57a9f236 FR |
5658 | RTL_W32(RxConfig, tmp); |
5659 | ||
1da177e4 LT |
5660 | spin_unlock_irqrestore(&tp->lock, flags); |
5661 | } | |
5662 | ||
5663 | /** | |
5664 | * rtl8169_get_stats - Get rtl8169 read/write statistics | |
5665 | * @dev: The Ethernet Device to get statistics for | |
5666 | * | |
5667 | * Get TX/RX statistics for rtl8169 | |
5668 | */ | |
5669 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) | |
5670 | { | |
5671 | struct rtl8169_private *tp = netdev_priv(dev); | |
5672 | void __iomem *ioaddr = tp->mmio_addr; | |
5673 | unsigned long flags; | |
5674 | ||
5675 | if (netif_running(dev)) { | |
5676 | spin_lock_irqsave(&tp->lock, flags); | |
523a6094 | 5677 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
5678 | spin_unlock_irqrestore(&tp->lock, flags); |
5679 | } | |
5b0384f4 | 5680 | |
cebf8cc7 | 5681 | return &dev->stats; |
1da177e4 LT |
5682 | } |
5683 | ||
861ab440 | 5684 | static void rtl8169_net_suspend(struct net_device *dev) |
5d06a99f | 5685 | { |
065c27c1 | 5686 | struct rtl8169_private *tp = netdev_priv(dev); |
5687 | ||
5d06a99f | 5688 | if (!netif_running(dev)) |
861ab440 | 5689 | return; |
5d06a99f | 5690 | |
065c27c1 | 5691 | rtl_pll_power_down(tp); |
5692 | ||
5d06a99f FR |
5693 | netif_device_detach(dev); |
5694 | netif_stop_queue(dev); | |
861ab440 RW |
5695 | } |
5696 | ||
5697 | #ifdef CONFIG_PM | |
5698 | ||
5699 | static int rtl8169_suspend(struct device *device) | |
5700 | { | |
5701 | struct pci_dev *pdev = to_pci_dev(device); | |
5702 | struct net_device *dev = pci_get_drvdata(pdev); | |
5d06a99f | 5703 | |
861ab440 | 5704 | rtl8169_net_suspend(dev); |
1371fa6d | 5705 | |
5d06a99f FR |
5706 | return 0; |
5707 | } | |
5708 | ||
e1759441 RW |
5709 | static void __rtl8169_resume(struct net_device *dev) |
5710 | { | |
065c27c1 | 5711 | struct rtl8169_private *tp = netdev_priv(dev); |
5712 | ||
e1759441 | 5713 | netif_device_attach(dev); |
065c27c1 | 5714 | |
5715 | rtl_pll_power_up(tp); | |
5716 | ||
e1759441 RW |
5717 | rtl8169_schedule_work(dev, rtl8169_reset_task); |
5718 | } | |
5719 | ||
861ab440 | 5720 | static int rtl8169_resume(struct device *device) |
5d06a99f | 5721 | { |
861ab440 | 5722 | struct pci_dev *pdev = to_pci_dev(device); |
5d06a99f | 5723 | struct net_device *dev = pci_get_drvdata(pdev); |
fccec10b SG |
5724 | struct rtl8169_private *tp = netdev_priv(dev); |
5725 | ||
5726 | rtl8169_init_phy(dev, tp); | |
5d06a99f | 5727 | |
e1759441 RW |
5728 | if (netif_running(dev)) |
5729 | __rtl8169_resume(dev); | |
5d06a99f | 5730 | |
e1759441 RW |
5731 | return 0; |
5732 | } | |
5733 | ||
5734 | static int rtl8169_runtime_suspend(struct device *device) | |
5735 | { | |
5736 | struct pci_dev *pdev = to_pci_dev(device); | |
5737 | struct net_device *dev = pci_get_drvdata(pdev); | |
5738 | struct rtl8169_private *tp = netdev_priv(dev); | |
5739 | ||
5740 | if (!tp->TxDescArray) | |
5741 | return 0; | |
5742 | ||
5743 | spin_lock_irq(&tp->lock); | |
5744 | tp->saved_wolopts = __rtl8169_get_wol(tp); | |
5745 | __rtl8169_set_wol(tp, WAKE_ANY); | |
5746 | spin_unlock_irq(&tp->lock); | |
5747 | ||
5748 | rtl8169_net_suspend(dev); | |
5749 | ||
5750 | return 0; | |
5751 | } | |
5752 | ||
5753 | static int rtl8169_runtime_resume(struct device *device) | |
5754 | { | |
5755 | struct pci_dev *pdev = to_pci_dev(device); | |
5756 | struct net_device *dev = pci_get_drvdata(pdev); | |
5757 | struct rtl8169_private *tp = netdev_priv(dev); | |
5758 | ||
5759 | if (!tp->TxDescArray) | |
5760 | return 0; | |
5761 | ||
5762 | spin_lock_irq(&tp->lock); | |
5763 | __rtl8169_set_wol(tp, tp->saved_wolopts); | |
5764 | tp->saved_wolopts = 0; | |
5765 | spin_unlock_irq(&tp->lock); | |
5766 | ||
fccec10b SG |
5767 | rtl8169_init_phy(dev, tp); |
5768 | ||
e1759441 | 5769 | __rtl8169_resume(dev); |
5d06a99f | 5770 | |
5d06a99f FR |
5771 | return 0; |
5772 | } | |
5773 | ||
e1759441 RW |
5774 | static int rtl8169_runtime_idle(struct device *device) |
5775 | { | |
5776 | struct pci_dev *pdev = to_pci_dev(device); | |
5777 | struct net_device *dev = pci_get_drvdata(pdev); | |
5778 | struct rtl8169_private *tp = netdev_priv(dev); | |
5779 | ||
e4fbce74 | 5780 | return tp->TxDescArray ? -EBUSY : 0; |
e1759441 RW |
5781 | } |
5782 | ||
47145210 | 5783 | static const struct dev_pm_ops rtl8169_pm_ops = { |
cecb5fd7 FR |
5784 | .suspend = rtl8169_suspend, |
5785 | .resume = rtl8169_resume, | |
5786 | .freeze = rtl8169_suspend, | |
5787 | .thaw = rtl8169_resume, | |
5788 | .poweroff = rtl8169_suspend, | |
5789 | .restore = rtl8169_resume, | |
5790 | .runtime_suspend = rtl8169_runtime_suspend, | |
5791 | .runtime_resume = rtl8169_runtime_resume, | |
5792 | .runtime_idle = rtl8169_runtime_idle, | |
861ab440 RW |
5793 | }; |
5794 | ||
5795 | #define RTL8169_PM_OPS (&rtl8169_pm_ops) | |
5796 | ||
5797 | #else /* !CONFIG_PM */ | |
5798 | ||
5799 | #define RTL8169_PM_OPS NULL | |
5800 | ||
5801 | #endif /* !CONFIG_PM */ | |
5802 | ||
649b3b8c | 5803 | static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp) |
5804 | { | |
5805 | void __iomem *ioaddr = tp->mmio_addr; | |
5806 | ||
5807 | /* WoL fails with 8168b when the receiver is disabled. */ | |
5808 | switch (tp->mac_version) { | |
5809 | case RTL_GIGA_MAC_VER_11: | |
5810 | case RTL_GIGA_MAC_VER_12: | |
5811 | case RTL_GIGA_MAC_VER_17: | |
5812 | pci_clear_master(tp->pci_dev); | |
5813 | ||
5814 | RTL_W8(ChipCmd, CmdRxEnb); | |
5815 | /* PCI commit */ | |
5816 | RTL_R8(ChipCmd); | |
5817 | break; | |
5818 | default: | |
5819 | break; | |
5820 | } | |
5821 | } | |
5822 | ||
1765f95d FR |
5823 | static void rtl_shutdown(struct pci_dev *pdev) |
5824 | { | |
861ab440 | 5825 | struct net_device *dev = pci_get_drvdata(pdev); |
4bb3f522 | 5826 | struct rtl8169_private *tp = netdev_priv(dev); |
861ab440 RW |
5827 | |
5828 | rtl8169_net_suspend(dev); | |
1765f95d | 5829 | |
cecb5fd7 | 5830 | /* Restore original MAC address */ |
cc098dc7 IV |
5831 | rtl_rar_set(tp, dev->perm_addr); |
5832 | ||
4bb3f522 | 5833 | spin_lock_irq(&tp->lock); |
5834 | ||
92fc43b4 | 5835 | rtl8169_hw_reset(tp); |
4bb3f522 | 5836 | |
5837 | spin_unlock_irq(&tp->lock); | |
5838 | ||
861ab440 | 5839 | if (system_state == SYSTEM_POWER_OFF) { |
649b3b8c | 5840 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
5841 | rtl_wol_suspend_quirk(tp); | |
5842 | rtl_wol_shutdown_quirk(tp); | |
ca52efd5 | 5843 | } |
5844 | ||
861ab440 RW |
5845 | pci_wake_from_d3(pdev, true); |
5846 | pci_set_power_state(pdev, PCI_D3hot); | |
5847 | } | |
5848 | } | |
5d06a99f | 5849 | |
1da177e4 LT |
5850 | static struct pci_driver rtl8169_pci_driver = { |
5851 | .name = MODULENAME, | |
5852 | .id_table = rtl8169_pci_tbl, | |
5853 | .probe = rtl8169_init_one, | |
5854 | .remove = __devexit_p(rtl8169_remove_one), | |
1765f95d | 5855 | .shutdown = rtl_shutdown, |
861ab440 | 5856 | .driver.pm = RTL8169_PM_OPS, |
1da177e4 LT |
5857 | }; |
5858 | ||
07d3f51f | 5859 | static int __init rtl8169_init_module(void) |
1da177e4 | 5860 | { |
29917620 | 5861 | return pci_register_driver(&rtl8169_pci_driver); |
1da177e4 LT |
5862 | } |
5863 | ||
07d3f51f | 5864 | static void __exit rtl8169_cleanup_module(void) |
1da177e4 LT |
5865 | { |
5866 | pci_unregister_driver(&rtl8169_pci_driver); | |
5867 | } | |
5868 | ||
5869 | module_init(rtl8169_init_module); | |
5870 | module_exit(rtl8169_cleanup_module); |