]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/r8169.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
add support for smc91x ethernet interface on zylonite
[mirror_ubuntu-bionic-kernel.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
f7ccf420
SH		 31#ifdef CONFIG_R8169_NAPI
32#define NAPI_SUFFIX "-NAPI"
33#else
34#define NAPI_SUFFIX ""
35#endif
36
37#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 38#define MODULENAME "r8169"
39#define PFX MODULENAME ": "
40
41#ifdef RTL8169_DEBUG
42#define assert(expr) \
5b0384f4
FR		 43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
06fa7358
JP		 47#define dprintk(fmt, args...) \
48 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 49#else
50#define assert(expr) do {} while (0)
51#define dprintk(fmt, args...) do {} while (0)
52#endif /* RTL8169_DEBUG */
53
b57b7e5a 54#define R8169_MSG_DEFAULT \
f0e837d9 55 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 56
1da177e4
LT		 57#define TX_BUFFS_AVAIL(tp) \
58 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
59
60#ifdef CONFIG_R8169_NAPI
61#define rtl8169_rx_skb netif_receive_skb
0b50f81d 62#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 63#define rtl8169_rx_quota(count, quota) min(count, quota)
64#else
65#define rtl8169_rx_skb netif_rx
0b50f81d 66#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 67#define rtl8169_rx_quota(count, quota) count
68#endif
69
1da177e4 70/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 71static const int max_interrupt_work = 20;
1da177e4
LT		 72
73/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
74 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 75static const int multicast_filter_limit = 32;
1da177e4
LT		 76
77/* MAC address length */
78#define MAC_ADDR_LEN 6
79
80#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
81#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
82#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 83#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 84#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
85#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
86#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
87
88#define R8169_REGS_SIZE 256
89#define R8169_NAPI_WEIGHT 64
90#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
91#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
92#define RX_BUF_SIZE 1536 /* Rx Buffer size */
93#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
94#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
95
96#define RTL8169_TX_TIMEOUT (6*HZ)
97#define RTL8169_PHY_TIMEOUT (10*HZ)
98
99/* write/read MMIO register */
100#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
101#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
102#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
103#define RTL_R8(reg) readb (ioaddr + (reg))
104#define RTL_R16(reg) readw (ioaddr + (reg))
105#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
106
107enum mac_version {
ba6eb6ee
FR		 108 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
109 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
110 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
111 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
112 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 113 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530 114 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 115 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
116 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
117 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
118 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
119 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
120 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
121 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
122 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
123 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
1da177e4
LT		 124};
125
1da177e4
LT		 126#define _R(NAME,MAC,MASK) \
127 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
128
3c6bee1d 129static const struct {
1da177e4
LT		 130 const char *name;
131 u8 mac_version;
132 u32 RxConfigMask; /* Clears the bits supported by this chip */
133} rtl_chip_info[] = {
ba6eb6ee
FR		 134 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
135 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
136 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
137 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
138 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 139 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 140 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
142 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
143 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 144 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
145 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
146 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
147 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
148 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
1da177e4
LT		 150};
151#undef _R
152
bcf0bf90
FR		 153enum cfg_version {
154 RTL_CFG_0 = 0x00,
155 RTL_CFG_1,
156 RTL_CFG_2
157};
158
07ce4064
FR		 159static void rtl_hw_start_8169(struct net_device *);
160static void rtl_hw_start_8168(struct net_device *);
161static void rtl_hw_start_8101(struct net_device *);
162
1da177e4 163static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 167 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 168 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
169 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 170 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 171 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
172 { PCI_VENDOR_ID_LINKSYS, 0x1032,
173 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 174 {0,},
175};
176
177MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
178
179static int rx_copybreak = 200;
180static int use_dac;
b57b7e5a
SH		 181static struct {
182 u32 msg_enable;
183} debug = { -1 };
1da177e4 184
07d3f51f
FR		 185enum rtl_registers {
186 MAC0 = 0, /* Ethernet hardware address. */
773d2021 187 MAC4 = 4,
07d3f51f
FR		 188 MAR0 = 8, /* Multicast filter. */
189 CounterAddrLow = 0x10,
190 CounterAddrHigh = 0x14,
191 TxDescStartAddrLow = 0x20,
192 TxDescStartAddrHigh = 0x24,
193 TxHDescStartAddrLow = 0x28,
194 TxHDescStartAddrHigh = 0x2c,
195 FLASH = 0x30,
196 ERSR = 0x36,
197 ChipCmd = 0x37,
198 TxPoll = 0x38,
199 IntrMask = 0x3c,
200 IntrStatus = 0x3e,
201 TxConfig = 0x40,
202 RxConfig = 0x44,
203 RxMissed = 0x4c,
204 Cfg9346 = 0x50,
205 Config0 = 0x51,
206 Config1 = 0x52,
207 Config2 = 0x53,
208 Config3 = 0x54,
209 Config4 = 0x55,
210 Config5 = 0x56,
211 MultiIntr = 0x5c,
212 PHYAR = 0x60,
213 TBICSR = 0x64,
214 TBI_ANAR = 0x68,
215 TBI_LPAR = 0x6a,
216 PHYstatus = 0x6c,
217 RxMaxSize = 0xda,
218 CPlusCmd = 0xe0,
219 IntrMitigate = 0xe2,
220 RxDescAddrLow = 0xe4,
221 RxDescAddrHigh = 0xe8,
222 EarlyTxThres = 0xec,
223 FuncEvent = 0xf0,
224 FuncEventMask = 0xf4,
225 FuncPresetState = 0xf8,
226 FuncForceEvent = 0xfc,
1da177e4
LT		 227};
228
07d3f51f 229enum rtl_register_content {
1da177e4 230 /* InterruptStatusBits */
07d3f51f
FR		 231 SYSErr = 0x8000,
232 PCSTimeout = 0x4000,
233 SWInt = 0x0100,
234 TxDescUnavail = 0x0080,
235 RxFIFOOver = 0x0040,
236 LinkChg = 0x0020,
237 RxOverflow = 0x0010,
238 TxErr = 0x0008,
239 TxOK = 0x0004,
240 RxErr = 0x0002,
241 RxOK = 0x0001,
1da177e4
LT		 242
243 /* RxStatusDesc */
9dccf611
FR		 244 RxFOVF = (1 << 23),
245 RxRWT = (1 << 22),
246 RxRES = (1 << 21),
247 RxRUNT = (1 << 20),
248 RxCRC = (1 << 19),
1da177e4
LT		 249
250 /* ChipCmdBits */
07d3f51f
FR		 251 CmdReset = 0x10,
252 CmdRxEnb = 0x08,
253 CmdTxEnb = 0x04,
254 RxBufEmpty = 0x01,
1da177e4 255
275391a4
FR		 256 /* TXPoll register p.5 */
257 HPQ = 0x80, /* Poll cmd on the high prio queue */
258 NPQ = 0x40, /* Poll cmd on the low prio queue */
259 FSWInt = 0x01, /* Forced software interrupt */
260
1da177e4 261 /* Cfg9346Bits */
07d3f51f
FR		 262 Cfg9346_Lock = 0x00,
263 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 264
265 /* rx_mode_bits */
07d3f51f
FR		 266 AcceptErr = 0x20,
267 AcceptRunt = 0x10,
268 AcceptBroadcast = 0x08,
269 AcceptMulticast = 0x04,
270 AcceptMyPhys = 0x02,
271 AcceptAllPhys = 0x01,
1da177e4
LT		 272
273 /* RxConfigBits */
07d3f51f
FR		 274 RxCfgFIFOShift = 13,
275 RxCfgDMAShift = 8,
1da177e4
LT		 276
277 /* TxConfigBits */
278 TxInterFrameGapShift = 24,
279 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
280
5d06a99f 281 /* Config1 register p.24 */
fbac58fc 282 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
5d06a99f
FR		 283 PMEnable = (1 << 0), /* Power Management Enable */
284
6dccd16b
FR		 285 /* Config2 register p. 25 */
286 PCI_Clock_66MHz = 0x01,
287 PCI_Clock_33MHz = 0x00,
288
61a4dcc2
FR		 289 /* Config3 register p.25 */
290 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
291 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
292
5d06a99f 293 /* Config5 register p.27 */
61a4dcc2
FR		 294 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
295 MWF = (1 << 5), /* Accept Multicast wakeup frame */
296 UWF = (1 << 4), /* Accept Unicast wakeup frame */
297 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 298 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
299
1da177e4
LT		 300 /* TBICSR p.28 */
301 TBIReset = 0x80000000,
302 TBILoopback = 0x40000000,
303 TBINwEnable = 0x20000000,
304 TBINwRestart = 0x10000000,
305 TBILinkOk = 0x02000000,
306 TBINwComplete = 0x01000000,
307
308 /* CPlusCmd p.31 */
0e485150 309 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 310 RxVlan = (1 << 6),
311 RxChkSum = (1 << 5),
312 PCIDAC = (1 << 4),
313 PCIMulRW = (1 << 3),
0e485150
FR		 314 INTT_0 = 0x0000, // 8168
315 INTT_1 = 0x0001, // 8168
316 INTT_2 = 0x0002, // 8168
317 INTT_3 = 0x0003, // 8168
1da177e4
LT		 318
319 /* rtl8169_PHYstatus */
07d3f51f
FR		 320 TBI_Enable = 0x80,
321 TxFlowCtrl = 0x40,
322 RxFlowCtrl = 0x20,
323 _1000bpsF = 0x10,
324 _100bps = 0x08,
325 _10bps = 0x04,
326 LinkStatus = 0x02,
327 FullDup = 0x01,
1da177e4 328
1da177e4 329 /* _TBICSRBit */
07d3f51f 330 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 331
332 /* DumpCounterCommand */
07d3f51f 333 CounterDump = 0x8,
1da177e4
LT		 334};
335
07d3f51f 336enum desc_status_bit {
1da177e4
LT		 337 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
338 RingEnd = (1 << 30), /* End of descriptor ring */
339 FirstFrag = (1 << 29), /* First segment of a packet */
340 LastFrag = (1 << 28), /* Final segment of a packet */
341
342 /* Tx private */
343 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
344 MSSShift = 16, /* MSS value position */
345 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
346 IPCS = (1 << 18), /* Calculate IP checksum */
347 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
348 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
349 TxVlanTag = (1 << 17), /* Add VLAN tag */
350
351 /* Rx private */
352 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
353 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
354
355#define RxProtoUDP (PID1)
356#define RxProtoTCP (PID0)
357#define RxProtoIP (PID1 | PID0)
358#define RxProtoMask RxProtoIP
359
360 IPFail = (1 << 16), /* IP checksum failed */
361 UDPFail = (1 << 15), /* UDP/IP checksum failed */
362 TCPFail = (1 << 14), /* TCP/IP checksum failed */
363 RxVlanTag = (1 << 16), /* VLAN tag available */
364};
365
366#define RsvdMask 0x3fffc000
367
368struct TxDesc {
6cccd6e7
REB		 369 __le32 opts1;
370 __le32 opts2;
371 __le64 addr;
1da177e4
LT		 372};
373
374struct RxDesc {
6cccd6e7
REB		 375 __le32 opts1;
376 __le32 opts2;
377 __le64 addr;
1da177e4
LT		 378};
379
380struct ring_info {
381 struct sk_buff *skb;
382 u32 len;
383 u8 __pad[sizeof(void *) - sizeof(u32)];
384};
385
f23e7fda
FR		 386enum features {
387 RTL_FEATURE_WOL = (1 << 0),
fbac58fc 388 RTL_FEATURE_MSI = (1 << 1),
f23e7fda
FR		 389};
390
1da177e4
LT		 391struct rtl8169_private {
392 void __iomem *mmio_addr; /* memory map physical address */
393 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 394 struct net_device *dev;
7fab06c0 395#ifdef CONFIG_R8169_NAPI
bea3348e 396 struct napi_struct napi;
7fab06c0 397#endif
1da177e4 398 spinlock_t lock; /* spin lock flag */
b57b7e5a 399 u32 msg_enable;
1da177e4
LT		 400 int chipset;
401 int mac_version;
1da177e4
LT		 402 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
403 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
404 u32 dirty_rx;
405 u32 dirty_tx;
406 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
407 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
408 dma_addr_t TxPhyAddr;
409 dma_addr_t RxPhyAddr;
410 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
411 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 412 unsigned align;
1da177e4
LT		 413 unsigned rx_buf_sz;
414 struct timer_list timer;
415 u16 cp_cmd;
0e485150
FR		 416 u16 intr_event;
417 u16 napi_event;
1da177e4
LT		 418 u16 intr_mask;
419 int phy_auto_nego_reg;
420 int phy_1000_ctrl_reg;
421#ifdef CONFIG_R8169_VLAN
422 struct vlan_group *vlgrp;
423#endif
424 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
425 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
426 void (*phy_reset_enable)(void __iomem *);
07ce4064 427 void (*hw_start)(struct net_device *);
1da177e4
LT		 428 unsigned int (*phy_reset_pending)(void __iomem *);
429 unsigned int (*link_ok)(void __iomem *);
c4028958 430 struct delayed_work task;
f23e7fda 431 unsigned features;
1da177e4
LT		 432};
433
979b6c13 434MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 435MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 436module_param(rx_copybreak, int, 0);
1b7efd58 437MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 438module_param(use_dac, int, 0);
439MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 440module_param_named(debug, debug.msg_enable, int, 0);
441MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 442MODULE_LICENSE("GPL");
443MODULE_VERSION(RTL8169_VERSION);
444
445static int rtl8169_open(struct net_device *dev);
446static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 447static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 448static int rtl8169_init_ring(struct net_device *dev);
07ce4064 449static void rtl_hw_start(struct net_device *dev);
1da177e4 450static int rtl8169_close(struct net_device *dev);
07ce4064 451static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 452static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 453static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 454static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 455 void __iomem *, u32 budget);
4dcb7d33 456static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 457static void rtl8169_down(struct net_device *dev);
99f252b0 458static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 459
460#ifdef CONFIG_R8169_NAPI
bea3348e 461static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4
LT		 462#endif
463
1da177e4 464static const unsigned int rtl8169_rx_config =
5b0384f4 465 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 466
07d3f51f 467static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 468{
469 int i;
470
07d3f51f 471 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
1da177e4 472
2371408c 473 for (i = 20; i > 0; i--) {
07d3f51f
FR		 474 /*
475 * Check if the RTL8169 has completed writing to the specified
476 * MII register.
477 */
5b0384f4 478 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 479 break;
2371408c 480 udelay(25);
1da177e4
LT		 481 }
482}
483
07d3f51f 484static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 485{
486 int i, value = -1;
487
07d3f51f 488 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
1da177e4 489
2371408c 490 for (i = 20; i > 0; i--) {
07d3f51f
FR		 491 /*
492 * Check if the RTL8169 has completed retrieving data from
493 * the specified MII register.
494 */
1da177e4
LT		 495 if (RTL_R32(PHYAR) & 0x80000000) {
496 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
497 break;
498 }
2371408c 499 udelay(25);
1da177e4
LT		 500 }
501 return value;
502}
503
504static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
505{
506 RTL_W16(IntrMask, 0x0000);
507
508 RTL_W16(IntrStatus, 0xffff);
509}
510
511static void rtl8169_asic_down(void __iomem *ioaddr)
512{
513 RTL_W8(ChipCmd, 0x00);
514 rtl8169_irq_mask_and_ack(ioaddr);
515 RTL_R16(CPlusCmd);
516}
517
518static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
519{
520 return RTL_R32(TBICSR) & TBIReset;
521}
522
523static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
524{
64e4bfb4 525 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 526}
527
528static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
529{
530 return RTL_R32(TBICSR) & TBILinkOk;
531}
532
533static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
534{
535 return RTL_R8(PHYstatus) & LinkStatus;
536}
537
538static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
539{
540 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
541}
542
543static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
544{
545 unsigned int val;
546
9e0db8ef
FR		 547 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
548 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 549}
550
551static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 552 struct rtl8169_private *tp,
553 void __iomem *ioaddr)
1da177e4
LT		 554{
555 unsigned long flags;
556
557 spin_lock_irqsave(&tp->lock, flags);
558 if (tp->link_ok(ioaddr)) {
559 netif_carrier_on(dev);
b57b7e5a
SH		 560 if (netif_msg_ifup(tp))
561 printk(KERN_INFO PFX "%s: link up\n", dev->name);
562 } else {
563 if (netif_msg_ifdown(tp))
564 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 565 netif_carrier_off(dev);
b57b7e5a 566 }
1da177e4
LT		 567 spin_unlock_irqrestore(&tp->lock, flags);
568}
569
61a4dcc2
FR		 570static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
571{
572 struct rtl8169_private *tp = netdev_priv(dev);
573 void __iomem *ioaddr = tp->mmio_addr;
574 u8 options;
575
576 wol->wolopts = 0;
577
578#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
579 wol->supported = WAKE_ANY;
580
581 spin_lock_irq(&tp->lock);
582
583 options = RTL_R8(Config1);
584 if (!(options & PMEnable))
585 goto out_unlock;
586
587 options = RTL_R8(Config3);
588 if (options & LinkUp)
589 wol->wolopts |= WAKE_PHY;
590 if (options & MagicPacket)
591 wol->wolopts |= WAKE_MAGIC;
592
593 options = RTL_R8(Config5);
594 if (options & UWF)
595 wol->wolopts |= WAKE_UCAST;
596 if (options & BWF)
5b0384f4 597 wol->wolopts |= WAKE_BCAST;
61a4dcc2 598 if (options & MWF)
5b0384f4 599 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 600
601out_unlock:
602 spin_unlock_irq(&tp->lock);
603}
604
605static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
606{
607 struct rtl8169_private *tp = netdev_priv(dev);
608 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 609 unsigned int i;
61a4dcc2
FR		 610 static struct {
611 u32 opt;
612 u16 reg;
613 u8 mask;
614 } cfg[] = {
615 { WAKE_ANY, Config1, PMEnable },
616 { WAKE_PHY, Config3, LinkUp },
617 { WAKE_MAGIC, Config3, MagicPacket },
618 { WAKE_UCAST, Config5, UWF },
619 { WAKE_BCAST, Config5, BWF },
620 { WAKE_MCAST, Config5, MWF },
621 { WAKE_ANY, Config5, LanWake }
622 };
623
624 spin_lock_irq(&tp->lock);
625
626 RTL_W8(Cfg9346, Cfg9346_Unlock);
627
628 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
629 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
630 if (wol->wolopts & cfg[i].opt)
631 options |= cfg[i].mask;
632 RTL_W8(cfg[i].reg, options);
633 }
634
635 RTL_W8(Cfg9346, Cfg9346_Lock);
636
f23e7fda
FR		 637 if (wol->wolopts)
638 tp->features |= RTL_FEATURE_WOL;
639 else
640 tp->features &= ~RTL_FEATURE_WOL;
61a4dcc2
FR		 641
642 spin_unlock_irq(&tp->lock);
643
644 return 0;
645}
646
1da177e4
LT		 647static void rtl8169_get_drvinfo(struct net_device *dev,
648 struct ethtool_drvinfo *info)
649{
650 struct rtl8169_private *tp = netdev_priv(dev);
651
652 strcpy(info->driver, MODULENAME);
653 strcpy(info->version, RTL8169_VERSION);
654 strcpy(info->bus_info, pci_name(tp->pci_dev));
655}
656
657static int rtl8169_get_regs_len(struct net_device *dev)
658{
659 return R8169_REGS_SIZE;
660}
661
662static int rtl8169_set_speed_tbi(struct net_device *dev,
663 u8 autoneg, u16 speed, u8 duplex)
664{
665 struct rtl8169_private *tp = netdev_priv(dev);
666 void __iomem *ioaddr = tp->mmio_addr;
667 int ret = 0;
668 u32 reg;
669
670 reg = RTL_R32(TBICSR);
671 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
672 (duplex == DUPLEX_FULL)) {
673 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
674 } else if (autoneg == AUTONEG_ENABLE)
675 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
676 else {
b57b7e5a
SH		 677 if (netif_msg_link(tp)) {
678 printk(KERN_WARNING "%s: "
679 "incorrect speed setting refused in TBI mode\n",
680 dev->name);
681 }
1da177e4
LT		 682 ret = -EOPNOTSUPP;
683 }
684
685 return ret;
686}
687
688static int rtl8169_set_speed_xmii(struct net_device *dev,
689 u8 autoneg, u16 speed, u8 duplex)
690{
691 struct rtl8169_private *tp = netdev_priv(dev);
692 void __iomem *ioaddr = tp->mmio_addr;
693 int auto_nego, giga_ctrl;
694
64e4bfb4
FR		 695 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
696 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
697 ADVERTISE_100HALF | ADVERTISE_100FULL);
698 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
699 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 700
701 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 702 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
703 ADVERTISE_100HALF | ADVERTISE_100FULL);
704 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 705 } else {
706 if (speed == SPEED_10)
64e4bfb4 707 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 708 else if (speed == SPEED_100)
64e4bfb4 709 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 710 else if (speed == SPEED_1000)
64e4bfb4 711 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 712
713 if (duplex == DUPLEX_HALF)
64e4bfb4 714 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 715
716 if (duplex == DUPLEX_FULL)
64e4bfb4 717 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 718
719 /* This tweak comes straight from Realtek's driver. */
720 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 721 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
722 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 723 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 724 }
725 }
726
727 /* The 8100e/8101e do Fast Ethernet only. */
728 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
729 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 730 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
731 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 732 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 733 netif_msg_link(tp)) {
734 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
735 dev->name);
736 }
64e4bfb4 737 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 738 }
739
623a1593
FR		 740 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
741
e3cf0cc0
FR		 742 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
743 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
2584fbc3
RS		 744 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
745 mdio_write(ioaddr, 0x1f, 0x0000);
746 mdio_write(ioaddr, 0x0e, 0x0000);
747 }
748
1da177e4
LT		 749 tp->phy_auto_nego_reg = auto_nego;
750 tp->phy_1000_ctrl_reg = giga_ctrl;
751
64e4bfb4
FR		 752 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
753 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
754 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 755 return 0;
756}
757
758static int rtl8169_set_speed(struct net_device *dev,
759 u8 autoneg, u16 speed, u8 duplex)
760{
761 struct rtl8169_private *tp = netdev_priv(dev);
762 int ret;
763
764 ret = tp->set_speed(dev, autoneg, speed, duplex);
765
64e4bfb4 766 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 767 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
768
769 return ret;
770}
771
772static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
773{
774 struct rtl8169_private *tp = netdev_priv(dev);
775 unsigned long flags;
776 int ret;
777
778 spin_lock_irqsave(&tp->lock, flags);
779 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
780 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 781
1da177e4
LT		 782 return ret;
783}
784
785static u32 rtl8169_get_rx_csum(struct net_device *dev)
786{
787 struct rtl8169_private *tp = netdev_priv(dev);
788
789 return tp->cp_cmd & RxChkSum;
790}
791
792static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
793{
794 struct rtl8169_private *tp = netdev_priv(dev);
795 void __iomem *ioaddr = tp->mmio_addr;
796 unsigned long flags;
797
798 spin_lock_irqsave(&tp->lock, flags);
799
800 if (data)
801 tp->cp_cmd |= RxChkSum;
802 else
803 tp->cp_cmd &= ~RxChkSum;
804
805 RTL_W16(CPlusCmd, tp->cp_cmd);
806 RTL_R16(CPlusCmd);
807
808 spin_unlock_irqrestore(&tp->lock, flags);
809
810 return 0;
811}
812
813#ifdef CONFIG_R8169_VLAN
814
815static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
816 struct sk_buff *skb)
817{
818 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
819 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
820}
821
822static void rtl8169_vlan_rx_register(struct net_device *dev,
823 struct vlan_group *grp)
824{
825 struct rtl8169_private *tp = netdev_priv(dev);
826 void __iomem *ioaddr = tp->mmio_addr;
827 unsigned long flags;
828
829 spin_lock_irqsave(&tp->lock, flags);
830 tp->vlgrp = grp;
831 if (tp->vlgrp)
832 tp->cp_cmd |= RxVlan;
833 else
834 tp->cp_cmd &= ~RxVlan;
835 RTL_W16(CPlusCmd, tp->cp_cmd);
836 RTL_R16(CPlusCmd);
837 spin_unlock_irqrestore(&tp->lock, flags);
838}
839
1da177e4
LT		 840static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
841 struct sk_buff *skb)
842{
843 u32 opts2 = le32_to_cpu(desc->opts2);
844 int ret;
845
846 if (tp->vlgrp && (opts2 & RxVlanTag)) {
07d3f51f 847 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 848 ret = 0;
849 } else
850 ret = -1;
851 desc->opts2 = 0;
852 return ret;
853}
854
855#else /* !CONFIG_R8169_VLAN */
856
857static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
858 struct sk_buff *skb)
859{
860 return 0;
861}
862
863static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
864 struct sk_buff *skb)
865{
866 return -1;
867}
868
869#endif
870
871static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
872{
873 struct rtl8169_private *tp = netdev_priv(dev);
874 void __iomem *ioaddr = tp->mmio_addr;
875 u32 status;
876
877 cmd->supported =
878 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
879 cmd->port = PORT_FIBRE;
880 cmd->transceiver = XCVR_INTERNAL;
881
882 status = RTL_R32(TBICSR);
883 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
884 cmd->autoneg = !!(status & TBINwEnable);
885
886 cmd->speed = SPEED_1000;
887 cmd->duplex = DUPLEX_FULL; /* Always set */
888}
889
890static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
891{
892 struct rtl8169_private *tp = netdev_priv(dev);
893 void __iomem *ioaddr = tp->mmio_addr;
894 u8 status;
895
896 cmd->supported = SUPPORTED_10baseT_Half |
897 SUPPORTED_10baseT_Full |
898 SUPPORTED_100baseT_Half |
899 SUPPORTED_100baseT_Full |
900 SUPPORTED_1000baseT_Full |
901 SUPPORTED_Autoneg |
5b0384f4 902 SUPPORTED_TP;
1da177e4
LT		 903
904 cmd->autoneg = 1;
905 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
906
64e4bfb4 907 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 908 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 909 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 910 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 911 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 912 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 913 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 914 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 915 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 916 cmd->advertising |= ADVERTISED_1000baseT_Full;
917
918 status = RTL_R8(PHYstatus);
919
920 if (status & _1000bpsF)
921 cmd->speed = SPEED_1000;
922 else if (status & _100bps)
923 cmd->speed = SPEED_100;
924 else if (status & _10bps)
925 cmd->speed = SPEED_10;
926
623a1593
FR		 927 if (status & TxFlowCtrl)
928 cmd->advertising |= ADVERTISED_Asym_Pause;
929 if (status & RxFlowCtrl)
930 cmd->advertising |= ADVERTISED_Pause;
931
1da177e4
LT		 932 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
933 DUPLEX_FULL : DUPLEX_HALF;
934}
935
936static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
937{
938 struct rtl8169_private *tp = netdev_priv(dev);
939 unsigned long flags;
940
941 spin_lock_irqsave(&tp->lock, flags);
942
943 tp->get_settings(dev, cmd);
944
945 spin_unlock_irqrestore(&tp->lock, flags);
946 return 0;
947}
948
949static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
950 void *p)
951{
5b0384f4
FR		 952 struct rtl8169_private *tp = netdev_priv(dev);
953 unsigned long flags;
1da177e4 954
5b0384f4
FR		 955 if (regs->len > R8169_REGS_SIZE)
956 regs->len = R8169_REGS_SIZE;
1da177e4 957
5b0384f4
FR		 958 spin_lock_irqsave(&tp->lock, flags);
959 memcpy_fromio(p, tp->mmio_addr, regs->len);
960 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 961}
962
b57b7e5a
SH		 963static u32 rtl8169_get_msglevel(struct net_device *dev)
964{
965 struct rtl8169_private *tp = netdev_priv(dev);
966
967 return tp->msg_enable;
968}
969
970static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
971{
972 struct rtl8169_private *tp = netdev_priv(dev);
973
974 tp->msg_enable = value;
975}
976
d4a3a0fc
SH		 977static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
978 "tx_packets",
979 "rx_packets",
980 "tx_errors",
981 "rx_errors",
982 "rx_missed",
983 "align_errors",
984 "tx_single_collisions",
985 "tx_multi_collisions",
986 "unicast",
987 "broadcast",
988 "multicast",
989 "tx_aborted",
990 "tx_underrun",
991};
992
993struct rtl8169_counters {
b1eab701
AV		 994 __le64 tx_packets;
995 __le64 rx_packets;
996 __le64 tx_errors;
997 __le32 rx_errors;
998 __le16 rx_missed;
999 __le16 align_errors;
1000 __le32 tx_one_collision;
1001 __le32 tx_multi_collision;
1002 __le64 rx_unicast;
1003 __le64 rx_broadcast;
1004 __le32 rx_multicast;
1005 __le16 tx_aborted;
1006 __le16 tx_underun;
d4a3a0fc
SH		 1007};
1008
b9f2c044 1009static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1010{
b9f2c044
JG		 1011 switch (sset) {
1012 case ETH_SS_STATS:
1013 return ARRAY_SIZE(rtl8169_gstrings);
1014 default:
1015 return -EOPNOTSUPP;
1016 }
d4a3a0fc
SH		 1017}
1018
1019static void rtl8169_get_ethtool_stats(struct net_device *dev,
1020 struct ethtool_stats *stats, u64 *data)
1021{
1022 struct rtl8169_private *tp = netdev_priv(dev);
1023 void __iomem *ioaddr = tp->mmio_addr;
1024 struct rtl8169_counters *counters;
1025 dma_addr_t paddr;
1026 u32 cmd;
1027
1028 ASSERT_RTNL();
1029
1030 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1031 if (!counters)
1032 return;
1033
1034 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1035 cmd = (u64)paddr & DMA_32BIT_MASK;
1036 RTL_W32(CounterAddrLow, cmd);
1037 RTL_W32(CounterAddrLow, cmd | CounterDump);
1038
1039 while (RTL_R32(CounterAddrLow) & CounterDump) {
1040 if (msleep_interruptible(1))
1041 break;
1042 }
1043
1044 RTL_W32(CounterAddrLow, 0);
1045 RTL_W32(CounterAddrHigh, 0);
1046
5b0384f4 1047 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1048 data[1] = le64_to_cpu(counters->rx_packets);
1049 data[2] = le64_to_cpu(counters->tx_errors);
1050 data[3] = le32_to_cpu(counters->rx_errors);
1051 data[4] = le16_to_cpu(counters->rx_missed);
1052 data[5] = le16_to_cpu(counters->align_errors);
1053 data[6] = le32_to_cpu(counters->tx_one_collision);
1054 data[7] = le32_to_cpu(counters->tx_multi_collision);
1055 data[8] = le64_to_cpu(counters->rx_unicast);
1056 data[9] = le64_to_cpu(counters->rx_broadcast);
1057 data[10] = le32_to_cpu(counters->rx_multicast);
1058 data[11] = le16_to_cpu(counters->tx_aborted);
1059 data[12] = le16_to_cpu(counters->tx_underun);
1060
1061 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1062}
1063
1064static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1065{
1066 switch(stringset) {
1067 case ETH_SS_STATS:
1068 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1069 break;
1070 }
1071}
1072
7282d491 1073static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1074 .get_drvinfo = rtl8169_get_drvinfo,
1075 .get_regs_len = rtl8169_get_regs_len,
1076 .get_link = ethtool_op_get_link,
1077 .get_settings = rtl8169_get_settings,
1078 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1079 .get_msglevel = rtl8169_get_msglevel,
1080 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1081 .get_rx_csum = rtl8169_get_rx_csum,
1082 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1083 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1084 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1085 .set_tso = ethtool_op_set_tso,
1086 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1087 .get_wol = rtl8169_get_wol,
1088 .set_wol = rtl8169_set_wol,
d4a3a0fc 1089 .get_strings = rtl8169_get_strings,
b9f2c044 1090 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1091 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1092};
1093
07d3f51f
FR		 1094static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1095 int bitnum, int bitval)
1da177e4
LT		 1096{
1097 int val;
1098
1099 val = mdio_read(ioaddr, reg);
1100 val = (bitval == 1) ?
1101 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1102 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1103}
1104
07d3f51f
FR		 1105static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1106 void __iomem *ioaddr)
1da177e4 1107{
0e485150
FR		 1108 /*
1109 * The driver currently handles the 8168Bf and the 8168Be identically
1110 * but they can be identified more specifically through the test below
1111 * if needed:
1112 *
1113 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1114 *
1115 * Same thing for the 8101Eb and the 8101Ec:
1116 *
1117 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1118 */
1da177e4
LT		 1119 const struct {
1120 u32 mask;
e3cf0cc0 1121 u32 val;
1da177e4
LT		 1122 int mac_version;
1123 } mac_info[] = {
e3cf0cc0
FR		 1124 /* 8168B family. */
1125 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1126 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1127 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1128 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1129
1130 /* 8168B family. */
1131 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1132 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1133 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1134 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1135
1136 /* 8101 family. */
1137 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1138 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1139 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1140 /* FIXME: where did these entries come from ? -- FR */
1141 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1142 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1143
1144 /* 8110 family. */
1145 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1146 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1147 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1148 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1149 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1150 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1151
1152 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1153 }, *p = mac_info;
1154 u32 reg;
1155
e3cf0cc0
FR		 1156 reg = RTL_R32(TxConfig);
1157 while ((reg & p->mask) != p->val)
1da177e4
LT		 1158 p++;
1159 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1160
1161 if (p->mask == 0x00000000) {
1162 struct pci_dev *pdev = tp->pci_dev;
1163
1164 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1165 }
1da177e4
LT		 1166}
1167
1168static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1169{
bcf0bf90 1170 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1171}
1172
867763c1
FR		 1173struct phy_reg {
1174 u16 reg;
1175 u16 val;
1176};
1177
1178static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1179{
1180 while (len-- > 0) {
1181 mdio_write(ioaddr, regs->reg, regs->val);
1182 regs++;
1183 }
1184}
1185
5615d9f1 1186static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1187{
1da177e4
LT		 1188 struct {
1189 u16 regs[5]; /* Beware of bit-sign propagation */
1190 } phy_magic[5] = { {
1191 { 0x0000, //w 4 15 12 0
1192 0x00a1, //w 3 15 0 00a1
1193 0x0008, //w 2 15 0 0008
1194 0x1020, //w 1 15 0 1020
1195 0x1000 } },{ //w 0 15 0 1000
1196 { 0x7000, //w 4 15 12 7
1197 0xff41, //w 3 15 0 ff41
1198 0xde60, //w 2 15 0 de60
1199 0x0140, //w 1 15 0 0140
1200 0x0077 } },{ //w 0 15 0 0077
1201 { 0xa000, //w 4 15 12 a
1202 0xdf01, //w 3 15 0 df01
1203 0xdf20, //w 2 15 0 df20
1204 0xff95, //w 1 15 0 ff95
1205 0xfa00 } },{ //w 0 15 0 fa00
1206 { 0xb000, //w 4 15 12 b
1207 0xff41, //w 3 15 0 ff41
1208 0xde20, //w 2 15 0 de20
1209 0x0140, //w 1 15 0 0140
1210 0x00bb } },{ //w 0 15 0 00bb
1211 { 0xf000, //w 4 15 12 f
1212 0xdf01, //w 3 15 0 df01
1213 0xdf20, //w 2 15 0 df20
1214 0xff95, //w 1 15 0 ff95
1215 0xbf00 } //w 0 15 0 bf00
1216 }
1217 }, *p = phy_magic;
07d3f51f 1218 unsigned int i;
1da177e4 1219
a441d7b6
FR		 1220 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1221 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1222 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1223 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1224
1225 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1226 int val, pos = 4;
1227
1228 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1229 mdio_write(ioaddr, pos, val);
1230 while (--pos >= 0)
1231 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1232 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1233 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1234 }
a441d7b6 1235 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1236}
1237
5615d9f1
FR		 1238static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1239{
a441d7b6
FR		 1240 struct phy_reg phy_reg_init[] = {
1241 { 0x1f, 0x0002 },
1242 { 0x01, 0x90d0 },
1243 { 0x1f, 0x0000 }
1244 };
1245
1246 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1 1247}
7da97ec9
FR		 1248static void rtl8168b_hw_phy_config(void __iomem *ioaddr)
1249{
1250 struct phy_reg phy_reg_init[] = {
1251 { 0x1f, 0x0000 },
1252 { 0x10, 0xf41b },
1253 { 0x1f, 0x0000 }
1254 };
1255
1256 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1257}
5615d9f1 1258
867763c1
FR		 1259static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1260{
1261 struct phy_reg phy_reg_init[] = {
1262 { 0x1f, 0x0000 },
1263 { 0x1d, 0x0f00 },
1264 { 0x1f, 0x0002 },
1265 { 0x0c, 0x1ec8 },
1266 { 0x1f, 0x0000 }
1267 };
1268
1269 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1270}
1271
1272static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1273{
1274 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1275 { 0x1f, 0x0001 },
1276 { 0x12, 0x2300 },
867763c1
FR		 1277 { 0x1f, 0x0002 },
1278 { 0x00, 0x88d4 },
1279 { 0x01, 0x82b1 },
1280 { 0x03, 0x7002 },
1281 { 0x08, 0x9e30 },
1282 { 0x09, 0x01f0 },
1283 { 0x0a, 0x5500 },
1284 { 0x0c, 0x00c8 },
1285 { 0x1f, 0x0003 },
1286 { 0x12, 0xc096 },
1287 { 0x16, 0x000a },
1288 { 0x1f, 0x0000 }
1289 };
1290
1291 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1292}
1293
7da97ec9
FR		 1294static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1295{
1296 struct phy_reg phy_reg_init[] = {
1297 { 0x1f, 0x0000 },
1298 { 0x12, 0x2300 },
1299 { 0x1f, 0x0003 },
1300 { 0x16, 0x0f0a },
1301 { 0x1f, 0x0000 },
1302 { 0x1f, 0x0002 },
1303 { 0x0c, 0x7eb8 },
1304 { 0x1f, 0x0000 }
1305 };
1306
1307 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1308}
1309
5615d9f1
FR		 1310static void rtl_hw_phy_config(struct net_device *dev)
1311{
1312 struct rtl8169_private *tp = netdev_priv(dev);
1313 void __iomem *ioaddr = tp->mmio_addr;
1314
1315 rtl8169_print_mac_version(tp);
1316
1317 switch (tp->mac_version) {
1318 case RTL_GIGA_MAC_VER_01:
1319 break;
1320 case RTL_GIGA_MAC_VER_02:
1321 case RTL_GIGA_MAC_VER_03:
1322 rtl8169s_hw_phy_config(ioaddr);
1323 break;
1324 case RTL_GIGA_MAC_VER_04:
1325 rtl8169sb_hw_phy_config(ioaddr);
1326 break;
7da97ec9
FR		 1327 case RTL_GIGA_MAC_VER_11:
1328 case RTL_GIGA_MAC_VER_12:
1329 case RTL_GIGA_MAC_VER_17:
1330 rtl8168b_hw_phy_config(ioaddr);
1331 break;
867763c1
FR		 1332 case RTL_GIGA_MAC_VER_18:
1333 rtl8168cp_hw_phy_config(ioaddr);
1334 break;
1335 case RTL_GIGA_MAC_VER_19:
1336 rtl8168c_hw_phy_config(ioaddr);
1337 break;
7da97ec9
FR		 1338 case RTL_GIGA_MAC_VER_20:
1339 rtl8168cx_hw_phy_config(ioaddr);
1340 break;
5615d9f1
FR		 1341 default:
1342 break;
1343 }
1344}
1345
1da177e4
LT		 1346static void rtl8169_phy_timer(unsigned long __opaque)
1347{
1348 struct net_device *dev = (struct net_device *)__opaque;
1349 struct rtl8169_private *tp = netdev_priv(dev);
1350 struct timer_list *timer = &tp->timer;
1351 void __iomem *ioaddr = tp->mmio_addr;
1352 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1353
bcf0bf90 1354 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1355
64e4bfb4 1356 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1357 return;
1358
1359 spin_lock_irq(&tp->lock);
1360
1361 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1362 /*
1da177e4
LT		 1363 * A busy loop could burn quite a few cycles on nowadays CPU.
1364 * Let's delay the execution of the timer for a few ticks.
1365 */
1366 timeout = HZ/10;
1367 goto out_mod_timer;
1368 }
1369
1370 if (tp->link_ok(ioaddr))
1371 goto out_unlock;
1372
b57b7e5a
SH		 1373 if (netif_msg_link(tp))
1374 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1375
1376 tp->phy_reset_enable(ioaddr);
1377
1378out_mod_timer:
1379 mod_timer(timer, jiffies + timeout);
1380out_unlock:
1381 spin_unlock_irq(&tp->lock);
1382}
1383
1384static inline void rtl8169_delete_timer(struct net_device *dev)
1385{
1386 struct rtl8169_private *tp = netdev_priv(dev);
1387 struct timer_list *timer = &tp->timer;
1388
e179bb7b 1389 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1390 return;
1391
1392 del_timer_sync(timer);
1393}
1394
1395static inline void rtl8169_request_timer(struct net_device *dev)
1396{
1397 struct rtl8169_private *tp = netdev_priv(dev);
1398 struct timer_list *timer = &tp->timer;
1399
e179bb7b 1400 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1401 return;
1402
2efa53f3 1403 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1404}
1405
1406#ifdef CONFIG_NET_POLL_CONTROLLER
1407/*
1408 * Polling 'interrupt' - used by things like netconsole to send skbs
1409 * without having to re-enable interrupts. It's not called while
1410 * the interrupt routine is executing.
1411 */
1412static void rtl8169_netpoll(struct net_device *dev)
1413{
1414 struct rtl8169_private *tp = netdev_priv(dev);
1415 struct pci_dev *pdev = tp->pci_dev;
1416
1417 disable_irq(pdev->irq);
7d12e780 1418 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1419 enable_irq(pdev->irq);
1420}
1421#endif
1422
1423static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1424 void __iomem *ioaddr)
1425{
1426 iounmap(ioaddr);
1427 pci_release_regions(pdev);
1428 pci_disable_device(pdev);
1429 free_netdev(dev);
1430}
1431
bf793295
FR		 1432static void rtl8169_phy_reset(struct net_device *dev,
1433 struct rtl8169_private *tp)
1434{
1435 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1436 unsigned int i;
bf793295
FR		 1437
1438 tp->phy_reset_enable(ioaddr);
1439 for (i = 0; i < 100; i++) {
1440 if (!tp->phy_reset_pending(ioaddr))
1441 return;
1442 msleep(1);
1443 }
1444 if (netif_msg_link(tp))
1445 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1446}
1447
4ff96fa6
FR		 1448static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1449{
1450 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1451
5615d9f1 1452 rtl_hw_phy_config(dev);
4ff96fa6
FR		 1453
1454 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1455 RTL_W8(0x82, 0x01);
1456
6dccd16b
FR		 1457 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1458
1459 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1460 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1461
bcf0bf90 1462 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1463 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1464 RTL_W8(0x82, 0x01);
1465 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1466 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1467 }
1468
bf793295
FR		 1469 rtl8169_phy_reset(dev, tp);
1470
901dda2b
FR		 1471 /*
1472 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1473 * only 8101. Don't panic.
1474 */
1475 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1476
1477 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1478 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1479}
1480
773d2021
FR		 1481static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1482{
1483 void __iomem *ioaddr = tp->mmio_addr;
1484 u32 high;
1485 u32 low;
1486
1487 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1488 high = addr[4] | (addr[5] << 8);
1489
1490 spin_lock_irq(&tp->lock);
1491
1492 RTL_W8(Cfg9346, Cfg9346_Unlock);
1493 RTL_W32(MAC0, low);
1494 RTL_W32(MAC4, high);
1495 RTL_W8(Cfg9346, Cfg9346_Lock);
1496
1497 spin_unlock_irq(&tp->lock);
1498}
1499
1500static int rtl_set_mac_address(struct net_device *dev, void *p)
1501{
1502 struct rtl8169_private *tp = netdev_priv(dev);
1503 struct sockaddr *addr = p;
1504
1505 if (!is_valid_ether_addr(addr->sa_data))
1506 return -EADDRNOTAVAIL;
1507
1508 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1509
1510 rtl_rar_set(tp, dev->dev_addr);
1511
1512 return 0;
1513}
1514
5f787a1a
FR		 1515static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1516{
1517 struct rtl8169_private *tp = netdev_priv(dev);
1518 struct mii_ioctl_data *data = if_mii(ifr);
1519
1520 if (!netif_running(dev))
1521 return -ENODEV;
1522
1523 switch (cmd) {
1524 case SIOCGMIIPHY:
1525 data->phy_id = 32; /* Internal PHY */
1526 return 0;
1527
1528 case SIOCGMIIREG:
1529 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1530 return 0;
1531
1532 case SIOCSMIIREG:
1533 if (!capable(CAP_NET_ADMIN))
1534 return -EPERM;
1535 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1536 return 0;
1537 }
1538 return -EOPNOTSUPP;
1539}
1540
0e485150
FR		 1541static const struct rtl_cfg_info {
1542 void (*hw_start)(struct net_device *);
1543 unsigned int region;
1544 unsigned int align;
1545 u16 intr_event;
1546 u16 napi_event;
fbac58fc 1547 unsigned msi;
0e485150
FR		 1548} rtl_cfg_infos [] = {
1549 [RTL_CFG_0] = {
1550 .hw_start = rtl_hw_start_8169,
1551 .region = 1,
e9f63f30 1552 .align = 0,
0e485150
FR		 1553 .intr_event = SYSErr | LinkChg | RxOverflow |
1554 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1555 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1556 .msi = 0
0e485150
FR		 1557 },
1558 [RTL_CFG_1] = {
1559 .hw_start = rtl_hw_start_8168,
1560 .region = 2,
1561 .align = 8,
1562 .intr_event = SYSErr | LinkChg | RxOverflow |
1563 TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1564 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
1565 .msi = RTL_FEATURE_MSI
0e485150
FR		 1566 },
1567 [RTL_CFG_2] = {
1568 .hw_start = rtl_hw_start_8101,
1569 .region = 2,
1570 .align = 8,
1571 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1572 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc
FR		 1573 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1574 .msi = RTL_FEATURE_MSI
0e485150
FR		 1575 }
1576};
1577
fbac58fc
FR		 1578/* Cfg9346_Unlock assumed. */
1579static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1580 const struct rtl_cfg_info *cfg)
1581{
1582 unsigned msi = 0;
1583 u8 cfg2;
1584
1585 cfg2 = RTL_R8(Config2) & ~MSIEnable;
1586 if (cfg->msi) {
1587 if (pci_enable_msi(pdev)) {
1588 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1589 } else {
1590 cfg2 |= MSIEnable;
1591 msi = RTL_FEATURE_MSI;
1592 }
1593 }
1594 RTL_W8(Config2, cfg2);
1595 return msi;
1596}
1597
1598static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1599{
1600 if (tp->features & RTL_FEATURE_MSI) {
1601 pci_disable_msi(pdev);
1602 tp->features &= ~RTL_FEATURE_MSI;
1603 }
1604}
1605
1da177e4 1606static int __devinit
4ff96fa6 1607rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1608{
0e485150
FR		 1609 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1610 const unsigned int region = cfg->region;
1da177e4 1611 struct rtl8169_private *tp;
4ff96fa6
FR		 1612 struct net_device *dev;
1613 void __iomem *ioaddr;
07d3f51f
FR		 1614 unsigned int i;
1615 int rc;
1da177e4 1616
4ff96fa6
FR		 1617 if (netif_msg_drv(&debug)) {
1618 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1619 MODULENAME, RTL8169_VERSION);
1620 }
1da177e4 1621
1da177e4 1622 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1623 if (!dev) {
b57b7e5a 1624 if (netif_msg_drv(&debug))
9b91cf9d 1625 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1626 rc = -ENOMEM;
1627 goto out;
1da177e4
LT		 1628 }
1629
1da177e4
LT		 1630 SET_NETDEV_DEV(dev, &pdev->dev);
1631 tp = netdev_priv(dev);
c4028958 1632 tp->dev = dev;
b57b7e5a 1633 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1634
1635 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1636 rc = pci_enable_device(pdev);
b57b7e5a 1637 if (rc < 0) {
2e8a538d 1638 if (netif_msg_probe(tp))
9b91cf9d 1639 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1640 goto err_out_free_dev_1;
1da177e4
LT		 1641 }
1642
1643 rc = pci_set_mwi(pdev);
1644 if (rc < 0)
4ff96fa6 1645 goto err_out_disable_2;
1da177e4 1646
1da177e4 1647 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1648 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1649 if (netif_msg_probe(tp)) {
9b91cf9d 1650 dev_err(&pdev->dev,
bcf0bf90
FR		 1651 "region #%d not an MMIO resource, aborting\n",
1652 region);
4ff96fa6 1653 }
1da177e4 1654 rc = -ENODEV;
4ff96fa6 1655 goto err_out_mwi_3;
1da177e4 1656 }
4ff96fa6 1657
1da177e4 1658 /* check for weird/broken PCI region reporting */
bcf0bf90 1659 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1660 if (netif_msg_probe(tp)) {
9b91cf9d 1661 dev_err(&pdev->dev,
4ff96fa6
FR		 1662 "Invalid PCI region size(s), aborting\n");
1663 }
1da177e4 1664 rc = -ENODEV;
4ff96fa6 1665 goto err_out_mwi_3;
1da177e4
LT		 1666 }
1667
1668 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1669 if (rc < 0) {
2e8a538d 1670 if (netif_msg_probe(tp))
9b91cf9d 1671 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1672 goto err_out_mwi_3;
1da177e4
LT		 1673 }
1674
1675 tp->cp_cmd = PCIMulRW | RxChkSum;
1676
1677 if ((sizeof(dma_addr_t) > 4) &&
1678 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1679 tp->cp_cmd |= PCIDAC;
1680 dev->features |= NETIF_F_HIGHDMA;
1681 } else {
1682 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1683 if (rc < 0) {
4ff96fa6 1684 if (netif_msg_probe(tp)) {
9b91cf9d 1685 dev_err(&pdev->dev,
4ff96fa6
FR		 1686 "DMA configuration failed.\n");
1687 }
1688 goto err_out_free_res_4;
1da177e4
LT		 1689 }
1690 }
1691
1692 pci_set_master(pdev);
1693
1694 /* ioremap MMIO region */
bcf0bf90 1695 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1696 if (!ioaddr) {
b57b7e5a 1697 if (netif_msg_probe(tp))
9b91cf9d 1698 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1699 rc = -EIO;
4ff96fa6 1700 goto err_out_free_res_4;
1da177e4
LT		 1701 }
1702
1703 /* Unneeded ? Don't mess with Mrs. Murphy. */
1704 rtl8169_irq_mask_and_ack(ioaddr);
1705
1706 /* Soft reset the chip. */
1707 RTL_W8(ChipCmd, CmdReset);
1708
1709 /* Check that the chip has finished the reset. */
07d3f51f 1710 for (i = 0; i < 100; i++) {
1da177e4
LT		 1711 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1712 break;
b518fa8e 1713 msleep_interruptible(1);
1da177e4
LT		 1714 }
1715
1716 /* Identify chip attached to board */
1717 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 1718
1719 rtl8169_print_mac_version(tp);
1da177e4
LT		 1720
1721 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1722 if (tp->mac_version == rtl_chip_info[i].mac_version)
1723 break;
1724 }
1725 if (i < 0) {
1726 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1727 if (netif_msg_probe(tp)) {
2e8a538d 1728 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1729 "unknown chip version, assuming %s\n",
1730 rtl_chip_info[0].name);
b57b7e5a 1731 }
1da177e4
LT		 1732 i++;
1733 }
1734 tp->chipset = i;
1735
5d06a99f
FR		 1736 RTL_W8(Cfg9346, Cfg9346_Unlock);
1737 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1738 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
fbac58fc 1739 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 1740 RTL_W8(Cfg9346, Cfg9346_Lock);
1741
1da177e4
LT		 1742 if (RTL_R8(PHYstatus) & TBI_Enable) {
1743 tp->set_speed = rtl8169_set_speed_tbi;
1744 tp->get_settings = rtl8169_gset_tbi;
1745 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1746 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1747 tp->link_ok = rtl8169_tbi_link_ok;
1748
64e4bfb4 1749 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1750 } else {
1751 tp->set_speed = rtl8169_set_speed_xmii;
1752 tp->get_settings = rtl8169_gset_xmii;
1753 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1754 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1755 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1756
1757 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1758 }
1759
1760 /* Get MAC address. FIXME: read EEPROM */
1761 for (i = 0; i < MAC_ADDR_LEN; i++)
1762 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1763 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1764
1765 dev->open = rtl8169_open;
1766 dev->hard_start_xmit = rtl8169_start_xmit;
1767 dev->get_stats = rtl8169_get_stats;
1768 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1769 dev->stop = rtl8169_close;
1770 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1771 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1772 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1773 dev->irq = pdev->irq;
1774 dev->base_addr = (unsigned long) ioaddr;
1775 dev->change_mtu = rtl8169_change_mtu;
773d2021 1776 dev->set_mac_address = rtl_set_mac_address;
1da177e4
LT		 1777
1778#ifdef CONFIG_R8169_NAPI
bea3348e 1779 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 1780#endif
1781
1782#ifdef CONFIG_R8169_VLAN
1783 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1784 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1785#endif
1786
1787#ifdef CONFIG_NET_POLL_CONTROLLER
1788 dev->poll_controller = rtl8169_netpoll;
1789#endif
1790
1791 tp->intr_mask = 0xffff;
1792 tp->pci_dev = pdev;
1793 tp->mmio_addr = ioaddr;
0e485150
FR		 1794 tp->align = cfg->align;
1795 tp->hw_start = cfg->hw_start;
1796 tp->intr_event = cfg->intr_event;
1797 tp->napi_event = cfg->napi_event;
1da177e4 1798
2efa53f3
FR		 1799 init_timer(&tp->timer);
1800 tp->timer.data = (unsigned long) dev;
1801 tp->timer.function = rtl8169_phy_timer;
1802
1da177e4
LT		 1803 spin_lock_init(&tp->lock);
1804
1805 rc = register_netdev(dev);
4ff96fa6 1806 if (rc < 0)
fbac58fc 1807 goto err_out_msi_5;
1da177e4
LT		 1808
1809 pci_set_drvdata(pdev, dev);
1810
b57b7e5a 1811 if (netif_msg_probe(tp)) {
96b9709c
FR		 1812 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1813
b57b7e5a
SH		 1814 printk(KERN_INFO "%s: %s at 0x%lx, "
1815 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1816 "XID %08x IRQ %d\n",
b57b7e5a 1817 dev->name,
bcf0bf90 1818 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1819 dev->base_addr,
1820 dev->dev_addr[0], dev->dev_addr[1],
1821 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1822 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1823 }
1da177e4 1824
4ff96fa6 1825 rtl8169_init_phy(dev, tp);
1da177e4 1826
4ff96fa6
FR		 1827out:
1828 return rc;
1da177e4 1829
fbac58fc
FR		 1830err_out_msi_5:
1831 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 1832 iounmap(ioaddr);
1833err_out_free_res_4:
1834 pci_release_regions(pdev);
1835err_out_mwi_3:
1836 pci_clear_mwi(pdev);
1837err_out_disable_2:
1838 pci_disable_device(pdev);
1839err_out_free_dev_1:
1840 free_netdev(dev);
1841 goto out;
1da177e4
LT		 1842}
1843
07d3f51f 1844static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1845{
1846 struct net_device *dev = pci_get_drvdata(pdev);
1847 struct rtl8169_private *tp = netdev_priv(dev);
1848
eb2a021c
FR		 1849 flush_scheduled_work();
1850
1da177e4 1851 unregister_netdev(dev);
fbac58fc 1852 rtl_disable_msi(pdev, tp);
1da177e4
LT		 1853 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1854 pci_set_drvdata(pdev, NULL);
1855}
1856
1da177e4
LT		 1857static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1858 struct net_device *dev)
1859{
1860 unsigned int mtu = dev->mtu;
1861
1862 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1863}
1864
1865static int rtl8169_open(struct net_device *dev)
1866{
1867 struct rtl8169_private *tp = netdev_priv(dev);
1868 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1869 int retval = -ENOMEM;
1da177e4 1870
1da177e4 1871
99f252b0 1872 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1873
1874 /*
1875 * Rx and Tx desscriptors needs 256 bytes alignment.
1876 * pci_alloc_consistent provides more.
1877 */
1878 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1879 &tp->TxPhyAddr);
1880 if (!tp->TxDescArray)
99f252b0 1881 goto out;
1da177e4
LT		 1882
1883 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1884 &tp->RxPhyAddr);
1885 if (!tp->RxDescArray)
99f252b0 1886 goto err_free_tx_0;
1da177e4
LT		 1887
1888 retval = rtl8169_init_ring(dev);
1889 if (retval < 0)
99f252b0 1890 goto err_free_rx_1;
1da177e4 1891
c4028958 1892 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1893
99f252b0
FR		 1894 smp_mb();
1895
fbac58fc
FR		 1896 retval = request_irq(dev->irq, rtl8169_interrupt,
1897 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 1898 dev->name, dev);
1899 if (retval < 0)
1900 goto err_release_ring_2;
1901
bea3348e
SH		 1902#ifdef CONFIG_R8169_NAPI
1903 napi_enable(&tp->napi);
1904#endif
1905
07ce4064 1906 rtl_hw_start(dev);
1da177e4
LT		 1907
1908 rtl8169_request_timer(dev);
1909
1910 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1911out:
1912 return retval;
1913
99f252b0
FR		 1914err_release_ring_2:
1915 rtl8169_rx_clear(tp);
1916err_free_rx_1:
1da177e4
LT		 1917 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1918 tp->RxPhyAddr);
99f252b0 1919err_free_tx_0:
1da177e4
LT		 1920 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1921 tp->TxPhyAddr);
1da177e4
LT		 1922 goto out;
1923}
1924
1925static void rtl8169_hw_reset(void __iomem *ioaddr)
1926{
1927 /* Disable interrupts */
1928 rtl8169_irq_mask_and_ack(ioaddr);
1929
1930 /* Reset the chipset */
1931 RTL_W8(ChipCmd, CmdReset);
1932
1933 /* PCI commit */
1934 RTL_R8(ChipCmd);
1935}
1936
7f796d83 1937static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1938{
1939 void __iomem *ioaddr = tp->mmio_addr;
1940 u32 cfg = rtl8169_rx_config;
1941
1942 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1943 RTL_W32(RxConfig, cfg);
1944
1945 /* Set DMA burst size and Interframe Gap Time */
1946 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1947 (InterFrameGap << TxInterFrameGapShift));
1948}
1949
07ce4064 1950static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1951{
1952 struct rtl8169_private *tp = netdev_priv(dev);
1953 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1954 unsigned int i;
1da177e4
LT		 1955
1956 /* Soft reset the chip. */
1957 RTL_W8(ChipCmd, CmdReset);
1958
1959 /* Check that the chip has finished the reset. */
07d3f51f 1960 for (i = 0; i < 100; i++) {
1da177e4
LT		 1961 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1962 break;
b518fa8e 1963 msleep_interruptible(1);
1da177e4
LT		 1964 }
1965
07ce4064
FR		 1966 tp->hw_start(dev);
1967
07ce4064
FR		 1968 netif_start_queue(dev);
1969}
1970
1971
7f796d83
FR		 1972static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1973 void __iomem *ioaddr)
1974{
1975 /*
1976 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1977 * register to be written before TxDescAddrLow to work.
1978 * Switching from MMIO to I/O access fixes the issue as well.
1979 */
1980 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1981 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1982 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1983 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1984}
1985
1986static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1987{
1988 u16 cmd;
1989
1990 cmd = RTL_R16(CPlusCmd);
1991 RTL_W16(CPlusCmd, cmd);
1992 return cmd;
1993}
1994
1995static void rtl_set_rx_max_size(void __iomem *ioaddr)
1996{
1997 /* Low hurts. Let's disable the filtering. */
1998 RTL_W16(RxMaxSize, 16383);
1999}
2000
6dccd16b
FR		 2001static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2002{
2003 struct {
2004 u32 mac_version;
2005 u32 clk;
2006 u32 val;
2007 } cfg2_info [] = {
2008 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2009 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2010 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2011 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2012 }, *p = cfg2_info;
2013 unsigned int i;
2014 u32 clk;
2015
2016 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2017 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
2018 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2019 RTL_W32(0x7c, p->val);
2020 break;
2021 }
2022 }
2023}
2024
07ce4064
FR		 2025static void rtl_hw_start_8169(struct net_device *dev)
2026{
2027 struct rtl8169_private *tp = netdev_priv(dev);
2028 void __iomem *ioaddr = tp->mmio_addr;
2029 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2030
9cb427b6
FR		 2031 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2032 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2033 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2034 }
2035
1da177e4 2036 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2037 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2038 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2039 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2040 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2041 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2042
1da177e4
LT		 2043 RTL_W8(EarlyTxThres, EarlyTxThld);
2044
7f796d83 2045 rtl_set_rx_max_size(ioaddr);
1da177e4 2046
c946b304
FR		 2047 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2048 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2049 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2050 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2051 rtl_set_rx_tx_config_registers(tp);
1da177e4 2052
7f796d83 2053 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2054
bcf0bf90
FR		 2055 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2056 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2057 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2058 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2059 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2060 }
2061
bcf0bf90
FR		 2062 RTL_W16(CPlusCmd, tp->cp_cmd);
2063
6dccd16b
FR		 2064 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2065
1da177e4
LT		 2066 /*
2067 * Undocumented corner. Supposedly:
2068 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2069 */
2070 RTL_W16(IntrMitigate, 0x0000);
2071
7f796d83 2072 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2073
c946b304
FR		 2074 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2075 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2076 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2077 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2078 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2079 rtl_set_rx_tx_config_registers(tp);
2080 }
2081
1da177e4 2082 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2083
2084 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2085 RTL_R8(IntrMask);
1da177e4
LT		 2086
2087 RTL_W32(RxMissed, 0);
2088
07ce4064 2089 rtl_set_rx_mode(dev);
1da177e4
LT		 2090
2091 /* no early-rx interrupts */
2092 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2093
2094 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2095 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2096}
1da177e4 2097
07ce4064
FR		 2098static void rtl_hw_start_8168(struct net_device *dev)
2099{
2dd99530
FR		 2100 struct rtl8169_private *tp = netdev_priv(dev);
2101 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 2102 struct pci_dev *pdev = tp->pci_dev;
2103 u8 ctl;
2dd99530
FR		 2104
2105 RTL_W8(Cfg9346, Cfg9346_Unlock);
2106
2107 RTL_W8(EarlyTxThres, EarlyTxThld);
2108
2109 rtl_set_rx_max_size(ioaddr);
2110
0e485150
FR		 2111 rtl_set_rx_tx_config_registers(tp);
2112
2113 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2114
2115 RTL_W16(CPlusCmd, tp->cp_cmd);
2116
0e485150
FR		 2117 /* Tx performance tweak. */
2118 pci_read_config_byte(pdev, 0x69, &ctl);
2119 ctl = (ctl & ~0x70) | 0x50;
2120 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 2121
0e485150 2122 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2123
0e485150
FR		 2124 /* Work around for RxFIFO overflow. */
2125 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2126 tp->intr_event |= RxFIFOOver | PCSTimeout;
2127 tp->intr_event &= ~RxOverflow;
2128 }
2129
2130 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2131
2132 RTL_W8(Cfg9346, Cfg9346_Lock);
2133
2134 RTL_R8(IntrMask);
2135
2136 RTL_W32(RxMissed, 0);
2137
2138 rtl_set_rx_mode(dev);
2139
0e485150
FR		 2140 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2141
2dd99530 2142 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2143
0e485150 2144 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2145}
1da177e4 2146
07ce4064
FR		 2147static void rtl_hw_start_8101(struct net_device *dev)
2148{
cdf1a608
FR		 2149 struct rtl8169_private *tp = netdev_priv(dev);
2150 void __iomem *ioaddr = tp->mmio_addr;
2151 struct pci_dev *pdev = tp->pci_dev;
2152
e3cf0cc0
FR		 2153 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2154 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
cdf1a608
FR		 2155 pci_write_config_word(pdev, 0x68, 0x00);
2156 pci_write_config_word(pdev, 0x69, 0x08);
2157 }
2158
2159 RTL_W8(Cfg9346, Cfg9346_Unlock);
2160
2161 RTL_W8(EarlyTxThres, EarlyTxThld);
2162
2163 rtl_set_rx_max_size(ioaddr);
2164
2165 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2166
2167 RTL_W16(CPlusCmd, tp->cp_cmd);
2168
2169 RTL_W16(IntrMitigate, 0x0000);
2170
2171 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2172
2173 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2174 rtl_set_rx_tx_config_registers(tp);
2175
2176 RTL_W8(Cfg9346, Cfg9346_Lock);
2177
2178 RTL_R8(IntrMask);
2179
2180 RTL_W32(RxMissed, 0);
2181
2182 rtl_set_rx_mode(dev);
2183
0e485150
FR		 2184 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2185
cdf1a608 2186 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2187
0e485150 2188 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2189}
2190
2191static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2192{
2193 struct rtl8169_private *tp = netdev_priv(dev);
2194 int ret = 0;
2195
2196 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2197 return -EINVAL;
2198
2199 dev->mtu = new_mtu;
2200
2201 if (!netif_running(dev))
2202 goto out;
2203
2204 rtl8169_down(dev);
2205
2206 rtl8169_set_rxbufsize(tp, dev);
2207
2208 ret = rtl8169_init_ring(dev);
2209 if (ret < 0)
2210 goto out;
2211
bea3348e
SH		 2212#ifdef CONFIG_R8169_NAPI
2213 napi_enable(&tp->napi);
2214#endif
1da177e4 2215
07ce4064 2216 rtl_hw_start(dev);
1da177e4
LT		 2217
2218 rtl8169_request_timer(dev);
2219
2220out:
2221 return ret;
2222}
2223
2224static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2225{
2226 desc->addr = 0x0badbadbadbadbadull;
2227 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2228}
2229
2230static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2231 struct sk_buff **sk_buff, struct RxDesc *desc)
2232{
2233 struct pci_dev *pdev = tp->pci_dev;
2234
2235 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2236 PCI_DMA_FROMDEVICE);
2237 dev_kfree_skb(*sk_buff);
2238 *sk_buff = NULL;
2239 rtl8169_make_unusable_by_asic(desc);
2240}
2241
2242static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2243{
2244 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2245
2246 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2247}
2248
2249static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2250 u32 rx_buf_sz)
2251{
2252 desc->addr = cpu_to_le64(mapping);
2253 wmb();
2254 rtl8169_mark_to_asic(desc, rx_buf_sz);
2255}
2256
15d31758
SH		 2257static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2258 struct net_device *dev,
2259 struct RxDesc *desc, int rx_buf_sz,
2260 unsigned int align)
1da177e4
LT		 2261{
2262 struct sk_buff *skb;
2263 dma_addr_t mapping;
e9f63f30 2264 unsigned int pad;
1da177e4 2265
e9f63f30
FR		 2266 pad = align ? align : NET_IP_ALIGN;
2267
2268 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2269 if (!skb)
2270 goto err_out;
2271
e9f63f30 2272 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2273
689be439 2274 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2275 PCI_DMA_FROMDEVICE);
2276
2277 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2278out:
15d31758 2279 return skb;
1da177e4
LT		 2280
2281err_out:
1da177e4
LT		 2282 rtl8169_make_unusable_by_asic(desc);
2283 goto out;
2284}
2285
2286static void rtl8169_rx_clear(struct rtl8169_private *tp)
2287{
07d3f51f 2288 unsigned int i;
1da177e4
LT		 2289
2290 for (i = 0; i < NUM_RX_DESC; i++) {
2291 if (tp->Rx_skbuff[i]) {
2292 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2293 tp->RxDescArray + i);
2294 }
2295 }
2296}
2297
2298static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2299 u32 start, u32 end)
2300{
2301 u32 cur;
5b0384f4 2302
4ae47c2d 2303 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2304 struct sk_buff *skb;
2305 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2306
4ae47c2d
FR		 2307 WARN_ON((s32)(end - cur) < 0);
2308
1da177e4
LT		 2309 if (tp->Rx_skbuff[i])
2310 continue;
bcf0bf90 2311
15d31758
SH		 2312 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2313 tp->RxDescArray + i,
2314 tp->rx_buf_sz, tp->align);
2315 if (!skb)
1da177e4 2316 break;
15d31758
SH		 2317
2318 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2319 }
2320 return cur - start;
2321}
2322
2323static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2324{
2325 desc->opts1 |= cpu_to_le32(RingEnd);
2326}
2327
2328static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2329{
2330 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2331}
2332
2333static int rtl8169_init_ring(struct net_device *dev)
2334{
2335 struct rtl8169_private *tp = netdev_priv(dev);
2336
2337 rtl8169_init_ring_indexes(tp);
2338
2339 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2340 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2341
2342 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2343 goto err_out;
2344
2345 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2346
2347 return 0;
2348
2349err_out:
2350 rtl8169_rx_clear(tp);
2351 return -ENOMEM;
2352}
2353
2354static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2355 struct TxDesc *desc)
2356{
2357 unsigned int len = tx_skb->len;
2358
2359 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2360 desc->opts1 = 0x00;
2361 desc->opts2 = 0x00;
2362 desc->addr = 0x00;
2363 tx_skb->len = 0;
2364}
2365
2366static void rtl8169_tx_clear(struct rtl8169_private *tp)
2367{
2368 unsigned int i;
2369
2370 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2371 unsigned int entry = i % NUM_TX_DESC;
2372 struct ring_info *tx_skb = tp->tx_skb + entry;
2373 unsigned int len = tx_skb->len;
2374
2375 if (len) {
2376 struct sk_buff *skb = tx_skb->skb;
2377
2378 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2379 tp->TxDescArray + entry);
2380 if (skb) {
2381 dev_kfree_skb(skb);
2382 tx_skb->skb = NULL;
2383 }
cebf8cc7 2384 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2385 }
2386 }
2387 tp->cur_tx = tp->dirty_tx = 0;
2388}
2389
c4028958 2390static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2391{
2392 struct rtl8169_private *tp = netdev_priv(dev);
2393
c4028958 2394 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2395 schedule_delayed_work(&tp->task, 4);
2396}
2397
2398static void rtl8169_wait_for_quiescence(struct net_device *dev)
2399{
2400 struct rtl8169_private *tp = netdev_priv(dev);
2401 void __iomem *ioaddr = tp->mmio_addr;
2402
2403 synchronize_irq(dev->irq);
2404
2405 /* Wait for any pending NAPI task to complete */
bea3348e
SH		 2406#ifdef CONFIG_R8169_NAPI
2407 napi_disable(&tp->napi);
2408#endif
1da177e4
LT		 2409
2410 rtl8169_irq_mask_and_ack(ioaddr);
2411
bea3348e
SH		 2412#ifdef CONFIG_R8169_NAPI
2413 napi_enable(&tp->napi);
2414#endif
1da177e4
LT		 2415}
2416
c4028958 2417static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2418{
c4028958
DH		 2419 struct rtl8169_private *tp =
2420 container_of(work, struct rtl8169_private, task.work);
2421 struct net_device *dev = tp->dev;
1da177e4
LT		 2422 int ret;
2423
eb2a021c
FR		 2424 rtnl_lock();
2425
2426 if (!netif_running(dev))
2427 goto out_unlock;
2428
2429 rtl8169_wait_for_quiescence(dev);
2430 rtl8169_close(dev);
1da177e4
LT		 2431
2432 ret = rtl8169_open(dev);
2433 if (unlikely(ret < 0)) {
07d3f51f 2434 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 2435 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 2436 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2437 }
2438 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2439 }
eb2a021c
FR		 2440
2441out_unlock:
2442 rtnl_unlock();
1da177e4
LT		 2443}
2444
c4028958 2445static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2446{
c4028958
DH		 2447 struct rtl8169_private *tp =
2448 container_of(work, struct rtl8169_private, task.work);
2449 struct net_device *dev = tp->dev;
1da177e4 2450
eb2a021c
FR		 2451 rtnl_lock();
2452
1da177e4 2453 if (!netif_running(dev))
eb2a021c 2454 goto out_unlock;
1da177e4
LT		 2455
2456 rtl8169_wait_for_quiescence(dev);
2457
bea3348e 2458 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 2459 rtl8169_tx_clear(tp);
2460
2461 if (tp->dirty_rx == tp->cur_rx) {
2462 rtl8169_init_ring_indexes(tp);
07ce4064 2463 rtl_hw_start(dev);
1da177e4 2464 netif_wake_queue(dev);
cebf8cc7 2465 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 2466 } else {
07d3f51f 2467 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 2468 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 2469 dev->name);
1da177e4
LT		 2470 }
2471 rtl8169_schedule_work(dev, rtl8169_reset_task);
2472 }
eb2a021c
FR		 2473
2474out_unlock:
2475 rtnl_unlock();
1da177e4
LT		 2476}
2477
2478static void rtl8169_tx_timeout(struct net_device *dev)
2479{
2480 struct rtl8169_private *tp = netdev_priv(dev);
2481
2482 rtl8169_hw_reset(tp->mmio_addr);
2483
2484 /* Let's wait a bit while any (async) irq lands on */
2485 rtl8169_schedule_work(dev, rtl8169_reset_task);
2486}
2487
2488static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2489 u32 opts1)
2490{
2491 struct skb_shared_info *info = skb_shinfo(skb);
2492 unsigned int cur_frag, entry;
a6343afb 2493 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2494
2495 entry = tp->cur_tx;
2496 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2497 skb_frag_t *frag = info->frags + cur_frag;
2498 dma_addr_t mapping;
2499 u32 status, len;
2500 void *addr;
2501
2502 entry = (entry + 1) % NUM_TX_DESC;
2503
2504 txd = tp->TxDescArray + entry;
2505 len = frag->size;
2506 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2507 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2508
2509 /* anti gcc 2.95.3 bugware (sic) */
2510 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2511
2512 txd->opts1 = cpu_to_le32(status);
2513 txd->addr = cpu_to_le64(mapping);
2514
2515 tp->tx_skb[entry].len = len;
2516 }
2517
2518 if (cur_frag) {
2519 tp->tx_skb[entry].skb = skb;
2520 txd->opts1 |= cpu_to_le32(LastFrag);
2521 }
2522
2523 return cur_frag;
2524}
2525
2526static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2527{
2528 if (dev->features & NETIF_F_TSO) {
7967168c 2529 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2530
2531 if (mss)
2532 return LargeSend | ((mss & MSSMask) << MSSShift);
2533 }
84fa7933 2534 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2535 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2536
2537 if (ip->protocol == IPPROTO_TCP)
2538 return IPCS | TCPCS;
2539 else if (ip->protocol == IPPROTO_UDP)
2540 return IPCS | UDPCS;
2541 WARN_ON(1); /* we need a WARN() */
2542 }
2543 return 0;
2544}
2545
2546static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2547{
2548 struct rtl8169_private *tp = netdev_priv(dev);
2549 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2550 struct TxDesc *txd = tp->TxDescArray + entry;
2551 void __iomem *ioaddr = tp->mmio_addr;
2552 dma_addr_t mapping;
2553 u32 status, len;
2554 u32 opts1;
188f4af0 2555 int ret = NETDEV_TX_OK;
5b0384f4 2556
1da177e4 2557 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2558 if (netif_msg_drv(tp)) {
2559 printk(KERN_ERR
2560 "%s: BUG! Tx Ring full when queue awake!\n",
2561 dev->name);
2562 }
1da177e4
LT		 2563 goto err_stop;
2564 }
2565
2566 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2567 goto err_stop;
2568
2569 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2570
2571 frags = rtl8169_xmit_frags(tp, skb, opts1);
2572 if (frags) {
2573 len = skb_headlen(skb);
2574 opts1 |= FirstFrag;
2575 } else {
2576 len = skb->len;
2577
2578 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2579 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2580 goto err_update_stats;
2581 len = ETH_ZLEN;
2582 }
2583
2584 opts1 |= FirstFrag | LastFrag;
2585 tp->tx_skb[entry].skb = skb;
2586 }
2587
2588 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2589
2590 tp->tx_skb[entry].len = len;
2591 txd->addr = cpu_to_le64(mapping);
2592 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2593
2594 wmb();
2595
2596 /* anti gcc 2.95.3 bugware (sic) */
2597 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2598 txd->opts1 = cpu_to_le32(status);
2599
2600 dev->trans_start = jiffies;
2601
2602 tp->cur_tx += frags + 1;
2603
2604 smp_wmb();
2605
275391a4 2606 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2607
2608 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2609 netif_stop_queue(dev);
2610 smp_rmb();
2611 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2612 netif_wake_queue(dev);
2613 }
2614
2615out:
2616 return ret;
2617
2618err_stop:
2619 netif_stop_queue(dev);
188f4af0 2620 ret = NETDEV_TX_BUSY;
1da177e4 2621err_update_stats:
cebf8cc7 2622 dev->stats.tx_dropped++;
1da177e4
LT		 2623 goto out;
2624}
2625
2626static void rtl8169_pcierr_interrupt(struct net_device *dev)
2627{
2628 struct rtl8169_private *tp = netdev_priv(dev);
2629 struct pci_dev *pdev = tp->pci_dev;
2630 void __iomem *ioaddr = tp->mmio_addr;
2631 u16 pci_status, pci_cmd;
2632
2633 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2634 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2635
b57b7e5a
SH		 2636 if (netif_msg_intr(tp)) {
2637 printk(KERN_ERR
2638 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2639 dev->name, pci_cmd, pci_status);
2640 }
1da177e4
LT		 2641
2642 /*
2643 * The recovery sequence below admits a very elaborated explanation:
2644 * - it seems to work;
d03902b8
FR		 2645 * - I did not see what else could be done;
2646 * - it makes iop3xx happy.
1da177e4
LT		 2647 *
2648 * Feel free to adjust to your needs.
2649 */
a27993f3 2650 if (pdev->broken_parity_status)
d03902b8
FR		 2651 pci_cmd &= ~PCI_COMMAND_PARITY;
2652 else
2653 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2654
2655 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2656
2657 pci_write_config_word(pdev, PCI_STATUS,
2658 pci_status & (PCI_STATUS_DETECTED_PARITY |
2659 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2660 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2661
2662 /* The infamous DAC f*ckup only happens at boot time */
2663 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2664 if (netif_msg_intr(tp))
2665 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2666 tp->cp_cmd &= ~PCIDAC;
2667 RTL_W16(CPlusCmd, tp->cp_cmd);
2668 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2669 }
2670
2671 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2672
2673 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2674}
2675
07d3f51f
FR		 2676static void rtl8169_tx_interrupt(struct net_device *dev,
2677 struct rtl8169_private *tp,
2678 void __iomem *ioaddr)
1da177e4
LT		 2679{
2680 unsigned int dirty_tx, tx_left;
2681
1da177e4
LT		 2682 dirty_tx = tp->dirty_tx;
2683 smp_rmb();
2684 tx_left = tp->cur_tx - dirty_tx;
2685
2686 while (tx_left > 0) {
2687 unsigned int entry = dirty_tx % NUM_TX_DESC;
2688 struct ring_info *tx_skb = tp->tx_skb + entry;
2689 u32 len = tx_skb->len;
2690 u32 status;
2691
2692 rmb();
2693 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2694 if (status & DescOwn)
2695 break;
2696
cebf8cc7
FR		 2697 dev->stats.tx_bytes += len;
2698 dev->stats.tx_packets++;
1da177e4
LT		 2699
2700 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2701
2702 if (status & LastFrag) {
2703 dev_kfree_skb_irq(tx_skb->skb);
2704 tx_skb->skb = NULL;
2705 }
2706 dirty_tx++;
2707 tx_left--;
2708 }
2709
2710 if (tp->dirty_tx != dirty_tx) {
2711 tp->dirty_tx = dirty_tx;
2712 smp_wmb();
2713 if (netif_queue_stopped(dev) &&
2714 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2715 netif_wake_queue(dev);
2716 }
d78ae2dc
FR		 2717 /*
2718 * 8168 hack: TxPoll requests are lost when the Tx packets are
2719 * too close. Let's kick an extra TxPoll request when a burst
2720 * of start_xmit activity is detected (if it is not detected,
2721 * it is slow enough). -- FR
2722 */
2723 smp_rmb();
2724 if (tp->cur_tx != dirty_tx)
2725 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 2726 }
2727}
2728
126fa4b9
FR		 2729static inline int rtl8169_fragmented_frame(u32 status)
2730{
2731 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2732}
2733
1da177e4
LT		 2734static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2735{
2736 u32 opts1 = le32_to_cpu(desc->opts1);
2737 u32 status = opts1 & RxProtoMask;
2738
2739 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2740 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2741 ((status == RxProtoIP) && !(opts1 & IPFail)))
2742 skb->ip_summed = CHECKSUM_UNNECESSARY;
2743 else
2744 skb->ip_summed = CHECKSUM_NONE;
2745}
2746
07d3f51f
FR		 2747static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2748 struct rtl8169_private *tp, int pkt_size,
2749 dma_addr_t addr)
1da177e4 2750{
b449655f
SH		 2751 struct sk_buff *skb;
2752 bool done = false;
1da177e4 2753
b449655f
SH		 2754 if (pkt_size >= rx_copybreak)
2755 goto out;
1da177e4 2756
07d3f51f 2757 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2758 if (!skb)
2759 goto out;
2760
07d3f51f
FR		 2761 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2762 PCI_DMA_FROMDEVICE);
86402234 2763 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2764 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2765 *sk_buff = skb;
2766 done = true;
2767out:
2768 return done;
1da177e4
LT		 2769}
2770
07d3f51f
FR		 2771static int rtl8169_rx_interrupt(struct net_device *dev,
2772 struct rtl8169_private *tp,
bea3348e 2773 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 2774{
2775 unsigned int cur_rx, rx_left;
2776 unsigned int delta, count;
2777
1da177e4
LT		 2778 cur_rx = tp->cur_rx;
2779 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
bea3348e 2780 rx_left = rtl8169_rx_quota(rx_left, budget);
1da177e4 2781
4dcb7d33 2782 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2783 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2784 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2785 u32 status;
2786
2787 rmb();
126fa4b9 2788 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2789
2790 if (status & DescOwn)
2791 break;
4dcb7d33 2792 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2793 if (netif_msg_rx_err(tp)) {
2794 printk(KERN_INFO
2795 "%s: Rx ERROR. status = %08x\n",
2796 dev->name, status);
2797 }
cebf8cc7 2798 dev->stats.rx_errors++;
1da177e4 2799 if (status & (RxRWT | RxRUNT))
cebf8cc7 2800 dev->stats.rx_length_errors++;
1da177e4 2801 if (status & RxCRC)
cebf8cc7 2802 dev->stats.rx_crc_errors++;
9dccf611
FR		 2803 if (status & RxFOVF) {
2804 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 2805 dev->stats.rx_fifo_errors++;
9dccf611 2806 }
126fa4b9 2807 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2808 } else {
1da177e4 2809 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2810 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2811 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2812 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2813
126fa4b9
FR		 2814 /*
2815 * The driver does not support incoming fragmented
2816 * frames. They are seen as a symptom of over-mtu
2817 * sized frames.
2818 */
2819 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 2820 dev->stats.rx_dropped++;
2821 dev->stats.rx_length_errors++;
126fa4b9 2822 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2823 continue;
126fa4b9
FR		 2824 }
2825
1da177e4 2826 rtl8169_rx_csum(skb, desc);
bcf0bf90 2827
07d3f51f 2828 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2829 pci_dma_sync_single_for_device(pdev, addr,
2830 pkt_size, PCI_DMA_FROMDEVICE);
2831 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2832 } else {
2833 pci_unmap_single(pdev, addr, pkt_size,
2834 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2835 tp->Rx_skbuff[entry] = NULL;
2836 }
2837
1da177e4
LT		 2838 skb_put(skb, pkt_size);
2839 skb->protocol = eth_type_trans(skb, dev);
2840
2841 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2842 rtl8169_rx_skb(skb);
2843
2844 dev->last_rx = jiffies;
cebf8cc7
FR		 2845 dev->stats.rx_bytes += pkt_size;
2846 dev->stats.rx_packets++;
1da177e4 2847 }
6dccd16b
FR		 2848
2849 /* Work around for AMD plateform. */
2850 if ((desc->opts2 & 0xfffe000) &&
2851 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2852 desc->opts2 = 0;
2853 cur_rx++;
2854 }
1da177e4
LT		 2855 }
2856
2857 count = cur_rx - tp->cur_rx;
2858 tp->cur_rx = cur_rx;
2859
2860 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2861 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2862 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2863 tp->dirty_rx += delta;
2864
2865 /*
2866 * FIXME: until there is periodic timer to try and refill the ring,
2867 * a temporary shortage may definitely kill the Rx process.
2868 * - disable the asic to try and avoid an overflow and kick it again
2869 * after refill ?
2870 * - how do others driver handle this condition (Uh oh...).
2871 */
b57b7e5a 2872 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2873 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2874
2875 return count;
2876}
2877
07d3f51f 2878static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2879{
07d3f51f 2880 struct net_device *dev = dev_instance;
1da177e4
LT		 2881 struct rtl8169_private *tp = netdev_priv(dev);
2882 int boguscnt = max_interrupt_work;
2883 void __iomem *ioaddr = tp->mmio_addr;
2884 int status;
2885 int handled = 0;
2886
2887 do {
2888 status = RTL_R16(IntrStatus);
2889
2890 /* hotplug/major error/no more work/shared irq */
2891 if ((status == 0xFFFF) || !status)
2892 break;
2893
2894 handled = 1;
2895
2896 if (unlikely(!netif_running(dev))) {
2897 rtl8169_asic_down(ioaddr);
2898 goto out;
2899 }
2900
2901 status &= tp->intr_mask;
2902 RTL_W16(IntrStatus,
2903 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2904
0e485150
FR		 2905 if (!(status & tp->intr_event))
2906 break;
2907
2908 /* Work around for rx fifo overflow */
2909 if (unlikely(status & RxFIFOOver) &&
2910 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2911 netif_stop_queue(dev);
2912 rtl8169_tx_timeout(dev);
1da177e4 2913 break;
0e485150 2914 }
1da177e4
LT		 2915
2916 if (unlikely(status & SYSErr)) {
2917 rtl8169_pcierr_interrupt(dev);
2918 break;
2919 }
2920
2921 if (status & LinkChg)
2922 rtl8169_check_link_status(dev, tp, ioaddr);
2923
2924#ifdef CONFIG_R8169_NAPI
313b0305
FR		 2925 if (status & tp->napi_event) {
2926 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2927 tp->intr_mask = ~tp->napi_event;
2928
bea3348e
SH		 2929 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2930 __netif_rx_schedule(dev, &tp->napi);
313b0305
FR		 2931 else if (netif_msg_intr(tp)) {
2932 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2933 dev->name, status);
2934 }
1da177e4
LT		 2935 }
2936 break;
2937#else
2938 /* Rx interrupt */
07d3f51f 2939 if (status & (RxOK | RxOverflow | RxFIFOOver))
bea3348e 2940 rtl8169_rx_interrupt(dev, tp, ioaddr, ~(u32)0);
07d3f51f 2941
1da177e4
LT		 2942 /* Tx interrupt */
2943 if (status & (TxOK | TxErr))
2944 rtl8169_tx_interrupt(dev, tp, ioaddr);
2945#endif
2946
2947 boguscnt--;
2948 } while (boguscnt > 0);
2949
2950 if (boguscnt <= 0) {
7c8b2eb4 2951 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2952 printk(KERN_WARNING
2953 "%s: Too much work at interrupt!\n", dev->name);
2954 }
1da177e4
LT		 2955 /* Clear all interrupt sources. */
2956 RTL_W16(IntrStatus, 0xffff);
2957 }
2958out:
2959 return IRQ_RETVAL(handled);
2960}
2961
2962#ifdef CONFIG_R8169_NAPI
bea3348e 2963static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 2964{
bea3348e
SH		 2965 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2966 struct net_device *dev = tp->dev;
1da177e4 2967 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 2968 int work_done;
1da177e4 2969
bea3348e 2970 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 2971 rtl8169_tx_interrupt(dev, tp, ioaddr);
2972
bea3348e
SH		 2973 if (work_done < budget) {
2974 netif_rx_complete(dev, napi);
1da177e4
LT		 2975 tp->intr_mask = 0xffff;
2976 /*
2977 * 20040426: the barrier is not strictly required but the
2978 * behavior of the irq handler could be less predictable
2979 * without it. Btw, the lack of flush for the posted pci
2980 * write is safe - FR
2981 */
2982 smp_wmb();
0e485150 2983 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2984 }
2985
bea3348e 2986 return work_done;
1da177e4
LT		 2987}
2988#endif
2989
2990static void rtl8169_down(struct net_device *dev)
2991{
2992 struct rtl8169_private *tp = netdev_priv(dev);
2993 void __iomem *ioaddr = tp->mmio_addr;
733b736c 2994 unsigned int intrmask;
1da177e4
LT		 2995
2996 rtl8169_delete_timer(dev);
2997
2998 netif_stop_queue(dev);
2999
93dd79e8
SH		 3000#ifdef CONFIG_R8169_NAPI
3001 napi_disable(&tp->napi);
3002#endif
3003
1da177e4
LT		 3004core_down:
3005 spin_lock_irq(&tp->lock);
3006
3007 rtl8169_asic_down(ioaddr);
3008
3009 /* Update the error counts. */
cebf8cc7 3010 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 3011 RTL_W32(RxMissed, 0);
3012
3013 spin_unlock_irq(&tp->lock);
3014
3015 synchronize_irq(dev->irq);
3016
1da177e4 3017 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3018 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3019
3020 /*
3021 * And now for the 50k$ question: are IRQ disabled or not ?
3022 *
3023 * Two paths lead here:
3024 * 1) dev->close
3025 * -> netif_running() is available to sync the current code and the
3026 * IRQ handler. See rtl8169_interrupt for details.
3027 * 2) dev->change_mtu
3028 * -> rtl8169_poll can not be issued again and re-enable the
3029 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3030 *
3031 * No loop if hotpluged or major error (0xffff).
1da177e4 3032 */
733b736c
AP		 3033 intrmask = RTL_R16(IntrMask);
3034 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3035 goto core_down;
3036
3037 rtl8169_tx_clear(tp);
3038
3039 rtl8169_rx_clear(tp);
3040}
3041
3042static int rtl8169_close(struct net_device *dev)
3043{
3044 struct rtl8169_private *tp = netdev_priv(dev);
3045 struct pci_dev *pdev = tp->pci_dev;
3046
3047 rtl8169_down(dev);
3048
3049 free_irq(dev->irq, dev);
3050
1da177e4
LT		 3051 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3052 tp->RxPhyAddr);
3053 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3054 tp->TxPhyAddr);
3055 tp->TxDescArray = NULL;
3056 tp->RxDescArray = NULL;
3057
3058 return 0;
3059}
3060
07ce4064 3061static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3062{
3063 struct rtl8169_private *tp = netdev_priv(dev);
3064 void __iomem *ioaddr = tp->mmio_addr;
3065 unsigned long flags;
3066 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3067 int rx_mode;
1da177e4
LT		 3068 u32 tmp = 0;
3069
3070 if (dev->flags & IFF_PROMISC) {
3071 /* Unconditionally log net taps. */
b57b7e5a
SH		 3072 if (netif_msg_link(tp)) {
3073 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3074 dev->name);
3075 }
1da177e4
LT		 3076 rx_mode =
3077 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3078 AcceptAllPhys;
3079 mc_filter[1] = mc_filter[0] = 0xffffffff;
3080 } else if ((dev->mc_count > multicast_filter_limit)
3081 || (dev->flags & IFF_ALLMULTI)) {
3082 /* Too many to filter perfectly -- accept all multicasts. */
3083 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3084 mc_filter[1] = mc_filter[0] = 0xffffffff;
3085 } else {
3086 struct dev_mc_list *mclist;
07d3f51f
FR		 3087 unsigned int i;
3088
1da177e4
LT		 3089 rx_mode = AcceptBroadcast | AcceptMyPhys;
3090 mc_filter[1] = mc_filter[0] = 0;
3091 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3092 i++, mclist = mclist->next) {
3093 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3094 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3095 rx_mode |= AcceptMulticast;
3096 }
3097 }
3098
3099 spin_lock_irqsave(&tp->lock, flags);
3100
3101 tmp = rtl8169_rx_config | rx_mode |
3102 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3103
bcf0bf90
FR		 3104 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
3105 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
3106 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3107 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 3108 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
3109 (tp->mac_version == RTL_GIGA_MAC_VER_16) ||
3110 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
bcf0bf90
FR		 3111 mc_filter[0] = 0xffffffff;
3112 mc_filter[1] = 0xffffffff;
3113 }
3114
1da177e4
LT		 3115 RTL_W32(MAR0 + 0, mc_filter[0]);
3116 RTL_W32(MAR0 + 4, mc_filter[1]);
3117
57a9f236
FR		 3118 RTL_W32(RxConfig, tmp);
3119
1da177e4
LT		 3120 spin_unlock_irqrestore(&tp->lock, flags);
3121}
3122
3123/**
3124 * rtl8169_get_stats - Get rtl8169 read/write statistics
3125 * @dev: The Ethernet Device to get statistics for
3126 *
3127 * Get TX/RX statistics for rtl8169
3128 */
3129static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3130{
3131 struct rtl8169_private *tp = netdev_priv(dev);
3132 void __iomem *ioaddr = tp->mmio_addr;
3133 unsigned long flags;
3134
3135 if (netif_running(dev)) {
3136 spin_lock_irqsave(&tp->lock, flags);
cebf8cc7 3137 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 3138 RTL_W32(RxMissed, 0);
3139 spin_unlock_irqrestore(&tp->lock, flags);
3140 }
5b0384f4 3141
cebf8cc7 3142 return &dev->stats;
1da177e4
LT		 3143}
3144
5d06a99f
FR		 3145#ifdef CONFIG_PM
3146
3147static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3148{
3149 struct net_device *dev = pci_get_drvdata(pdev);
3150 struct rtl8169_private *tp = netdev_priv(dev);
3151 void __iomem *ioaddr = tp->mmio_addr;
3152
3153 if (!netif_running(dev))
1371fa6d 3154 goto out_pci_suspend;
5d06a99f
FR		 3155
3156 netif_device_detach(dev);
3157 netif_stop_queue(dev);
3158
3159 spin_lock_irq(&tp->lock);
3160
3161 rtl8169_asic_down(ioaddr);
3162
cebf8cc7 3163 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
5d06a99f
FR		 3164 RTL_W32(RxMissed, 0);
3165
3166 spin_unlock_irq(&tp->lock);
3167
1371fa6d 3168out_pci_suspend:
5d06a99f 3169 pci_save_state(pdev);
f23e7fda
FR		 3170 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3171 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3172 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3173
5d06a99f
FR		 3174 return 0;
3175}
3176
3177static int rtl8169_resume(struct pci_dev *pdev)
3178{
3179 struct net_device *dev = pci_get_drvdata(pdev);
3180
1371fa6d
FR		 3181 pci_set_power_state(pdev, PCI_D0);
3182 pci_restore_state(pdev);
3183 pci_enable_wake(pdev, PCI_D0, 0);
3184
5d06a99f
FR		 3185 if (!netif_running(dev))
3186 goto out;
3187
3188 netif_device_attach(dev);
3189
5d06a99f
FR		 3190 rtl8169_schedule_work(dev, rtl8169_reset_task);
3191out:
3192 return 0;
3193}
3194
3195#endif /* CONFIG_PM */
3196
1da177e4
LT		 3197static struct pci_driver rtl8169_pci_driver = {
3198 .name = MODULENAME,
3199 .id_table = rtl8169_pci_tbl,
3200 .probe = rtl8169_init_one,
3201 .remove = __devexit_p(rtl8169_remove_one),
3202#ifdef CONFIG_PM
3203 .suspend = rtl8169_suspend,
3204 .resume = rtl8169_resume,
3205#endif
3206};
3207
07d3f51f 3208static int __init rtl8169_init_module(void)
1da177e4 3209{
29917620 3210 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3211}
3212
07d3f51f 3213static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3214{
3215 pci_unregister_driver(&rtl8169_pci_driver);
3216}
3217
3218module_init(rtl8169_init_module);
3219module_exit(rtl8169_cleanup_module);
ubuntu-bionic-kernel mirror