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Commit | Line | Data |
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1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/dma-mapping.h> | |
e1759441 | 26 | #include <linux/pm_runtime.h> |
bca03d5f | 27 | #include <linux/firmware.h> |
ba04c7c9 | 28 | #include <linux/pci-aspm.h> |
1da177e4 | 29 | |
99f252b0 | 30 | #include <asm/system.h> |
1da177e4 LT |
31 | #include <asm/io.h> |
32 | #include <asm/irq.h> | |
33 | ||
865c652d | 34 | #define RTL8169_VERSION "2.3LK-NAPI" |
1da177e4 LT |
35 | #define MODULENAME "r8169" |
36 | #define PFX MODULENAME ": " | |
37 | ||
bca03d5f | 38 | #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw" |
39 | #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw" | |
01dc7fec | 40 | #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw" |
41 | #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw" | |
5a5e4443 | 42 | #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw" |
bca03d5f | 43 | |
1da177e4 LT |
44 | #ifdef RTL8169_DEBUG |
45 | #define assert(expr) \ | |
5b0384f4 FR |
46 | if (!(expr)) { \ |
47 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
b39d66a8 | 48 | #expr,__FILE__,__func__,__LINE__); \ |
5b0384f4 | 49 | } |
06fa7358 JP |
50 | #define dprintk(fmt, args...) \ |
51 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
52 | #else |
53 | #define assert(expr) do {} while (0) | |
54 | #define dprintk(fmt, args...) do {} while (0) | |
55 | #endif /* RTL8169_DEBUG */ | |
56 | ||
b57b7e5a | 57 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 58 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 59 | |
1da177e4 LT |
60 | #define TX_BUFFS_AVAIL(tp) \ |
61 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) | |
62 | ||
1da177e4 LT |
63 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). |
64 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 65 | static const int multicast_filter_limit = 32; |
1da177e4 LT |
66 | |
67 | /* MAC address length */ | |
68 | #define MAC_ADDR_LEN 6 | |
69 | ||
9c14ceaf | 70 | #define MAX_READ_REQUEST_SHIFT 12 |
1da177e4 LT |
71 | #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ |
72 | #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
73 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
1da177e4 LT |
74 | #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ |
75 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
76 | ||
77 | #define R8169_REGS_SIZE 256 | |
78 | #define R8169_NAPI_WEIGHT 64 | |
79 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
80 | #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ | |
81 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ | |
82 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) | |
83 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
84 | ||
85 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
86 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
87 | ||
ea8dbdd1 | 88 | #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
89 | #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) | |
e1564ec9 FR |
90 | #define RTL_EEPROM_SIG_ADDR 0x0000 |
91 | ||
1da177e4 LT |
92 | /* write/read MMIO register */ |
93 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
94 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
95 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
96 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
97 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
06f555f3 | 98 | #define RTL_R32(reg) readl (ioaddr + (reg)) |
1da177e4 LT |
99 | |
100 | enum mac_version { | |
f21b75e9 | 101 | RTL_GIGA_MAC_NONE = 0x00, |
ba6eb6ee FR |
102 | RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
103 | RTL_GIGA_MAC_VER_02 = 0x02, // 8169S | |
104 | RTL_GIGA_MAC_VER_03 = 0x03, // 8110S | |
105 | RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB | |
106 | RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd | |
6dccd16b | 107 | RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
2857ffb7 FR |
108 | RTL_GIGA_MAC_VER_07 = 0x07, // 8102e |
109 | RTL_GIGA_MAC_VER_08 = 0x08, // 8102e | |
110 | RTL_GIGA_MAC_VER_09 = 0x09, // 8102e | |
111 | RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e | |
2dd99530 | 112 | RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
e3cf0cc0 FR |
113 | RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be |
114 | RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb | |
115 | RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? | |
116 | RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? | |
117 | RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec | |
118 | RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf | |
119 | RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP | |
120 | RTL_GIGA_MAC_VER_19 = 0x13, // 8168C | |
197ff761 | 121 | RTL_GIGA_MAC_VER_20 = 0x14, // 8168C |
6fb07058 | 122 | RTL_GIGA_MAC_VER_21 = 0x15, // 8168C |
ef3386f0 | 123 | RTL_GIGA_MAC_VER_22 = 0x16, // 8168C |
7f3e3d3a | 124 | RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP |
5b538df9 | 125 | RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP |
daf9df6d | 126 | RTL_GIGA_MAC_VER_25 = 0x19, // 8168D |
127 | RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D | |
e6de30d6 | 128 | RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP |
129 | RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP | |
5a5e4443 HW |
130 | RTL_GIGA_MAC_VER_29 = 0x1d, // 8105E |
131 | RTL_GIGA_MAC_VER_30 = 0x1e, // 8105E | |
4804b3b3 | 132 | RTL_GIGA_MAC_VER_31 = 0x1f, // 8168DP |
01dc7fec | 133 | RTL_GIGA_MAC_VER_32 = 0x20, // 8168E |
134 | RTL_GIGA_MAC_VER_33 = 0x21, // 8168E | |
1da177e4 LT |
135 | }; |
136 | ||
1da177e4 LT |
137 | #define _R(NAME,MAC,MASK) \ |
138 | { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } | |
139 | ||
3c6bee1d | 140 | static const struct { |
1da177e4 LT |
141 | const char *name; |
142 | u8 mac_version; | |
143 | u32 RxConfigMask; /* Clears the bits supported by this chip */ | |
144 | } rtl_chip_info[] = { | |
ba6eb6ee FR |
145 | _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 |
146 | _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S | |
147 | _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S | |
148 | _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB | |
149 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd | |
6dccd16b | 150 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe |
2857ffb7 FR |
151 | _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E |
152 | _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E | |
153 | _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E | |
154 | _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E | |
bcf0bf90 FR |
155 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
156 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E | |
157 | _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 | |
158 | _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 | |
e3cf0cc0 FR |
159 | _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 |
160 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E | |
161 | _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E | |
162 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E | |
163 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E | |
197ff761 | 164 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E |
6fb07058 | 165 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E |
ef3386f0 | 166 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E |
7f3e3d3a | 167 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E |
5b538df9 | 168 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E |
daf9df6d | 169 | _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E |
170 | _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E | |
e6de30d6 | 171 | _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E |
5a5e4443 HW |
172 | _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880), // PCI-E |
173 | _R("RTL8105e", RTL_GIGA_MAC_VER_29, 0xff7e1880), // PCI-E | |
4804b3b3 | 174 | _R("RTL8105e", RTL_GIGA_MAC_VER_30, 0xff7e1880), // PCI-E |
01dc7fec | 175 | _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_31, 0xff7e1880), // PCI-E |
176 | _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_32, 0xff7e1880), // PCI-E | |
177 | _R("RTL8168e/8111e", RTL_GIGA_MAC_VER_33, 0xff7e1880) // PCI-E | |
1da177e4 LT |
178 | }; |
179 | #undef _R | |
180 | ||
bcf0bf90 FR |
181 | enum cfg_version { |
182 | RTL_CFG_0 = 0x00, | |
183 | RTL_CFG_1, | |
184 | RTL_CFG_2 | |
185 | }; | |
186 | ||
07ce4064 FR |
187 | static void rtl_hw_start_8169(struct net_device *); |
188 | static void rtl_hw_start_8168(struct net_device *); | |
189 | static void rtl_hw_start_8101(struct net_device *); | |
190 | ||
a3aa1884 | 191 | static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = { |
bcf0bf90 | 192 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 193 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 194 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 195 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 FR |
196 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
197 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, | |
bc1660b5 | 198 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
199 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
200 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
201 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
202 | { 0x0001, 0x8168, |
203 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
204 | {0,}, |
205 | }; | |
206 | ||
207 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
208 | ||
6f0333b8 | 209 | static int rx_buf_sz = 16383; |
4300e8c7 | 210 | static int use_dac; |
b57b7e5a SH |
211 | static struct { |
212 | u32 msg_enable; | |
213 | } debug = { -1 }; | |
1da177e4 | 214 | |
07d3f51f FR |
215 | enum rtl_registers { |
216 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 217 | MAC4 = 4, |
07d3f51f FR |
218 | MAR0 = 8, /* Multicast filter. */ |
219 | CounterAddrLow = 0x10, | |
220 | CounterAddrHigh = 0x14, | |
221 | TxDescStartAddrLow = 0x20, | |
222 | TxDescStartAddrHigh = 0x24, | |
223 | TxHDescStartAddrLow = 0x28, | |
224 | TxHDescStartAddrHigh = 0x2c, | |
225 | FLASH = 0x30, | |
226 | ERSR = 0x36, | |
227 | ChipCmd = 0x37, | |
228 | TxPoll = 0x38, | |
229 | IntrMask = 0x3c, | |
230 | IntrStatus = 0x3e, | |
231 | TxConfig = 0x40, | |
232 | RxConfig = 0x44, | |
233 | RxMissed = 0x4c, | |
234 | Cfg9346 = 0x50, | |
235 | Config0 = 0x51, | |
236 | Config1 = 0x52, | |
237 | Config2 = 0x53, | |
238 | Config3 = 0x54, | |
239 | Config4 = 0x55, | |
240 | Config5 = 0x56, | |
241 | MultiIntr = 0x5c, | |
242 | PHYAR = 0x60, | |
07d3f51f FR |
243 | PHYstatus = 0x6c, |
244 | RxMaxSize = 0xda, | |
245 | CPlusCmd = 0xe0, | |
246 | IntrMitigate = 0xe2, | |
247 | RxDescAddrLow = 0xe4, | |
248 | RxDescAddrHigh = 0xe8, | |
f0298f81 | 249 | EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */ |
250 | ||
251 | #define NoEarlyTx 0x3f /* Max value : no early transmit. */ | |
252 | ||
253 | MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */ | |
254 | ||
255 | #define TxPacketMax (8064 >> 7) | |
256 | ||
07d3f51f FR |
257 | FuncEvent = 0xf0, |
258 | FuncEventMask = 0xf4, | |
259 | FuncPresetState = 0xf8, | |
260 | FuncForceEvent = 0xfc, | |
1da177e4 LT |
261 | }; |
262 | ||
f162a5d1 FR |
263 | enum rtl8110_registers { |
264 | TBICSR = 0x64, | |
265 | TBI_ANAR = 0x68, | |
266 | TBI_LPAR = 0x6a, | |
267 | }; | |
268 | ||
269 | enum rtl8168_8101_registers { | |
270 | CSIDR = 0x64, | |
271 | CSIAR = 0x68, | |
272 | #define CSIAR_FLAG 0x80000000 | |
273 | #define CSIAR_WRITE_CMD 0x80000000 | |
274 | #define CSIAR_BYTE_ENABLE 0x0f | |
275 | #define CSIAR_BYTE_ENABLE_SHIFT 12 | |
276 | #define CSIAR_ADDR_MASK 0x0fff | |
065c27c1 | 277 | PMCH = 0x6f, |
f162a5d1 FR |
278 | EPHYAR = 0x80, |
279 | #define EPHYAR_FLAG 0x80000000 | |
280 | #define EPHYAR_WRITE_CMD 0x80000000 | |
281 | #define EPHYAR_REG_MASK 0x1f | |
282 | #define EPHYAR_REG_SHIFT 16 | |
283 | #define EPHYAR_DATA_MASK 0xffff | |
5a5e4443 HW |
284 | DLLPR = 0xd0, |
285 | #define PM_SWITCH (1 << 6) | |
f162a5d1 FR |
286 | DBG_REG = 0xd1, |
287 | #define FIX_NAK_1 (1 << 4) | |
288 | #define FIX_NAK_2 (1 << 3) | |
5a5e4443 HW |
289 | TWSI = 0xd2, |
290 | MCU = 0xd3, | |
291 | #define EN_NDP (1 << 3) | |
292 | #define EN_OOB_RESET (1 << 2) | |
daf9df6d | 293 | EFUSEAR = 0xdc, |
294 | #define EFUSEAR_FLAG 0x80000000 | |
295 | #define EFUSEAR_WRITE_CMD 0x80000000 | |
296 | #define EFUSEAR_READ_CMD 0x00000000 | |
297 | #define EFUSEAR_REG_MASK 0x03ff | |
298 | #define EFUSEAR_REG_SHIFT 8 | |
299 | #define EFUSEAR_DATA_MASK 0xff | |
f162a5d1 FR |
300 | }; |
301 | ||
c0e45c1c | 302 | enum rtl8168_registers { |
b646d900 | 303 | ERIDR = 0x70, |
304 | ERIAR = 0x74, | |
305 | #define ERIAR_FLAG 0x80000000 | |
306 | #define ERIAR_WRITE_CMD 0x80000000 | |
307 | #define ERIAR_READ_CMD 0x00000000 | |
308 | #define ERIAR_ADDR_BYTE_ALIGN 4 | |
309 | #define ERIAR_EXGMAC 0 | |
310 | #define ERIAR_MSIX 1 | |
311 | #define ERIAR_ASF 2 | |
312 | #define ERIAR_TYPE_SHIFT 16 | |
313 | #define ERIAR_BYTEEN 0x0f | |
314 | #define ERIAR_BYTEEN_SHIFT 12 | |
c0e45c1c | 315 | EPHY_RXER_NUM = 0x7c, |
316 | OCPDR = 0xb0, /* OCP GPHY access */ | |
317 | #define OCPDR_WRITE_CMD 0x80000000 | |
318 | #define OCPDR_READ_CMD 0x00000000 | |
319 | #define OCPDR_REG_MASK 0x7f | |
320 | #define OCPDR_GPHY_REG_SHIFT 16 | |
321 | #define OCPDR_DATA_MASK 0xffff | |
322 | OCPAR = 0xb4, | |
323 | #define OCPAR_FLAG 0x80000000 | |
324 | #define OCPAR_GPHY_WRITE_CMD 0x8000f060 | |
325 | #define OCPAR_GPHY_READ_CMD 0x0000f060 | |
01dc7fec | 326 | RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */ |
327 | MISC = 0xf0, /* 8168e only. */ | |
328 | txpla_rst = (1 << 29) | |
c0e45c1c | 329 | }; |
330 | ||
07d3f51f | 331 | enum rtl_register_content { |
1da177e4 | 332 | /* InterruptStatusBits */ |
07d3f51f FR |
333 | SYSErr = 0x8000, |
334 | PCSTimeout = 0x4000, | |
335 | SWInt = 0x0100, | |
336 | TxDescUnavail = 0x0080, | |
337 | RxFIFOOver = 0x0040, | |
338 | LinkChg = 0x0020, | |
339 | RxOverflow = 0x0010, | |
340 | TxErr = 0x0008, | |
341 | TxOK = 0x0004, | |
342 | RxErr = 0x0002, | |
343 | RxOK = 0x0001, | |
1da177e4 LT |
344 | |
345 | /* RxStatusDesc */ | |
9dccf611 FR |
346 | RxFOVF = (1 << 23), |
347 | RxRWT = (1 << 22), | |
348 | RxRES = (1 << 21), | |
349 | RxRUNT = (1 << 20), | |
350 | RxCRC = (1 << 19), | |
1da177e4 LT |
351 | |
352 | /* ChipCmdBits */ | |
07d3f51f FR |
353 | CmdReset = 0x10, |
354 | CmdRxEnb = 0x08, | |
355 | CmdTxEnb = 0x04, | |
356 | RxBufEmpty = 0x01, | |
1da177e4 | 357 | |
275391a4 FR |
358 | /* TXPoll register p.5 */ |
359 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
360 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
361 | FSWInt = 0x01, /* Forced software interrupt */ | |
362 | ||
1da177e4 | 363 | /* Cfg9346Bits */ |
07d3f51f FR |
364 | Cfg9346_Lock = 0x00, |
365 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
366 | |
367 | /* rx_mode_bits */ | |
07d3f51f FR |
368 | AcceptErr = 0x20, |
369 | AcceptRunt = 0x10, | |
370 | AcceptBroadcast = 0x08, | |
371 | AcceptMulticast = 0x04, | |
372 | AcceptMyPhys = 0x02, | |
373 | AcceptAllPhys = 0x01, | |
1da177e4 LT |
374 | |
375 | /* RxConfigBits */ | |
07d3f51f FR |
376 | RxCfgFIFOShift = 13, |
377 | RxCfgDMAShift = 8, | |
1da177e4 LT |
378 | |
379 | /* TxConfigBits */ | |
380 | TxInterFrameGapShift = 24, | |
381 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
382 | ||
5d06a99f | 383 | /* Config1 register p.24 */ |
f162a5d1 FR |
384 | LEDS1 = (1 << 7), |
385 | LEDS0 = (1 << 6), | |
fbac58fc | 386 | MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
f162a5d1 FR |
387 | Speed_down = (1 << 4), |
388 | MEMMAP = (1 << 3), | |
389 | IOMAP = (1 << 2), | |
390 | VPD = (1 << 1), | |
5d06a99f FR |
391 | PMEnable = (1 << 0), /* Power Management Enable */ |
392 | ||
6dccd16b FR |
393 | /* Config2 register p. 25 */ |
394 | PCI_Clock_66MHz = 0x01, | |
395 | PCI_Clock_33MHz = 0x00, | |
396 | ||
61a4dcc2 FR |
397 | /* Config3 register p.25 */ |
398 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
399 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
f162a5d1 | 400 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 401 | |
5d06a99f | 402 | /* Config5 register p.27 */ |
61a4dcc2 FR |
403 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
404 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
405 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
01dc7fec | 406 | spi_en = (1 << 3), |
61a4dcc2 | 407 | LanWake = (1 << 1), /* LanWake enable/disable */ |
5d06a99f FR |
408 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
409 | ||
1da177e4 LT |
410 | /* TBICSR p.28 */ |
411 | TBIReset = 0x80000000, | |
412 | TBILoopback = 0x40000000, | |
413 | TBINwEnable = 0x20000000, | |
414 | TBINwRestart = 0x10000000, | |
415 | TBILinkOk = 0x02000000, | |
416 | TBINwComplete = 0x01000000, | |
417 | ||
418 | /* CPlusCmd p.31 */ | |
f162a5d1 FR |
419 | EnableBist = (1 << 15), // 8168 8101 |
420 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
421 | Normal_mode = (1 << 13), // unused | |
422 | Force_half_dup = (1 << 12), // 8168 8101 | |
423 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
424 | Force_txflow_en = (1 << 10), // 8168 8101 | |
425 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
426 | ASF = (1 << 8), // 8168 8101 | |
427 | PktCntrDisable = (1 << 7), // 8168 8101 | |
428 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
429 | RxVlan = (1 << 6), |
430 | RxChkSum = (1 << 5), | |
431 | PCIDAC = (1 << 4), | |
432 | PCIMulRW = (1 << 3), | |
0e485150 FR |
433 | INTT_0 = 0x0000, // 8168 |
434 | INTT_1 = 0x0001, // 8168 | |
435 | INTT_2 = 0x0002, // 8168 | |
436 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
437 | |
438 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
439 | TBI_Enable = 0x80, |
440 | TxFlowCtrl = 0x40, | |
441 | RxFlowCtrl = 0x20, | |
442 | _1000bpsF = 0x10, | |
443 | _100bps = 0x08, | |
444 | _10bps = 0x04, | |
445 | LinkStatus = 0x02, | |
446 | FullDup = 0x01, | |
1da177e4 | 447 | |
1da177e4 | 448 | /* _TBICSRBit */ |
07d3f51f | 449 | TBILinkOK = 0x02000000, |
d4a3a0fc SH |
450 | |
451 | /* DumpCounterCommand */ | |
07d3f51f | 452 | CounterDump = 0x8, |
1da177e4 LT |
453 | }; |
454 | ||
07d3f51f | 455 | enum desc_status_bit { |
1da177e4 LT |
456 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
457 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
458 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
459 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
460 | ||
461 | /* Tx private */ | |
462 | LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ | |
463 | MSSShift = 16, /* MSS value position */ | |
464 | MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ | |
465 | IPCS = (1 << 18), /* Calculate IP checksum */ | |
466 | UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ | |
467 | TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ | |
468 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
469 | ||
470 | /* Rx private */ | |
471 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
472 | PID0 = (1 << 17), /* Protocol ID bit 2/2 */ | |
473 | ||
474 | #define RxProtoUDP (PID1) | |
475 | #define RxProtoTCP (PID0) | |
476 | #define RxProtoIP (PID1 | PID0) | |
477 | #define RxProtoMask RxProtoIP | |
478 | ||
479 | IPFail = (1 << 16), /* IP checksum failed */ | |
480 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
481 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
482 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
483 | }; | |
484 | ||
485 | #define RsvdMask 0x3fffc000 | |
486 | ||
487 | struct TxDesc { | |
6cccd6e7 REB |
488 | __le32 opts1; |
489 | __le32 opts2; | |
490 | __le64 addr; | |
1da177e4 LT |
491 | }; |
492 | ||
493 | struct RxDesc { | |
6cccd6e7 REB |
494 | __le32 opts1; |
495 | __le32 opts2; | |
496 | __le64 addr; | |
1da177e4 LT |
497 | }; |
498 | ||
499 | struct ring_info { | |
500 | struct sk_buff *skb; | |
501 | u32 len; | |
502 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
503 | }; | |
504 | ||
f23e7fda | 505 | enum features { |
ccdffb9a FR |
506 | RTL_FEATURE_WOL = (1 << 0), |
507 | RTL_FEATURE_MSI = (1 << 1), | |
508 | RTL_FEATURE_GMII = (1 << 2), | |
f23e7fda FR |
509 | }; |
510 | ||
355423d0 IV |
511 | struct rtl8169_counters { |
512 | __le64 tx_packets; | |
513 | __le64 rx_packets; | |
514 | __le64 tx_errors; | |
515 | __le32 rx_errors; | |
516 | __le16 rx_missed; | |
517 | __le16 align_errors; | |
518 | __le32 tx_one_collision; | |
519 | __le32 tx_multi_collision; | |
520 | __le64 rx_unicast; | |
521 | __le64 rx_broadcast; | |
522 | __le32 rx_multicast; | |
523 | __le16 tx_aborted; | |
524 | __le16 tx_underun; | |
525 | }; | |
526 | ||
1da177e4 LT |
527 | struct rtl8169_private { |
528 | void __iomem *mmio_addr; /* memory map physical address */ | |
529 | struct pci_dev *pci_dev; /* Index of PCI device */ | |
c4028958 | 530 | struct net_device *dev; |
bea3348e | 531 | struct napi_struct napi; |
1da177e4 | 532 | spinlock_t lock; /* spin lock flag */ |
b57b7e5a | 533 | u32 msg_enable; |
1da177e4 LT |
534 | int chipset; |
535 | int mac_version; | |
1da177e4 LT |
536 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
537 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
538 | u32 dirty_rx; | |
539 | u32 dirty_tx; | |
540 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ | |
541 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
542 | dma_addr_t TxPhyAddr; | |
543 | dma_addr_t RxPhyAddr; | |
6f0333b8 | 544 | void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */ |
1da177e4 | 545 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ |
1da177e4 LT |
546 | struct timer_list timer; |
547 | u16 cp_cmd; | |
0e485150 FR |
548 | u16 intr_event; |
549 | u16 napi_event; | |
1da177e4 | 550 | u16 intr_mask; |
1da177e4 | 551 | int phy_1000_ctrl_reg; |
c0e45c1c | 552 | |
553 | struct mdio_ops { | |
554 | void (*write)(void __iomem *, int, int); | |
555 | int (*read)(void __iomem *, int); | |
556 | } mdio_ops; | |
557 | ||
065c27c1 | 558 | struct pll_power_ops { |
559 | void (*down)(struct rtl8169_private *); | |
560 | void (*up)(struct rtl8169_private *); | |
561 | } pll_power_ops; | |
562 | ||
54405cde | 563 | int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv); |
ccdffb9a | 564 | int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
4da19633 | 565 | void (*phy_reset_enable)(struct rtl8169_private *tp); |
07ce4064 | 566 | void (*hw_start)(struct net_device *); |
4da19633 | 567 | unsigned int (*phy_reset_pending)(struct rtl8169_private *tp); |
1da177e4 | 568 | unsigned int (*link_ok)(void __iomem *); |
8b4ab28d | 569 | int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd); |
9c14ceaf | 570 | int pcie_cap; |
c4028958 | 571 | struct delayed_work task; |
f23e7fda | 572 | unsigned features; |
ccdffb9a FR |
573 | |
574 | struct mii_if_info mii; | |
355423d0 | 575 | struct rtl8169_counters counters; |
e1759441 | 576 | u32 saved_wolopts; |
f1e02ed1 | 577 | |
578 | const struct firmware *fw; | |
1da177e4 LT |
579 | }; |
580 | ||
979b6c13 | 581 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 582 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 583 | module_param(use_dac, int, 0); |
4300e8c7 | 584 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); |
b57b7e5a SH |
585 | module_param_named(debug, debug.msg_enable, int, 0); |
586 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
587 | MODULE_LICENSE("GPL"); |
588 | MODULE_VERSION(RTL8169_VERSION); | |
bca03d5f | 589 | MODULE_FIRMWARE(FIRMWARE_8168D_1); |
590 | MODULE_FIRMWARE(FIRMWARE_8168D_2); | |
01dc7fec | 591 | MODULE_FIRMWARE(FIRMWARE_8168E_1); |
592 | MODULE_FIRMWARE(FIRMWARE_8168E_2); | |
5a5e4443 | 593 | MODULE_FIRMWARE(FIRMWARE_8105E_1); |
1da177e4 LT |
594 | |
595 | static int rtl8169_open(struct net_device *dev); | |
61357325 SH |
596 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
597 | struct net_device *dev); | |
7d12e780 | 598 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
1da177e4 | 599 | static int rtl8169_init_ring(struct net_device *dev); |
07ce4064 | 600 | static void rtl_hw_start(struct net_device *dev); |
1da177e4 | 601 | static int rtl8169_close(struct net_device *dev); |
07ce4064 | 602 | static void rtl_set_rx_mode(struct net_device *dev); |
1da177e4 | 603 | static void rtl8169_tx_timeout(struct net_device *dev); |
4dcb7d33 | 604 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
1da177e4 | 605 | static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
bea3348e | 606 | void __iomem *, u32 budget); |
4dcb7d33 | 607 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
1da177e4 | 608 | static void rtl8169_down(struct net_device *dev); |
99f252b0 | 609 | static void rtl8169_rx_clear(struct rtl8169_private *tp); |
bea3348e | 610 | static int rtl8169_poll(struct napi_struct *napi, int budget); |
1da177e4 | 611 | |
1da177e4 | 612 | static const unsigned int rtl8169_rx_config = |
5b0384f4 | 613 | (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
1da177e4 | 614 | |
b646d900 | 615 | static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg) |
616 | { | |
617 | void __iomem *ioaddr = tp->mmio_addr; | |
618 | int i; | |
619 | ||
620 | RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
621 | for (i = 0; i < 20; i++) { | |
622 | udelay(100); | |
623 | if (RTL_R32(OCPAR) & OCPAR_FLAG) | |
624 | break; | |
625 | } | |
626 | return RTL_R32(OCPDR); | |
627 | } | |
628 | ||
629 | static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data) | |
630 | { | |
631 | void __iomem *ioaddr = tp->mmio_addr; | |
632 | int i; | |
633 | ||
634 | RTL_W32(OCPDR, data); | |
635 | RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); | |
636 | for (i = 0; i < 20; i++) { | |
637 | udelay(100); | |
638 | if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0) | |
639 | break; | |
640 | } | |
641 | } | |
642 | ||
fac5b3ca | 643 | static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd) |
b646d900 | 644 | { |
fac5b3ca | 645 | void __iomem *ioaddr = tp->mmio_addr; |
b646d900 | 646 | int i; |
647 | ||
648 | RTL_W8(ERIDR, cmd); | |
649 | RTL_W32(ERIAR, 0x800010e8); | |
650 | msleep(2); | |
651 | for (i = 0; i < 5; i++) { | |
652 | udelay(100); | |
653 | if (!(RTL_R32(ERIDR) & ERIAR_FLAG)) | |
654 | break; | |
655 | } | |
656 | ||
fac5b3ca | 657 | ocp_write(tp, 0x1, 0x30, 0x00000001); |
b646d900 | 658 | } |
659 | ||
660 | #define OOB_CMD_RESET 0x00 | |
661 | #define OOB_CMD_DRIVER_START 0x05 | |
662 | #define OOB_CMD_DRIVER_STOP 0x06 | |
663 | ||
664 | static void rtl8168_driver_start(struct rtl8169_private *tp) | |
665 | { | |
666 | int i; | |
4804b3b3 | 667 | u32 reg; |
b646d900 | 668 | |
669 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START); | |
670 | ||
4804b3b3 | 671 | if (tp->mac_version == RTL_GIGA_MAC_VER_31) |
672 | reg = 0xb8; | |
673 | else | |
674 | reg = 0x10; | |
675 | ||
b646d900 | 676 | for (i = 0; i < 10; i++) { |
677 | msleep(10); | |
4804b3b3 | 678 | if (ocp_read(tp, 0x0f, reg) & 0x00000800) |
b646d900 | 679 | break; |
680 | } | |
681 | } | |
682 | ||
683 | static void rtl8168_driver_stop(struct rtl8169_private *tp) | |
684 | { | |
685 | int i; | |
4804b3b3 | 686 | u32 reg; |
b646d900 | 687 | |
688 | rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP); | |
689 | ||
4804b3b3 | 690 | if (tp->mac_version == RTL_GIGA_MAC_VER_31) |
691 | reg = 0xb8; | |
692 | else | |
693 | reg = 0x10; | |
694 | ||
b646d900 | 695 | for (i = 0; i < 10; i++) { |
696 | msleep(10); | |
4804b3b3 | 697 | if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0) |
b646d900 | 698 | break; |
699 | } | |
700 | } | |
701 | ||
4804b3b3 | 702 | static int r8168dp_check_dash(struct rtl8169_private *tp) |
703 | { | |
704 | u32 reg; | |
705 | ||
706 | if (tp->mac_version == RTL_GIGA_MAC_VER_31) | |
707 | reg = 0xb8; | |
708 | else | |
709 | reg = 0x10; | |
710 | ||
711 | if (ocp_read(tp, 0xF, reg) & 0x00008000) | |
712 | return 1; | |
713 | else | |
714 | return 0; | |
715 | } | |
b646d900 | 716 | |
4da19633 | 717 | static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
1da177e4 LT |
718 | { |
719 | int i; | |
720 | ||
a6baf3af | 721 | RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 722 | |
2371408c | 723 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
724 | /* |
725 | * Check if the RTL8169 has completed writing to the specified | |
726 | * MII register. | |
727 | */ | |
5b0384f4 | 728 | if (!(RTL_R32(PHYAR) & 0x80000000)) |
1da177e4 | 729 | break; |
2371408c | 730 | udelay(25); |
1da177e4 | 731 | } |
024a07ba | 732 | /* |
81a95f04 TT |
733 | * According to hardware specs a 20us delay is required after write |
734 | * complete indication, but before sending next command. | |
024a07ba | 735 | */ |
81a95f04 | 736 | udelay(20); |
1da177e4 LT |
737 | } |
738 | ||
4da19633 | 739 | static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr) |
1da177e4 LT |
740 | { |
741 | int i, value = -1; | |
742 | ||
a6baf3af | 743 | RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
1da177e4 | 744 | |
2371408c | 745 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
746 | /* |
747 | * Check if the RTL8169 has completed retrieving data from | |
748 | * the specified MII register. | |
749 | */ | |
1da177e4 | 750 | if (RTL_R32(PHYAR) & 0x80000000) { |
a6baf3af | 751 | value = RTL_R32(PHYAR) & 0xffff; |
1da177e4 LT |
752 | break; |
753 | } | |
2371408c | 754 | udelay(25); |
1da177e4 | 755 | } |
81a95f04 TT |
756 | /* |
757 | * According to hardware specs a 20us delay is required after read | |
758 | * complete indication, but before sending next command. | |
759 | */ | |
760 | udelay(20); | |
761 | ||
1da177e4 LT |
762 | return value; |
763 | } | |
764 | ||
c0e45c1c | 765 | static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data) |
766 | { | |
767 | int i; | |
768 | ||
769 | RTL_W32(OCPDR, data | | |
770 | ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT)); | |
771 | RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD); | |
772 | RTL_W32(EPHY_RXER_NUM, 0); | |
773 | ||
774 | for (i = 0; i < 100; i++) { | |
775 | mdelay(1); | |
776 | if (!(RTL_R32(OCPAR) & OCPAR_FLAG)) | |
777 | break; | |
778 | } | |
779 | } | |
780 | ||
781 | static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value) | |
782 | { | |
783 | r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD | | |
784 | (value & OCPDR_DATA_MASK)); | |
785 | } | |
786 | ||
787 | static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr) | |
788 | { | |
789 | int i; | |
790 | ||
791 | r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD); | |
792 | ||
793 | mdelay(1); | |
794 | RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD); | |
795 | RTL_W32(EPHY_RXER_NUM, 0); | |
796 | ||
797 | for (i = 0; i < 100; i++) { | |
798 | mdelay(1); | |
799 | if (RTL_R32(OCPAR) & OCPAR_FLAG) | |
800 | break; | |
801 | } | |
802 | ||
803 | return RTL_R32(OCPDR) & OCPDR_DATA_MASK; | |
804 | } | |
805 | ||
e6de30d6 | 806 | #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000 |
807 | ||
808 | static void r8168dp_2_mdio_start(void __iomem *ioaddr) | |
809 | { | |
810 | RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); | |
811 | } | |
812 | ||
813 | static void r8168dp_2_mdio_stop(void __iomem *ioaddr) | |
814 | { | |
815 | RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT); | |
816 | } | |
817 | ||
818 | static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value) | |
819 | { | |
820 | r8168dp_2_mdio_start(ioaddr); | |
821 | ||
822 | r8169_mdio_write(ioaddr, reg_addr, value); | |
823 | ||
824 | r8168dp_2_mdio_stop(ioaddr); | |
825 | } | |
826 | ||
827 | static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr) | |
828 | { | |
829 | int value; | |
830 | ||
831 | r8168dp_2_mdio_start(ioaddr); | |
832 | ||
833 | value = r8169_mdio_read(ioaddr, reg_addr); | |
834 | ||
835 | r8168dp_2_mdio_stop(ioaddr); | |
836 | ||
837 | return value; | |
838 | } | |
839 | ||
4da19633 | 840 | static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val) |
dacf8154 | 841 | { |
c0e45c1c | 842 | tp->mdio_ops.write(tp->mmio_addr, location, val); |
dacf8154 FR |
843 | } |
844 | ||
4da19633 | 845 | static int rtl_readphy(struct rtl8169_private *tp, int location) |
846 | { | |
c0e45c1c | 847 | return tp->mdio_ops.read(tp->mmio_addr, location); |
4da19633 | 848 | } |
849 | ||
850 | static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value) | |
851 | { | |
852 | rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value); | |
853 | } | |
854 | ||
855 | static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m) | |
daf9df6d | 856 | { |
857 | int val; | |
858 | ||
4da19633 | 859 | val = rtl_readphy(tp, reg_addr); |
860 | rtl_writephy(tp, reg_addr, (val | p) & ~m); | |
daf9df6d | 861 | } |
862 | ||
ccdffb9a FR |
863 | static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
864 | int val) | |
865 | { | |
866 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 867 | |
4da19633 | 868 | rtl_writephy(tp, location, val); |
ccdffb9a FR |
869 | } |
870 | ||
871 | static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) | |
872 | { | |
873 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a | 874 | |
4da19633 | 875 | return rtl_readphy(tp, location); |
ccdffb9a FR |
876 | } |
877 | ||
dacf8154 FR |
878 | static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
879 | { | |
880 | unsigned int i; | |
881 | ||
882 | RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | | |
883 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
884 | ||
885 | for (i = 0; i < 100; i++) { | |
886 | if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) | |
887 | break; | |
888 | udelay(10); | |
889 | } | |
890 | } | |
891 | ||
892 | static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) | |
893 | { | |
894 | u16 value = 0xffff; | |
895 | unsigned int i; | |
896 | ||
897 | RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
898 | ||
899 | for (i = 0; i < 100; i++) { | |
900 | if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { | |
901 | value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; | |
902 | break; | |
903 | } | |
904 | udelay(10); | |
905 | } | |
906 | ||
907 | return value; | |
908 | } | |
909 | ||
910 | static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) | |
911 | { | |
912 | unsigned int i; | |
913 | ||
914 | RTL_W32(CSIDR, value); | |
915 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
916 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
917 | ||
918 | for (i = 0; i < 100; i++) { | |
919 | if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) | |
920 | break; | |
921 | udelay(10); | |
922 | } | |
923 | } | |
924 | ||
925 | static u32 rtl_csi_read(void __iomem *ioaddr, int addr) | |
926 | { | |
927 | u32 value = ~0x00; | |
928 | unsigned int i; | |
929 | ||
930 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | | |
931 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
932 | ||
933 | for (i = 0; i < 100; i++) { | |
934 | if (RTL_R32(CSIAR) & CSIAR_FLAG) { | |
935 | value = RTL_R32(CSIDR); | |
936 | break; | |
937 | } | |
938 | udelay(10); | |
939 | } | |
940 | ||
941 | return value; | |
942 | } | |
943 | ||
daf9df6d | 944 | static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr) |
945 | { | |
946 | u8 value = 0xff; | |
947 | unsigned int i; | |
948 | ||
949 | RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT); | |
950 | ||
951 | for (i = 0; i < 300; i++) { | |
952 | if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) { | |
953 | value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK; | |
954 | break; | |
955 | } | |
956 | udelay(100); | |
957 | } | |
958 | ||
959 | return value; | |
960 | } | |
961 | ||
1da177e4 LT |
962 | static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
963 | { | |
964 | RTL_W16(IntrMask, 0x0000); | |
965 | ||
966 | RTL_W16(IntrStatus, 0xffff); | |
967 | } | |
968 | ||
969 | static void rtl8169_asic_down(void __iomem *ioaddr) | |
970 | { | |
971 | RTL_W8(ChipCmd, 0x00); | |
972 | rtl8169_irq_mask_and_ack(ioaddr); | |
973 | RTL_R16(CPlusCmd); | |
974 | } | |
975 | ||
4da19633 | 976 | static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 977 | { |
4da19633 | 978 | void __iomem *ioaddr = tp->mmio_addr; |
979 | ||
1da177e4 LT |
980 | return RTL_R32(TBICSR) & TBIReset; |
981 | } | |
982 | ||
4da19633 | 983 | static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp) |
1da177e4 | 984 | { |
4da19633 | 985 | return rtl_readphy(tp, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
986 | } |
987 | ||
988 | static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) | |
989 | { | |
990 | return RTL_R32(TBICSR) & TBILinkOk; | |
991 | } | |
992 | ||
993 | static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) | |
994 | { | |
995 | return RTL_R8(PHYstatus) & LinkStatus; | |
996 | } | |
997 | ||
4da19633 | 998 | static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp) |
1da177e4 | 999 | { |
4da19633 | 1000 | void __iomem *ioaddr = tp->mmio_addr; |
1001 | ||
1da177e4 LT |
1002 | RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); |
1003 | } | |
1004 | ||
4da19633 | 1005 | static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp) |
1da177e4 LT |
1006 | { |
1007 | unsigned int val; | |
1008 | ||
4da19633 | 1009 | val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET; |
1010 | rtl_writephy(tp, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
1011 | } |
1012 | ||
e4fbce74 | 1013 | static void __rtl8169_check_link_status(struct net_device *dev, |
07d3f51f | 1014 | struct rtl8169_private *tp, |
e4fbce74 RW |
1015 | void __iomem *ioaddr, |
1016 | bool pm) | |
1da177e4 LT |
1017 | { |
1018 | unsigned long flags; | |
1019 | ||
1020 | spin_lock_irqsave(&tp->lock, flags); | |
1021 | if (tp->link_ok(ioaddr)) { | |
e1759441 | 1022 | /* This is to cancel a scheduled suspend if there's one. */ |
e4fbce74 RW |
1023 | if (pm) |
1024 | pm_request_resume(&tp->pci_dev->dev); | |
1da177e4 | 1025 | netif_carrier_on(dev); |
1519e57f FR |
1026 | if (net_ratelimit()) |
1027 | netif_info(tp, ifup, dev, "link up\n"); | |
b57b7e5a | 1028 | } else { |
1da177e4 | 1029 | netif_carrier_off(dev); |
bf82c189 | 1030 | netif_info(tp, ifdown, dev, "link down\n"); |
e4fbce74 RW |
1031 | if (pm) |
1032 | pm_schedule_suspend(&tp->pci_dev->dev, 100); | |
b57b7e5a | 1033 | } |
1da177e4 LT |
1034 | spin_unlock_irqrestore(&tp->lock, flags); |
1035 | } | |
1036 | ||
e4fbce74 RW |
1037 | static void rtl8169_check_link_status(struct net_device *dev, |
1038 | struct rtl8169_private *tp, | |
1039 | void __iomem *ioaddr) | |
1040 | { | |
1041 | __rtl8169_check_link_status(dev, tp, ioaddr, false); | |
1042 | } | |
1043 | ||
e1759441 RW |
1044 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) |
1045 | ||
1046 | static u32 __rtl8169_get_wol(struct rtl8169_private *tp) | |
61a4dcc2 | 1047 | { |
61a4dcc2 FR |
1048 | void __iomem *ioaddr = tp->mmio_addr; |
1049 | u8 options; | |
e1759441 | 1050 | u32 wolopts = 0; |
61a4dcc2 FR |
1051 | |
1052 | options = RTL_R8(Config1); | |
1053 | if (!(options & PMEnable)) | |
e1759441 | 1054 | return 0; |
61a4dcc2 FR |
1055 | |
1056 | options = RTL_R8(Config3); | |
1057 | if (options & LinkUp) | |
e1759441 | 1058 | wolopts |= WAKE_PHY; |
61a4dcc2 | 1059 | if (options & MagicPacket) |
e1759441 | 1060 | wolopts |= WAKE_MAGIC; |
61a4dcc2 FR |
1061 | |
1062 | options = RTL_R8(Config5); | |
1063 | if (options & UWF) | |
e1759441 | 1064 | wolopts |= WAKE_UCAST; |
61a4dcc2 | 1065 | if (options & BWF) |
e1759441 | 1066 | wolopts |= WAKE_BCAST; |
61a4dcc2 | 1067 | if (options & MWF) |
e1759441 | 1068 | wolopts |= WAKE_MCAST; |
61a4dcc2 | 1069 | |
e1759441 | 1070 | return wolopts; |
61a4dcc2 FR |
1071 | } |
1072 | ||
e1759441 | 1073 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
61a4dcc2 FR |
1074 | { |
1075 | struct rtl8169_private *tp = netdev_priv(dev); | |
e1759441 RW |
1076 | |
1077 | spin_lock_irq(&tp->lock); | |
1078 | ||
1079 | wol->supported = WAKE_ANY; | |
1080 | wol->wolopts = __rtl8169_get_wol(tp); | |
1081 | ||
1082 | spin_unlock_irq(&tp->lock); | |
1083 | } | |
1084 | ||
1085 | static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts) | |
1086 | { | |
61a4dcc2 | 1087 | void __iomem *ioaddr = tp->mmio_addr; |
07d3f51f | 1088 | unsigned int i; |
350f7596 | 1089 | static const struct { |
61a4dcc2 FR |
1090 | u32 opt; |
1091 | u16 reg; | |
1092 | u8 mask; | |
1093 | } cfg[] = { | |
1094 | { WAKE_ANY, Config1, PMEnable }, | |
1095 | { WAKE_PHY, Config3, LinkUp }, | |
1096 | { WAKE_MAGIC, Config3, MagicPacket }, | |
1097 | { WAKE_UCAST, Config5, UWF }, | |
1098 | { WAKE_BCAST, Config5, BWF }, | |
1099 | { WAKE_MCAST, Config5, MWF }, | |
1100 | { WAKE_ANY, Config5, LanWake } | |
1101 | }; | |
1102 | ||
61a4dcc2 FR |
1103 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
1104 | ||
1105 | for (i = 0; i < ARRAY_SIZE(cfg); i++) { | |
1106 | u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; | |
e1759441 | 1107 | if (wolopts & cfg[i].opt) |
61a4dcc2 FR |
1108 | options |= cfg[i].mask; |
1109 | RTL_W8(cfg[i].reg, options); | |
1110 | } | |
1111 | ||
1112 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
e1759441 RW |
1113 | } |
1114 | ||
1115 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
1116 | { | |
1117 | struct rtl8169_private *tp = netdev_priv(dev); | |
1118 | ||
1119 | spin_lock_irq(&tp->lock); | |
61a4dcc2 | 1120 | |
f23e7fda FR |
1121 | if (wol->wolopts) |
1122 | tp->features |= RTL_FEATURE_WOL; | |
1123 | else | |
1124 | tp->features &= ~RTL_FEATURE_WOL; | |
e1759441 | 1125 | __rtl8169_set_wol(tp, wol->wolopts); |
61a4dcc2 FR |
1126 | spin_unlock_irq(&tp->lock); |
1127 | ||
ea80907f | 1128 | device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
1129 | ||
61a4dcc2 FR |
1130 | return 0; |
1131 | } | |
1132 | ||
1da177e4 LT |
1133 | static void rtl8169_get_drvinfo(struct net_device *dev, |
1134 | struct ethtool_drvinfo *info) | |
1135 | { | |
1136 | struct rtl8169_private *tp = netdev_priv(dev); | |
1137 | ||
1138 | strcpy(info->driver, MODULENAME); | |
1139 | strcpy(info->version, RTL8169_VERSION); | |
1140 | strcpy(info->bus_info, pci_name(tp->pci_dev)); | |
1141 | } | |
1142 | ||
1143 | static int rtl8169_get_regs_len(struct net_device *dev) | |
1144 | { | |
1145 | return R8169_REGS_SIZE; | |
1146 | } | |
1147 | ||
1148 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
54405cde | 1149 | u8 autoneg, u16 speed, u8 duplex, u32 ignored) |
1da177e4 LT |
1150 | { |
1151 | struct rtl8169_private *tp = netdev_priv(dev); | |
1152 | void __iomem *ioaddr = tp->mmio_addr; | |
1153 | int ret = 0; | |
1154 | u32 reg; | |
1155 | ||
1156 | reg = RTL_R32(TBICSR); | |
1157 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && | |
1158 | (duplex == DUPLEX_FULL)) { | |
1159 | RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); | |
1160 | } else if (autoneg == AUTONEG_ENABLE) | |
1161 | RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); | |
1162 | else { | |
bf82c189 JP |
1163 | netif_warn(tp, link, dev, |
1164 | "incorrect speed setting refused in TBI mode\n"); | |
1da177e4 LT |
1165 | ret = -EOPNOTSUPP; |
1166 | } | |
1167 | ||
1168 | return ret; | |
1169 | } | |
1170 | ||
1171 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
54405cde | 1172 | u8 autoneg, u16 speed, u8 duplex, u32 adv) |
1da177e4 LT |
1173 | { |
1174 | struct rtl8169_private *tp = netdev_priv(dev); | |
3577aa1b | 1175 | int giga_ctrl, bmcr; |
54405cde | 1176 | int rc = -EINVAL; |
1da177e4 | 1177 | |
716b50a3 | 1178 | rtl_writephy(tp, 0x1f, 0x0000); |
1da177e4 LT |
1179 | |
1180 | if (autoneg == AUTONEG_ENABLE) { | |
3577aa1b | 1181 | int auto_nego; |
1182 | ||
4da19633 | 1183 | auto_nego = rtl_readphy(tp, MII_ADVERTISE); |
54405cde ON |
1184 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | |
1185 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
1186 | ||
1187 | if (adv & ADVERTISED_10baseT_Half) | |
1188 | auto_nego |= ADVERTISE_10HALF; | |
1189 | if (adv & ADVERTISED_10baseT_Full) | |
1190 | auto_nego |= ADVERTISE_10FULL; | |
1191 | if (adv & ADVERTISED_100baseT_Half) | |
1192 | auto_nego |= ADVERTISE_100HALF; | |
1193 | if (adv & ADVERTISED_100baseT_Full) | |
1194 | auto_nego |= ADVERTISE_100FULL; | |
1195 | ||
3577aa1b | 1196 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
1da177e4 | 1197 | |
4da19633 | 1198 | giga_ctrl = rtl_readphy(tp, MII_CTRL1000); |
3577aa1b | 1199 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
bcf0bf90 | 1200 | |
3577aa1b | 1201 | /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
1202 | if ((tp->mac_version != RTL_GIGA_MAC_VER_07) && | |
1203 | (tp->mac_version != RTL_GIGA_MAC_VER_08) && | |
1204 | (tp->mac_version != RTL_GIGA_MAC_VER_09) && | |
1205 | (tp->mac_version != RTL_GIGA_MAC_VER_10) && | |
1206 | (tp->mac_version != RTL_GIGA_MAC_VER_13) && | |
1207 | (tp->mac_version != RTL_GIGA_MAC_VER_14) && | |
1208 | (tp->mac_version != RTL_GIGA_MAC_VER_15) && | |
5a5e4443 HW |
1209 | (tp->mac_version != RTL_GIGA_MAC_VER_16) && |
1210 | (tp->mac_version != RTL_GIGA_MAC_VER_29) && | |
1211 | (tp->mac_version != RTL_GIGA_MAC_VER_30)) { | |
54405cde ON |
1212 | if (adv & ADVERTISED_1000baseT_Half) |
1213 | giga_ctrl |= ADVERTISE_1000HALF; | |
1214 | if (adv & ADVERTISED_1000baseT_Full) | |
1215 | giga_ctrl |= ADVERTISE_1000FULL; | |
1216 | } else if (adv & (ADVERTISED_1000baseT_Half | | |
1217 | ADVERTISED_1000baseT_Full)) { | |
bf82c189 JP |
1218 | netif_info(tp, link, dev, |
1219 | "PHY does not support 1000Mbps\n"); | |
54405cde | 1220 | goto out; |
bcf0bf90 | 1221 | } |
1da177e4 | 1222 | |
3577aa1b | 1223 | bmcr = BMCR_ANENABLE | BMCR_ANRESTART; |
1224 | ||
4da19633 | 1225 | rtl_writephy(tp, MII_ADVERTISE, auto_nego); |
1226 | rtl_writephy(tp, MII_CTRL1000, giga_ctrl); | |
3577aa1b | 1227 | } else { |
1228 | giga_ctrl = 0; | |
1229 | ||
1230 | if (speed == SPEED_10) | |
1231 | bmcr = 0; | |
1232 | else if (speed == SPEED_100) | |
1233 | bmcr = BMCR_SPEED100; | |
1234 | else | |
54405cde | 1235 | goto out; |
3577aa1b | 1236 | |
1237 | if (duplex == DUPLEX_FULL) | |
1238 | bmcr |= BMCR_FULLDPLX; | |
2584fbc3 RS |
1239 | } |
1240 | ||
1da177e4 LT |
1241 | tp->phy_1000_ctrl_reg = giga_ctrl; |
1242 | ||
4da19633 | 1243 | rtl_writephy(tp, MII_BMCR, bmcr); |
3577aa1b | 1244 | |
1245 | if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
1246 | (tp->mac_version == RTL_GIGA_MAC_VER_03)) { | |
1247 | if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) { | |
4da19633 | 1248 | rtl_writephy(tp, 0x17, 0x2138); |
1249 | rtl_writephy(tp, 0x0e, 0x0260); | |
3577aa1b | 1250 | } else { |
4da19633 | 1251 | rtl_writephy(tp, 0x17, 0x2108); |
1252 | rtl_writephy(tp, 0x0e, 0x0000); | |
3577aa1b | 1253 | } |
1254 | } | |
1255 | ||
54405cde ON |
1256 | rc = 0; |
1257 | out: | |
1258 | return rc; | |
1da177e4 LT |
1259 | } |
1260 | ||
1261 | static int rtl8169_set_speed(struct net_device *dev, | |
54405cde | 1262 | u8 autoneg, u16 speed, u8 duplex, u32 advertising) |
1da177e4 LT |
1263 | { |
1264 | struct rtl8169_private *tp = netdev_priv(dev); | |
1265 | int ret; | |
1266 | ||
54405cde | 1267 | ret = tp->set_speed(dev, autoneg, speed, duplex, advertising); |
1da177e4 | 1268 | |
64e4bfb4 | 1269 | if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
1da177e4 LT |
1270 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
1271 | ||
1272 | return ret; | |
1273 | } | |
1274 | ||
1275 | static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1276 | { | |
1277 | struct rtl8169_private *tp = netdev_priv(dev); | |
1278 | unsigned long flags; | |
1279 | int ret; | |
1280 | ||
1281 | spin_lock_irqsave(&tp->lock, flags); | |
54405cde ON |
1282 | ret = rtl8169_set_speed(dev, |
1283 | cmd->autoneg, cmd->speed, cmd->duplex, cmd->advertising); | |
1da177e4 | 1284 | spin_unlock_irqrestore(&tp->lock, flags); |
5b0384f4 | 1285 | |
1da177e4 LT |
1286 | return ret; |
1287 | } | |
1288 | ||
1289 | static u32 rtl8169_get_rx_csum(struct net_device *dev) | |
1290 | { | |
1291 | struct rtl8169_private *tp = netdev_priv(dev); | |
1292 | ||
1293 | return tp->cp_cmd & RxChkSum; | |
1294 | } | |
1295 | ||
1296 | static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) | |
1297 | { | |
1298 | struct rtl8169_private *tp = netdev_priv(dev); | |
1299 | void __iomem *ioaddr = tp->mmio_addr; | |
1300 | unsigned long flags; | |
1301 | ||
1302 | spin_lock_irqsave(&tp->lock, flags); | |
1303 | ||
1304 | if (data) | |
1305 | tp->cp_cmd |= RxChkSum; | |
1306 | else | |
1307 | tp->cp_cmd &= ~RxChkSum; | |
1308 | ||
1309 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
1310 | RTL_R16(CPlusCmd); | |
1311 | ||
1312 | spin_unlock_irqrestore(&tp->lock, flags); | |
1313 | ||
1314 | return 0; | |
1315 | } | |
1316 | ||
1da177e4 LT |
1317 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, |
1318 | struct sk_buff *skb) | |
1319 | { | |
eab6d18d | 1320 | return (vlan_tx_tag_present(skb)) ? |
1da177e4 LT |
1321 | TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; |
1322 | } | |
1323 | ||
7a8fc77b FR |
1324 | #define NETIF_F_HW_VLAN_TX_RX (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX) |
1325 | ||
1326 | static void rtl8169_vlan_mode(struct net_device *dev) | |
1da177e4 LT |
1327 | { |
1328 | struct rtl8169_private *tp = netdev_priv(dev); | |
1329 | void __iomem *ioaddr = tp->mmio_addr; | |
1330 | unsigned long flags; | |
1331 | ||
1332 | spin_lock_irqsave(&tp->lock, flags); | |
7a8fc77b | 1333 | if (dev->features & NETIF_F_HW_VLAN_RX) |
1da177e4 LT |
1334 | tp->cp_cmd |= RxVlan; |
1335 | else | |
1336 | tp->cp_cmd &= ~RxVlan; | |
1337 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
7a8fc77b | 1338 | /* PCI commit */ |
1da177e4 LT |
1339 | RTL_R16(CPlusCmd); |
1340 | spin_unlock_irqrestore(&tp->lock, flags); | |
7a8fc77b FR |
1341 | |
1342 | dev->vlan_features = dev->features &~ NETIF_F_HW_VLAN_TX_RX; | |
1da177e4 LT |
1343 | } |
1344 | ||
7a8fc77b | 1345 | static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb) |
1da177e4 LT |
1346 | { |
1347 | u32 opts2 = le32_to_cpu(desc->opts2); | |
1da177e4 | 1348 | |
7a8fc77b FR |
1349 | if (opts2 & RxVlanTag) |
1350 | __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff)); | |
2edae08e | 1351 | |
1da177e4 | 1352 | desc->opts2 = 0; |
1da177e4 LT |
1353 | } |
1354 | ||
ccdffb9a | 1355 | static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1356 | { |
1357 | struct rtl8169_private *tp = netdev_priv(dev); | |
1358 | void __iomem *ioaddr = tp->mmio_addr; | |
1359 | u32 status; | |
1360 | ||
1361 | cmd->supported = | |
1362 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; | |
1363 | cmd->port = PORT_FIBRE; | |
1364 | cmd->transceiver = XCVR_INTERNAL; | |
1365 | ||
1366 | status = RTL_R32(TBICSR); | |
1367 | cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; | |
1368 | cmd->autoneg = !!(status & TBINwEnable); | |
1369 | ||
1370 | cmd->speed = SPEED_1000; | |
1371 | cmd->duplex = DUPLEX_FULL; /* Always set */ | |
ccdffb9a FR |
1372 | |
1373 | return 0; | |
1da177e4 LT |
1374 | } |
1375 | ||
ccdffb9a | 1376 | static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1377 | { |
1378 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a FR |
1379 | |
1380 | return mii_ethtool_gset(&tp->mii, cmd); | |
1da177e4 LT |
1381 | } |
1382 | ||
1383 | static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1384 | { | |
1385 | struct rtl8169_private *tp = netdev_priv(dev); | |
1386 | unsigned long flags; | |
ccdffb9a | 1387 | int rc; |
1da177e4 LT |
1388 | |
1389 | spin_lock_irqsave(&tp->lock, flags); | |
1390 | ||
ccdffb9a | 1391 | rc = tp->get_settings(dev, cmd); |
1da177e4 LT |
1392 | |
1393 | spin_unlock_irqrestore(&tp->lock, flags); | |
ccdffb9a | 1394 | return rc; |
1da177e4 LT |
1395 | } |
1396 | ||
1397 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1398 | void *p) | |
1399 | { | |
5b0384f4 FR |
1400 | struct rtl8169_private *tp = netdev_priv(dev); |
1401 | unsigned long flags; | |
1da177e4 | 1402 | |
5b0384f4 FR |
1403 | if (regs->len > R8169_REGS_SIZE) |
1404 | regs->len = R8169_REGS_SIZE; | |
1da177e4 | 1405 | |
5b0384f4 FR |
1406 | spin_lock_irqsave(&tp->lock, flags); |
1407 | memcpy_fromio(p, tp->mmio_addr, regs->len); | |
1408 | spin_unlock_irqrestore(&tp->lock, flags); | |
1da177e4 LT |
1409 | } |
1410 | ||
b57b7e5a SH |
1411 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
1412 | { | |
1413 | struct rtl8169_private *tp = netdev_priv(dev); | |
1414 | ||
1415 | return tp->msg_enable; | |
1416 | } | |
1417 | ||
1418 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
1419 | { | |
1420 | struct rtl8169_private *tp = netdev_priv(dev); | |
1421 | ||
1422 | tp->msg_enable = value; | |
1423 | } | |
1424 | ||
d4a3a0fc SH |
1425 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
1426 | "tx_packets", | |
1427 | "rx_packets", | |
1428 | "tx_errors", | |
1429 | "rx_errors", | |
1430 | "rx_missed", | |
1431 | "align_errors", | |
1432 | "tx_single_collisions", | |
1433 | "tx_multi_collisions", | |
1434 | "unicast", | |
1435 | "broadcast", | |
1436 | "multicast", | |
1437 | "tx_aborted", | |
1438 | "tx_underrun", | |
1439 | }; | |
1440 | ||
b9f2c044 | 1441 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 1442 | { |
b9f2c044 JG |
1443 | switch (sset) { |
1444 | case ETH_SS_STATS: | |
1445 | return ARRAY_SIZE(rtl8169_gstrings); | |
1446 | default: | |
1447 | return -EOPNOTSUPP; | |
1448 | } | |
d4a3a0fc SH |
1449 | } |
1450 | ||
355423d0 | 1451 | static void rtl8169_update_counters(struct net_device *dev) |
d4a3a0fc SH |
1452 | { |
1453 | struct rtl8169_private *tp = netdev_priv(dev); | |
1454 | void __iomem *ioaddr = tp->mmio_addr; | |
1455 | struct rtl8169_counters *counters; | |
1456 | dma_addr_t paddr; | |
1457 | u32 cmd; | |
355423d0 | 1458 | int wait = 1000; |
48addcc9 | 1459 | struct device *d = &tp->pci_dev->dev; |
d4a3a0fc | 1460 | |
355423d0 IV |
1461 | /* |
1462 | * Some chips are unable to dump tally counters when the receiver | |
1463 | * is disabled. | |
1464 | */ | |
1465 | if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0) | |
1466 | return; | |
d4a3a0fc | 1467 | |
48addcc9 | 1468 | counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL); |
d4a3a0fc SH |
1469 | if (!counters) |
1470 | return; | |
1471 | ||
1472 | RTL_W32(CounterAddrHigh, (u64)paddr >> 32); | |
284901a9 | 1473 | cmd = (u64)paddr & DMA_BIT_MASK(32); |
d4a3a0fc SH |
1474 | RTL_W32(CounterAddrLow, cmd); |
1475 | RTL_W32(CounterAddrLow, cmd | CounterDump); | |
1476 | ||
355423d0 IV |
1477 | while (wait--) { |
1478 | if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) { | |
1479 | /* copy updated counters */ | |
1480 | memcpy(&tp->counters, counters, sizeof(*counters)); | |
d4a3a0fc | 1481 | break; |
355423d0 IV |
1482 | } |
1483 | udelay(10); | |
d4a3a0fc SH |
1484 | } |
1485 | ||
1486 | RTL_W32(CounterAddrLow, 0); | |
1487 | RTL_W32(CounterAddrHigh, 0); | |
1488 | ||
48addcc9 | 1489 | dma_free_coherent(d, sizeof(*counters), counters, paddr); |
d4a3a0fc SH |
1490 | } |
1491 | ||
355423d0 IV |
1492 | static void rtl8169_get_ethtool_stats(struct net_device *dev, |
1493 | struct ethtool_stats *stats, u64 *data) | |
1494 | { | |
1495 | struct rtl8169_private *tp = netdev_priv(dev); | |
1496 | ||
1497 | ASSERT_RTNL(); | |
1498 | ||
1499 | rtl8169_update_counters(dev); | |
1500 | ||
1501 | data[0] = le64_to_cpu(tp->counters.tx_packets); | |
1502 | data[1] = le64_to_cpu(tp->counters.rx_packets); | |
1503 | data[2] = le64_to_cpu(tp->counters.tx_errors); | |
1504 | data[3] = le32_to_cpu(tp->counters.rx_errors); | |
1505 | data[4] = le16_to_cpu(tp->counters.rx_missed); | |
1506 | data[5] = le16_to_cpu(tp->counters.align_errors); | |
1507 | data[6] = le32_to_cpu(tp->counters.tx_one_collision); | |
1508 | data[7] = le32_to_cpu(tp->counters.tx_multi_collision); | |
1509 | data[8] = le64_to_cpu(tp->counters.rx_unicast); | |
1510 | data[9] = le64_to_cpu(tp->counters.rx_broadcast); | |
1511 | data[10] = le32_to_cpu(tp->counters.rx_multicast); | |
1512 | data[11] = le16_to_cpu(tp->counters.tx_aborted); | |
1513 | data[12] = le16_to_cpu(tp->counters.tx_underun); | |
1514 | } | |
1515 | ||
d4a3a0fc SH |
1516 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) |
1517 | { | |
1518 | switch(stringset) { | |
1519 | case ETH_SS_STATS: | |
1520 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
1521 | break; | |
1522 | } | |
1523 | } | |
1524 | ||
7a8fc77b FR |
1525 | static int rtl8169_set_flags(struct net_device *dev, u32 data) |
1526 | { | |
1527 | struct rtl8169_private *tp = netdev_priv(dev); | |
1528 | unsigned long old_feat = dev->features; | |
1529 | int rc; | |
1530 | ||
1531 | if ((tp->mac_version == RTL_GIGA_MAC_VER_05) && | |
1532 | !(data & ETH_FLAG_RXVLAN)) { | |
1533 | netif_info(tp, drv, dev, "8110SCd requires hardware Rx VLAN\n"); | |
1534 | return -EINVAL; | |
1535 | } | |
1536 | ||
1537 | rc = ethtool_op_set_flags(dev, data, ETH_FLAG_TXVLAN | ETH_FLAG_RXVLAN); | |
1538 | if (rc) | |
1539 | return rc; | |
1540 | ||
1541 | if ((old_feat ^ dev->features) & NETIF_F_HW_VLAN_RX) | |
1542 | rtl8169_vlan_mode(dev); | |
1543 | ||
1544 | return 0; | |
1545 | } | |
1546 | ||
7282d491 | 1547 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
1548 | .get_drvinfo = rtl8169_get_drvinfo, |
1549 | .get_regs_len = rtl8169_get_regs_len, | |
1550 | .get_link = ethtool_op_get_link, | |
1551 | .get_settings = rtl8169_get_settings, | |
1552 | .set_settings = rtl8169_set_settings, | |
b57b7e5a SH |
1553 | .get_msglevel = rtl8169_get_msglevel, |
1554 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 LT |
1555 | .get_rx_csum = rtl8169_get_rx_csum, |
1556 | .set_rx_csum = rtl8169_set_rx_csum, | |
1da177e4 | 1557 | .set_tx_csum = ethtool_op_set_tx_csum, |
1da177e4 | 1558 | .set_sg = ethtool_op_set_sg, |
1da177e4 LT |
1559 | .set_tso = ethtool_op_set_tso, |
1560 | .get_regs = rtl8169_get_regs, | |
61a4dcc2 FR |
1561 | .get_wol = rtl8169_get_wol, |
1562 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 1563 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 1564 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 1565 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
7a8fc77b FR |
1566 | .set_flags = rtl8169_set_flags, |
1567 | .get_flags = ethtool_op_get_flags, | |
1da177e4 LT |
1568 | }; |
1569 | ||
07d3f51f FR |
1570 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
1571 | void __iomem *ioaddr) | |
1da177e4 | 1572 | { |
0e485150 FR |
1573 | /* |
1574 | * The driver currently handles the 8168Bf and the 8168Be identically | |
1575 | * but they can be identified more specifically through the test below | |
1576 | * if needed: | |
1577 | * | |
1578 | * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be | |
0127215c FR |
1579 | * |
1580 | * Same thing for the 8101Eb and the 8101Ec: | |
1581 | * | |
1582 | * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec | |
0e485150 | 1583 | */ |
350f7596 | 1584 | static const struct { |
1da177e4 | 1585 | u32 mask; |
e3cf0cc0 | 1586 | u32 val; |
1da177e4 LT |
1587 | int mac_version; |
1588 | } mac_info[] = { | |
01dc7fec | 1589 | /* 8168E family. */ |
1590 | { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 }, | |
1591 | { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 }, | |
1592 | { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 }, | |
1593 | ||
5b538df9 | 1594 | /* 8168D family. */ |
daf9df6d | 1595 | { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 }, |
1596 | { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 }, | |
daf9df6d | 1597 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 }, |
5b538df9 | 1598 | |
e6de30d6 | 1599 | /* 8168DP family. */ |
1600 | { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 }, | |
1601 | { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 }, | |
4804b3b3 | 1602 | { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 }, |
e6de30d6 | 1603 | |
ef808d50 | 1604 | /* 8168C family. */ |
17c99297 | 1605 | { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 }, |
ef3386f0 | 1606 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
ef808d50 | 1607 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
7f3e3d3a | 1608 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
e3cf0cc0 FR |
1609 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
1610 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
197ff761 | 1611 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
6fb07058 | 1612 | { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
ef808d50 | 1613 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
e3cf0cc0 FR |
1614 | |
1615 | /* 8168B family. */ | |
1616 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
1617 | { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, | |
1618 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, | |
1619 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
1620 | ||
1621 | /* 8101 family. */ | |
36a0e6c2 | 1622 | { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 }, |
5a5e4443 HW |
1623 | { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 }, |
1624 | { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 }, | |
1625 | { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 }, | |
2857ffb7 FR |
1626 | { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
1627 | { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, | |
1628 | { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, | |
1629 | { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, | |
1630 | { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, | |
1631 | { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, | |
e3cf0cc0 | 1632 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
2857ffb7 | 1633 | { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
e3cf0cc0 | 1634 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
2857ffb7 FR |
1635 | { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
1636 | { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, | |
e3cf0cc0 FR |
1637 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
1638 | /* FIXME: where did these entries come from ? -- FR */ | |
1639 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
1640 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
1641 | ||
1642 | /* 8110 family. */ | |
1643 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
1644 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
1645 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
1646 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
1647 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
1648 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
1649 | ||
f21b75e9 JD |
1650 | /* Catch-all */ |
1651 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE } | |
1da177e4 LT |
1652 | }, *p = mac_info; |
1653 | u32 reg; | |
1654 | ||
e3cf0cc0 FR |
1655 | reg = RTL_R32(TxConfig); |
1656 | while ((reg & p->mask) != p->val) | |
1da177e4 LT |
1657 | p++; |
1658 | tp->mac_version = p->mac_version; | |
1659 | } | |
1660 | ||
1661 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
1662 | { | |
bcf0bf90 | 1663 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
1664 | } |
1665 | ||
867763c1 FR |
1666 | struct phy_reg { |
1667 | u16 reg; | |
1668 | u16 val; | |
1669 | }; | |
1670 | ||
4da19633 | 1671 | static void rtl_writephy_batch(struct rtl8169_private *tp, |
1672 | const struct phy_reg *regs, int len) | |
867763c1 FR |
1673 | { |
1674 | while (len-- > 0) { | |
4da19633 | 1675 | rtl_writephy(tp, regs->reg, regs->val); |
867763c1 FR |
1676 | regs++; |
1677 | } | |
1678 | } | |
1679 | ||
bca03d5f | 1680 | #define PHY_READ 0x00000000 |
1681 | #define PHY_DATA_OR 0x10000000 | |
1682 | #define PHY_DATA_AND 0x20000000 | |
1683 | #define PHY_BJMPN 0x30000000 | |
1684 | #define PHY_READ_EFUSE 0x40000000 | |
1685 | #define PHY_READ_MAC_BYTE 0x50000000 | |
1686 | #define PHY_WRITE_MAC_BYTE 0x60000000 | |
1687 | #define PHY_CLEAR_READCOUNT 0x70000000 | |
1688 | #define PHY_WRITE 0x80000000 | |
1689 | #define PHY_READCOUNT_EQ_SKIP 0x90000000 | |
1690 | #define PHY_COMP_EQ_SKIPN 0xa0000000 | |
1691 | #define PHY_COMP_NEQ_SKIPN 0xb0000000 | |
1692 | #define PHY_WRITE_PREVIOUS 0xc0000000 | |
1693 | #define PHY_SKIPN 0xd0000000 | |
1694 | #define PHY_DELAY_MS 0xe0000000 | |
1695 | #define PHY_WRITE_ERI_WORD 0xf0000000 | |
1696 | ||
1697 | static void | |
1698 | rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw) | |
1699 | { | |
bca03d5f | 1700 | __le32 *phytable = (__le32 *)fw->data; |
1701 | struct net_device *dev = tp->dev; | |
42b82dc1 | 1702 | size_t index, fw_size = fw->size / sizeof(*phytable); |
1703 | u32 predata, count; | |
bca03d5f | 1704 | |
1705 | if (fw->size % sizeof(*phytable)) { | |
1706 | netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size); | |
1707 | return; | |
1708 | } | |
1709 | ||
42b82dc1 | 1710 | for (index = 0; index < fw_size; index++) { |
1711 | u32 action = le32_to_cpu(phytable[index]); | |
1712 | u32 regno = (action & 0x0fff0000) >> 16; | |
bca03d5f | 1713 | |
42b82dc1 | 1714 | switch(action & 0xf0000000) { |
1715 | case PHY_READ: | |
1716 | case PHY_DATA_OR: | |
1717 | case PHY_DATA_AND: | |
1718 | case PHY_READ_EFUSE: | |
1719 | case PHY_CLEAR_READCOUNT: | |
1720 | case PHY_WRITE: | |
1721 | case PHY_WRITE_PREVIOUS: | |
1722 | case PHY_DELAY_MS: | |
1723 | break; | |
1724 | ||
1725 | case PHY_BJMPN: | |
1726 | if (regno > index) { | |
1727 | netif_err(tp, probe, tp->dev, | |
1728 | "Out of range of firmware\n"); | |
1729 | return; | |
1730 | } | |
1731 | break; | |
1732 | case PHY_READCOUNT_EQ_SKIP: | |
1733 | if (index + 2 >= fw_size) { | |
1734 | netif_err(tp, probe, tp->dev, | |
1735 | "Out of range of firmware\n"); | |
1736 | return; | |
1737 | } | |
1738 | break; | |
1739 | case PHY_COMP_EQ_SKIPN: | |
1740 | case PHY_COMP_NEQ_SKIPN: | |
1741 | case PHY_SKIPN: | |
1742 | if (index + 1 + regno >= fw_size) { | |
1743 | netif_err(tp, probe, tp->dev, | |
1744 | "Out of range of firmware\n"); | |
1745 | return; | |
1746 | } | |
bca03d5f | 1747 | break; |
1748 | ||
42b82dc1 | 1749 | case PHY_READ_MAC_BYTE: |
1750 | case PHY_WRITE_MAC_BYTE: | |
1751 | case PHY_WRITE_ERI_WORD: | |
1752 | default: | |
1753 | netif_err(tp, probe, tp->dev, | |
1754 | "Invalid action 0x%08x\n", action); | |
bca03d5f | 1755 | return; |
1756 | } | |
1757 | } | |
1758 | ||
42b82dc1 | 1759 | predata = 0; |
1760 | count = 0; | |
1761 | ||
1762 | for (index = 0; index < fw_size; ) { | |
1763 | u32 action = le32_to_cpu(phytable[index]); | |
bca03d5f | 1764 | u32 data = action & 0x0000ffff; |
42b82dc1 | 1765 | u32 regno = (action & 0x0fff0000) >> 16; |
1766 | ||
1767 | if (!action) | |
1768 | break; | |
bca03d5f | 1769 | |
1770 | switch(action & 0xf0000000) { | |
42b82dc1 | 1771 | case PHY_READ: |
1772 | predata = rtl_readphy(tp, regno); | |
1773 | count++; | |
1774 | index++; | |
1775 | break; | |
1776 | case PHY_DATA_OR: | |
1777 | predata |= data; | |
1778 | index++; | |
1779 | break; | |
1780 | case PHY_DATA_AND: | |
1781 | predata &= data; | |
1782 | index++; | |
1783 | break; | |
1784 | case PHY_BJMPN: | |
1785 | index -= regno; | |
1786 | break; | |
1787 | case PHY_READ_EFUSE: | |
1788 | predata = rtl8168d_efuse_read(tp->mmio_addr, regno); | |
1789 | index++; | |
1790 | break; | |
1791 | case PHY_CLEAR_READCOUNT: | |
1792 | count = 0; | |
1793 | index++; | |
1794 | break; | |
bca03d5f | 1795 | case PHY_WRITE: |
42b82dc1 | 1796 | rtl_writephy(tp, regno, data); |
1797 | index++; | |
1798 | break; | |
1799 | case PHY_READCOUNT_EQ_SKIP: | |
1800 | if (count == data) | |
1801 | index += 2; | |
1802 | else | |
1803 | index += 1; | |
bca03d5f | 1804 | break; |
42b82dc1 | 1805 | case PHY_COMP_EQ_SKIPN: |
1806 | if (predata == data) | |
1807 | index += regno; | |
1808 | index++; | |
1809 | break; | |
1810 | case PHY_COMP_NEQ_SKIPN: | |
1811 | if (predata != data) | |
1812 | index += regno; | |
1813 | index++; | |
1814 | break; | |
1815 | case PHY_WRITE_PREVIOUS: | |
1816 | rtl_writephy(tp, regno, predata); | |
1817 | index++; | |
1818 | break; | |
1819 | case PHY_SKIPN: | |
1820 | index += regno + 1; | |
1821 | break; | |
1822 | case PHY_DELAY_MS: | |
1823 | mdelay(data); | |
1824 | index++; | |
1825 | break; | |
1826 | ||
1827 | case PHY_READ_MAC_BYTE: | |
1828 | case PHY_WRITE_MAC_BYTE: | |
1829 | case PHY_WRITE_ERI_WORD: | |
bca03d5f | 1830 | default: |
1831 | BUG(); | |
1832 | } | |
1833 | } | |
1834 | } | |
1835 | ||
f1e02ed1 | 1836 | static void rtl_release_firmware(struct rtl8169_private *tp) |
1837 | { | |
1838 | release_firmware(tp->fw); | |
1839 | tp->fw = NULL; | |
1840 | } | |
1841 | ||
1842 | static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name) | |
1843 | { | |
1844 | const struct firmware **fw = &tp->fw; | |
1845 | int rc = !*fw; | |
1846 | ||
1847 | if (rc) { | |
1848 | rc = request_firmware(fw, fw_name, &tp->pci_dev->dev); | |
1849 | if (rc < 0) | |
1850 | goto out; | |
1851 | } | |
1852 | ||
1853 | /* TODO: release firmware once rtl_phy_write_fw signals failures. */ | |
1854 | rtl_phy_write_fw(tp, *fw); | |
1855 | out: | |
1856 | return rc; | |
1857 | } | |
1858 | ||
4da19633 | 1859 | static void rtl8169s_hw_phy_config(struct rtl8169_private *tp) |
1da177e4 | 1860 | { |
350f7596 | 1861 | static const struct phy_reg phy_reg_init[] = { |
0b9b571d | 1862 | { 0x1f, 0x0001 }, |
1863 | { 0x06, 0x006e }, | |
1864 | { 0x08, 0x0708 }, | |
1865 | { 0x15, 0x4000 }, | |
1866 | { 0x18, 0x65c7 }, | |
1da177e4 | 1867 | |
0b9b571d | 1868 | { 0x1f, 0x0001 }, |
1869 | { 0x03, 0x00a1 }, | |
1870 | { 0x02, 0x0008 }, | |
1871 | { 0x01, 0x0120 }, | |
1872 | { 0x00, 0x1000 }, | |
1873 | { 0x04, 0x0800 }, | |
1874 | { 0x04, 0x0000 }, | |
1da177e4 | 1875 | |
0b9b571d | 1876 | { 0x03, 0xff41 }, |
1877 | { 0x02, 0xdf60 }, | |
1878 | { 0x01, 0x0140 }, | |
1879 | { 0x00, 0x0077 }, | |
1880 | { 0x04, 0x7800 }, | |
1881 | { 0x04, 0x7000 }, | |
1882 | ||
1883 | { 0x03, 0x802f }, | |
1884 | { 0x02, 0x4f02 }, | |
1885 | { 0x01, 0x0409 }, | |
1886 | { 0x00, 0xf0f9 }, | |
1887 | { 0x04, 0x9800 }, | |
1888 | { 0x04, 0x9000 }, | |
1889 | ||
1890 | { 0x03, 0xdf01 }, | |
1891 | { 0x02, 0xdf20 }, | |
1892 | { 0x01, 0xff95 }, | |
1893 | { 0x00, 0xba00 }, | |
1894 | { 0x04, 0xa800 }, | |
1895 | { 0x04, 0xa000 }, | |
1896 | ||
1897 | { 0x03, 0xff41 }, | |
1898 | { 0x02, 0xdf20 }, | |
1899 | { 0x01, 0x0140 }, | |
1900 | { 0x00, 0x00bb }, | |
1901 | { 0x04, 0xb800 }, | |
1902 | { 0x04, 0xb000 }, | |
1903 | ||
1904 | { 0x03, 0xdf41 }, | |
1905 | { 0x02, 0xdc60 }, | |
1906 | { 0x01, 0x6340 }, | |
1907 | { 0x00, 0x007d }, | |
1908 | { 0x04, 0xd800 }, | |
1909 | { 0x04, 0xd000 }, | |
1910 | ||
1911 | { 0x03, 0xdf01 }, | |
1912 | { 0x02, 0xdf20 }, | |
1913 | { 0x01, 0x100a }, | |
1914 | { 0x00, 0xa0ff }, | |
1915 | { 0x04, 0xf800 }, | |
1916 | { 0x04, 0xf000 }, | |
1917 | ||
1918 | { 0x1f, 0x0000 }, | |
1919 | { 0x0b, 0x0000 }, | |
1920 | { 0x00, 0x9200 } | |
1921 | }; | |
1da177e4 | 1922 | |
4da19633 | 1923 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
1da177e4 LT |
1924 | } |
1925 | ||
4da19633 | 1926 | static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp) |
5615d9f1 | 1927 | { |
350f7596 | 1928 | static const struct phy_reg phy_reg_init[] = { |
a441d7b6 FR |
1929 | { 0x1f, 0x0002 }, |
1930 | { 0x01, 0x90d0 }, | |
1931 | { 0x1f, 0x0000 } | |
1932 | }; | |
1933 | ||
4da19633 | 1934 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5615d9f1 FR |
1935 | } |
1936 | ||
4da19633 | 1937 | static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp) |
2e955856 | 1938 | { |
1939 | struct pci_dev *pdev = tp->pci_dev; | |
1940 | u16 vendor_id, device_id; | |
1941 | ||
1942 | pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id); | |
1943 | pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id); | |
1944 | ||
1945 | if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000)) | |
1946 | return; | |
1947 | ||
4da19633 | 1948 | rtl_writephy(tp, 0x1f, 0x0001); |
1949 | rtl_writephy(tp, 0x10, 0xf01b); | |
1950 | rtl_writephy(tp, 0x1f, 0x0000); | |
2e955856 | 1951 | } |
1952 | ||
4da19633 | 1953 | static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp) |
2e955856 | 1954 | { |
350f7596 | 1955 | static const struct phy_reg phy_reg_init[] = { |
2e955856 | 1956 | { 0x1f, 0x0001 }, |
1957 | { 0x04, 0x0000 }, | |
1958 | { 0x03, 0x00a1 }, | |
1959 | { 0x02, 0x0008 }, | |
1960 | { 0x01, 0x0120 }, | |
1961 | { 0x00, 0x1000 }, | |
1962 | { 0x04, 0x0800 }, | |
1963 | { 0x04, 0x9000 }, | |
1964 | { 0x03, 0x802f }, | |
1965 | { 0x02, 0x4f02 }, | |
1966 | { 0x01, 0x0409 }, | |
1967 | { 0x00, 0xf099 }, | |
1968 | { 0x04, 0x9800 }, | |
1969 | { 0x04, 0xa000 }, | |
1970 | { 0x03, 0xdf01 }, | |
1971 | { 0x02, 0xdf20 }, | |
1972 | { 0x01, 0xff95 }, | |
1973 | { 0x00, 0xba00 }, | |
1974 | { 0x04, 0xa800 }, | |
1975 | { 0x04, 0xf000 }, | |
1976 | { 0x03, 0xdf01 }, | |
1977 | { 0x02, 0xdf20 }, | |
1978 | { 0x01, 0x101a }, | |
1979 | { 0x00, 0xa0ff }, | |
1980 | { 0x04, 0xf800 }, | |
1981 | { 0x04, 0x0000 }, | |
1982 | { 0x1f, 0x0000 }, | |
1983 | ||
1984 | { 0x1f, 0x0001 }, | |
1985 | { 0x10, 0xf41b }, | |
1986 | { 0x14, 0xfb54 }, | |
1987 | { 0x18, 0xf5c7 }, | |
1988 | { 0x1f, 0x0000 }, | |
1989 | ||
1990 | { 0x1f, 0x0001 }, | |
1991 | { 0x17, 0x0cc0 }, | |
1992 | { 0x1f, 0x0000 } | |
1993 | }; | |
1994 | ||
4da19633 | 1995 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2e955856 | 1996 | |
4da19633 | 1997 | rtl8169scd_hw_phy_config_quirk(tp); |
2e955856 | 1998 | } |
1999 | ||
4da19633 | 2000 | static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp) |
8c7006aa | 2001 | { |
350f7596 | 2002 | static const struct phy_reg phy_reg_init[] = { |
8c7006aa | 2003 | { 0x1f, 0x0001 }, |
2004 | { 0x04, 0x0000 }, | |
2005 | { 0x03, 0x00a1 }, | |
2006 | { 0x02, 0x0008 }, | |
2007 | { 0x01, 0x0120 }, | |
2008 | { 0x00, 0x1000 }, | |
2009 | { 0x04, 0x0800 }, | |
2010 | { 0x04, 0x9000 }, | |
2011 | { 0x03, 0x802f }, | |
2012 | { 0x02, 0x4f02 }, | |
2013 | { 0x01, 0x0409 }, | |
2014 | { 0x00, 0xf099 }, | |
2015 | { 0x04, 0x9800 }, | |
2016 | { 0x04, 0xa000 }, | |
2017 | { 0x03, 0xdf01 }, | |
2018 | { 0x02, 0xdf20 }, | |
2019 | { 0x01, 0xff95 }, | |
2020 | { 0x00, 0xba00 }, | |
2021 | { 0x04, 0xa800 }, | |
2022 | { 0x04, 0xf000 }, | |
2023 | { 0x03, 0xdf01 }, | |
2024 | { 0x02, 0xdf20 }, | |
2025 | { 0x01, 0x101a }, | |
2026 | { 0x00, 0xa0ff }, | |
2027 | { 0x04, 0xf800 }, | |
2028 | { 0x04, 0x0000 }, | |
2029 | { 0x1f, 0x0000 }, | |
2030 | ||
2031 | { 0x1f, 0x0001 }, | |
2032 | { 0x0b, 0x8480 }, | |
2033 | { 0x1f, 0x0000 }, | |
2034 | ||
2035 | { 0x1f, 0x0001 }, | |
2036 | { 0x18, 0x67c7 }, | |
2037 | { 0x04, 0x2000 }, | |
2038 | { 0x03, 0x002f }, | |
2039 | { 0x02, 0x4360 }, | |
2040 | { 0x01, 0x0109 }, | |
2041 | { 0x00, 0x3022 }, | |
2042 | { 0x04, 0x2800 }, | |
2043 | { 0x1f, 0x0000 }, | |
2044 | ||
2045 | { 0x1f, 0x0001 }, | |
2046 | { 0x17, 0x0cc0 }, | |
2047 | { 0x1f, 0x0000 } | |
2048 | }; | |
2049 | ||
4da19633 | 2050 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
8c7006aa | 2051 | } |
2052 | ||
4da19633 | 2053 | static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2054 | { |
350f7596 | 2055 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2056 | { 0x10, 0xf41b }, |
2057 | { 0x1f, 0x0000 } | |
2058 | }; | |
2059 | ||
4da19633 | 2060 | rtl_writephy(tp, 0x1f, 0x0001); |
2061 | rtl_patchphy(tp, 0x16, 1 << 0); | |
236b8082 | 2062 | |
4da19633 | 2063 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2064 | } |
2065 | ||
4da19633 | 2066 | static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp) |
236b8082 | 2067 | { |
350f7596 | 2068 | static const struct phy_reg phy_reg_init[] = { |
236b8082 FR |
2069 | { 0x1f, 0x0001 }, |
2070 | { 0x10, 0xf41b }, | |
2071 | { 0x1f, 0x0000 } | |
2072 | }; | |
2073 | ||
4da19633 | 2074 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
236b8082 FR |
2075 | } |
2076 | ||
4da19633 | 2077 | static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2078 | { |
350f7596 | 2079 | static const struct phy_reg phy_reg_init[] = { |
867763c1 FR |
2080 | { 0x1f, 0x0000 }, |
2081 | { 0x1d, 0x0f00 }, | |
2082 | { 0x1f, 0x0002 }, | |
2083 | { 0x0c, 0x1ec8 }, | |
2084 | { 0x1f, 0x0000 } | |
2085 | }; | |
2086 | ||
4da19633 | 2087 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
867763c1 FR |
2088 | } |
2089 | ||
4da19633 | 2090 | static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp) |
ef3386f0 | 2091 | { |
350f7596 | 2092 | static const struct phy_reg phy_reg_init[] = { |
ef3386f0 FR |
2093 | { 0x1f, 0x0001 }, |
2094 | { 0x1d, 0x3d98 }, | |
2095 | { 0x1f, 0x0000 } | |
2096 | }; | |
2097 | ||
4da19633 | 2098 | rtl_writephy(tp, 0x1f, 0x0000); |
2099 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2100 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
ef3386f0 | 2101 | |
4da19633 | 2102 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
ef3386f0 FR |
2103 | } |
2104 | ||
4da19633 | 2105 | static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp) |
867763c1 | 2106 | { |
350f7596 | 2107 | static const struct phy_reg phy_reg_init[] = { |
a3f80671 FR |
2108 | { 0x1f, 0x0001 }, |
2109 | { 0x12, 0x2300 }, | |
867763c1 FR |
2110 | { 0x1f, 0x0002 }, |
2111 | { 0x00, 0x88d4 }, | |
2112 | { 0x01, 0x82b1 }, | |
2113 | { 0x03, 0x7002 }, | |
2114 | { 0x08, 0x9e30 }, | |
2115 | { 0x09, 0x01f0 }, | |
2116 | { 0x0a, 0x5500 }, | |
2117 | { 0x0c, 0x00c8 }, | |
2118 | { 0x1f, 0x0003 }, | |
2119 | { 0x12, 0xc096 }, | |
2120 | { 0x16, 0x000a }, | |
f50d4275 FR |
2121 | { 0x1f, 0x0000 }, |
2122 | { 0x1f, 0x0000 }, | |
2123 | { 0x09, 0x2000 }, | |
2124 | { 0x09, 0x0000 } | |
867763c1 FR |
2125 | }; |
2126 | ||
4da19633 | 2127 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2128 | |
4da19633 | 2129 | rtl_patchphy(tp, 0x14, 1 << 5); |
2130 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2131 | rtl_writephy(tp, 0x1f, 0x0000); | |
867763c1 FR |
2132 | } |
2133 | ||
4da19633 | 2134 | static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp) |
7da97ec9 | 2135 | { |
350f7596 | 2136 | static const struct phy_reg phy_reg_init[] = { |
f50d4275 | 2137 | { 0x1f, 0x0001 }, |
7da97ec9 | 2138 | { 0x12, 0x2300 }, |
f50d4275 FR |
2139 | { 0x03, 0x802f }, |
2140 | { 0x02, 0x4f02 }, | |
2141 | { 0x01, 0x0409 }, | |
2142 | { 0x00, 0xf099 }, | |
2143 | { 0x04, 0x9800 }, | |
2144 | { 0x04, 0x9000 }, | |
2145 | { 0x1d, 0x3d98 }, | |
7da97ec9 FR |
2146 | { 0x1f, 0x0002 }, |
2147 | { 0x0c, 0x7eb8 }, | |
f50d4275 FR |
2148 | { 0x06, 0x0761 }, |
2149 | { 0x1f, 0x0003 }, | |
2150 | { 0x16, 0x0f0a }, | |
7da97ec9 FR |
2151 | { 0x1f, 0x0000 } |
2152 | }; | |
2153 | ||
4da19633 | 2154 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
f50d4275 | 2155 | |
4da19633 | 2156 | rtl_patchphy(tp, 0x16, 1 << 0); |
2157 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2158 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2159 | rtl_writephy(tp, 0x1f, 0x0000); | |
7da97ec9 FR |
2160 | } |
2161 | ||
4da19633 | 2162 | static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp) |
197ff761 | 2163 | { |
350f7596 | 2164 | static const struct phy_reg phy_reg_init[] = { |
197ff761 FR |
2165 | { 0x1f, 0x0001 }, |
2166 | { 0x12, 0x2300 }, | |
2167 | { 0x1d, 0x3d98 }, | |
2168 | { 0x1f, 0x0002 }, | |
2169 | { 0x0c, 0x7eb8 }, | |
2170 | { 0x06, 0x5461 }, | |
2171 | { 0x1f, 0x0003 }, | |
2172 | { 0x16, 0x0f0a }, | |
2173 | { 0x1f, 0x0000 } | |
2174 | }; | |
2175 | ||
4da19633 | 2176 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
197ff761 | 2177 | |
4da19633 | 2178 | rtl_patchphy(tp, 0x16, 1 << 0); |
2179 | rtl_patchphy(tp, 0x14, 1 << 5); | |
2180 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2181 | rtl_writephy(tp, 0x1f, 0x0000); | |
197ff761 FR |
2182 | } |
2183 | ||
4da19633 | 2184 | static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp) |
6fb07058 | 2185 | { |
4da19633 | 2186 | rtl8168c_3_hw_phy_config(tp); |
6fb07058 FR |
2187 | } |
2188 | ||
bca03d5f | 2189 | static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp) |
5b538df9 | 2190 | { |
350f7596 | 2191 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 2192 | /* Channel Estimation */ |
5b538df9 | 2193 | { 0x1f, 0x0001 }, |
daf9df6d | 2194 | { 0x06, 0x4064 }, |
2195 | { 0x07, 0x2863 }, | |
2196 | { 0x08, 0x059c }, | |
2197 | { 0x09, 0x26b4 }, | |
2198 | { 0x0a, 0x6a19 }, | |
2199 | { 0x0b, 0xdcc8 }, | |
2200 | { 0x10, 0xf06d }, | |
2201 | { 0x14, 0x7f68 }, | |
2202 | { 0x18, 0x7fd9 }, | |
2203 | { 0x1c, 0xf0ff }, | |
2204 | { 0x1d, 0x3d9c }, | |
5b538df9 | 2205 | { 0x1f, 0x0003 }, |
daf9df6d | 2206 | { 0x12, 0xf49f }, |
2207 | { 0x13, 0x070b }, | |
2208 | { 0x1a, 0x05ad }, | |
bca03d5f | 2209 | { 0x14, 0x94c0 }, |
2210 | ||
2211 | /* | |
2212 | * Tx Error Issue | |
2213 | * enhance line driver power | |
2214 | */ | |
5b538df9 | 2215 | { 0x1f, 0x0002 }, |
daf9df6d | 2216 | { 0x06, 0x5561 }, |
2217 | { 0x1f, 0x0005 }, | |
2218 | { 0x05, 0x8332 }, | |
bca03d5f | 2219 | { 0x06, 0x5561 }, |
2220 | ||
2221 | /* | |
2222 | * Can not link to 1Gbps with bad cable | |
2223 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
2224 | */ | |
2225 | { 0x1f, 0x0001 }, | |
2226 | { 0x17, 0x0cc0 }, | |
daf9df6d | 2227 | |
5b538df9 | 2228 | { 0x1f, 0x0000 }, |
bca03d5f | 2229 | { 0x0d, 0xf880 } |
daf9df6d | 2230 | }; |
bca03d5f | 2231 | void __iomem *ioaddr = tp->mmio_addr; |
daf9df6d | 2232 | |
4da19633 | 2233 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
daf9df6d | 2234 | |
bca03d5f | 2235 | /* |
2236 | * Rx Error Issue | |
2237 | * Fine Tune Switching regulator parameter | |
2238 | */ | |
4da19633 | 2239 | rtl_writephy(tp, 0x1f, 0x0002); |
2240 | rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef); | |
2241 | rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00); | |
daf9df6d | 2242 | |
daf9df6d | 2243 | if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
350f7596 | 2244 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2245 | { 0x1f, 0x0002 }, |
2246 | { 0x05, 0x669a }, | |
2247 | { 0x1f, 0x0005 }, | |
2248 | { 0x05, 0x8330 }, | |
2249 | { 0x06, 0x669a }, | |
2250 | { 0x1f, 0x0002 } | |
2251 | }; | |
2252 | int val; | |
2253 | ||
4da19633 | 2254 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2255 | |
4da19633 | 2256 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 2257 | |
2258 | if ((val & 0x00ff) != 0x006c) { | |
350f7596 | 2259 | static const u32 set[] = { |
daf9df6d | 2260 | 0x0065, 0x0066, 0x0067, 0x0068, |
2261 | 0x0069, 0x006a, 0x006b, 0x006c | |
2262 | }; | |
2263 | int i; | |
2264 | ||
4da19633 | 2265 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 2266 | |
2267 | val &= 0xff00; | |
2268 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 2269 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 2270 | } |
2271 | } else { | |
350f7596 | 2272 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2273 | { 0x1f, 0x0002 }, |
2274 | { 0x05, 0x6662 }, | |
2275 | { 0x1f, 0x0005 }, | |
2276 | { 0x05, 0x8330 }, | |
2277 | { 0x06, 0x6662 } | |
2278 | }; | |
2279 | ||
4da19633 | 2280 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2281 | } |
2282 | ||
bca03d5f | 2283 | /* RSET couple improve */ |
4da19633 | 2284 | rtl_writephy(tp, 0x1f, 0x0002); |
2285 | rtl_patchphy(tp, 0x0d, 0x0300); | |
2286 | rtl_patchphy(tp, 0x0f, 0x0010); | |
daf9df6d | 2287 | |
bca03d5f | 2288 | /* Fine tune PLL performance */ |
4da19633 | 2289 | rtl_writephy(tp, 0x1f, 0x0002); |
2290 | rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); | |
2291 | rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 2292 | |
4da19633 | 2293 | rtl_writephy(tp, 0x1f, 0x0005); |
2294 | rtl_writephy(tp, 0x05, 0x001b); | |
f1e02ed1 | 2295 | if ((rtl_readphy(tp, 0x06) != 0xbf00) || |
2296 | (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) { | |
bca03d5f | 2297 | netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n"); |
2298 | } | |
2299 | ||
4da19633 | 2300 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 2301 | } |
2302 | ||
bca03d5f | 2303 | static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 2304 | { |
350f7596 | 2305 | static const struct phy_reg phy_reg_init_0[] = { |
bca03d5f | 2306 | /* Channel Estimation */ |
daf9df6d | 2307 | { 0x1f, 0x0001 }, |
2308 | { 0x06, 0x4064 }, | |
2309 | { 0x07, 0x2863 }, | |
2310 | { 0x08, 0x059c }, | |
2311 | { 0x09, 0x26b4 }, | |
2312 | { 0x0a, 0x6a19 }, | |
2313 | { 0x0b, 0xdcc8 }, | |
2314 | { 0x10, 0xf06d }, | |
2315 | { 0x14, 0x7f68 }, | |
2316 | { 0x18, 0x7fd9 }, | |
2317 | { 0x1c, 0xf0ff }, | |
2318 | { 0x1d, 0x3d9c }, | |
2319 | { 0x1f, 0x0003 }, | |
2320 | { 0x12, 0xf49f }, | |
2321 | { 0x13, 0x070b }, | |
2322 | { 0x1a, 0x05ad }, | |
2323 | { 0x14, 0x94c0 }, | |
2324 | ||
bca03d5f | 2325 | /* |
2326 | * Tx Error Issue | |
2327 | * enhance line driver power | |
2328 | */ | |
daf9df6d | 2329 | { 0x1f, 0x0002 }, |
2330 | { 0x06, 0x5561 }, | |
2331 | { 0x1f, 0x0005 }, | |
2332 | { 0x05, 0x8332 }, | |
bca03d5f | 2333 | { 0x06, 0x5561 }, |
2334 | ||
2335 | /* | |
2336 | * Can not link to 1Gbps with bad cable | |
2337 | * Decrease SNR threshold form 21.07dB to 19.04dB | |
2338 | */ | |
2339 | { 0x1f, 0x0001 }, | |
2340 | { 0x17, 0x0cc0 }, | |
daf9df6d | 2341 | |
2342 | { 0x1f, 0x0000 }, | |
bca03d5f | 2343 | { 0x0d, 0xf880 } |
5b538df9 | 2344 | }; |
bca03d5f | 2345 | void __iomem *ioaddr = tp->mmio_addr; |
5b538df9 | 2346 | |
4da19633 | 2347 | rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); |
5b538df9 | 2348 | |
daf9df6d | 2349 | if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) { |
350f7596 | 2350 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2351 | { 0x1f, 0x0002 }, |
2352 | { 0x05, 0x669a }, | |
5b538df9 | 2353 | { 0x1f, 0x0005 }, |
daf9df6d | 2354 | { 0x05, 0x8330 }, |
2355 | { 0x06, 0x669a }, | |
2356 | ||
2357 | { 0x1f, 0x0002 } | |
2358 | }; | |
2359 | int val; | |
2360 | ||
4da19633 | 2361 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
daf9df6d | 2362 | |
4da19633 | 2363 | val = rtl_readphy(tp, 0x0d); |
daf9df6d | 2364 | if ((val & 0x00ff) != 0x006c) { |
b6bc7650 | 2365 | static const u32 set[] = { |
daf9df6d | 2366 | 0x0065, 0x0066, 0x0067, 0x0068, |
2367 | 0x0069, 0x006a, 0x006b, 0x006c | |
2368 | }; | |
2369 | int i; | |
2370 | ||
4da19633 | 2371 | rtl_writephy(tp, 0x1f, 0x0002); |
daf9df6d | 2372 | |
2373 | val &= 0xff00; | |
2374 | for (i = 0; i < ARRAY_SIZE(set); i++) | |
4da19633 | 2375 | rtl_writephy(tp, 0x0d, val | set[i]); |
daf9df6d | 2376 | } |
2377 | } else { | |
350f7596 | 2378 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2379 | { 0x1f, 0x0002 }, |
2380 | { 0x05, 0x2642 }, | |
5b538df9 | 2381 | { 0x1f, 0x0005 }, |
daf9df6d | 2382 | { 0x05, 0x8330 }, |
2383 | { 0x06, 0x2642 } | |
5b538df9 FR |
2384 | }; |
2385 | ||
4da19633 | 2386 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
2387 | } |
2388 | ||
bca03d5f | 2389 | /* Fine tune PLL performance */ |
4da19633 | 2390 | rtl_writephy(tp, 0x1f, 0x0002); |
2391 | rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600); | |
2392 | rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000); | |
daf9df6d | 2393 | |
bca03d5f | 2394 | /* Switching regulator Slew rate */ |
4da19633 | 2395 | rtl_writephy(tp, 0x1f, 0x0002); |
2396 | rtl_patchphy(tp, 0x0f, 0x0017); | |
daf9df6d | 2397 | |
4da19633 | 2398 | rtl_writephy(tp, 0x1f, 0x0005); |
2399 | rtl_writephy(tp, 0x05, 0x001b); | |
f1e02ed1 | 2400 | if ((rtl_readphy(tp, 0x06) != 0xb300) || |
2401 | (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) { | |
bca03d5f | 2402 | netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n"); |
2403 | } | |
2404 | ||
4da19633 | 2405 | rtl_writephy(tp, 0x1f, 0x0000); |
daf9df6d | 2406 | } |
2407 | ||
4da19633 | 2408 | static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp) |
daf9df6d | 2409 | { |
350f7596 | 2410 | static const struct phy_reg phy_reg_init[] = { |
daf9df6d | 2411 | { 0x1f, 0x0002 }, |
2412 | { 0x10, 0x0008 }, | |
2413 | { 0x0d, 0x006c }, | |
2414 | ||
2415 | { 0x1f, 0x0000 }, | |
2416 | { 0x0d, 0xf880 }, | |
2417 | ||
2418 | { 0x1f, 0x0001 }, | |
2419 | { 0x17, 0x0cc0 }, | |
2420 | ||
2421 | { 0x1f, 0x0001 }, | |
2422 | { 0x0b, 0xa4d8 }, | |
2423 | { 0x09, 0x281c }, | |
2424 | { 0x07, 0x2883 }, | |
2425 | { 0x0a, 0x6b35 }, | |
2426 | { 0x1d, 0x3da4 }, | |
2427 | { 0x1c, 0xeffd }, | |
2428 | { 0x14, 0x7f52 }, | |
2429 | { 0x18, 0x7fc6 }, | |
2430 | { 0x08, 0x0601 }, | |
2431 | { 0x06, 0x4063 }, | |
2432 | { 0x10, 0xf074 }, | |
2433 | { 0x1f, 0x0003 }, | |
2434 | { 0x13, 0x0789 }, | |
2435 | { 0x12, 0xf4bd }, | |
2436 | { 0x1a, 0x04fd }, | |
2437 | { 0x14, 0x84b0 }, | |
2438 | { 0x1f, 0x0000 }, | |
2439 | { 0x00, 0x9200 }, | |
2440 | ||
2441 | { 0x1f, 0x0005 }, | |
2442 | { 0x01, 0x0340 }, | |
2443 | { 0x1f, 0x0001 }, | |
2444 | { 0x04, 0x4000 }, | |
2445 | { 0x03, 0x1d21 }, | |
2446 | { 0x02, 0x0c32 }, | |
2447 | { 0x01, 0x0200 }, | |
2448 | { 0x00, 0x5554 }, | |
2449 | { 0x04, 0x4800 }, | |
2450 | { 0x04, 0x4000 }, | |
2451 | { 0x04, 0xf000 }, | |
2452 | { 0x03, 0xdf01 }, | |
2453 | { 0x02, 0xdf20 }, | |
2454 | { 0x01, 0x101a }, | |
2455 | { 0x00, 0xa0ff }, | |
2456 | { 0x04, 0xf800 }, | |
2457 | { 0x04, 0xf000 }, | |
2458 | { 0x1f, 0x0000 }, | |
2459 | ||
2460 | { 0x1f, 0x0007 }, | |
2461 | { 0x1e, 0x0023 }, | |
2462 | { 0x16, 0x0000 }, | |
2463 | { 0x1f, 0x0000 } | |
2464 | }; | |
2465 | ||
4da19633 | 2466 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
5b538df9 FR |
2467 | } |
2468 | ||
e6de30d6 | 2469 | static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp) |
2470 | { | |
2471 | static const struct phy_reg phy_reg_init[] = { | |
2472 | { 0x1f, 0x0001 }, | |
2473 | { 0x17, 0x0cc0 }, | |
2474 | ||
2475 | { 0x1f, 0x0007 }, | |
2476 | { 0x1e, 0x002d }, | |
2477 | { 0x18, 0x0040 }, | |
2478 | { 0x1f, 0x0000 } | |
2479 | }; | |
2480 | ||
2481 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
2482 | rtl_patchphy(tp, 0x0d, 1 << 5); | |
2483 | } | |
2484 | ||
01dc7fec | 2485 | static void rtl8168e_hw_phy_config(struct rtl8169_private *tp) |
2486 | { | |
2487 | static const struct phy_reg phy_reg_init[] = { | |
2488 | /* Enable Delay cap */ | |
2489 | { 0x1f, 0x0005 }, | |
2490 | { 0x05, 0x8b80 }, | |
2491 | { 0x06, 0xc896 }, | |
2492 | { 0x1f, 0x0000 }, | |
2493 | ||
2494 | /* Channel estimation fine tune */ | |
2495 | { 0x1f, 0x0001 }, | |
2496 | { 0x0b, 0x6c20 }, | |
2497 | { 0x07, 0x2872 }, | |
2498 | { 0x1c, 0xefff }, | |
2499 | { 0x1f, 0x0003 }, | |
2500 | { 0x14, 0x6420 }, | |
2501 | { 0x1f, 0x0000 }, | |
2502 | ||
2503 | /* Update PFM & 10M TX idle timer */ | |
2504 | { 0x1f, 0x0007 }, | |
2505 | { 0x1e, 0x002f }, | |
2506 | { 0x15, 0x1919 }, | |
2507 | { 0x1f, 0x0000 }, | |
2508 | ||
2509 | { 0x1f, 0x0007 }, | |
2510 | { 0x1e, 0x00ac }, | |
2511 | { 0x18, 0x0006 }, | |
2512 | { 0x1f, 0x0000 } | |
2513 | }; | |
2514 | ||
2515 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
2516 | ||
2517 | /* DCO enable for 10M IDLE Power */ | |
2518 | rtl_writephy(tp, 0x1f, 0x0007); | |
2519 | rtl_writephy(tp, 0x1e, 0x0023); | |
2520 | rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000); | |
2521 | rtl_writephy(tp, 0x1f, 0x0000); | |
2522 | ||
2523 | /* For impedance matching */ | |
2524 | rtl_writephy(tp, 0x1f, 0x0002); | |
2525 | rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00); | |
2526 | rtl_writephy(tp, 0x1F, 0x0000); | |
2527 | ||
2528 | /* PHY auto speed down */ | |
2529 | rtl_writephy(tp, 0x1f, 0x0007); | |
2530 | rtl_writephy(tp, 0x1e, 0x002d); | |
2531 | rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000); | |
2532 | rtl_writephy(tp, 0x1f, 0x0000); | |
2533 | rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000); | |
2534 | ||
2535 | rtl_writephy(tp, 0x1f, 0x0005); | |
2536 | rtl_writephy(tp, 0x05, 0x8b86); | |
2537 | rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000); | |
2538 | rtl_writephy(tp, 0x1f, 0x0000); | |
2539 | ||
2540 | rtl_writephy(tp, 0x1f, 0x0005); | |
2541 | rtl_writephy(tp, 0x05, 0x8b85); | |
2542 | rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000); | |
2543 | rtl_writephy(tp, 0x1f, 0x0007); | |
2544 | rtl_writephy(tp, 0x1e, 0x0020); | |
2545 | rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100); | |
2546 | rtl_writephy(tp, 0x1f, 0x0006); | |
2547 | rtl_writephy(tp, 0x00, 0x5a00); | |
2548 | rtl_writephy(tp, 0x1f, 0x0000); | |
2549 | rtl_writephy(tp, 0x0d, 0x0007); | |
2550 | rtl_writephy(tp, 0x0e, 0x003c); | |
2551 | rtl_writephy(tp, 0x0d, 0x4007); | |
2552 | rtl_writephy(tp, 0x0e, 0x0000); | |
2553 | rtl_writephy(tp, 0x0d, 0x0000); | |
2554 | } | |
2555 | ||
2556 | static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp) | |
2557 | { | |
2558 | if (rtl_apply_firmware(tp, FIRMWARE_8168E_1) < 0) | |
2559 | netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n"); | |
2560 | ||
2561 | rtl8168e_hw_phy_config(tp); | |
2562 | } | |
2563 | ||
2564 | static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp) | |
2565 | { | |
2566 | if (rtl_apply_firmware(tp, FIRMWARE_8168E_2) < 0) | |
2567 | netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n"); | |
2568 | ||
2569 | rtl8168e_hw_phy_config(tp); | |
2570 | } | |
2571 | ||
4da19633 | 2572 | static void rtl8102e_hw_phy_config(struct rtl8169_private *tp) |
2857ffb7 | 2573 | { |
350f7596 | 2574 | static const struct phy_reg phy_reg_init[] = { |
2857ffb7 FR |
2575 | { 0x1f, 0x0003 }, |
2576 | { 0x08, 0x441d }, | |
2577 | { 0x01, 0x9100 }, | |
2578 | { 0x1f, 0x0000 } | |
2579 | }; | |
2580 | ||
4da19633 | 2581 | rtl_writephy(tp, 0x1f, 0x0000); |
2582 | rtl_patchphy(tp, 0x11, 1 << 12); | |
2583 | rtl_patchphy(tp, 0x19, 1 << 13); | |
2584 | rtl_patchphy(tp, 0x10, 1 << 15); | |
2857ffb7 | 2585 | |
4da19633 | 2586 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); |
2857ffb7 FR |
2587 | } |
2588 | ||
5a5e4443 HW |
2589 | static void rtl8105e_hw_phy_config(struct rtl8169_private *tp) |
2590 | { | |
2591 | static const struct phy_reg phy_reg_init[] = { | |
2592 | { 0x1f, 0x0005 }, | |
2593 | { 0x1a, 0x0000 }, | |
2594 | { 0x1f, 0x0000 }, | |
2595 | ||
2596 | { 0x1f, 0x0004 }, | |
2597 | { 0x1c, 0x0000 }, | |
2598 | { 0x1f, 0x0000 }, | |
2599 | ||
2600 | { 0x1f, 0x0001 }, | |
2601 | { 0x15, 0x7701 }, | |
2602 | { 0x1f, 0x0000 } | |
2603 | }; | |
2604 | ||
2605 | /* Disable ALDPS before ram code */ | |
2606 | rtl_writephy(tp, 0x1f, 0x0000); | |
2607 | rtl_writephy(tp, 0x18, 0x0310); | |
2608 | msleep(100); | |
2609 | ||
2610 | if (rtl_apply_firmware(tp, FIRMWARE_8105E_1) < 0) | |
2611 | netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n"); | |
2612 | ||
2613 | rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
2614 | } | |
2615 | ||
5615d9f1 FR |
2616 | static void rtl_hw_phy_config(struct net_device *dev) |
2617 | { | |
2618 | struct rtl8169_private *tp = netdev_priv(dev); | |
5615d9f1 FR |
2619 | |
2620 | rtl8169_print_mac_version(tp); | |
2621 | ||
2622 | switch (tp->mac_version) { | |
2623 | case RTL_GIGA_MAC_VER_01: | |
2624 | break; | |
2625 | case RTL_GIGA_MAC_VER_02: | |
2626 | case RTL_GIGA_MAC_VER_03: | |
4da19633 | 2627 | rtl8169s_hw_phy_config(tp); |
5615d9f1 FR |
2628 | break; |
2629 | case RTL_GIGA_MAC_VER_04: | |
4da19633 | 2630 | rtl8169sb_hw_phy_config(tp); |
5615d9f1 | 2631 | break; |
2e955856 | 2632 | case RTL_GIGA_MAC_VER_05: |
4da19633 | 2633 | rtl8169scd_hw_phy_config(tp); |
2e955856 | 2634 | break; |
8c7006aa | 2635 | case RTL_GIGA_MAC_VER_06: |
4da19633 | 2636 | rtl8169sce_hw_phy_config(tp); |
8c7006aa | 2637 | break; |
2857ffb7 FR |
2638 | case RTL_GIGA_MAC_VER_07: |
2639 | case RTL_GIGA_MAC_VER_08: | |
2640 | case RTL_GIGA_MAC_VER_09: | |
4da19633 | 2641 | rtl8102e_hw_phy_config(tp); |
2857ffb7 | 2642 | break; |
236b8082 | 2643 | case RTL_GIGA_MAC_VER_11: |
4da19633 | 2644 | rtl8168bb_hw_phy_config(tp); |
236b8082 FR |
2645 | break; |
2646 | case RTL_GIGA_MAC_VER_12: | |
4da19633 | 2647 | rtl8168bef_hw_phy_config(tp); |
236b8082 FR |
2648 | break; |
2649 | case RTL_GIGA_MAC_VER_17: | |
4da19633 | 2650 | rtl8168bef_hw_phy_config(tp); |
236b8082 | 2651 | break; |
867763c1 | 2652 | case RTL_GIGA_MAC_VER_18: |
4da19633 | 2653 | rtl8168cp_1_hw_phy_config(tp); |
867763c1 FR |
2654 | break; |
2655 | case RTL_GIGA_MAC_VER_19: | |
4da19633 | 2656 | rtl8168c_1_hw_phy_config(tp); |
867763c1 | 2657 | break; |
7da97ec9 | 2658 | case RTL_GIGA_MAC_VER_20: |
4da19633 | 2659 | rtl8168c_2_hw_phy_config(tp); |
7da97ec9 | 2660 | break; |
197ff761 | 2661 | case RTL_GIGA_MAC_VER_21: |
4da19633 | 2662 | rtl8168c_3_hw_phy_config(tp); |
197ff761 | 2663 | break; |
6fb07058 | 2664 | case RTL_GIGA_MAC_VER_22: |
4da19633 | 2665 | rtl8168c_4_hw_phy_config(tp); |
6fb07058 | 2666 | break; |
ef3386f0 | 2667 | case RTL_GIGA_MAC_VER_23: |
7f3e3d3a | 2668 | case RTL_GIGA_MAC_VER_24: |
4da19633 | 2669 | rtl8168cp_2_hw_phy_config(tp); |
ef3386f0 | 2670 | break; |
5b538df9 | 2671 | case RTL_GIGA_MAC_VER_25: |
bca03d5f | 2672 | rtl8168d_1_hw_phy_config(tp); |
daf9df6d | 2673 | break; |
2674 | case RTL_GIGA_MAC_VER_26: | |
bca03d5f | 2675 | rtl8168d_2_hw_phy_config(tp); |
daf9df6d | 2676 | break; |
2677 | case RTL_GIGA_MAC_VER_27: | |
4da19633 | 2678 | rtl8168d_3_hw_phy_config(tp); |
5b538df9 | 2679 | break; |
e6de30d6 | 2680 | case RTL_GIGA_MAC_VER_28: |
2681 | rtl8168d_4_hw_phy_config(tp); | |
2682 | break; | |
5a5e4443 HW |
2683 | case RTL_GIGA_MAC_VER_29: |
2684 | case RTL_GIGA_MAC_VER_30: | |
2685 | rtl8105e_hw_phy_config(tp); | |
2686 | break; | |
01dc7fec | 2687 | case RTL_GIGA_MAC_VER_32: |
2688 | rtl8168e_1_hw_phy_config(tp); | |
2689 | break; | |
2690 | case RTL_GIGA_MAC_VER_33: | |
2691 | rtl8168e_2_hw_phy_config(tp); | |
2692 | break; | |
ef3386f0 | 2693 | |
5615d9f1 FR |
2694 | default: |
2695 | break; | |
2696 | } | |
2697 | } | |
2698 | ||
1da177e4 LT |
2699 | static void rtl8169_phy_timer(unsigned long __opaque) |
2700 | { | |
2701 | struct net_device *dev = (struct net_device *)__opaque; | |
2702 | struct rtl8169_private *tp = netdev_priv(dev); | |
2703 | struct timer_list *timer = &tp->timer; | |
2704 | void __iomem *ioaddr = tp->mmio_addr; | |
2705 | unsigned long timeout = RTL8169_PHY_TIMEOUT; | |
2706 | ||
bcf0bf90 | 2707 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 2708 | |
64e4bfb4 | 2709 | if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
1da177e4 LT |
2710 | return; |
2711 | ||
2712 | spin_lock_irq(&tp->lock); | |
2713 | ||
4da19633 | 2714 | if (tp->phy_reset_pending(tp)) { |
5b0384f4 | 2715 | /* |
1da177e4 LT |
2716 | * A busy loop could burn quite a few cycles on nowadays CPU. |
2717 | * Let's delay the execution of the timer for a few ticks. | |
2718 | */ | |
2719 | timeout = HZ/10; | |
2720 | goto out_mod_timer; | |
2721 | } | |
2722 | ||
2723 | if (tp->link_ok(ioaddr)) | |
2724 | goto out_unlock; | |
2725 | ||
bf82c189 | 2726 | netif_warn(tp, link, dev, "PHY reset until link up\n"); |
1da177e4 | 2727 | |
4da19633 | 2728 | tp->phy_reset_enable(tp); |
1da177e4 LT |
2729 | |
2730 | out_mod_timer: | |
2731 | mod_timer(timer, jiffies + timeout); | |
2732 | out_unlock: | |
2733 | spin_unlock_irq(&tp->lock); | |
2734 | } | |
2735 | ||
2736 | static inline void rtl8169_delete_timer(struct net_device *dev) | |
2737 | { | |
2738 | struct rtl8169_private *tp = netdev_priv(dev); | |
2739 | struct timer_list *timer = &tp->timer; | |
2740 | ||
e179bb7b | 2741 | if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
1da177e4 LT |
2742 | return; |
2743 | ||
2744 | del_timer_sync(timer); | |
2745 | } | |
2746 | ||
2747 | static inline void rtl8169_request_timer(struct net_device *dev) | |
2748 | { | |
2749 | struct rtl8169_private *tp = netdev_priv(dev); | |
2750 | struct timer_list *timer = &tp->timer; | |
2751 | ||
e179bb7b | 2752 | if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
1da177e4 LT |
2753 | return; |
2754 | ||
2efa53f3 | 2755 | mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); |
1da177e4 LT |
2756 | } |
2757 | ||
2758 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2759 | /* | |
2760 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
2761 | * without having to re-enable interrupts. It's not called while | |
2762 | * the interrupt routine is executing. | |
2763 | */ | |
2764 | static void rtl8169_netpoll(struct net_device *dev) | |
2765 | { | |
2766 | struct rtl8169_private *tp = netdev_priv(dev); | |
2767 | struct pci_dev *pdev = tp->pci_dev; | |
2768 | ||
2769 | disable_irq(pdev->irq); | |
7d12e780 | 2770 | rtl8169_interrupt(pdev->irq, dev); |
1da177e4 LT |
2771 | enable_irq(pdev->irq); |
2772 | } | |
2773 | #endif | |
2774 | ||
2775 | static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, | |
2776 | void __iomem *ioaddr) | |
2777 | { | |
2778 | iounmap(ioaddr); | |
2779 | pci_release_regions(pdev); | |
87aeec76 | 2780 | pci_clear_mwi(pdev); |
1da177e4 LT |
2781 | pci_disable_device(pdev); |
2782 | free_netdev(dev); | |
2783 | } | |
2784 | ||
bf793295 FR |
2785 | static void rtl8169_phy_reset(struct net_device *dev, |
2786 | struct rtl8169_private *tp) | |
2787 | { | |
07d3f51f | 2788 | unsigned int i; |
bf793295 | 2789 | |
4da19633 | 2790 | tp->phy_reset_enable(tp); |
bf793295 | 2791 | for (i = 0; i < 100; i++) { |
4da19633 | 2792 | if (!tp->phy_reset_pending(tp)) |
bf793295 FR |
2793 | return; |
2794 | msleep(1); | |
2795 | } | |
bf82c189 | 2796 | netif_err(tp, link, dev, "PHY reset failed\n"); |
bf793295 FR |
2797 | } |
2798 | ||
4ff96fa6 FR |
2799 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
2800 | { | |
2801 | void __iomem *ioaddr = tp->mmio_addr; | |
4ff96fa6 | 2802 | |
5615d9f1 | 2803 | rtl_hw_phy_config(dev); |
4ff96fa6 | 2804 | |
77332894 MS |
2805 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
2806 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
2807 | RTL_W8(0x82, 0x01); | |
2808 | } | |
4ff96fa6 | 2809 | |
6dccd16b FR |
2810 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
2811 | ||
2812 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
2813 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 2814 | |
bcf0bf90 | 2815 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 FR |
2816 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
2817 | RTL_W8(0x82, 0x01); | |
2818 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); | |
4da19633 | 2819 | rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0 |
4ff96fa6 FR |
2820 | } |
2821 | ||
bf793295 FR |
2822 | rtl8169_phy_reset(dev, tp); |
2823 | ||
54405cde ON |
2824 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL, |
2825 | ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full | | |
2826 | ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full | | |
db552b33 | 2827 | (tp->mii.supports_gmii ? |
54405cde | 2828 | ADVERTISED_1000baseT_Half | |
db552b33 | 2829 | ADVERTISED_1000baseT_Full : 0)); |
4ff96fa6 | 2830 | |
bf82c189 JP |
2831 | if (RTL_R8(PHYstatus) & TBI_Enable) |
2832 | netif_info(tp, link, dev, "TBI auto-negotiating\n"); | |
4ff96fa6 FR |
2833 | } |
2834 | ||
773d2021 FR |
2835 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
2836 | { | |
2837 | void __iomem *ioaddr = tp->mmio_addr; | |
2838 | u32 high; | |
2839 | u32 low; | |
2840 | ||
2841 | low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); | |
2842 | high = addr[4] | (addr[5] << 8); | |
2843 | ||
2844 | spin_lock_irq(&tp->lock); | |
2845 | ||
2846 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
908ba2bf | 2847 | |
773d2021 | 2848 | RTL_W32(MAC4, high); |
908ba2bf | 2849 | RTL_R32(MAC4); |
2850 | ||
78f1cd02 | 2851 | RTL_W32(MAC0, low); |
908ba2bf | 2852 | RTL_R32(MAC0); |
2853 | ||
773d2021 FR |
2854 | RTL_W8(Cfg9346, Cfg9346_Lock); |
2855 | ||
2856 | spin_unlock_irq(&tp->lock); | |
2857 | } | |
2858 | ||
2859 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
2860 | { | |
2861 | struct rtl8169_private *tp = netdev_priv(dev); | |
2862 | struct sockaddr *addr = p; | |
2863 | ||
2864 | if (!is_valid_ether_addr(addr->sa_data)) | |
2865 | return -EADDRNOTAVAIL; | |
2866 | ||
2867 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
2868 | ||
2869 | rtl_rar_set(tp, dev->dev_addr); | |
2870 | ||
2871 | return 0; | |
2872 | } | |
2873 | ||
5f787a1a FR |
2874 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
2875 | { | |
2876 | struct rtl8169_private *tp = netdev_priv(dev); | |
2877 | struct mii_ioctl_data *data = if_mii(ifr); | |
2878 | ||
8b4ab28d FR |
2879 | return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV; |
2880 | } | |
5f787a1a | 2881 | |
8b4ab28d FR |
2882 | static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
2883 | { | |
5f787a1a FR |
2884 | switch (cmd) { |
2885 | case SIOCGMIIPHY: | |
2886 | data->phy_id = 32; /* Internal PHY */ | |
2887 | return 0; | |
2888 | ||
2889 | case SIOCGMIIREG: | |
4da19633 | 2890 | data->val_out = rtl_readphy(tp, data->reg_num & 0x1f); |
5f787a1a FR |
2891 | return 0; |
2892 | ||
2893 | case SIOCSMIIREG: | |
4da19633 | 2894 | rtl_writephy(tp, data->reg_num & 0x1f, data->val_in); |
5f787a1a FR |
2895 | return 0; |
2896 | } | |
2897 | return -EOPNOTSUPP; | |
2898 | } | |
2899 | ||
8b4ab28d FR |
2900 | static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd) |
2901 | { | |
2902 | return -EOPNOTSUPP; | |
2903 | } | |
2904 | ||
0e485150 FR |
2905 | static const struct rtl_cfg_info { |
2906 | void (*hw_start)(struct net_device *); | |
2907 | unsigned int region; | |
2908 | unsigned int align; | |
2909 | u16 intr_event; | |
2910 | u16 napi_event; | |
ccdffb9a | 2911 | unsigned features; |
f21b75e9 | 2912 | u8 default_ver; |
0e485150 FR |
2913 | } rtl_cfg_infos [] = { |
2914 | [RTL_CFG_0] = { | |
2915 | .hw_start = rtl_hw_start_8169, | |
2916 | .region = 1, | |
e9f63f30 | 2917 | .align = 0, |
0e485150 FR |
2918 | .intr_event = SYSErr | LinkChg | RxOverflow | |
2919 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 2920 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
2921 | .features = RTL_FEATURE_GMII, |
2922 | .default_ver = RTL_GIGA_MAC_VER_01, | |
0e485150 FR |
2923 | }, |
2924 | [RTL_CFG_1] = { | |
2925 | .hw_start = rtl_hw_start_8168, | |
2926 | .region = 2, | |
2927 | .align = 8, | |
53f57357 | 2928 | .intr_event = SYSErr | LinkChg | RxOverflow | |
0e485150 | 2929 | TxErr | TxOK | RxOK | RxErr, |
fbac58fc | 2930 | .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
2931 | .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI, |
2932 | .default_ver = RTL_GIGA_MAC_VER_11, | |
0e485150 FR |
2933 | }, |
2934 | [RTL_CFG_2] = { | |
2935 | .hw_start = rtl_hw_start_8101, | |
2936 | .region = 2, | |
2937 | .align = 8, | |
2938 | .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | | |
2939 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 2940 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
f21b75e9 JD |
2941 | .features = RTL_FEATURE_MSI, |
2942 | .default_ver = RTL_GIGA_MAC_VER_13, | |
0e485150 FR |
2943 | } |
2944 | }; | |
2945 | ||
fbac58fc FR |
2946 | /* Cfg9346_Unlock assumed. */ |
2947 | static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, | |
2948 | const struct rtl_cfg_info *cfg) | |
2949 | { | |
2950 | unsigned msi = 0; | |
2951 | u8 cfg2; | |
2952 | ||
2953 | cfg2 = RTL_R8(Config2) & ~MSIEnable; | |
ccdffb9a | 2954 | if (cfg->features & RTL_FEATURE_MSI) { |
fbac58fc FR |
2955 | if (pci_enable_msi(pdev)) { |
2956 | dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); | |
2957 | } else { | |
2958 | cfg2 |= MSIEnable; | |
2959 | msi = RTL_FEATURE_MSI; | |
2960 | } | |
2961 | } | |
2962 | RTL_W8(Config2, cfg2); | |
2963 | return msi; | |
2964 | } | |
2965 | ||
2966 | static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) | |
2967 | { | |
2968 | if (tp->features & RTL_FEATURE_MSI) { | |
2969 | pci_disable_msi(pdev); | |
2970 | tp->features &= ~RTL_FEATURE_MSI; | |
2971 | } | |
2972 | } | |
2973 | ||
8b4ab28d FR |
2974 | static const struct net_device_ops rtl8169_netdev_ops = { |
2975 | .ndo_open = rtl8169_open, | |
2976 | .ndo_stop = rtl8169_close, | |
2977 | .ndo_get_stats = rtl8169_get_stats, | |
00829823 | 2978 | .ndo_start_xmit = rtl8169_start_xmit, |
8b4ab28d FR |
2979 | .ndo_tx_timeout = rtl8169_tx_timeout, |
2980 | .ndo_validate_addr = eth_validate_addr, | |
2981 | .ndo_change_mtu = rtl8169_change_mtu, | |
2982 | .ndo_set_mac_address = rtl_set_mac_address, | |
2983 | .ndo_do_ioctl = rtl8169_ioctl, | |
2984 | .ndo_set_multicast_list = rtl_set_rx_mode, | |
8b4ab28d FR |
2985 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2986 | .ndo_poll_controller = rtl8169_netpoll, | |
2987 | #endif | |
2988 | ||
2989 | }; | |
2990 | ||
c0e45c1c | 2991 | static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp) |
2992 | { | |
2993 | struct mdio_ops *ops = &tp->mdio_ops; | |
2994 | ||
2995 | switch (tp->mac_version) { | |
2996 | case RTL_GIGA_MAC_VER_27: | |
2997 | ops->write = r8168dp_1_mdio_write; | |
2998 | ops->read = r8168dp_1_mdio_read; | |
2999 | break; | |
e6de30d6 | 3000 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 3001 | case RTL_GIGA_MAC_VER_31: |
e6de30d6 | 3002 | ops->write = r8168dp_2_mdio_write; |
3003 | ops->read = r8168dp_2_mdio_read; | |
3004 | break; | |
c0e45c1c | 3005 | default: |
3006 | ops->write = r8169_mdio_write; | |
3007 | ops->read = r8169_mdio_read; | |
3008 | break; | |
3009 | } | |
3010 | } | |
3011 | ||
065c27c1 | 3012 | static void r810x_phy_power_down(struct rtl8169_private *tp) |
3013 | { | |
3014 | rtl_writephy(tp, 0x1f, 0x0000); | |
3015 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
3016 | } | |
3017 | ||
3018 | static void r810x_phy_power_up(struct rtl8169_private *tp) | |
3019 | { | |
3020 | rtl_writephy(tp, 0x1f, 0x0000); | |
3021 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); | |
3022 | } | |
3023 | ||
3024 | static void r810x_pll_power_down(struct rtl8169_private *tp) | |
3025 | { | |
3026 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { | |
3027 | rtl_writephy(tp, 0x1f, 0x0000); | |
3028 | rtl_writephy(tp, MII_BMCR, 0x0000); | |
3029 | return; | |
3030 | } | |
3031 | ||
3032 | r810x_phy_power_down(tp); | |
3033 | } | |
3034 | ||
3035 | static void r810x_pll_power_up(struct rtl8169_private *tp) | |
3036 | { | |
3037 | r810x_phy_power_up(tp); | |
3038 | } | |
3039 | ||
3040 | static void r8168_phy_power_up(struct rtl8169_private *tp) | |
3041 | { | |
3042 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 3043 | switch (tp->mac_version) { |
3044 | case RTL_GIGA_MAC_VER_11: | |
3045 | case RTL_GIGA_MAC_VER_12: | |
3046 | case RTL_GIGA_MAC_VER_17: | |
3047 | case RTL_GIGA_MAC_VER_18: | |
3048 | case RTL_GIGA_MAC_VER_19: | |
3049 | case RTL_GIGA_MAC_VER_20: | |
3050 | case RTL_GIGA_MAC_VER_21: | |
3051 | case RTL_GIGA_MAC_VER_22: | |
3052 | case RTL_GIGA_MAC_VER_23: | |
3053 | case RTL_GIGA_MAC_VER_24: | |
3054 | case RTL_GIGA_MAC_VER_25: | |
3055 | case RTL_GIGA_MAC_VER_26: | |
3056 | case RTL_GIGA_MAC_VER_27: | |
3057 | case RTL_GIGA_MAC_VER_28: | |
3058 | case RTL_GIGA_MAC_VER_31: | |
3059 | rtl_writephy(tp, 0x0e, 0x0000); | |
3060 | break; | |
3061 | default: | |
3062 | break; | |
3063 | } | |
065c27c1 | 3064 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE); |
3065 | } | |
3066 | ||
3067 | static void r8168_phy_power_down(struct rtl8169_private *tp) | |
3068 | { | |
3069 | rtl_writephy(tp, 0x1f, 0x0000); | |
01dc7fec | 3070 | switch (tp->mac_version) { |
3071 | case RTL_GIGA_MAC_VER_32: | |
3072 | case RTL_GIGA_MAC_VER_33: | |
3073 | rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN); | |
3074 | break; | |
3075 | ||
3076 | case RTL_GIGA_MAC_VER_11: | |
3077 | case RTL_GIGA_MAC_VER_12: | |
3078 | case RTL_GIGA_MAC_VER_17: | |
3079 | case RTL_GIGA_MAC_VER_18: | |
3080 | case RTL_GIGA_MAC_VER_19: | |
3081 | case RTL_GIGA_MAC_VER_20: | |
3082 | case RTL_GIGA_MAC_VER_21: | |
3083 | case RTL_GIGA_MAC_VER_22: | |
3084 | case RTL_GIGA_MAC_VER_23: | |
3085 | case RTL_GIGA_MAC_VER_24: | |
3086 | case RTL_GIGA_MAC_VER_25: | |
3087 | case RTL_GIGA_MAC_VER_26: | |
3088 | case RTL_GIGA_MAC_VER_27: | |
3089 | case RTL_GIGA_MAC_VER_28: | |
3090 | case RTL_GIGA_MAC_VER_31: | |
3091 | rtl_writephy(tp, 0x0e, 0x0200); | |
3092 | default: | |
3093 | rtl_writephy(tp, MII_BMCR, BMCR_PDOWN); | |
3094 | break; | |
3095 | } | |
065c27c1 | 3096 | } |
3097 | ||
3098 | static void r8168_pll_power_down(struct rtl8169_private *tp) | |
3099 | { | |
3100 | void __iomem *ioaddr = tp->mmio_addr; | |
3101 | ||
5d2e1957 | 3102 | if (((tp->mac_version == RTL_GIGA_MAC_VER_27) || |
4804b3b3 | 3103 | (tp->mac_version == RTL_GIGA_MAC_VER_28) || |
3104 | (tp->mac_version == RTL_GIGA_MAC_VER_31)) && | |
3105 | r8168dp_check_dash(tp)) { | |
065c27c1 | 3106 | return; |
5d2e1957 | 3107 | } |
065c27c1 | 3108 | |
3109 | if (((tp->mac_version == RTL_GIGA_MAC_VER_23) || | |
3110 | (tp->mac_version == RTL_GIGA_MAC_VER_24)) && | |
3111 | (RTL_R16(CPlusCmd) & ASF)) { | |
3112 | return; | |
3113 | } | |
3114 | ||
01dc7fec | 3115 | if (tp->mac_version == RTL_GIGA_MAC_VER_32 || |
3116 | tp->mac_version == RTL_GIGA_MAC_VER_33) | |
3117 | rtl_ephy_write(ioaddr, 0x19, 0xff64); | |
3118 | ||
065c27c1 | 3119 | if (__rtl8169_get_wol(tp) & WAKE_ANY) { |
3120 | rtl_writephy(tp, 0x1f, 0x0000); | |
3121 | rtl_writephy(tp, MII_BMCR, 0x0000); | |
3122 | ||
3123 | RTL_W32(RxConfig, RTL_R32(RxConfig) | | |
3124 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys); | |
3125 | return; | |
3126 | } | |
3127 | ||
3128 | r8168_phy_power_down(tp); | |
3129 | ||
3130 | switch (tp->mac_version) { | |
3131 | case RTL_GIGA_MAC_VER_25: | |
3132 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
3133 | case RTL_GIGA_MAC_VER_27: |
3134 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 3135 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 3136 | case RTL_GIGA_MAC_VER_32: |
3137 | case RTL_GIGA_MAC_VER_33: | |
065c27c1 | 3138 | RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80); |
3139 | break; | |
3140 | } | |
3141 | } | |
3142 | ||
3143 | static void r8168_pll_power_up(struct rtl8169_private *tp) | |
3144 | { | |
3145 | void __iomem *ioaddr = tp->mmio_addr; | |
3146 | ||
5d2e1957 | 3147 | if (((tp->mac_version == RTL_GIGA_MAC_VER_27) || |
4804b3b3 | 3148 | (tp->mac_version == RTL_GIGA_MAC_VER_28) || |
3149 | (tp->mac_version == RTL_GIGA_MAC_VER_31)) && | |
3150 | r8168dp_check_dash(tp)) { | |
065c27c1 | 3151 | return; |
5d2e1957 | 3152 | } |
065c27c1 | 3153 | |
3154 | switch (tp->mac_version) { | |
3155 | case RTL_GIGA_MAC_VER_25: | |
3156 | case RTL_GIGA_MAC_VER_26: | |
5d2e1957 HW |
3157 | case RTL_GIGA_MAC_VER_27: |
3158 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 3159 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 3160 | case RTL_GIGA_MAC_VER_32: |
3161 | case RTL_GIGA_MAC_VER_33: | |
065c27c1 | 3162 | RTL_W8(PMCH, RTL_R8(PMCH) | 0x80); |
3163 | break; | |
3164 | } | |
3165 | ||
3166 | r8168_phy_power_up(tp); | |
3167 | } | |
3168 | ||
3169 | static void rtl_pll_power_op(struct rtl8169_private *tp, | |
3170 | void (*op)(struct rtl8169_private *)) | |
3171 | { | |
3172 | if (op) | |
3173 | op(tp); | |
3174 | } | |
3175 | ||
3176 | static void rtl_pll_power_down(struct rtl8169_private *tp) | |
3177 | { | |
3178 | rtl_pll_power_op(tp, tp->pll_power_ops.down); | |
3179 | } | |
3180 | ||
3181 | static void rtl_pll_power_up(struct rtl8169_private *tp) | |
3182 | { | |
3183 | rtl_pll_power_op(tp, tp->pll_power_ops.up); | |
3184 | } | |
3185 | ||
3186 | static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp) | |
3187 | { | |
3188 | struct pll_power_ops *ops = &tp->pll_power_ops; | |
3189 | ||
3190 | switch (tp->mac_version) { | |
3191 | case RTL_GIGA_MAC_VER_07: | |
3192 | case RTL_GIGA_MAC_VER_08: | |
3193 | case RTL_GIGA_MAC_VER_09: | |
3194 | case RTL_GIGA_MAC_VER_10: | |
3195 | case RTL_GIGA_MAC_VER_16: | |
5a5e4443 HW |
3196 | case RTL_GIGA_MAC_VER_29: |
3197 | case RTL_GIGA_MAC_VER_30: | |
065c27c1 | 3198 | ops->down = r810x_pll_power_down; |
3199 | ops->up = r810x_pll_power_up; | |
3200 | break; | |
3201 | ||
3202 | case RTL_GIGA_MAC_VER_11: | |
3203 | case RTL_GIGA_MAC_VER_12: | |
3204 | case RTL_GIGA_MAC_VER_17: | |
3205 | case RTL_GIGA_MAC_VER_18: | |
3206 | case RTL_GIGA_MAC_VER_19: | |
3207 | case RTL_GIGA_MAC_VER_20: | |
3208 | case RTL_GIGA_MAC_VER_21: | |
3209 | case RTL_GIGA_MAC_VER_22: | |
3210 | case RTL_GIGA_MAC_VER_23: | |
3211 | case RTL_GIGA_MAC_VER_24: | |
3212 | case RTL_GIGA_MAC_VER_25: | |
3213 | case RTL_GIGA_MAC_VER_26: | |
3214 | case RTL_GIGA_MAC_VER_27: | |
e6de30d6 | 3215 | case RTL_GIGA_MAC_VER_28: |
4804b3b3 | 3216 | case RTL_GIGA_MAC_VER_31: |
01dc7fec | 3217 | case RTL_GIGA_MAC_VER_32: |
3218 | case RTL_GIGA_MAC_VER_33: | |
065c27c1 | 3219 | ops->down = r8168_pll_power_down; |
3220 | ops->up = r8168_pll_power_up; | |
3221 | break; | |
3222 | ||
3223 | default: | |
3224 | ops->down = NULL; | |
3225 | ops->up = NULL; | |
3226 | break; | |
3227 | } | |
3228 | } | |
3229 | ||
1da177e4 | 3230 | static int __devinit |
4ff96fa6 | 3231 | rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 3232 | { |
0e485150 FR |
3233 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
3234 | const unsigned int region = cfg->region; | |
1da177e4 | 3235 | struct rtl8169_private *tp; |
ccdffb9a | 3236 | struct mii_if_info *mii; |
4ff96fa6 FR |
3237 | struct net_device *dev; |
3238 | void __iomem *ioaddr; | |
07d3f51f FR |
3239 | unsigned int i; |
3240 | int rc; | |
1da177e4 | 3241 | |
4ff96fa6 FR |
3242 | if (netif_msg_drv(&debug)) { |
3243 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
3244 | MODULENAME, RTL8169_VERSION); | |
3245 | } | |
1da177e4 | 3246 | |
1da177e4 | 3247 | dev = alloc_etherdev(sizeof (*tp)); |
4ff96fa6 | 3248 | if (!dev) { |
b57b7e5a | 3249 | if (netif_msg_drv(&debug)) |
9b91cf9d | 3250 | dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
4ff96fa6 FR |
3251 | rc = -ENOMEM; |
3252 | goto out; | |
1da177e4 LT |
3253 | } |
3254 | ||
1da177e4 | 3255 | SET_NETDEV_DEV(dev, &pdev->dev); |
8b4ab28d | 3256 | dev->netdev_ops = &rtl8169_netdev_ops; |
1da177e4 | 3257 | tp = netdev_priv(dev); |
c4028958 | 3258 | tp->dev = dev; |
21e197f2 | 3259 | tp->pci_dev = pdev; |
b57b7e5a | 3260 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
1da177e4 | 3261 | |
ccdffb9a FR |
3262 | mii = &tp->mii; |
3263 | mii->dev = dev; | |
3264 | mii->mdio_read = rtl_mdio_read; | |
3265 | mii->mdio_write = rtl_mdio_write; | |
3266 | mii->phy_id_mask = 0x1f; | |
3267 | mii->reg_num_mask = 0x1f; | |
3268 | mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); | |
3269 | ||
ba04c7c9 SG |
3270 | /* disable ASPM completely as that cause random device stop working |
3271 | * problems as well as full system hangs for some PCIe devices users */ | |
3272 | pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | | |
3273 | PCIE_LINK_STATE_CLKPM); | |
3274 | ||
1da177e4 LT |
3275 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
3276 | rc = pci_enable_device(pdev); | |
b57b7e5a | 3277 | if (rc < 0) { |
bf82c189 | 3278 | netif_err(tp, probe, dev, "enable failure\n"); |
4ff96fa6 | 3279 | goto err_out_free_dev_1; |
1da177e4 LT |
3280 | } |
3281 | ||
87aeec76 | 3282 | if (pci_set_mwi(pdev) < 0) |
3283 | netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n"); | |
1da177e4 | 3284 | |
1da177e4 | 3285 | /* make sure PCI base addr 1 is MMIO */ |
bcf0bf90 | 3286 | if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
bf82c189 JP |
3287 | netif_err(tp, probe, dev, |
3288 | "region #%d not an MMIO resource, aborting\n", | |
3289 | region); | |
1da177e4 | 3290 | rc = -ENODEV; |
87aeec76 | 3291 | goto err_out_mwi_2; |
1da177e4 | 3292 | } |
4ff96fa6 | 3293 | |
1da177e4 | 3294 | /* check for weird/broken PCI region reporting */ |
bcf0bf90 | 3295 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
bf82c189 JP |
3296 | netif_err(tp, probe, dev, |
3297 | "Invalid PCI region size(s), aborting\n"); | |
1da177e4 | 3298 | rc = -ENODEV; |
87aeec76 | 3299 | goto err_out_mwi_2; |
1da177e4 LT |
3300 | } |
3301 | ||
3302 | rc = pci_request_regions(pdev, MODULENAME); | |
b57b7e5a | 3303 | if (rc < 0) { |
bf82c189 | 3304 | netif_err(tp, probe, dev, "could not request regions\n"); |
87aeec76 | 3305 | goto err_out_mwi_2; |
1da177e4 LT |
3306 | } |
3307 | ||
d24e9aaf | 3308 | tp->cp_cmd = RxChkSum; |
1da177e4 LT |
3309 | |
3310 | if ((sizeof(dma_addr_t) > 4) && | |
4300e8c7 | 3311 | !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) { |
1da177e4 LT |
3312 | tp->cp_cmd |= PCIDAC; |
3313 | dev->features |= NETIF_F_HIGHDMA; | |
3314 | } else { | |
284901a9 | 3315 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); |
1da177e4 | 3316 | if (rc < 0) { |
bf82c189 | 3317 | netif_err(tp, probe, dev, "DMA configuration failed\n"); |
87aeec76 | 3318 | goto err_out_free_res_3; |
1da177e4 LT |
3319 | } |
3320 | } | |
3321 | ||
1da177e4 | 3322 | /* ioremap MMIO region */ |
bcf0bf90 | 3323 | ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
4ff96fa6 | 3324 | if (!ioaddr) { |
bf82c189 | 3325 | netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n"); |
1da177e4 | 3326 | rc = -EIO; |
87aeec76 | 3327 | goto err_out_free_res_3; |
1da177e4 LT |
3328 | } |
3329 | ||
4300e8c7 DM |
3330 | tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
3331 | if (!tp->pcie_cap) | |
3332 | netif_info(tp, probe, dev, "no PCI Express capability\n"); | |
3333 | ||
d78ad8cb | 3334 | RTL_W16(IntrMask, 0x0000); |
1da177e4 LT |
3335 | |
3336 | /* Soft reset the chip. */ | |
3337 | RTL_W8(ChipCmd, CmdReset); | |
3338 | ||
3339 | /* Check that the chip has finished the reset. */ | |
07d3f51f | 3340 | for (i = 0; i < 100; i++) { |
1da177e4 LT |
3341 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
3342 | break; | |
b518fa8e | 3343 | msleep_interruptible(1); |
1da177e4 LT |
3344 | } |
3345 | ||
d78ad8cb KW |
3346 | RTL_W16(IntrStatus, 0xffff); |
3347 | ||
ca52efd5 | 3348 | pci_set_master(pdev); |
3349 | ||
1da177e4 LT |
3350 | /* Identify chip attached to board */ |
3351 | rtl8169_get_mac_version(tp, ioaddr); | |
1da177e4 | 3352 | |
7a8fc77b FR |
3353 | /* |
3354 | * Pretend we are using VLANs; This bypasses a nasty bug where | |
3355 | * Interrupts stop flowing on high load on 8110SCd controllers. | |
3356 | */ | |
3357 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) | |
3358 | tp->cp_cmd |= RxVlan; | |
3359 | ||
c0e45c1c | 3360 | rtl_init_mdio_ops(tp); |
065c27c1 | 3361 | rtl_init_pll_power_ops(tp); |
c0e45c1c | 3362 | |
f21b75e9 JD |
3363 | /* Use appropriate default if unknown */ |
3364 | if (tp->mac_version == RTL_GIGA_MAC_NONE) { | |
bf82c189 JP |
3365 | netif_notice(tp, probe, dev, |
3366 | "unknown MAC, using family default\n"); | |
f21b75e9 JD |
3367 | tp->mac_version = cfg->default_ver; |
3368 | } | |
3369 | ||
1da177e4 | 3370 | rtl8169_print_mac_version(tp); |
1da177e4 | 3371 | |
cee60c37 | 3372 | for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { |
1da177e4 LT |
3373 | if (tp->mac_version == rtl_chip_info[i].mac_version) |
3374 | break; | |
3375 | } | |
cee60c37 | 3376 | if (i == ARRAY_SIZE(rtl_chip_info)) { |
f21b75e9 JD |
3377 | dev_err(&pdev->dev, |
3378 | "driver bug, MAC version not found in rtl_chip_info\n"); | |
87aeec76 | 3379 | goto err_out_msi_4; |
1da177e4 LT |
3380 | } |
3381 | tp->chipset = i; | |
3382 | ||
5d06a99f FR |
3383 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
3384 | RTL_W8(Config1, RTL_R8(Config1) | PMEnable); | |
3385 | RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); | |
20037fa4 BP |
3386 | if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
3387 | tp->features |= RTL_FEATURE_WOL; | |
3388 | if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) | |
3389 | tp->features |= RTL_FEATURE_WOL; | |
fbac58fc | 3390 | tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
5d06a99f FR |
3391 | RTL_W8(Cfg9346, Cfg9346_Lock); |
3392 | ||
66ec5d4f FR |
3393 | if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && |
3394 | (RTL_R8(PHYstatus) & TBI_Enable)) { | |
1da177e4 LT |
3395 | tp->set_speed = rtl8169_set_speed_tbi; |
3396 | tp->get_settings = rtl8169_gset_tbi; | |
3397 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; | |
3398 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
3399 | tp->link_ok = rtl8169_tbi_link_ok; | |
8b4ab28d | 3400 | tp->do_ioctl = rtl_tbi_ioctl; |
1da177e4 | 3401 | |
64e4bfb4 | 3402 | tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ |
1da177e4 LT |
3403 | } else { |
3404 | tp->set_speed = rtl8169_set_speed_xmii; | |
3405 | tp->get_settings = rtl8169_gset_xmii; | |
3406 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; | |
3407 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
3408 | tp->link_ok = rtl8169_xmii_link_ok; | |
8b4ab28d | 3409 | tp->do_ioctl = rtl_xmii_ioctl; |
1da177e4 LT |
3410 | } |
3411 | ||
df58ef51 FR |
3412 | spin_lock_init(&tp->lock); |
3413 | ||
738e1e69 PV |
3414 | tp->mmio_addr = ioaddr; |
3415 | ||
7bf6bf48 | 3416 | /* Get MAC address */ |
1da177e4 LT |
3417 | for (i = 0; i < MAC_ADDR_LEN; i++) |
3418 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | |
6d6525b7 | 3419 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 | 3420 | |
1da177e4 | 3421 | SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); |
1da177e4 LT |
3422 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
3423 | dev->irq = pdev->irq; | |
3424 | dev->base_addr = (unsigned long) ioaddr; | |
1da177e4 | 3425 | |
bea3348e | 3426 | netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
1da177e4 | 3427 | |
7a8fc77b | 3428 | dev->features |= NETIF_F_HW_VLAN_TX_RX | NETIF_F_GRO; |
1da177e4 LT |
3429 | |
3430 | tp->intr_mask = 0xffff; | |
0e485150 FR |
3431 | tp->hw_start = cfg->hw_start; |
3432 | tp->intr_event = cfg->intr_event; | |
3433 | tp->napi_event = cfg->napi_event; | |
1da177e4 | 3434 | |
2efa53f3 FR |
3435 | init_timer(&tp->timer); |
3436 | tp->timer.data = (unsigned long) dev; | |
3437 | tp->timer.function = rtl8169_phy_timer; | |
3438 | ||
1da177e4 | 3439 | rc = register_netdev(dev); |
4ff96fa6 | 3440 | if (rc < 0) |
87aeec76 | 3441 | goto err_out_msi_4; |
1da177e4 LT |
3442 | |
3443 | pci_set_drvdata(pdev, dev); | |
3444 | ||
bf82c189 JP |
3445 | netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n", |
3446 | rtl_chip_info[tp->chipset].name, | |
3447 | dev->base_addr, dev->dev_addr, | |
3448 | (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq); | |
1da177e4 | 3449 | |
e6de30d6 | 3450 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27) || |
4804b3b3 | 3451 | (tp->mac_version == RTL_GIGA_MAC_VER_28) || |
3452 | (tp->mac_version == RTL_GIGA_MAC_VER_31)) { | |
b646d900 | 3453 | rtl8168_driver_start(tp); |
e6de30d6 | 3454 | } |
b646d900 | 3455 | |
8b76ab39 | 3456 | device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
1da177e4 | 3457 | |
f3ec4f87 AS |
3458 | if (pci_dev_run_wake(pdev)) |
3459 | pm_runtime_put_noidle(&pdev->dev); | |
e1759441 | 3460 | |
0d672e9f IV |
3461 | netif_carrier_off(dev); |
3462 | ||
4ff96fa6 FR |
3463 | out: |
3464 | return rc; | |
1da177e4 | 3465 | |
87aeec76 | 3466 | err_out_msi_4: |
fbac58fc | 3467 | rtl_disable_msi(pdev, tp); |
4ff96fa6 | 3468 | iounmap(ioaddr); |
87aeec76 | 3469 | err_out_free_res_3: |
4ff96fa6 | 3470 | pci_release_regions(pdev); |
87aeec76 | 3471 | err_out_mwi_2: |
4ff96fa6 | 3472 | pci_clear_mwi(pdev); |
4ff96fa6 FR |
3473 | pci_disable_device(pdev); |
3474 | err_out_free_dev_1: | |
3475 | free_netdev(dev); | |
3476 | goto out; | |
1da177e4 LT |
3477 | } |
3478 | ||
07d3f51f | 3479 | static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
3480 | { |
3481 | struct net_device *dev = pci_get_drvdata(pdev); | |
3482 | struct rtl8169_private *tp = netdev_priv(dev); | |
3483 | ||
e6de30d6 | 3484 | if ((tp->mac_version == RTL_GIGA_MAC_VER_27) || |
4804b3b3 | 3485 | (tp->mac_version == RTL_GIGA_MAC_VER_28) || |
3486 | (tp->mac_version == RTL_GIGA_MAC_VER_31)) { | |
b646d900 | 3487 | rtl8168_driver_stop(tp); |
e6de30d6 | 3488 | } |
b646d900 | 3489 | |
23f333a2 | 3490 | cancel_delayed_work_sync(&tp->task); |
eb2a021c | 3491 | |
f1e02ed1 | 3492 | rtl_release_firmware(tp); |
3493 | ||
1da177e4 | 3494 | unregister_netdev(dev); |
cc098dc7 | 3495 | |
f3ec4f87 AS |
3496 | if (pci_dev_run_wake(pdev)) |
3497 | pm_runtime_get_noresume(&pdev->dev); | |
e1759441 | 3498 | |
cc098dc7 IV |
3499 | /* restore original MAC address */ |
3500 | rtl_rar_set(tp, dev->perm_addr); | |
3501 | ||
fbac58fc | 3502 | rtl_disable_msi(pdev, tp); |
1da177e4 LT |
3503 | rtl8169_release_board(pdev, dev, tp->mmio_addr); |
3504 | pci_set_drvdata(pdev, NULL); | |
3505 | } | |
3506 | ||
1da177e4 LT |
3507 | static int rtl8169_open(struct net_device *dev) |
3508 | { | |
3509 | struct rtl8169_private *tp = netdev_priv(dev); | |
eee3a96c | 3510 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 3511 | struct pci_dev *pdev = tp->pci_dev; |
99f252b0 | 3512 | int retval = -ENOMEM; |
1da177e4 | 3513 | |
e1759441 | 3514 | pm_runtime_get_sync(&pdev->dev); |
1da177e4 | 3515 | |
1da177e4 LT |
3516 | /* |
3517 | * Rx and Tx desscriptors needs 256 bytes alignment. | |
82553bb6 | 3518 | * dma_alloc_coherent provides more. |
1da177e4 | 3519 | */ |
82553bb6 SG |
3520 | tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES, |
3521 | &tp->TxPhyAddr, GFP_KERNEL); | |
1da177e4 | 3522 | if (!tp->TxDescArray) |
e1759441 | 3523 | goto err_pm_runtime_put; |
1da177e4 | 3524 | |
82553bb6 SG |
3525 | tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES, |
3526 | &tp->RxPhyAddr, GFP_KERNEL); | |
1da177e4 | 3527 | if (!tp->RxDescArray) |
99f252b0 | 3528 | goto err_free_tx_0; |
1da177e4 LT |
3529 | |
3530 | retval = rtl8169_init_ring(dev); | |
3531 | if (retval < 0) | |
99f252b0 | 3532 | goto err_free_rx_1; |
1da177e4 | 3533 | |
c4028958 | 3534 | INIT_DELAYED_WORK(&tp->task, NULL); |
1da177e4 | 3535 | |
99f252b0 FR |
3536 | smp_mb(); |
3537 | ||
fbac58fc FR |
3538 | retval = request_irq(dev->irq, rtl8169_interrupt, |
3539 | (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, | |
99f252b0 FR |
3540 | dev->name, dev); |
3541 | if (retval < 0) | |
3542 | goto err_release_ring_2; | |
3543 | ||
bea3348e | 3544 | napi_enable(&tp->napi); |
bea3348e | 3545 | |
eee3a96c | 3546 | rtl8169_init_phy(dev, tp); |
3547 | ||
7a8fc77b | 3548 | rtl8169_vlan_mode(dev); |
eee3a96c | 3549 | |
065c27c1 | 3550 | rtl_pll_power_up(tp); |
3551 | ||
07ce4064 | 3552 | rtl_hw_start(dev); |
1da177e4 LT |
3553 | |
3554 | rtl8169_request_timer(dev); | |
3555 | ||
e1759441 RW |
3556 | tp->saved_wolopts = 0; |
3557 | pm_runtime_put_noidle(&pdev->dev); | |
3558 | ||
eee3a96c | 3559 | rtl8169_check_link_status(dev, tp, ioaddr); |
1da177e4 LT |
3560 | out: |
3561 | return retval; | |
3562 | ||
99f252b0 FR |
3563 | err_release_ring_2: |
3564 | rtl8169_rx_clear(tp); | |
3565 | err_free_rx_1: | |
82553bb6 SG |
3566 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
3567 | tp->RxPhyAddr); | |
e1759441 | 3568 | tp->RxDescArray = NULL; |
99f252b0 | 3569 | err_free_tx_0: |
82553bb6 SG |
3570 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, |
3571 | tp->TxPhyAddr); | |
e1759441 RW |
3572 | tp->TxDescArray = NULL; |
3573 | err_pm_runtime_put: | |
3574 | pm_runtime_put_noidle(&pdev->dev); | |
1da177e4 LT |
3575 | goto out; |
3576 | } | |
3577 | ||
e6de30d6 | 3578 | static void rtl8169_hw_reset(struct rtl8169_private *tp) |
1da177e4 | 3579 | { |
e6de30d6 | 3580 | void __iomem *ioaddr = tp->mmio_addr; |
3581 | ||
1da177e4 LT |
3582 | /* Disable interrupts */ |
3583 | rtl8169_irq_mask_and_ack(ioaddr); | |
3584 | ||
5d2e1957 | 3585 | if (tp->mac_version == RTL_GIGA_MAC_VER_27 || |
4804b3b3 | 3586 | tp->mac_version == RTL_GIGA_MAC_VER_28 || |
3587 | tp->mac_version == RTL_GIGA_MAC_VER_31) { | |
e6de30d6 | 3588 | while (RTL_R8(TxPoll) & NPQ) |
3589 | udelay(20); | |
3590 | ||
3591 | } | |
3592 | ||
1da177e4 LT |
3593 | /* Reset the chipset */ |
3594 | RTL_W8(ChipCmd, CmdReset); | |
3595 | ||
3596 | /* PCI commit */ | |
3597 | RTL_R8(ChipCmd); | |
3598 | } | |
3599 | ||
7f796d83 | 3600 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 FR |
3601 | { |
3602 | void __iomem *ioaddr = tp->mmio_addr; | |
3603 | u32 cfg = rtl8169_rx_config; | |
3604 | ||
3605 | cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); | |
3606 | RTL_W32(RxConfig, cfg); | |
3607 | ||
3608 | /* Set DMA burst size and Interframe Gap Time */ | |
3609 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
3610 | (InterFrameGap << TxInterFrameGapShift)); | |
3611 | } | |
3612 | ||
07ce4064 | 3613 | static void rtl_hw_start(struct net_device *dev) |
1da177e4 LT |
3614 | { |
3615 | struct rtl8169_private *tp = netdev_priv(dev); | |
3616 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 3617 | unsigned int i; |
1da177e4 LT |
3618 | |
3619 | /* Soft reset the chip. */ | |
3620 | RTL_W8(ChipCmd, CmdReset); | |
3621 | ||
3622 | /* Check that the chip has finished the reset. */ | |
07d3f51f | 3623 | for (i = 0; i < 100; i++) { |
1da177e4 LT |
3624 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
3625 | break; | |
b518fa8e | 3626 | msleep_interruptible(1); |
1da177e4 LT |
3627 | } |
3628 | ||
07ce4064 FR |
3629 | tp->hw_start(dev); |
3630 | ||
07ce4064 FR |
3631 | netif_start_queue(dev); |
3632 | } | |
3633 | ||
3634 | ||
7f796d83 FR |
3635 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
3636 | void __iomem *ioaddr) | |
3637 | { | |
3638 | /* | |
3639 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
3640 | * register to be written before TxDescAddrLow to work. | |
3641 | * Switching from MMIO to I/O access fixes the issue as well. | |
3642 | */ | |
3643 | RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); | |
284901a9 | 3644 | RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 | 3645 | RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); |
284901a9 | 3646 | RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32)); |
7f796d83 FR |
3647 | } |
3648 | ||
3649 | static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) | |
3650 | { | |
3651 | u16 cmd; | |
3652 | ||
3653 | cmd = RTL_R16(CPlusCmd); | |
3654 | RTL_W16(CPlusCmd, cmd); | |
3655 | return cmd; | |
3656 | } | |
3657 | ||
fdd7b4c3 | 3658 | static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz) |
7f796d83 FR |
3659 | { |
3660 | /* Low hurts. Let's disable the filtering. */ | |
207d6e87 | 3661 | RTL_W16(RxMaxSize, rx_buf_sz + 1); |
7f796d83 FR |
3662 | } |
3663 | ||
6dccd16b FR |
3664 | static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
3665 | { | |
350f7596 | 3666 | static const struct { |
6dccd16b FR |
3667 | u32 mac_version; |
3668 | u32 clk; | |
3669 | u32 val; | |
3670 | } cfg2_info [] = { | |
3671 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
3672 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
3673 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
3674 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
3675 | }, *p = cfg2_info; | |
3676 | unsigned int i; | |
3677 | u32 clk; | |
3678 | ||
3679 | clk = RTL_R8(Config2) & PCI_Clock_66MHz; | |
cadf1855 | 3680 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
6dccd16b FR |
3681 | if ((p->mac_version == mac_version) && (p->clk == clk)) { |
3682 | RTL_W32(0x7c, p->val); | |
3683 | break; | |
3684 | } | |
3685 | } | |
3686 | } | |
3687 | ||
07ce4064 FR |
3688 | static void rtl_hw_start_8169(struct net_device *dev) |
3689 | { | |
3690 | struct rtl8169_private *tp = netdev_priv(dev); | |
3691 | void __iomem *ioaddr = tp->mmio_addr; | |
3692 | struct pci_dev *pdev = tp->pci_dev; | |
07ce4064 | 3693 | |
9cb427b6 FR |
3694 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
3695 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); | |
3696 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
3697 | } | |
3698 | ||
1da177e4 | 3699 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
9cb427b6 FR |
3700 | if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
3701 | (tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
3702 | (tp->mac_version == RTL_GIGA_MAC_VER_03) || | |
3703 | (tp->mac_version == RTL_GIGA_MAC_VER_04)) | |
3704 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
3705 | ||
f0298f81 | 3706 | RTL_W8(EarlyTxThres, NoEarlyTx); |
1da177e4 | 3707 | |
6f0333b8 | 3708 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
1da177e4 | 3709 | |
c946b304 FR |
3710 | if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
3711 | (tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
3712 | (tp->mac_version == RTL_GIGA_MAC_VER_03) || | |
3713 | (tp->mac_version == RTL_GIGA_MAC_VER_04)) | |
3714 | rtl_set_rx_tx_config_registers(tp); | |
1da177e4 | 3715 | |
7f796d83 | 3716 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
1da177e4 | 3717 | |
bcf0bf90 FR |
3718 | if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
3719 | (tp->mac_version == RTL_GIGA_MAC_VER_03)) { | |
06fa7358 | 3720 | dprintk("Set MAC Reg C+CR Offset 0xE0. " |
1da177e4 | 3721 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 3722 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
3723 | } |
3724 | ||
bcf0bf90 FR |
3725 | RTL_W16(CPlusCmd, tp->cp_cmd); |
3726 | ||
6dccd16b FR |
3727 | rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
3728 | ||
1da177e4 LT |
3729 | /* |
3730 | * Undocumented corner. Supposedly: | |
3731 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
3732 | */ | |
3733 | RTL_W16(IntrMitigate, 0x0000); | |
3734 | ||
7f796d83 | 3735 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
9cb427b6 | 3736 | |
c946b304 FR |
3737 | if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && |
3738 | (tp->mac_version != RTL_GIGA_MAC_VER_02) && | |
3739 | (tp->mac_version != RTL_GIGA_MAC_VER_03) && | |
3740 | (tp->mac_version != RTL_GIGA_MAC_VER_04)) { | |
3741 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
3742 | rtl_set_rx_tx_config_registers(tp); | |
3743 | } | |
3744 | ||
1da177e4 | 3745 | RTL_W8(Cfg9346, Cfg9346_Lock); |
b518fa8e FR |
3746 | |
3747 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
3748 | RTL_R8(IntrMask); | |
1da177e4 LT |
3749 | |
3750 | RTL_W32(RxMissed, 0); | |
3751 | ||
07ce4064 | 3752 | rtl_set_rx_mode(dev); |
1da177e4 LT |
3753 | |
3754 | /* no early-rx interrupts */ | |
3755 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | |
6dccd16b FR |
3756 | |
3757 | /* Enable all known interrupts by setting the interrupt mask. */ | |
0e485150 | 3758 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 3759 | } |
1da177e4 | 3760 | |
9c14ceaf | 3761 | static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
458a9f61 | 3762 | { |
9c14ceaf FR |
3763 | struct net_device *dev = pci_get_drvdata(pdev); |
3764 | struct rtl8169_private *tp = netdev_priv(dev); | |
3765 | int cap = tp->pcie_cap; | |
3766 | ||
3767 | if (cap) { | |
3768 | u16 ctl; | |
458a9f61 | 3769 | |
9c14ceaf FR |
3770 | pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
3771 | ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; | |
3772 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); | |
3773 | } | |
458a9f61 FR |
3774 | } |
3775 | ||
650e8d5d | 3776 | static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits) |
dacf8154 FR |
3777 | { |
3778 | u32 csi; | |
3779 | ||
3780 | csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; | |
650e8d5d | 3781 | rtl_csi_write(ioaddr, 0x070c, csi | bits); |
3782 | } | |
3783 | ||
e6de30d6 | 3784 | static void rtl_csi_access_enable_1(void __iomem *ioaddr) |
3785 | { | |
3786 | rtl_csi_access_enable(ioaddr, 0x17000000); | |
3787 | } | |
3788 | ||
650e8d5d | 3789 | static void rtl_csi_access_enable_2(void __iomem *ioaddr) |
3790 | { | |
3791 | rtl_csi_access_enable(ioaddr, 0x27000000); | |
dacf8154 FR |
3792 | } |
3793 | ||
3794 | struct ephy_info { | |
3795 | unsigned int offset; | |
3796 | u16 mask; | |
3797 | u16 bits; | |
3798 | }; | |
3799 | ||
350f7596 | 3800 | static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len) |
dacf8154 FR |
3801 | { |
3802 | u16 w; | |
3803 | ||
3804 | while (len-- > 0) { | |
3805 | w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; | |
3806 | rtl_ephy_write(ioaddr, e->offset, w); | |
3807 | e++; | |
3808 | } | |
3809 | } | |
3810 | ||
b726e493 FR |
3811 | static void rtl_disable_clock_request(struct pci_dev *pdev) |
3812 | { | |
3813 | struct net_device *dev = pci_get_drvdata(pdev); | |
3814 | struct rtl8169_private *tp = netdev_priv(dev); | |
3815 | int cap = tp->pcie_cap; | |
3816 | ||
3817 | if (cap) { | |
3818 | u16 ctl; | |
3819 | ||
3820 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
3821 | ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
3822 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
3823 | } | |
3824 | } | |
3825 | ||
e6de30d6 | 3826 | static void rtl_enable_clock_request(struct pci_dev *pdev) |
3827 | { | |
3828 | struct net_device *dev = pci_get_drvdata(pdev); | |
3829 | struct rtl8169_private *tp = netdev_priv(dev); | |
3830 | int cap = tp->pcie_cap; | |
3831 | ||
3832 | if (cap) { | |
3833 | u16 ctl; | |
3834 | ||
3835 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
3836 | ctl |= PCI_EXP_LNKCTL_CLKREQ_EN; | |
3837 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
3838 | } | |
3839 | } | |
3840 | ||
b726e493 FR |
3841 | #define R8168_CPCMD_QUIRK_MASK (\ |
3842 | EnableBist | \ | |
3843 | Mac_dbgo_oe | \ | |
3844 | Force_half_dup | \ | |
3845 | Force_rxflow_en | \ | |
3846 | Force_txflow_en | \ | |
3847 | Cxpl_dbg_sel | \ | |
3848 | ASF | \ | |
3849 | PktCntrDisable | \ | |
3850 | Mac_dbgo_sel) | |
3851 | ||
219a1e9d FR |
3852 | static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
3853 | { | |
b726e493 FR |
3854 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
3855 | ||
3856 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
3857 | ||
2e68ae44 FR |
3858 | rtl_tx_performance_tweak(pdev, |
3859 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
219a1e9d FR |
3860 | } |
3861 | ||
3862 | static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) | |
3863 | { | |
3864 | rtl_hw_start_8168bb(ioaddr, pdev); | |
b726e493 | 3865 | |
f0298f81 | 3866 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
b726e493 FR |
3867 | |
3868 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
219a1e9d FR |
3869 | } |
3870 | ||
3871 | static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) | |
3872 | { | |
b726e493 FR |
3873 | RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
3874 | ||
3875 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
3876 | ||
219a1e9d | 3877 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
b726e493 FR |
3878 | |
3879 | rtl_disable_clock_request(pdev); | |
3880 | ||
3881 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
219a1e9d FR |
3882 | } |
3883 | ||
ef3386f0 | 3884 | static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
219a1e9d | 3885 | { |
350f7596 | 3886 | static const struct ephy_info e_info_8168cp[] = { |
b726e493 FR |
3887 | { 0x01, 0, 0x0001 }, |
3888 | { 0x02, 0x0800, 0x1000 }, | |
3889 | { 0x03, 0, 0x0042 }, | |
3890 | { 0x06, 0x0080, 0x0000 }, | |
3891 | { 0x07, 0, 0x2000 } | |
3892 | }; | |
3893 | ||
650e8d5d | 3894 | rtl_csi_access_enable_2(ioaddr); |
b726e493 FR |
3895 | |
3896 | rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); | |
3897 | ||
219a1e9d FR |
3898 | __rtl_hw_start_8168cp(ioaddr, pdev); |
3899 | } | |
3900 | ||
ef3386f0 FR |
3901 | static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
3902 | { | |
650e8d5d | 3903 | rtl_csi_access_enable_2(ioaddr); |
ef3386f0 FR |
3904 | |
3905 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
3906 | ||
3907 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
3908 | ||
3909 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
3910 | } | |
3911 | ||
7f3e3d3a FR |
3912 | static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
3913 | { | |
650e8d5d | 3914 | rtl_csi_access_enable_2(ioaddr); |
7f3e3d3a FR |
3915 | |
3916 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
3917 | ||
3918 | /* Magic. */ | |
3919 | RTL_W8(DBG_REG, 0x20); | |
3920 | ||
f0298f81 | 3921 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
7f3e3d3a FR |
3922 | |
3923 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
3924 | ||
3925 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
3926 | } | |
3927 | ||
219a1e9d FR |
3928 | static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
3929 | { | |
350f7596 | 3930 | static const struct ephy_info e_info_8168c_1[] = { |
b726e493 FR |
3931 | { 0x02, 0x0800, 0x1000 }, |
3932 | { 0x03, 0, 0x0002 }, | |
3933 | { 0x06, 0x0080, 0x0000 } | |
3934 | }; | |
3935 | ||
650e8d5d | 3936 | rtl_csi_access_enable_2(ioaddr); |
b726e493 FR |
3937 | |
3938 | RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); | |
3939 | ||
3940 | rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); | |
3941 | ||
219a1e9d FR |
3942 | __rtl_hw_start_8168cp(ioaddr, pdev); |
3943 | } | |
3944 | ||
3945 | static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
3946 | { | |
350f7596 | 3947 | static const struct ephy_info e_info_8168c_2[] = { |
b726e493 FR |
3948 | { 0x01, 0, 0x0001 }, |
3949 | { 0x03, 0x0400, 0x0220 } | |
3950 | }; | |
3951 | ||
650e8d5d | 3952 | rtl_csi_access_enable_2(ioaddr); |
b726e493 FR |
3953 | |
3954 | rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); | |
3955 | ||
219a1e9d FR |
3956 | __rtl_hw_start_8168cp(ioaddr, pdev); |
3957 | } | |
3958 | ||
197ff761 FR |
3959 | static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
3960 | { | |
3961 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
3962 | } | |
3963 | ||
6fb07058 FR |
3964 | static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
3965 | { | |
650e8d5d | 3966 | rtl_csi_access_enable_2(ioaddr); |
6fb07058 FR |
3967 | |
3968 | __rtl_hw_start_8168cp(ioaddr, pdev); | |
3969 | } | |
3970 | ||
5b538df9 FR |
3971 | static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
3972 | { | |
650e8d5d | 3973 | rtl_csi_access_enable_2(ioaddr); |
5b538df9 FR |
3974 | |
3975 | rtl_disable_clock_request(pdev); | |
3976 | ||
f0298f81 | 3977 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
5b538df9 FR |
3978 | |
3979 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
3980 | ||
3981 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
3982 | } | |
3983 | ||
4804b3b3 | 3984 | static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev) |
3985 | { | |
3986 | rtl_csi_access_enable_1(ioaddr); | |
3987 | ||
3988 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
3989 | ||
3990 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
3991 | ||
3992 | rtl_disable_clock_request(pdev); | |
3993 | } | |
3994 | ||
e6de30d6 | 3995 | static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev) |
3996 | { | |
3997 | static const struct ephy_info e_info_8168d_4[] = { | |
3998 | { 0x0b, ~0, 0x48 }, | |
3999 | { 0x19, 0x20, 0x50 }, | |
4000 | { 0x0c, ~0, 0x20 } | |
4001 | }; | |
4002 | int i; | |
4003 | ||
4004 | rtl_csi_access_enable_1(ioaddr); | |
4005 | ||
4006 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4007 | ||
4008 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
4009 | ||
4010 | for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) { | |
4011 | const struct ephy_info *e = e_info_8168d_4 + i; | |
4012 | u16 w; | |
4013 | ||
4014 | w = rtl_ephy_read(ioaddr, e->offset); | |
4015 | rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits); | |
4016 | } | |
4017 | ||
4018 | rtl_enable_clock_request(pdev); | |
4019 | } | |
4020 | ||
01dc7fec | 4021 | static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev) |
4022 | { | |
4023 | static const struct ephy_info e_info_8168e[] = { | |
4024 | { 0x00, 0x0200, 0x0100 }, | |
4025 | { 0x00, 0x0000, 0x0004 }, | |
4026 | { 0x06, 0x0002, 0x0001 }, | |
4027 | { 0x06, 0x0000, 0x0030 }, | |
4028 | { 0x07, 0x0000, 0x2000 }, | |
4029 | { 0x00, 0x0000, 0x0020 }, | |
4030 | { 0x03, 0x5800, 0x2000 }, | |
4031 | { 0x03, 0x0000, 0x0001 }, | |
4032 | { 0x01, 0x0800, 0x1000 }, | |
4033 | { 0x07, 0x0000, 0x4000 }, | |
4034 | { 0x1e, 0x0000, 0x2000 }, | |
4035 | { 0x19, 0xffff, 0xfe6c }, | |
4036 | { 0x0a, 0x0000, 0x0040 } | |
4037 | }; | |
4038 | ||
4039 | rtl_csi_access_enable_2(ioaddr); | |
4040 | ||
4041 | rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e)); | |
4042 | ||
4043 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4044 | ||
4045 | RTL_W8(MaxTxPacketSize, TxPacketMax); | |
4046 | ||
4047 | rtl_disable_clock_request(pdev); | |
4048 | ||
4049 | /* Reset tx FIFO pointer */ | |
4050 | RTL_W32(MISC, RTL_R32(MISC) | txpla_rst); | |
4051 | RTL_W32(MISC, RTL_R32(MISC) & ~txpla_rst); | |
4052 | ||
4053 | RTL_W8(Config5, RTL_R8(Config5) & ~spi_en); | |
4054 | } | |
4055 | ||
07ce4064 FR |
4056 | static void rtl_hw_start_8168(struct net_device *dev) |
4057 | { | |
2dd99530 FR |
4058 | struct rtl8169_private *tp = netdev_priv(dev); |
4059 | void __iomem *ioaddr = tp->mmio_addr; | |
0e485150 | 4060 | struct pci_dev *pdev = tp->pci_dev; |
2dd99530 FR |
4061 | |
4062 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
4063 | ||
f0298f81 | 4064 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
2dd99530 | 4065 | |
6f0333b8 | 4066 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
2dd99530 | 4067 | |
0e485150 | 4068 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
2dd99530 FR |
4069 | |
4070 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
4071 | ||
0e485150 | 4072 | RTL_W16(IntrMitigate, 0x5151); |
2dd99530 | 4073 | |
0e485150 | 4074 | /* Work around for RxFIFO overflow. */ |
b5ba6d12 IV |
4075 | if (tp->mac_version == RTL_GIGA_MAC_VER_11 || |
4076 | tp->mac_version == RTL_GIGA_MAC_VER_22) { | |
0e485150 FR |
4077 | tp->intr_event |= RxFIFOOver | PCSTimeout; |
4078 | tp->intr_event &= ~RxOverflow; | |
4079 | } | |
4080 | ||
4081 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2dd99530 | 4082 | |
b8363901 FR |
4083 | rtl_set_rx_mode(dev); |
4084 | ||
4085 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
4086 | (InterFrameGap << TxInterFrameGapShift)); | |
2dd99530 FR |
4087 | |
4088 | RTL_R8(IntrMask); | |
4089 | ||
219a1e9d FR |
4090 | switch (tp->mac_version) { |
4091 | case RTL_GIGA_MAC_VER_11: | |
4092 | rtl_hw_start_8168bb(ioaddr, pdev); | |
4804b3b3 | 4093 | break; |
219a1e9d FR |
4094 | |
4095 | case RTL_GIGA_MAC_VER_12: | |
4096 | case RTL_GIGA_MAC_VER_17: | |
4097 | rtl_hw_start_8168bef(ioaddr, pdev); | |
4804b3b3 | 4098 | break; |
219a1e9d FR |
4099 | |
4100 | case RTL_GIGA_MAC_VER_18: | |
ef3386f0 | 4101 | rtl_hw_start_8168cp_1(ioaddr, pdev); |
4804b3b3 | 4102 | break; |
219a1e9d FR |
4103 | |
4104 | case RTL_GIGA_MAC_VER_19: | |
4105 | rtl_hw_start_8168c_1(ioaddr, pdev); | |
4804b3b3 | 4106 | break; |
219a1e9d FR |
4107 | |
4108 | case RTL_GIGA_MAC_VER_20: | |
4109 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
4804b3b3 | 4110 | break; |
219a1e9d | 4111 | |
197ff761 FR |
4112 | case RTL_GIGA_MAC_VER_21: |
4113 | rtl_hw_start_8168c_3(ioaddr, pdev); | |
4804b3b3 | 4114 | break; |
197ff761 | 4115 | |
6fb07058 FR |
4116 | case RTL_GIGA_MAC_VER_22: |
4117 | rtl_hw_start_8168c_4(ioaddr, pdev); | |
4804b3b3 | 4118 | break; |
6fb07058 | 4119 | |
ef3386f0 FR |
4120 | case RTL_GIGA_MAC_VER_23: |
4121 | rtl_hw_start_8168cp_2(ioaddr, pdev); | |
4804b3b3 | 4122 | break; |
ef3386f0 | 4123 | |
7f3e3d3a FR |
4124 | case RTL_GIGA_MAC_VER_24: |
4125 | rtl_hw_start_8168cp_3(ioaddr, pdev); | |
4804b3b3 | 4126 | break; |
7f3e3d3a | 4127 | |
5b538df9 | 4128 | case RTL_GIGA_MAC_VER_25: |
daf9df6d | 4129 | case RTL_GIGA_MAC_VER_26: |
4130 | case RTL_GIGA_MAC_VER_27: | |
5b538df9 | 4131 | rtl_hw_start_8168d(ioaddr, pdev); |
4804b3b3 | 4132 | break; |
5b538df9 | 4133 | |
e6de30d6 | 4134 | case RTL_GIGA_MAC_VER_28: |
4135 | rtl_hw_start_8168d_4(ioaddr, pdev); | |
4804b3b3 | 4136 | break; |
4137 | case RTL_GIGA_MAC_VER_31: | |
4138 | rtl_hw_start_8168dp(ioaddr, pdev); | |
4139 | break; | |
4140 | ||
01dc7fec | 4141 | case RTL_GIGA_MAC_VER_32: |
4142 | case RTL_GIGA_MAC_VER_33: | |
4143 | rtl_hw_start_8168e(ioaddr, pdev); | |
4144 | break; | |
e6de30d6 | 4145 | |
219a1e9d FR |
4146 | default: |
4147 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | |
4148 | dev->name, tp->mac_version); | |
4804b3b3 | 4149 | break; |
219a1e9d | 4150 | } |
2dd99530 | 4151 | |
0e485150 FR |
4152 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
4153 | ||
b8363901 FR |
4154 | RTL_W8(Cfg9346, Cfg9346_Lock); |
4155 | ||
2dd99530 | 4156 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
6dccd16b | 4157 | |
0e485150 | 4158 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 4159 | } |
1da177e4 | 4160 | |
2857ffb7 FR |
4161 | #define R810X_CPCMD_QUIRK_MASK (\ |
4162 | EnableBist | \ | |
4163 | Mac_dbgo_oe | \ | |
4164 | Force_half_dup | \ | |
5edcc537 | 4165 | Force_rxflow_en | \ |
2857ffb7 FR |
4166 | Force_txflow_en | \ |
4167 | Cxpl_dbg_sel | \ | |
4168 | ASF | \ | |
4169 | PktCntrDisable | \ | |
d24e9aaf | 4170 | Mac_dbgo_sel) |
2857ffb7 FR |
4171 | |
4172 | static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) | |
4173 | { | |
350f7596 | 4174 | static const struct ephy_info e_info_8102e_1[] = { |
2857ffb7 FR |
4175 | { 0x01, 0, 0x6e65 }, |
4176 | { 0x02, 0, 0x091f }, | |
4177 | { 0x03, 0, 0xc2f9 }, | |
4178 | { 0x06, 0, 0xafb5 }, | |
4179 | { 0x07, 0, 0x0e00 }, | |
4180 | { 0x19, 0, 0xec80 }, | |
4181 | { 0x01, 0, 0x2e65 }, | |
4182 | { 0x01, 0, 0x6e65 } | |
4183 | }; | |
4184 | u8 cfg1; | |
4185 | ||
650e8d5d | 4186 | rtl_csi_access_enable_2(ioaddr); |
2857ffb7 FR |
4187 | |
4188 | RTL_W8(DBG_REG, FIX_NAK_1); | |
4189 | ||
4190 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4191 | ||
4192 | RTL_W8(Config1, | |
4193 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); | |
4194 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
4195 | ||
4196 | cfg1 = RTL_R8(Config1); | |
4197 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) | |
4198 | RTL_W8(Config1, cfg1 & ~LEDS0); | |
4199 | ||
2857ffb7 FR |
4200 | rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); |
4201 | } | |
4202 | ||
4203 | static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
4204 | { | |
650e8d5d | 4205 | rtl_csi_access_enable_2(ioaddr); |
2857ffb7 FR |
4206 | |
4207 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
4208 | ||
4209 | RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); | |
4210 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2857ffb7 FR |
4211 | } |
4212 | ||
4213 | static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) | |
4214 | { | |
4215 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
4216 | ||
4217 | rtl_ephy_write(ioaddr, 0x03, 0xc2f9); | |
4218 | } | |
4219 | ||
5a5e4443 HW |
4220 | static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev) |
4221 | { | |
4222 | static const struct ephy_info e_info_8105e_1[] = { | |
4223 | { 0x07, 0, 0x4000 }, | |
4224 | { 0x19, 0, 0x0200 }, | |
4225 | { 0x19, 0, 0x0020 }, | |
4226 | { 0x1e, 0, 0x2000 }, | |
4227 | { 0x03, 0, 0x0001 }, | |
4228 | { 0x19, 0, 0x0100 }, | |
4229 | { 0x19, 0, 0x0004 }, | |
4230 | { 0x0a, 0, 0x0020 } | |
4231 | }; | |
4232 | ||
4233 | /* Force LAN exit from ASPM if Rx/Tx are not idel */ | |
4234 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800); | |
4235 | ||
4236 | /* disable Early Tally Counter */ | |
4237 | RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000); | |
4238 | ||
4239 | RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET); | |
4240 | RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH); | |
4241 | ||
4242 | rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1)); | |
4243 | } | |
4244 | ||
4245 | static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
4246 | { | |
4247 | rtl_hw_start_8105e_1(ioaddr, pdev); | |
4248 | rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000); | |
4249 | } | |
4250 | ||
07ce4064 FR |
4251 | static void rtl_hw_start_8101(struct net_device *dev) |
4252 | { | |
cdf1a608 FR |
4253 | struct rtl8169_private *tp = netdev_priv(dev); |
4254 | void __iomem *ioaddr = tp->mmio_addr; | |
4255 | struct pci_dev *pdev = tp->pci_dev; | |
4256 | ||
e3cf0cc0 FR |
4257 | if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
4258 | (tp->mac_version == RTL_GIGA_MAC_VER_16)) { | |
9c14ceaf FR |
4259 | int cap = tp->pcie_cap; |
4260 | ||
4261 | if (cap) { | |
4262 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, | |
4263 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
4264 | } | |
cdf1a608 FR |
4265 | } |
4266 | ||
d24e9aaf HW |
4267 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
4268 | ||
2857ffb7 FR |
4269 | switch (tp->mac_version) { |
4270 | case RTL_GIGA_MAC_VER_07: | |
4271 | rtl_hw_start_8102e_1(ioaddr, pdev); | |
4272 | break; | |
4273 | ||
4274 | case RTL_GIGA_MAC_VER_08: | |
4275 | rtl_hw_start_8102e_3(ioaddr, pdev); | |
4276 | break; | |
4277 | ||
4278 | case RTL_GIGA_MAC_VER_09: | |
4279 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
4280 | break; | |
5a5e4443 HW |
4281 | |
4282 | case RTL_GIGA_MAC_VER_29: | |
4283 | rtl_hw_start_8105e_1(ioaddr, pdev); | |
4284 | break; | |
4285 | case RTL_GIGA_MAC_VER_30: | |
4286 | rtl_hw_start_8105e_2(ioaddr, pdev); | |
4287 | break; | |
cdf1a608 FR |
4288 | } |
4289 | ||
d24e9aaf | 4290 | RTL_W8(Cfg9346, Cfg9346_Lock); |
cdf1a608 | 4291 | |
f0298f81 | 4292 | RTL_W8(MaxTxPacketSize, TxPacketMax); |
cdf1a608 | 4293 | |
6f0333b8 | 4294 | rtl_set_rx_max_size(ioaddr, rx_buf_sz); |
cdf1a608 | 4295 | |
d24e9aaf | 4296 | tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK; |
cdf1a608 FR |
4297 | RTL_W16(CPlusCmd, tp->cp_cmd); |
4298 | ||
4299 | RTL_W16(IntrMitigate, 0x0000); | |
4300 | ||
4301 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
4302 | ||
4303 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
4304 | rtl_set_rx_tx_config_registers(tp); | |
4305 | ||
cdf1a608 FR |
4306 | RTL_R8(IntrMask); |
4307 | ||
cdf1a608 FR |
4308 | rtl_set_rx_mode(dev); |
4309 | ||
4310 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); | |
6dccd16b | 4311 | |
0e485150 | 4312 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
4313 | } |
4314 | ||
4315 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
4316 | { | |
1da177e4 LT |
4317 | if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) |
4318 | return -EINVAL; | |
4319 | ||
4320 | dev->mtu = new_mtu; | |
323bb685 | 4321 | return 0; |
1da177e4 LT |
4322 | } |
4323 | ||
4324 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
4325 | { | |
95e0918d | 4326 | desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
1da177e4 LT |
4327 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
4328 | } | |
4329 | ||
6f0333b8 ED |
4330 | static void rtl8169_free_rx_databuff(struct rtl8169_private *tp, |
4331 | void **data_buff, struct RxDesc *desc) | |
1da177e4 | 4332 | { |
48addcc9 | 4333 | dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz, |
231aee63 | 4334 | DMA_FROM_DEVICE); |
48addcc9 | 4335 | |
6f0333b8 ED |
4336 | kfree(*data_buff); |
4337 | *data_buff = NULL; | |
1da177e4 LT |
4338 | rtl8169_make_unusable_by_asic(desc); |
4339 | } | |
4340 | ||
4341 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) | |
4342 | { | |
4343 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
4344 | ||
4345 | desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); | |
4346 | } | |
4347 | ||
4348 | static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, | |
4349 | u32 rx_buf_sz) | |
4350 | { | |
4351 | desc->addr = cpu_to_le64(mapping); | |
4352 | wmb(); | |
4353 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
4354 | } | |
4355 | ||
6f0333b8 ED |
4356 | static inline void *rtl8169_align(void *data) |
4357 | { | |
4358 | return (void *)ALIGN((long)data, 16); | |
4359 | } | |
4360 | ||
0ecbe1ca SG |
4361 | static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp, |
4362 | struct RxDesc *desc) | |
1da177e4 | 4363 | { |
6f0333b8 | 4364 | void *data; |
1da177e4 | 4365 | dma_addr_t mapping; |
48addcc9 | 4366 | struct device *d = &tp->pci_dev->dev; |
0ecbe1ca | 4367 | struct net_device *dev = tp->dev; |
6f0333b8 | 4368 | int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1; |
1da177e4 | 4369 | |
6f0333b8 ED |
4370 | data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node); |
4371 | if (!data) | |
4372 | return NULL; | |
e9f63f30 | 4373 | |
6f0333b8 ED |
4374 | if (rtl8169_align(data) != data) { |
4375 | kfree(data); | |
4376 | data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node); | |
4377 | if (!data) | |
4378 | return NULL; | |
4379 | } | |
3eafe507 | 4380 | |
48addcc9 | 4381 | mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz, |
231aee63 | 4382 | DMA_FROM_DEVICE); |
d827d86b SG |
4383 | if (unlikely(dma_mapping_error(d, mapping))) { |
4384 | if (net_ratelimit()) | |
4385 | netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n"); | |
3eafe507 | 4386 | goto err_out; |
d827d86b | 4387 | } |
1da177e4 LT |
4388 | |
4389 | rtl8169_map_to_asic(desc, mapping, rx_buf_sz); | |
6f0333b8 | 4390 | return data; |
3eafe507 SG |
4391 | |
4392 | err_out: | |
4393 | kfree(data); | |
4394 | return NULL; | |
1da177e4 LT |
4395 | } |
4396 | ||
4397 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
4398 | { | |
07d3f51f | 4399 | unsigned int i; |
1da177e4 LT |
4400 | |
4401 | for (i = 0; i < NUM_RX_DESC; i++) { | |
6f0333b8 ED |
4402 | if (tp->Rx_databuff[i]) { |
4403 | rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i, | |
1da177e4 LT |
4404 | tp->RxDescArray + i); |
4405 | } | |
4406 | } | |
4407 | } | |
4408 | ||
0ecbe1ca | 4409 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) |
1da177e4 | 4410 | { |
0ecbe1ca SG |
4411 | desc->opts1 |= cpu_to_le32(RingEnd); |
4412 | } | |
5b0384f4 | 4413 | |
0ecbe1ca SG |
4414 | static int rtl8169_rx_fill(struct rtl8169_private *tp) |
4415 | { | |
4416 | unsigned int i; | |
1da177e4 | 4417 | |
0ecbe1ca SG |
4418 | for (i = 0; i < NUM_RX_DESC; i++) { |
4419 | void *data; | |
4ae47c2d | 4420 | |
6f0333b8 | 4421 | if (tp->Rx_databuff[i]) |
1da177e4 | 4422 | continue; |
bcf0bf90 | 4423 | |
0ecbe1ca | 4424 | data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i); |
6f0333b8 ED |
4425 | if (!data) { |
4426 | rtl8169_make_unusable_by_asic(tp->RxDescArray + i); | |
0ecbe1ca | 4427 | goto err_out; |
6f0333b8 ED |
4428 | } |
4429 | tp->Rx_databuff[i] = data; | |
1da177e4 | 4430 | } |
1da177e4 | 4431 | |
0ecbe1ca SG |
4432 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); |
4433 | return 0; | |
4434 | ||
4435 | err_out: | |
4436 | rtl8169_rx_clear(tp); | |
4437 | return -ENOMEM; | |
1da177e4 LT |
4438 | } |
4439 | ||
4440 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) | |
4441 | { | |
4442 | tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; | |
4443 | } | |
4444 | ||
4445 | static int rtl8169_init_ring(struct net_device *dev) | |
4446 | { | |
4447 | struct rtl8169_private *tp = netdev_priv(dev); | |
4448 | ||
4449 | rtl8169_init_ring_indexes(tp); | |
4450 | ||
4451 | memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); | |
6f0333b8 | 4452 | memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *)); |
1da177e4 | 4453 | |
0ecbe1ca | 4454 | return rtl8169_rx_fill(tp); |
1da177e4 LT |
4455 | } |
4456 | ||
48addcc9 | 4457 | static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb, |
1da177e4 LT |
4458 | struct TxDesc *desc) |
4459 | { | |
4460 | unsigned int len = tx_skb->len; | |
4461 | ||
48addcc9 SG |
4462 | dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE); |
4463 | ||
1da177e4 LT |
4464 | desc->opts1 = 0x00; |
4465 | desc->opts2 = 0x00; | |
4466 | desc->addr = 0x00; | |
4467 | tx_skb->len = 0; | |
4468 | } | |
4469 | ||
3eafe507 SG |
4470 | static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start, |
4471 | unsigned int n) | |
1da177e4 LT |
4472 | { |
4473 | unsigned int i; | |
4474 | ||
3eafe507 SG |
4475 | for (i = 0; i < n; i++) { |
4476 | unsigned int entry = (start + i) % NUM_TX_DESC; | |
1da177e4 LT |
4477 | struct ring_info *tx_skb = tp->tx_skb + entry; |
4478 | unsigned int len = tx_skb->len; | |
4479 | ||
4480 | if (len) { | |
4481 | struct sk_buff *skb = tx_skb->skb; | |
4482 | ||
48addcc9 | 4483 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
1da177e4 LT |
4484 | tp->TxDescArray + entry); |
4485 | if (skb) { | |
cac4b22f | 4486 | tp->dev->stats.tx_dropped++; |
1da177e4 LT |
4487 | dev_kfree_skb(skb); |
4488 | tx_skb->skb = NULL; | |
4489 | } | |
1da177e4 LT |
4490 | } |
4491 | } | |
3eafe507 SG |
4492 | } |
4493 | ||
4494 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
4495 | { | |
4496 | rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC); | |
1da177e4 LT |
4497 | tp->cur_tx = tp->dirty_tx = 0; |
4498 | } | |
4499 | ||
c4028958 | 4500 | static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
1da177e4 LT |
4501 | { |
4502 | struct rtl8169_private *tp = netdev_priv(dev); | |
4503 | ||
c4028958 | 4504 | PREPARE_DELAYED_WORK(&tp->task, task); |
1da177e4 LT |
4505 | schedule_delayed_work(&tp->task, 4); |
4506 | } | |
4507 | ||
4508 | static void rtl8169_wait_for_quiescence(struct net_device *dev) | |
4509 | { | |
4510 | struct rtl8169_private *tp = netdev_priv(dev); | |
4511 | void __iomem *ioaddr = tp->mmio_addr; | |
4512 | ||
4513 | synchronize_irq(dev->irq); | |
4514 | ||
4515 | /* Wait for any pending NAPI task to complete */ | |
bea3348e | 4516 | napi_disable(&tp->napi); |
1da177e4 LT |
4517 | |
4518 | rtl8169_irq_mask_and_ack(ioaddr); | |
4519 | ||
d1d08d12 DM |
4520 | tp->intr_mask = 0xffff; |
4521 | RTL_W16(IntrMask, tp->intr_event); | |
bea3348e | 4522 | napi_enable(&tp->napi); |
1da177e4 LT |
4523 | } |
4524 | ||
c4028958 | 4525 | static void rtl8169_reinit_task(struct work_struct *work) |
1da177e4 | 4526 | { |
c4028958 DH |
4527 | struct rtl8169_private *tp = |
4528 | container_of(work, struct rtl8169_private, task.work); | |
4529 | struct net_device *dev = tp->dev; | |
1da177e4 LT |
4530 | int ret; |
4531 | ||
eb2a021c FR |
4532 | rtnl_lock(); |
4533 | ||
4534 | if (!netif_running(dev)) | |
4535 | goto out_unlock; | |
4536 | ||
4537 | rtl8169_wait_for_quiescence(dev); | |
4538 | rtl8169_close(dev); | |
1da177e4 LT |
4539 | |
4540 | ret = rtl8169_open(dev); | |
4541 | if (unlikely(ret < 0)) { | |
bf82c189 JP |
4542 | if (net_ratelimit()) |
4543 | netif_err(tp, drv, dev, | |
4544 | "reinit failure (status = %d). Rescheduling\n", | |
4545 | ret); | |
1da177e4 LT |
4546 | rtl8169_schedule_work(dev, rtl8169_reinit_task); |
4547 | } | |
eb2a021c FR |
4548 | |
4549 | out_unlock: | |
4550 | rtnl_unlock(); | |
1da177e4 LT |
4551 | } |
4552 | ||
c4028958 | 4553 | static void rtl8169_reset_task(struct work_struct *work) |
1da177e4 | 4554 | { |
c4028958 DH |
4555 | struct rtl8169_private *tp = |
4556 | container_of(work, struct rtl8169_private, task.work); | |
4557 | struct net_device *dev = tp->dev; | |
1da177e4 | 4558 | |
eb2a021c FR |
4559 | rtnl_lock(); |
4560 | ||
1da177e4 | 4561 | if (!netif_running(dev)) |
eb2a021c | 4562 | goto out_unlock; |
1da177e4 LT |
4563 | |
4564 | rtl8169_wait_for_quiescence(dev); | |
4565 | ||
bea3348e | 4566 | rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); |
1da177e4 LT |
4567 | rtl8169_tx_clear(tp); |
4568 | ||
4569 | if (tp->dirty_rx == tp->cur_rx) { | |
4570 | rtl8169_init_ring_indexes(tp); | |
07ce4064 | 4571 | rtl_hw_start(dev); |
1da177e4 | 4572 | netif_wake_queue(dev); |
cebf8cc7 | 4573 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
1da177e4 | 4574 | } else { |
bf82c189 JP |
4575 | if (net_ratelimit()) |
4576 | netif_emerg(tp, intr, dev, "Rx buffers shortage\n"); | |
1da177e4 LT |
4577 | rtl8169_schedule_work(dev, rtl8169_reset_task); |
4578 | } | |
eb2a021c FR |
4579 | |
4580 | out_unlock: | |
4581 | rtnl_unlock(); | |
1da177e4 LT |
4582 | } |
4583 | ||
4584 | static void rtl8169_tx_timeout(struct net_device *dev) | |
4585 | { | |
4586 | struct rtl8169_private *tp = netdev_priv(dev); | |
4587 | ||
e6de30d6 | 4588 | rtl8169_hw_reset(tp); |
1da177e4 LT |
4589 | |
4590 | /* Let's wait a bit while any (async) irq lands on */ | |
4591 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
4592 | } | |
4593 | ||
4594 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
4595 | u32 opts1) | |
4596 | { | |
4597 | struct skb_shared_info *info = skb_shinfo(skb); | |
4598 | unsigned int cur_frag, entry; | |
a6343afb | 4599 | struct TxDesc * uninitialized_var(txd); |
48addcc9 | 4600 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
4601 | |
4602 | entry = tp->cur_tx; | |
4603 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
4604 | skb_frag_t *frag = info->frags + cur_frag; | |
4605 | dma_addr_t mapping; | |
4606 | u32 status, len; | |
4607 | void *addr; | |
4608 | ||
4609 | entry = (entry + 1) % NUM_TX_DESC; | |
4610 | ||
4611 | txd = tp->TxDescArray + entry; | |
4612 | len = frag->size; | |
4613 | addr = ((void *) page_address(frag->page)) + frag->page_offset; | |
48addcc9 | 4614 | mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE); |
d827d86b SG |
4615 | if (unlikely(dma_mapping_error(d, mapping))) { |
4616 | if (net_ratelimit()) | |
4617 | netif_err(tp, drv, tp->dev, | |
4618 | "Failed to map TX fragments DMA!\n"); | |
3eafe507 | 4619 | goto err_out; |
d827d86b | 4620 | } |
1da177e4 LT |
4621 | |
4622 | /* anti gcc 2.95.3 bugware (sic) */ | |
4623 | status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
4624 | ||
4625 | txd->opts1 = cpu_to_le32(status); | |
4626 | txd->addr = cpu_to_le64(mapping); | |
4627 | ||
4628 | tp->tx_skb[entry].len = len; | |
4629 | } | |
4630 | ||
4631 | if (cur_frag) { | |
4632 | tp->tx_skb[entry].skb = skb; | |
4633 | txd->opts1 |= cpu_to_le32(LastFrag); | |
4634 | } | |
4635 | ||
4636 | return cur_frag; | |
3eafe507 SG |
4637 | |
4638 | err_out: | |
4639 | rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag); | |
4640 | return -EIO; | |
1da177e4 LT |
4641 | } |
4642 | ||
4643 | static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) | |
4644 | { | |
4645 | if (dev->features & NETIF_F_TSO) { | |
7967168c | 4646 | u32 mss = skb_shinfo(skb)->gso_size; |
1da177e4 LT |
4647 | |
4648 | if (mss) | |
4649 | return LargeSend | ((mss & MSSMask) << MSSShift); | |
4650 | } | |
84fa7933 | 4651 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 | 4652 | const struct iphdr *ip = ip_hdr(skb); |
1da177e4 LT |
4653 | |
4654 | if (ip->protocol == IPPROTO_TCP) | |
4655 | return IPCS | TCPCS; | |
4656 | else if (ip->protocol == IPPROTO_UDP) | |
4657 | return IPCS | UDPCS; | |
4658 | WARN_ON(1); /* we need a WARN() */ | |
4659 | } | |
4660 | return 0; | |
4661 | } | |
4662 | ||
61357325 SH |
4663 | static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb, |
4664 | struct net_device *dev) | |
1da177e4 LT |
4665 | { |
4666 | struct rtl8169_private *tp = netdev_priv(dev); | |
3eafe507 | 4667 | unsigned int entry = tp->cur_tx % NUM_TX_DESC; |
1da177e4 LT |
4668 | struct TxDesc *txd = tp->TxDescArray + entry; |
4669 | void __iomem *ioaddr = tp->mmio_addr; | |
48addcc9 | 4670 | struct device *d = &tp->pci_dev->dev; |
1da177e4 LT |
4671 | dma_addr_t mapping; |
4672 | u32 status, len; | |
4673 | u32 opts1; | |
3eafe507 | 4674 | int frags; |
5b0384f4 | 4675 | |
1da177e4 | 4676 | if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
bf82c189 | 4677 | netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n"); |
3eafe507 | 4678 | goto err_stop_0; |
1da177e4 LT |
4679 | } |
4680 | ||
4681 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
3eafe507 SG |
4682 | goto err_stop_0; |
4683 | ||
4684 | len = skb_headlen(skb); | |
48addcc9 | 4685 | mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE); |
d827d86b SG |
4686 | if (unlikely(dma_mapping_error(d, mapping))) { |
4687 | if (net_ratelimit()) | |
4688 | netif_err(tp, drv, dev, "Failed to map TX DMA!\n"); | |
3eafe507 | 4689 | goto err_dma_0; |
d827d86b | 4690 | } |
3eafe507 SG |
4691 | |
4692 | tp->tx_skb[entry].len = len; | |
4693 | txd->addr = cpu_to_le64(mapping); | |
4694 | txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); | |
1da177e4 LT |
4695 | |
4696 | opts1 = DescOwn | rtl8169_tso_csum(skb, dev); | |
4697 | ||
4698 | frags = rtl8169_xmit_frags(tp, skb, opts1); | |
3eafe507 SG |
4699 | if (frags < 0) |
4700 | goto err_dma_1; | |
4701 | else if (frags) | |
1da177e4 | 4702 | opts1 |= FirstFrag; |
3eafe507 | 4703 | else { |
1da177e4 LT |
4704 | opts1 |= FirstFrag | LastFrag; |
4705 | tp->tx_skb[entry].skb = skb; | |
4706 | } | |
4707 | ||
1da177e4 LT |
4708 | wmb(); |
4709 | ||
4710 | /* anti gcc 2.95.3 bugware (sic) */ | |
4711 | status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
4712 | txd->opts1 = cpu_to_le32(status); | |
4713 | ||
1da177e4 LT |
4714 | tp->cur_tx += frags + 1; |
4715 | ||
4c020a96 | 4716 | wmb(); |
1da177e4 | 4717 | |
275391a4 | 4718 | RTL_W8(TxPoll, NPQ); /* set polling bit */ |
1da177e4 LT |
4719 | |
4720 | if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { | |
4721 | netif_stop_queue(dev); | |
4722 | smp_rmb(); | |
4723 | if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) | |
4724 | netif_wake_queue(dev); | |
4725 | } | |
4726 | ||
61357325 | 4727 | return NETDEV_TX_OK; |
1da177e4 | 4728 | |
3eafe507 | 4729 | err_dma_1: |
48addcc9 | 4730 | rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd); |
3eafe507 SG |
4731 | err_dma_0: |
4732 | dev_kfree_skb(skb); | |
4733 | dev->stats.tx_dropped++; | |
4734 | return NETDEV_TX_OK; | |
4735 | ||
4736 | err_stop_0: | |
1da177e4 | 4737 | netif_stop_queue(dev); |
cebf8cc7 | 4738 | dev->stats.tx_dropped++; |
61357325 | 4739 | return NETDEV_TX_BUSY; |
1da177e4 LT |
4740 | } |
4741 | ||
4742 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
4743 | { | |
4744 | struct rtl8169_private *tp = netdev_priv(dev); | |
4745 | struct pci_dev *pdev = tp->pci_dev; | |
1da177e4 LT |
4746 | u16 pci_status, pci_cmd; |
4747 | ||
4748 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
4749 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
4750 | ||
bf82c189 JP |
4751 | netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n", |
4752 | pci_cmd, pci_status); | |
1da177e4 LT |
4753 | |
4754 | /* | |
4755 | * The recovery sequence below admits a very elaborated explanation: | |
4756 | * - it seems to work; | |
d03902b8 FR |
4757 | * - I did not see what else could be done; |
4758 | * - it makes iop3xx happy. | |
1da177e4 LT |
4759 | * |
4760 | * Feel free to adjust to your needs. | |
4761 | */ | |
a27993f3 | 4762 | if (pdev->broken_parity_status) |
d03902b8 FR |
4763 | pci_cmd &= ~PCI_COMMAND_PARITY; |
4764 | else | |
4765 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
4766 | ||
4767 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
4768 | |
4769 | pci_write_config_word(pdev, PCI_STATUS, | |
4770 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
4771 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
4772 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
4773 | ||
4774 | /* The infamous DAC f*ckup only happens at boot time */ | |
4775 | if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { | |
e6de30d6 | 4776 | void __iomem *ioaddr = tp->mmio_addr; |
4777 | ||
bf82c189 | 4778 | netif_info(tp, intr, dev, "disabling PCI DAC\n"); |
1da177e4 LT |
4779 | tp->cp_cmd &= ~PCIDAC; |
4780 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
4781 | dev->features &= ~NETIF_F_HIGHDMA; | |
1da177e4 LT |
4782 | } |
4783 | ||
e6de30d6 | 4784 | rtl8169_hw_reset(tp); |
d03902b8 FR |
4785 | |
4786 | rtl8169_schedule_work(dev, rtl8169_reinit_task); | |
1da177e4 LT |
4787 | } |
4788 | ||
07d3f51f FR |
4789 | static void rtl8169_tx_interrupt(struct net_device *dev, |
4790 | struct rtl8169_private *tp, | |
4791 | void __iomem *ioaddr) | |
1da177e4 LT |
4792 | { |
4793 | unsigned int dirty_tx, tx_left; | |
4794 | ||
1da177e4 LT |
4795 | dirty_tx = tp->dirty_tx; |
4796 | smp_rmb(); | |
4797 | tx_left = tp->cur_tx - dirty_tx; | |
4798 | ||
4799 | while (tx_left > 0) { | |
4800 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
4801 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
1da177e4 LT |
4802 | u32 status; |
4803 | ||
4804 | rmb(); | |
4805 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); | |
4806 | if (status & DescOwn) | |
4807 | break; | |
4808 | ||
48addcc9 SG |
4809 | rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb, |
4810 | tp->TxDescArray + entry); | |
1da177e4 | 4811 | if (status & LastFrag) { |
cac4b22f SG |
4812 | dev->stats.tx_packets++; |
4813 | dev->stats.tx_bytes += tx_skb->skb->len; | |
87433bfc | 4814 | dev_kfree_skb(tx_skb->skb); |
1da177e4 LT |
4815 | tx_skb->skb = NULL; |
4816 | } | |
4817 | dirty_tx++; | |
4818 | tx_left--; | |
4819 | } | |
4820 | ||
4821 | if (tp->dirty_tx != dirty_tx) { | |
4822 | tp->dirty_tx = dirty_tx; | |
4823 | smp_wmb(); | |
4824 | if (netif_queue_stopped(dev) && | |
4825 | (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { | |
4826 | netif_wake_queue(dev); | |
4827 | } | |
d78ae2dc FR |
4828 | /* |
4829 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
4830 | * too close. Let's kick an extra TxPoll request when a burst | |
4831 | * of start_xmit activity is detected (if it is not detected, | |
4832 | * it is slow enough). -- FR | |
4833 | */ | |
4834 | smp_rmb(); | |
4835 | if (tp->cur_tx != dirty_tx) | |
4836 | RTL_W8(TxPoll, NPQ); | |
1da177e4 LT |
4837 | } |
4838 | } | |
4839 | ||
126fa4b9 FR |
4840 | static inline int rtl8169_fragmented_frame(u32 status) |
4841 | { | |
4842 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
4843 | } | |
4844 | ||
adea1ac7 | 4845 | static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1) |
1da177e4 | 4846 | { |
1da177e4 LT |
4847 | u32 status = opts1 & RxProtoMask; |
4848 | ||
4849 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
d5d3ebe3 | 4850 | ((status == RxProtoUDP) && !(opts1 & UDPFail))) |
1da177e4 LT |
4851 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
4852 | else | |
bc8acf2c | 4853 | skb_checksum_none_assert(skb); |
1da177e4 LT |
4854 | } |
4855 | ||
6f0333b8 ED |
4856 | static struct sk_buff *rtl8169_try_rx_copy(void *data, |
4857 | struct rtl8169_private *tp, | |
4858 | int pkt_size, | |
4859 | dma_addr_t addr) | |
1da177e4 | 4860 | { |
b449655f | 4861 | struct sk_buff *skb; |
48addcc9 | 4862 | struct device *d = &tp->pci_dev->dev; |
b449655f | 4863 | |
6f0333b8 | 4864 | data = rtl8169_align(data); |
48addcc9 | 4865 | dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE); |
6f0333b8 ED |
4866 | prefetch(data); |
4867 | skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size); | |
4868 | if (skb) | |
4869 | memcpy(skb->data, data, pkt_size); | |
48addcc9 SG |
4870 | dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE); |
4871 | ||
6f0333b8 | 4872 | return skb; |
1da177e4 LT |
4873 | } |
4874 | ||
630b943c ED |
4875 | /* |
4876 | * Warning : rtl8169_rx_interrupt() might be called : | |
4877 | * 1) from NAPI (softirq) context | |
4878 | * (polling = 1 : we should call netif_receive_skb()) | |
4879 | * 2) from process context (rtl8169_reset_task()) | |
4880 | * (polling = 0 : we must call netif_rx() instead) | |
4881 | */ | |
07d3f51f FR |
4882 | static int rtl8169_rx_interrupt(struct net_device *dev, |
4883 | struct rtl8169_private *tp, | |
bea3348e | 4884 | void __iomem *ioaddr, u32 budget) |
1da177e4 LT |
4885 | { |
4886 | unsigned int cur_rx, rx_left; | |
6f0333b8 | 4887 | unsigned int count; |
630b943c | 4888 | int polling = (budget != ~(u32)0) ? 1 : 0; |
1da177e4 | 4889 | |
1da177e4 LT |
4890 | cur_rx = tp->cur_rx; |
4891 | rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; | |
865c652d | 4892 | rx_left = min(rx_left, budget); |
1da177e4 | 4893 | |
4dcb7d33 | 4894 | for (; rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 4895 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 4896 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
4897 | u32 status; |
4898 | ||
4899 | rmb(); | |
126fa4b9 | 4900 | status = le32_to_cpu(desc->opts1); |
1da177e4 LT |
4901 | |
4902 | if (status & DescOwn) | |
4903 | break; | |
4dcb7d33 | 4904 | if (unlikely(status & RxRES)) { |
bf82c189 JP |
4905 | netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n", |
4906 | status); | |
cebf8cc7 | 4907 | dev->stats.rx_errors++; |
1da177e4 | 4908 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 4909 | dev->stats.rx_length_errors++; |
1da177e4 | 4910 | if (status & RxCRC) |
cebf8cc7 | 4911 | dev->stats.rx_crc_errors++; |
9dccf611 FR |
4912 | if (status & RxFOVF) { |
4913 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
cebf8cc7 | 4914 | dev->stats.rx_fifo_errors++; |
9dccf611 | 4915 | } |
6f0333b8 | 4916 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
1da177e4 | 4917 | } else { |
6f0333b8 | 4918 | struct sk_buff *skb; |
b449655f | 4919 | dma_addr_t addr = le64_to_cpu(desc->addr); |
1da177e4 | 4920 | int pkt_size = (status & 0x00001FFF) - 4; |
1da177e4 | 4921 | |
126fa4b9 FR |
4922 | /* |
4923 | * The driver does not support incoming fragmented | |
4924 | * frames. They are seen as a symptom of over-mtu | |
4925 | * sized frames. | |
4926 | */ | |
4927 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
4928 | dev->stats.rx_dropped++; |
4929 | dev->stats.rx_length_errors++; | |
6f0333b8 | 4930 | rtl8169_mark_to_asic(desc, rx_buf_sz); |
4dcb7d33 | 4931 | continue; |
126fa4b9 FR |
4932 | } |
4933 | ||
6f0333b8 ED |
4934 | skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry], |
4935 | tp, pkt_size, addr); | |
4936 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
4937 | if (!skb) { | |
4938 | dev->stats.rx_dropped++; | |
4939 | continue; | |
1da177e4 LT |
4940 | } |
4941 | ||
adea1ac7 | 4942 | rtl8169_rx_csum(skb, status); |
1da177e4 LT |
4943 | skb_put(skb, pkt_size); |
4944 | skb->protocol = eth_type_trans(skb, dev); | |
4945 | ||
7a8fc77b FR |
4946 | rtl8169_rx_vlan_tag(desc, skb); |
4947 | ||
4948 | if (likely(polling)) | |
4949 | napi_gro_receive(&tp->napi, skb); | |
4950 | else | |
4951 | netif_rx(skb); | |
1da177e4 | 4952 | |
cebf8cc7 FR |
4953 | dev->stats.rx_bytes += pkt_size; |
4954 | dev->stats.rx_packets++; | |
1da177e4 | 4955 | } |
6dccd16b FR |
4956 | |
4957 | /* Work around for AMD plateform. */ | |
95e0918d | 4958 | if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
6dccd16b FR |
4959 | (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
4960 | desc->opts2 = 0; | |
4961 | cur_rx++; | |
4962 | } | |
1da177e4 LT |
4963 | } |
4964 | ||
4965 | count = cur_rx - tp->cur_rx; | |
4966 | tp->cur_rx = cur_rx; | |
4967 | ||
6f0333b8 | 4968 | tp->dirty_rx += count; |
1da177e4 LT |
4969 | |
4970 | return count; | |
4971 | } | |
4972 | ||
07d3f51f | 4973 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 4974 | { |
07d3f51f | 4975 | struct net_device *dev = dev_instance; |
1da177e4 | 4976 | struct rtl8169_private *tp = netdev_priv(dev); |
1da177e4 | 4977 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 4978 | int handled = 0; |
865c652d | 4979 | int status; |
1da177e4 | 4980 | |
f11a377b DD |
4981 | /* loop handling interrupts until we have no new ones or |
4982 | * we hit a invalid/hotplug case. | |
4983 | */ | |
865c652d | 4984 | status = RTL_R16(IntrStatus); |
f11a377b DD |
4985 | while (status && status != 0xffff) { |
4986 | handled = 1; | |
1da177e4 | 4987 | |
f11a377b DD |
4988 | /* Handle all of the error cases first. These will reset |
4989 | * the chip, so just exit the loop. | |
4990 | */ | |
4991 | if (unlikely(!netif_running(dev))) { | |
4992 | rtl8169_asic_down(ioaddr); | |
4993 | break; | |
4994 | } | |
1da177e4 | 4995 | |
1519e57f FR |
4996 | if (unlikely(status & RxFIFOOver)) { |
4997 | switch (tp->mac_version) { | |
4998 | /* Work around for rx fifo overflow */ | |
4999 | case RTL_GIGA_MAC_VER_11: | |
5000 | case RTL_GIGA_MAC_VER_22: | |
5001 | case RTL_GIGA_MAC_VER_26: | |
5002 | netif_stop_queue(dev); | |
5003 | rtl8169_tx_timeout(dev); | |
5004 | goto done; | |
f60ac8e7 FR |
5005 | /* Testers needed. */ |
5006 | case RTL_GIGA_MAC_VER_17: | |
5007 | case RTL_GIGA_MAC_VER_19: | |
5008 | case RTL_GIGA_MAC_VER_20: | |
5009 | case RTL_GIGA_MAC_VER_21: | |
5010 | case RTL_GIGA_MAC_VER_23: | |
5011 | case RTL_GIGA_MAC_VER_24: | |
5012 | case RTL_GIGA_MAC_VER_27: | |
5013 | case RTL_GIGA_MAC_VER_28: | |
4804b3b3 | 5014 | case RTL_GIGA_MAC_VER_31: |
1519e57f FR |
5015 | /* Experimental science. Pktgen proof. */ |
5016 | case RTL_GIGA_MAC_VER_12: | |
5017 | case RTL_GIGA_MAC_VER_25: | |
5018 | if (status == RxFIFOOver) | |
5019 | goto done; | |
5020 | break; | |
5021 | default: | |
5022 | break; | |
5023 | } | |
f11a377b | 5024 | } |
1da177e4 | 5025 | |
f11a377b DD |
5026 | if (unlikely(status & SYSErr)) { |
5027 | rtl8169_pcierr_interrupt(dev); | |
5028 | break; | |
5029 | } | |
1da177e4 | 5030 | |
f11a377b | 5031 | if (status & LinkChg) |
e4fbce74 | 5032 | __rtl8169_check_link_status(dev, tp, ioaddr, true); |
0e485150 | 5033 | |
f11a377b DD |
5034 | /* We need to see the lastest version of tp->intr_mask to |
5035 | * avoid ignoring an MSI interrupt and having to wait for | |
5036 | * another event which may never come. | |
5037 | */ | |
5038 | smp_rmb(); | |
5039 | if (status & tp->intr_mask & tp->napi_event) { | |
5040 | RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); | |
5041 | tp->intr_mask = ~tp->napi_event; | |
5042 | ||
5043 | if (likely(napi_schedule_prep(&tp->napi))) | |
5044 | __napi_schedule(&tp->napi); | |
bf82c189 JP |
5045 | else |
5046 | netif_info(tp, intr, dev, | |
5047 | "interrupt %04x in poll\n", status); | |
f11a377b | 5048 | } |
1da177e4 | 5049 | |
f11a377b DD |
5050 | /* We only get a new MSI interrupt when all active irq |
5051 | * sources on the chip have been acknowledged. So, ack | |
5052 | * everything we've seen and check if new sources have become | |
5053 | * active to avoid blocking all interrupts from the chip. | |
5054 | */ | |
5055 | RTL_W16(IntrStatus, | |
5056 | (status & RxFIFOOver) ? (status | RxOverflow) : status); | |
5057 | status = RTL_R16(IntrStatus); | |
865c652d | 5058 | } |
1519e57f | 5059 | done: |
1da177e4 LT |
5060 | return IRQ_RETVAL(handled); |
5061 | } | |
5062 | ||
bea3348e | 5063 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 5064 | { |
bea3348e SH |
5065 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
5066 | struct net_device *dev = tp->dev; | |
1da177e4 | 5067 | void __iomem *ioaddr = tp->mmio_addr; |
bea3348e | 5068 | int work_done; |
1da177e4 | 5069 | |
bea3348e | 5070 | work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
1da177e4 LT |
5071 | rtl8169_tx_interrupt(dev, tp, ioaddr); |
5072 | ||
bea3348e | 5073 | if (work_done < budget) { |
288379f0 | 5074 | napi_complete(napi); |
f11a377b DD |
5075 | |
5076 | /* We need for force the visibility of tp->intr_mask | |
5077 | * for other CPUs, as we can loose an MSI interrupt | |
5078 | * and potentially wait for a retransmit timeout if we don't. | |
5079 | * The posted write to IntrMask is safe, as it will | |
5080 | * eventually make it to the chip and we won't loose anything | |
5081 | * until it does. | |
1da177e4 | 5082 | */ |
f11a377b | 5083 | tp->intr_mask = 0xffff; |
4c020a96 | 5084 | wmb(); |
0e485150 | 5085 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
5086 | } |
5087 | ||
bea3348e | 5088 | return work_done; |
1da177e4 | 5089 | } |
1da177e4 | 5090 | |
523a6094 FR |
5091 | static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
5092 | { | |
5093 | struct rtl8169_private *tp = netdev_priv(dev); | |
5094 | ||
5095 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) | |
5096 | return; | |
5097 | ||
5098 | dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); | |
5099 | RTL_W32(RxMissed, 0); | |
5100 | } | |
5101 | ||
1da177e4 LT |
5102 | static void rtl8169_down(struct net_device *dev) |
5103 | { | |
5104 | struct rtl8169_private *tp = netdev_priv(dev); | |
5105 | void __iomem *ioaddr = tp->mmio_addr; | |
1da177e4 LT |
5106 | |
5107 | rtl8169_delete_timer(dev); | |
5108 | ||
5109 | netif_stop_queue(dev); | |
5110 | ||
93dd79e8 | 5111 | napi_disable(&tp->napi); |
93dd79e8 | 5112 | |
1da177e4 LT |
5113 | spin_lock_irq(&tp->lock); |
5114 | ||
5115 | rtl8169_asic_down(ioaddr); | |
323bb685 SG |
5116 | /* |
5117 | * At this point device interrupts can not be enabled in any function, | |
5118 | * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task, | |
5119 | * rtl8169_reinit_task) and napi is disabled (rtl8169_poll). | |
5120 | */ | |
523a6094 | 5121 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
5122 | |
5123 | spin_unlock_irq(&tp->lock); | |
5124 | ||
5125 | synchronize_irq(dev->irq); | |
5126 | ||
1da177e4 | 5127 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
fbd568a3 | 5128 | synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
1da177e4 | 5129 | |
1da177e4 LT |
5130 | rtl8169_tx_clear(tp); |
5131 | ||
5132 | rtl8169_rx_clear(tp); | |
065c27c1 | 5133 | |
5134 | rtl_pll_power_down(tp); | |
1da177e4 LT |
5135 | } |
5136 | ||
5137 | static int rtl8169_close(struct net_device *dev) | |
5138 | { | |
5139 | struct rtl8169_private *tp = netdev_priv(dev); | |
5140 | struct pci_dev *pdev = tp->pci_dev; | |
5141 | ||
e1759441 RW |
5142 | pm_runtime_get_sync(&pdev->dev); |
5143 | ||
355423d0 IV |
5144 | /* update counters before going down */ |
5145 | rtl8169_update_counters(dev); | |
5146 | ||
1da177e4 LT |
5147 | rtl8169_down(dev); |
5148 | ||
5149 | free_irq(dev->irq, dev); | |
5150 | ||
82553bb6 SG |
5151 | dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray, |
5152 | tp->RxPhyAddr); | |
5153 | dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
5154 | tp->TxPhyAddr); | |
1da177e4 LT |
5155 | tp->TxDescArray = NULL; |
5156 | tp->RxDescArray = NULL; | |
5157 | ||
e1759441 RW |
5158 | pm_runtime_put_sync(&pdev->dev); |
5159 | ||
1da177e4 LT |
5160 | return 0; |
5161 | } | |
5162 | ||
07ce4064 | 5163 | static void rtl_set_rx_mode(struct net_device *dev) |
1da177e4 LT |
5164 | { |
5165 | struct rtl8169_private *tp = netdev_priv(dev); | |
5166 | void __iomem *ioaddr = tp->mmio_addr; | |
5167 | unsigned long flags; | |
5168 | u32 mc_filter[2]; /* Multicast hash filter */ | |
07d3f51f | 5169 | int rx_mode; |
1da177e4 LT |
5170 | u32 tmp = 0; |
5171 | ||
5172 | if (dev->flags & IFF_PROMISC) { | |
5173 | /* Unconditionally log net taps. */ | |
bf82c189 | 5174 | netif_notice(tp, link, dev, "Promiscuous mode enabled\n"); |
1da177e4 LT |
5175 | rx_mode = |
5176 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
5177 | AcceptAllPhys; | |
5178 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
4cd24eaf | 5179 | } else if ((netdev_mc_count(dev) > multicast_filter_limit) || |
8e95a202 | 5180 | (dev->flags & IFF_ALLMULTI)) { |
1da177e4 LT |
5181 | /* Too many to filter perfectly -- accept all multicasts. */ |
5182 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
5183 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
5184 | } else { | |
22bedad3 | 5185 | struct netdev_hw_addr *ha; |
07d3f51f | 5186 | |
1da177e4 LT |
5187 | rx_mode = AcceptBroadcast | AcceptMyPhys; |
5188 | mc_filter[1] = mc_filter[0] = 0; | |
22bedad3 JP |
5189 | netdev_for_each_mc_addr(ha, dev) { |
5190 | int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; | |
1da177e4 LT |
5191 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); |
5192 | rx_mode |= AcceptMulticast; | |
5193 | } | |
5194 | } | |
5195 | ||
5196 | spin_lock_irqsave(&tp->lock, flags); | |
5197 | ||
5198 | tmp = rtl8169_rx_config | rx_mode | | |
5199 | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); | |
5200 | ||
f887cce8 | 5201 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
1087f4f4 FR |
5202 | u32 data = mc_filter[0]; |
5203 | ||
5204 | mc_filter[0] = swab32(mc_filter[1]); | |
5205 | mc_filter[1] = swab32(data); | |
bcf0bf90 FR |
5206 | } |
5207 | ||
1da177e4 | 5208 | RTL_W32(MAR0 + 4, mc_filter[1]); |
78f1cd02 | 5209 | RTL_W32(MAR0 + 0, mc_filter[0]); |
1da177e4 | 5210 | |
57a9f236 FR |
5211 | RTL_W32(RxConfig, tmp); |
5212 | ||
1da177e4 LT |
5213 | spin_unlock_irqrestore(&tp->lock, flags); |
5214 | } | |
5215 | ||
5216 | /** | |
5217 | * rtl8169_get_stats - Get rtl8169 read/write statistics | |
5218 | * @dev: The Ethernet Device to get statistics for | |
5219 | * | |
5220 | * Get TX/RX statistics for rtl8169 | |
5221 | */ | |
5222 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) | |
5223 | { | |
5224 | struct rtl8169_private *tp = netdev_priv(dev); | |
5225 | void __iomem *ioaddr = tp->mmio_addr; | |
5226 | unsigned long flags; | |
5227 | ||
5228 | if (netif_running(dev)) { | |
5229 | spin_lock_irqsave(&tp->lock, flags); | |
523a6094 | 5230 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
5231 | spin_unlock_irqrestore(&tp->lock, flags); |
5232 | } | |
5b0384f4 | 5233 | |
cebf8cc7 | 5234 | return &dev->stats; |
1da177e4 LT |
5235 | } |
5236 | ||
861ab440 | 5237 | static void rtl8169_net_suspend(struct net_device *dev) |
5d06a99f | 5238 | { |
065c27c1 | 5239 | struct rtl8169_private *tp = netdev_priv(dev); |
5240 | ||
5d06a99f | 5241 | if (!netif_running(dev)) |
861ab440 | 5242 | return; |
5d06a99f | 5243 | |
065c27c1 | 5244 | rtl_pll_power_down(tp); |
5245 | ||
5d06a99f FR |
5246 | netif_device_detach(dev); |
5247 | netif_stop_queue(dev); | |
861ab440 RW |
5248 | } |
5249 | ||
5250 | #ifdef CONFIG_PM | |
5251 | ||
5252 | static int rtl8169_suspend(struct device *device) | |
5253 | { | |
5254 | struct pci_dev *pdev = to_pci_dev(device); | |
5255 | struct net_device *dev = pci_get_drvdata(pdev); | |
5d06a99f | 5256 | |
861ab440 | 5257 | rtl8169_net_suspend(dev); |
1371fa6d | 5258 | |
5d06a99f FR |
5259 | return 0; |
5260 | } | |
5261 | ||
e1759441 RW |
5262 | static void __rtl8169_resume(struct net_device *dev) |
5263 | { | |
065c27c1 | 5264 | struct rtl8169_private *tp = netdev_priv(dev); |
5265 | ||
e1759441 | 5266 | netif_device_attach(dev); |
065c27c1 | 5267 | |
5268 | rtl_pll_power_up(tp); | |
5269 | ||
e1759441 RW |
5270 | rtl8169_schedule_work(dev, rtl8169_reset_task); |
5271 | } | |
5272 | ||
861ab440 | 5273 | static int rtl8169_resume(struct device *device) |
5d06a99f | 5274 | { |
861ab440 | 5275 | struct pci_dev *pdev = to_pci_dev(device); |
5d06a99f | 5276 | struct net_device *dev = pci_get_drvdata(pdev); |
fccec10b SG |
5277 | struct rtl8169_private *tp = netdev_priv(dev); |
5278 | ||
5279 | rtl8169_init_phy(dev, tp); | |
5d06a99f | 5280 | |
e1759441 RW |
5281 | if (netif_running(dev)) |
5282 | __rtl8169_resume(dev); | |
5d06a99f | 5283 | |
e1759441 RW |
5284 | return 0; |
5285 | } | |
5286 | ||
5287 | static int rtl8169_runtime_suspend(struct device *device) | |
5288 | { | |
5289 | struct pci_dev *pdev = to_pci_dev(device); | |
5290 | struct net_device *dev = pci_get_drvdata(pdev); | |
5291 | struct rtl8169_private *tp = netdev_priv(dev); | |
5292 | ||
5293 | if (!tp->TxDescArray) | |
5294 | return 0; | |
5295 | ||
5296 | spin_lock_irq(&tp->lock); | |
5297 | tp->saved_wolopts = __rtl8169_get_wol(tp); | |
5298 | __rtl8169_set_wol(tp, WAKE_ANY); | |
5299 | spin_unlock_irq(&tp->lock); | |
5300 | ||
5301 | rtl8169_net_suspend(dev); | |
5302 | ||
5303 | return 0; | |
5304 | } | |
5305 | ||
5306 | static int rtl8169_runtime_resume(struct device *device) | |
5307 | { | |
5308 | struct pci_dev *pdev = to_pci_dev(device); | |
5309 | struct net_device *dev = pci_get_drvdata(pdev); | |
5310 | struct rtl8169_private *tp = netdev_priv(dev); | |
5311 | ||
5312 | if (!tp->TxDescArray) | |
5313 | return 0; | |
5314 | ||
5315 | spin_lock_irq(&tp->lock); | |
5316 | __rtl8169_set_wol(tp, tp->saved_wolopts); | |
5317 | tp->saved_wolopts = 0; | |
5318 | spin_unlock_irq(&tp->lock); | |
5319 | ||
fccec10b SG |
5320 | rtl8169_init_phy(dev, tp); |
5321 | ||
e1759441 | 5322 | __rtl8169_resume(dev); |
5d06a99f | 5323 | |
5d06a99f FR |
5324 | return 0; |
5325 | } | |
5326 | ||
e1759441 RW |
5327 | static int rtl8169_runtime_idle(struct device *device) |
5328 | { | |
5329 | struct pci_dev *pdev = to_pci_dev(device); | |
5330 | struct net_device *dev = pci_get_drvdata(pdev); | |
5331 | struct rtl8169_private *tp = netdev_priv(dev); | |
5332 | ||
e4fbce74 | 5333 | return tp->TxDescArray ? -EBUSY : 0; |
e1759441 RW |
5334 | } |
5335 | ||
47145210 | 5336 | static const struct dev_pm_ops rtl8169_pm_ops = { |
861ab440 RW |
5337 | .suspend = rtl8169_suspend, |
5338 | .resume = rtl8169_resume, | |
5339 | .freeze = rtl8169_suspend, | |
5340 | .thaw = rtl8169_resume, | |
5341 | .poweroff = rtl8169_suspend, | |
5342 | .restore = rtl8169_resume, | |
e1759441 RW |
5343 | .runtime_suspend = rtl8169_runtime_suspend, |
5344 | .runtime_resume = rtl8169_runtime_resume, | |
5345 | .runtime_idle = rtl8169_runtime_idle, | |
861ab440 RW |
5346 | }; |
5347 | ||
5348 | #define RTL8169_PM_OPS (&rtl8169_pm_ops) | |
5349 | ||
5350 | #else /* !CONFIG_PM */ | |
5351 | ||
5352 | #define RTL8169_PM_OPS NULL | |
5353 | ||
5354 | #endif /* !CONFIG_PM */ | |
5355 | ||
1765f95d FR |
5356 | static void rtl_shutdown(struct pci_dev *pdev) |
5357 | { | |
861ab440 | 5358 | struct net_device *dev = pci_get_drvdata(pdev); |
4bb3f522 | 5359 | struct rtl8169_private *tp = netdev_priv(dev); |
5360 | void __iomem *ioaddr = tp->mmio_addr; | |
861ab440 RW |
5361 | |
5362 | rtl8169_net_suspend(dev); | |
1765f95d | 5363 | |
cc098dc7 IV |
5364 | /* restore original MAC address */ |
5365 | rtl_rar_set(tp, dev->perm_addr); | |
5366 | ||
4bb3f522 | 5367 | spin_lock_irq(&tp->lock); |
5368 | ||
5369 | rtl8169_asic_down(ioaddr); | |
5370 | ||
5371 | spin_unlock_irq(&tp->lock); | |
5372 | ||
861ab440 | 5373 | if (system_state == SYSTEM_POWER_OFF) { |
ca52efd5 | 5374 | /* WoL fails with some 8168 when the receiver is disabled. */ |
5375 | if (tp->features & RTL_FEATURE_WOL) { | |
5376 | pci_clear_master(pdev); | |
5377 | ||
5378 | RTL_W8(ChipCmd, CmdRxEnb); | |
5379 | /* PCI commit */ | |
5380 | RTL_R8(ChipCmd); | |
5381 | } | |
5382 | ||
861ab440 RW |
5383 | pci_wake_from_d3(pdev, true); |
5384 | pci_set_power_state(pdev, PCI_D3hot); | |
5385 | } | |
5386 | } | |
5d06a99f | 5387 | |
1da177e4 LT |
5388 | static struct pci_driver rtl8169_pci_driver = { |
5389 | .name = MODULENAME, | |
5390 | .id_table = rtl8169_pci_tbl, | |
5391 | .probe = rtl8169_init_one, | |
5392 | .remove = __devexit_p(rtl8169_remove_one), | |
1765f95d | 5393 | .shutdown = rtl_shutdown, |
861ab440 | 5394 | .driver.pm = RTL8169_PM_OPS, |
1da177e4 LT |
5395 | }; |
5396 | ||
07d3f51f | 5397 | static int __init rtl8169_init_module(void) |
1da177e4 | 5398 | { |
29917620 | 5399 | return pci_register_driver(&rtl8169_pci_driver); |
1da177e4 LT |
5400 | } |
5401 | ||
07d3f51f | 5402 | static void __exit rtl8169_cleanup_module(void) |
1da177e4 LT |
5403 | { |
5404 | pci_unregister_driver(&rtl8169_pci_driver); | |
5405 | } | |
5406 | ||
5407 | module_init(rtl8169_init_module); | |
5408 | module_exit(rtl8169_cleanup_module); |