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r8169: use pci_find_capability for the PCI-E features
[mirror_ubuntu-focal-kernel.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__FUNCTION__,__LINE__); \
40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 55static const int max_interrupt_work = 20;
1da177e4
LT		 56
57/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 59static const int multicast_filter_limit = 32;
1da177e4
LT		 60
61/* MAC address length */
62#define MAC_ADDR_LEN 6
63
9c14ceaf 64#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 65#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 68#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 69#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
ba6eb6ee
FR		 93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530 99 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 100 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
101 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
102 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
103 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
104 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
105 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
106 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
107 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
108 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
1da177e4
LT		 109};
110
1da177e4
LT		 111#define _R(NAME,MAC,MASK) \
112 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
113
3c6bee1d 114static const struct {
1da177e4
LT		 115 const char *name;
116 u8 mac_version;
117 u32 RxConfigMask; /* Clears the bits supported by this chip */
118} rtl_chip_info[] = {
ba6eb6ee
FR		 119 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
120 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
121 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
122 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
123 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 124 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 125 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
126 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
127 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
128 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 129 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
130 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
131 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
132 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
133 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
134 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
1da177e4
LT		 135};
136#undef _R
137
bcf0bf90
FR		 138enum cfg_version {
139 RTL_CFG_0 = 0x00,
140 RTL_CFG_1,
141 RTL_CFG_2
142};
143
07ce4064
FR		 144static void rtl_hw_start_8169(struct net_device *);
145static void rtl_hw_start_8168(struct net_device *);
146static void rtl_hw_start_8101(struct net_device *);
147
1da177e4 148static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 149 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 150 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 151 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 152 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 153 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
154 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 155 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 156 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
157 { PCI_VENDOR_ID_LINKSYS, 0x1032,
158 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 159 { 0x0001, 0x8168,
160 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 161 {0,},
162};
163
164MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
165
166static int rx_copybreak = 200;
167static int use_dac;
b57b7e5a
SH		 168static struct {
169 u32 msg_enable;
170} debug = { -1 };
1da177e4 171
07d3f51f
FR		 172enum rtl_registers {
173 MAC0 = 0, /* Ethernet hardware address. */
773d2021 174 MAC4 = 4,
07d3f51f
FR		 175 MAR0 = 8, /* Multicast filter. */
176 CounterAddrLow = 0x10,
177 CounterAddrHigh = 0x14,
178 TxDescStartAddrLow = 0x20,
179 TxDescStartAddrHigh = 0x24,
180 TxHDescStartAddrLow = 0x28,
181 TxHDescStartAddrHigh = 0x2c,
182 FLASH = 0x30,
183 ERSR = 0x36,
184 ChipCmd = 0x37,
185 TxPoll = 0x38,
186 IntrMask = 0x3c,
187 IntrStatus = 0x3e,
188 TxConfig = 0x40,
189 RxConfig = 0x44,
190 RxMissed = 0x4c,
191 Cfg9346 = 0x50,
192 Config0 = 0x51,
193 Config1 = 0x52,
194 Config2 = 0x53,
195 Config3 = 0x54,
196 Config4 = 0x55,
197 Config5 = 0x56,
198 MultiIntr = 0x5c,
199 PHYAR = 0x60,
200 TBICSR = 0x64,
201 TBI_ANAR = 0x68,
202 TBI_LPAR = 0x6a,
203 PHYstatus = 0x6c,
204 RxMaxSize = 0xda,
205 CPlusCmd = 0xe0,
206 IntrMitigate = 0xe2,
207 RxDescAddrLow = 0xe4,
208 RxDescAddrHigh = 0xe8,
209 EarlyTxThres = 0xec,
210 FuncEvent = 0xf0,
211 FuncEventMask = 0xf4,
212 FuncPresetState = 0xf8,
213 FuncForceEvent = 0xfc,
1da177e4
LT		 214};
215
07d3f51f 216enum rtl_register_content {
1da177e4 217 /* InterruptStatusBits */
07d3f51f
FR		 218 SYSErr = 0x8000,
219 PCSTimeout = 0x4000,
220 SWInt = 0x0100,
221 TxDescUnavail = 0x0080,
222 RxFIFOOver = 0x0040,
223 LinkChg = 0x0020,
224 RxOverflow = 0x0010,
225 TxErr = 0x0008,
226 TxOK = 0x0004,
227 RxErr = 0x0002,
228 RxOK = 0x0001,
1da177e4
LT		 229
230 /* RxStatusDesc */
9dccf611
FR		 231 RxFOVF = (1 << 23),
232 RxRWT = (1 << 22),
233 RxRES = (1 << 21),
234 RxRUNT = (1 << 20),
235 RxCRC = (1 << 19),
1da177e4
LT		 236
237 /* ChipCmdBits */
07d3f51f
FR		 238 CmdReset = 0x10,
239 CmdRxEnb = 0x08,
240 CmdTxEnb = 0x04,
241 RxBufEmpty = 0x01,
1da177e4 242
275391a4
FR		 243 /* TXPoll register p.5 */
244 HPQ = 0x80, /* Poll cmd on the high prio queue */
245 NPQ = 0x40, /* Poll cmd on the low prio queue */
246 FSWInt = 0x01, /* Forced software interrupt */
247
1da177e4 248 /* Cfg9346Bits */
07d3f51f
FR		 249 Cfg9346_Lock = 0x00,
250 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 251
252 /* rx_mode_bits */
07d3f51f
FR		 253 AcceptErr = 0x20,
254 AcceptRunt = 0x10,
255 AcceptBroadcast = 0x08,
256 AcceptMulticast = 0x04,
257 AcceptMyPhys = 0x02,
258 AcceptAllPhys = 0x01,
1da177e4
LT		 259
260 /* RxConfigBits */
07d3f51f
FR		 261 RxCfgFIFOShift = 13,
262 RxCfgDMAShift = 8,
1da177e4
LT		 263
264 /* TxConfigBits */
265 TxInterFrameGapShift = 24,
266 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
267
5d06a99f 268 /* Config1 register p.24 */
fbac58fc 269 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
5d06a99f
FR		 270 PMEnable = (1 << 0), /* Power Management Enable */
271
6dccd16b
FR		 272 /* Config2 register p. 25 */
273 PCI_Clock_66MHz = 0x01,
274 PCI_Clock_33MHz = 0x00,
275
61a4dcc2
FR		 276 /* Config3 register p.25 */
277 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
278 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
279
5d06a99f 280 /* Config5 register p.27 */
61a4dcc2
FR		 281 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
282 MWF = (1 << 5), /* Accept Multicast wakeup frame */
283 UWF = (1 << 4), /* Accept Unicast wakeup frame */
284 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 285 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
286
1da177e4
LT		 287 /* TBICSR p.28 */
288 TBIReset = 0x80000000,
289 TBILoopback = 0x40000000,
290 TBINwEnable = 0x20000000,
291 TBINwRestart = 0x10000000,
292 TBILinkOk = 0x02000000,
293 TBINwComplete = 0x01000000,
294
295 /* CPlusCmd p.31 */
0e485150 296 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 297 RxVlan = (1 << 6),
298 RxChkSum = (1 << 5),
299 PCIDAC = (1 << 4),
300 PCIMulRW = (1 << 3),
0e485150
FR		 301 INTT_0 = 0x0000, // 8168
302 INTT_1 = 0x0001, // 8168
303 INTT_2 = 0x0002, // 8168
304 INTT_3 = 0x0003, // 8168
1da177e4
LT		 305
306 /* rtl8169_PHYstatus */
07d3f51f
FR		 307 TBI_Enable = 0x80,
308 TxFlowCtrl = 0x40,
309 RxFlowCtrl = 0x20,
310 _1000bpsF = 0x10,
311 _100bps = 0x08,
312 _10bps = 0x04,
313 LinkStatus = 0x02,
314 FullDup = 0x01,
1da177e4 315
1da177e4 316 /* _TBICSRBit */
07d3f51f 317 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 318
319 /* DumpCounterCommand */
07d3f51f 320 CounterDump = 0x8,
1da177e4
LT		 321};
322
07d3f51f 323enum desc_status_bit {
1da177e4
LT		 324 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
325 RingEnd = (1 << 30), /* End of descriptor ring */
326 FirstFrag = (1 << 29), /* First segment of a packet */
327 LastFrag = (1 << 28), /* Final segment of a packet */
328
329 /* Tx private */
330 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
331 MSSShift = 16, /* MSS value position */
332 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
333 IPCS = (1 << 18), /* Calculate IP checksum */
334 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
335 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
336 TxVlanTag = (1 << 17), /* Add VLAN tag */
337
338 /* Rx private */
339 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
340 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
341
342#define RxProtoUDP (PID1)
343#define RxProtoTCP (PID0)
344#define RxProtoIP (PID1 | PID0)
345#define RxProtoMask RxProtoIP
346
347 IPFail = (1 << 16), /* IP checksum failed */
348 UDPFail = (1 << 15), /* UDP/IP checksum failed */
349 TCPFail = (1 << 14), /* TCP/IP checksum failed */
350 RxVlanTag = (1 << 16), /* VLAN tag available */
351};
352
353#define RsvdMask 0x3fffc000
354
355struct TxDesc {
6cccd6e7
REB		 356 __le32 opts1;
357 __le32 opts2;
358 __le64 addr;
1da177e4
LT		 359};
360
361struct RxDesc {
6cccd6e7
REB		 362 __le32 opts1;
363 __le32 opts2;
364 __le64 addr;
1da177e4
LT		 365};
366
367struct ring_info {
368 struct sk_buff *skb;
369 u32 len;
370 u8 __pad[sizeof(void *) - sizeof(u32)];
371};
372
f23e7fda 373enum features {
ccdffb9a
FR		 374 RTL_FEATURE_WOL = (1 << 0),
375 RTL_FEATURE_MSI = (1 << 1),
376 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 377};
378
1da177e4
LT		 379struct rtl8169_private {
380 void __iomem *mmio_addr; /* memory map physical address */
381 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 382 struct net_device *dev;
bea3348e 383 struct napi_struct napi;
1da177e4 384 spinlock_t lock; /* spin lock flag */
b57b7e5a 385 u32 msg_enable;
1da177e4
LT		 386 int chipset;
387 int mac_version;
1da177e4
LT		 388 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
389 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
390 u32 dirty_rx;
391 u32 dirty_tx;
392 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
393 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
394 dma_addr_t TxPhyAddr;
395 dma_addr_t RxPhyAddr;
396 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
397 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 398 unsigned align;
1da177e4
LT		 399 unsigned rx_buf_sz;
400 struct timer_list timer;
401 u16 cp_cmd;
0e485150
FR		 402 u16 intr_event;
403 u16 napi_event;
1da177e4
LT		 404 u16 intr_mask;
405 int phy_auto_nego_reg;
406 int phy_1000_ctrl_reg;
407#ifdef CONFIG_R8169_VLAN
408 struct vlan_group *vlgrp;
409#endif
410 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 411 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 412 void (*phy_reset_enable)(void __iomem *);
07ce4064 413 void (*hw_start)(struct net_device *);
1da177e4
LT		 414 unsigned int (*phy_reset_pending)(void __iomem *);
415 unsigned int (*link_ok)(void __iomem *);
9c14ceaf 416 int pcie_cap;
c4028958 417 struct delayed_work task;
f23e7fda 418 unsigned features;
ccdffb9a
FR		 419
420 struct mii_if_info mii;
1da177e4
LT		 421};
422
979b6c13 423MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 424MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 425module_param(rx_copybreak, int, 0);
1b7efd58 426MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 427module_param(use_dac, int, 0);
428MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 429module_param_named(debug, debug.msg_enable, int, 0);
430MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 431MODULE_LICENSE("GPL");
432MODULE_VERSION(RTL8169_VERSION);
433
434static int rtl8169_open(struct net_device *dev);
435static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 436static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 437static int rtl8169_init_ring(struct net_device *dev);
07ce4064 438static void rtl_hw_start(struct net_device *dev);
1da177e4 439static int rtl8169_close(struct net_device *dev);
07ce4064 440static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 441static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 442static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 443static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 444 void __iomem *, u32 budget);
4dcb7d33 445static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 446static void rtl8169_down(struct net_device *dev);
99f252b0 447static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 448static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 449
1da177e4 450static const unsigned int rtl8169_rx_config =
5b0384f4 451 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 452
07d3f51f 453static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 454{
455 int i;
456
a6baf3af 457 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 458
2371408c 459 for (i = 20; i > 0; i--) {
07d3f51f
FR		 460 /*
461 * Check if the RTL8169 has completed writing to the specified
462 * MII register.
463 */
5b0384f4 464 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 465 break;
2371408c 466 udelay(25);
1da177e4
LT		 467 }
468}
469
07d3f51f 470static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 471{
472 int i, value = -1;
473
a6baf3af 474 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 475
2371408c 476 for (i = 20; i > 0; i--) {
07d3f51f
FR		 477 /*
478 * Check if the RTL8169 has completed retrieving data from
479 * the specified MII register.
480 */
1da177e4 481 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 482 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 483 break;
484 }
2371408c 485 udelay(25);
1da177e4
LT		 486 }
487 return value;
488}
489
ccdffb9a
FR		 490static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
491 int val)
492{
493 struct rtl8169_private *tp = netdev_priv(dev);
494 void __iomem *ioaddr = tp->mmio_addr;
495
496 mdio_write(ioaddr, location, val);
497}
498
499static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
500{
501 struct rtl8169_private *tp = netdev_priv(dev);
502 void __iomem *ioaddr = tp->mmio_addr;
503
504 return mdio_read(ioaddr, location);
505}
506
1da177e4
LT		 507static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
508{
509 RTL_W16(IntrMask, 0x0000);
510
511 RTL_W16(IntrStatus, 0xffff);
512}
513
514static void rtl8169_asic_down(void __iomem *ioaddr)
515{
516 RTL_W8(ChipCmd, 0x00);
517 rtl8169_irq_mask_and_ack(ioaddr);
518 RTL_R16(CPlusCmd);
519}
520
521static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
522{
523 return RTL_R32(TBICSR) & TBIReset;
524}
525
526static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
527{
64e4bfb4 528 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 529}
530
531static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
532{
533 return RTL_R32(TBICSR) & TBILinkOk;
534}
535
536static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
537{
538 return RTL_R8(PHYstatus) & LinkStatus;
539}
540
541static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
542{
543 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
544}
545
546static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
547{
548 unsigned int val;
549
9e0db8ef
FR		 550 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
551 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 552}
553
554static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 555 struct rtl8169_private *tp,
556 void __iomem *ioaddr)
1da177e4
LT		 557{
558 unsigned long flags;
559
560 spin_lock_irqsave(&tp->lock, flags);
561 if (tp->link_ok(ioaddr)) {
562 netif_carrier_on(dev);
b57b7e5a
SH		 563 if (netif_msg_ifup(tp))
564 printk(KERN_INFO PFX "%s: link up\n", dev->name);
565 } else {
566 if (netif_msg_ifdown(tp))
567 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 568 netif_carrier_off(dev);
b57b7e5a 569 }
1da177e4
LT		 570 spin_unlock_irqrestore(&tp->lock, flags);
571}
572
61a4dcc2
FR		 573static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
574{
575 struct rtl8169_private *tp = netdev_priv(dev);
576 void __iomem *ioaddr = tp->mmio_addr;
577 u8 options;
578
579 wol->wolopts = 0;
580
581#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
582 wol->supported = WAKE_ANY;
583
584 spin_lock_irq(&tp->lock);
585
586 options = RTL_R8(Config1);
587 if (!(options & PMEnable))
588 goto out_unlock;
589
590 options = RTL_R8(Config3);
591 if (options & LinkUp)
592 wol->wolopts |= WAKE_PHY;
593 if (options & MagicPacket)
594 wol->wolopts |= WAKE_MAGIC;
595
596 options = RTL_R8(Config5);
597 if (options & UWF)
598 wol->wolopts |= WAKE_UCAST;
599 if (options & BWF)
5b0384f4 600 wol->wolopts |= WAKE_BCAST;
61a4dcc2 601 if (options & MWF)
5b0384f4 602 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 603
604out_unlock:
605 spin_unlock_irq(&tp->lock);
606}
607
608static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
609{
610 struct rtl8169_private *tp = netdev_priv(dev);
611 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 612 unsigned int i;
61a4dcc2
FR		 613 static struct {
614 u32 opt;
615 u16 reg;
616 u8 mask;
617 } cfg[] = {
618 { WAKE_ANY, Config1, PMEnable },
619 { WAKE_PHY, Config3, LinkUp },
620 { WAKE_MAGIC, Config3, MagicPacket },
621 { WAKE_UCAST, Config5, UWF },
622 { WAKE_BCAST, Config5, BWF },
623 { WAKE_MCAST, Config5, MWF },
624 { WAKE_ANY, Config5, LanWake }
625 };
626
627 spin_lock_irq(&tp->lock);
628
629 RTL_W8(Cfg9346, Cfg9346_Unlock);
630
631 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
632 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
633 if (wol->wolopts & cfg[i].opt)
634 options |= cfg[i].mask;
635 RTL_W8(cfg[i].reg, options);
636 }
637
638 RTL_W8(Cfg9346, Cfg9346_Lock);
639
f23e7fda
FR		 640 if (wol->wolopts)
641 tp->features |= RTL_FEATURE_WOL;
642 else
643 tp->features &= ~RTL_FEATURE_WOL;
61a4dcc2
FR		 644
645 spin_unlock_irq(&tp->lock);
646
647 return 0;
648}
649
1da177e4
LT		 650static void rtl8169_get_drvinfo(struct net_device *dev,
651 struct ethtool_drvinfo *info)
652{
653 struct rtl8169_private *tp = netdev_priv(dev);
654
655 strcpy(info->driver, MODULENAME);
656 strcpy(info->version, RTL8169_VERSION);
657 strcpy(info->bus_info, pci_name(tp->pci_dev));
658}
659
660static int rtl8169_get_regs_len(struct net_device *dev)
661{
662 return R8169_REGS_SIZE;
663}
664
665static int rtl8169_set_speed_tbi(struct net_device *dev,
666 u8 autoneg, u16 speed, u8 duplex)
667{
668 struct rtl8169_private *tp = netdev_priv(dev);
669 void __iomem *ioaddr = tp->mmio_addr;
670 int ret = 0;
671 u32 reg;
672
673 reg = RTL_R32(TBICSR);
674 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
675 (duplex == DUPLEX_FULL)) {
676 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
677 } else if (autoneg == AUTONEG_ENABLE)
678 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
679 else {
b57b7e5a
SH		 680 if (netif_msg_link(tp)) {
681 printk(KERN_WARNING "%s: "
682 "incorrect speed setting refused in TBI mode\n",
683 dev->name);
684 }
1da177e4
LT		 685 ret = -EOPNOTSUPP;
686 }
687
688 return ret;
689}
690
691static int rtl8169_set_speed_xmii(struct net_device *dev,
692 u8 autoneg, u16 speed, u8 duplex)
693{
694 struct rtl8169_private *tp = netdev_priv(dev);
695 void __iomem *ioaddr = tp->mmio_addr;
696 int auto_nego, giga_ctrl;
697
64e4bfb4
FR		 698 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
699 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
700 ADVERTISE_100HALF | ADVERTISE_100FULL);
701 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
702 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 703
704 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 705 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
706 ADVERTISE_100HALF | ADVERTISE_100FULL);
707 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 708 } else {
709 if (speed == SPEED_10)
64e4bfb4 710 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 711 else if (speed == SPEED_100)
64e4bfb4 712 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 713 else if (speed == SPEED_1000)
64e4bfb4 714 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 715
716 if (duplex == DUPLEX_HALF)
64e4bfb4 717 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 718
719 if (duplex == DUPLEX_FULL)
64e4bfb4 720 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 721
722 /* This tweak comes straight from Realtek's driver. */
723 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 724 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
725 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 726 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 727 }
728 }
729
730 /* The 8100e/8101e do Fast Ethernet only. */
731 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
732 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 733 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
734 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 735 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 736 netif_msg_link(tp)) {
737 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
738 dev->name);
739 }
64e4bfb4 740 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 741 }
742
623a1593
FR		 743 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
744
e3cf0cc0
FR		 745 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
746 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
2584fbc3
RS		 747 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
748 mdio_write(ioaddr, 0x1f, 0x0000);
749 mdio_write(ioaddr, 0x0e, 0x0000);
750 }
751
1da177e4
LT		 752 tp->phy_auto_nego_reg = auto_nego;
753 tp->phy_1000_ctrl_reg = giga_ctrl;
754
64e4bfb4
FR		 755 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
756 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
757 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 758 return 0;
759}
760
761static int rtl8169_set_speed(struct net_device *dev,
762 u8 autoneg, u16 speed, u8 duplex)
763{
764 struct rtl8169_private *tp = netdev_priv(dev);
765 int ret;
766
767 ret = tp->set_speed(dev, autoneg, speed, duplex);
768
64e4bfb4 769 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 770 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
771
772 return ret;
773}
774
775static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
776{
777 struct rtl8169_private *tp = netdev_priv(dev);
778 unsigned long flags;
779 int ret;
780
781 spin_lock_irqsave(&tp->lock, flags);
782 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
783 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 784
1da177e4
LT		 785 return ret;
786}
787
788static u32 rtl8169_get_rx_csum(struct net_device *dev)
789{
790 struct rtl8169_private *tp = netdev_priv(dev);
791
792 return tp->cp_cmd & RxChkSum;
793}
794
795static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
796{
797 struct rtl8169_private *tp = netdev_priv(dev);
798 void __iomem *ioaddr = tp->mmio_addr;
799 unsigned long flags;
800
801 spin_lock_irqsave(&tp->lock, flags);
802
803 if (data)
804 tp->cp_cmd |= RxChkSum;
805 else
806 tp->cp_cmd &= ~RxChkSum;
807
808 RTL_W16(CPlusCmd, tp->cp_cmd);
809 RTL_R16(CPlusCmd);
810
811 spin_unlock_irqrestore(&tp->lock, flags);
812
813 return 0;
814}
815
816#ifdef CONFIG_R8169_VLAN
817
818static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
819 struct sk_buff *skb)
820{
821 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
822 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
823}
824
825static void rtl8169_vlan_rx_register(struct net_device *dev,
826 struct vlan_group *grp)
827{
828 struct rtl8169_private *tp = netdev_priv(dev);
829 void __iomem *ioaddr = tp->mmio_addr;
830 unsigned long flags;
831
832 spin_lock_irqsave(&tp->lock, flags);
833 tp->vlgrp = grp;
834 if (tp->vlgrp)
835 tp->cp_cmd |= RxVlan;
836 else
837 tp->cp_cmd &= ~RxVlan;
838 RTL_W16(CPlusCmd, tp->cp_cmd);
839 RTL_R16(CPlusCmd);
840 spin_unlock_irqrestore(&tp->lock, flags);
841}
842
1da177e4
LT		 843static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
844 struct sk_buff *skb)
845{
846 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 847 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 848 int ret;
849
865c652d
FR		 850 if (vlgrp && (opts2 & RxVlanTag)) {
851 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 852 ret = 0;
853 } else
854 ret = -1;
855 desc->opts2 = 0;
856 return ret;
857}
858
859#else /* !CONFIG_R8169_VLAN */
860
861static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
862 struct sk_buff *skb)
863{
864 return 0;
865}
866
867static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
868 struct sk_buff *skb)
869{
870 return -1;
871}
872
873#endif
874
ccdffb9a 875static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 876{
877 struct rtl8169_private *tp = netdev_priv(dev);
878 void __iomem *ioaddr = tp->mmio_addr;
879 u32 status;
880
881 cmd->supported =
882 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
883 cmd->port = PORT_FIBRE;
884 cmd->transceiver = XCVR_INTERNAL;
885
886 status = RTL_R32(TBICSR);
887 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
888 cmd->autoneg = !!(status & TBINwEnable);
889
890 cmd->speed = SPEED_1000;
891 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 892
893 return 0;
1da177e4
LT		 894}
895
ccdffb9a 896static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 897{
898 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 899
900 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 901}
902
903static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
904{
905 struct rtl8169_private *tp = netdev_priv(dev);
906 unsigned long flags;
ccdffb9a 907 int rc;
1da177e4
LT		 908
909 spin_lock_irqsave(&tp->lock, flags);
910
ccdffb9a 911 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 912
913 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 914 return rc;
1da177e4
LT		 915}
916
917static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
918 void *p)
919{
5b0384f4
FR		 920 struct rtl8169_private *tp = netdev_priv(dev);
921 unsigned long flags;
1da177e4 922
5b0384f4
FR		 923 if (regs->len > R8169_REGS_SIZE)
924 regs->len = R8169_REGS_SIZE;
1da177e4 925
5b0384f4
FR		 926 spin_lock_irqsave(&tp->lock, flags);
927 memcpy_fromio(p, tp->mmio_addr, regs->len);
928 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 929}
930
b57b7e5a
SH		 931static u32 rtl8169_get_msglevel(struct net_device *dev)
932{
933 struct rtl8169_private *tp = netdev_priv(dev);
934
935 return tp->msg_enable;
936}
937
938static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
939{
940 struct rtl8169_private *tp = netdev_priv(dev);
941
942 tp->msg_enable = value;
943}
944
d4a3a0fc
SH		 945static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
946 "tx_packets",
947 "rx_packets",
948 "tx_errors",
949 "rx_errors",
950 "rx_missed",
951 "align_errors",
952 "tx_single_collisions",
953 "tx_multi_collisions",
954 "unicast",
955 "broadcast",
956 "multicast",
957 "tx_aborted",
958 "tx_underrun",
959};
960
961struct rtl8169_counters {
b1eab701
AV		 962 __le64 tx_packets;
963 __le64 rx_packets;
964 __le64 tx_errors;
965 __le32 rx_errors;
966 __le16 rx_missed;
967 __le16 align_errors;
968 __le32 tx_one_collision;
969 __le32 tx_multi_collision;
970 __le64 rx_unicast;
971 __le64 rx_broadcast;
972 __le32 rx_multicast;
973 __le16 tx_aborted;
974 __le16 tx_underun;
d4a3a0fc
SH		 975};
976
b9f2c044 977static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 978{
b9f2c044
JG		 979 switch (sset) {
980 case ETH_SS_STATS:
981 return ARRAY_SIZE(rtl8169_gstrings);
982 default:
983 return -EOPNOTSUPP;
984 }
d4a3a0fc
SH		 985}
986
987static void rtl8169_get_ethtool_stats(struct net_device *dev,
988 struct ethtool_stats *stats, u64 *data)
989{
990 struct rtl8169_private *tp = netdev_priv(dev);
991 void __iomem *ioaddr = tp->mmio_addr;
992 struct rtl8169_counters *counters;
993 dma_addr_t paddr;
994 u32 cmd;
995
996 ASSERT_RTNL();
997
998 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
999 if (!counters)
1000 return;
1001
1002 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1003 cmd = (u64)paddr & DMA_32BIT_MASK;
1004 RTL_W32(CounterAddrLow, cmd);
1005 RTL_W32(CounterAddrLow, cmd | CounterDump);
1006
1007 while (RTL_R32(CounterAddrLow) & CounterDump) {
1008 if (msleep_interruptible(1))
1009 break;
1010 }
1011
1012 RTL_W32(CounterAddrLow, 0);
1013 RTL_W32(CounterAddrHigh, 0);
1014
5b0384f4 1015 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1016 data[1] = le64_to_cpu(counters->rx_packets);
1017 data[2] = le64_to_cpu(counters->tx_errors);
1018 data[3] = le32_to_cpu(counters->rx_errors);
1019 data[4] = le16_to_cpu(counters->rx_missed);
1020 data[5] = le16_to_cpu(counters->align_errors);
1021 data[6] = le32_to_cpu(counters->tx_one_collision);
1022 data[7] = le32_to_cpu(counters->tx_multi_collision);
1023 data[8] = le64_to_cpu(counters->rx_unicast);
1024 data[9] = le64_to_cpu(counters->rx_broadcast);
1025 data[10] = le32_to_cpu(counters->rx_multicast);
1026 data[11] = le16_to_cpu(counters->tx_aborted);
1027 data[12] = le16_to_cpu(counters->tx_underun);
1028
1029 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1030}
1031
1032static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1033{
1034 switch(stringset) {
1035 case ETH_SS_STATS:
1036 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1037 break;
1038 }
1039}
1040
7282d491 1041static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1042 .get_drvinfo = rtl8169_get_drvinfo,
1043 .get_regs_len = rtl8169_get_regs_len,
1044 .get_link = ethtool_op_get_link,
1045 .get_settings = rtl8169_get_settings,
1046 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1047 .get_msglevel = rtl8169_get_msglevel,
1048 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1049 .get_rx_csum = rtl8169_get_rx_csum,
1050 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1051 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1052 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1053 .set_tso = ethtool_op_set_tso,
1054 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1055 .get_wol = rtl8169_get_wol,
1056 .set_wol = rtl8169_set_wol,
d4a3a0fc 1057 .get_strings = rtl8169_get_strings,
b9f2c044 1058 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1059 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1060};
1061
07d3f51f
FR		 1062static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1063 int bitnum, int bitval)
1da177e4
LT		 1064{
1065 int val;
1066
1067 val = mdio_read(ioaddr, reg);
1068 val = (bitval == 1) ?
1069 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1070 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1071}
1072
07d3f51f
FR		 1073static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1074 void __iomem *ioaddr)
1da177e4 1075{
0e485150
FR		 1076 /*
1077 * The driver currently handles the 8168Bf and the 8168Be identically
1078 * but they can be identified more specifically through the test below
1079 * if needed:
1080 *
1081 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1082 *
1083 * Same thing for the 8101Eb and the 8101Ec:
1084 *
1085 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1086 */
1da177e4
LT		 1087 const struct {
1088 u32 mask;
e3cf0cc0 1089 u32 val;
1da177e4
LT		 1090 int mac_version;
1091 } mac_info[] = {
e3cf0cc0
FR		 1092 /* 8168B family. */
1093 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1094 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1095 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1096 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1097
1098 /* 8168B family. */
1099 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1100 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1101 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1102 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1103
1104 /* 8101 family. */
1105 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1106 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1107 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1108 /* FIXME: where did these entries come from ? -- FR */
1109 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1110 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1111
1112 /* 8110 family. */
1113 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1114 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1115 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1116 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1117 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1118 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1119
1120 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1121 }, *p = mac_info;
1122 u32 reg;
1123
e3cf0cc0
FR		 1124 reg = RTL_R32(TxConfig);
1125 while ((reg & p->mask) != p->val)
1da177e4
LT		 1126 p++;
1127 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1128
1129 if (p->mask == 0x00000000) {
1130 struct pci_dev *pdev = tp->pci_dev;
1131
1132 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1133 }
1da177e4
LT		 1134}
1135
1136static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1137{
bcf0bf90 1138 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1139}
1140
867763c1
FR		 1141struct phy_reg {
1142 u16 reg;
1143 u16 val;
1144};
1145
1146static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1147{
1148 while (len-- > 0) {
1149 mdio_write(ioaddr, regs->reg, regs->val);
1150 regs++;
1151 }
1152}
1153
5615d9f1 1154static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1155{
1da177e4
LT		 1156 struct {
1157 u16 regs[5]; /* Beware of bit-sign propagation */
1158 } phy_magic[5] = { {
1159 { 0x0000, //w 4 15 12 0
1160 0x00a1, //w 3 15 0 00a1
1161 0x0008, //w 2 15 0 0008
1162 0x1020, //w 1 15 0 1020
1163 0x1000 } },{ //w 0 15 0 1000
1164 { 0x7000, //w 4 15 12 7
1165 0xff41, //w 3 15 0 ff41
1166 0xde60, //w 2 15 0 de60
1167 0x0140, //w 1 15 0 0140
1168 0x0077 } },{ //w 0 15 0 0077
1169 { 0xa000, //w 4 15 12 a
1170 0xdf01, //w 3 15 0 df01
1171 0xdf20, //w 2 15 0 df20
1172 0xff95, //w 1 15 0 ff95
1173 0xfa00 } },{ //w 0 15 0 fa00
1174 { 0xb000, //w 4 15 12 b
1175 0xff41, //w 3 15 0 ff41
1176 0xde20, //w 2 15 0 de20
1177 0x0140, //w 1 15 0 0140
1178 0x00bb } },{ //w 0 15 0 00bb
1179 { 0xf000, //w 4 15 12 f
1180 0xdf01, //w 3 15 0 df01
1181 0xdf20, //w 2 15 0 df20
1182 0xff95, //w 1 15 0 ff95
1183 0xbf00 } //w 0 15 0 bf00
1184 }
1185 }, *p = phy_magic;
07d3f51f 1186 unsigned int i;
1da177e4 1187
a441d7b6
FR		 1188 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1189 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1190 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1191 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1192
1193 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1194 int val, pos = 4;
1195
1196 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1197 mdio_write(ioaddr, pos, val);
1198 while (--pos >= 0)
1199 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1200 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1201 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1202 }
a441d7b6 1203 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1204}
1205
5615d9f1
FR		 1206static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1207{
a441d7b6
FR		 1208 struct phy_reg phy_reg_init[] = {
1209 { 0x1f, 0x0002 },
1210 { 0x01, 0x90d0 },
1211 { 0x1f, 0x0000 }
1212 };
1213
1214 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1215}
1216
867763c1
FR		 1217static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1218{
1219 struct phy_reg phy_reg_init[] = {
1220 { 0x1f, 0x0000 },
1221 { 0x1d, 0x0f00 },
1222 { 0x1f, 0x0002 },
1223 { 0x0c, 0x1ec8 },
1224 { 0x1f, 0x0000 }
1225 };
1226
1227 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1228}
1229
1230static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1231{
1232 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1233 { 0x1f, 0x0001 },
1234 { 0x12, 0x2300 },
867763c1
FR		 1235 { 0x1f, 0x0002 },
1236 { 0x00, 0x88d4 },
1237 { 0x01, 0x82b1 },
1238 { 0x03, 0x7002 },
1239 { 0x08, 0x9e30 },
1240 { 0x09, 0x01f0 },
1241 { 0x0a, 0x5500 },
1242 { 0x0c, 0x00c8 },
1243 { 0x1f, 0x0003 },
1244 { 0x12, 0xc096 },
1245 { 0x16, 0x000a },
1246 { 0x1f, 0x0000 }
1247 };
1248
1249 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1250}
1251
7da97ec9
FR		 1252static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1253{
1254 struct phy_reg phy_reg_init[] = {
1255 { 0x1f, 0x0000 },
1256 { 0x12, 0x2300 },
1257 { 0x1f, 0x0003 },
1258 { 0x16, 0x0f0a },
1259 { 0x1f, 0x0000 },
1260 { 0x1f, 0x0002 },
1261 { 0x0c, 0x7eb8 },
1262 { 0x1f, 0x0000 }
1263 };
1264
1265 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1266}
1267
5615d9f1
FR		 1268static void rtl_hw_phy_config(struct net_device *dev)
1269{
1270 struct rtl8169_private *tp = netdev_priv(dev);
1271 void __iomem *ioaddr = tp->mmio_addr;
1272
1273 rtl8169_print_mac_version(tp);
1274
1275 switch (tp->mac_version) {
1276 case RTL_GIGA_MAC_VER_01:
1277 break;
1278 case RTL_GIGA_MAC_VER_02:
1279 case RTL_GIGA_MAC_VER_03:
1280 rtl8169s_hw_phy_config(ioaddr);
1281 break;
1282 case RTL_GIGA_MAC_VER_04:
1283 rtl8169sb_hw_phy_config(ioaddr);
1284 break;
867763c1
FR		 1285 case RTL_GIGA_MAC_VER_18:
1286 rtl8168cp_hw_phy_config(ioaddr);
1287 break;
1288 case RTL_GIGA_MAC_VER_19:
1289 rtl8168c_hw_phy_config(ioaddr);
1290 break;
7da97ec9
FR		 1291 case RTL_GIGA_MAC_VER_20:
1292 rtl8168cx_hw_phy_config(ioaddr);
1293 break;
5615d9f1
FR		 1294 default:
1295 break;
1296 }
1297}
1298
1da177e4
LT		 1299static void rtl8169_phy_timer(unsigned long __opaque)
1300{
1301 struct net_device *dev = (struct net_device *)__opaque;
1302 struct rtl8169_private *tp = netdev_priv(dev);
1303 struct timer_list *timer = &tp->timer;
1304 void __iomem *ioaddr = tp->mmio_addr;
1305 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1306
bcf0bf90 1307 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1308
64e4bfb4 1309 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1310 return;
1311
1312 spin_lock_irq(&tp->lock);
1313
1314 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1315 /*
1da177e4
LT		 1316 * A busy loop could burn quite a few cycles on nowadays CPU.
1317 * Let's delay the execution of the timer for a few ticks.
1318 */
1319 timeout = HZ/10;
1320 goto out_mod_timer;
1321 }
1322
1323 if (tp->link_ok(ioaddr))
1324 goto out_unlock;
1325
b57b7e5a
SH		 1326 if (netif_msg_link(tp))
1327 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1328
1329 tp->phy_reset_enable(ioaddr);
1330
1331out_mod_timer:
1332 mod_timer(timer, jiffies + timeout);
1333out_unlock:
1334 spin_unlock_irq(&tp->lock);
1335}
1336
1337static inline void rtl8169_delete_timer(struct net_device *dev)
1338{
1339 struct rtl8169_private *tp = netdev_priv(dev);
1340 struct timer_list *timer = &tp->timer;
1341
e179bb7b 1342 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1343 return;
1344
1345 del_timer_sync(timer);
1346}
1347
1348static inline void rtl8169_request_timer(struct net_device *dev)
1349{
1350 struct rtl8169_private *tp = netdev_priv(dev);
1351 struct timer_list *timer = &tp->timer;
1352
e179bb7b 1353 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1354 return;
1355
2efa53f3 1356 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1357}
1358
1359#ifdef CONFIG_NET_POLL_CONTROLLER
1360/*
1361 * Polling 'interrupt' - used by things like netconsole to send skbs
1362 * without having to re-enable interrupts. It's not called while
1363 * the interrupt routine is executing.
1364 */
1365static void rtl8169_netpoll(struct net_device *dev)
1366{
1367 struct rtl8169_private *tp = netdev_priv(dev);
1368 struct pci_dev *pdev = tp->pci_dev;
1369
1370 disable_irq(pdev->irq);
7d12e780 1371 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1372 enable_irq(pdev->irq);
1373}
1374#endif
1375
1376static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1377 void __iomem *ioaddr)
1378{
1379 iounmap(ioaddr);
1380 pci_release_regions(pdev);
1381 pci_disable_device(pdev);
1382 free_netdev(dev);
1383}
1384
bf793295
FR		 1385static void rtl8169_phy_reset(struct net_device *dev,
1386 struct rtl8169_private *tp)
1387{
1388 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1389 unsigned int i;
bf793295
FR		 1390
1391 tp->phy_reset_enable(ioaddr);
1392 for (i = 0; i < 100; i++) {
1393 if (!tp->phy_reset_pending(ioaddr))
1394 return;
1395 msleep(1);
1396 }
1397 if (netif_msg_link(tp))
1398 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1399}
1400
4ff96fa6
FR		 1401static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1402{
1403 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1404
5615d9f1 1405 rtl_hw_phy_config(dev);
4ff96fa6 1406
77332894
MS		 1407 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1408 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1409 RTL_W8(0x82, 0x01);
1410 }
4ff96fa6 1411
6dccd16b
FR		 1412 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1413
1414 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1415 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1416
bcf0bf90 1417 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1418 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1419 RTL_W8(0x82, 0x01);
1420 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1421 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1422 }
1423
bf793295
FR		 1424 rtl8169_phy_reset(dev, tp);
1425
901dda2b
FR		 1426 /*
1427 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1428 * only 8101. Don't panic.
1429 */
1430 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1431
1432 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1433 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1434}
1435
773d2021
FR		 1436static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1437{
1438 void __iomem *ioaddr = tp->mmio_addr;
1439 u32 high;
1440 u32 low;
1441
1442 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1443 high = addr[4] | (addr[5] << 8);
1444
1445 spin_lock_irq(&tp->lock);
1446
1447 RTL_W8(Cfg9346, Cfg9346_Unlock);
1448 RTL_W32(MAC0, low);
1449 RTL_W32(MAC4, high);
1450 RTL_W8(Cfg9346, Cfg9346_Lock);
1451
1452 spin_unlock_irq(&tp->lock);
1453}
1454
1455static int rtl_set_mac_address(struct net_device *dev, void *p)
1456{
1457 struct rtl8169_private *tp = netdev_priv(dev);
1458 struct sockaddr *addr = p;
1459
1460 if (!is_valid_ether_addr(addr->sa_data))
1461 return -EADDRNOTAVAIL;
1462
1463 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1464
1465 rtl_rar_set(tp, dev->dev_addr);
1466
1467 return 0;
1468}
1469
5f787a1a
FR		 1470static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1471{
1472 struct rtl8169_private *tp = netdev_priv(dev);
1473 struct mii_ioctl_data *data = if_mii(ifr);
1474
1475 if (!netif_running(dev))
1476 return -ENODEV;
1477
1478 switch (cmd) {
1479 case SIOCGMIIPHY:
1480 data->phy_id = 32; /* Internal PHY */
1481 return 0;
1482
1483 case SIOCGMIIREG:
1484 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1485 return 0;
1486
1487 case SIOCSMIIREG:
1488 if (!capable(CAP_NET_ADMIN))
1489 return -EPERM;
1490 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1491 return 0;
1492 }
1493 return -EOPNOTSUPP;
1494}
1495
0e485150
FR		 1496static const struct rtl_cfg_info {
1497 void (*hw_start)(struct net_device *);
1498 unsigned int region;
1499 unsigned int align;
1500 u16 intr_event;
1501 u16 napi_event;
ccdffb9a 1502 unsigned features;
0e485150
FR		 1503} rtl_cfg_infos [] = {
1504 [RTL_CFG_0] = {
1505 .hw_start = rtl_hw_start_8169,
1506 .region = 1,
e9f63f30 1507 .align = 0,
0e485150
FR		 1508 .intr_event = SYSErr | LinkChg | RxOverflow |
1509 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1510 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1511 .features = RTL_FEATURE_GMII
0e485150
FR		 1512 },
1513 [RTL_CFG_1] = {
1514 .hw_start = rtl_hw_start_8168,
1515 .region = 2,
1516 .align = 8,
1517 .intr_event = SYSErr | LinkChg | RxOverflow |
1518 TxErr | TxOK | RxOK | RxErr,
fbac58fc 1519 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1520 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
0e485150
FR		 1521 },
1522 [RTL_CFG_2] = {
1523 .hw_start = rtl_hw_start_8101,
1524 .region = 2,
1525 .align = 8,
1526 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1527 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1528 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1529 .features = RTL_FEATURE_MSI
0e485150
FR		 1530 }
1531};
1532
fbac58fc
FR		 1533/* Cfg9346_Unlock assumed. */
1534static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1535 const struct rtl_cfg_info *cfg)
1536{
1537 unsigned msi = 0;
1538 u8 cfg2;
1539
1540 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 1541 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 1542 if (pci_enable_msi(pdev)) {
1543 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1544 } else {
1545 cfg2 |= MSIEnable;
1546 msi = RTL_FEATURE_MSI;
1547 }
1548 }
1549 RTL_W8(Config2, cfg2);
1550 return msi;
1551}
1552
1553static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1554{
1555 if (tp->features & RTL_FEATURE_MSI) {
1556 pci_disable_msi(pdev);
1557 tp->features &= ~RTL_FEATURE_MSI;
1558 }
1559}
1560
1da177e4 1561static int __devinit
4ff96fa6 1562rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1563{
0e485150
FR		 1564 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1565 const unsigned int region = cfg->region;
1da177e4 1566 struct rtl8169_private *tp;
ccdffb9a 1567 struct mii_if_info *mii;
4ff96fa6
FR		 1568 struct net_device *dev;
1569 void __iomem *ioaddr;
07d3f51f
FR		 1570 unsigned int i;
1571 int rc;
1da177e4 1572
4ff96fa6
FR		 1573 if (netif_msg_drv(&debug)) {
1574 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1575 MODULENAME, RTL8169_VERSION);
1576 }
1da177e4 1577
1da177e4 1578 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1579 if (!dev) {
b57b7e5a 1580 if (netif_msg_drv(&debug))
9b91cf9d 1581 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1582 rc = -ENOMEM;
1583 goto out;
1da177e4
LT		 1584 }
1585
1da177e4
LT		 1586 SET_NETDEV_DEV(dev, &pdev->dev);
1587 tp = netdev_priv(dev);
c4028958 1588 tp->dev = dev;
21e197f2 1589 tp->pci_dev = pdev;
b57b7e5a 1590 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 1591
ccdffb9a
FR		 1592 mii = &tp->mii;
1593 mii->dev = dev;
1594 mii->mdio_read = rtl_mdio_read;
1595 mii->mdio_write = rtl_mdio_write;
1596 mii->phy_id_mask = 0x1f;
1597 mii->reg_num_mask = 0x1f;
1598 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1599
1da177e4
LT		 1600 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1601 rc = pci_enable_device(pdev);
b57b7e5a 1602 if (rc < 0) {
2e8a538d 1603 if (netif_msg_probe(tp))
9b91cf9d 1604 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1605 goto err_out_free_dev_1;
1da177e4
LT		 1606 }
1607
1608 rc = pci_set_mwi(pdev);
1609 if (rc < 0)
4ff96fa6 1610 goto err_out_disable_2;
1da177e4 1611
1da177e4 1612 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1613 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1614 if (netif_msg_probe(tp)) {
9b91cf9d 1615 dev_err(&pdev->dev,
bcf0bf90
FR		 1616 "region #%d not an MMIO resource, aborting\n",
1617 region);
4ff96fa6 1618 }
1da177e4 1619 rc = -ENODEV;
4ff96fa6 1620 goto err_out_mwi_3;
1da177e4 1621 }
4ff96fa6 1622
1da177e4 1623 /* check for weird/broken PCI region reporting */
bcf0bf90 1624 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1625 if (netif_msg_probe(tp)) {
9b91cf9d 1626 dev_err(&pdev->dev,
4ff96fa6
FR		 1627 "Invalid PCI region size(s), aborting\n");
1628 }
1da177e4 1629 rc = -ENODEV;
4ff96fa6 1630 goto err_out_mwi_3;
1da177e4
LT		 1631 }
1632
1633 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1634 if (rc < 0) {
2e8a538d 1635 if (netif_msg_probe(tp))
9b91cf9d 1636 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1637 goto err_out_mwi_3;
1da177e4
LT		 1638 }
1639
1640 tp->cp_cmd = PCIMulRW | RxChkSum;
1641
1642 if ((sizeof(dma_addr_t) > 4) &&
1643 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1644 tp->cp_cmd |= PCIDAC;
1645 dev->features |= NETIF_F_HIGHDMA;
1646 } else {
1647 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1648 if (rc < 0) {
4ff96fa6 1649 if (netif_msg_probe(tp)) {
9b91cf9d 1650 dev_err(&pdev->dev,
4ff96fa6
FR		 1651 "DMA configuration failed.\n");
1652 }
1653 goto err_out_free_res_4;
1da177e4
LT		 1654 }
1655 }
1656
1657 pci_set_master(pdev);
1658
1659 /* ioremap MMIO region */
bcf0bf90 1660 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1661 if (!ioaddr) {
b57b7e5a 1662 if (netif_msg_probe(tp))
9b91cf9d 1663 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1664 rc = -EIO;
4ff96fa6 1665 goto err_out_free_res_4;
1da177e4
LT		 1666 }
1667
9c14ceaf
FR		 1668 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1669 if (!tp->pcie_cap && netif_msg_probe(tp))
1670 dev_info(&pdev->dev, "no PCI Express capability\n");
1671
1da177e4
LT		 1672 /* Unneeded ? Don't mess with Mrs. Murphy. */
1673 rtl8169_irq_mask_and_ack(ioaddr);
1674
1675 /* Soft reset the chip. */
1676 RTL_W8(ChipCmd, CmdReset);
1677
1678 /* Check that the chip has finished the reset. */
07d3f51f 1679 for (i = 0; i < 100; i++) {
1da177e4
LT		 1680 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1681 break;
b518fa8e 1682 msleep_interruptible(1);
1da177e4
LT		 1683 }
1684
1685 /* Identify chip attached to board */
1686 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 1687
1688 rtl8169_print_mac_version(tp);
1da177e4 1689
cee60c37 1690 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 1691 if (tp->mac_version == rtl_chip_info[i].mac_version)
1692 break;
1693 }
cee60c37 1694 if (i == ARRAY_SIZE(rtl_chip_info)) {
1da177e4 1695 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1696 if (netif_msg_probe(tp)) {
2e8a538d 1697 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1698 "unknown chip version, assuming %s\n",
1699 rtl_chip_info[0].name);
b57b7e5a 1700 }
cee60c37 1701 i = 0;
1da177e4
LT		 1702 }
1703 tp->chipset = i;
1704
5d06a99f
FR		 1705 RTL_W8(Cfg9346, Cfg9346_Unlock);
1706 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1707 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
fbac58fc 1708 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 1709 RTL_W8(Cfg9346, Cfg9346_Lock);
1710
66ec5d4f
FR		 1711 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1712 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 1713 tp->set_speed = rtl8169_set_speed_tbi;
1714 tp->get_settings = rtl8169_gset_tbi;
1715 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1716 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1717 tp->link_ok = rtl8169_tbi_link_ok;
1718
64e4bfb4 1719 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1720 } else {
1721 tp->set_speed = rtl8169_set_speed_xmii;
1722 tp->get_settings = rtl8169_gset_xmii;
1723 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1724 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1725 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1726
1727 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1728 }
1729
1730 /* Get MAC address. FIXME: read EEPROM */
1731 for (i = 0; i < MAC_ADDR_LEN; i++)
1732 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1733 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1734
1735 dev->open = rtl8169_open;
1736 dev->hard_start_xmit = rtl8169_start_xmit;
1737 dev->get_stats = rtl8169_get_stats;
1738 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1739 dev->stop = rtl8169_close;
1740 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1741 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1742 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1743 dev->irq = pdev->irq;
1744 dev->base_addr = (unsigned long) ioaddr;
1745 dev->change_mtu = rtl8169_change_mtu;
773d2021 1746 dev->set_mac_address = rtl_set_mac_address;
1da177e4 1747
bea3348e 1748 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 1749
1750#ifdef CONFIG_R8169_VLAN
1751 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1752 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1753#endif
1754
1755#ifdef CONFIG_NET_POLL_CONTROLLER
1756 dev->poll_controller = rtl8169_netpoll;
1757#endif
1758
1759 tp->intr_mask = 0xffff;
1da177e4 1760 tp->mmio_addr = ioaddr;
0e485150
FR		 1761 tp->align = cfg->align;
1762 tp->hw_start = cfg->hw_start;
1763 tp->intr_event = cfg->intr_event;
1764 tp->napi_event = cfg->napi_event;
1da177e4 1765
2efa53f3
FR		 1766 init_timer(&tp->timer);
1767 tp->timer.data = (unsigned long) dev;
1768 tp->timer.function = rtl8169_phy_timer;
1769
1da177e4
LT		 1770 spin_lock_init(&tp->lock);
1771
1772 rc = register_netdev(dev);
4ff96fa6 1773 if (rc < 0)
fbac58fc 1774 goto err_out_msi_5;
1da177e4
LT		 1775
1776 pci_set_drvdata(pdev, dev);
1777
b57b7e5a 1778 if (netif_msg_probe(tp)) {
96b9709c
FR		 1779 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1780
b57b7e5a
SH		 1781 printk(KERN_INFO "%s: %s at 0x%lx, "
1782 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1783 "XID %08x IRQ %d\n",
b57b7e5a 1784 dev->name,
bcf0bf90 1785 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1786 dev->base_addr,
1787 dev->dev_addr[0], dev->dev_addr[1],
1788 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1789 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1790 }
1da177e4 1791
4ff96fa6 1792 rtl8169_init_phy(dev, tp);
1da177e4 1793
4ff96fa6
FR		 1794out:
1795 return rc;
1da177e4 1796
fbac58fc
FR		 1797err_out_msi_5:
1798 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 1799 iounmap(ioaddr);
1800err_out_free_res_4:
1801 pci_release_regions(pdev);
1802err_out_mwi_3:
1803 pci_clear_mwi(pdev);
1804err_out_disable_2:
1805 pci_disable_device(pdev);
1806err_out_free_dev_1:
1807 free_netdev(dev);
1808 goto out;
1da177e4
LT		 1809}
1810
07d3f51f 1811static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1812{
1813 struct net_device *dev = pci_get_drvdata(pdev);
1814 struct rtl8169_private *tp = netdev_priv(dev);
1815
eb2a021c
FR		 1816 flush_scheduled_work();
1817
1da177e4 1818 unregister_netdev(dev);
fbac58fc 1819 rtl_disable_msi(pdev, tp);
1da177e4
LT		 1820 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1821 pci_set_drvdata(pdev, NULL);
1822}
1823
1da177e4
LT		 1824static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1825 struct net_device *dev)
1826{
1827 unsigned int mtu = dev->mtu;
1828
1829 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1830}
1831
1832static int rtl8169_open(struct net_device *dev)
1833{
1834 struct rtl8169_private *tp = netdev_priv(dev);
1835 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1836 int retval = -ENOMEM;
1da177e4 1837
1da177e4 1838
99f252b0 1839 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1840
1841 /*
1842 * Rx and Tx desscriptors needs 256 bytes alignment.
1843 * pci_alloc_consistent provides more.
1844 */
1845 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1846 &tp->TxPhyAddr);
1847 if (!tp->TxDescArray)
99f252b0 1848 goto out;
1da177e4
LT		 1849
1850 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1851 &tp->RxPhyAddr);
1852 if (!tp->RxDescArray)
99f252b0 1853 goto err_free_tx_0;
1da177e4
LT		 1854
1855 retval = rtl8169_init_ring(dev);
1856 if (retval < 0)
99f252b0 1857 goto err_free_rx_1;
1da177e4 1858
c4028958 1859 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1860
99f252b0
FR		 1861 smp_mb();
1862
fbac58fc
FR		 1863 retval = request_irq(dev->irq, rtl8169_interrupt,
1864 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 1865 dev->name, dev);
1866 if (retval < 0)
1867 goto err_release_ring_2;
1868
bea3348e 1869 napi_enable(&tp->napi);
bea3348e 1870
07ce4064 1871 rtl_hw_start(dev);
1da177e4
LT		 1872
1873 rtl8169_request_timer(dev);
1874
1875 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1876out:
1877 return retval;
1878
99f252b0
FR		 1879err_release_ring_2:
1880 rtl8169_rx_clear(tp);
1881err_free_rx_1:
1da177e4
LT		 1882 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1883 tp->RxPhyAddr);
99f252b0 1884err_free_tx_0:
1da177e4
LT		 1885 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1886 tp->TxPhyAddr);
1da177e4
LT		 1887 goto out;
1888}
1889
1890static void rtl8169_hw_reset(void __iomem *ioaddr)
1891{
1892 /* Disable interrupts */
1893 rtl8169_irq_mask_and_ack(ioaddr);
1894
1895 /* Reset the chipset */
1896 RTL_W8(ChipCmd, CmdReset);
1897
1898 /* PCI commit */
1899 RTL_R8(ChipCmd);
1900}
1901
7f796d83 1902static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1903{
1904 void __iomem *ioaddr = tp->mmio_addr;
1905 u32 cfg = rtl8169_rx_config;
1906
1907 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1908 RTL_W32(RxConfig, cfg);
1909
1910 /* Set DMA burst size and Interframe Gap Time */
1911 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1912 (InterFrameGap << TxInterFrameGapShift));
1913}
1914
07ce4064 1915static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1916{
1917 struct rtl8169_private *tp = netdev_priv(dev);
1918 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1919 unsigned int i;
1da177e4
LT		 1920
1921 /* Soft reset the chip. */
1922 RTL_W8(ChipCmd, CmdReset);
1923
1924 /* Check that the chip has finished the reset. */
07d3f51f 1925 for (i = 0; i < 100; i++) {
1da177e4
LT		 1926 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1927 break;
b518fa8e 1928 msleep_interruptible(1);
1da177e4
LT		 1929 }
1930
07ce4064
FR		 1931 tp->hw_start(dev);
1932
07ce4064
FR		 1933 netif_start_queue(dev);
1934}
1935
1936
7f796d83
FR		 1937static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1938 void __iomem *ioaddr)
1939{
1940 /*
1941 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1942 * register to be written before TxDescAddrLow to work.
1943 * Switching from MMIO to I/O access fixes the issue as well.
1944 */
1945 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1946 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1947 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1948 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1949}
1950
1951static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1952{
1953 u16 cmd;
1954
1955 cmd = RTL_R16(CPlusCmd);
1956 RTL_W16(CPlusCmd, cmd);
1957 return cmd;
1958}
1959
1960static void rtl_set_rx_max_size(void __iomem *ioaddr)
1961{
1962 /* Low hurts. Let's disable the filtering. */
1963 RTL_W16(RxMaxSize, 16383);
1964}
1965
6dccd16b
FR		 1966static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1967{
1968 struct {
1969 u32 mac_version;
1970 u32 clk;
1971 u32 val;
1972 } cfg2_info [] = {
1973 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1974 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1975 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1976 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1977 }, *p = cfg2_info;
1978 unsigned int i;
1979 u32 clk;
1980
1981 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 1982 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 1983 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1984 RTL_W32(0x7c, p->val);
1985 break;
1986 }
1987 }
1988}
1989
07ce4064
FR		 1990static void rtl_hw_start_8169(struct net_device *dev)
1991{
1992 struct rtl8169_private *tp = netdev_priv(dev);
1993 void __iomem *ioaddr = tp->mmio_addr;
1994 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1995
9cb427b6
FR		 1996 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1997 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1998 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1999 }
2000
1da177e4 2001 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2002 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2003 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2004 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2005 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2006 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2007
1da177e4
LT		 2008 RTL_W8(EarlyTxThres, EarlyTxThld);
2009
7f796d83 2010 rtl_set_rx_max_size(ioaddr);
1da177e4 2011
c946b304
FR		 2012 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2013 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2014 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2015 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2016 rtl_set_rx_tx_config_registers(tp);
1da177e4 2017
7f796d83 2018 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2019
bcf0bf90
FR		 2020 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2021 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2022 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2023 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2024 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2025 }
2026
bcf0bf90
FR		 2027 RTL_W16(CPlusCmd, tp->cp_cmd);
2028
6dccd16b
FR		 2029 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2030
1da177e4
LT		 2031 /*
2032 * Undocumented corner. Supposedly:
2033 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2034 */
2035 RTL_W16(IntrMitigate, 0x0000);
2036
7f796d83 2037 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2038
c946b304
FR		 2039 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2040 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2041 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2042 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2043 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2044 rtl_set_rx_tx_config_registers(tp);
2045 }
2046
1da177e4 2047 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2048
2049 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2050 RTL_R8(IntrMask);
1da177e4
LT		 2051
2052 RTL_W32(RxMissed, 0);
2053
07ce4064 2054 rtl_set_rx_mode(dev);
1da177e4
LT		 2055
2056 /* no early-rx interrupts */
2057 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2058
2059 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2060 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2061}
1da177e4 2062
9c14ceaf 2063static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 2064{
9c14ceaf
FR		 2065 struct net_device *dev = pci_get_drvdata(pdev);
2066 struct rtl8169_private *tp = netdev_priv(dev);
2067 int cap = tp->pcie_cap;
2068
2069 if (cap) {
2070 u16 ctl;
458a9f61 2071
9c14ceaf
FR		 2072 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2073 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2074 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2075 }
458a9f61
FR		 2076}
2077
07ce4064
FR		 2078static void rtl_hw_start_8168(struct net_device *dev)
2079{
2dd99530
FR		 2080 struct rtl8169_private *tp = netdev_priv(dev);
2081 void __iomem *ioaddr = tp->mmio_addr;
0e485150 2082 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 2083
2084 RTL_W8(Cfg9346, Cfg9346_Unlock);
2085
2086 RTL_W8(EarlyTxThres, EarlyTxThld);
2087
2088 rtl_set_rx_max_size(ioaddr);
2089
0e485150
FR		 2090 rtl_set_rx_tx_config_registers(tp);
2091
2092 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2093
2094 RTL_W16(CPlusCmd, tp->cp_cmd);
2095
9c14ceaf 2096 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2dd99530 2097
0e485150 2098 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2099
0e485150
FR		 2100 /* Work around for RxFIFO overflow. */
2101 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2102 tp->intr_event |= RxFIFOOver | PCSTimeout;
2103 tp->intr_event &= ~RxOverflow;
2104 }
2105
2106 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2107
2108 RTL_W8(Cfg9346, Cfg9346_Lock);
2109
2110 RTL_R8(IntrMask);
2111
2112 RTL_W32(RxMissed, 0);
2113
2114 rtl_set_rx_mode(dev);
2115
0e485150
FR		 2116 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2117
2dd99530 2118 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2119
0e485150 2120 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2121}
1da177e4 2122
07ce4064
FR		 2123static void rtl_hw_start_8101(struct net_device *dev)
2124{
cdf1a608
FR		 2125 struct rtl8169_private *tp = netdev_priv(dev);
2126 void __iomem *ioaddr = tp->mmio_addr;
2127 struct pci_dev *pdev = tp->pci_dev;
2128
e3cf0cc0
FR		 2129 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2130 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 2131 int cap = tp->pcie_cap;
2132
2133 if (cap) {
2134 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2135 PCI_EXP_DEVCTL_NOSNOOP_EN);
2136 }
cdf1a608
FR		 2137 }
2138
2139 RTL_W8(Cfg9346, Cfg9346_Unlock);
2140
2141 RTL_W8(EarlyTxThres, EarlyTxThld);
2142
2143 rtl_set_rx_max_size(ioaddr);
2144
2145 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2146
2147 RTL_W16(CPlusCmd, tp->cp_cmd);
2148
2149 RTL_W16(IntrMitigate, 0x0000);
2150
2151 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2152
2153 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2154 rtl_set_rx_tx_config_registers(tp);
2155
2156 RTL_W8(Cfg9346, Cfg9346_Lock);
2157
2158 RTL_R8(IntrMask);
2159
2160 RTL_W32(RxMissed, 0);
2161
2162 rtl_set_rx_mode(dev);
2163
0e485150
FR		 2164 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2165
cdf1a608 2166 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2167
0e485150 2168 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2169}
2170
2171static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2172{
2173 struct rtl8169_private *tp = netdev_priv(dev);
2174 int ret = 0;
2175
2176 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2177 return -EINVAL;
2178
2179 dev->mtu = new_mtu;
2180
2181 if (!netif_running(dev))
2182 goto out;
2183
2184 rtl8169_down(dev);
2185
2186 rtl8169_set_rxbufsize(tp, dev);
2187
2188 ret = rtl8169_init_ring(dev);
2189 if (ret < 0)
2190 goto out;
2191
bea3348e 2192 napi_enable(&tp->napi);
1da177e4 2193
07ce4064 2194 rtl_hw_start(dev);
1da177e4
LT		 2195
2196 rtl8169_request_timer(dev);
2197
2198out:
2199 return ret;
2200}
2201
2202static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2203{
95e0918d 2204 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 2205 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2206}
2207
2208static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2209 struct sk_buff **sk_buff, struct RxDesc *desc)
2210{
2211 struct pci_dev *pdev = tp->pci_dev;
2212
2213 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2214 PCI_DMA_FROMDEVICE);
2215 dev_kfree_skb(*sk_buff);
2216 *sk_buff = NULL;
2217 rtl8169_make_unusable_by_asic(desc);
2218}
2219
2220static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2221{
2222 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2223
2224 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2225}
2226
2227static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2228 u32 rx_buf_sz)
2229{
2230 desc->addr = cpu_to_le64(mapping);
2231 wmb();
2232 rtl8169_mark_to_asic(desc, rx_buf_sz);
2233}
2234
15d31758
SH		 2235static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2236 struct net_device *dev,
2237 struct RxDesc *desc, int rx_buf_sz,
2238 unsigned int align)
1da177e4
LT		 2239{
2240 struct sk_buff *skb;
2241 dma_addr_t mapping;
e9f63f30 2242 unsigned int pad;
1da177e4 2243
e9f63f30
FR		 2244 pad = align ? align : NET_IP_ALIGN;
2245
2246 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2247 if (!skb)
2248 goto err_out;
2249
e9f63f30 2250 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2251
689be439 2252 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2253 PCI_DMA_FROMDEVICE);
2254
2255 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2256out:
15d31758 2257 return skb;
1da177e4
LT		 2258
2259err_out:
1da177e4
LT		 2260 rtl8169_make_unusable_by_asic(desc);
2261 goto out;
2262}
2263
2264static void rtl8169_rx_clear(struct rtl8169_private *tp)
2265{
07d3f51f 2266 unsigned int i;
1da177e4
LT		 2267
2268 for (i = 0; i < NUM_RX_DESC; i++) {
2269 if (tp->Rx_skbuff[i]) {
2270 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2271 tp->RxDescArray + i);
2272 }
2273 }
2274}
2275
2276static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2277 u32 start, u32 end)
2278{
2279 u32 cur;
5b0384f4 2280
4ae47c2d 2281 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2282 struct sk_buff *skb;
2283 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2284
4ae47c2d
FR		 2285 WARN_ON((s32)(end - cur) < 0);
2286
1da177e4
LT		 2287 if (tp->Rx_skbuff[i])
2288 continue;
bcf0bf90 2289
15d31758
SH		 2290 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2291 tp->RxDescArray + i,
2292 tp->rx_buf_sz, tp->align);
2293 if (!skb)
1da177e4 2294 break;
15d31758
SH		 2295
2296 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2297 }
2298 return cur - start;
2299}
2300
2301static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2302{
2303 desc->opts1 |= cpu_to_le32(RingEnd);
2304}
2305
2306static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2307{
2308 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2309}
2310
2311static int rtl8169_init_ring(struct net_device *dev)
2312{
2313 struct rtl8169_private *tp = netdev_priv(dev);
2314
2315 rtl8169_init_ring_indexes(tp);
2316
2317 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2318 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2319
2320 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2321 goto err_out;
2322
2323 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2324
2325 return 0;
2326
2327err_out:
2328 rtl8169_rx_clear(tp);
2329 return -ENOMEM;
2330}
2331
2332static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2333 struct TxDesc *desc)
2334{
2335 unsigned int len = tx_skb->len;
2336
2337 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2338 desc->opts1 = 0x00;
2339 desc->opts2 = 0x00;
2340 desc->addr = 0x00;
2341 tx_skb->len = 0;
2342}
2343
2344static void rtl8169_tx_clear(struct rtl8169_private *tp)
2345{
2346 unsigned int i;
2347
2348 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2349 unsigned int entry = i % NUM_TX_DESC;
2350 struct ring_info *tx_skb = tp->tx_skb + entry;
2351 unsigned int len = tx_skb->len;
2352
2353 if (len) {
2354 struct sk_buff *skb = tx_skb->skb;
2355
2356 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2357 tp->TxDescArray + entry);
2358 if (skb) {
2359 dev_kfree_skb(skb);
2360 tx_skb->skb = NULL;
2361 }
cebf8cc7 2362 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2363 }
2364 }
2365 tp->cur_tx = tp->dirty_tx = 0;
2366}
2367
c4028958 2368static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2369{
2370 struct rtl8169_private *tp = netdev_priv(dev);
2371
c4028958 2372 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2373 schedule_delayed_work(&tp->task, 4);
2374}
2375
2376static void rtl8169_wait_for_quiescence(struct net_device *dev)
2377{
2378 struct rtl8169_private *tp = netdev_priv(dev);
2379 void __iomem *ioaddr = tp->mmio_addr;
2380
2381 synchronize_irq(dev->irq);
2382
2383 /* Wait for any pending NAPI task to complete */
bea3348e 2384 napi_disable(&tp->napi);
1da177e4
LT		 2385
2386 rtl8169_irq_mask_and_ack(ioaddr);
2387
d1d08d12
DM		 2388 tp->intr_mask = 0xffff;
2389 RTL_W16(IntrMask, tp->intr_event);
bea3348e 2390 napi_enable(&tp->napi);
1da177e4
LT		 2391}
2392
c4028958 2393static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2394{
c4028958
DH		 2395 struct rtl8169_private *tp =
2396 container_of(work, struct rtl8169_private, task.work);
2397 struct net_device *dev = tp->dev;
1da177e4
LT		 2398 int ret;
2399
eb2a021c
FR		 2400 rtnl_lock();
2401
2402 if (!netif_running(dev))
2403 goto out_unlock;
2404
2405 rtl8169_wait_for_quiescence(dev);
2406 rtl8169_close(dev);
1da177e4
LT		 2407
2408 ret = rtl8169_open(dev);
2409 if (unlikely(ret < 0)) {
07d3f51f 2410 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 2411 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 2412 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2413 }
2414 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2415 }
eb2a021c
FR		 2416
2417out_unlock:
2418 rtnl_unlock();
1da177e4
LT		 2419}
2420
c4028958 2421static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2422{
c4028958
DH		 2423 struct rtl8169_private *tp =
2424 container_of(work, struct rtl8169_private, task.work);
2425 struct net_device *dev = tp->dev;
1da177e4 2426
eb2a021c
FR		 2427 rtnl_lock();
2428
1da177e4 2429 if (!netif_running(dev))
eb2a021c 2430 goto out_unlock;
1da177e4
LT		 2431
2432 rtl8169_wait_for_quiescence(dev);
2433
bea3348e 2434 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 2435 rtl8169_tx_clear(tp);
2436
2437 if (tp->dirty_rx == tp->cur_rx) {
2438 rtl8169_init_ring_indexes(tp);
07ce4064 2439 rtl_hw_start(dev);
1da177e4 2440 netif_wake_queue(dev);
cebf8cc7 2441 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 2442 } else {
07d3f51f 2443 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 2444 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 2445 dev->name);
1da177e4
LT		 2446 }
2447 rtl8169_schedule_work(dev, rtl8169_reset_task);
2448 }
eb2a021c
FR		 2449
2450out_unlock:
2451 rtnl_unlock();
1da177e4
LT		 2452}
2453
2454static void rtl8169_tx_timeout(struct net_device *dev)
2455{
2456 struct rtl8169_private *tp = netdev_priv(dev);
2457
2458 rtl8169_hw_reset(tp->mmio_addr);
2459
2460 /* Let's wait a bit while any (async) irq lands on */
2461 rtl8169_schedule_work(dev, rtl8169_reset_task);
2462}
2463
2464static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2465 u32 opts1)
2466{
2467 struct skb_shared_info *info = skb_shinfo(skb);
2468 unsigned int cur_frag, entry;
a6343afb 2469 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2470
2471 entry = tp->cur_tx;
2472 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2473 skb_frag_t *frag = info->frags + cur_frag;
2474 dma_addr_t mapping;
2475 u32 status, len;
2476 void *addr;
2477
2478 entry = (entry + 1) % NUM_TX_DESC;
2479
2480 txd = tp->TxDescArray + entry;
2481 len = frag->size;
2482 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2483 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2484
2485 /* anti gcc 2.95.3 bugware (sic) */
2486 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2487
2488 txd->opts1 = cpu_to_le32(status);
2489 txd->addr = cpu_to_le64(mapping);
2490
2491 tp->tx_skb[entry].len = len;
2492 }
2493
2494 if (cur_frag) {
2495 tp->tx_skb[entry].skb = skb;
2496 txd->opts1 |= cpu_to_le32(LastFrag);
2497 }
2498
2499 return cur_frag;
2500}
2501
2502static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2503{
2504 if (dev->features & NETIF_F_TSO) {
7967168c 2505 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2506
2507 if (mss)
2508 return LargeSend | ((mss & MSSMask) << MSSShift);
2509 }
84fa7933 2510 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2511 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2512
2513 if (ip->protocol == IPPROTO_TCP)
2514 return IPCS | TCPCS;
2515 else if (ip->protocol == IPPROTO_UDP)
2516 return IPCS | UDPCS;
2517 WARN_ON(1); /* we need a WARN() */
2518 }
2519 return 0;
2520}
2521
2522static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2523{
2524 struct rtl8169_private *tp = netdev_priv(dev);
2525 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2526 struct TxDesc *txd = tp->TxDescArray + entry;
2527 void __iomem *ioaddr = tp->mmio_addr;
2528 dma_addr_t mapping;
2529 u32 status, len;
2530 u32 opts1;
188f4af0 2531 int ret = NETDEV_TX_OK;
5b0384f4 2532
1da177e4 2533 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2534 if (netif_msg_drv(tp)) {
2535 printk(KERN_ERR
2536 "%s: BUG! Tx Ring full when queue awake!\n",
2537 dev->name);
2538 }
1da177e4
LT		 2539 goto err_stop;
2540 }
2541
2542 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2543 goto err_stop;
2544
2545 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2546
2547 frags = rtl8169_xmit_frags(tp, skb, opts1);
2548 if (frags) {
2549 len = skb_headlen(skb);
2550 opts1 |= FirstFrag;
2551 } else {
2552 len = skb->len;
2553
2554 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2555 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2556 goto err_update_stats;
2557 len = ETH_ZLEN;
2558 }
2559
2560 opts1 |= FirstFrag | LastFrag;
2561 tp->tx_skb[entry].skb = skb;
2562 }
2563
2564 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2565
2566 tp->tx_skb[entry].len = len;
2567 txd->addr = cpu_to_le64(mapping);
2568 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2569
2570 wmb();
2571
2572 /* anti gcc 2.95.3 bugware (sic) */
2573 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2574 txd->opts1 = cpu_to_le32(status);
2575
2576 dev->trans_start = jiffies;
2577
2578 tp->cur_tx += frags + 1;
2579
2580 smp_wmb();
2581
275391a4 2582 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2583
2584 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2585 netif_stop_queue(dev);
2586 smp_rmb();
2587 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2588 netif_wake_queue(dev);
2589 }
2590
2591out:
2592 return ret;
2593
2594err_stop:
2595 netif_stop_queue(dev);
188f4af0 2596 ret = NETDEV_TX_BUSY;
1da177e4 2597err_update_stats:
cebf8cc7 2598 dev->stats.tx_dropped++;
1da177e4
LT		 2599 goto out;
2600}
2601
2602static void rtl8169_pcierr_interrupt(struct net_device *dev)
2603{
2604 struct rtl8169_private *tp = netdev_priv(dev);
2605 struct pci_dev *pdev = tp->pci_dev;
2606 void __iomem *ioaddr = tp->mmio_addr;
2607 u16 pci_status, pci_cmd;
2608
2609 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2610 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2611
b57b7e5a
SH		 2612 if (netif_msg_intr(tp)) {
2613 printk(KERN_ERR
2614 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2615 dev->name, pci_cmd, pci_status);
2616 }
1da177e4
LT		 2617
2618 /*
2619 * The recovery sequence below admits a very elaborated explanation:
2620 * - it seems to work;
d03902b8
FR		 2621 * - I did not see what else could be done;
2622 * - it makes iop3xx happy.
1da177e4
LT		 2623 *
2624 * Feel free to adjust to your needs.
2625 */
a27993f3 2626 if (pdev->broken_parity_status)
d03902b8
FR		 2627 pci_cmd &= ~PCI_COMMAND_PARITY;
2628 else
2629 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2630
2631 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2632
2633 pci_write_config_word(pdev, PCI_STATUS,
2634 pci_status & (PCI_STATUS_DETECTED_PARITY |
2635 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2636 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2637
2638 /* The infamous DAC f*ckup only happens at boot time */
2639 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2640 if (netif_msg_intr(tp))
2641 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2642 tp->cp_cmd &= ~PCIDAC;
2643 RTL_W16(CPlusCmd, tp->cp_cmd);
2644 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2645 }
2646
2647 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2648
2649 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2650}
2651
07d3f51f
FR		 2652static void rtl8169_tx_interrupt(struct net_device *dev,
2653 struct rtl8169_private *tp,
2654 void __iomem *ioaddr)
1da177e4
LT		 2655{
2656 unsigned int dirty_tx, tx_left;
2657
1da177e4
LT		 2658 dirty_tx = tp->dirty_tx;
2659 smp_rmb();
2660 tx_left = tp->cur_tx - dirty_tx;
2661
2662 while (tx_left > 0) {
2663 unsigned int entry = dirty_tx % NUM_TX_DESC;
2664 struct ring_info *tx_skb = tp->tx_skb + entry;
2665 u32 len = tx_skb->len;
2666 u32 status;
2667
2668 rmb();
2669 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2670 if (status & DescOwn)
2671 break;
2672
cebf8cc7
FR		 2673 dev->stats.tx_bytes += len;
2674 dev->stats.tx_packets++;
1da177e4
LT		 2675
2676 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2677
2678 if (status & LastFrag) {
2679 dev_kfree_skb_irq(tx_skb->skb);
2680 tx_skb->skb = NULL;
2681 }
2682 dirty_tx++;
2683 tx_left--;
2684 }
2685
2686 if (tp->dirty_tx != dirty_tx) {
2687 tp->dirty_tx = dirty_tx;
2688 smp_wmb();
2689 if (netif_queue_stopped(dev) &&
2690 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2691 netif_wake_queue(dev);
2692 }
d78ae2dc
FR		 2693 /*
2694 * 8168 hack: TxPoll requests are lost when the Tx packets are
2695 * too close. Let's kick an extra TxPoll request when a burst
2696 * of start_xmit activity is detected (if it is not detected,
2697 * it is slow enough). -- FR
2698 */
2699 smp_rmb();
2700 if (tp->cur_tx != dirty_tx)
2701 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 2702 }
2703}
2704
126fa4b9
FR		 2705static inline int rtl8169_fragmented_frame(u32 status)
2706{
2707 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2708}
2709
1da177e4
LT		 2710static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2711{
2712 u32 opts1 = le32_to_cpu(desc->opts1);
2713 u32 status = opts1 & RxProtoMask;
2714
2715 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2716 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2717 ((status == RxProtoIP) && !(opts1 & IPFail)))
2718 skb->ip_summed = CHECKSUM_UNNECESSARY;
2719 else
2720 skb->ip_summed = CHECKSUM_NONE;
2721}
2722
07d3f51f
FR		 2723static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2724 struct rtl8169_private *tp, int pkt_size,
2725 dma_addr_t addr)
1da177e4 2726{
b449655f
SH		 2727 struct sk_buff *skb;
2728 bool done = false;
1da177e4 2729
b449655f
SH		 2730 if (pkt_size >= rx_copybreak)
2731 goto out;
1da177e4 2732
07d3f51f 2733 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2734 if (!skb)
2735 goto out;
2736
07d3f51f
FR		 2737 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2738 PCI_DMA_FROMDEVICE);
86402234 2739 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2740 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2741 *sk_buff = skb;
2742 done = true;
2743out:
2744 return done;
1da177e4
LT		 2745}
2746
07d3f51f
FR		 2747static int rtl8169_rx_interrupt(struct net_device *dev,
2748 struct rtl8169_private *tp,
bea3348e 2749 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 2750{
2751 unsigned int cur_rx, rx_left;
2752 unsigned int delta, count;
2753
1da177e4
LT		 2754 cur_rx = tp->cur_rx;
2755 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 2756 rx_left = min(rx_left, budget);
1da177e4 2757
4dcb7d33 2758 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2759 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2760 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2761 u32 status;
2762
2763 rmb();
126fa4b9 2764 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2765
2766 if (status & DescOwn)
2767 break;
4dcb7d33 2768 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2769 if (netif_msg_rx_err(tp)) {
2770 printk(KERN_INFO
2771 "%s: Rx ERROR. status = %08x\n",
2772 dev->name, status);
2773 }
cebf8cc7 2774 dev->stats.rx_errors++;
1da177e4 2775 if (status & (RxRWT | RxRUNT))
cebf8cc7 2776 dev->stats.rx_length_errors++;
1da177e4 2777 if (status & RxCRC)
cebf8cc7 2778 dev->stats.rx_crc_errors++;
9dccf611
FR		 2779 if (status & RxFOVF) {
2780 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 2781 dev->stats.rx_fifo_errors++;
9dccf611 2782 }
126fa4b9 2783 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2784 } else {
1da177e4 2785 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2786 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2787 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2788 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2789
126fa4b9
FR		 2790 /*
2791 * The driver does not support incoming fragmented
2792 * frames. They are seen as a symptom of over-mtu
2793 * sized frames.
2794 */
2795 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 2796 dev->stats.rx_dropped++;
2797 dev->stats.rx_length_errors++;
126fa4b9 2798 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2799 continue;
126fa4b9
FR		 2800 }
2801
1da177e4 2802 rtl8169_rx_csum(skb, desc);
bcf0bf90 2803
07d3f51f 2804 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2805 pci_dma_sync_single_for_device(pdev, addr,
2806 pkt_size, PCI_DMA_FROMDEVICE);
2807 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2808 } else {
2809 pci_unmap_single(pdev, addr, pkt_size,
2810 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2811 tp->Rx_skbuff[entry] = NULL;
2812 }
2813
1da177e4
LT		 2814 skb_put(skb, pkt_size);
2815 skb->protocol = eth_type_trans(skb, dev);
2816
2817 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 2818 netif_receive_skb(skb);
1da177e4
LT		 2819
2820 dev->last_rx = jiffies;
cebf8cc7
FR		 2821 dev->stats.rx_bytes += pkt_size;
2822 dev->stats.rx_packets++;
1da177e4 2823 }
6dccd16b
FR		 2824
2825 /* Work around for AMD plateform. */
95e0918d 2826 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 2827 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2828 desc->opts2 = 0;
2829 cur_rx++;
2830 }
1da177e4
LT		 2831 }
2832
2833 count = cur_rx - tp->cur_rx;
2834 tp->cur_rx = cur_rx;
2835
2836 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2837 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2838 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2839 tp->dirty_rx += delta;
2840
2841 /*
2842 * FIXME: until there is periodic timer to try and refill the ring,
2843 * a temporary shortage may definitely kill the Rx process.
2844 * - disable the asic to try and avoid an overflow and kick it again
2845 * after refill ?
2846 * - how do others driver handle this condition (Uh oh...).
2847 */
b57b7e5a 2848 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2849 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2850
2851 return count;
2852}
2853
07d3f51f 2854static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2855{
07d3f51f 2856 struct net_device *dev = dev_instance;
1da177e4 2857 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 2858 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 2859 int handled = 0;
865c652d 2860 int status;
1da177e4 2861
865c652d 2862 status = RTL_R16(IntrStatus);
1da177e4 2863
865c652d
FR		 2864 /* hotplug/major error/no more work/shared irq */
2865 if ((status == 0xffff) || !status)
2866 goto out;
1da177e4 2867
865c652d 2868 handled = 1;
1da177e4 2869
865c652d
FR		 2870 if (unlikely(!netif_running(dev))) {
2871 rtl8169_asic_down(ioaddr);
2872 goto out;
2873 }
1da177e4 2874
865c652d
FR		 2875 status &= tp->intr_mask;
2876 RTL_W16(IntrStatus,
2877 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1da177e4 2878
865c652d
FR		 2879 if (!(status & tp->intr_event))
2880 goto out;
0e485150 2881
865c652d
FR		 2882 /* Work around for rx fifo overflow */
2883 if (unlikely(status & RxFIFOOver) &&
2884 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2885 netif_stop_queue(dev);
2886 rtl8169_tx_timeout(dev);
2887 goto out;
2888 }
1da177e4 2889
865c652d
FR		 2890 if (unlikely(status & SYSErr)) {
2891 rtl8169_pcierr_interrupt(dev);
2892 goto out;
2893 }
1da177e4 2894
865c652d
FR		 2895 if (status & LinkChg)
2896 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4 2897
865c652d
FR		 2898 if (status & tp->napi_event) {
2899 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2900 tp->intr_mask = ~tp->napi_event;
313b0305 2901
bea3348e
SH		 2902 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
2903 __netif_rx_schedule(dev, &tp->napi);
865c652d
FR		 2904 else if (netif_msg_intr(tp)) {
2905 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2906 dev->name, status);
b57b7e5a 2907 }
1da177e4
LT		 2908 }
2909out:
2910 return IRQ_RETVAL(handled);
2911}
2912
bea3348e 2913static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 2914{
bea3348e
SH		 2915 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
2916 struct net_device *dev = tp->dev;
1da177e4 2917 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 2918 int work_done;
1da177e4 2919
bea3348e 2920 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 2921 rtl8169_tx_interrupt(dev, tp, ioaddr);
2922
bea3348e
SH		 2923 if (work_done < budget) {
2924 netif_rx_complete(dev, napi);
1da177e4
LT		 2925 tp->intr_mask = 0xffff;
2926 /*
2927 * 20040426: the barrier is not strictly required but the
2928 * behavior of the irq handler could be less predictable
2929 * without it. Btw, the lack of flush for the posted pci
2930 * write is safe - FR
2931 */
2932 smp_wmb();
0e485150 2933 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2934 }
2935
bea3348e 2936 return work_done;
1da177e4 2937}
1da177e4
LT		 2938
2939static void rtl8169_down(struct net_device *dev)
2940{
2941 struct rtl8169_private *tp = netdev_priv(dev);
2942 void __iomem *ioaddr = tp->mmio_addr;
733b736c 2943 unsigned int intrmask;
1da177e4
LT		 2944
2945 rtl8169_delete_timer(dev);
2946
2947 netif_stop_queue(dev);
2948
93dd79e8 2949 napi_disable(&tp->napi);
93dd79e8 2950
1da177e4
LT		 2951core_down:
2952 spin_lock_irq(&tp->lock);
2953
2954 rtl8169_asic_down(ioaddr);
2955
2956 /* Update the error counts. */
cebf8cc7 2957 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 2958 RTL_W32(RxMissed, 0);
2959
2960 spin_unlock_irq(&tp->lock);
2961
2962 synchronize_irq(dev->irq);
2963
1da177e4 2964 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2965 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2966
2967 /*
2968 * And now for the 50k$ question: are IRQ disabled or not ?
2969 *
2970 * Two paths lead here:
2971 * 1) dev->close
2972 * -> netif_running() is available to sync the current code and the
2973 * IRQ handler. See rtl8169_interrupt for details.
2974 * 2) dev->change_mtu
2975 * -> rtl8169_poll can not be issued again and re-enable the
2976 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2977 *
2978 * No loop if hotpluged or major error (0xffff).
1da177e4 2979 */
733b736c
AP		 2980 intrmask = RTL_R16(IntrMask);
2981 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2982 goto core_down;
2983
2984 rtl8169_tx_clear(tp);
2985
2986 rtl8169_rx_clear(tp);
2987}
2988
2989static int rtl8169_close(struct net_device *dev)
2990{
2991 struct rtl8169_private *tp = netdev_priv(dev);
2992 struct pci_dev *pdev = tp->pci_dev;
2993
2994 rtl8169_down(dev);
2995
2996 free_irq(dev->irq, dev);
2997
1da177e4
LT		 2998 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2999 tp->RxPhyAddr);
3000 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3001 tp->TxPhyAddr);
3002 tp->TxDescArray = NULL;
3003 tp->RxDescArray = NULL;
3004
3005 return 0;
3006}
3007
07ce4064 3008static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3009{
3010 struct rtl8169_private *tp = netdev_priv(dev);
3011 void __iomem *ioaddr = tp->mmio_addr;
3012 unsigned long flags;
3013 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3014 int rx_mode;
1da177e4
LT		 3015 u32 tmp = 0;
3016
3017 if (dev->flags & IFF_PROMISC) {
3018 /* Unconditionally log net taps. */
b57b7e5a
SH		 3019 if (netif_msg_link(tp)) {
3020 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3021 dev->name);
3022 }
1da177e4
LT		 3023 rx_mode =
3024 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3025 AcceptAllPhys;
3026 mc_filter[1] = mc_filter[0] = 0xffffffff;
3027 } else if ((dev->mc_count > multicast_filter_limit)
3028 || (dev->flags & IFF_ALLMULTI)) {
3029 /* Too many to filter perfectly -- accept all multicasts. */
3030 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3031 mc_filter[1] = mc_filter[0] = 0xffffffff;
3032 } else {
3033 struct dev_mc_list *mclist;
07d3f51f
FR		 3034 unsigned int i;
3035
1da177e4
LT		 3036 rx_mode = AcceptBroadcast | AcceptMyPhys;
3037 mc_filter[1] = mc_filter[0] = 0;
3038 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3039 i++, mclist = mclist->next) {
3040 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3041 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3042 rx_mode |= AcceptMulticast;
3043 }
3044 }
3045
3046 spin_lock_irqsave(&tp->lock, flags);
3047
3048 tmp = rtl8169_rx_config | rx_mode |
3049 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3050
f887cce8 3051 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3052 u32 data = mc_filter[0];
3053
3054 mc_filter[0] = swab32(mc_filter[1]);
3055 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3056 }
3057
1da177e4
LT		 3058 RTL_W32(MAR0 + 0, mc_filter[0]);
3059 RTL_W32(MAR0 + 4, mc_filter[1]);
3060
57a9f236
FR		 3061 RTL_W32(RxConfig, tmp);
3062
1da177e4
LT		 3063 spin_unlock_irqrestore(&tp->lock, flags);
3064}
3065
3066/**
3067 * rtl8169_get_stats - Get rtl8169 read/write statistics
3068 * @dev: The Ethernet Device to get statistics for
3069 *
3070 * Get TX/RX statistics for rtl8169
3071 */
3072static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3073{
3074 struct rtl8169_private *tp = netdev_priv(dev);
3075 void __iomem *ioaddr = tp->mmio_addr;
3076 unsigned long flags;
3077
3078 if (netif_running(dev)) {
3079 spin_lock_irqsave(&tp->lock, flags);
cebf8cc7 3080 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
1da177e4
LT		 3081 RTL_W32(RxMissed, 0);
3082 spin_unlock_irqrestore(&tp->lock, flags);
3083 }
5b0384f4 3084
cebf8cc7 3085 return &dev->stats;
1da177e4
LT		 3086}
3087
5d06a99f
FR		 3088#ifdef CONFIG_PM
3089
3090static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3091{
3092 struct net_device *dev = pci_get_drvdata(pdev);
3093 struct rtl8169_private *tp = netdev_priv(dev);
3094 void __iomem *ioaddr = tp->mmio_addr;
3095
3096 if (!netif_running(dev))
1371fa6d 3097 goto out_pci_suspend;
5d06a99f
FR		 3098
3099 netif_device_detach(dev);
3100 netif_stop_queue(dev);
3101
3102 spin_lock_irq(&tp->lock);
3103
3104 rtl8169_asic_down(ioaddr);
3105
cebf8cc7 3106 dev->stats.rx_missed_errors += RTL_R32(RxMissed);
5d06a99f
FR		 3107 RTL_W32(RxMissed, 0);
3108
3109 spin_unlock_irq(&tp->lock);
3110
1371fa6d 3111out_pci_suspend:
5d06a99f 3112 pci_save_state(pdev);
f23e7fda
FR		 3113 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3114 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3115 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3116
5d06a99f
FR		 3117 return 0;
3118}
3119
3120static int rtl8169_resume(struct pci_dev *pdev)
3121{
3122 struct net_device *dev = pci_get_drvdata(pdev);
3123
1371fa6d
FR		 3124 pci_set_power_state(pdev, PCI_D0);
3125 pci_restore_state(pdev);
3126 pci_enable_wake(pdev, PCI_D0, 0);
3127
5d06a99f
FR		 3128 if (!netif_running(dev))
3129 goto out;
3130
3131 netif_device_attach(dev);
3132
5d06a99f
FR		 3133 rtl8169_schedule_work(dev, rtl8169_reset_task);
3134out:
3135 return 0;
3136}
3137
3138#endif /* CONFIG_PM */
3139
1da177e4
LT		 3140static struct pci_driver rtl8169_pci_driver = {
3141 .name = MODULENAME,
3142 .id_table = rtl8169_pci_tbl,
3143 .probe = rtl8169_init_one,
3144 .remove = __devexit_p(rtl8169_remove_one),
3145#ifdef CONFIG_PM
3146 .suspend = rtl8169_suspend,
3147 .resume = rtl8169_resume,
3148#endif
3149};
3150
07d3f51f 3151static int __init rtl8169_init_module(void)
1da177e4 3152{
29917620 3153 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3154}
3155
07d3f51f 3156static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3157{
3158 pci_unregister_driver(&rtl8169_pci_driver);
3159}
3160
3161module_init(rtl8169_init_module);
3162module_exit(rtl8169_cleanup_module);
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