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[mirror_ubuntu-zesty-kernel.git] / drivers / net / r8169.c
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1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
f7ccf420
SH		 31#ifdef CONFIG_R8169_NAPI
32#define NAPI_SUFFIX "-NAPI"
33#else
34#define NAPI_SUFFIX ""
35#endif
36
37#define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
1da177e4
LT		 38#define MODULENAME "r8169"
39#define PFX MODULENAME ": "
40
41#ifdef RTL8169_DEBUG
42#define assert(expr) \
5b0384f4
FR		 43 if (!(expr)) { \
44 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
45 #expr,__FILE__,__FUNCTION__,__LINE__); \
46 }
1da177e4
LT		 47#define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
48#else
49#define assert(expr) do {} while (0)
50#define dprintk(fmt, args...) do {} while (0)
51#endif /* RTL8169_DEBUG */
52
b57b7e5a 53#define R8169_MSG_DEFAULT \
f0e837d9 54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 55
1da177e4
LT		 56#define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
59#ifdef CONFIG_R8169_NAPI
60#define rtl8169_rx_skb netif_receive_skb
0b50f81d 61#define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
1da177e4
LT		 62#define rtl8169_rx_quota(count, quota) min(count, quota)
63#else
64#define rtl8169_rx_skb netif_rx
0b50f81d 65#define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
1da177e4
LT		 66#define rtl8169_rx_quota(count, quota) count
67#endif
68
1da177e4 69/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 70static const int max_interrupt_work = 20;
1da177e4
LT		 71
72/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
73 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 74static const int multicast_filter_limit = 32;
1da177e4
LT		 75
76/* MAC address length */
77#define MAC_ADDR_LEN 6
78
79#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
80#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
81#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 82#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 83#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
84#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
85#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
86
87#define R8169_REGS_SIZE 256
88#define R8169_NAPI_WEIGHT 64
89#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
90#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
91#define RX_BUF_SIZE 1536 /* Rx Buffer size */
92#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
93#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
94
95#define RTL8169_TX_TIMEOUT (6*HZ)
96#define RTL8169_PHY_TIMEOUT (10*HZ)
97
98/* write/read MMIO register */
99#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
100#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
101#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
102#define RTL_R8(reg) readb (ioaddr + (reg))
103#define RTL_R16(reg) readw (ioaddr + (reg))
104#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
105
106enum mac_version {
ba6eb6ee
FR		 107 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
108 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
109 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
110 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
111 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 112 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2dd99530
FR		 113 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
114 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be 8168Bf
cdf1a608
FR		 115 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb 8101Ec
116 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101
117 RTL_GIGA_MAC_VER_15 = 0x0f // 8101
1da177e4
LT		 118};
119
120enum phy_version {
121 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
122 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
123 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
124 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
125 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
126 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
127};
128
1da177e4
LT		 129#define _R(NAME,MAC,MASK) \
130 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
131
3c6bee1d 132static const struct {
1da177e4
LT		 133 const char *name;
134 u8 mac_version;
135 u32 RxConfigMask; /* Clears the bits supported by this chip */
136} rtl_chip_info[] = {
ba6eb6ee
FR		 137 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
138 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
139 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
140 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 142 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
bcf0bf90
FR		 143 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
144 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
146 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
147 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880) // PCI-E 8139
1da177e4
LT		 148};
149#undef _R
150
bcf0bf90
FR		 151enum cfg_version {
152 RTL_CFG_0 = 0x00,
153 RTL_CFG_1,
154 RTL_CFG_2
155};
156
07ce4064
FR		 157static void rtl_hw_start_8169(struct net_device *);
158static void rtl_hw_start_8168(struct net_device *);
159static void rtl_hw_start_8101(struct net_device *);
160
1da177e4 161static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 162 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 163 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 164 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 165 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 166 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
167 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
73f5e28b 168 { PCI_DEVICE(0x1259, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 169 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
170 { PCI_VENDOR_ID_LINKSYS, 0x1032,
171 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
1da177e4
LT		 172 {0,},
173};
174
175MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
176
177static int rx_copybreak = 200;
178static int use_dac;
b57b7e5a
SH		 179static struct {
180 u32 msg_enable;
181} debug = { -1 };
1da177e4 182
07d3f51f
FR		 183enum rtl_registers {
184 MAC0 = 0, /* Ethernet hardware address. */
773d2021 185 MAC4 = 4,
07d3f51f
FR		 186 MAR0 = 8, /* Multicast filter. */
187 CounterAddrLow = 0x10,
188 CounterAddrHigh = 0x14,
189 TxDescStartAddrLow = 0x20,
190 TxDescStartAddrHigh = 0x24,
191 TxHDescStartAddrLow = 0x28,
192 TxHDescStartAddrHigh = 0x2c,
193 FLASH = 0x30,
194 ERSR = 0x36,
195 ChipCmd = 0x37,
196 TxPoll = 0x38,
197 IntrMask = 0x3c,
198 IntrStatus = 0x3e,
199 TxConfig = 0x40,
200 RxConfig = 0x44,
201 RxMissed = 0x4c,
202 Cfg9346 = 0x50,
203 Config0 = 0x51,
204 Config1 = 0x52,
205 Config2 = 0x53,
206 Config3 = 0x54,
207 Config4 = 0x55,
208 Config5 = 0x56,
209 MultiIntr = 0x5c,
210 PHYAR = 0x60,
211 TBICSR = 0x64,
212 TBI_ANAR = 0x68,
213 TBI_LPAR = 0x6a,
214 PHYstatus = 0x6c,
215 RxMaxSize = 0xda,
216 CPlusCmd = 0xe0,
217 IntrMitigate = 0xe2,
218 RxDescAddrLow = 0xe4,
219 RxDescAddrHigh = 0xe8,
220 EarlyTxThres = 0xec,
221 FuncEvent = 0xf0,
222 FuncEventMask = 0xf4,
223 FuncPresetState = 0xf8,
224 FuncForceEvent = 0xfc,
1da177e4
LT		 225};
226
07d3f51f 227enum rtl_register_content {
1da177e4 228 /* InterruptStatusBits */
07d3f51f
FR		 229 SYSErr = 0x8000,
230 PCSTimeout = 0x4000,
231 SWInt = 0x0100,
232 TxDescUnavail = 0x0080,
233 RxFIFOOver = 0x0040,
234 LinkChg = 0x0020,
235 RxOverflow = 0x0010,
236 TxErr = 0x0008,
237 TxOK = 0x0004,
238 RxErr = 0x0002,
239 RxOK = 0x0001,
1da177e4
LT		 240
241 /* RxStatusDesc */
9dccf611
FR		 242 RxFOVF = (1 << 23),
243 RxRWT = (1 << 22),
244 RxRES = (1 << 21),
245 RxRUNT = (1 << 20),
246 RxCRC = (1 << 19),
1da177e4
LT		 247
248 /* ChipCmdBits */
07d3f51f
FR		 249 CmdReset = 0x10,
250 CmdRxEnb = 0x08,
251 CmdTxEnb = 0x04,
252 RxBufEmpty = 0x01,
1da177e4 253
275391a4
FR		 254 /* TXPoll register p.5 */
255 HPQ = 0x80, /* Poll cmd on the high prio queue */
256 NPQ = 0x40, /* Poll cmd on the low prio queue */
257 FSWInt = 0x01, /* Forced software interrupt */
258
1da177e4 259 /* Cfg9346Bits */
07d3f51f
FR		 260 Cfg9346_Lock = 0x00,
261 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 262
263 /* rx_mode_bits */
07d3f51f
FR		 264 AcceptErr = 0x20,
265 AcceptRunt = 0x10,
266 AcceptBroadcast = 0x08,
267 AcceptMulticast = 0x04,
268 AcceptMyPhys = 0x02,
269 AcceptAllPhys = 0x01,
1da177e4
LT		 270
271 /* RxConfigBits */
07d3f51f
FR		 272 RxCfgFIFOShift = 13,
273 RxCfgDMAShift = 8,
1da177e4
LT		 274
275 /* TxConfigBits */
276 TxInterFrameGapShift = 24,
277 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
278
5d06a99f
FR		 279 /* Config1 register p.24 */
280 PMEnable = (1 << 0), /* Power Management Enable */
281
6dccd16b
FR		 282 /* Config2 register p. 25 */
283 PCI_Clock_66MHz = 0x01,
284 PCI_Clock_33MHz = 0x00,
285
61a4dcc2
FR		 286 /* Config3 register p.25 */
287 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
288 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
289
5d06a99f 290 /* Config5 register p.27 */
61a4dcc2
FR		 291 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
292 MWF = (1 << 5), /* Accept Multicast wakeup frame */
293 UWF = (1 << 4), /* Accept Unicast wakeup frame */
294 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 295 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
296
1da177e4
LT		 297 /* TBICSR p.28 */
298 TBIReset = 0x80000000,
299 TBILoopback = 0x40000000,
300 TBINwEnable = 0x20000000,
301 TBINwRestart = 0x10000000,
302 TBILinkOk = 0x02000000,
303 TBINwComplete = 0x01000000,
304
305 /* CPlusCmd p.31 */
0e485150 306 PktCntrDisable = (1 << 7), // 8168
1da177e4
LT		 307 RxVlan = (1 << 6),
308 RxChkSum = (1 << 5),
309 PCIDAC = (1 << 4),
310 PCIMulRW = (1 << 3),
0e485150
FR		 311 INTT_0 = 0x0000, // 8168
312 INTT_1 = 0x0001, // 8168
313 INTT_2 = 0x0002, // 8168
314 INTT_3 = 0x0003, // 8168
1da177e4
LT		 315
316 /* rtl8169_PHYstatus */
07d3f51f
FR		 317 TBI_Enable = 0x80,
318 TxFlowCtrl = 0x40,
319 RxFlowCtrl = 0x20,
320 _1000bpsF = 0x10,
321 _100bps = 0x08,
322 _10bps = 0x04,
323 LinkStatus = 0x02,
324 FullDup = 0x01,
1da177e4 325
1da177e4 326 /* _TBICSRBit */
07d3f51f 327 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 328
329 /* DumpCounterCommand */
07d3f51f 330 CounterDump = 0x8,
1da177e4
LT		 331};
332
07d3f51f 333enum desc_status_bit {
1da177e4
LT		 334 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
335 RingEnd = (1 << 30), /* End of descriptor ring */
336 FirstFrag = (1 << 29), /* First segment of a packet */
337 LastFrag = (1 << 28), /* Final segment of a packet */
338
339 /* Tx private */
340 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
341 MSSShift = 16, /* MSS value position */
342 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
343 IPCS = (1 << 18), /* Calculate IP checksum */
344 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
345 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
346 TxVlanTag = (1 << 17), /* Add VLAN tag */
347
348 /* Rx private */
349 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
350 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
351
352#define RxProtoUDP (PID1)
353#define RxProtoTCP (PID0)
354#define RxProtoIP (PID1 | PID0)
355#define RxProtoMask RxProtoIP
356
357 IPFail = (1 << 16), /* IP checksum failed */
358 UDPFail = (1 << 15), /* UDP/IP checksum failed */
359 TCPFail = (1 << 14), /* TCP/IP checksum failed */
360 RxVlanTag = (1 << 16), /* VLAN tag available */
361};
362
363#define RsvdMask 0x3fffc000
364
365struct TxDesc {
6cccd6e7
REB		 366 __le32 opts1;
367 __le32 opts2;
368 __le64 addr;
1da177e4
LT		 369};
370
371struct RxDesc {
6cccd6e7
REB		 372 __le32 opts1;
373 __le32 opts2;
374 __le64 addr;
1da177e4
LT		 375};
376
377struct ring_info {
378 struct sk_buff *skb;
379 u32 len;
380 u8 __pad[sizeof(void *) - sizeof(u32)];
381};
382
383struct rtl8169_private {
384 void __iomem *mmio_addr; /* memory map physical address */
385 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 386 struct net_device *dev;
1da177e4
LT		 387 struct net_device_stats stats; /* statistics of net device */
388 spinlock_t lock; /* spin lock flag */
b57b7e5a 389 u32 msg_enable;
1da177e4
LT		 390 int chipset;
391 int mac_version;
392 int phy_version;
393 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
394 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
395 u32 dirty_rx;
396 u32 dirty_tx;
397 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
398 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
399 dma_addr_t TxPhyAddr;
400 dma_addr_t RxPhyAddr;
401 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
402 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 403 unsigned align;
1da177e4
LT		 404 unsigned rx_buf_sz;
405 struct timer_list timer;
406 u16 cp_cmd;
0e485150
FR		 407 u16 intr_event;
408 u16 napi_event;
1da177e4
LT		 409 u16 intr_mask;
410 int phy_auto_nego_reg;
411 int phy_1000_ctrl_reg;
412#ifdef CONFIG_R8169_VLAN
413 struct vlan_group *vlgrp;
414#endif
415 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
416 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
417 void (*phy_reset_enable)(void __iomem *);
07ce4064 418 void (*hw_start)(struct net_device *);
1da177e4
LT		 419 unsigned int (*phy_reset_pending)(void __iomem *);
420 unsigned int (*link_ok)(void __iomem *);
c4028958 421 struct delayed_work task;
61a4dcc2 422 unsigned wol_enabled : 1;
1da177e4
LT		 423};
424
979b6c13 425MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 426MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 427module_param(rx_copybreak, int, 0);
1b7efd58 428MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 429module_param(use_dac, int, 0);
430MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 431module_param_named(debug, debug.msg_enable, int, 0);
432MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 433MODULE_LICENSE("GPL");
434MODULE_VERSION(RTL8169_VERSION);
435
436static int rtl8169_open(struct net_device *dev);
437static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 438static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 439static int rtl8169_init_ring(struct net_device *dev);
07ce4064 440static void rtl_hw_start(struct net_device *dev);
1da177e4 441static int rtl8169_close(struct net_device *dev);
07ce4064 442static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 443static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 444static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4
LT		 445static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
446 void __iomem *);
4dcb7d33 447static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 448static void rtl8169_down(struct net_device *dev);
99f252b0 449static void rtl8169_rx_clear(struct rtl8169_private *tp);
1da177e4
LT		 450
451#ifdef CONFIG_R8169_NAPI
452static int rtl8169_poll(struct net_device *dev, int *budget);
453#endif
454
1da177e4 455static const unsigned int rtl8169_rx_config =
5b0384f4 456 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 457
07d3f51f 458static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 459{
460 int i;
461
07d3f51f 462 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0xFF) << 16 | value);
1da177e4 463
2371408c 464 for (i = 20; i > 0; i--) {
07d3f51f
FR		 465 /*
466 * Check if the RTL8169 has completed writing to the specified
467 * MII register.
468 */
5b0384f4 469 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 470 break;
2371408c 471 udelay(25);
1da177e4
LT		 472 }
473}
474
07d3f51f 475static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 476{
477 int i, value = -1;
478
07d3f51f 479 RTL_W32(PHYAR, 0x0 | (reg_addr & 0xFF) << 16);
1da177e4 480
2371408c 481 for (i = 20; i > 0; i--) {
07d3f51f
FR		 482 /*
483 * Check if the RTL8169 has completed retrieving data from
484 * the specified MII register.
485 */
1da177e4
LT		 486 if (RTL_R32(PHYAR) & 0x80000000) {
487 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
488 break;
489 }
2371408c 490 udelay(25);
1da177e4
LT		 491 }
492 return value;
493}
494
495static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
496{
497 RTL_W16(IntrMask, 0x0000);
498
499 RTL_W16(IntrStatus, 0xffff);
500}
501
502static void rtl8169_asic_down(void __iomem *ioaddr)
503{
504 RTL_W8(ChipCmd, 0x00);
505 rtl8169_irq_mask_and_ack(ioaddr);
506 RTL_R16(CPlusCmd);
507}
508
509static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
510{
511 return RTL_R32(TBICSR) & TBIReset;
512}
513
514static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
515{
64e4bfb4 516 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 517}
518
519static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
520{
521 return RTL_R32(TBICSR) & TBILinkOk;
522}
523
524static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
525{
526 return RTL_R8(PHYstatus) & LinkStatus;
527}
528
529static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
530{
531 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
532}
533
534static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
535{
536 unsigned int val;
537
9e0db8ef
FR		 538 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
539 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 540}
541
542static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 543 struct rtl8169_private *tp,
544 void __iomem *ioaddr)
1da177e4
LT		 545{
546 unsigned long flags;
547
548 spin_lock_irqsave(&tp->lock, flags);
549 if (tp->link_ok(ioaddr)) {
550 netif_carrier_on(dev);
b57b7e5a
SH		 551 if (netif_msg_ifup(tp))
552 printk(KERN_INFO PFX "%s: link up\n", dev->name);
553 } else {
554 if (netif_msg_ifdown(tp))
555 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 556 netif_carrier_off(dev);
b57b7e5a 557 }
1da177e4
LT		 558 spin_unlock_irqrestore(&tp->lock, flags);
559}
560
61a4dcc2
FR		 561static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
562{
563 struct rtl8169_private *tp = netdev_priv(dev);
564 void __iomem *ioaddr = tp->mmio_addr;
565 u8 options;
566
567 wol->wolopts = 0;
568
569#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
570 wol->supported = WAKE_ANY;
571
572 spin_lock_irq(&tp->lock);
573
574 options = RTL_R8(Config1);
575 if (!(options & PMEnable))
576 goto out_unlock;
577
578 options = RTL_R8(Config3);
579 if (options & LinkUp)
580 wol->wolopts |= WAKE_PHY;
581 if (options & MagicPacket)
582 wol->wolopts |= WAKE_MAGIC;
583
584 options = RTL_R8(Config5);
585 if (options & UWF)
586 wol->wolopts |= WAKE_UCAST;
587 if (options & BWF)
5b0384f4 588 wol->wolopts |= WAKE_BCAST;
61a4dcc2 589 if (options & MWF)
5b0384f4 590 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 591
592out_unlock:
593 spin_unlock_irq(&tp->lock);
594}
595
596static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
597{
598 struct rtl8169_private *tp = netdev_priv(dev);
599 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 600 unsigned int i;
61a4dcc2
FR		 601 static struct {
602 u32 opt;
603 u16 reg;
604 u8 mask;
605 } cfg[] = {
606 { WAKE_ANY, Config1, PMEnable },
607 { WAKE_PHY, Config3, LinkUp },
608 { WAKE_MAGIC, Config3, MagicPacket },
609 { WAKE_UCAST, Config5, UWF },
610 { WAKE_BCAST, Config5, BWF },
611 { WAKE_MCAST, Config5, MWF },
612 { WAKE_ANY, Config5, LanWake }
613 };
614
615 spin_lock_irq(&tp->lock);
616
617 RTL_W8(Cfg9346, Cfg9346_Unlock);
618
619 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
620 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
621 if (wol->wolopts & cfg[i].opt)
622 options |= cfg[i].mask;
623 RTL_W8(cfg[i].reg, options);
624 }
625
626 RTL_W8(Cfg9346, Cfg9346_Lock);
627
628 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
629
630 spin_unlock_irq(&tp->lock);
631
632 return 0;
633}
634
1da177e4
LT		 635static void rtl8169_get_drvinfo(struct net_device *dev,
636 struct ethtool_drvinfo *info)
637{
638 struct rtl8169_private *tp = netdev_priv(dev);
639
640 strcpy(info->driver, MODULENAME);
641 strcpy(info->version, RTL8169_VERSION);
642 strcpy(info->bus_info, pci_name(tp->pci_dev));
643}
644
645static int rtl8169_get_regs_len(struct net_device *dev)
646{
647 return R8169_REGS_SIZE;
648}
649
650static int rtl8169_set_speed_tbi(struct net_device *dev,
651 u8 autoneg, u16 speed, u8 duplex)
652{
653 struct rtl8169_private *tp = netdev_priv(dev);
654 void __iomem *ioaddr = tp->mmio_addr;
655 int ret = 0;
656 u32 reg;
657
658 reg = RTL_R32(TBICSR);
659 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
660 (duplex == DUPLEX_FULL)) {
661 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
662 } else if (autoneg == AUTONEG_ENABLE)
663 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
664 else {
b57b7e5a
SH		 665 if (netif_msg_link(tp)) {
666 printk(KERN_WARNING "%s: "
667 "incorrect speed setting refused in TBI mode\n",
668 dev->name);
669 }
1da177e4
LT		 670 ret = -EOPNOTSUPP;
671 }
672
673 return ret;
674}
675
676static int rtl8169_set_speed_xmii(struct net_device *dev,
677 u8 autoneg, u16 speed, u8 duplex)
678{
679 struct rtl8169_private *tp = netdev_priv(dev);
680 void __iomem *ioaddr = tp->mmio_addr;
681 int auto_nego, giga_ctrl;
682
64e4bfb4
FR		 683 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
684 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
685 ADVERTISE_100HALF | ADVERTISE_100FULL);
686 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
687 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 688
689 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 690 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
691 ADVERTISE_100HALF | ADVERTISE_100FULL);
692 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 693 } else {
694 if (speed == SPEED_10)
64e4bfb4 695 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 696 else if (speed == SPEED_100)
64e4bfb4 697 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 698 else if (speed == SPEED_1000)
64e4bfb4 699 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 700
701 if (duplex == DUPLEX_HALF)
64e4bfb4 702 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 703
704 if (duplex == DUPLEX_FULL)
64e4bfb4 705 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 706
707 /* This tweak comes straight from Realtek's driver. */
708 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
709 (tp->mac_version == RTL_GIGA_MAC_VER_13)) {
64e4bfb4 710 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 711 }
712 }
713
714 /* The 8100e/8101e do Fast Ethernet only. */
715 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
716 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
717 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
64e4bfb4 718 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 719 netif_msg_link(tp)) {
720 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
721 dev->name);
722 }
64e4bfb4 723 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 724 }
725
623a1593
FR		 726 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
727
2584fbc3
RS		 728 if (tp->mac_version == RTL_GIGA_MAC_VER_12) {
729 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
730 mdio_write(ioaddr, 0x1f, 0x0000);
731 mdio_write(ioaddr, 0x0e, 0x0000);
732 }
733
1da177e4
LT		 734 tp->phy_auto_nego_reg = auto_nego;
735 tp->phy_1000_ctrl_reg = giga_ctrl;
736
64e4bfb4
FR		 737 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
738 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
739 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 740 return 0;
741}
742
743static int rtl8169_set_speed(struct net_device *dev,
744 u8 autoneg, u16 speed, u8 duplex)
745{
746 struct rtl8169_private *tp = netdev_priv(dev);
747 int ret;
748
749 ret = tp->set_speed(dev, autoneg, speed, duplex);
750
64e4bfb4 751 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 752 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
753
754 return ret;
755}
756
757static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
758{
759 struct rtl8169_private *tp = netdev_priv(dev);
760 unsigned long flags;
761 int ret;
762
763 spin_lock_irqsave(&tp->lock, flags);
764 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
765 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 766
1da177e4
LT		 767 return ret;
768}
769
770static u32 rtl8169_get_rx_csum(struct net_device *dev)
771{
772 struct rtl8169_private *tp = netdev_priv(dev);
773
774 return tp->cp_cmd & RxChkSum;
775}
776
777static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
778{
779 struct rtl8169_private *tp = netdev_priv(dev);
780 void __iomem *ioaddr = tp->mmio_addr;
781 unsigned long flags;
782
783 spin_lock_irqsave(&tp->lock, flags);
784
785 if (data)
786 tp->cp_cmd |= RxChkSum;
787 else
788 tp->cp_cmd &= ~RxChkSum;
789
790 RTL_W16(CPlusCmd, tp->cp_cmd);
791 RTL_R16(CPlusCmd);
792
793 spin_unlock_irqrestore(&tp->lock, flags);
794
795 return 0;
796}
797
798#ifdef CONFIG_R8169_VLAN
799
800static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
801 struct sk_buff *skb)
802{
803 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
804 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
805}
806
807static void rtl8169_vlan_rx_register(struct net_device *dev,
808 struct vlan_group *grp)
809{
810 struct rtl8169_private *tp = netdev_priv(dev);
811 void __iomem *ioaddr = tp->mmio_addr;
812 unsigned long flags;
813
814 spin_lock_irqsave(&tp->lock, flags);
815 tp->vlgrp = grp;
816 if (tp->vlgrp)
817 tp->cp_cmd |= RxVlan;
818 else
819 tp->cp_cmd &= ~RxVlan;
820 RTL_W16(CPlusCmd, tp->cp_cmd);
821 RTL_R16(CPlusCmd);
822 spin_unlock_irqrestore(&tp->lock, flags);
823}
824
1da177e4
LT		 825static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
826 struct sk_buff *skb)
827{
828 u32 opts2 = le32_to_cpu(desc->opts2);
829 int ret;
830
831 if (tp->vlgrp && (opts2 & RxVlanTag)) {
07d3f51f 832 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 833 ret = 0;
834 } else
835 ret = -1;
836 desc->opts2 = 0;
837 return ret;
838}
839
840#else /* !CONFIG_R8169_VLAN */
841
842static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
843 struct sk_buff *skb)
844{
845 return 0;
846}
847
848static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
849 struct sk_buff *skb)
850{
851 return -1;
852}
853
854#endif
855
856static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
857{
858 struct rtl8169_private *tp = netdev_priv(dev);
859 void __iomem *ioaddr = tp->mmio_addr;
860 u32 status;
861
862 cmd->supported =
863 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
864 cmd->port = PORT_FIBRE;
865 cmd->transceiver = XCVR_INTERNAL;
866
867 status = RTL_R32(TBICSR);
868 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
869 cmd->autoneg = !!(status & TBINwEnable);
870
871 cmd->speed = SPEED_1000;
872 cmd->duplex = DUPLEX_FULL; /* Always set */
873}
874
875static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
876{
877 struct rtl8169_private *tp = netdev_priv(dev);
878 void __iomem *ioaddr = tp->mmio_addr;
879 u8 status;
880
881 cmd->supported = SUPPORTED_10baseT_Half |
882 SUPPORTED_10baseT_Full |
883 SUPPORTED_100baseT_Half |
884 SUPPORTED_100baseT_Full |
885 SUPPORTED_1000baseT_Full |
886 SUPPORTED_Autoneg |
5b0384f4 887 SUPPORTED_TP;
1da177e4
LT		 888
889 cmd->autoneg = 1;
890 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
891
64e4bfb4 892 if (tp->phy_auto_nego_reg & ADVERTISE_10HALF)
1da177e4 893 cmd->advertising |= ADVERTISED_10baseT_Half;
64e4bfb4 894 if (tp->phy_auto_nego_reg & ADVERTISE_10FULL)
1da177e4 895 cmd->advertising |= ADVERTISED_10baseT_Full;
64e4bfb4 896 if (tp->phy_auto_nego_reg & ADVERTISE_100HALF)
1da177e4 897 cmd->advertising |= ADVERTISED_100baseT_Half;
64e4bfb4 898 if (tp->phy_auto_nego_reg & ADVERTISE_100FULL)
1da177e4 899 cmd->advertising |= ADVERTISED_100baseT_Full;
64e4bfb4 900 if (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)
1da177e4
LT		 901 cmd->advertising |= ADVERTISED_1000baseT_Full;
902
903 status = RTL_R8(PHYstatus);
904
905 if (status & _1000bpsF)
906 cmd->speed = SPEED_1000;
907 else if (status & _100bps)
908 cmd->speed = SPEED_100;
909 else if (status & _10bps)
910 cmd->speed = SPEED_10;
911
623a1593
FR		 912 if (status & TxFlowCtrl)
913 cmd->advertising |= ADVERTISED_Asym_Pause;
914 if (status & RxFlowCtrl)
915 cmd->advertising |= ADVERTISED_Pause;
916
1da177e4
LT		 917 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
918 DUPLEX_FULL : DUPLEX_HALF;
919}
920
921static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
922{
923 struct rtl8169_private *tp = netdev_priv(dev);
924 unsigned long flags;
925
926 spin_lock_irqsave(&tp->lock, flags);
927
928 tp->get_settings(dev, cmd);
929
930 spin_unlock_irqrestore(&tp->lock, flags);
931 return 0;
932}
933
934static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
935 void *p)
936{
5b0384f4
FR		 937 struct rtl8169_private *tp = netdev_priv(dev);
938 unsigned long flags;
1da177e4 939
5b0384f4
FR		 940 if (regs->len > R8169_REGS_SIZE)
941 regs->len = R8169_REGS_SIZE;
1da177e4 942
5b0384f4
FR		 943 spin_lock_irqsave(&tp->lock, flags);
944 memcpy_fromio(p, tp->mmio_addr, regs->len);
945 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 946}
947
b57b7e5a
SH		 948static u32 rtl8169_get_msglevel(struct net_device *dev)
949{
950 struct rtl8169_private *tp = netdev_priv(dev);
951
952 return tp->msg_enable;
953}
954
955static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
956{
957 struct rtl8169_private *tp = netdev_priv(dev);
958
959 tp->msg_enable = value;
960}
961
d4a3a0fc
SH		 962static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
963 "tx_packets",
964 "rx_packets",
965 "tx_errors",
966 "rx_errors",
967 "rx_missed",
968 "align_errors",
969 "tx_single_collisions",
970 "tx_multi_collisions",
971 "unicast",
972 "broadcast",
973 "multicast",
974 "tx_aborted",
975 "tx_underrun",
976};
977
978struct rtl8169_counters {
979 u64 tx_packets;
980 u64 rx_packets;
981 u64 tx_errors;
982 u32 rx_errors;
983 u16 rx_missed;
984 u16 align_errors;
985 u32 tx_one_collision;
986 u32 tx_multi_collision;
987 u64 rx_unicast;
988 u64 rx_broadcast;
989 u32 rx_multicast;
990 u16 tx_aborted;
991 u16 tx_underun;
992};
993
994static int rtl8169_get_stats_count(struct net_device *dev)
995{
996 return ARRAY_SIZE(rtl8169_gstrings);
997}
998
999static void rtl8169_get_ethtool_stats(struct net_device *dev,
1000 struct ethtool_stats *stats, u64 *data)
1001{
1002 struct rtl8169_private *tp = netdev_priv(dev);
1003 void __iomem *ioaddr = tp->mmio_addr;
1004 struct rtl8169_counters *counters;
1005 dma_addr_t paddr;
1006 u32 cmd;
1007
1008 ASSERT_RTNL();
1009
1010 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1011 if (!counters)
1012 return;
1013
1014 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1015 cmd = (u64)paddr & DMA_32BIT_MASK;
1016 RTL_W32(CounterAddrLow, cmd);
1017 RTL_W32(CounterAddrLow, cmd | CounterDump);
1018
1019 while (RTL_R32(CounterAddrLow) & CounterDump) {
1020 if (msleep_interruptible(1))
1021 break;
1022 }
1023
1024 RTL_W32(CounterAddrLow, 0);
1025 RTL_W32(CounterAddrHigh, 0);
1026
5b0384f4 1027 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1028 data[1] = le64_to_cpu(counters->rx_packets);
1029 data[2] = le64_to_cpu(counters->tx_errors);
1030 data[3] = le32_to_cpu(counters->rx_errors);
1031 data[4] = le16_to_cpu(counters->rx_missed);
1032 data[5] = le16_to_cpu(counters->align_errors);
1033 data[6] = le32_to_cpu(counters->tx_one_collision);
1034 data[7] = le32_to_cpu(counters->tx_multi_collision);
1035 data[8] = le64_to_cpu(counters->rx_unicast);
1036 data[9] = le64_to_cpu(counters->rx_broadcast);
1037 data[10] = le32_to_cpu(counters->rx_multicast);
1038 data[11] = le16_to_cpu(counters->tx_aborted);
1039 data[12] = le16_to_cpu(counters->tx_underun);
1040
1041 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1042}
1043
1044static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1045{
1046 switch(stringset) {
1047 case ETH_SS_STATS:
1048 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1049 break;
1050 }
1051}
1052
7282d491 1053static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1054 .get_drvinfo = rtl8169_get_drvinfo,
1055 .get_regs_len = rtl8169_get_regs_len,
1056 .get_link = ethtool_op_get_link,
1057 .get_settings = rtl8169_get_settings,
1058 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1059 .get_msglevel = rtl8169_get_msglevel,
1060 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1061 .get_rx_csum = rtl8169_get_rx_csum,
1062 .set_rx_csum = rtl8169_set_rx_csum,
1063 .get_tx_csum = ethtool_op_get_tx_csum,
1064 .set_tx_csum = ethtool_op_set_tx_csum,
1065 .get_sg = ethtool_op_get_sg,
1066 .set_sg = ethtool_op_set_sg,
1067 .get_tso = ethtool_op_get_tso,
1068 .set_tso = ethtool_op_set_tso,
1069 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1070 .get_wol = rtl8169_get_wol,
1071 .set_wol = rtl8169_set_wol,
d4a3a0fc
SH		 1072 .get_strings = rtl8169_get_strings,
1073 .get_stats_count = rtl8169_get_stats_count,
1074 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1075};
1076
07d3f51f
FR		 1077static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1078 int bitnum, int bitval)
1da177e4
LT		 1079{
1080 int val;
1081
1082 val = mdio_read(ioaddr, reg);
1083 val = (bitval == 1) ?
1084 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1085 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1086}
1087
07d3f51f
FR		 1088static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1089 void __iomem *ioaddr)
1da177e4 1090{
0e485150
FR		 1091 /*
1092 * The driver currently handles the 8168Bf and the 8168Be identically
1093 * but they can be identified more specifically through the test below
1094 * if needed:
1095 *
1096 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1097 *
1098 * Same thing for the 8101Eb and the 8101Ec:
1099 *
1100 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1101 */
1da177e4
LT		 1102 const struct {
1103 u32 mask;
1104 int mac_version;
1105 } mac_info[] = {
bcf0bf90
FR		 1106 { 0x38800000, RTL_GIGA_MAC_VER_15 },
1107 { 0x38000000, RTL_GIGA_MAC_VER_12 },
1108 { 0x34000000, RTL_GIGA_MAC_VER_13 },
1109 { 0x30800000, RTL_GIGA_MAC_VER_14 },
5b0384f4 1110 { 0x30000000, RTL_GIGA_MAC_VER_11 },
6dccd16b 1111 { 0x98000000, RTL_GIGA_MAC_VER_06 },
bcf0bf90
FR		 1112 { 0x18000000, RTL_GIGA_MAC_VER_05 },
1113 { 0x10000000, RTL_GIGA_MAC_VER_04 },
1114 { 0x04000000, RTL_GIGA_MAC_VER_03 },
1115 { 0x00800000, RTL_GIGA_MAC_VER_02 },
1116 { 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1117 }, *p = mac_info;
1118 u32 reg;
1119
6dccd16b 1120 reg = RTL_R32(TxConfig) & 0xfc800000;
1da177e4
LT		 1121 while ((reg & p->mask) != p->mask)
1122 p++;
1123 tp->mac_version = p->mac_version;
1124}
1125
1126static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1127{
bcf0bf90 1128 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1129}
1130
07d3f51f
FR		 1131static void rtl8169_get_phy_version(struct rtl8169_private *tp,
1132 void __iomem *ioaddr)
1da177e4
LT		 1133{
1134 const struct {
1135 u16 mask;
1136 u16 set;
1137 int phy_version;
1138 } phy_info[] = {
1139 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1140 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1141 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1142 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1143 }, *p = phy_info;
1144 u16 reg;
1145
64e4bfb4 1146 reg = mdio_read(ioaddr, MII_PHYSID2) & 0xffff;
1da177e4
LT		 1147 while ((reg & p->mask) != p->set)
1148 p++;
1149 tp->phy_version = p->phy_version;
1150}
1151
1152static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1153{
1154 struct {
1155 int version;
1156 char *msg;
1157 u32 reg;
1158 } phy_print[] = {
1159 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1160 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1161 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1162 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1163 { 0, NULL, 0x0000 }
1164 }, *p;
1165
1166 for (p = phy_print; p->msg; p++) {
1167 if (tp->phy_version == p->version) {
1168 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1169 return;
1170 }
1171 }
1172 dprintk("phy_version == Unknown\n");
1173}
1174
1175static void rtl8169_hw_phy_config(struct net_device *dev)
1176{
1177 struct rtl8169_private *tp = netdev_priv(dev);
1178 void __iomem *ioaddr = tp->mmio_addr;
1179 struct {
1180 u16 regs[5]; /* Beware of bit-sign propagation */
1181 } phy_magic[5] = { {
1182 { 0x0000, //w 4 15 12 0
1183 0x00a1, //w 3 15 0 00a1
1184 0x0008, //w 2 15 0 0008
1185 0x1020, //w 1 15 0 1020
1186 0x1000 } },{ //w 0 15 0 1000
1187 { 0x7000, //w 4 15 12 7
1188 0xff41, //w 3 15 0 ff41
1189 0xde60, //w 2 15 0 de60
1190 0x0140, //w 1 15 0 0140
1191 0x0077 } },{ //w 0 15 0 0077
1192 { 0xa000, //w 4 15 12 a
1193 0xdf01, //w 3 15 0 df01
1194 0xdf20, //w 2 15 0 df20
1195 0xff95, //w 1 15 0 ff95
1196 0xfa00 } },{ //w 0 15 0 fa00
1197 { 0xb000, //w 4 15 12 b
1198 0xff41, //w 3 15 0 ff41
1199 0xde20, //w 2 15 0 de20
1200 0x0140, //w 1 15 0 0140
1201 0x00bb } },{ //w 0 15 0 00bb
1202 { 0xf000, //w 4 15 12 f
1203 0xdf01, //w 3 15 0 df01
1204 0xdf20, //w 2 15 0 df20
1205 0xff95, //w 1 15 0 ff95
1206 0xbf00 } //w 0 15 0 bf00
1207 }
1208 }, *p = phy_magic;
07d3f51f 1209 unsigned int i;
1da177e4
LT		 1210
1211 rtl8169_print_mac_version(tp);
1212 rtl8169_print_phy_version(tp);
1213
bcf0bf90 1214 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1215 return;
1216 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1217 return;
1218
1219 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1220 dprintk("Do final_reg2.cfg\n");
1221
1222 /* Shazam ! */
1223
bcf0bf90 1224 if (tp->mac_version == RTL_GIGA_MAC_VER_04) {
1da177e4
LT		 1225 mdio_write(ioaddr, 31, 0x0002);
1226 mdio_write(ioaddr, 1, 0x90d0);
1227 mdio_write(ioaddr, 31, 0x0000);
1228 return;
1229 }
1230
1231 /* phy config for RTL8169s mac_version C chip */
1232 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1233 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1234 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1235 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1236
1237 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1238 int val, pos = 4;
1239
1240 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1241 mdio_write(ioaddr, pos, val);
1242 while (--pos >= 0)
1243 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1244 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1245 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1246 }
1247 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1248}
1249
1250static void rtl8169_phy_timer(unsigned long __opaque)
1251{
1252 struct net_device *dev = (struct net_device *)__opaque;
1253 struct rtl8169_private *tp = netdev_priv(dev);
1254 struct timer_list *timer = &tp->timer;
1255 void __iomem *ioaddr = tp->mmio_addr;
1256 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1257
bcf0bf90 1258 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4
LT		 1259 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1260
64e4bfb4 1261 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1262 return;
1263
1264 spin_lock_irq(&tp->lock);
1265
1266 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1267 /*
1da177e4
LT		 1268 * A busy loop could burn quite a few cycles on nowadays CPU.
1269 * Let's delay the execution of the timer for a few ticks.
1270 */
1271 timeout = HZ/10;
1272 goto out_mod_timer;
1273 }
1274
1275 if (tp->link_ok(ioaddr))
1276 goto out_unlock;
1277
b57b7e5a
SH		 1278 if (netif_msg_link(tp))
1279 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1280
1281 tp->phy_reset_enable(ioaddr);
1282
1283out_mod_timer:
1284 mod_timer(timer, jiffies + timeout);
1285out_unlock:
1286 spin_unlock_irq(&tp->lock);
1287}
1288
1289static inline void rtl8169_delete_timer(struct net_device *dev)
1290{
1291 struct rtl8169_private *tp = netdev_priv(dev);
1292 struct timer_list *timer = &tp->timer;
1293
bcf0bf90 1294 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1295 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1296 return;
1297
1298 del_timer_sync(timer);
1299}
1300
1301static inline void rtl8169_request_timer(struct net_device *dev)
1302{
1303 struct rtl8169_private *tp = netdev_priv(dev);
1304 struct timer_list *timer = &tp->timer;
1305
bcf0bf90 1306 if ((tp->mac_version <= RTL_GIGA_MAC_VER_01) ||
1da177e4
LT		 1307 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1308 return;
1309
2efa53f3 1310 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1311}
1312
1313#ifdef CONFIG_NET_POLL_CONTROLLER
1314/*
1315 * Polling 'interrupt' - used by things like netconsole to send skbs
1316 * without having to re-enable interrupts. It's not called while
1317 * the interrupt routine is executing.
1318 */
1319static void rtl8169_netpoll(struct net_device *dev)
1320{
1321 struct rtl8169_private *tp = netdev_priv(dev);
1322 struct pci_dev *pdev = tp->pci_dev;
1323
1324 disable_irq(pdev->irq);
7d12e780 1325 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1326 enable_irq(pdev->irq);
1327}
1328#endif
1329
1330static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1331 void __iomem *ioaddr)
1332{
1333 iounmap(ioaddr);
1334 pci_release_regions(pdev);
1335 pci_disable_device(pdev);
1336 free_netdev(dev);
1337}
1338
bf793295
FR		 1339static void rtl8169_phy_reset(struct net_device *dev,
1340 struct rtl8169_private *tp)
1341{
1342 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1343 unsigned int i;
bf793295
FR		 1344
1345 tp->phy_reset_enable(ioaddr);
1346 for (i = 0; i < 100; i++) {
1347 if (!tp->phy_reset_pending(ioaddr))
1348 return;
1349 msleep(1);
1350 }
1351 if (netif_msg_link(tp))
1352 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1353}
1354
4ff96fa6
FR		 1355static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1356{
1357 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6
FR		 1358
1359 rtl8169_hw_phy_config(dev);
1360
1361 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1362 RTL_W8(0x82, 0x01);
1363
6dccd16b
FR		 1364 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1365
1366 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1367 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1368
bcf0bf90 1369 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1370 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1371 RTL_W8(0x82, 0x01);
1372 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1373 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1374 }
1375
bf793295
FR		 1376 rtl8169_phy_reset(dev, tp);
1377
901dda2b
FR		 1378 /*
1379 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1380 * only 8101. Don't panic.
1381 */
1382 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1383
1384 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1385 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1386}
1387
773d2021
FR		 1388static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1389{
1390 void __iomem *ioaddr = tp->mmio_addr;
1391 u32 high;
1392 u32 low;
1393
1394 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1395 high = addr[4] | (addr[5] << 8);
1396
1397 spin_lock_irq(&tp->lock);
1398
1399 RTL_W8(Cfg9346, Cfg9346_Unlock);
1400 RTL_W32(MAC0, low);
1401 RTL_W32(MAC4, high);
1402 RTL_W8(Cfg9346, Cfg9346_Lock);
1403
1404 spin_unlock_irq(&tp->lock);
1405}
1406
1407static int rtl_set_mac_address(struct net_device *dev, void *p)
1408{
1409 struct rtl8169_private *tp = netdev_priv(dev);
1410 struct sockaddr *addr = p;
1411
1412 if (!is_valid_ether_addr(addr->sa_data))
1413 return -EADDRNOTAVAIL;
1414
1415 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1416
1417 rtl_rar_set(tp, dev->dev_addr);
1418
1419 return 0;
1420}
1421
5f787a1a
FR		 1422static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1423{
1424 struct rtl8169_private *tp = netdev_priv(dev);
1425 struct mii_ioctl_data *data = if_mii(ifr);
1426
1427 if (!netif_running(dev))
1428 return -ENODEV;
1429
1430 switch (cmd) {
1431 case SIOCGMIIPHY:
1432 data->phy_id = 32; /* Internal PHY */
1433 return 0;
1434
1435 case SIOCGMIIREG:
1436 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1437 return 0;
1438
1439 case SIOCSMIIREG:
1440 if (!capable(CAP_NET_ADMIN))
1441 return -EPERM;
1442 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1443 return 0;
1444 }
1445 return -EOPNOTSUPP;
1446}
1447
0e485150
FR		 1448static const struct rtl_cfg_info {
1449 void (*hw_start)(struct net_device *);
1450 unsigned int region;
1451 unsigned int align;
1452 u16 intr_event;
1453 u16 napi_event;
1454} rtl_cfg_infos [] = {
1455 [RTL_CFG_0] = {
1456 .hw_start = rtl_hw_start_8169,
1457 .region = 1,
e9f63f30 1458 .align = 0,
0e485150
FR		 1459 .intr_event = SYSErr | LinkChg | RxOverflow |
1460 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1461 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1462 },
1463 [RTL_CFG_1] = {
1464 .hw_start = rtl_hw_start_8168,
1465 .region = 2,
1466 .align = 8,
1467 .intr_event = SYSErr | LinkChg | RxOverflow |
1468 TxErr | TxOK | RxOK | RxErr,
1469 .napi_event = TxErr | TxOK | RxOK | RxOverflow
1470 },
1471 [RTL_CFG_2] = {
1472 .hw_start = rtl_hw_start_8101,
1473 .region = 2,
1474 .align = 8,
1475 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1476 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1477 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow
1478 }
1479};
1480
1da177e4 1481static int __devinit
4ff96fa6 1482rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1483{
0e485150
FR		 1484 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1485 const unsigned int region = cfg->region;
1da177e4 1486 struct rtl8169_private *tp;
4ff96fa6
FR		 1487 struct net_device *dev;
1488 void __iomem *ioaddr;
07d3f51f
FR		 1489 unsigned int i;
1490 int rc;
1da177e4 1491
4ff96fa6
FR		 1492 if (netif_msg_drv(&debug)) {
1493 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1494 MODULENAME, RTL8169_VERSION);
1495 }
1da177e4 1496
1da177e4 1497 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1498 if (!dev) {
b57b7e5a 1499 if (netif_msg_drv(&debug))
9b91cf9d 1500 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1501 rc = -ENOMEM;
1502 goto out;
1da177e4
LT		 1503 }
1504
1505 SET_MODULE_OWNER(dev);
1506 SET_NETDEV_DEV(dev, &pdev->dev);
1507 tp = netdev_priv(dev);
c4028958 1508 tp->dev = dev;
b57b7e5a 1509 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4
LT		 1510
1511 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1512 rc = pci_enable_device(pdev);
b57b7e5a 1513 if (rc < 0) {
2e8a538d 1514 if (netif_msg_probe(tp))
9b91cf9d 1515 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1516 goto err_out_free_dev_1;
1da177e4
LT		 1517 }
1518
1519 rc = pci_set_mwi(pdev);
1520 if (rc < 0)
4ff96fa6 1521 goto err_out_disable_2;
1da177e4 1522
1da177e4 1523 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1524 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1525 if (netif_msg_probe(tp)) {
9b91cf9d 1526 dev_err(&pdev->dev,
bcf0bf90
FR		 1527 "region #%d not an MMIO resource, aborting\n",
1528 region);
4ff96fa6 1529 }
1da177e4 1530 rc = -ENODEV;
4ff96fa6 1531 goto err_out_mwi_3;
1da177e4 1532 }
4ff96fa6 1533
1da177e4 1534 /* check for weird/broken PCI region reporting */
bcf0bf90 1535 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1536 if (netif_msg_probe(tp)) {
9b91cf9d 1537 dev_err(&pdev->dev,
4ff96fa6
FR		 1538 "Invalid PCI region size(s), aborting\n");
1539 }
1da177e4 1540 rc = -ENODEV;
4ff96fa6 1541 goto err_out_mwi_3;
1da177e4
LT		 1542 }
1543
1544 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1545 if (rc < 0) {
2e8a538d 1546 if (netif_msg_probe(tp))
9b91cf9d 1547 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1548 goto err_out_mwi_3;
1da177e4
LT		 1549 }
1550
1551 tp->cp_cmd = PCIMulRW | RxChkSum;
1552
1553 if ((sizeof(dma_addr_t) > 4) &&
1554 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1555 tp->cp_cmd |= PCIDAC;
1556 dev->features |= NETIF_F_HIGHDMA;
1557 } else {
1558 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1559 if (rc < 0) {
4ff96fa6 1560 if (netif_msg_probe(tp)) {
9b91cf9d 1561 dev_err(&pdev->dev,
4ff96fa6
FR		 1562 "DMA configuration failed.\n");
1563 }
1564 goto err_out_free_res_4;
1da177e4
LT		 1565 }
1566 }
1567
1568 pci_set_master(pdev);
1569
1570 /* ioremap MMIO region */
bcf0bf90 1571 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1572 if (!ioaddr) {
b57b7e5a 1573 if (netif_msg_probe(tp))
9b91cf9d 1574 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1575 rc = -EIO;
4ff96fa6 1576 goto err_out_free_res_4;
1da177e4
LT		 1577 }
1578
1579 /* Unneeded ? Don't mess with Mrs. Murphy. */
1580 rtl8169_irq_mask_and_ack(ioaddr);
1581
1582 /* Soft reset the chip. */
1583 RTL_W8(ChipCmd, CmdReset);
1584
1585 /* Check that the chip has finished the reset. */
07d3f51f 1586 for (i = 0; i < 100; i++) {
1da177e4
LT		 1587 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1588 break;
b518fa8e 1589 msleep_interruptible(1);
1da177e4
LT		 1590 }
1591
1592 /* Identify chip attached to board */
1593 rtl8169_get_mac_version(tp, ioaddr);
1594 rtl8169_get_phy_version(tp, ioaddr);
1595
1596 rtl8169_print_mac_version(tp);
1597 rtl8169_print_phy_version(tp);
1598
1599 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1600 if (tp->mac_version == rtl_chip_info[i].mac_version)
1601 break;
1602 }
1603 if (i < 0) {
1604 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1605 if (netif_msg_probe(tp)) {
2e8a538d 1606 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1607 "unknown chip version, assuming %s\n",
1608 rtl_chip_info[0].name);
b57b7e5a 1609 }
1da177e4
LT		 1610 i++;
1611 }
1612 tp->chipset = i;
1613
5d06a99f
FR		 1614 RTL_W8(Cfg9346, Cfg9346_Unlock);
1615 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1616 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1617 RTL_W8(Cfg9346, Cfg9346_Lock);
1618
1da177e4
LT		 1619 if (RTL_R8(PHYstatus) & TBI_Enable) {
1620 tp->set_speed = rtl8169_set_speed_tbi;
1621 tp->get_settings = rtl8169_gset_tbi;
1622 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1623 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1624 tp->link_ok = rtl8169_tbi_link_ok;
1625
64e4bfb4 1626 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1627 } else {
1628 tp->set_speed = rtl8169_set_speed_xmii;
1629 tp->get_settings = rtl8169_gset_xmii;
1630 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1631 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1632 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1633
1634 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1635 }
1636
1637 /* Get MAC address. FIXME: read EEPROM */
1638 for (i = 0; i < MAC_ADDR_LEN; i++)
1639 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1640 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1641
1642 dev->open = rtl8169_open;
1643 dev->hard_start_xmit = rtl8169_start_xmit;
1644 dev->get_stats = rtl8169_get_stats;
1645 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1646 dev->stop = rtl8169_close;
1647 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1648 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1649 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1650 dev->irq = pdev->irq;
1651 dev->base_addr = (unsigned long) ioaddr;
1652 dev->change_mtu = rtl8169_change_mtu;
773d2021 1653 dev->set_mac_address = rtl_set_mac_address;
1da177e4
LT		 1654
1655#ifdef CONFIG_R8169_NAPI
1656 dev->poll = rtl8169_poll;
1657 dev->weight = R8169_NAPI_WEIGHT;
1da177e4
LT		 1658#endif
1659
1660#ifdef CONFIG_R8169_VLAN
1661 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1662 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1663#endif
1664
1665#ifdef CONFIG_NET_POLL_CONTROLLER
1666 dev->poll_controller = rtl8169_netpoll;
1667#endif
1668
1669 tp->intr_mask = 0xffff;
1670 tp->pci_dev = pdev;
1671 tp->mmio_addr = ioaddr;
0e485150
FR		 1672 tp->align = cfg->align;
1673 tp->hw_start = cfg->hw_start;
1674 tp->intr_event = cfg->intr_event;
1675 tp->napi_event = cfg->napi_event;
1da177e4 1676
2efa53f3
FR		 1677 init_timer(&tp->timer);
1678 tp->timer.data = (unsigned long) dev;
1679 tp->timer.function = rtl8169_phy_timer;
1680
1da177e4
LT		 1681 spin_lock_init(&tp->lock);
1682
1683 rc = register_netdev(dev);
4ff96fa6
FR		 1684 if (rc < 0)
1685 goto err_out_unmap_5;
1da177e4
LT		 1686
1687 pci_set_drvdata(pdev, dev);
1688
b57b7e5a 1689 if (netif_msg_probe(tp)) {
96b9709c
FR		 1690 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
1691
b57b7e5a
SH		 1692 printk(KERN_INFO "%s: %s at 0x%lx, "
1693 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 1694 "XID %08x IRQ %d\n",
b57b7e5a 1695 dev->name,
bcf0bf90 1696 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 1697 dev->base_addr,
1698 dev->dev_addr[0], dev->dev_addr[1],
1699 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 1700 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 1701 }
1da177e4 1702
4ff96fa6 1703 rtl8169_init_phy(dev, tp);
1da177e4 1704
4ff96fa6
FR		 1705out:
1706 return rc;
1da177e4 1707
4ff96fa6
FR		 1708err_out_unmap_5:
1709 iounmap(ioaddr);
1710err_out_free_res_4:
1711 pci_release_regions(pdev);
1712err_out_mwi_3:
1713 pci_clear_mwi(pdev);
1714err_out_disable_2:
1715 pci_disable_device(pdev);
1716err_out_free_dev_1:
1717 free_netdev(dev);
1718 goto out;
1da177e4
LT		 1719}
1720
07d3f51f 1721static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1722{
1723 struct net_device *dev = pci_get_drvdata(pdev);
1724 struct rtl8169_private *tp = netdev_priv(dev);
1725
eb2a021c
FR		 1726 flush_scheduled_work();
1727
1da177e4
LT		 1728 unregister_netdev(dev);
1729 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1730 pci_set_drvdata(pdev, NULL);
1731}
1732
1da177e4
LT		 1733static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1734 struct net_device *dev)
1735{
1736 unsigned int mtu = dev->mtu;
1737
1738 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1739}
1740
1741static int rtl8169_open(struct net_device *dev)
1742{
1743 struct rtl8169_private *tp = netdev_priv(dev);
1744 struct pci_dev *pdev = tp->pci_dev;
99f252b0 1745 int retval = -ENOMEM;
1da177e4 1746
1da177e4 1747
99f252b0 1748 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 1749
1750 /*
1751 * Rx and Tx desscriptors needs 256 bytes alignment.
1752 * pci_alloc_consistent provides more.
1753 */
1754 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1755 &tp->TxPhyAddr);
1756 if (!tp->TxDescArray)
99f252b0 1757 goto out;
1da177e4
LT		 1758
1759 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1760 &tp->RxPhyAddr);
1761 if (!tp->RxDescArray)
99f252b0 1762 goto err_free_tx_0;
1da177e4
LT		 1763
1764 retval = rtl8169_init_ring(dev);
1765 if (retval < 0)
99f252b0 1766 goto err_free_rx_1;
1da177e4 1767
c4028958 1768 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 1769
99f252b0
FR		 1770 smp_mb();
1771
1772 retval = request_irq(dev->irq, rtl8169_interrupt, IRQF_SHARED,
1773 dev->name, dev);
1774 if (retval < 0)
1775 goto err_release_ring_2;
1776
07ce4064 1777 rtl_hw_start(dev);
1da177e4
LT		 1778
1779 rtl8169_request_timer(dev);
1780
1781 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1782out:
1783 return retval;
1784
99f252b0
FR		 1785err_release_ring_2:
1786 rtl8169_rx_clear(tp);
1787err_free_rx_1:
1da177e4
LT		 1788 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1789 tp->RxPhyAddr);
99f252b0 1790err_free_tx_0:
1da177e4
LT		 1791 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1792 tp->TxPhyAddr);
1da177e4
LT		 1793 goto out;
1794}
1795
1796static void rtl8169_hw_reset(void __iomem *ioaddr)
1797{
1798 /* Disable interrupts */
1799 rtl8169_irq_mask_and_ack(ioaddr);
1800
1801 /* Reset the chipset */
1802 RTL_W8(ChipCmd, CmdReset);
1803
1804 /* PCI commit */
1805 RTL_R8(ChipCmd);
1806}
1807
7f796d83 1808static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 1809{
1810 void __iomem *ioaddr = tp->mmio_addr;
1811 u32 cfg = rtl8169_rx_config;
1812
1813 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1814 RTL_W32(RxConfig, cfg);
1815
1816 /* Set DMA burst size and Interframe Gap Time */
1817 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
1818 (InterFrameGap << TxInterFrameGapShift));
1819}
1820
07ce4064 1821static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 1822{
1823 struct rtl8169_private *tp = netdev_priv(dev);
1824 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1825 unsigned int i;
1da177e4
LT		 1826
1827 /* Soft reset the chip. */
1828 RTL_W8(ChipCmd, CmdReset);
1829
1830 /* Check that the chip has finished the reset. */
07d3f51f 1831 for (i = 0; i < 100; i++) {
1da177e4
LT		 1832 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1833 break;
b518fa8e 1834 msleep_interruptible(1);
1da177e4
LT		 1835 }
1836
07ce4064
FR		 1837 tp->hw_start(dev);
1838
07ce4064
FR		 1839 netif_start_queue(dev);
1840}
1841
1842
7f796d83
FR		 1843static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
1844 void __iomem *ioaddr)
1845{
1846 /*
1847 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
1848 * register to be written before TxDescAddrLow to work.
1849 * Switching from MMIO to I/O access fixes the issue as well.
1850 */
1851 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
1852 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
1853 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
1854 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
1855}
1856
1857static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
1858{
1859 u16 cmd;
1860
1861 cmd = RTL_R16(CPlusCmd);
1862 RTL_W16(CPlusCmd, cmd);
1863 return cmd;
1864}
1865
1866static void rtl_set_rx_max_size(void __iomem *ioaddr)
1867{
1868 /* Low hurts. Let's disable the filtering. */
1869 RTL_W16(RxMaxSize, 16383);
1870}
1871
6dccd16b
FR		 1872static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
1873{
1874 struct {
1875 u32 mac_version;
1876 u32 clk;
1877 u32 val;
1878 } cfg2_info [] = {
1879 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
1880 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
1881 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
1882 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
1883 }, *p = cfg2_info;
1884 unsigned int i;
1885 u32 clk;
1886
1887 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
1888 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++) {
1889 if ((p->mac_version == mac_version) && (p->clk == clk)) {
1890 RTL_W32(0x7c, p->val);
1891 break;
1892 }
1893 }
1894}
1895
07ce4064
FR		 1896static void rtl_hw_start_8169(struct net_device *dev)
1897{
1898 struct rtl8169_private *tp = netdev_priv(dev);
1899 void __iomem *ioaddr = tp->mmio_addr;
1900 struct pci_dev *pdev = tp->pci_dev;
07ce4064 1901
9cb427b6
FR		 1902 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
1903 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
1904 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
1905 }
1906
1da177e4 1907 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 1908 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
1909 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1910 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
1911 (tp->mac_version == RTL_GIGA_MAC_VER_04))
1912 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1913
1da177e4
LT		 1914 RTL_W8(EarlyTxThres, EarlyTxThld);
1915
7f796d83 1916 rtl_set_rx_max_size(ioaddr);
1da177e4 1917
6dccd16b 1918 rtl_set_rx_tx_config_registers(tp);
1da177e4 1919
7f796d83 1920 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 1921
bcf0bf90
FR		 1922 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1923 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1da177e4
LT		 1924 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1925 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 1926 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 1927 }
1928
bcf0bf90
FR		 1929 RTL_W16(CPlusCmd, tp->cp_cmd);
1930
6dccd16b
FR		 1931 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
1932
1da177e4
LT		 1933 /*
1934 * Undocumented corner. Supposedly:
1935 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1936 */
1937 RTL_W16(IntrMitigate, 0x0000);
1938
7f796d83 1939 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 1940
1da177e4 1941 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 1942
1943 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
1944 RTL_R8(IntrMask);
1da177e4
LT		 1945
1946 RTL_W32(RxMissed, 0);
1947
07ce4064 1948 rtl_set_rx_mode(dev);
1da177e4
LT		 1949
1950 /* no early-rx interrupts */
1951 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 1952
1953 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 1954 RTL_W16(IntrMask, tp->intr_event);
6dccd16b
FR		 1955
1956 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
07ce4064 1957}
1da177e4 1958
07ce4064
FR		 1959static void rtl_hw_start_8168(struct net_device *dev)
1960{
2dd99530
FR		 1961 struct rtl8169_private *tp = netdev_priv(dev);
1962 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1963 struct pci_dev *pdev = tp->pci_dev;
1964 u8 ctl;
2dd99530
FR		 1965
1966 RTL_W8(Cfg9346, Cfg9346_Unlock);
1967
1968 RTL_W8(EarlyTxThres, EarlyTxThld);
1969
1970 rtl_set_rx_max_size(ioaddr);
1971
0e485150
FR		 1972 rtl_set_rx_tx_config_registers(tp);
1973
1974 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 1975
1976 RTL_W16(CPlusCmd, tp->cp_cmd);
1977
0e485150
FR		 1978 /* Tx performance tweak. */
1979 pci_read_config_byte(pdev, 0x69, &ctl);
1980 ctl = (ctl & ~0x70) | 0x50;
1981 pci_write_config_byte(pdev, 0x69, ctl);
2dd99530 1982
0e485150 1983 RTL_W16(IntrMitigate, 0x5151);
2dd99530 1984
0e485150
FR		 1985 /* Work around for RxFIFO overflow. */
1986 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
1987 tp->intr_event |= RxFIFOOver | PCSTimeout;
1988 tp->intr_event &= ~RxOverflow;
1989 }
1990
1991 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 1992
1993 RTL_W8(Cfg9346, Cfg9346_Lock);
1994
1995 RTL_R8(IntrMask);
1996
1997 RTL_W32(RxMissed, 0);
1998
1999 rtl_set_rx_mode(dev);
2000
0e485150
FR		 2001 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2002
2dd99530 2003 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2004
0e485150 2005 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2006}
1da177e4 2007
07ce4064
FR		 2008static void rtl_hw_start_8101(struct net_device *dev)
2009{
cdf1a608
FR		 2010 struct rtl8169_private *tp = netdev_priv(dev);
2011 void __iomem *ioaddr = tp->mmio_addr;
2012 struct pci_dev *pdev = tp->pci_dev;
2013
2014 if (tp->mac_version == RTL_GIGA_MAC_VER_13) {
2015 pci_write_config_word(pdev, 0x68, 0x00);
2016 pci_write_config_word(pdev, 0x69, 0x08);
2017 }
2018
2019 RTL_W8(Cfg9346, Cfg9346_Unlock);
2020
2021 RTL_W8(EarlyTxThres, EarlyTxThld);
2022
2023 rtl_set_rx_max_size(ioaddr);
2024
2025 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2026
2027 RTL_W16(CPlusCmd, tp->cp_cmd);
2028
2029 RTL_W16(IntrMitigate, 0x0000);
2030
2031 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2032
2033 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2034 rtl_set_rx_tx_config_registers(tp);
2035
2036 RTL_W8(Cfg9346, Cfg9346_Lock);
2037
2038 RTL_R8(IntrMask);
2039
2040 RTL_W32(RxMissed, 0);
2041
2042 rtl_set_rx_mode(dev);
2043
0e485150
FR		 2044 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2045
cdf1a608 2046 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2047
0e485150 2048 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2049}
2050
2051static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2052{
2053 struct rtl8169_private *tp = netdev_priv(dev);
2054 int ret = 0;
2055
2056 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2057 return -EINVAL;
2058
2059 dev->mtu = new_mtu;
2060
2061 if (!netif_running(dev))
2062 goto out;
2063
2064 rtl8169_down(dev);
2065
2066 rtl8169_set_rxbufsize(tp, dev);
2067
2068 ret = rtl8169_init_ring(dev);
2069 if (ret < 0)
2070 goto out;
2071
2072 netif_poll_enable(dev);
2073
07ce4064 2074 rtl_hw_start(dev);
1da177e4
LT		 2075
2076 rtl8169_request_timer(dev);
2077
2078out:
2079 return ret;
2080}
2081
2082static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2083{
2084 desc->addr = 0x0badbadbadbadbadull;
2085 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2086}
2087
2088static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2089 struct sk_buff **sk_buff, struct RxDesc *desc)
2090{
2091 struct pci_dev *pdev = tp->pci_dev;
2092
2093 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2094 PCI_DMA_FROMDEVICE);
2095 dev_kfree_skb(*sk_buff);
2096 *sk_buff = NULL;
2097 rtl8169_make_unusable_by_asic(desc);
2098}
2099
2100static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2101{
2102 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2103
2104 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2105}
2106
2107static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2108 u32 rx_buf_sz)
2109{
2110 desc->addr = cpu_to_le64(mapping);
2111 wmb();
2112 rtl8169_mark_to_asic(desc, rx_buf_sz);
2113}
2114
15d31758
SH		 2115static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2116 struct net_device *dev,
2117 struct RxDesc *desc, int rx_buf_sz,
2118 unsigned int align)
1da177e4
LT		 2119{
2120 struct sk_buff *skb;
2121 dma_addr_t mapping;
e9f63f30 2122 unsigned int pad;
1da177e4 2123
e9f63f30
FR		 2124 pad = align ? align : NET_IP_ALIGN;
2125
2126 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2127 if (!skb)
2128 goto err_out;
2129
e9f63f30 2130 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2131
689be439 2132 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2133 PCI_DMA_FROMDEVICE);
2134
2135 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2136out:
15d31758 2137 return skb;
1da177e4
LT		 2138
2139err_out:
1da177e4
LT		 2140 rtl8169_make_unusable_by_asic(desc);
2141 goto out;
2142}
2143
2144static void rtl8169_rx_clear(struct rtl8169_private *tp)
2145{
07d3f51f 2146 unsigned int i;
1da177e4
LT		 2147
2148 for (i = 0; i < NUM_RX_DESC; i++) {
2149 if (tp->Rx_skbuff[i]) {
2150 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2151 tp->RxDescArray + i);
2152 }
2153 }
2154}
2155
2156static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2157 u32 start, u32 end)
2158{
2159 u32 cur;
5b0384f4 2160
4ae47c2d 2161 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2162 struct sk_buff *skb;
2163 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2164
4ae47c2d
FR		 2165 WARN_ON((s32)(end - cur) < 0);
2166
1da177e4
LT		 2167 if (tp->Rx_skbuff[i])
2168 continue;
bcf0bf90 2169
15d31758
SH		 2170 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2171 tp->RxDescArray + i,
2172 tp->rx_buf_sz, tp->align);
2173 if (!skb)
1da177e4 2174 break;
15d31758
SH		 2175
2176 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2177 }
2178 return cur - start;
2179}
2180
2181static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2182{
2183 desc->opts1 |= cpu_to_le32(RingEnd);
2184}
2185
2186static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2187{
2188 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2189}
2190
2191static int rtl8169_init_ring(struct net_device *dev)
2192{
2193 struct rtl8169_private *tp = netdev_priv(dev);
2194
2195 rtl8169_init_ring_indexes(tp);
2196
2197 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2198 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2199
2200 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2201 goto err_out;
2202
2203 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2204
2205 return 0;
2206
2207err_out:
2208 rtl8169_rx_clear(tp);
2209 return -ENOMEM;
2210}
2211
2212static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2213 struct TxDesc *desc)
2214{
2215 unsigned int len = tx_skb->len;
2216
2217 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2218 desc->opts1 = 0x00;
2219 desc->opts2 = 0x00;
2220 desc->addr = 0x00;
2221 tx_skb->len = 0;
2222}
2223
2224static void rtl8169_tx_clear(struct rtl8169_private *tp)
2225{
2226 unsigned int i;
2227
2228 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2229 unsigned int entry = i % NUM_TX_DESC;
2230 struct ring_info *tx_skb = tp->tx_skb + entry;
2231 unsigned int len = tx_skb->len;
2232
2233 if (len) {
2234 struct sk_buff *skb = tx_skb->skb;
2235
2236 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2237 tp->TxDescArray + entry);
2238 if (skb) {
2239 dev_kfree_skb(skb);
2240 tx_skb->skb = NULL;
2241 }
2242 tp->stats.tx_dropped++;
2243 }
2244 }
2245 tp->cur_tx = tp->dirty_tx = 0;
2246}
2247
c4028958 2248static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2249{
2250 struct rtl8169_private *tp = netdev_priv(dev);
2251
c4028958 2252 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2253 schedule_delayed_work(&tp->task, 4);
2254}
2255
2256static void rtl8169_wait_for_quiescence(struct net_device *dev)
2257{
2258 struct rtl8169_private *tp = netdev_priv(dev);
2259 void __iomem *ioaddr = tp->mmio_addr;
2260
2261 synchronize_irq(dev->irq);
2262
2263 /* Wait for any pending NAPI task to complete */
2264 netif_poll_disable(dev);
2265
2266 rtl8169_irq_mask_and_ack(ioaddr);
2267
2268 netif_poll_enable(dev);
2269}
2270
c4028958 2271static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2272{
c4028958
DH		 2273 struct rtl8169_private *tp =
2274 container_of(work, struct rtl8169_private, task.work);
2275 struct net_device *dev = tp->dev;
1da177e4
LT		 2276 int ret;
2277
eb2a021c
FR		 2278 rtnl_lock();
2279
2280 if (!netif_running(dev))
2281 goto out_unlock;
2282
2283 rtl8169_wait_for_quiescence(dev);
2284 rtl8169_close(dev);
1da177e4
LT		 2285
2286 ret = rtl8169_open(dev);
2287 if (unlikely(ret < 0)) {
07d3f51f
FR		 2288 if (net_ratelimit() && netif_msg_drv(tp)) {
2289 printk(PFX KERN_ERR "%s: reinit failure (status = %d)."
2290 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2291 }
2292 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2293 }
eb2a021c
FR		 2294
2295out_unlock:
2296 rtnl_unlock();
1da177e4
LT		 2297}
2298
c4028958 2299static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2300{
c4028958
DH		 2301 struct rtl8169_private *tp =
2302 container_of(work, struct rtl8169_private, task.work);
2303 struct net_device *dev = tp->dev;
1da177e4 2304
eb2a021c
FR		 2305 rtnl_lock();
2306
1da177e4 2307 if (!netif_running(dev))
eb2a021c 2308 goto out_unlock;
1da177e4
LT		 2309
2310 rtl8169_wait_for_quiescence(dev);
2311
2312 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2313 rtl8169_tx_clear(tp);
2314
2315 if (tp->dirty_rx == tp->cur_rx) {
2316 rtl8169_init_ring_indexes(tp);
07ce4064 2317 rtl_hw_start(dev);
1da177e4
LT		 2318 netif_wake_queue(dev);
2319 } else {
07d3f51f
FR		 2320 if (net_ratelimit() && netif_msg_intr(tp)) {
2321 printk(PFX KERN_EMERG "%s: Rx buffers shortage\n",
2322 dev->name);
1da177e4
LT		 2323 }
2324 rtl8169_schedule_work(dev, rtl8169_reset_task);
2325 }
eb2a021c
FR		 2326
2327out_unlock:
2328 rtnl_unlock();
1da177e4
LT		 2329}
2330
2331static void rtl8169_tx_timeout(struct net_device *dev)
2332{
2333 struct rtl8169_private *tp = netdev_priv(dev);
2334
2335 rtl8169_hw_reset(tp->mmio_addr);
2336
2337 /* Let's wait a bit while any (async) irq lands on */
2338 rtl8169_schedule_work(dev, rtl8169_reset_task);
2339}
2340
2341static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2342 u32 opts1)
2343{
2344 struct skb_shared_info *info = skb_shinfo(skb);
2345 unsigned int cur_frag, entry;
a6343afb 2346 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2347
2348 entry = tp->cur_tx;
2349 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2350 skb_frag_t *frag = info->frags + cur_frag;
2351 dma_addr_t mapping;
2352 u32 status, len;
2353 void *addr;
2354
2355 entry = (entry + 1) % NUM_TX_DESC;
2356
2357 txd = tp->TxDescArray + entry;
2358 len = frag->size;
2359 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2360 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2361
2362 /* anti gcc 2.95.3 bugware (sic) */
2363 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2364
2365 txd->opts1 = cpu_to_le32(status);
2366 txd->addr = cpu_to_le64(mapping);
2367
2368 tp->tx_skb[entry].len = len;
2369 }
2370
2371 if (cur_frag) {
2372 tp->tx_skb[entry].skb = skb;
2373 txd->opts1 |= cpu_to_le32(LastFrag);
2374 }
2375
2376 return cur_frag;
2377}
2378
2379static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2380{
2381 if (dev->features & NETIF_F_TSO) {
7967168c 2382 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2383
2384 if (mss)
2385 return LargeSend | ((mss & MSSMask) << MSSShift);
2386 }
84fa7933 2387 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2388 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2389
2390 if (ip->protocol == IPPROTO_TCP)
2391 return IPCS | TCPCS;
2392 else if (ip->protocol == IPPROTO_UDP)
2393 return IPCS | UDPCS;
2394 WARN_ON(1); /* we need a WARN() */
2395 }
2396 return 0;
2397}
2398
2399static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2400{
2401 struct rtl8169_private *tp = netdev_priv(dev);
2402 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2403 struct TxDesc *txd = tp->TxDescArray + entry;
2404 void __iomem *ioaddr = tp->mmio_addr;
2405 dma_addr_t mapping;
2406 u32 status, len;
2407 u32 opts1;
188f4af0 2408 int ret = NETDEV_TX_OK;
5b0384f4 2409
1da177e4 2410 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2411 if (netif_msg_drv(tp)) {
2412 printk(KERN_ERR
2413 "%s: BUG! Tx Ring full when queue awake!\n",
2414 dev->name);
2415 }
1da177e4
LT		 2416 goto err_stop;
2417 }
2418
2419 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2420 goto err_stop;
2421
2422 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2423
2424 frags = rtl8169_xmit_frags(tp, skb, opts1);
2425 if (frags) {
2426 len = skb_headlen(skb);
2427 opts1 |= FirstFrag;
2428 } else {
2429 len = skb->len;
2430
2431 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2432 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2433 goto err_update_stats;
2434 len = ETH_ZLEN;
2435 }
2436
2437 opts1 |= FirstFrag | LastFrag;
2438 tp->tx_skb[entry].skb = skb;
2439 }
2440
2441 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2442
2443 tp->tx_skb[entry].len = len;
2444 txd->addr = cpu_to_le64(mapping);
2445 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2446
2447 wmb();
2448
2449 /* anti gcc 2.95.3 bugware (sic) */
2450 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2451 txd->opts1 = cpu_to_le32(status);
2452
2453 dev->trans_start = jiffies;
2454
2455 tp->cur_tx += frags + 1;
2456
2457 smp_wmb();
2458
275391a4 2459 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2460
2461 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2462 netif_stop_queue(dev);
2463 smp_rmb();
2464 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2465 netif_wake_queue(dev);
2466 }
2467
2468out:
2469 return ret;
2470
2471err_stop:
2472 netif_stop_queue(dev);
188f4af0 2473 ret = NETDEV_TX_BUSY;
1da177e4
LT		 2474err_update_stats:
2475 tp->stats.tx_dropped++;
2476 goto out;
2477}
2478
2479static void rtl8169_pcierr_interrupt(struct net_device *dev)
2480{
2481 struct rtl8169_private *tp = netdev_priv(dev);
2482 struct pci_dev *pdev = tp->pci_dev;
2483 void __iomem *ioaddr = tp->mmio_addr;
2484 u16 pci_status, pci_cmd;
2485
2486 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2487 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2488
b57b7e5a
SH		 2489 if (netif_msg_intr(tp)) {
2490 printk(KERN_ERR
2491 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2492 dev->name, pci_cmd, pci_status);
2493 }
1da177e4
LT		 2494
2495 /*
2496 * The recovery sequence below admits a very elaborated explanation:
2497 * - it seems to work;
d03902b8
FR		 2498 * - I did not see what else could be done;
2499 * - it makes iop3xx happy.
1da177e4
LT		 2500 *
2501 * Feel free to adjust to your needs.
2502 */
a27993f3 2503 if (pdev->broken_parity_status)
d03902b8
FR		 2504 pci_cmd &= ~PCI_COMMAND_PARITY;
2505 else
2506 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2507
2508 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2509
2510 pci_write_config_word(pdev, PCI_STATUS,
2511 pci_status & (PCI_STATUS_DETECTED_PARITY |
2512 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2513 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2514
2515 /* The infamous DAC f*ckup only happens at boot time */
2516 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2517 if (netif_msg_intr(tp))
2518 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2519 tp->cp_cmd &= ~PCIDAC;
2520 RTL_W16(CPlusCmd, tp->cp_cmd);
2521 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2522 }
2523
2524 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2525
2526 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2527}
2528
07d3f51f
FR		 2529static void rtl8169_tx_interrupt(struct net_device *dev,
2530 struct rtl8169_private *tp,
2531 void __iomem *ioaddr)
1da177e4
LT		 2532{
2533 unsigned int dirty_tx, tx_left;
2534
1da177e4
LT		 2535 dirty_tx = tp->dirty_tx;
2536 smp_rmb();
2537 tx_left = tp->cur_tx - dirty_tx;
2538
2539 while (tx_left > 0) {
2540 unsigned int entry = dirty_tx % NUM_TX_DESC;
2541 struct ring_info *tx_skb = tp->tx_skb + entry;
2542 u32 len = tx_skb->len;
2543 u32 status;
2544
2545 rmb();
2546 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2547 if (status & DescOwn)
2548 break;
2549
2550 tp->stats.tx_bytes += len;
2551 tp->stats.tx_packets++;
2552
2553 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2554
2555 if (status & LastFrag) {
2556 dev_kfree_skb_irq(tx_skb->skb);
2557 tx_skb->skb = NULL;
2558 }
2559 dirty_tx++;
2560 tx_left--;
2561 }
2562
2563 if (tp->dirty_tx != dirty_tx) {
2564 tp->dirty_tx = dirty_tx;
2565 smp_wmb();
2566 if (netif_queue_stopped(dev) &&
2567 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2568 netif_wake_queue(dev);
2569 }
2570 }
2571}
2572
126fa4b9
FR		 2573static inline int rtl8169_fragmented_frame(u32 status)
2574{
2575 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2576}
2577
1da177e4
LT		 2578static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2579{
2580 u32 opts1 = le32_to_cpu(desc->opts1);
2581 u32 status = opts1 & RxProtoMask;
2582
2583 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2584 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2585 ((status == RxProtoIP) && !(opts1 & IPFail)))
2586 skb->ip_summed = CHECKSUM_UNNECESSARY;
2587 else
2588 skb->ip_summed = CHECKSUM_NONE;
2589}
2590
07d3f51f
FR		 2591static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
2592 struct rtl8169_private *tp, int pkt_size,
2593 dma_addr_t addr)
1da177e4 2594{
b449655f
SH		 2595 struct sk_buff *skb;
2596 bool done = false;
1da177e4 2597
b449655f
SH		 2598 if (pkt_size >= rx_copybreak)
2599 goto out;
1da177e4 2600
07d3f51f 2601 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 2602 if (!skb)
2603 goto out;
2604
07d3f51f
FR		 2605 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
2606 PCI_DMA_FROMDEVICE);
86402234 2607 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 2608 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
2609 *sk_buff = skb;
2610 done = true;
2611out:
2612 return done;
1da177e4
LT		 2613}
2614
07d3f51f
FR		 2615static int rtl8169_rx_interrupt(struct net_device *dev,
2616 struct rtl8169_private *tp,
2617 void __iomem *ioaddr)
1da177e4
LT		 2618{
2619 unsigned int cur_rx, rx_left;
2620 unsigned int delta, count;
2621
1da177e4
LT		 2622 cur_rx = tp->cur_rx;
2623 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2624 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2625
4dcb7d33 2626 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 2627 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 2628 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 2629 u32 status;
2630
2631 rmb();
126fa4b9 2632 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 2633
2634 if (status & DescOwn)
2635 break;
4dcb7d33 2636 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 2637 if (netif_msg_rx_err(tp)) {
2638 printk(KERN_INFO
2639 "%s: Rx ERROR. status = %08x\n",
2640 dev->name, status);
2641 }
1da177e4
LT		 2642 tp->stats.rx_errors++;
2643 if (status & (RxRWT | RxRUNT))
2644 tp->stats.rx_length_errors++;
2645 if (status & RxCRC)
2646 tp->stats.rx_crc_errors++;
9dccf611
FR		 2647 if (status & RxFOVF) {
2648 rtl8169_schedule_work(dev, rtl8169_reset_task);
2649 tp->stats.rx_fifo_errors++;
2650 }
126fa4b9 2651 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 2652 } else {
1da177e4 2653 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 2654 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 2655 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 2656 struct pci_dev *pdev = tp->pci_dev;
1da177e4 2657
126fa4b9
FR		 2658 /*
2659 * The driver does not support incoming fragmented
2660 * frames. They are seen as a symptom of over-mtu
2661 * sized frames.
2662 */
2663 if (unlikely(rtl8169_fragmented_frame(status))) {
2664 tp->stats.rx_dropped++;
2665 tp->stats.rx_length_errors++;
2666 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 2667 continue;
126fa4b9
FR		 2668 }
2669
1da177e4 2670 rtl8169_rx_csum(skb, desc);
bcf0bf90 2671
07d3f51f 2672 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 2673 pci_dma_sync_single_for_device(pdev, addr,
2674 pkt_size, PCI_DMA_FROMDEVICE);
2675 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2676 } else {
2677 pci_unmap_single(pdev, addr, pkt_size,
2678 PCI_DMA_FROMDEVICE);
1da177e4
LT		 2679 tp->Rx_skbuff[entry] = NULL;
2680 }
2681
1da177e4
LT		 2682 skb_put(skb, pkt_size);
2683 skb->protocol = eth_type_trans(skb, dev);
2684
2685 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2686 rtl8169_rx_skb(skb);
2687
2688 dev->last_rx = jiffies;
2689 tp->stats.rx_bytes += pkt_size;
2690 tp->stats.rx_packets++;
2691 }
6dccd16b
FR		 2692
2693 /* Work around for AMD plateform. */
2694 if ((desc->opts2 & 0xfffe000) &&
2695 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
2696 desc->opts2 = 0;
2697 cur_rx++;
2698 }
1da177e4
LT		 2699 }
2700
2701 count = cur_rx - tp->cur_rx;
2702 tp->cur_rx = cur_rx;
2703
2704 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 2705 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 2706 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2707 tp->dirty_rx += delta;
2708
2709 /*
2710 * FIXME: until there is periodic timer to try and refill the ring,
2711 * a temporary shortage may definitely kill the Rx process.
2712 * - disable the asic to try and avoid an overflow and kick it again
2713 * after refill ?
2714 * - how do others driver handle this condition (Uh oh...).
2715 */
b57b7e5a 2716 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 2717 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2718
2719 return count;
2720}
2721
07d3f51f 2722static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 2723{
07d3f51f 2724 struct net_device *dev = dev_instance;
1da177e4
LT		 2725 struct rtl8169_private *tp = netdev_priv(dev);
2726 int boguscnt = max_interrupt_work;
2727 void __iomem *ioaddr = tp->mmio_addr;
2728 int status;
2729 int handled = 0;
2730
2731 do {
2732 status = RTL_R16(IntrStatus);
2733
2734 /* hotplug/major error/no more work/shared irq */
2735 if ((status == 0xFFFF) || !status)
2736 break;
2737
2738 handled = 1;
2739
2740 if (unlikely(!netif_running(dev))) {
2741 rtl8169_asic_down(ioaddr);
2742 goto out;
2743 }
2744
2745 status &= tp->intr_mask;
2746 RTL_W16(IntrStatus,
2747 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2748
0e485150
FR		 2749 if (!(status & tp->intr_event))
2750 break;
2751
2752 /* Work around for rx fifo overflow */
2753 if (unlikely(status & RxFIFOOver) &&
2754 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
2755 netif_stop_queue(dev);
2756 rtl8169_tx_timeout(dev);
1da177e4 2757 break;
0e485150 2758 }
1da177e4
LT		 2759
2760 if (unlikely(status & SYSErr)) {
2761 rtl8169_pcierr_interrupt(dev);
2762 break;
2763 }
2764
2765 if (status & LinkChg)
2766 rtl8169_check_link_status(dev, tp, ioaddr);
2767
2768#ifdef CONFIG_R8169_NAPI
313b0305
FR		 2769 if (status & tp->napi_event) {
2770 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
2771 tp->intr_mask = ~tp->napi_event;
2772
2773 if (likely(netif_rx_schedule_prep(dev)))
2774 __netif_rx_schedule(dev);
2775 else if (netif_msg_intr(tp)) {
2776 printk(KERN_INFO "%s: interrupt %04x in poll\n",
2777 dev->name, status);
2778 }
1da177e4
LT		 2779 }
2780 break;
2781#else
2782 /* Rx interrupt */
07d3f51f 2783 if (status & (RxOK | RxOverflow | RxFIFOOver))
1da177e4 2784 rtl8169_rx_interrupt(dev, tp, ioaddr);
07d3f51f 2785
1da177e4
LT		 2786 /* Tx interrupt */
2787 if (status & (TxOK | TxErr))
2788 rtl8169_tx_interrupt(dev, tp, ioaddr);
2789#endif
2790
2791 boguscnt--;
2792 } while (boguscnt > 0);
2793
2794 if (boguscnt <= 0) {
7c8b2eb4 2795 if (netif_msg_intr(tp) && net_ratelimit() ) {
b57b7e5a
SH		 2796 printk(KERN_WARNING
2797 "%s: Too much work at interrupt!\n", dev->name);
2798 }
1da177e4
LT		 2799 /* Clear all interrupt sources. */
2800 RTL_W16(IntrStatus, 0xffff);
2801 }
2802out:
2803 return IRQ_RETVAL(handled);
2804}
2805
2806#ifdef CONFIG_R8169_NAPI
2807static int rtl8169_poll(struct net_device *dev, int *budget)
2808{
2809 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2810 struct rtl8169_private *tp = netdev_priv(dev);
2811 void __iomem *ioaddr = tp->mmio_addr;
2812
2813 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2814 rtl8169_tx_interrupt(dev, tp, ioaddr);
2815
2816 *budget -= work_done;
2817 dev->quota -= work_done;
2818
2819 if (work_done < work_to_do) {
2820 netif_rx_complete(dev);
2821 tp->intr_mask = 0xffff;
2822 /*
2823 * 20040426: the barrier is not strictly required but the
2824 * behavior of the irq handler could be less predictable
2825 * without it. Btw, the lack of flush for the posted pci
2826 * write is safe - FR
2827 */
2828 smp_wmb();
0e485150 2829 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2830 }
2831
2832 return (work_done >= work_to_do);
2833}
2834#endif
2835
2836static void rtl8169_down(struct net_device *dev)
2837{
2838 struct rtl8169_private *tp = netdev_priv(dev);
2839 void __iomem *ioaddr = tp->mmio_addr;
2840 unsigned int poll_locked = 0;
733b736c 2841 unsigned int intrmask;
1da177e4
LT		 2842
2843 rtl8169_delete_timer(dev);
2844
2845 netif_stop_queue(dev);
2846
1da177e4
LT		 2847core_down:
2848 spin_lock_irq(&tp->lock);
2849
2850 rtl8169_asic_down(ioaddr);
2851
2852 /* Update the error counts. */
2853 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2854 RTL_W32(RxMissed, 0);
2855
2856 spin_unlock_irq(&tp->lock);
2857
2858 synchronize_irq(dev->irq);
2859
2860 if (!poll_locked) {
2861 netif_poll_disable(dev);
2862 poll_locked++;
2863 }
2864
2865 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 2866 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 2867
2868 /*
2869 * And now for the 50k$ question: are IRQ disabled or not ?
2870 *
2871 * Two paths lead here:
2872 * 1) dev->close
2873 * -> netif_running() is available to sync the current code and the
2874 * IRQ handler. See rtl8169_interrupt for details.
2875 * 2) dev->change_mtu
2876 * -> rtl8169_poll can not be issued again and re-enable the
2877 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 2878 *
2879 * No loop if hotpluged or major error (0xffff).
1da177e4 2880 */
733b736c
AP		 2881 intrmask = RTL_R16(IntrMask);
2882 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 2883 goto core_down;
2884
2885 rtl8169_tx_clear(tp);
2886
2887 rtl8169_rx_clear(tp);
2888}
2889
2890static int rtl8169_close(struct net_device *dev)
2891{
2892 struct rtl8169_private *tp = netdev_priv(dev);
2893 struct pci_dev *pdev = tp->pci_dev;
2894
2895 rtl8169_down(dev);
2896
2897 free_irq(dev->irq, dev);
2898
2899 netif_poll_enable(dev);
2900
2901 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2902 tp->RxPhyAddr);
2903 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2904 tp->TxPhyAddr);
2905 tp->TxDescArray = NULL;
2906 tp->RxDescArray = NULL;
2907
2908 return 0;
2909}
2910
07ce4064 2911static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 2912{
2913 struct rtl8169_private *tp = netdev_priv(dev);
2914 void __iomem *ioaddr = tp->mmio_addr;
2915 unsigned long flags;
2916 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 2917 int rx_mode;
1da177e4
LT		 2918 u32 tmp = 0;
2919
2920 if (dev->flags & IFF_PROMISC) {
2921 /* Unconditionally log net taps. */
b57b7e5a
SH		 2922 if (netif_msg_link(tp)) {
2923 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2924 dev->name);
2925 }
1da177e4
LT		 2926 rx_mode =
2927 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2928 AcceptAllPhys;
2929 mc_filter[1] = mc_filter[0] = 0xffffffff;
2930 } else if ((dev->mc_count > multicast_filter_limit)
2931 || (dev->flags & IFF_ALLMULTI)) {
2932 /* Too many to filter perfectly -- accept all multicasts. */
2933 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2934 mc_filter[1] = mc_filter[0] = 0xffffffff;
2935 } else {
2936 struct dev_mc_list *mclist;
07d3f51f
FR		 2937 unsigned int i;
2938
1da177e4
LT		 2939 rx_mode = AcceptBroadcast | AcceptMyPhys;
2940 mc_filter[1] = mc_filter[0] = 0;
2941 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2942 i++, mclist = mclist->next) {
2943 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2944 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2945 rx_mode |= AcceptMulticast;
2946 }
2947 }
2948
2949 spin_lock_irqsave(&tp->lock, flags);
2950
2951 tmp = rtl8169_rx_config | rx_mode |
2952 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2953
bcf0bf90
FR		 2954 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
2955 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
2956 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2957 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
2958 (tp->mac_version == RTL_GIGA_MAC_VER_15)) {
2959 mc_filter[0] = 0xffffffff;
2960 mc_filter[1] = 0xffffffff;
2961 }
2962
1da177e4
LT		 2963 RTL_W32(MAR0 + 0, mc_filter[0]);
2964 RTL_W32(MAR0 + 4, mc_filter[1]);
2965
57a9f236
FR		 2966 RTL_W32(RxConfig, tmp);
2967
1da177e4
LT		 2968 spin_unlock_irqrestore(&tp->lock, flags);
2969}
2970
2971/**
2972 * rtl8169_get_stats - Get rtl8169 read/write statistics
2973 * @dev: The Ethernet Device to get statistics for
2974 *
2975 * Get TX/RX statistics for rtl8169
2976 */
2977static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2978{
2979 struct rtl8169_private *tp = netdev_priv(dev);
2980 void __iomem *ioaddr = tp->mmio_addr;
2981 unsigned long flags;
2982
2983 if (netif_running(dev)) {
2984 spin_lock_irqsave(&tp->lock, flags);
2985 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2986 RTL_W32(RxMissed, 0);
2987 spin_unlock_irqrestore(&tp->lock, flags);
2988 }
5b0384f4 2989
1da177e4
LT		 2990 return &tp->stats;
2991}
2992
5d06a99f
FR		 2993#ifdef CONFIG_PM
2994
2995static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2996{
2997 struct net_device *dev = pci_get_drvdata(pdev);
2998 struct rtl8169_private *tp = netdev_priv(dev);
2999 void __iomem *ioaddr = tp->mmio_addr;
3000
3001 if (!netif_running(dev))
1371fa6d 3002 goto out_pci_suspend;
5d06a99f
FR		 3003
3004 netif_device_detach(dev);
3005 netif_stop_queue(dev);
3006
3007 spin_lock_irq(&tp->lock);
3008
3009 rtl8169_asic_down(ioaddr);
3010
3011 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
3012 RTL_W32(RxMissed, 0);
3013
3014 spin_unlock_irq(&tp->lock);
3015
1371fa6d 3016out_pci_suspend:
5d06a99f 3017 pci_save_state(pdev);
61a4dcc2 3018 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
5d06a99f 3019 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3020
5d06a99f
FR		 3021 return 0;
3022}
3023
3024static int rtl8169_resume(struct pci_dev *pdev)
3025{
3026 struct net_device *dev = pci_get_drvdata(pdev);
3027
1371fa6d
FR		 3028 pci_set_power_state(pdev, PCI_D0);
3029 pci_restore_state(pdev);
3030 pci_enable_wake(pdev, PCI_D0, 0);
3031
5d06a99f
FR		 3032 if (!netif_running(dev))
3033 goto out;
3034
3035 netif_device_attach(dev);
3036
5d06a99f
FR		 3037 rtl8169_schedule_work(dev, rtl8169_reset_task);
3038out:
3039 return 0;
3040}
3041
3042#endif /* CONFIG_PM */
3043
1da177e4
LT		 3044static struct pci_driver rtl8169_pci_driver = {
3045 .name = MODULENAME,
3046 .id_table = rtl8169_pci_tbl,
3047 .probe = rtl8169_init_one,
3048 .remove = __devexit_p(rtl8169_remove_one),
3049#ifdef CONFIG_PM
3050 .suspend = rtl8169_suspend,
3051 .resume = rtl8169_resume,
3052#endif
3053};
3054
07d3f51f 3055static int __init rtl8169_init_module(void)
1da177e4 3056{
29917620 3057 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3058}
3059
07d3f51f 3060static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3061{
3062 pci_unregister_driver(&rtl8169_pci_driver);
3063}
3064
3065module_init(rtl8169_init_module);
3066module_exit(rtl8169_cleanup_module);
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