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r8169: move the firmware down into the device private data.
[mirror_ubuntu-zesty-kernel.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
a6b7a407 25#include <linux/interrupt.h>
1da177e4 26#include <linux/dma-mapping.h>
e1759441 27#include <linux/pm_runtime.h>
bca03d5f 28#include <linux/firmware.h>
ba04c7c9 29#include <linux/pci-aspm.h>
70c71606 30#include <linux/prefetch.h>
1da177e4 31
99f252b0 32#include <asm/system.h>
1da177e4
LT		 33#include <asm/io.h>
34#include <asm/irq.h>
35
865c652d 36#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 37#define MODULENAME "r8169"
38#define PFX MODULENAME ": "
39
bca03d5f 40#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
41#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 42#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
43#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
5a5e4443 44#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 45
1da177e4
LT		 46#ifdef RTL8169_DEBUG
47#define assert(expr) \
5b0384f4
FR		 48 if (!(expr)) { \
49 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 50 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 51 }
06fa7358
JP		 52#define dprintk(fmt, args...) \
53 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 54#else
55#define assert(expr) do {} while (0)
56#define dprintk(fmt, args...) do {} while (0)
57#endif /* RTL8169_DEBUG */
58
b57b7e5a 59#define R8169_MSG_DEFAULT \
f0e837d9 60 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 61
1da177e4
LT		 62#define TX_BUFFS_AVAIL(tp) \
63 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
64
1da177e4
LT		 65/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
66 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 67static const int multicast_filter_limit = 32;
1da177e4
LT		 68
69/* MAC address length */
70#define MAC_ADDR_LEN 6
71
9c14ceaf 72#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 73#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
74#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
75#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 76#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
77#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
78
79#define R8169_REGS_SIZE 256
80#define R8169_NAPI_WEIGHT 64
81#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
82#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
83#define RX_BUF_SIZE 1536 /* Rx Buffer size */
84#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
85#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
86
87#define RTL8169_TX_TIMEOUT (6*HZ)
88#define RTL8169_PHY_TIMEOUT (10*HZ)
89
ea8dbdd1 90#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
91#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 92#define RTL_EEPROM_SIG_ADDR 0x0000
93
1da177e4
LT		 94/* write/read MMIO register */
95#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
96#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
97#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
98#define RTL_R8(reg) readb (ioaddr + (reg))
99#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 100#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 101
102enum mac_version {
85bffe6c
FR		 103 RTL_GIGA_MAC_VER_01 = 0,
104 RTL_GIGA_MAC_VER_02,
105 RTL_GIGA_MAC_VER_03,
106 RTL_GIGA_MAC_VER_04,
107 RTL_GIGA_MAC_VER_05,
108 RTL_GIGA_MAC_VER_06,
109 RTL_GIGA_MAC_VER_07,
110 RTL_GIGA_MAC_VER_08,
111 RTL_GIGA_MAC_VER_09,
112 RTL_GIGA_MAC_VER_10,
113 RTL_GIGA_MAC_VER_11,
114 RTL_GIGA_MAC_VER_12,
115 RTL_GIGA_MAC_VER_13,
116 RTL_GIGA_MAC_VER_14,
117 RTL_GIGA_MAC_VER_15,
118 RTL_GIGA_MAC_VER_16,
119 RTL_GIGA_MAC_VER_17,
120 RTL_GIGA_MAC_VER_18,
121 RTL_GIGA_MAC_VER_19,
122 RTL_GIGA_MAC_VER_20,
123 RTL_GIGA_MAC_VER_21,
124 RTL_GIGA_MAC_VER_22,
125 RTL_GIGA_MAC_VER_23,
126 RTL_GIGA_MAC_VER_24,
127 RTL_GIGA_MAC_VER_25,
128 RTL_GIGA_MAC_VER_26,
129 RTL_GIGA_MAC_VER_27,
130 RTL_GIGA_MAC_VER_28,
131 RTL_GIGA_MAC_VER_29,
132 RTL_GIGA_MAC_VER_30,
133 RTL_GIGA_MAC_VER_31,
134 RTL_GIGA_MAC_VER_32,
135 RTL_GIGA_MAC_VER_33,
136 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 137};
138
2b7b4318
FR		 139enum rtl_tx_desc_version {
140 RTL_TD_0 = 0,
141 RTL_TD_1 = 1,
142};
143
85bffe6c
FR		 144#define _R(NAME,TD,FW) \
145 { .name = NAME, .txd_version = TD, .fw_name = FW }
1da177e4 146
3c6bee1d 147static const struct {
1da177e4 148 const char *name;
2b7b4318 149 enum rtl_tx_desc_version txd_version;
953a12cc 150 const char *fw_name;
85bffe6c
FR		 151} rtl_chip_infos[] = {
152 /* PCI devices. */
153 [RTL_GIGA_MAC_VER_01] =
154 _R("RTL8169", RTL_TD_0, NULL),
155 [RTL_GIGA_MAC_VER_02] =
156 _R("RTL8169s", RTL_TD_0, NULL),
157 [RTL_GIGA_MAC_VER_03] =
158 _R("RTL8110s", RTL_TD_0, NULL),
159 [RTL_GIGA_MAC_VER_04] =
160 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
161 [RTL_GIGA_MAC_VER_05] =
162 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
163 [RTL_GIGA_MAC_VER_06] =
164 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
165 /* PCI-E devices. */
166 [RTL_GIGA_MAC_VER_07] =
167 _R("RTL8102e", RTL_TD_1, NULL),
168 [RTL_GIGA_MAC_VER_08] =
169 _R("RTL8102e", RTL_TD_1, NULL),
170 [RTL_GIGA_MAC_VER_09] =
171 _R("RTL8102e", RTL_TD_1, NULL),
172 [RTL_GIGA_MAC_VER_10] =
173 _R("RTL8101e", RTL_TD_0, NULL),
174 [RTL_GIGA_MAC_VER_11] =
175 _R("RTL8168b/8111b", RTL_TD_0, NULL),
176 [RTL_GIGA_MAC_VER_12] =
177 _R("RTL8168b/8111b", RTL_TD_0, NULL),
178 [RTL_GIGA_MAC_VER_13] =
179 _R("RTL8101e", RTL_TD_0, NULL),
180 [RTL_GIGA_MAC_VER_14] =
181 _R("RTL8100e", RTL_TD_0, NULL),
182 [RTL_GIGA_MAC_VER_15] =
183 _R("RTL8100e", RTL_TD_0, NULL),
184 [RTL_GIGA_MAC_VER_16] =
185 _R("RTL8101e", RTL_TD_0, NULL),
186 [RTL_GIGA_MAC_VER_17] =
187 _R("RTL8168b/8111b", RTL_TD_0, NULL),
188 [RTL_GIGA_MAC_VER_18] =
189 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
190 [RTL_GIGA_MAC_VER_19] =
191 _R("RTL8168c/8111c", RTL_TD_1, NULL),
192 [RTL_GIGA_MAC_VER_20] =
193 _R("RTL8168c/8111c", RTL_TD_1, NULL),
194 [RTL_GIGA_MAC_VER_21] =
195 _R("RTL8168c/8111c", RTL_TD_1, NULL),
196 [RTL_GIGA_MAC_VER_22] =
197 _R("RTL8168c/8111c", RTL_TD_1, NULL),
198 [RTL_GIGA_MAC_VER_23] =
199 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
200 [RTL_GIGA_MAC_VER_24] =
201 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
202 [RTL_GIGA_MAC_VER_25] =
203 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
204 [RTL_GIGA_MAC_VER_26] =
205 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
206 [RTL_GIGA_MAC_VER_27] =
207 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
208 [RTL_GIGA_MAC_VER_28] =
209 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
210 [RTL_GIGA_MAC_VER_29] =
211 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
212 [RTL_GIGA_MAC_VER_30] =
213 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
214 [RTL_GIGA_MAC_VER_31] =
215 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
216 [RTL_GIGA_MAC_VER_32] =
217 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
218 [RTL_GIGA_MAC_VER_33] =
219 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2)
953a12cc 220};
85bffe6c 221#undef _R
953a12cc 222
bcf0bf90
FR		 223enum cfg_version {
224 RTL_CFG_0 = 0x00,
225 RTL_CFG_1,
226 RTL_CFG_2
227};
228
07ce4064
FR		 229static void rtl_hw_start_8169(struct net_device *);
230static void rtl_hw_start_8168(struct net_device *);
231static void rtl_hw_start_8101(struct net_device *);
232
a3aa1884 233static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 234 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 235 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 238 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
239 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 240 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 241 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
242 { PCI_VENDOR_ID_LINKSYS, 0x1032,
243 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 244 { 0x0001, 0x8168,
245 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 246 {0,},
247};
248
249MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
250
6f0333b8 251static int rx_buf_sz = 16383;
4300e8c7 252static int use_dac;
b57b7e5a
SH		 253static struct {
254 u32 msg_enable;
255} debug = { -1 };
1da177e4 256
07d3f51f
FR		 257enum rtl_registers {
258 MAC0 = 0, /* Ethernet hardware address. */
773d2021 259 MAC4 = 4,
07d3f51f
FR		 260 MAR0 = 8, /* Multicast filter. */
261 CounterAddrLow = 0x10,
262 CounterAddrHigh = 0x14,
263 TxDescStartAddrLow = 0x20,
264 TxDescStartAddrHigh = 0x24,
265 TxHDescStartAddrLow = 0x28,
266 TxHDescStartAddrHigh = 0x2c,
267 FLASH = 0x30,
268 ERSR = 0x36,
269 ChipCmd = 0x37,
270 TxPoll = 0x38,
271 IntrMask = 0x3c,
272 IntrStatus = 0x3e,
273 TxConfig = 0x40,
274 RxConfig = 0x44,
2b7b4318
FR		 275
276#define RTL_RX_CONFIG_MASK 0xff7e1880u
277
07d3f51f
FR		 278 RxMissed = 0x4c,
279 Cfg9346 = 0x50,
280 Config0 = 0x51,
281 Config1 = 0x52,
282 Config2 = 0x53,
283 Config3 = 0x54,
284 Config4 = 0x55,
285 Config5 = 0x56,
286 MultiIntr = 0x5c,
287 PHYAR = 0x60,
07d3f51f
FR		 288 PHYstatus = 0x6c,
289 RxMaxSize = 0xda,
290 CPlusCmd = 0xe0,
291 IntrMitigate = 0xe2,
292 RxDescAddrLow = 0xe4,
293 RxDescAddrHigh = 0xe8,
f0298f81 294 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
295
296#define NoEarlyTx 0x3f /* Max value : no early transmit. */
297
298 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
299
300#define TxPacketMax (8064 >> 7)
301
07d3f51f
FR		 302 FuncEvent = 0xf0,
303 FuncEventMask = 0xf4,
304 FuncPresetState = 0xf8,
305 FuncForceEvent = 0xfc,
1da177e4
LT		 306};
307
f162a5d1
FR		 308enum rtl8110_registers {
309 TBICSR = 0x64,
310 TBI_ANAR = 0x68,
311 TBI_LPAR = 0x6a,
312};
313
314enum rtl8168_8101_registers {
315 CSIDR = 0x64,
316 CSIAR = 0x68,
317#define CSIAR_FLAG 0x80000000
318#define CSIAR_WRITE_CMD 0x80000000
319#define CSIAR_BYTE_ENABLE 0x0f
320#define CSIAR_BYTE_ENABLE_SHIFT 12
321#define CSIAR_ADDR_MASK 0x0fff
065c27c1 322 PMCH = 0x6f,
f162a5d1
FR		 323 EPHYAR = 0x80,
324#define EPHYAR_FLAG 0x80000000
325#define EPHYAR_WRITE_CMD 0x80000000
326#define EPHYAR_REG_MASK 0x1f
327#define EPHYAR_REG_SHIFT 16
328#define EPHYAR_DATA_MASK 0xffff
5a5e4443
HW		 329 DLLPR = 0xd0,
330#define PM_SWITCH (1 << 6)
f162a5d1
FR		 331 DBG_REG = 0xd1,
332#define FIX_NAK_1 (1 << 4)
333#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 334 TWSI = 0xd2,
335 MCU = 0xd3,
336#define EN_NDP (1 << 3)
337#define EN_OOB_RESET (1 << 2)
daf9df6d 338 EFUSEAR = 0xdc,
339#define EFUSEAR_FLAG 0x80000000
340#define EFUSEAR_WRITE_CMD 0x80000000
341#define EFUSEAR_READ_CMD 0x00000000
342#define EFUSEAR_REG_MASK 0x03ff
343#define EFUSEAR_REG_SHIFT 8
344#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 345};
346
c0e45c1c 347enum rtl8168_registers {
b646d900 348 ERIDR = 0x70,
349 ERIAR = 0x74,
350#define ERIAR_FLAG 0x80000000
351#define ERIAR_WRITE_CMD 0x80000000
352#define ERIAR_READ_CMD 0x00000000
353#define ERIAR_ADDR_BYTE_ALIGN 4
354#define ERIAR_EXGMAC 0
355#define ERIAR_MSIX 1
356#define ERIAR_ASF 2
357#define ERIAR_TYPE_SHIFT 16
358#define ERIAR_BYTEEN 0x0f
359#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 360 EPHY_RXER_NUM = 0x7c,
361 OCPDR = 0xb0, /* OCP GPHY access */
362#define OCPDR_WRITE_CMD 0x80000000
363#define OCPDR_READ_CMD 0x00000000
364#define OCPDR_REG_MASK 0x7f
365#define OCPDR_GPHY_REG_SHIFT 16
366#define OCPDR_DATA_MASK 0xffff
367 OCPAR = 0xb4,
368#define OCPAR_FLAG 0x80000000
369#define OCPAR_GPHY_WRITE_CMD 0x8000f060
370#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 371 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
372 MISC = 0xf0, /* 8168e only. */
cecb5fd7 373#define TXPLA_RST (1 << 29)
c0e45c1c 374};
375
07d3f51f 376enum rtl_register_content {
1da177e4 377 /* InterruptStatusBits */
07d3f51f
FR		 378 SYSErr = 0x8000,
379 PCSTimeout = 0x4000,
380 SWInt = 0x0100,
381 TxDescUnavail = 0x0080,
382 RxFIFOOver = 0x0040,
383 LinkChg = 0x0020,
384 RxOverflow = 0x0010,
385 TxErr = 0x0008,
386 TxOK = 0x0004,
387 RxErr = 0x0002,
388 RxOK = 0x0001,
1da177e4
LT		 389
390 /* RxStatusDesc */
9dccf611
FR		 391 RxFOVF = (1 << 23),
392 RxRWT = (1 << 22),
393 RxRES = (1 << 21),
394 RxRUNT = (1 << 20),
395 RxCRC = (1 << 19),
1da177e4
LT		 396
397 /* ChipCmdBits */
07d3f51f
FR		 398 CmdReset = 0x10,
399 CmdRxEnb = 0x08,
400 CmdTxEnb = 0x04,
401 RxBufEmpty = 0x01,
1da177e4 402
275391a4
FR		 403 /* TXPoll register p.5 */
404 HPQ = 0x80, /* Poll cmd on the high prio queue */
405 NPQ = 0x40, /* Poll cmd on the low prio queue */
406 FSWInt = 0x01, /* Forced software interrupt */
407
1da177e4 408 /* Cfg9346Bits */
07d3f51f
FR		 409 Cfg9346_Lock = 0x00,
410 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 411
412 /* rx_mode_bits */
07d3f51f
FR		 413 AcceptErr = 0x20,
414 AcceptRunt = 0x10,
415 AcceptBroadcast = 0x08,
416 AcceptMulticast = 0x04,
417 AcceptMyPhys = 0x02,
418 AcceptAllPhys = 0x01,
1da177e4
LT		 419
420 /* RxConfigBits */
07d3f51f
FR		 421 RxCfgFIFOShift = 13,
422 RxCfgDMAShift = 8,
1da177e4
LT		 423
424 /* TxConfigBits */
425 TxInterFrameGapShift = 24,
426 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
427
5d06a99f 428 /* Config1 register p.24 */
f162a5d1
FR		 429 LEDS1 = (1 << 7),
430 LEDS0 = (1 << 6),
fbac58fc 431 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 432 Speed_down = (1 << 4),
433 MEMMAP = (1 << 3),
434 IOMAP = (1 << 2),
435 VPD = (1 << 1),
5d06a99f
FR		 436 PMEnable = (1 << 0), /* Power Management Enable */
437
6dccd16b
FR		 438 /* Config2 register p. 25 */
439 PCI_Clock_66MHz = 0x01,
440 PCI_Clock_33MHz = 0x00,
441
61a4dcc2
FR		 442 /* Config3 register p.25 */
443 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
444 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 445 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 446
5d06a99f 447 /* Config5 register p.27 */
61a4dcc2
FR		 448 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
449 MWF = (1 << 5), /* Accept Multicast wakeup frame */
450 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 451 Spi_en = (1 << 3),
61a4dcc2 452 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 453 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
454
1da177e4
LT		 455 /* TBICSR p.28 */
456 TBIReset = 0x80000000,
457 TBILoopback = 0x40000000,
458 TBINwEnable = 0x20000000,
459 TBINwRestart = 0x10000000,
460 TBILinkOk = 0x02000000,
461 TBINwComplete = 0x01000000,
462
463 /* CPlusCmd p.31 */
f162a5d1
FR		 464 EnableBist = (1 << 15), // 8168 8101
465 Mac_dbgo_oe = (1 << 14), // 8168 8101
466 Normal_mode = (1 << 13), // unused
467 Force_half_dup = (1 << 12), // 8168 8101
468 Force_rxflow_en = (1 << 11), // 8168 8101
469 Force_txflow_en = (1 << 10), // 8168 8101
470 Cxpl_dbg_sel = (1 << 9), // 8168 8101
471 ASF = (1 << 8), // 8168 8101
472 PktCntrDisable = (1 << 7), // 8168 8101
473 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 474 RxVlan = (1 << 6),
475 RxChkSum = (1 << 5),
476 PCIDAC = (1 << 4),
477 PCIMulRW = (1 << 3),
0e485150
FR		 478 INTT_0 = 0x0000, // 8168
479 INTT_1 = 0x0001, // 8168
480 INTT_2 = 0x0002, // 8168
481 INTT_3 = 0x0003, // 8168
1da177e4
LT		 482
483 /* rtl8169_PHYstatus */
07d3f51f
FR		 484 TBI_Enable = 0x80,
485 TxFlowCtrl = 0x40,
486 RxFlowCtrl = 0x20,
487 _1000bpsF = 0x10,
488 _100bps = 0x08,
489 _10bps = 0x04,
490 LinkStatus = 0x02,
491 FullDup = 0x01,
1da177e4 492
1da177e4 493 /* _TBICSRBit */
07d3f51f 494 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 495
496 /* DumpCounterCommand */
07d3f51f 497 CounterDump = 0x8,
1da177e4
LT		 498};
499
2b7b4318
FR		 500enum rtl_desc_bit {
501 /* First doubleword. */
1da177e4
LT		 502 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
503 RingEnd = (1 << 30), /* End of descriptor ring */
504 FirstFrag = (1 << 29), /* First segment of a packet */
505 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 506};
507
508/* Generic case. */
509enum rtl_tx_desc_bit {
510 /* First doubleword. */
511 TD_LSO = (1 << 27), /* Large Send Offload */
512#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 513
2b7b4318
FR		 514 /* Second doubleword. */
515 TxVlanTag = (1 << 17), /* Add VLAN tag */
516};
517
518/* 8169, 8168b and 810x except 8102e. */
519enum rtl_tx_desc_bit_0 {
520 /* First doubleword. */
521#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
522 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
523 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
524 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
525};
526
527/* 8102e, 8168c and beyond. */
528enum rtl_tx_desc_bit_1 {
529 /* Second doubleword. */
530#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
531 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
532 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
533 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
534};
1da177e4 535
2b7b4318
FR		 536static const struct rtl_tx_desc_info {
537 struct {
538 u32 udp;
539 u32 tcp;
540 } checksum;
541 u16 mss_shift;
542 u16 opts_offset;
543} tx_desc_info [] = {
544 [RTL_TD_0] = {
545 .checksum = {
546 .udp = TD0_IP_CS | TD0_UDP_CS,
547 .tcp = TD0_IP_CS | TD0_TCP_CS
548 },
549 .mss_shift = TD0_MSS_SHIFT,
550 .opts_offset = 0
551 },
552 [RTL_TD_1] = {
553 .checksum = {
554 .udp = TD1_IP_CS | TD1_UDP_CS,
555 .tcp = TD1_IP_CS | TD1_TCP_CS
556 },
557 .mss_shift = TD1_MSS_SHIFT,
558 .opts_offset = 1
559 }
560};
561
562enum rtl_rx_desc_bit {
1da177e4
LT		 563 /* Rx private */
564 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
565 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
566
567#define RxProtoUDP (PID1)
568#define RxProtoTCP (PID0)
569#define RxProtoIP (PID1 | PID0)
570#define RxProtoMask RxProtoIP
571
572 IPFail = (1 << 16), /* IP checksum failed */
573 UDPFail = (1 << 15), /* UDP/IP checksum failed */
574 TCPFail = (1 << 14), /* TCP/IP checksum failed */
575 RxVlanTag = (1 << 16), /* VLAN tag available */
576};
577
578#define RsvdMask 0x3fffc000
579
580struct TxDesc {
6cccd6e7
REB		 581 __le32 opts1;
582 __le32 opts2;
583 __le64 addr;
1da177e4
LT		 584};
585
586struct RxDesc {
6cccd6e7
REB		 587 __le32 opts1;
588 __le32 opts2;
589 __le64 addr;
1da177e4
LT		 590};
591
592struct ring_info {
593 struct sk_buff *skb;
594 u32 len;
595 u8 __pad[sizeof(void *) - sizeof(u32)];
596};
597
f23e7fda 598enum features {
ccdffb9a
FR		 599 RTL_FEATURE_WOL = (1 << 0),
600 RTL_FEATURE_MSI = (1 << 1),
601 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 602};
603
355423d0
IV		 604struct rtl8169_counters {
605 __le64 tx_packets;
606 __le64 rx_packets;
607 __le64 tx_errors;
608 __le32 rx_errors;
609 __le16 rx_missed;
610 __le16 align_errors;
611 __le32 tx_one_collision;
612 __le32 tx_multi_collision;
613 __le64 rx_unicast;
614 __le64 rx_broadcast;
615 __le32 rx_multicast;
616 __le16 tx_aborted;
617 __le16 tx_underun;
618};
619
1da177e4
LT		 620struct rtl8169_private {
621 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 622 struct pci_dev *pci_dev;
c4028958 623 struct net_device *dev;
bea3348e 624 struct napi_struct napi;
cecb5fd7 625 spinlock_t lock;
b57b7e5a 626 u32 msg_enable;
2b7b4318
FR		 627 u16 txd_version;
628 u16 mac_version;
1da177e4
LT		 629 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
630 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
631 u32 dirty_rx;
632 u32 dirty_tx;
633 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
634 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
635 dma_addr_t TxPhyAddr;
636 dma_addr_t RxPhyAddr;
6f0333b8 637 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 638 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 639 struct timer_list timer;
640 u16 cp_cmd;
0e485150
FR		 641 u16 intr_event;
642 u16 napi_event;
1da177e4 643 u16 intr_mask;
c0e45c1c 644
645 struct mdio_ops {
646 void (*write)(void __iomem *, int, int);
647 int (*read)(void __iomem *, int);
648 } mdio_ops;
649
065c27c1 650 struct pll_power_ops {
651 void (*down)(struct rtl8169_private *);
652 void (*up)(struct rtl8169_private *);
653 } pll_power_ops;
654
54405cde 655 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 656 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 657 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 658 void (*hw_start)(struct net_device *);
4da19633 659 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 660 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 661 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 662 int pcie_cap;
c4028958 663 struct delayed_work task;
f23e7fda 664 unsigned features;
ccdffb9a
FR		 665
666 struct mii_if_info mii;
355423d0 667 struct rtl8169_counters counters;
e1759441 668 u32 saved_wolopts;
f1e02ed1 669
b6ffd97f
FR		 670 struct rtl_fw {
671 const struct firmware *fw;
672 } *rtl_fw;
953a12cc 673#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
1da177e4
LT		 674};
675
979b6c13 676MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 677MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 678module_param(use_dac, int, 0);
4300e8c7 679MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 680module_param_named(debug, debug.msg_enable, int, 0);
681MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 682MODULE_LICENSE("GPL");
683MODULE_VERSION(RTL8169_VERSION);
bca03d5f 684MODULE_FIRMWARE(FIRMWARE_8168D_1);
685MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 686MODULE_FIRMWARE(FIRMWARE_8168E_1);
687MODULE_FIRMWARE(FIRMWARE_8168E_2);
5a5e4443 688MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 689
690static int rtl8169_open(struct net_device *dev);
61357325
SH		 691static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
692 struct net_device *dev);
7d12e780 693static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 694static int rtl8169_init_ring(struct net_device *dev);
07ce4064 695static void rtl_hw_start(struct net_device *dev);
1da177e4 696static int rtl8169_close(struct net_device *dev);
07ce4064 697static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 698static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 699static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 700static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 701 void __iomem *, u32 budget);
4dcb7d33 702static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 703static void rtl8169_down(struct net_device *dev);
99f252b0 704static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 705static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 706
1da177e4 707static const unsigned int rtl8169_rx_config =
5b0384f4 708 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 709
b646d900 710static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
711{
712 void __iomem *ioaddr = tp->mmio_addr;
713 int i;
714
715 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
716 for (i = 0; i < 20; i++) {
717 udelay(100);
718 if (RTL_R32(OCPAR) & OCPAR_FLAG)
719 break;
720 }
721 return RTL_R32(OCPDR);
722}
723
724static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
725{
726 void __iomem *ioaddr = tp->mmio_addr;
727 int i;
728
729 RTL_W32(OCPDR, data);
730 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
731 for (i = 0; i < 20; i++) {
732 udelay(100);
733 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
734 break;
735 }
736}
737
fac5b3ca 738static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 739{
fac5b3ca 740 void __iomem *ioaddr = tp->mmio_addr;
b646d900 741 int i;
742
743 RTL_W8(ERIDR, cmd);
744 RTL_W32(ERIAR, 0x800010e8);
745 msleep(2);
746 for (i = 0; i < 5; i++) {
747 udelay(100);
748 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
749 break;
750 }
751
fac5b3ca 752 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 753}
754
755#define OOB_CMD_RESET 0x00
756#define OOB_CMD_DRIVER_START 0x05
757#define OOB_CMD_DRIVER_STOP 0x06
758
cecb5fd7
FR		 759static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
760{
761 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
762}
763
b646d900 764static void rtl8168_driver_start(struct rtl8169_private *tp)
765{
cecb5fd7 766 u16 reg;
b646d900 767 int i;
768
769 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
770
cecb5fd7 771 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 772
b646d900 773 for (i = 0; i < 10; i++) {
774 msleep(10);
4804b3b3 775 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 776 break;
777 }
778}
779
780static void rtl8168_driver_stop(struct rtl8169_private *tp)
781{
cecb5fd7 782 u16 reg;
b646d900 783 int i;
784
785 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
786
cecb5fd7 787 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 788
b646d900 789 for (i = 0; i < 10; i++) {
790 msleep(10);
4804b3b3 791 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 792 break;
793 }
794}
795
4804b3b3 796static int r8168dp_check_dash(struct rtl8169_private *tp)
797{
cecb5fd7 798 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 799
cecb5fd7 800 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 801}
b646d900 802
4da19633 803static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 804{
805 int i;
806
a6baf3af 807 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 808
2371408c 809 for (i = 20; i > 0; i--) {
07d3f51f
FR		 810 /*
811 * Check if the RTL8169 has completed writing to the specified
812 * MII register.
813 */
5b0384f4 814 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 815 break;
2371408c 816 udelay(25);
1da177e4 817 }
024a07ba 818 /*
81a95f04
TT		 819 * According to hardware specs a 20us delay is required after write
820 * complete indication, but before sending next command.
024a07ba 821 */
81a95f04 822 udelay(20);
1da177e4
LT		 823}
824
4da19633 825static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 826{
827 int i, value = -1;
828
a6baf3af 829 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 830
2371408c 831 for (i = 20; i > 0; i--) {
07d3f51f
FR		 832 /*
833 * Check if the RTL8169 has completed retrieving data from
834 * the specified MII register.
835 */
1da177e4 836 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 837 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 838 break;
839 }
2371408c 840 udelay(25);
1da177e4 841 }
81a95f04
TT		 842 /*
843 * According to hardware specs a 20us delay is required after read
844 * complete indication, but before sending next command.
845 */
846 udelay(20);
847
1da177e4
LT		 848 return value;
849}
850
c0e45c1c 851static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
852{
853 int i;
854
855 RTL_W32(OCPDR, data |
856 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
857 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
858 RTL_W32(EPHY_RXER_NUM, 0);
859
860 for (i = 0; i < 100; i++) {
861 mdelay(1);
862 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
863 break;
864 }
865}
866
867static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
868{
869 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
870 (value & OCPDR_DATA_MASK));
871}
872
873static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
874{
875 int i;
876
877 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
878
879 mdelay(1);
880 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
881 RTL_W32(EPHY_RXER_NUM, 0);
882
883 for (i = 0; i < 100; i++) {
884 mdelay(1);
885 if (RTL_R32(OCPAR) & OCPAR_FLAG)
886 break;
887 }
888
889 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
890}
891
e6de30d6 892#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
893
894static void r8168dp_2_mdio_start(void __iomem *ioaddr)
895{
896 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
897}
898
899static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
900{
901 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
902}
903
904static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
905{
906 r8168dp_2_mdio_start(ioaddr);
907
908 r8169_mdio_write(ioaddr, reg_addr, value);
909
910 r8168dp_2_mdio_stop(ioaddr);
911}
912
913static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
914{
915 int value;
916
917 r8168dp_2_mdio_start(ioaddr);
918
919 value = r8169_mdio_read(ioaddr, reg_addr);
920
921 r8168dp_2_mdio_stop(ioaddr);
922
923 return value;
924}
925
4da19633 926static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 927{
c0e45c1c 928 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 929}
930
4da19633 931static int rtl_readphy(struct rtl8169_private *tp, int location)
932{
c0e45c1c 933 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 934}
935
936static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
937{
938 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
939}
940
941static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 942{
943 int val;
944
4da19633 945 val = rtl_readphy(tp, reg_addr);
946 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 947}
948
ccdffb9a
FR		 949static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
950 int val)
951{
952 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 953
4da19633 954 rtl_writephy(tp, location, val);
ccdffb9a
FR		 955}
956
957static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
958{
959 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 960
4da19633 961 return rtl_readphy(tp, location);
ccdffb9a
FR		 962}
963
dacf8154
FR		 964static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
965{
966 unsigned int i;
967
968 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
969 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
970
971 for (i = 0; i < 100; i++) {
972 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
973 break;
974 udelay(10);
975 }
976}
977
978static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
979{
980 u16 value = 0xffff;
981 unsigned int i;
982
983 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
984
985 for (i = 0; i < 100; i++) {
986 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
987 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
988 break;
989 }
990 udelay(10);
991 }
992
993 return value;
994}
995
996static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
997{
998 unsigned int i;
999
1000 RTL_W32(CSIDR, value);
1001 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1002 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1003
1004 for (i = 0; i < 100; i++) {
1005 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1006 break;
1007 udelay(10);
1008 }
1009}
1010
1011static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1012{
1013 u32 value = ~0x00;
1014 unsigned int i;
1015
1016 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1017 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1018
1019 for (i = 0; i < 100; i++) {
1020 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1021 value = RTL_R32(CSIDR);
1022 break;
1023 }
1024 udelay(10);
1025 }
1026
1027 return value;
1028}
1029
daf9df6d 1030static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1031{
1032 u8 value = 0xff;
1033 unsigned int i;
1034
1035 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1036
1037 for (i = 0; i < 300; i++) {
1038 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1039 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1040 break;
1041 }
1042 udelay(100);
1043 }
1044
1045 return value;
1046}
1047
1da177e4
LT		 1048static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1049{
1050 RTL_W16(IntrMask, 0x0000);
1051
1052 RTL_W16(IntrStatus, 0xffff);
1053}
1054
1055static void rtl8169_asic_down(void __iomem *ioaddr)
1056{
1057 RTL_W8(ChipCmd, 0x00);
1058 rtl8169_irq_mask_and_ack(ioaddr);
1059 RTL_R16(CPlusCmd);
1060}
1061
4da19633 1062static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1063{
4da19633 1064 void __iomem *ioaddr = tp->mmio_addr;
1065
1da177e4
LT		 1066 return RTL_R32(TBICSR) & TBIReset;
1067}
1068
4da19633 1069static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1070{
4da19633 1071 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1072}
1073
1074static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1075{
1076 return RTL_R32(TBICSR) & TBILinkOk;
1077}
1078
1079static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1080{
1081 return RTL_R8(PHYstatus) & LinkStatus;
1082}
1083
4da19633 1084static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1085{
4da19633 1086 void __iomem *ioaddr = tp->mmio_addr;
1087
1da177e4
LT		 1088 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1089}
1090
4da19633 1091static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1092{
1093 unsigned int val;
1094
4da19633 1095 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1096 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1097}
1098
e4fbce74 1099static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1100 struct rtl8169_private *tp,
1101 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1102{
1103 unsigned long flags;
1104
1105 spin_lock_irqsave(&tp->lock, flags);
1106 if (tp->link_ok(ioaddr)) {
e1759441 1107 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1108 if (pm)
1109 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1110 netif_carrier_on(dev);
1519e57f
FR		 1111 if (net_ratelimit())
1112 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1113 } else {
1da177e4 1114 netif_carrier_off(dev);
bf82c189 1115 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1116 if (pm)
1117 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1118 }
1da177e4
LT		 1119 spin_unlock_irqrestore(&tp->lock, flags);
1120}
1121
e4fbce74
RW		 1122static void rtl8169_check_link_status(struct net_device *dev,
1123 struct rtl8169_private *tp,
1124 void __iomem *ioaddr)
1125{
1126 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1127}
1128
e1759441
RW		 1129#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1130
1131static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1132{
61a4dcc2
FR		 1133 void __iomem *ioaddr = tp->mmio_addr;
1134 u8 options;
e1759441 1135 u32 wolopts = 0;
61a4dcc2
FR		 1136
1137 options = RTL_R8(Config1);
1138 if (!(options & PMEnable))
e1759441 1139 return 0;
61a4dcc2
FR		 1140
1141 options = RTL_R8(Config3);
1142 if (options & LinkUp)
e1759441 1143 wolopts |= WAKE_PHY;
61a4dcc2 1144 if (options & MagicPacket)
e1759441 1145 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1146
1147 options = RTL_R8(Config5);
1148 if (options & UWF)
e1759441 1149 wolopts |= WAKE_UCAST;
61a4dcc2 1150 if (options & BWF)
e1759441 1151 wolopts |= WAKE_BCAST;
61a4dcc2 1152 if (options & MWF)
e1759441 1153 wolopts |= WAKE_MCAST;
61a4dcc2 1154
e1759441 1155 return wolopts;
61a4dcc2
FR		 1156}
1157
e1759441 1158static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1159{
1160 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1161
1162 spin_lock_irq(&tp->lock);
1163
1164 wol->supported = WAKE_ANY;
1165 wol->wolopts = __rtl8169_get_wol(tp);
1166
1167 spin_unlock_irq(&tp->lock);
1168}
1169
1170static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1171{
61a4dcc2 1172 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1173 unsigned int i;
350f7596 1174 static const struct {
61a4dcc2
FR		 1175 u32 opt;
1176 u16 reg;
1177 u8 mask;
1178 } cfg[] = {
1179 { WAKE_ANY, Config1, PMEnable },
1180 { WAKE_PHY, Config3, LinkUp },
1181 { WAKE_MAGIC, Config3, MagicPacket },
1182 { WAKE_UCAST, Config5, UWF },
1183 { WAKE_BCAST, Config5, BWF },
1184 { WAKE_MCAST, Config5, MWF },
1185 { WAKE_ANY, Config5, LanWake }
1186 };
1187
61a4dcc2
FR		 1188 RTL_W8(Cfg9346, Cfg9346_Unlock);
1189
1190 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1191 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1192 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1193 options |= cfg[i].mask;
1194 RTL_W8(cfg[i].reg, options);
1195 }
1196
1197 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1198}
1199
1200static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1201{
1202 struct rtl8169_private *tp = netdev_priv(dev);
1203
1204 spin_lock_irq(&tp->lock);
61a4dcc2 1205
f23e7fda
FR		 1206 if (wol->wolopts)
1207 tp->features |= RTL_FEATURE_WOL;
1208 else
1209 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1210 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1211 spin_unlock_irq(&tp->lock);
1212
ea80907f 1213 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1214
61a4dcc2
FR		 1215 return 0;
1216}
1217
31bd204f
FR		 1218static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1219{
85bffe6c 1220 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1221}
1222
1da177e4
LT		 1223static void rtl8169_get_drvinfo(struct net_device *dev,
1224 struct ethtool_drvinfo *info)
1225{
1226 struct rtl8169_private *tp = netdev_priv(dev);
b6ffd97f 1227 struct rtl_fw *rtl_fw = tp->rtl_fw;
1da177e4
LT		 1228
1229 strcpy(info->driver, MODULENAME);
1230 strcpy(info->version, RTL8169_VERSION);
1231 strcpy(info->bus_info, pci_name(tp->pci_dev));
b6ffd97f 1232 strncpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
31bd204f 1233 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1da177e4
LT		 1234}
1235
1236static int rtl8169_get_regs_len(struct net_device *dev)
1237{
1238 return R8169_REGS_SIZE;
1239}
1240
1241static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1242 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1243{
1244 struct rtl8169_private *tp = netdev_priv(dev);
1245 void __iomem *ioaddr = tp->mmio_addr;
1246 int ret = 0;
1247 u32 reg;
1248
1249 reg = RTL_R32(TBICSR);
1250 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1251 (duplex == DUPLEX_FULL)) {
1252 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1253 } else if (autoneg == AUTONEG_ENABLE)
1254 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1255 else {
bf82c189
JP		 1256 netif_warn(tp, link, dev,
1257 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1258 ret = -EOPNOTSUPP;
1259 }
1260
1261 return ret;
1262}
1263
1264static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1265 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1266{
1267 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1268 int giga_ctrl, bmcr;
54405cde 1269 int rc = -EINVAL;
1da177e4 1270
716b50a3 1271 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1272
1273 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1274 int auto_nego;
1275
4da19633 1276 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1277 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1278 ADVERTISE_100HALF | ADVERTISE_100FULL);
1279
1280 if (adv & ADVERTISED_10baseT_Half)
1281 auto_nego |= ADVERTISE_10HALF;
1282 if (adv & ADVERTISED_10baseT_Full)
1283 auto_nego |= ADVERTISE_10FULL;
1284 if (adv & ADVERTISED_100baseT_Half)
1285 auto_nego |= ADVERTISE_100HALF;
1286 if (adv & ADVERTISED_100baseT_Full)
1287 auto_nego |= ADVERTISE_100FULL;
1288
3577aa1b 1289 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1290
4da19633 1291 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1292 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1293
3577aa1b 1294 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1295 if (tp->mii.supports_gmii) {
54405cde
ON		 1296 if (adv & ADVERTISED_1000baseT_Half)
1297 giga_ctrl |= ADVERTISE_1000HALF;
1298 if (adv & ADVERTISED_1000baseT_Full)
1299 giga_ctrl |= ADVERTISE_1000FULL;
1300 } else if (adv & (ADVERTISED_1000baseT_Half |
1301 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1302 netif_info(tp, link, dev,
1303 "PHY does not support 1000Mbps\n");
54405cde 1304 goto out;
bcf0bf90 1305 }
1da177e4 1306
3577aa1b 1307 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1308
4da19633 1309 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1310 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1311 } else {
1312 giga_ctrl = 0;
1313
1314 if (speed == SPEED_10)
1315 bmcr = 0;
1316 else if (speed == SPEED_100)
1317 bmcr = BMCR_SPEED100;
1318 else
54405cde 1319 goto out;
3577aa1b 1320
1321 if (duplex == DUPLEX_FULL)
1322 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1323 }
1324
4da19633 1325 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1326
cecb5fd7
FR		 1327 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1328 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1329 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1330 rtl_writephy(tp, 0x17, 0x2138);
1331 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1332 } else {
4da19633 1333 rtl_writephy(tp, 0x17, 0x2108);
1334 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1335 }
1336 }
1337
54405cde
ON		 1338 rc = 0;
1339out:
1340 return rc;
1da177e4
LT		 1341}
1342
1343static int rtl8169_set_speed(struct net_device *dev,
54405cde 1344 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1345{
1346 struct rtl8169_private *tp = netdev_priv(dev);
1347 int ret;
1348
54405cde 1349 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1350 if (ret < 0)
1351 goto out;
1da177e4 1352
4876cc1e
FR		 1353 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1354 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1355 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1356 }
1357out:
1da177e4
LT		 1358 return ret;
1359}
1360
1361static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1362{
1363 struct rtl8169_private *tp = netdev_priv(dev);
1364 unsigned long flags;
1365 int ret;
1366
4876cc1e
FR		 1367 del_timer_sync(&tp->timer);
1368
1da177e4 1369 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1370 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1371 cmd->duplex, cmd->advertising);
1da177e4 1372 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1373
1da177e4
LT		 1374 return ret;
1375}
1376
350fb32a 1377static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1378{
2b7b4318 1379 if (dev->mtu > TD_MSS_MAX)
350fb32a 1380 features &= ~NETIF_F_ALL_TSO;
1da177e4 1381
350fb32a 1382 return features;
1da177e4
LT		 1383}
1384
350fb32a 1385static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1386{
1387 struct rtl8169_private *tp = netdev_priv(dev);
1388 void __iomem *ioaddr = tp->mmio_addr;
1389 unsigned long flags;
1390
1391 spin_lock_irqsave(&tp->lock, flags);
1392
350fb32a 1393 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1394 tp->cp_cmd |= RxChkSum;
1395 else
1396 tp->cp_cmd &= ~RxChkSum;
1397
350fb32a
MM		 1398 if (dev->features & NETIF_F_HW_VLAN_RX)
1399 tp->cp_cmd |= RxVlan;
1400 else
1401 tp->cp_cmd &= ~RxVlan;
1402
1da177e4
LT		 1403 RTL_W16(CPlusCmd, tp->cp_cmd);
1404 RTL_R16(CPlusCmd);
1405
1406 spin_unlock_irqrestore(&tp->lock, flags);
1407
1408 return 0;
1409}
1410
1da177e4
LT		 1411static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1412 struct sk_buff *skb)
1413{
eab6d18d 1414 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1415 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1416}
1417
7a8fc77b 1418static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1419{
1420 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1421
7a8fc77b
FR		 1422 if (opts2 & RxVlanTag)
1423 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1424
1da177e4 1425 desc->opts2 = 0;
1da177e4
LT		 1426}
1427
ccdffb9a 1428static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1429{
1430 struct rtl8169_private *tp = netdev_priv(dev);
1431 void __iomem *ioaddr = tp->mmio_addr;
1432 u32 status;
1433
1434 cmd->supported =
1435 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1436 cmd->port = PORT_FIBRE;
1437 cmd->transceiver = XCVR_INTERNAL;
1438
1439 status = RTL_R32(TBICSR);
1440 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1441 cmd->autoneg = !!(status & TBINwEnable);
1442
70739497 1443 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1444 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1445
1446 return 0;
1da177e4
LT		 1447}
1448
ccdffb9a 1449static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1450{
1451 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1452
1453 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1454}
1455
1456static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1457{
1458 struct rtl8169_private *tp = netdev_priv(dev);
1459 unsigned long flags;
ccdffb9a 1460 int rc;
1da177e4
LT		 1461
1462 spin_lock_irqsave(&tp->lock, flags);
1463
ccdffb9a 1464 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1465
1466 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1467 return rc;
1da177e4
LT		 1468}
1469
1470static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1471 void *p)
1472{
5b0384f4
FR		 1473 struct rtl8169_private *tp = netdev_priv(dev);
1474 unsigned long flags;
1da177e4 1475
5b0384f4
FR		 1476 if (regs->len > R8169_REGS_SIZE)
1477 regs->len = R8169_REGS_SIZE;
1da177e4 1478
5b0384f4
FR		 1479 spin_lock_irqsave(&tp->lock, flags);
1480 memcpy_fromio(p, tp->mmio_addr, regs->len);
1481 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1482}
1483
b57b7e5a
SH		 1484static u32 rtl8169_get_msglevel(struct net_device *dev)
1485{
1486 struct rtl8169_private *tp = netdev_priv(dev);
1487
1488 return tp->msg_enable;
1489}
1490
1491static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1492{
1493 struct rtl8169_private *tp = netdev_priv(dev);
1494
1495 tp->msg_enable = value;
1496}
1497
d4a3a0fc
SH		 1498static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1499 "tx_packets",
1500 "rx_packets",
1501 "tx_errors",
1502 "rx_errors",
1503 "rx_missed",
1504 "align_errors",
1505 "tx_single_collisions",
1506 "tx_multi_collisions",
1507 "unicast",
1508 "broadcast",
1509 "multicast",
1510 "tx_aborted",
1511 "tx_underrun",
1512};
1513
b9f2c044 1514static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1515{
b9f2c044
JG		 1516 switch (sset) {
1517 case ETH_SS_STATS:
1518 return ARRAY_SIZE(rtl8169_gstrings);
1519 default:
1520 return -EOPNOTSUPP;
1521 }
d4a3a0fc
SH		 1522}
1523
355423d0 1524static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1525{
1526 struct rtl8169_private *tp = netdev_priv(dev);
1527 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1528 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1529 struct rtl8169_counters *counters;
1530 dma_addr_t paddr;
1531 u32 cmd;
355423d0 1532 int wait = 1000;
d4a3a0fc 1533
355423d0
IV		 1534 /*
1535 * Some chips are unable to dump tally counters when the receiver
1536 * is disabled.
1537 */
1538 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1539 return;
d4a3a0fc 1540
48addcc9 1541 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1542 if (!counters)
1543 return;
1544
1545 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1546 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1547 RTL_W32(CounterAddrLow, cmd);
1548 RTL_W32(CounterAddrLow, cmd | CounterDump);
1549
355423d0
IV		 1550 while (wait--) {
1551 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1552 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1553 break;
355423d0
IV		 1554 }
1555 udelay(10);
d4a3a0fc
SH		 1556 }
1557
1558 RTL_W32(CounterAddrLow, 0);
1559 RTL_W32(CounterAddrHigh, 0);
1560
48addcc9 1561 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1562}
1563
355423d0
IV		 1564static void rtl8169_get_ethtool_stats(struct net_device *dev,
1565 struct ethtool_stats *stats, u64 *data)
1566{
1567 struct rtl8169_private *tp = netdev_priv(dev);
1568
1569 ASSERT_RTNL();
1570
1571 rtl8169_update_counters(dev);
1572
1573 data[0] = le64_to_cpu(tp->counters.tx_packets);
1574 data[1] = le64_to_cpu(tp->counters.rx_packets);
1575 data[2] = le64_to_cpu(tp->counters.tx_errors);
1576 data[3] = le32_to_cpu(tp->counters.rx_errors);
1577 data[4] = le16_to_cpu(tp->counters.rx_missed);
1578 data[5] = le16_to_cpu(tp->counters.align_errors);
1579 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1580 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1581 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1582 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1583 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1584 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1585 data[12] = le16_to_cpu(tp->counters.tx_underun);
1586}
1587
d4a3a0fc
SH		 1588static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1589{
1590 switch(stringset) {
1591 case ETH_SS_STATS:
1592 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1593 break;
1594 }
1595}
1596
7282d491 1597static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1598 .get_drvinfo = rtl8169_get_drvinfo,
1599 .get_regs_len = rtl8169_get_regs_len,
1600 .get_link = ethtool_op_get_link,
1601 .get_settings = rtl8169_get_settings,
1602 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1603 .get_msglevel = rtl8169_get_msglevel,
1604 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1605 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1606 .get_wol = rtl8169_get_wol,
1607 .set_wol = rtl8169_set_wol,
d4a3a0fc 1608 .get_strings = rtl8169_get_strings,
b9f2c044 1609 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1610 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1611};
1612
07d3f51f 1613static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1614 struct net_device *dev, u8 default_version)
1da177e4 1615{
5d320a20 1616 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1617 /*
1618 * The driver currently handles the 8168Bf and the 8168Be identically
1619 * but they can be identified more specifically through the test below
1620 * if needed:
1621 *
1622 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1623 *
1624 * Same thing for the 8101Eb and the 8101Ec:
1625 *
1626 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1627 */
350f7596 1628 static const struct {
1da177e4 1629 u32 mask;
e3cf0cc0 1630 u32 val;
1da177e4
LT		 1631 int mac_version;
1632 } mac_info[] = {
01dc7fec 1633 /* 8168E family. */
1634 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1635 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1636 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1637
5b538df9 1638 /* 8168D family. */
daf9df6d 1639 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1640 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1641 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1642
e6de30d6 1643 /* 8168DP family. */
1644 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1645 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1646 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1647
ef808d50 1648 /* 8168C family. */
17c99297 1649 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1650 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1651 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1652 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1653 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1654 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1655 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1656 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1657 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1658
1659 /* 8168B family. */
1660 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1661 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1662 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1663 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1664
1665 /* 8101 family. */
36a0e6c2 1666 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1667 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1668 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1669 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1670 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1671 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1672 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1673 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1674 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1675 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1676 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1677 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1678 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1679 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1680 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1681 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1682 /* FIXME: where did these entries come from ? -- FR */
1683 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1684 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1685
1686 /* 8110 family. */
1687 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1688 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1689 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1690 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1691 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1692 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1693
f21b75e9
JD		 1694 /* Catch-all */
1695 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1696 }, *p = mac_info;
1697 u32 reg;
1698
e3cf0cc0
FR		 1699 reg = RTL_R32(TxConfig);
1700 while ((reg & p->mask) != p->val)
1da177e4
LT		 1701 p++;
1702 tp->mac_version = p->mac_version;
5d320a20
FR		 1703
1704 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1705 netif_notice(tp, probe, dev,
1706 "unknown MAC, using family default\n");
1707 tp->mac_version = default_version;
1708 }
1da177e4
LT		 1709}
1710
1711static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1712{
bcf0bf90 1713 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1714}
1715
867763c1
FR		 1716struct phy_reg {
1717 u16 reg;
1718 u16 val;
1719};
1720
4da19633 1721static void rtl_writephy_batch(struct rtl8169_private *tp,
1722 const struct phy_reg *regs, int len)
867763c1
FR		 1723{
1724 while (len-- > 0) {
4da19633 1725 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1726 regs++;
1727 }
1728}
1729
bca03d5f 1730#define PHY_READ 0x00000000
1731#define PHY_DATA_OR 0x10000000
1732#define PHY_DATA_AND 0x20000000
1733#define PHY_BJMPN 0x30000000
1734#define PHY_READ_EFUSE 0x40000000
1735#define PHY_READ_MAC_BYTE 0x50000000
1736#define PHY_WRITE_MAC_BYTE 0x60000000
1737#define PHY_CLEAR_READCOUNT 0x70000000
1738#define PHY_WRITE 0x80000000
1739#define PHY_READCOUNT_EQ_SKIP 0x90000000
1740#define PHY_COMP_EQ_SKIPN 0xa0000000
1741#define PHY_COMP_NEQ_SKIPN 0xb0000000
1742#define PHY_WRITE_PREVIOUS 0xc0000000
1743#define PHY_SKIPN 0xd0000000
1744#define PHY_DELAY_MS 0xe0000000
1745#define PHY_WRITE_ERI_WORD 0xf0000000
1746
b6ffd97f 1747static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
bca03d5f 1748{
b6ffd97f 1749 const struct firmware *fw = rtl_fw->fw;
bca03d5f 1750 __le32 *phytable = (__le32 *)fw->data;
1751 struct net_device *dev = tp->dev;
42b82dc1 1752 size_t index, fw_size = fw->size / sizeof(*phytable);
1753 u32 predata, count;
bca03d5f 1754
1755 if (fw->size % sizeof(*phytable)) {
1756 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1757 return;
1758 }
1759
42b82dc1 1760 for (index = 0; index < fw_size; index++) {
1761 u32 action = le32_to_cpu(phytable[index]);
1762 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1763
42b82dc1 1764 switch(action & 0xf0000000) {
1765 case PHY_READ:
1766 case PHY_DATA_OR:
1767 case PHY_DATA_AND:
1768 case PHY_READ_EFUSE:
1769 case PHY_CLEAR_READCOUNT:
1770 case PHY_WRITE:
1771 case PHY_WRITE_PREVIOUS:
1772 case PHY_DELAY_MS:
1773 break;
1774
1775 case PHY_BJMPN:
1776 if (regno > index) {
1777 netif_err(tp, probe, tp->dev,
cecb5fd7 1778 "Out of range of firmware\n");
42b82dc1 1779 return;
1780 }
1781 break;
1782 case PHY_READCOUNT_EQ_SKIP:
1783 if (index + 2 >= fw_size) {
1784 netif_err(tp, probe, tp->dev,
cecb5fd7 1785 "Out of range of firmware\n");
42b82dc1 1786 return;
1787 }
1788 break;
1789 case PHY_COMP_EQ_SKIPN:
1790 case PHY_COMP_NEQ_SKIPN:
1791 case PHY_SKIPN:
1792 if (index + 1 + regno >= fw_size) {
1793 netif_err(tp, probe, tp->dev,
cecb5fd7 1794 "Out of range of firmware\n");
42b82dc1 1795 return;
1796 }
bca03d5f 1797 break;
1798
42b82dc1 1799 case PHY_READ_MAC_BYTE:
1800 case PHY_WRITE_MAC_BYTE:
1801 case PHY_WRITE_ERI_WORD:
1802 default:
1803 netif_err(tp, probe, tp->dev,
1804 "Invalid action 0x%08x\n", action);
bca03d5f 1805 return;
1806 }
1807 }
1808
42b82dc1 1809 predata = 0;
1810 count = 0;
1811
1812 for (index = 0; index < fw_size; ) {
1813 u32 action = le32_to_cpu(phytable[index]);
bca03d5f 1814 u32 data = action & 0x0000ffff;
42b82dc1 1815 u32 regno = (action & 0x0fff0000) >> 16;
1816
1817 if (!action)
1818 break;
bca03d5f 1819
1820 switch(action & 0xf0000000) {
42b82dc1 1821 case PHY_READ:
1822 predata = rtl_readphy(tp, regno);
1823 count++;
1824 index++;
1825 break;
1826 case PHY_DATA_OR:
1827 predata |= data;
1828 index++;
1829 break;
1830 case PHY_DATA_AND:
1831 predata &= data;
1832 index++;
1833 break;
1834 case PHY_BJMPN:
1835 index -= regno;
1836 break;
1837 case PHY_READ_EFUSE:
1838 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1839 index++;
1840 break;
1841 case PHY_CLEAR_READCOUNT:
1842 count = 0;
1843 index++;
1844 break;
bca03d5f 1845 case PHY_WRITE:
42b82dc1 1846 rtl_writephy(tp, regno, data);
1847 index++;
1848 break;
1849 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 1850 index += (count == data) ? 2 : 1;
bca03d5f 1851 break;
42b82dc1 1852 case PHY_COMP_EQ_SKIPN:
1853 if (predata == data)
1854 index += regno;
1855 index++;
1856 break;
1857 case PHY_COMP_NEQ_SKIPN:
1858 if (predata != data)
1859 index += regno;
1860 index++;
1861 break;
1862 case PHY_WRITE_PREVIOUS:
1863 rtl_writephy(tp, regno, predata);
1864 index++;
1865 break;
1866 case PHY_SKIPN:
1867 index += regno + 1;
1868 break;
1869 case PHY_DELAY_MS:
1870 mdelay(data);
1871 index++;
1872 break;
1873
1874 case PHY_READ_MAC_BYTE:
1875 case PHY_WRITE_MAC_BYTE:
1876 case PHY_WRITE_ERI_WORD:
bca03d5f 1877 default:
1878 BUG();
1879 }
1880 }
1881}
1882
f1e02ed1 1883static void rtl_release_firmware(struct rtl8169_private *tp)
1884{
b6ffd97f
FR		 1885 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
1886 release_firmware(tp->rtl_fw->fw);
1887 kfree(tp->rtl_fw);
1888 }
1889 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 1890}
1891
953a12cc 1892static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 1893{
b6ffd97f 1894 struct rtl_fw *rtl_fw = tp->rtl_fw;
f1e02ed1 1895
1896 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
b6ffd97f
FR		 1897 if (!IS_ERR_OR_NULL(rtl_fw))
1898 rtl_phy_write_fw(tp, rtl_fw);
953a12cc
FR		 1899}
1900
1901static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1902{
1903 if (rtl_readphy(tp, reg) != val)
1904 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1905 else
1906 rtl_apply_firmware(tp);
f1e02ed1 1907}
1908
4da19633 1909static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1910{
350f7596 1911 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1912 { 0x1f, 0x0001 },
1913 { 0x06, 0x006e },
1914 { 0x08, 0x0708 },
1915 { 0x15, 0x4000 },
1916 { 0x18, 0x65c7 },
1da177e4 1917
0b9b571d 1918 { 0x1f, 0x0001 },
1919 { 0x03, 0x00a1 },
1920 { 0x02, 0x0008 },
1921 { 0x01, 0x0120 },
1922 { 0x00, 0x1000 },
1923 { 0x04, 0x0800 },
1924 { 0x04, 0x0000 },
1da177e4 1925
0b9b571d 1926 { 0x03, 0xff41 },
1927 { 0x02, 0xdf60 },
1928 { 0x01, 0x0140 },
1929 { 0x00, 0x0077 },
1930 { 0x04, 0x7800 },
1931 { 0x04, 0x7000 },
1932
1933 { 0x03, 0x802f },
1934 { 0x02, 0x4f02 },
1935 { 0x01, 0x0409 },
1936 { 0x00, 0xf0f9 },
1937 { 0x04, 0x9800 },
1938 { 0x04, 0x9000 },
1939
1940 { 0x03, 0xdf01 },
1941 { 0x02, 0xdf20 },
1942 { 0x01, 0xff95 },
1943 { 0x00, 0xba00 },
1944 { 0x04, 0xa800 },
1945 { 0x04, 0xa000 },
1946
1947 { 0x03, 0xff41 },
1948 { 0x02, 0xdf20 },
1949 { 0x01, 0x0140 },
1950 { 0x00, 0x00bb },
1951 { 0x04, 0xb800 },
1952 { 0x04, 0xb000 },
1953
1954 { 0x03, 0xdf41 },
1955 { 0x02, 0xdc60 },
1956 { 0x01, 0x6340 },
1957 { 0x00, 0x007d },
1958 { 0x04, 0xd800 },
1959 { 0x04, 0xd000 },
1960
1961 { 0x03, 0xdf01 },
1962 { 0x02, 0xdf20 },
1963 { 0x01, 0x100a },
1964 { 0x00, 0xa0ff },
1965 { 0x04, 0xf800 },
1966 { 0x04, 0xf000 },
1967
1968 { 0x1f, 0x0000 },
1969 { 0x0b, 0x0000 },
1970 { 0x00, 0x9200 }
1971 };
1da177e4 1972
4da19633 1973 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1974}
1975
4da19633 1976static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1977{
350f7596 1978 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1979 { 0x1f, 0x0002 },
1980 { 0x01, 0x90d0 },
1981 { 0x1f, 0x0000 }
1982 };
1983
4da19633 1984 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1985}
1986
4da19633 1987static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1988{
1989 struct pci_dev *pdev = tp->pci_dev;
1990 u16 vendor_id, device_id;
1991
1992 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1993 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1994
1995 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1996 return;
1997
4da19633 1998 rtl_writephy(tp, 0x1f, 0x0001);
1999 rtl_writephy(tp, 0x10, 0xf01b);
2000 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 2001}
2002
4da19633 2003static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 2004{
350f7596 2005 static const struct phy_reg phy_reg_init[] = {
2e955856 2006 { 0x1f, 0x0001 },
2007 { 0x04, 0x0000 },
2008 { 0x03, 0x00a1 },
2009 { 0x02, 0x0008 },
2010 { 0x01, 0x0120 },
2011 { 0x00, 0x1000 },
2012 { 0x04, 0x0800 },
2013 { 0x04, 0x9000 },
2014 { 0x03, 0x802f },
2015 { 0x02, 0x4f02 },
2016 { 0x01, 0x0409 },
2017 { 0x00, 0xf099 },
2018 { 0x04, 0x9800 },
2019 { 0x04, 0xa000 },
2020 { 0x03, 0xdf01 },
2021 { 0x02, 0xdf20 },
2022 { 0x01, 0xff95 },
2023 { 0x00, 0xba00 },
2024 { 0x04, 0xa800 },
2025 { 0x04, 0xf000 },
2026 { 0x03, 0xdf01 },
2027 { 0x02, 0xdf20 },
2028 { 0x01, 0x101a },
2029 { 0x00, 0xa0ff },
2030 { 0x04, 0xf800 },
2031 { 0x04, 0x0000 },
2032 { 0x1f, 0x0000 },
2033
2034 { 0x1f, 0x0001 },
2035 { 0x10, 0xf41b },
2036 { 0x14, 0xfb54 },
2037 { 0x18, 0xf5c7 },
2038 { 0x1f, 0x0000 },
2039
2040 { 0x1f, 0x0001 },
2041 { 0x17, 0x0cc0 },
2042 { 0x1f, 0x0000 }
2043 };
2044
4da19633 2045 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2046
4da19633 2047 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2048}
2049
4da19633 2050static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2051{
350f7596 2052 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2053 { 0x1f, 0x0001 },
2054 { 0x04, 0x0000 },
2055 { 0x03, 0x00a1 },
2056 { 0x02, 0x0008 },
2057 { 0x01, 0x0120 },
2058 { 0x00, 0x1000 },
2059 { 0x04, 0x0800 },
2060 { 0x04, 0x9000 },
2061 { 0x03, 0x802f },
2062 { 0x02, 0x4f02 },
2063 { 0x01, 0x0409 },
2064 { 0x00, 0xf099 },
2065 { 0x04, 0x9800 },
2066 { 0x04, 0xa000 },
2067 { 0x03, 0xdf01 },
2068 { 0x02, 0xdf20 },
2069 { 0x01, 0xff95 },
2070 { 0x00, 0xba00 },
2071 { 0x04, 0xa800 },
2072 { 0x04, 0xf000 },
2073 { 0x03, 0xdf01 },
2074 { 0x02, 0xdf20 },
2075 { 0x01, 0x101a },
2076 { 0x00, 0xa0ff },
2077 { 0x04, 0xf800 },
2078 { 0x04, 0x0000 },
2079 { 0x1f, 0x0000 },
2080
2081 { 0x1f, 0x0001 },
2082 { 0x0b, 0x8480 },
2083 { 0x1f, 0x0000 },
2084
2085 { 0x1f, 0x0001 },
2086 { 0x18, 0x67c7 },
2087 { 0x04, 0x2000 },
2088 { 0x03, 0x002f },
2089 { 0x02, 0x4360 },
2090 { 0x01, 0x0109 },
2091 { 0x00, 0x3022 },
2092 { 0x04, 0x2800 },
2093 { 0x1f, 0x0000 },
2094
2095 { 0x1f, 0x0001 },
2096 { 0x17, 0x0cc0 },
2097 { 0x1f, 0x0000 }
2098 };
2099
4da19633 2100 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2101}
2102
4da19633 2103static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2104{
350f7596 2105 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2106 { 0x10, 0xf41b },
2107 { 0x1f, 0x0000 }
2108 };
2109
4da19633 2110 rtl_writephy(tp, 0x1f, 0x0001);
2111 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2112
4da19633 2113 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2114}
2115
4da19633 2116static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2117{
350f7596 2118 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2119 { 0x1f, 0x0001 },
2120 { 0x10, 0xf41b },
2121 { 0x1f, 0x0000 }
2122 };
2123
4da19633 2124 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2125}
2126
4da19633 2127static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2128{
350f7596 2129 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2130 { 0x1f, 0x0000 },
2131 { 0x1d, 0x0f00 },
2132 { 0x1f, 0x0002 },
2133 { 0x0c, 0x1ec8 },
2134 { 0x1f, 0x0000 }
2135 };
2136
4da19633 2137 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2138}
2139
4da19633 2140static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2141{
350f7596 2142 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2143 { 0x1f, 0x0001 },
2144 { 0x1d, 0x3d98 },
2145 { 0x1f, 0x0000 }
2146 };
2147
4da19633 2148 rtl_writephy(tp, 0x1f, 0x0000);
2149 rtl_patchphy(tp, 0x14, 1 << 5);
2150 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2151
4da19633 2152 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2153}
2154
4da19633 2155static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2156{
350f7596 2157 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2158 { 0x1f, 0x0001 },
2159 { 0x12, 0x2300 },
867763c1
FR		 2160 { 0x1f, 0x0002 },
2161 { 0x00, 0x88d4 },
2162 { 0x01, 0x82b1 },
2163 { 0x03, 0x7002 },
2164 { 0x08, 0x9e30 },
2165 { 0x09, 0x01f0 },
2166 { 0x0a, 0x5500 },
2167 { 0x0c, 0x00c8 },
2168 { 0x1f, 0x0003 },
2169 { 0x12, 0xc096 },
2170 { 0x16, 0x000a },
f50d4275
FR		 2171 { 0x1f, 0x0000 },
2172 { 0x1f, 0x0000 },
2173 { 0x09, 0x2000 },
2174 { 0x09, 0x0000 }
867763c1
FR		 2175 };
2176
4da19633 2177 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2178
4da19633 2179 rtl_patchphy(tp, 0x14, 1 << 5);
2180 rtl_patchphy(tp, 0x0d, 1 << 5);
2181 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2182}
2183
4da19633 2184static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2185{
350f7596 2186 static const struct phy_reg phy_reg_init[] = {
f50d4275 2187 { 0x1f, 0x0001 },
7da97ec9 2188 { 0x12, 0x2300 },
f50d4275
FR		 2189 { 0x03, 0x802f },
2190 { 0x02, 0x4f02 },
2191 { 0x01, 0x0409 },
2192 { 0x00, 0xf099 },
2193 { 0x04, 0x9800 },
2194 { 0x04, 0x9000 },
2195 { 0x1d, 0x3d98 },
7da97ec9
FR		 2196 { 0x1f, 0x0002 },
2197 { 0x0c, 0x7eb8 },
f50d4275
FR		 2198 { 0x06, 0x0761 },
2199 { 0x1f, 0x0003 },
2200 { 0x16, 0x0f0a },
7da97ec9
FR		 2201 { 0x1f, 0x0000 }
2202 };
2203
4da19633 2204 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2205
4da19633 2206 rtl_patchphy(tp, 0x16, 1 << 0);
2207 rtl_patchphy(tp, 0x14, 1 << 5);
2208 rtl_patchphy(tp, 0x0d, 1 << 5);
2209 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2210}
2211
4da19633 2212static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2213{
350f7596 2214 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2215 { 0x1f, 0x0001 },
2216 { 0x12, 0x2300 },
2217 { 0x1d, 0x3d98 },
2218 { 0x1f, 0x0002 },
2219 { 0x0c, 0x7eb8 },
2220 { 0x06, 0x5461 },
2221 { 0x1f, 0x0003 },
2222 { 0x16, 0x0f0a },
2223 { 0x1f, 0x0000 }
2224 };
2225
4da19633 2226 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2227
4da19633 2228 rtl_patchphy(tp, 0x16, 1 << 0);
2229 rtl_patchphy(tp, 0x14, 1 << 5);
2230 rtl_patchphy(tp, 0x0d, 1 << 5);
2231 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2232}
2233
4da19633 2234static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2235{
4da19633 2236 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2237}
2238
bca03d5f 2239static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2240{
350f7596 2241 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2242 /* Channel Estimation */
5b538df9 2243 { 0x1f, 0x0001 },
daf9df6d 2244 { 0x06, 0x4064 },
2245 { 0x07, 0x2863 },
2246 { 0x08, 0x059c },
2247 { 0x09, 0x26b4 },
2248 { 0x0a, 0x6a19 },
2249 { 0x0b, 0xdcc8 },
2250 { 0x10, 0xf06d },
2251 { 0x14, 0x7f68 },
2252 { 0x18, 0x7fd9 },
2253 { 0x1c, 0xf0ff },
2254 { 0x1d, 0x3d9c },
5b538df9 2255 { 0x1f, 0x0003 },
daf9df6d 2256 { 0x12, 0xf49f },
2257 { 0x13, 0x070b },
2258 { 0x1a, 0x05ad },
bca03d5f 2259 { 0x14, 0x94c0 },
2260
2261 /*
2262 * Tx Error Issue
cecb5fd7 2263 * Enhance line driver power
bca03d5f 2264 */
5b538df9 2265 { 0x1f, 0x0002 },
daf9df6d 2266 { 0x06, 0x5561 },
2267 { 0x1f, 0x0005 },
2268 { 0x05, 0x8332 },
bca03d5f 2269 { 0x06, 0x5561 },
2270
2271 /*
2272 * Can not link to 1Gbps with bad cable
2273 * Decrease SNR threshold form 21.07dB to 19.04dB
2274 */
2275 { 0x1f, 0x0001 },
2276 { 0x17, 0x0cc0 },
daf9df6d 2277
5b538df9 2278 { 0x1f, 0x0000 },
bca03d5f 2279 { 0x0d, 0xf880 }
daf9df6d 2280 };
bca03d5f 2281 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2282
4da19633 2283 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2284
bca03d5f 2285 /*
2286 * Rx Error Issue
2287 * Fine Tune Switching regulator parameter
2288 */
4da19633 2289 rtl_writephy(tp, 0x1f, 0x0002);
2290 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2291 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2292
daf9df6d 2293 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2294 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2295 { 0x1f, 0x0002 },
2296 { 0x05, 0x669a },
2297 { 0x1f, 0x0005 },
2298 { 0x05, 0x8330 },
2299 { 0x06, 0x669a },
2300 { 0x1f, 0x0002 }
2301 };
2302 int val;
2303
4da19633 2304 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2305
4da19633 2306 val = rtl_readphy(tp, 0x0d);
daf9df6d 2307
2308 if ((val & 0x00ff) != 0x006c) {
350f7596 2309 static const u32 set[] = {
daf9df6d 2310 0x0065, 0x0066, 0x0067, 0x0068,
2311 0x0069, 0x006a, 0x006b, 0x006c
2312 };
2313 int i;
2314
4da19633 2315 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2316
2317 val &= 0xff00;
2318 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2319 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2320 }
2321 } else {
350f7596 2322 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2323 { 0x1f, 0x0002 },
2324 { 0x05, 0x6662 },
2325 { 0x1f, 0x0005 },
2326 { 0x05, 0x8330 },
2327 { 0x06, 0x6662 }
2328 };
2329
4da19633 2330 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2331 }
2332
bca03d5f 2333 /* RSET couple improve */
4da19633 2334 rtl_writephy(tp, 0x1f, 0x0002);
2335 rtl_patchphy(tp, 0x0d, 0x0300);
2336 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2337
bca03d5f 2338 /* Fine tune PLL performance */
4da19633 2339 rtl_writephy(tp, 0x1f, 0x0002);
2340 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2341 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2342
4da19633 2343 rtl_writephy(tp, 0x1f, 0x0005);
2344 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2345
2346 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2347
4da19633 2348 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2349}
2350
bca03d5f 2351static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2352{
350f7596 2353 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2354 /* Channel Estimation */
daf9df6d 2355 { 0x1f, 0x0001 },
2356 { 0x06, 0x4064 },
2357 { 0x07, 0x2863 },
2358 { 0x08, 0x059c },
2359 { 0x09, 0x26b4 },
2360 { 0x0a, 0x6a19 },
2361 { 0x0b, 0xdcc8 },
2362 { 0x10, 0xf06d },
2363 { 0x14, 0x7f68 },
2364 { 0x18, 0x7fd9 },
2365 { 0x1c, 0xf0ff },
2366 { 0x1d, 0x3d9c },
2367 { 0x1f, 0x0003 },
2368 { 0x12, 0xf49f },
2369 { 0x13, 0x070b },
2370 { 0x1a, 0x05ad },
2371 { 0x14, 0x94c0 },
2372
bca03d5f 2373 /*
2374 * Tx Error Issue
cecb5fd7 2375 * Enhance line driver power
bca03d5f 2376 */
daf9df6d 2377 { 0x1f, 0x0002 },
2378 { 0x06, 0x5561 },
2379 { 0x1f, 0x0005 },
2380 { 0x05, 0x8332 },
bca03d5f 2381 { 0x06, 0x5561 },
2382
2383 /*
2384 * Can not link to 1Gbps with bad cable
2385 * Decrease SNR threshold form 21.07dB to 19.04dB
2386 */
2387 { 0x1f, 0x0001 },
2388 { 0x17, 0x0cc0 },
daf9df6d 2389
2390 { 0x1f, 0x0000 },
bca03d5f 2391 { 0x0d, 0xf880 }
5b538df9 2392 };
bca03d5f 2393 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2394
4da19633 2395 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2396
daf9df6d 2397 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2398 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2399 { 0x1f, 0x0002 },
2400 { 0x05, 0x669a },
5b538df9 2401 { 0x1f, 0x0005 },
daf9df6d 2402 { 0x05, 0x8330 },
2403 { 0x06, 0x669a },
2404
2405 { 0x1f, 0x0002 }
2406 };
2407 int val;
2408
4da19633 2409 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2410
4da19633 2411 val = rtl_readphy(tp, 0x0d);
daf9df6d 2412 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2413 static const u32 set[] = {
daf9df6d 2414 0x0065, 0x0066, 0x0067, 0x0068,
2415 0x0069, 0x006a, 0x006b, 0x006c
2416 };
2417 int i;
2418
4da19633 2419 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2420
2421 val &= 0xff00;
2422 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2423 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2424 }
2425 } else {
350f7596 2426 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2427 { 0x1f, 0x0002 },
2428 { 0x05, 0x2642 },
5b538df9 2429 { 0x1f, 0x0005 },
daf9df6d 2430 { 0x05, 0x8330 },
2431 { 0x06, 0x2642 }
5b538df9
FR		 2432 };
2433
4da19633 2434 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2435 }
2436
bca03d5f 2437 /* Fine tune PLL performance */
4da19633 2438 rtl_writephy(tp, 0x1f, 0x0002);
2439 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2440 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2441
bca03d5f 2442 /* Switching regulator Slew rate */
4da19633 2443 rtl_writephy(tp, 0x1f, 0x0002);
2444 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2445
4da19633 2446 rtl_writephy(tp, 0x1f, 0x0005);
2447 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2448
2449 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2450
4da19633 2451 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2452}
2453
4da19633 2454static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2455{
350f7596 2456 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2457 { 0x1f, 0x0002 },
2458 { 0x10, 0x0008 },
2459 { 0x0d, 0x006c },
2460
2461 { 0x1f, 0x0000 },
2462 { 0x0d, 0xf880 },
2463
2464 { 0x1f, 0x0001 },
2465 { 0x17, 0x0cc0 },
2466
2467 { 0x1f, 0x0001 },
2468 { 0x0b, 0xa4d8 },
2469 { 0x09, 0x281c },
2470 { 0x07, 0x2883 },
2471 { 0x0a, 0x6b35 },
2472 { 0x1d, 0x3da4 },
2473 { 0x1c, 0xeffd },
2474 { 0x14, 0x7f52 },
2475 { 0x18, 0x7fc6 },
2476 { 0x08, 0x0601 },
2477 { 0x06, 0x4063 },
2478 { 0x10, 0xf074 },
2479 { 0x1f, 0x0003 },
2480 { 0x13, 0x0789 },
2481 { 0x12, 0xf4bd },
2482 { 0x1a, 0x04fd },
2483 { 0x14, 0x84b0 },
2484 { 0x1f, 0x0000 },
2485 { 0x00, 0x9200 },
2486
2487 { 0x1f, 0x0005 },
2488 { 0x01, 0x0340 },
2489 { 0x1f, 0x0001 },
2490 { 0x04, 0x4000 },
2491 { 0x03, 0x1d21 },
2492 { 0x02, 0x0c32 },
2493 { 0x01, 0x0200 },
2494 { 0x00, 0x5554 },
2495 { 0x04, 0x4800 },
2496 { 0x04, 0x4000 },
2497 { 0x04, 0xf000 },
2498 { 0x03, 0xdf01 },
2499 { 0x02, 0xdf20 },
2500 { 0x01, 0x101a },
2501 { 0x00, 0xa0ff },
2502 { 0x04, 0xf800 },
2503 { 0x04, 0xf000 },
2504 { 0x1f, 0x0000 },
2505
2506 { 0x1f, 0x0007 },
2507 { 0x1e, 0x0023 },
2508 { 0x16, 0x0000 },
2509 { 0x1f, 0x0000 }
2510 };
2511
4da19633 2512 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2513}
2514
e6de30d6 2515static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2516{
2517 static const struct phy_reg phy_reg_init[] = {
2518 { 0x1f, 0x0001 },
2519 { 0x17, 0x0cc0 },
2520
2521 { 0x1f, 0x0007 },
2522 { 0x1e, 0x002d },
2523 { 0x18, 0x0040 },
2524 { 0x1f, 0x0000 }
2525 };
2526
2527 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2528 rtl_patchphy(tp, 0x0d, 1 << 5);
2529}
2530
01dc7fec 2531static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2532{
2533 static const struct phy_reg phy_reg_init[] = {
2534 /* Enable Delay cap */
2535 { 0x1f, 0x0005 },
2536 { 0x05, 0x8b80 },
2537 { 0x06, 0xc896 },
2538 { 0x1f, 0x0000 },
2539
2540 /* Channel estimation fine tune */
2541 { 0x1f, 0x0001 },
2542 { 0x0b, 0x6c20 },
2543 { 0x07, 0x2872 },
2544 { 0x1c, 0xefff },
2545 { 0x1f, 0x0003 },
2546 { 0x14, 0x6420 },
2547 { 0x1f, 0x0000 },
2548
2549 /* Update PFM & 10M TX idle timer */
2550 { 0x1f, 0x0007 },
2551 { 0x1e, 0x002f },
2552 { 0x15, 0x1919 },
2553 { 0x1f, 0x0000 },
2554
2555 { 0x1f, 0x0007 },
2556 { 0x1e, 0x00ac },
2557 { 0x18, 0x0006 },
2558 { 0x1f, 0x0000 }
2559 };
2560
15ecd039
FR		 2561 rtl_apply_firmware(tp);
2562
01dc7fec 2563 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2564
2565 /* DCO enable for 10M IDLE Power */
2566 rtl_writephy(tp, 0x1f, 0x0007);
2567 rtl_writephy(tp, 0x1e, 0x0023);
2568 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2569 rtl_writephy(tp, 0x1f, 0x0000);
2570
2571 /* For impedance matching */
2572 rtl_writephy(tp, 0x1f, 0x0002);
2573 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2574 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2575
2576 /* PHY auto speed down */
2577 rtl_writephy(tp, 0x1f, 0x0007);
2578 rtl_writephy(tp, 0x1e, 0x002d);
2579 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2580 rtl_writephy(tp, 0x1f, 0x0000);
2581 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2582
2583 rtl_writephy(tp, 0x1f, 0x0005);
2584 rtl_writephy(tp, 0x05, 0x8b86);
2585 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2586 rtl_writephy(tp, 0x1f, 0x0000);
2587
2588 rtl_writephy(tp, 0x1f, 0x0005);
2589 rtl_writephy(tp, 0x05, 0x8b85);
2590 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2591 rtl_writephy(tp, 0x1f, 0x0007);
2592 rtl_writephy(tp, 0x1e, 0x0020);
2593 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2594 rtl_writephy(tp, 0x1f, 0x0006);
2595 rtl_writephy(tp, 0x00, 0x5a00);
2596 rtl_writephy(tp, 0x1f, 0x0000);
2597 rtl_writephy(tp, 0x0d, 0x0007);
2598 rtl_writephy(tp, 0x0e, 0x003c);
2599 rtl_writephy(tp, 0x0d, 0x4007);
2600 rtl_writephy(tp, 0x0e, 0x0000);
2601 rtl_writephy(tp, 0x0d, 0x0000);
2602}
2603
4da19633 2604static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2605{
350f7596 2606 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2607 { 0x1f, 0x0003 },
2608 { 0x08, 0x441d },
2609 { 0x01, 0x9100 },
2610 { 0x1f, 0x0000 }
2611 };
2612
4da19633 2613 rtl_writephy(tp, 0x1f, 0x0000);
2614 rtl_patchphy(tp, 0x11, 1 << 12);
2615 rtl_patchphy(tp, 0x19, 1 << 13);
2616 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2617
4da19633 2618 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2619}
2620
5a5e4443
HW		 2621static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2622{
2623 static const struct phy_reg phy_reg_init[] = {
2624 { 0x1f, 0x0005 },
2625 { 0x1a, 0x0000 },
2626 { 0x1f, 0x0000 },
2627
2628 { 0x1f, 0x0004 },
2629 { 0x1c, 0x0000 },
2630 { 0x1f, 0x0000 },
2631
2632 { 0x1f, 0x0001 },
2633 { 0x15, 0x7701 },
2634 { 0x1f, 0x0000 }
2635 };
2636
2637 /* Disable ALDPS before ram code */
2638 rtl_writephy(tp, 0x1f, 0x0000);
2639 rtl_writephy(tp, 0x18, 0x0310);
2640 msleep(100);
2641
953a12cc 2642 rtl_apply_firmware(tp);
5a5e4443
HW		 2643
2644 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2645}
2646
5615d9f1
FR		 2647static void rtl_hw_phy_config(struct net_device *dev)
2648{
2649 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2650
2651 rtl8169_print_mac_version(tp);
2652
2653 switch (tp->mac_version) {
2654 case RTL_GIGA_MAC_VER_01:
2655 break;
2656 case RTL_GIGA_MAC_VER_02:
2657 case RTL_GIGA_MAC_VER_03:
4da19633 2658 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2659 break;
2660 case RTL_GIGA_MAC_VER_04:
4da19633 2661 rtl8169sb_hw_phy_config(tp);
5615d9f1 2662 break;
2e955856 2663 case RTL_GIGA_MAC_VER_05:
4da19633 2664 rtl8169scd_hw_phy_config(tp);
2e955856 2665 break;
8c7006aa 2666 case RTL_GIGA_MAC_VER_06:
4da19633 2667 rtl8169sce_hw_phy_config(tp);
8c7006aa 2668 break;
2857ffb7
FR		 2669 case RTL_GIGA_MAC_VER_07:
2670 case RTL_GIGA_MAC_VER_08:
2671 case RTL_GIGA_MAC_VER_09:
4da19633 2672 rtl8102e_hw_phy_config(tp);
2857ffb7 2673 break;
236b8082 2674 case RTL_GIGA_MAC_VER_11:
4da19633 2675 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2676 break;
2677 case RTL_GIGA_MAC_VER_12:
4da19633 2678 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2679 break;
2680 case RTL_GIGA_MAC_VER_17:
4da19633 2681 rtl8168bef_hw_phy_config(tp);
236b8082 2682 break;
867763c1 2683 case RTL_GIGA_MAC_VER_18:
4da19633 2684 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2685 break;
2686 case RTL_GIGA_MAC_VER_19:
4da19633 2687 rtl8168c_1_hw_phy_config(tp);
867763c1 2688 break;
7da97ec9 2689 case RTL_GIGA_MAC_VER_20:
4da19633 2690 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2691 break;
197ff761 2692 case RTL_GIGA_MAC_VER_21:
4da19633 2693 rtl8168c_3_hw_phy_config(tp);
197ff761 2694 break;
6fb07058 2695 case RTL_GIGA_MAC_VER_22:
4da19633 2696 rtl8168c_4_hw_phy_config(tp);
6fb07058 2697 break;
ef3386f0 2698 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2699 case RTL_GIGA_MAC_VER_24:
4da19633 2700 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2701 break;
5b538df9 2702 case RTL_GIGA_MAC_VER_25:
bca03d5f 2703 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2704 break;
2705 case RTL_GIGA_MAC_VER_26:
bca03d5f 2706 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2707 break;
2708 case RTL_GIGA_MAC_VER_27:
4da19633 2709 rtl8168d_3_hw_phy_config(tp);
5b538df9 2710 break;
e6de30d6 2711 case RTL_GIGA_MAC_VER_28:
2712 rtl8168d_4_hw_phy_config(tp);
2713 break;
5a5e4443
HW		 2714 case RTL_GIGA_MAC_VER_29:
2715 case RTL_GIGA_MAC_VER_30:
2716 rtl8105e_hw_phy_config(tp);
2717 break;
cecb5fd7
FR		 2718 case RTL_GIGA_MAC_VER_31:
2719 /* None. */
2720 break;
01dc7fec 2721 case RTL_GIGA_MAC_VER_32:
01dc7fec 2722 case RTL_GIGA_MAC_VER_33:
15ecd039 2723 rtl8168e_hw_phy_config(tp);
01dc7fec 2724 break;
ef3386f0 2725
5615d9f1
FR		 2726 default:
2727 break;
2728 }
2729}
2730
1da177e4
LT		 2731static void rtl8169_phy_timer(unsigned long __opaque)
2732{
2733 struct net_device *dev = (struct net_device *)__opaque;
2734 struct rtl8169_private *tp = netdev_priv(dev);
2735 struct timer_list *timer = &tp->timer;
2736 void __iomem *ioaddr = tp->mmio_addr;
2737 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2738
bcf0bf90 2739 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2740
1da177e4
LT		 2741 spin_lock_irq(&tp->lock);
2742
4da19633 2743 if (tp->phy_reset_pending(tp)) {
5b0384f4 2744 /*
1da177e4
LT		 2745 * A busy loop could burn quite a few cycles on nowadays CPU.
2746 * Let's delay the execution of the timer for a few ticks.
2747 */
2748 timeout = HZ/10;
2749 goto out_mod_timer;
2750 }
2751
2752 if (tp->link_ok(ioaddr))
2753 goto out_unlock;
2754
bf82c189 2755 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2756
4da19633 2757 tp->phy_reset_enable(tp);
1da177e4
LT		 2758
2759out_mod_timer:
2760 mod_timer(timer, jiffies + timeout);
2761out_unlock:
2762 spin_unlock_irq(&tp->lock);
2763}
2764
1da177e4
LT		 2765#ifdef CONFIG_NET_POLL_CONTROLLER
2766/*
2767 * Polling 'interrupt' - used by things like netconsole to send skbs
2768 * without having to re-enable interrupts. It's not called while
2769 * the interrupt routine is executing.
2770 */
2771static void rtl8169_netpoll(struct net_device *dev)
2772{
2773 struct rtl8169_private *tp = netdev_priv(dev);
2774 struct pci_dev *pdev = tp->pci_dev;
2775
2776 disable_irq(pdev->irq);
7d12e780 2777 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2778 enable_irq(pdev->irq);
2779}
2780#endif
2781
2782static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2783 void __iomem *ioaddr)
2784{
2785 iounmap(ioaddr);
2786 pci_release_regions(pdev);
87aeec76 2787 pci_clear_mwi(pdev);
1da177e4
LT		 2788 pci_disable_device(pdev);
2789 free_netdev(dev);
2790}
2791
bf793295
FR		 2792static void rtl8169_phy_reset(struct net_device *dev,
2793 struct rtl8169_private *tp)
2794{
07d3f51f 2795 unsigned int i;
bf793295 2796
4da19633 2797 tp->phy_reset_enable(tp);
bf793295 2798 for (i = 0; i < 100; i++) {
4da19633 2799 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2800 return;
2801 msleep(1);
2802 }
bf82c189 2803 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2804}
2805
4ff96fa6
FR		 2806static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2807{
2808 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2809
5615d9f1 2810 rtl_hw_phy_config(dev);
4ff96fa6 2811
77332894
MS		 2812 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2813 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2814 RTL_W8(0x82, 0x01);
2815 }
4ff96fa6 2816
6dccd16b
FR		 2817 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2818
2819 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2820 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2821
bcf0bf90 2822 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2823 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2824 RTL_W8(0x82, 0x01);
2825 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2826 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2827 }
2828
bf793295
FR		 2829 rtl8169_phy_reset(dev, tp);
2830
54405cde 2831 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 2832 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2833 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2834 (tp->mii.supports_gmii ?
2835 ADVERTISED_1000baseT_Half |
2836 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 2837
bf82c189
JP		 2838 if (RTL_R8(PHYstatus) & TBI_Enable)
2839 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2840}
2841
773d2021
FR		 2842static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2843{
2844 void __iomem *ioaddr = tp->mmio_addr;
2845 u32 high;
2846 u32 low;
2847
2848 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2849 high = addr[4] | (addr[5] << 8);
2850
2851 spin_lock_irq(&tp->lock);
2852
2853 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2854
773d2021 2855 RTL_W32(MAC4, high);
908ba2bf 2856 RTL_R32(MAC4);
2857
78f1cd02 2858 RTL_W32(MAC0, low);
908ba2bf 2859 RTL_R32(MAC0);
2860
773d2021
FR		 2861 RTL_W8(Cfg9346, Cfg9346_Lock);
2862
2863 spin_unlock_irq(&tp->lock);
2864}
2865
2866static int rtl_set_mac_address(struct net_device *dev, void *p)
2867{
2868 struct rtl8169_private *tp = netdev_priv(dev);
2869 struct sockaddr *addr = p;
2870
2871 if (!is_valid_ether_addr(addr->sa_data))
2872 return -EADDRNOTAVAIL;
2873
2874 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2875
2876 rtl_rar_set(tp, dev->dev_addr);
2877
2878 return 0;
2879}
2880
5f787a1a
FR		 2881static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2882{
2883 struct rtl8169_private *tp = netdev_priv(dev);
2884 struct mii_ioctl_data *data = if_mii(ifr);
2885
8b4ab28d
FR		 2886 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2887}
5f787a1a 2888
cecb5fd7
FR		 2889static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2890 struct mii_ioctl_data *data, int cmd)
8b4ab28d 2891{
5f787a1a
FR		 2892 switch (cmd) {
2893 case SIOCGMIIPHY:
2894 data->phy_id = 32; /* Internal PHY */
2895 return 0;
2896
2897 case SIOCGMIIREG:
4da19633 2898 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2899 return 0;
2900
2901 case SIOCSMIIREG:
4da19633 2902 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2903 return 0;
2904 }
2905 return -EOPNOTSUPP;
2906}
2907
8b4ab28d
FR		 2908static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2909{
2910 return -EOPNOTSUPP;
2911}
2912
0e485150
FR		 2913static const struct rtl_cfg_info {
2914 void (*hw_start)(struct net_device *);
2915 unsigned int region;
2916 unsigned int align;
2917 u16 intr_event;
2918 u16 napi_event;
ccdffb9a 2919 unsigned features;
f21b75e9 2920 u8 default_ver;
0e485150
FR		 2921} rtl_cfg_infos [] = {
2922 [RTL_CFG_0] = {
2923 .hw_start = rtl_hw_start_8169,
2924 .region = 1,
e9f63f30 2925 .align = 0,
0e485150
FR		 2926 .intr_event = SYSErr | LinkChg | RxOverflow |
2927 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2928 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2929 .features = RTL_FEATURE_GMII,
2930 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2931 },
2932 [RTL_CFG_1] = {
2933 .hw_start = rtl_hw_start_8168,
2934 .region = 2,
2935 .align = 8,
53f57357 2936 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2937 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2938 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2939 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2940 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2941 },
2942 [RTL_CFG_2] = {
2943 .hw_start = rtl_hw_start_8101,
2944 .region = 2,
2945 .align = 8,
2946 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2947 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2948 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2949 .features = RTL_FEATURE_MSI,
2950 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2951 }
2952};
2953
fbac58fc
FR		 2954/* Cfg9346_Unlock assumed. */
2955static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2956 const struct rtl_cfg_info *cfg)
2957{
2958 unsigned msi = 0;
2959 u8 cfg2;
2960
2961 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2962 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2963 if (pci_enable_msi(pdev)) {
2964 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2965 } else {
2966 cfg2 |= MSIEnable;
2967 msi = RTL_FEATURE_MSI;
2968 }
2969 }
2970 RTL_W8(Config2, cfg2);
2971 return msi;
2972}
2973
2974static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2975{
2976 if (tp->features & RTL_FEATURE_MSI) {
2977 pci_disable_msi(pdev);
2978 tp->features &= ~RTL_FEATURE_MSI;
2979 }
2980}
2981
8b4ab28d
FR		 2982static const struct net_device_ops rtl8169_netdev_ops = {
2983 .ndo_open = rtl8169_open,
2984 .ndo_stop = rtl8169_close,
2985 .ndo_get_stats = rtl8169_get_stats,
00829823 2986 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2987 .ndo_tx_timeout = rtl8169_tx_timeout,
2988 .ndo_validate_addr = eth_validate_addr,
2989 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 2990 .ndo_fix_features = rtl8169_fix_features,
2991 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 2992 .ndo_set_mac_address = rtl_set_mac_address,
2993 .ndo_do_ioctl = rtl8169_ioctl,
2994 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 2995#ifdef CONFIG_NET_POLL_CONTROLLER
2996 .ndo_poll_controller = rtl8169_netpoll,
2997#endif
2998
2999};
3000
c0e45c1c 3001static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3002{
3003 struct mdio_ops *ops = &tp->mdio_ops;
3004
3005 switch (tp->mac_version) {
3006 case RTL_GIGA_MAC_VER_27:
3007 ops->write = r8168dp_1_mdio_write;
3008 ops->read = r8168dp_1_mdio_read;
3009 break;
e6de30d6 3010 case RTL_GIGA_MAC_VER_28:
4804b3b3 3011 case RTL_GIGA_MAC_VER_31:
e6de30d6 3012 ops->write = r8168dp_2_mdio_write;
3013 ops->read = r8168dp_2_mdio_read;
3014 break;
c0e45c1c 3015 default:
3016 ops->write = r8169_mdio_write;
3017 ops->read = r8169_mdio_read;
3018 break;
3019 }
3020}
3021
065c27c1 3022static void r810x_phy_power_down(struct rtl8169_private *tp)
3023{
3024 rtl_writephy(tp, 0x1f, 0x0000);
3025 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3026}
3027
3028static void r810x_phy_power_up(struct rtl8169_private *tp)
3029{
3030 rtl_writephy(tp, 0x1f, 0x0000);
3031 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3032}
3033
3034static void r810x_pll_power_down(struct rtl8169_private *tp)
3035{
3036 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3037 rtl_writephy(tp, 0x1f, 0x0000);
3038 rtl_writephy(tp, MII_BMCR, 0x0000);
3039 return;
3040 }
3041
3042 r810x_phy_power_down(tp);
3043}
3044
3045static void r810x_pll_power_up(struct rtl8169_private *tp)
3046{
3047 r810x_phy_power_up(tp);
3048}
3049
3050static void r8168_phy_power_up(struct rtl8169_private *tp)
3051{
3052 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3053 switch (tp->mac_version) {
3054 case RTL_GIGA_MAC_VER_11:
3055 case RTL_GIGA_MAC_VER_12:
3056 case RTL_GIGA_MAC_VER_17:
3057 case RTL_GIGA_MAC_VER_18:
3058 case RTL_GIGA_MAC_VER_19:
3059 case RTL_GIGA_MAC_VER_20:
3060 case RTL_GIGA_MAC_VER_21:
3061 case RTL_GIGA_MAC_VER_22:
3062 case RTL_GIGA_MAC_VER_23:
3063 case RTL_GIGA_MAC_VER_24:
3064 case RTL_GIGA_MAC_VER_25:
3065 case RTL_GIGA_MAC_VER_26:
3066 case RTL_GIGA_MAC_VER_27:
3067 case RTL_GIGA_MAC_VER_28:
3068 case RTL_GIGA_MAC_VER_31:
3069 rtl_writephy(tp, 0x0e, 0x0000);
3070 break;
3071 default:
3072 break;
3073 }
065c27c1 3074 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3075}
3076
3077static void r8168_phy_power_down(struct rtl8169_private *tp)
3078{
3079 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3080 switch (tp->mac_version) {
3081 case RTL_GIGA_MAC_VER_32:
3082 case RTL_GIGA_MAC_VER_33:
3083 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3084 break;
3085
3086 case RTL_GIGA_MAC_VER_11:
3087 case RTL_GIGA_MAC_VER_12:
3088 case RTL_GIGA_MAC_VER_17:
3089 case RTL_GIGA_MAC_VER_18:
3090 case RTL_GIGA_MAC_VER_19:
3091 case RTL_GIGA_MAC_VER_20:
3092 case RTL_GIGA_MAC_VER_21:
3093 case RTL_GIGA_MAC_VER_22:
3094 case RTL_GIGA_MAC_VER_23:
3095 case RTL_GIGA_MAC_VER_24:
3096 case RTL_GIGA_MAC_VER_25:
3097 case RTL_GIGA_MAC_VER_26:
3098 case RTL_GIGA_MAC_VER_27:
3099 case RTL_GIGA_MAC_VER_28:
3100 case RTL_GIGA_MAC_VER_31:
3101 rtl_writephy(tp, 0x0e, 0x0200);
3102 default:
3103 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3104 break;
3105 }
065c27c1 3106}
3107
3108static void r8168_pll_power_down(struct rtl8169_private *tp)
3109{
3110 void __iomem *ioaddr = tp->mmio_addr;
3111
cecb5fd7
FR		 3112 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3113 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3114 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3115 r8168dp_check_dash(tp)) {
065c27c1 3116 return;
5d2e1957 3117 }
065c27c1 3118
cecb5fd7
FR		 3119 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3120 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3121 (RTL_R16(CPlusCmd) & ASF)) {
3122 return;
3123 }
3124
01dc7fec 3125 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3126 tp->mac_version == RTL_GIGA_MAC_VER_33)
3127 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3128
065c27c1 3129 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3130 rtl_writephy(tp, 0x1f, 0x0000);
3131 rtl_writephy(tp, MII_BMCR, 0x0000);
3132
3133 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3134 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3135 return;
3136 }
3137
3138 r8168_phy_power_down(tp);
3139
3140 switch (tp->mac_version) {
3141 case RTL_GIGA_MAC_VER_25:
3142 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3143 case RTL_GIGA_MAC_VER_27:
3144 case RTL_GIGA_MAC_VER_28:
4804b3b3 3145 case RTL_GIGA_MAC_VER_31:
01dc7fec 3146 case RTL_GIGA_MAC_VER_32:
3147 case RTL_GIGA_MAC_VER_33:
065c27c1 3148 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3149 break;
3150 }
3151}
3152
3153static void r8168_pll_power_up(struct rtl8169_private *tp)
3154{
3155 void __iomem *ioaddr = tp->mmio_addr;
3156
cecb5fd7
FR		 3157 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3158 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3159 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3160 r8168dp_check_dash(tp)) {
065c27c1 3161 return;
5d2e1957 3162 }
065c27c1 3163
3164 switch (tp->mac_version) {
3165 case RTL_GIGA_MAC_VER_25:
3166 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3167 case RTL_GIGA_MAC_VER_27:
3168 case RTL_GIGA_MAC_VER_28:
4804b3b3 3169 case RTL_GIGA_MAC_VER_31:
01dc7fec 3170 case RTL_GIGA_MAC_VER_32:
3171 case RTL_GIGA_MAC_VER_33:
065c27c1 3172 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3173 break;
3174 }
3175
3176 r8168_phy_power_up(tp);
3177}
3178
3179static void rtl_pll_power_op(struct rtl8169_private *tp,
3180 void (*op)(struct rtl8169_private *))
3181{
3182 if (op)
3183 op(tp);
3184}
3185
3186static void rtl_pll_power_down(struct rtl8169_private *tp)
3187{
3188 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3189}
3190
3191static void rtl_pll_power_up(struct rtl8169_private *tp)
3192{
3193 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3194}
3195
3196static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3197{
3198 struct pll_power_ops *ops = &tp->pll_power_ops;
3199
3200 switch (tp->mac_version) {
3201 case RTL_GIGA_MAC_VER_07:
3202 case RTL_GIGA_MAC_VER_08:
3203 case RTL_GIGA_MAC_VER_09:
3204 case RTL_GIGA_MAC_VER_10:
3205 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3206 case RTL_GIGA_MAC_VER_29:
3207 case RTL_GIGA_MAC_VER_30:
065c27c1 3208 ops->down = r810x_pll_power_down;
3209 ops->up = r810x_pll_power_up;
3210 break;
3211
3212 case RTL_GIGA_MAC_VER_11:
3213 case RTL_GIGA_MAC_VER_12:
3214 case RTL_GIGA_MAC_VER_17:
3215 case RTL_GIGA_MAC_VER_18:
3216 case RTL_GIGA_MAC_VER_19:
3217 case RTL_GIGA_MAC_VER_20:
3218 case RTL_GIGA_MAC_VER_21:
3219 case RTL_GIGA_MAC_VER_22:
3220 case RTL_GIGA_MAC_VER_23:
3221 case RTL_GIGA_MAC_VER_24:
3222 case RTL_GIGA_MAC_VER_25:
3223 case RTL_GIGA_MAC_VER_26:
3224 case RTL_GIGA_MAC_VER_27:
e6de30d6 3225 case RTL_GIGA_MAC_VER_28:
4804b3b3 3226 case RTL_GIGA_MAC_VER_31:
01dc7fec 3227 case RTL_GIGA_MAC_VER_32:
3228 case RTL_GIGA_MAC_VER_33:
065c27c1 3229 ops->down = r8168_pll_power_down;
3230 ops->up = r8168_pll_power_up;
3231 break;
3232
3233 default:
3234 ops->down = NULL;
3235 ops->up = NULL;
3236 break;
3237 }
3238}
3239
6f43adc8
FR		 3240static void rtl_hw_reset(struct rtl8169_private *tp)
3241{
3242 void __iomem *ioaddr = tp->mmio_addr;
3243 int i;
3244
3245 /* Soft reset the chip. */
3246 RTL_W8(ChipCmd, CmdReset);
3247
3248 /* Check that the chip has finished the reset. */
3249 for (i = 0; i < 100; i++) {
3250 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3251 break;
3252 msleep_interruptible(1);
3253 }
3254}
3255
1da177e4 3256static int __devinit
4ff96fa6 3257rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3258{
0e485150
FR		 3259 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3260 const unsigned int region = cfg->region;
1da177e4 3261 struct rtl8169_private *tp;
ccdffb9a 3262 struct mii_if_info *mii;
4ff96fa6
FR		 3263 struct net_device *dev;
3264 void __iomem *ioaddr;
2b7b4318 3265 int chipset, i;
07d3f51f 3266 int rc;
1da177e4 3267
4ff96fa6
FR		 3268 if (netif_msg_drv(&debug)) {
3269 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3270 MODULENAME, RTL8169_VERSION);
3271 }
1da177e4 3272
1da177e4 3273 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3274 if (!dev) {
b57b7e5a 3275 if (netif_msg_drv(&debug))
9b91cf9d 3276 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3277 rc = -ENOMEM;
3278 goto out;
1da177e4
LT		 3279 }
3280
1da177e4 3281 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3282 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3283 tp = netdev_priv(dev);
c4028958 3284 tp->dev = dev;
21e197f2 3285 tp->pci_dev = pdev;
b57b7e5a 3286 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3287
ccdffb9a
FR		 3288 mii = &tp->mii;
3289 mii->dev = dev;
3290 mii->mdio_read = rtl_mdio_read;
3291 mii->mdio_write = rtl_mdio_write;
3292 mii->phy_id_mask = 0x1f;
3293 mii->reg_num_mask = 0x1f;
3294 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3295
ba04c7c9
SG		 3296 /* disable ASPM completely as that cause random device stop working
3297 * problems as well as full system hangs for some PCIe devices users */
3298 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3299 PCIE_LINK_STATE_CLKPM);
3300
1da177e4
LT		 3301 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3302 rc = pci_enable_device(pdev);
b57b7e5a 3303 if (rc < 0) {
bf82c189 3304 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3305 goto err_out_free_dev_1;
1da177e4
LT		 3306 }
3307
87aeec76 3308 if (pci_set_mwi(pdev) < 0)
3309 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3310
1da177e4 3311 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3312 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3313 netif_err(tp, probe, dev,
3314 "region #%d not an MMIO resource, aborting\n",
3315 region);
1da177e4 3316 rc = -ENODEV;
87aeec76 3317 goto err_out_mwi_2;
1da177e4 3318 }
4ff96fa6 3319
1da177e4 3320 /* check for weird/broken PCI region reporting */
bcf0bf90 3321 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3322 netif_err(tp, probe, dev,
3323 "Invalid PCI region size(s), aborting\n");
1da177e4 3324 rc = -ENODEV;
87aeec76 3325 goto err_out_mwi_2;
1da177e4
LT		 3326 }
3327
3328 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3329 if (rc < 0) {
bf82c189 3330 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3331 goto err_out_mwi_2;
1da177e4
LT		 3332 }
3333
d24e9aaf 3334 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3335
3336 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3337 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3338 tp->cp_cmd |= PCIDAC;
3339 dev->features |= NETIF_F_HIGHDMA;
3340 } else {
284901a9 3341 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3342 if (rc < 0) {
bf82c189 3343 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3344 goto err_out_free_res_3;
1da177e4
LT		 3345 }
3346 }
3347
1da177e4 3348 /* ioremap MMIO region */
bcf0bf90 3349 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3350 if (!ioaddr) {
bf82c189 3351 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3352 rc = -EIO;
87aeec76 3353 goto err_out_free_res_3;
1da177e4 3354 }
6f43adc8 3355 tp->mmio_addr = ioaddr;
1da177e4 3356
4300e8c7
DM		 3357 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3358 if (!tp->pcie_cap)
3359 netif_info(tp, probe, dev, "no PCI Express capability\n");
3360
d78ad8cb 3361 RTL_W16(IntrMask, 0x0000);
1da177e4 3362
6f43adc8 3363 rtl_hw_reset(tp);
1da177e4 3364
d78ad8cb
KW		 3365 RTL_W16(IntrStatus, 0xffff);
3366
ca52efd5 3367 pci_set_master(pdev);
3368
1da177e4 3369 /* Identify chip attached to board */
5d320a20 3370 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
1da177e4 3371
7a8fc77b
FR		 3372 /*
3373 * Pretend we are using VLANs; This bypasses a nasty bug where
3374 * Interrupts stop flowing on high load on 8110SCd controllers.
3375 */
3376 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3377 tp->cp_cmd |= RxVlan;
3378
c0e45c1c 3379 rtl_init_mdio_ops(tp);
065c27c1 3380 rtl_init_pll_power_ops(tp);
c0e45c1c 3381
1da177e4 3382 rtl8169_print_mac_version(tp);
1da177e4 3383
85bffe6c
FR		 3384 chipset = tp->mac_version;
3385 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 3386
5d06a99f
FR		 3387 RTL_W8(Cfg9346, Cfg9346_Unlock);
3388 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3389 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3390 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3391 tp->features |= RTL_FEATURE_WOL;
3392 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3393 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3394 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3395 RTL_W8(Cfg9346, Cfg9346_Lock);
3396
66ec5d4f
FR		 3397 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3398 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3399 tp->set_speed = rtl8169_set_speed_tbi;
3400 tp->get_settings = rtl8169_gset_tbi;
3401 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3402 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3403 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3404 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 3405 } else {
3406 tp->set_speed = rtl8169_set_speed_xmii;
3407 tp->get_settings = rtl8169_gset_xmii;
3408 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3409 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3410 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3411 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3412 }
3413
df58ef51
FR		 3414 spin_lock_init(&tp->lock);
3415
7bf6bf48 3416 /* Get MAC address */
1da177e4
LT		 3417 for (i = 0; i < MAC_ADDR_LEN; i++)
3418 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3419 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3420
1da177e4 3421 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3422 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3423 dev->irq = pdev->irq;
3424 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3425
bea3348e 3426 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3427
350fb32a
MM		 3428 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3429 * properly for all devices */
3430 dev->features |= NETIF_F_RXCSUM |
3431 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3432
3433 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3434 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3435 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3436 NETIF_F_HIGHDMA;
3437
3438 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3439 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3440 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3441
3442 tp->intr_mask = 0xffff;
0e485150
FR		 3443 tp->hw_start = cfg->hw_start;
3444 tp->intr_event = cfg->intr_event;
3445 tp->napi_event = cfg->napi_event;
1da177e4 3446
2efa53f3
FR		 3447 init_timer(&tp->timer);
3448 tp->timer.data = (unsigned long) dev;
3449 tp->timer.function = rtl8169_phy_timer;
3450
b6ffd97f 3451 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
953a12cc 3452
1da177e4 3453 rc = register_netdev(dev);
4ff96fa6 3454 if (rc < 0)
87aeec76 3455 goto err_out_msi_4;
1da177e4
LT		 3456
3457 pci_set_drvdata(pdev, dev);
3458
bf82c189 3459 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 3460 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3461 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3462
cecb5fd7
FR		 3463 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3464 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3465 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3466 rtl8168_driver_start(tp);
e6de30d6 3467 }
b646d900 3468
8b76ab39 3469 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3470
f3ec4f87
AS		 3471 if (pci_dev_run_wake(pdev))
3472 pm_runtime_put_noidle(&pdev->dev);
e1759441 3473
0d672e9f
IV		 3474 netif_carrier_off(dev);
3475
4ff96fa6
FR		 3476out:
3477 return rc;
1da177e4 3478
87aeec76 3479err_out_msi_4:
fbac58fc 3480 rtl_disable_msi(pdev, tp);
4ff96fa6 3481 iounmap(ioaddr);
87aeec76 3482err_out_free_res_3:
4ff96fa6 3483 pci_release_regions(pdev);
87aeec76 3484err_out_mwi_2:
4ff96fa6 3485 pci_clear_mwi(pdev);
4ff96fa6
FR		 3486 pci_disable_device(pdev);
3487err_out_free_dev_1:
3488 free_netdev(dev);
3489 goto out;
1da177e4
LT		 3490}
3491
07d3f51f 3492static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3493{
3494 struct net_device *dev = pci_get_drvdata(pdev);
3495 struct rtl8169_private *tp = netdev_priv(dev);
3496
cecb5fd7
FR		 3497 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3498 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3499 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3500 rtl8168_driver_stop(tp);
e6de30d6 3501 }
b646d900 3502
23f333a2 3503 cancel_delayed_work_sync(&tp->task);
eb2a021c 3504
1da177e4 3505 unregister_netdev(dev);
cc098dc7 3506
953a12cc
FR		 3507 rtl_release_firmware(tp);
3508
f3ec4f87
AS		 3509 if (pci_dev_run_wake(pdev))
3510 pm_runtime_get_noresume(&pdev->dev);
e1759441 3511
cc098dc7
IV		 3512 /* restore original MAC address */
3513 rtl_rar_set(tp, dev->perm_addr);
3514
fbac58fc 3515 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3516 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3517 pci_set_drvdata(pdev, NULL);
3518}
3519
b6ffd97f 3520static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
953a12cc 3521{
b6ffd97f
FR		 3522 struct rtl_fw *rtl_fw;
3523 const char *name;
3524 int rc = -ENOMEM;
953a12cc 3525
b6ffd97f
FR		 3526 name = rtl_lookup_firmware_name(tp);
3527 if (!name)
3528 goto out_no_firmware;
953a12cc 3529
b6ffd97f
FR		 3530 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3531 if (!rtl_fw)
3532 goto err_warn;
31bd204f 3533
b6ffd97f
FR		 3534 rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3535 if (rc < 0)
3536 goto err_free;
3537
3538 tp->rtl_fw = rtl_fw;
3539out:
3540 return;
3541
3542err_free:
3543 kfree(rtl_fw);
3544err_warn:
3545 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3546 name, rc);
3547out_no_firmware:
3548 tp->rtl_fw = NULL;
3549 goto out;
3550}
3551
3552static void rtl_request_firmware(struct rtl8169_private *tp)
3553{
3554 if (IS_ERR(tp->rtl_fw))
3555 rtl_request_uncached_firmware(tp);
953a12cc
FR		 3556}
3557
1da177e4
LT		 3558static int rtl8169_open(struct net_device *dev)
3559{
3560 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3561 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3562 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3563 int retval = -ENOMEM;
1da177e4 3564
e1759441 3565 pm_runtime_get_sync(&pdev->dev);
1da177e4 3566
1da177e4
LT		 3567 /*
3568 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3569 * dma_alloc_coherent provides more.
1da177e4 3570 */
82553bb6
SG		 3571 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3572 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3573 if (!tp->TxDescArray)
e1759441 3574 goto err_pm_runtime_put;
1da177e4 3575
82553bb6
SG		 3576 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3577 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3578 if (!tp->RxDescArray)
99f252b0 3579 goto err_free_tx_0;
1da177e4
LT		 3580
3581 retval = rtl8169_init_ring(dev);
3582 if (retval < 0)
99f252b0 3583 goto err_free_rx_1;
1da177e4 3584
c4028958 3585 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3586
99f252b0
FR		 3587 smp_mb();
3588
953a12cc
FR		 3589 rtl_request_firmware(tp);
3590
fbac58fc
FR		 3591 retval = request_irq(dev->irq, rtl8169_interrupt,
3592 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3593 dev->name, dev);
3594 if (retval < 0)
953a12cc 3595 goto err_release_fw_2;
99f252b0 3596
bea3348e 3597 napi_enable(&tp->napi);
bea3348e 3598
eee3a96c 3599 rtl8169_init_phy(dev, tp);
3600
350fb32a 3601 rtl8169_set_features(dev, dev->features);
eee3a96c 3602
065c27c1 3603 rtl_pll_power_up(tp);
3604
07ce4064 3605 rtl_hw_start(dev);
1da177e4 3606
e1759441
RW		 3607 tp->saved_wolopts = 0;
3608 pm_runtime_put_noidle(&pdev->dev);
3609
eee3a96c 3610 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3611out:
3612 return retval;
3613
953a12cc
FR		 3614err_release_fw_2:
3615 rtl_release_firmware(tp);
99f252b0
FR		 3616 rtl8169_rx_clear(tp);
3617err_free_rx_1:
82553bb6
SG		 3618 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3619 tp->RxPhyAddr);
e1759441 3620 tp->RxDescArray = NULL;
99f252b0 3621err_free_tx_0:
82553bb6
SG		 3622 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3623 tp->TxPhyAddr);
e1759441
RW		 3624 tp->TxDescArray = NULL;
3625err_pm_runtime_put:
3626 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3627 goto out;
3628}
3629
e6de30d6 3630static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3631{
e6de30d6 3632 void __iomem *ioaddr = tp->mmio_addr;
3633
1da177e4
LT		 3634 /* Disable interrupts */
3635 rtl8169_irq_mask_and_ack(ioaddr);
3636
5d2e1957 3637 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3638 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3639 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3640 while (RTL_R8(TxPoll) & NPQ)
3641 udelay(20);
3642
3643 }
3644
1da177e4
LT		 3645 /* Reset the chipset */
3646 RTL_W8(ChipCmd, CmdReset);
3647
3648 /* PCI commit */
3649 RTL_R8(ChipCmd);
3650}
3651
7f796d83 3652static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3653{
3654 void __iomem *ioaddr = tp->mmio_addr;
3655 u32 cfg = rtl8169_rx_config;
3656
2b7b4318 3657 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
9cb427b6
FR		 3658 RTL_W32(RxConfig, cfg);
3659
3660 /* Set DMA burst size and Interframe Gap Time */
3661 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3662 (InterFrameGap << TxInterFrameGapShift));
3663}
3664
07ce4064 3665static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3666{
3667 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3668
6f43adc8 3669 rtl_hw_reset(tp);
1da177e4 3670
07ce4064
FR		 3671 tp->hw_start(dev);
3672
07ce4064
FR		 3673 netif_start_queue(dev);
3674}
3675
7f796d83
FR		 3676static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3677 void __iomem *ioaddr)
3678{
3679 /*
3680 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3681 * register to be written before TxDescAddrLow to work.
3682 * Switching from MMIO to I/O access fixes the issue as well.
3683 */
3684 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3685 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3686 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3687 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3688}
3689
3690static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3691{
3692 u16 cmd;
3693
3694 cmd = RTL_R16(CPlusCmd);
3695 RTL_W16(CPlusCmd, cmd);
3696 return cmd;
3697}
3698
fdd7b4c3 3699static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3700{
3701 /* Low hurts. Let's disable the filtering. */
207d6e87 3702 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3703}
3704
6dccd16b
FR		 3705static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3706{
350f7596 3707 static const struct {
6dccd16b
FR		 3708 u32 mac_version;
3709 u32 clk;
3710 u32 val;
3711 } cfg2_info [] = {
3712 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3713 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3714 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3715 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3716 }, *p = cfg2_info;
3717 unsigned int i;
3718 u32 clk;
3719
3720 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3721 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3722 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3723 RTL_W32(0x7c, p->val);
3724 break;
3725 }
3726 }
3727}
3728
07ce4064
FR		 3729static void rtl_hw_start_8169(struct net_device *dev)
3730{
3731 struct rtl8169_private *tp = netdev_priv(dev);
3732 void __iomem *ioaddr = tp->mmio_addr;
3733 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3734
9cb427b6
FR		 3735 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3736 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3737 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3738 }
3739
1da177e4 3740 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 3741 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3742 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3743 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3744 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 3745 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3746
f0298f81 3747 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3748
6f0333b8 3749 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3750
cecb5fd7
FR		 3751 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3752 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3753 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3754 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 3755 rtl_set_rx_tx_config_registers(tp);
1da177e4 3756
7f796d83 3757 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3758
cecb5fd7
FR		 3759 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3760 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 3761 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3762 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3763 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3764 }
3765
bcf0bf90
FR		 3766 RTL_W16(CPlusCmd, tp->cp_cmd);
3767
6dccd16b
FR		 3768 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3769
1da177e4
LT		 3770 /*
3771 * Undocumented corner. Supposedly:
3772 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3773 */
3774 RTL_W16(IntrMitigate, 0x0000);
3775
7f796d83 3776 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3777
cecb5fd7
FR		 3778 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3779 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3780 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3781 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 3782 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3783 rtl_set_rx_tx_config_registers(tp);
3784 }
3785
1da177e4 3786 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3787
3788 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3789 RTL_R8(IntrMask);
1da177e4
LT		 3790
3791 RTL_W32(RxMissed, 0);
3792
07ce4064 3793 rtl_set_rx_mode(dev);
1da177e4
LT		 3794
3795 /* no early-rx interrupts */
3796 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3797
3798 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3799 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3800}
1da177e4 3801
9c14ceaf 3802static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3803{
9c14ceaf
FR		 3804 struct net_device *dev = pci_get_drvdata(pdev);
3805 struct rtl8169_private *tp = netdev_priv(dev);
3806 int cap = tp->pcie_cap;
3807
3808 if (cap) {
3809 u16 ctl;
458a9f61 3810
9c14ceaf
FR		 3811 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3812 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3813 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3814 }
458a9f61
FR		 3815}
3816
650e8d5d 3817static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3818{
3819 u32 csi;
3820
3821 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3822 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3823}
3824
e6de30d6 3825static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3826{
3827 rtl_csi_access_enable(ioaddr, 0x17000000);
3828}
3829
650e8d5d 3830static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3831{
3832 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3833}
3834
3835struct ephy_info {
3836 unsigned int offset;
3837 u16 mask;
3838 u16 bits;
3839};
3840
350f7596 3841static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3842{
3843 u16 w;
3844
3845 while (len-- > 0) {
3846 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3847 rtl_ephy_write(ioaddr, e->offset, w);
3848 e++;
3849 }
3850}
3851
b726e493
FR		 3852static void rtl_disable_clock_request(struct pci_dev *pdev)
3853{
3854 struct net_device *dev = pci_get_drvdata(pdev);
3855 struct rtl8169_private *tp = netdev_priv(dev);
3856 int cap = tp->pcie_cap;
3857
3858 if (cap) {
3859 u16 ctl;
3860
3861 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3862 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3863 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3864 }
3865}
3866
e6de30d6 3867static void rtl_enable_clock_request(struct pci_dev *pdev)
3868{
3869 struct net_device *dev = pci_get_drvdata(pdev);
3870 struct rtl8169_private *tp = netdev_priv(dev);
3871 int cap = tp->pcie_cap;
3872
3873 if (cap) {
3874 u16 ctl;
3875
3876 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3877 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3878 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3879 }
3880}
3881
b726e493
FR		 3882#define R8168_CPCMD_QUIRK_MASK (\
3883 EnableBist | \
3884 Mac_dbgo_oe | \
3885 Force_half_dup | \
3886 Force_rxflow_en | \
3887 Force_txflow_en | \
3888 Cxpl_dbg_sel | \
3889 ASF | \
3890 PktCntrDisable | \
3891 Mac_dbgo_sel)
3892
219a1e9d
FR		 3893static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3894{
b726e493
FR		 3895 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3896
3897 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3898
2e68ae44
FR		 3899 rtl_tx_performance_tweak(pdev,
3900 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3901}
3902
3903static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3904{
3905 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3906
f0298f81 3907 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3908
3909 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3910}
3911
3912static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3913{
b726e493
FR		 3914 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3915
3916 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3917
219a1e9d 3918 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3919
3920 rtl_disable_clock_request(pdev);
3921
3922 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3923}
3924
ef3386f0 3925static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3926{
350f7596 3927 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3928 { 0x01, 0, 0x0001 },
3929 { 0x02, 0x0800, 0x1000 },
3930 { 0x03, 0, 0x0042 },
3931 { 0x06, 0x0080, 0x0000 },
3932 { 0x07, 0, 0x2000 }
3933 };
3934
650e8d5d 3935 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3936
3937 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3938
219a1e9d
FR		 3939 __rtl_hw_start_8168cp(ioaddr, pdev);
3940}
3941
ef3386f0
FR		 3942static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3943{
650e8d5d 3944 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3945
3946 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3947
3948 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3949
3950 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3951}
3952
7f3e3d3a
FR		 3953static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3954{
650e8d5d 3955 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3956
3957 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3958
3959 /* Magic. */
3960 RTL_W8(DBG_REG, 0x20);
3961
f0298f81 3962 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3963
3964 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3965
3966 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3967}
3968
219a1e9d
FR		 3969static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3970{
350f7596 3971 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3972 { 0x02, 0x0800, 0x1000 },
3973 { 0x03, 0, 0x0002 },
3974 { 0x06, 0x0080, 0x0000 }
3975 };
3976
650e8d5d 3977 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3978
3979 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3980
3981 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3982
219a1e9d
FR		 3983 __rtl_hw_start_8168cp(ioaddr, pdev);
3984}
3985
3986static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3987{
350f7596 3988 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3989 { 0x01, 0, 0x0001 },
3990 { 0x03, 0x0400, 0x0220 }
3991 };
3992
650e8d5d 3993 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3994
3995 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3996
219a1e9d
FR		 3997 __rtl_hw_start_8168cp(ioaddr, pdev);
3998}
3999
197ff761
FR		 4000static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4001{
4002 rtl_hw_start_8168c_2(ioaddr, pdev);
4003}
4004
6fb07058
FR		 4005static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4006{
650e8d5d 4007 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 4008
4009 __rtl_hw_start_8168cp(ioaddr, pdev);
4010}
4011
5b538df9
FR		 4012static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4013{
650e8d5d 4014 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 4015
4016 rtl_disable_clock_request(pdev);
4017
f0298f81 4018 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 4019
4020 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4021
4022 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4023}
4024
4804b3b3 4025static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4026{
4027 rtl_csi_access_enable_1(ioaddr);
4028
4029 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4030
4031 RTL_W8(MaxTxPacketSize, TxPacketMax);
4032
4033 rtl_disable_clock_request(pdev);
4034}
4035
e6de30d6 4036static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4037{
4038 static const struct ephy_info e_info_8168d_4[] = {
4039 { 0x0b, ~0, 0x48 },
4040 { 0x19, 0x20, 0x50 },
4041 { 0x0c, ~0, 0x20 }
4042 };
4043 int i;
4044
4045 rtl_csi_access_enable_1(ioaddr);
4046
4047 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4048
4049 RTL_W8(MaxTxPacketSize, TxPacketMax);
4050
4051 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4052 const struct ephy_info *e = e_info_8168d_4 + i;
4053 u16 w;
4054
4055 w = rtl_ephy_read(ioaddr, e->offset);
4056 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4057 }
4058
4059 rtl_enable_clock_request(pdev);
4060}
4061
01dc7fec 4062static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4063{
4064 static const struct ephy_info e_info_8168e[] = {
4065 { 0x00, 0x0200, 0x0100 },
4066 { 0x00, 0x0000, 0x0004 },
4067 { 0x06, 0x0002, 0x0001 },
4068 { 0x06, 0x0000, 0x0030 },
4069 { 0x07, 0x0000, 0x2000 },
4070 { 0x00, 0x0000, 0x0020 },
4071 { 0x03, 0x5800, 0x2000 },
4072 { 0x03, 0x0000, 0x0001 },
4073 { 0x01, 0x0800, 0x1000 },
4074 { 0x07, 0x0000, 0x4000 },
4075 { 0x1e, 0x0000, 0x2000 },
4076 { 0x19, 0xffff, 0xfe6c },
4077 { 0x0a, 0x0000, 0x0040 }
4078 };
4079
4080 rtl_csi_access_enable_2(ioaddr);
4081
4082 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4083
4084 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4085
4086 RTL_W8(MaxTxPacketSize, TxPacketMax);
4087
4088 rtl_disable_clock_request(pdev);
4089
4090 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4091 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4092 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4093
cecb5fd7 4094 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4095}
4096
07ce4064
FR		 4097static void rtl_hw_start_8168(struct net_device *dev)
4098{
2dd99530
FR		 4099 struct rtl8169_private *tp = netdev_priv(dev);
4100 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4101 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4102
4103 RTL_W8(Cfg9346, Cfg9346_Unlock);
4104
f0298f81 4105 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4106
6f0333b8 4107 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4108
0e485150 4109 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4110
4111 RTL_W16(CPlusCmd, tp->cp_cmd);
4112
0e485150 4113 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4114
0e485150 4115 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4116 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4117 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4118 tp->intr_event |= RxFIFOOver | PCSTimeout;
4119 tp->intr_event &= ~RxOverflow;
4120 }
4121
4122 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4123
b8363901
FR		 4124 rtl_set_rx_mode(dev);
4125
4126 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4127 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4128
4129 RTL_R8(IntrMask);
4130
219a1e9d
FR		 4131 switch (tp->mac_version) {
4132 case RTL_GIGA_MAC_VER_11:
4133 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4134 break;
219a1e9d
FR		 4135
4136 case RTL_GIGA_MAC_VER_12:
4137 case RTL_GIGA_MAC_VER_17:
4138 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4139 break;
219a1e9d
FR		 4140
4141 case RTL_GIGA_MAC_VER_18:
ef3386f0 4142 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4143 break;
219a1e9d
FR		 4144
4145 case RTL_GIGA_MAC_VER_19:
4146 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4147 break;
219a1e9d
FR		 4148
4149 case RTL_GIGA_MAC_VER_20:
4150 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4151 break;
219a1e9d 4152
197ff761
FR		 4153 case RTL_GIGA_MAC_VER_21:
4154 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4155 break;
197ff761 4156
6fb07058
FR		 4157 case RTL_GIGA_MAC_VER_22:
4158 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4159 break;
6fb07058 4160
ef3386f0
FR		 4161 case RTL_GIGA_MAC_VER_23:
4162 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4163 break;
ef3386f0 4164
7f3e3d3a
FR		 4165 case RTL_GIGA_MAC_VER_24:
4166 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4167 break;
7f3e3d3a 4168
5b538df9 4169 case RTL_GIGA_MAC_VER_25:
daf9df6d 4170 case RTL_GIGA_MAC_VER_26:
4171 case RTL_GIGA_MAC_VER_27:
5b538df9 4172 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4173 break;
5b538df9 4174
e6de30d6 4175 case RTL_GIGA_MAC_VER_28:
4176 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4177 break;
cecb5fd7 4178
4804b3b3 4179 case RTL_GIGA_MAC_VER_31:
4180 rtl_hw_start_8168dp(ioaddr, pdev);
4181 break;
4182
01dc7fec 4183 case RTL_GIGA_MAC_VER_32:
4184 case RTL_GIGA_MAC_VER_33:
4185 rtl_hw_start_8168e(ioaddr, pdev);
4186 break;
e6de30d6 4187
219a1e9d
FR		 4188 default:
4189 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4190 dev->name, tp->mac_version);
4804b3b3 4191 break;
219a1e9d 4192 }
2dd99530 4193
0e485150
FR		 4194 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4195
b8363901
FR		 4196 RTL_W8(Cfg9346, Cfg9346_Lock);
4197
2dd99530 4198 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4199
0e485150 4200 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4201}
1da177e4 4202
2857ffb7
FR		 4203#define R810X_CPCMD_QUIRK_MASK (\
4204 EnableBist | \
4205 Mac_dbgo_oe | \
4206 Force_half_dup | \
5edcc537 4207 Force_rxflow_en | \
2857ffb7
FR		 4208 Force_txflow_en | \
4209 Cxpl_dbg_sel | \
4210 ASF | \
4211 PktCntrDisable | \
d24e9aaf 4212 Mac_dbgo_sel)
2857ffb7
FR		 4213
4214static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4215{
350f7596 4216 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4217 { 0x01, 0, 0x6e65 },
4218 { 0x02, 0, 0x091f },
4219 { 0x03, 0, 0xc2f9 },
4220 { 0x06, 0, 0xafb5 },
4221 { 0x07, 0, 0x0e00 },
4222 { 0x19, 0, 0xec80 },
4223 { 0x01, 0, 0x2e65 },
4224 { 0x01, 0, 0x6e65 }
4225 };
4226 u8 cfg1;
4227
650e8d5d 4228 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4229
4230 RTL_W8(DBG_REG, FIX_NAK_1);
4231
4232 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4233
4234 RTL_W8(Config1,
4235 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4236 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4237
4238 cfg1 = RTL_R8(Config1);
4239 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4240 RTL_W8(Config1, cfg1 & ~LEDS0);
4241
2857ffb7
FR		 4242 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4243}
4244
4245static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4246{
650e8d5d 4247 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4248
4249 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4250
4251 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4252 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4253}
4254
4255static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4256{
4257 rtl_hw_start_8102e_2(ioaddr, pdev);
4258
4259 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4260}
4261
5a5e4443
HW		 4262static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4263{
4264 static const struct ephy_info e_info_8105e_1[] = {
4265 { 0x07, 0, 0x4000 },
4266 { 0x19, 0, 0x0200 },
4267 { 0x19, 0, 0x0020 },
4268 { 0x1e, 0, 0x2000 },
4269 { 0x03, 0, 0x0001 },
4270 { 0x19, 0, 0x0100 },
4271 { 0x19, 0, 0x0004 },
4272 { 0x0a, 0, 0x0020 }
4273 };
4274
cecb5fd7 4275 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 4276 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4277
cecb5fd7 4278 /* Disable Early Tally Counter */
5a5e4443
HW		 4279 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4280
4281 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4282 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4283
4284 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4285}
4286
4287static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4288{
4289 rtl_hw_start_8105e_1(ioaddr, pdev);
4290 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4291}
4292
07ce4064
FR		 4293static void rtl_hw_start_8101(struct net_device *dev)
4294{
cdf1a608
FR		 4295 struct rtl8169_private *tp = netdev_priv(dev);
4296 void __iomem *ioaddr = tp->mmio_addr;
4297 struct pci_dev *pdev = tp->pci_dev;
4298
cecb5fd7
FR		 4299 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4300 tp->mac_version == RTL_GIGA_MAC_VER_16) {
9c14ceaf
FR		 4301 int cap = tp->pcie_cap;
4302
4303 if (cap) {
4304 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4305 PCI_EXP_DEVCTL_NOSNOOP_EN);
4306 }
cdf1a608
FR		 4307 }
4308
d24e9aaf
HW		 4309 RTL_W8(Cfg9346, Cfg9346_Unlock);
4310
2857ffb7
FR		 4311 switch (tp->mac_version) {
4312 case RTL_GIGA_MAC_VER_07:
4313 rtl_hw_start_8102e_1(ioaddr, pdev);
4314 break;
4315
4316 case RTL_GIGA_MAC_VER_08:
4317 rtl_hw_start_8102e_3(ioaddr, pdev);
4318 break;
4319
4320 case RTL_GIGA_MAC_VER_09:
4321 rtl_hw_start_8102e_2(ioaddr, pdev);
4322 break;
5a5e4443
HW		 4323
4324 case RTL_GIGA_MAC_VER_29:
4325 rtl_hw_start_8105e_1(ioaddr, pdev);
4326 break;
4327 case RTL_GIGA_MAC_VER_30:
4328 rtl_hw_start_8105e_2(ioaddr, pdev);
4329 break;
cdf1a608
FR		 4330 }
4331
d24e9aaf 4332 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4333
f0298f81 4334 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4335
6f0333b8 4336 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4337
d24e9aaf 4338 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4339 RTL_W16(CPlusCmd, tp->cp_cmd);
4340
4341 RTL_W16(IntrMitigate, 0x0000);
4342
4343 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4344
4345 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4346 rtl_set_rx_tx_config_registers(tp);
4347
cdf1a608
FR		 4348 RTL_R8(IntrMask);
4349
cdf1a608
FR		 4350 rtl_set_rx_mode(dev);
4351
4352 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4353
0e485150 4354 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4355}
4356
4357static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4358{
1da177e4
LT		 4359 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4360 return -EINVAL;
4361
4362 dev->mtu = new_mtu;
350fb32a
MM		 4363 netdev_update_features(dev);
4364
323bb685 4365 return 0;
1da177e4
LT		 4366}
4367
4368static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4369{
95e0918d 4370 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4371 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4372}
4373
6f0333b8
ED		 4374static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4375 void **data_buff, struct RxDesc *desc)
1da177e4 4376{
48addcc9 4377 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4378 DMA_FROM_DEVICE);
48addcc9 4379
6f0333b8
ED		 4380 kfree(*data_buff);
4381 *data_buff = NULL;
1da177e4
LT		 4382 rtl8169_make_unusable_by_asic(desc);
4383}
4384
4385static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4386{
4387 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4388
4389 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4390}
4391
4392static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4393 u32 rx_buf_sz)
4394{
4395 desc->addr = cpu_to_le64(mapping);
4396 wmb();
4397 rtl8169_mark_to_asic(desc, rx_buf_sz);
4398}
4399
6f0333b8
ED		 4400static inline void *rtl8169_align(void *data)
4401{
4402 return (void *)ALIGN((long)data, 16);
4403}
4404
0ecbe1ca
SG		 4405static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4406 struct RxDesc *desc)
1da177e4 4407{
6f0333b8 4408 void *data;
1da177e4 4409 dma_addr_t mapping;
48addcc9 4410 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4411 struct net_device *dev = tp->dev;
6f0333b8 4412 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4413
6f0333b8
ED		 4414 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4415 if (!data)
4416 return NULL;
e9f63f30 4417
6f0333b8
ED		 4418 if (rtl8169_align(data) != data) {
4419 kfree(data);
4420 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4421 if (!data)
4422 return NULL;
4423 }
3eafe507 4424
48addcc9 4425 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4426 DMA_FROM_DEVICE);
d827d86b
SG		 4427 if (unlikely(dma_mapping_error(d, mapping))) {
4428 if (net_ratelimit())
4429 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4430 goto err_out;
d827d86b 4431 }
1da177e4
LT		 4432
4433 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4434 return data;
3eafe507
SG		 4435
4436err_out:
4437 kfree(data);
4438 return NULL;
1da177e4
LT		 4439}
4440
4441static void rtl8169_rx_clear(struct rtl8169_private *tp)
4442{
07d3f51f 4443 unsigned int i;
1da177e4
LT		 4444
4445 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4446 if (tp->Rx_databuff[i]) {
4447 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4448 tp->RxDescArray + i);
4449 }
4450 }
4451}
4452
0ecbe1ca 4453static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4454{
0ecbe1ca
SG		 4455 desc->opts1 |= cpu_to_le32(RingEnd);
4456}
5b0384f4 4457
0ecbe1ca
SG		 4458static int rtl8169_rx_fill(struct rtl8169_private *tp)
4459{
4460 unsigned int i;
1da177e4 4461
0ecbe1ca
SG		 4462 for (i = 0; i < NUM_RX_DESC; i++) {
4463 void *data;
4ae47c2d 4464
6f0333b8 4465 if (tp->Rx_databuff[i])
1da177e4 4466 continue;
bcf0bf90 4467
0ecbe1ca 4468 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4469 if (!data) {
4470 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4471 goto err_out;
6f0333b8
ED		 4472 }
4473 tp->Rx_databuff[i] = data;
1da177e4 4474 }
1da177e4 4475
0ecbe1ca
SG		 4476 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4477 return 0;
4478
4479err_out:
4480 rtl8169_rx_clear(tp);
4481 return -ENOMEM;
1da177e4
LT		 4482}
4483
4484static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4485{
4486 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4487}
4488
4489static int rtl8169_init_ring(struct net_device *dev)
4490{
4491 struct rtl8169_private *tp = netdev_priv(dev);
4492
4493 rtl8169_init_ring_indexes(tp);
4494
4495 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4496 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4497
0ecbe1ca 4498 return rtl8169_rx_fill(tp);
1da177e4
LT		 4499}
4500
48addcc9 4501static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4502 struct TxDesc *desc)
4503{
4504 unsigned int len = tx_skb->len;
4505
48addcc9
SG		 4506 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4507
1da177e4
LT		 4508 desc->opts1 = 0x00;
4509 desc->opts2 = 0x00;
4510 desc->addr = 0x00;
4511 tx_skb->len = 0;
4512}
4513
3eafe507
SG		 4514static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4515 unsigned int n)
1da177e4
LT		 4516{
4517 unsigned int i;
4518
3eafe507
SG		 4519 for (i = 0; i < n; i++) {
4520 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4521 struct ring_info *tx_skb = tp->tx_skb + entry;
4522 unsigned int len = tx_skb->len;
4523
4524 if (len) {
4525 struct sk_buff *skb = tx_skb->skb;
4526
48addcc9 4527 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4528 tp->TxDescArray + entry);
4529 if (skb) {
cac4b22f 4530 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4531 dev_kfree_skb(skb);
4532 tx_skb->skb = NULL;
4533 }
1da177e4
LT		 4534 }
4535 }
3eafe507
SG		 4536}
4537
4538static void rtl8169_tx_clear(struct rtl8169_private *tp)
4539{
4540 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4541 tp->cur_tx = tp->dirty_tx = 0;
4542}
4543
c4028958 4544static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4545{
4546 struct rtl8169_private *tp = netdev_priv(dev);
4547
c4028958 4548 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4549 schedule_delayed_work(&tp->task, 4);
4550}
4551
4552static void rtl8169_wait_for_quiescence(struct net_device *dev)
4553{
4554 struct rtl8169_private *tp = netdev_priv(dev);
4555 void __iomem *ioaddr = tp->mmio_addr;
4556
4557 synchronize_irq(dev->irq);
4558
4559 /* Wait for any pending NAPI task to complete */
bea3348e 4560 napi_disable(&tp->napi);
1da177e4
LT		 4561
4562 rtl8169_irq_mask_and_ack(ioaddr);
4563
d1d08d12
DM		 4564 tp->intr_mask = 0xffff;
4565 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4566 napi_enable(&tp->napi);
1da177e4
LT		 4567}
4568
c4028958 4569static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4570{
c4028958
DH		 4571 struct rtl8169_private *tp =
4572 container_of(work, struct rtl8169_private, task.work);
4573 struct net_device *dev = tp->dev;
1da177e4
LT		 4574 int ret;
4575
eb2a021c
FR		 4576 rtnl_lock();
4577
4578 if (!netif_running(dev))
4579 goto out_unlock;
4580
4581 rtl8169_wait_for_quiescence(dev);
4582 rtl8169_close(dev);
1da177e4
LT		 4583
4584 ret = rtl8169_open(dev);
4585 if (unlikely(ret < 0)) {
bf82c189
JP		 4586 if (net_ratelimit())
4587 netif_err(tp, drv, dev,
4588 "reinit failure (status = %d). Rescheduling\n",
4589 ret);
1da177e4
LT		 4590 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4591 }
eb2a021c
FR		 4592
4593out_unlock:
4594 rtnl_unlock();
1da177e4
LT		 4595}
4596
c4028958 4597static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4598{
c4028958
DH		 4599 struct rtl8169_private *tp =
4600 container_of(work, struct rtl8169_private, task.work);
4601 struct net_device *dev = tp->dev;
56de414c 4602 int i;
1da177e4 4603
eb2a021c
FR		 4604 rtnl_lock();
4605
1da177e4 4606 if (!netif_running(dev))
eb2a021c 4607 goto out_unlock;
1da177e4
LT		 4608
4609 rtl8169_wait_for_quiescence(dev);
4610
56de414c
FR		 4611 for (i = 0; i < NUM_RX_DESC; i++)
4612 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4613
1da177e4
LT		 4614 rtl8169_tx_clear(tp);
4615
56de414c
FR		 4616 rtl8169_init_ring_indexes(tp);
4617 rtl_hw_start(dev);
4618 netif_wake_queue(dev);
4619 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 4620
4621out_unlock:
4622 rtnl_unlock();
1da177e4
LT		 4623}
4624
4625static void rtl8169_tx_timeout(struct net_device *dev)
4626{
4627 struct rtl8169_private *tp = netdev_priv(dev);
4628
e6de30d6 4629 rtl8169_hw_reset(tp);
1da177e4
LT		 4630
4631 /* Let's wait a bit while any (async) irq lands on */
4632 rtl8169_schedule_work(dev, rtl8169_reset_task);
4633}
4634
4635static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 4636 u32 *opts)
1da177e4
LT		 4637{
4638 struct skb_shared_info *info = skb_shinfo(skb);
4639 unsigned int cur_frag, entry;
a6343afb 4640 struct TxDesc * uninitialized_var(txd);
48addcc9 4641 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4642
4643 entry = tp->cur_tx;
4644 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4645 skb_frag_t *frag = info->frags + cur_frag;
4646 dma_addr_t mapping;
4647 u32 status, len;
4648 void *addr;
4649
4650 entry = (entry + 1) % NUM_TX_DESC;
4651
4652 txd = tp->TxDescArray + entry;
4653 len = frag->size;
4654 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4655 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4656 if (unlikely(dma_mapping_error(d, mapping))) {
4657 if (net_ratelimit())
4658 netif_err(tp, drv, tp->dev,
4659 "Failed to map TX fragments DMA!\n");
3eafe507 4660 goto err_out;
d827d86b 4661 }
1da177e4 4662
cecb5fd7 4663 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 4664 status = opts[0] | len |
4665 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4666
4667 txd->opts1 = cpu_to_le32(status);
2b7b4318 4668 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 4669 txd->addr = cpu_to_le64(mapping);
4670
4671 tp->tx_skb[entry].len = len;
4672 }
4673
4674 if (cur_frag) {
4675 tp->tx_skb[entry].skb = skb;
4676 txd->opts1 |= cpu_to_le32(LastFrag);
4677 }
4678
4679 return cur_frag;
3eafe507
SG		 4680
4681err_out:
4682 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4683 return -EIO;
1da177e4
LT		 4684}
4685
2b7b4318
FR		 4686static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4687 struct sk_buff *skb, u32 *opts)
1da177e4 4688{
2b7b4318 4689 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 4690 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 4691 int offset = info->opts_offset;
350fb32a 4692
2b7b4318
FR		 4693 if (mss) {
4694 opts[0] |= TD_LSO;
4695 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4696 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4697 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4698
4699 if (ip->protocol == IPPROTO_TCP)
2b7b4318 4700 opts[offset] |= info->checksum.tcp;
1da177e4 4701 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 4702 opts[offset] |= info->checksum.udp;
4703 else
4704 WARN_ON_ONCE(1);
1da177e4 4705 }
1da177e4
LT		 4706}
4707
61357325
SH		 4708static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4709 struct net_device *dev)
1da177e4
LT		 4710{
4711 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4712 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4713 struct TxDesc *txd = tp->TxDescArray + entry;
4714 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4715 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4716 dma_addr_t mapping;
4717 u32 status, len;
2b7b4318 4718 u32 opts[2];
3eafe507 4719 int frags;
5b0384f4 4720
1da177e4 4721 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4722 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4723 goto err_stop_0;
1da177e4
LT		 4724 }
4725
4726 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4727 goto err_stop_0;
4728
4729 len = skb_headlen(skb);
48addcc9 4730 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4731 if (unlikely(dma_mapping_error(d, mapping))) {
4732 if (net_ratelimit())
4733 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4734 goto err_dma_0;
d827d86b 4735 }
3eafe507
SG		 4736
4737 tp->tx_skb[entry].len = len;
4738 txd->addr = cpu_to_le64(mapping);
1da177e4 4739
2b7b4318
FR		 4740 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4741 opts[0] = DescOwn;
1da177e4 4742
2b7b4318
FR		 4743 rtl8169_tso_csum(tp, skb, opts);
4744
4745 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 4746 if (frags < 0)
4747 goto err_dma_1;
4748 else if (frags)
2b7b4318 4749 opts[0] |= FirstFrag;
3eafe507 4750 else {
2b7b4318 4751 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 4752 tp->tx_skb[entry].skb = skb;
4753 }
4754
2b7b4318
FR		 4755 txd->opts2 = cpu_to_le32(opts[1]);
4756
1da177e4
LT		 4757 wmb();
4758
cecb5fd7 4759 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 4760 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4761 txd->opts1 = cpu_to_le32(status);
4762
1da177e4
LT		 4763 tp->cur_tx += frags + 1;
4764
4c020a96 4765 wmb();
1da177e4 4766
cecb5fd7 4767 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4768
4769 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4770 netif_stop_queue(dev);
4771 smp_rmb();
4772 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4773 netif_wake_queue(dev);
4774 }
4775
61357325 4776 return NETDEV_TX_OK;
1da177e4 4777
3eafe507 4778err_dma_1:
48addcc9 4779 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4780err_dma_0:
4781 dev_kfree_skb(skb);
4782 dev->stats.tx_dropped++;
4783 return NETDEV_TX_OK;
4784
4785err_stop_0:
1da177e4 4786 netif_stop_queue(dev);
cebf8cc7 4787 dev->stats.tx_dropped++;
61357325 4788 return NETDEV_TX_BUSY;
1da177e4
LT		 4789}
4790
4791static void rtl8169_pcierr_interrupt(struct net_device *dev)
4792{
4793 struct rtl8169_private *tp = netdev_priv(dev);
4794 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4795 u16 pci_status, pci_cmd;
4796
4797 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4798 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4799
bf82c189
JP		 4800 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4801 pci_cmd, pci_status);
1da177e4
LT		 4802
4803 /*
4804 * The recovery sequence below admits a very elaborated explanation:
4805 * - it seems to work;
d03902b8
FR		 4806 * - I did not see what else could be done;
4807 * - it makes iop3xx happy.
1da177e4
LT		 4808 *
4809 * Feel free to adjust to your needs.
4810 */
a27993f3 4811 if (pdev->broken_parity_status)
d03902b8
FR		 4812 pci_cmd &= ~PCI_COMMAND_PARITY;
4813 else
4814 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4815
4816 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4817
4818 pci_write_config_word(pdev, PCI_STATUS,
4819 pci_status & (PCI_STATUS_DETECTED_PARITY |
4820 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4821 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4822
4823 /* The infamous DAC f*ckup only happens at boot time */
4824 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4825 void __iomem *ioaddr = tp->mmio_addr;
4826
bf82c189 4827 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4828 tp->cp_cmd &= ~PCIDAC;
4829 RTL_W16(CPlusCmd, tp->cp_cmd);
4830 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4831 }
4832
e6de30d6 4833 rtl8169_hw_reset(tp);
d03902b8
FR		 4834
4835 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4836}
4837
07d3f51f
FR		 4838static void rtl8169_tx_interrupt(struct net_device *dev,
4839 struct rtl8169_private *tp,
4840 void __iomem *ioaddr)
1da177e4
LT		 4841{
4842 unsigned int dirty_tx, tx_left;
4843
1da177e4
LT		 4844 dirty_tx = tp->dirty_tx;
4845 smp_rmb();
4846 tx_left = tp->cur_tx - dirty_tx;
4847
4848 while (tx_left > 0) {
4849 unsigned int entry = dirty_tx % NUM_TX_DESC;
4850 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4851 u32 status;
4852
4853 rmb();
4854 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4855 if (status & DescOwn)
4856 break;
4857
48addcc9
SG		 4858 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4859 tp->TxDescArray + entry);
1da177e4 4860 if (status & LastFrag) {
cac4b22f
SG		 4861 dev->stats.tx_packets++;
4862 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4863 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4864 tx_skb->skb = NULL;
4865 }
4866 dirty_tx++;
4867 tx_left--;
4868 }
4869
4870 if (tp->dirty_tx != dirty_tx) {
4871 tp->dirty_tx = dirty_tx;
4872 smp_wmb();
4873 if (netif_queue_stopped(dev) &&
4874 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4875 netif_wake_queue(dev);
4876 }
d78ae2dc
FR		 4877 /*
4878 * 8168 hack: TxPoll requests are lost when the Tx packets are
4879 * too close. Let's kick an extra TxPoll request when a burst
4880 * of start_xmit activity is detected (if it is not detected,
4881 * it is slow enough). -- FR
4882 */
4883 smp_rmb();
4884 if (tp->cur_tx != dirty_tx)
4885 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4886 }
4887}
4888
126fa4b9
FR		 4889static inline int rtl8169_fragmented_frame(u32 status)
4890{
4891 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4892}
4893
adea1ac7 4894static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4895{
1da177e4
LT		 4896 u32 status = opts1 & RxProtoMask;
4897
4898 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4899 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4900 skb->ip_summed = CHECKSUM_UNNECESSARY;
4901 else
bc8acf2c 4902 skb_checksum_none_assert(skb);
1da177e4
LT		 4903}
4904
6f0333b8
ED		 4905static struct sk_buff *rtl8169_try_rx_copy(void *data,
4906 struct rtl8169_private *tp,
4907 int pkt_size,
4908 dma_addr_t addr)
1da177e4 4909{
b449655f 4910 struct sk_buff *skb;
48addcc9 4911 struct device *d = &tp->pci_dev->dev;
b449655f 4912
6f0333b8 4913 data = rtl8169_align(data);
48addcc9 4914 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4915 prefetch(data);
4916 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4917 if (skb)
4918 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4919 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4920
6f0333b8 4921 return skb;
1da177e4
LT		 4922}
4923
07d3f51f
FR		 4924static int rtl8169_rx_interrupt(struct net_device *dev,
4925 struct rtl8169_private *tp,
bea3348e 4926 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4927{
4928 unsigned int cur_rx, rx_left;
6f0333b8 4929 unsigned int count;
1da177e4 4930
1da177e4
LT		 4931 cur_rx = tp->cur_rx;
4932 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4933 rx_left = min(rx_left, budget);
1da177e4 4934
4dcb7d33 4935 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4936 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4937 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4938 u32 status;
4939
4940 rmb();
126fa4b9 4941 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4942
4943 if (status & DescOwn)
4944 break;
4dcb7d33 4945 if (unlikely(status & RxRES)) {
bf82c189
JP		 4946 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4947 status);
cebf8cc7 4948 dev->stats.rx_errors++;
1da177e4 4949 if (status & (RxRWT | RxRUNT))
cebf8cc7 4950 dev->stats.rx_length_errors++;
1da177e4 4951 if (status & RxCRC)
cebf8cc7 4952 dev->stats.rx_crc_errors++;
9dccf611
FR		 4953 if (status & RxFOVF) {
4954 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4955 dev->stats.rx_fifo_errors++;
9dccf611 4956 }
6f0333b8 4957 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4958 } else {
6f0333b8 4959 struct sk_buff *skb;
b449655f 4960 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4961 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4962
126fa4b9
FR		 4963 /*
4964 * The driver does not support incoming fragmented
4965 * frames. They are seen as a symptom of over-mtu
4966 * sized frames.
4967 */
4968 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4969 dev->stats.rx_dropped++;
4970 dev->stats.rx_length_errors++;
6f0333b8 4971 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4972 continue;
126fa4b9
FR		 4973 }
4974
6f0333b8
ED		 4975 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4976 tp, pkt_size, addr);
4977 rtl8169_mark_to_asic(desc, rx_buf_sz);
4978 if (!skb) {
4979 dev->stats.rx_dropped++;
4980 continue;
1da177e4
LT		 4981 }
4982
adea1ac7 4983 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4984 skb_put(skb, pkt_size);
4985 skb->protocol = eth_type_trans(skb, dev);
4986
7a8fc77b
FR		 4987 rtl8169_rx_vlan_tag(desc, skb);
4988
56de414c 4989 napi_gro_receive(&tp->napi, skb);
1da177e4 4990
cebf8cc7
FR		 4991 dev->stats.rx_bytes += pkt_size;
4992 dev->stats.rx_packets++;
1da177e4 4993 }
6dccd16b
FR		 4994
4995 /* Work around for AMD plateform. */
95e0918d 4996 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4997 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4998 desc->opts2 = 0;
4999 cur_rx++;
5000 }
1da177e4
LT		 5001 }
5002
5003 count = cur_rx - tp->cur_rx;
5004 tp->cur_rx = cur_rx;
5005
6f0333b8 5006 tp->dirty_rx += count;
1da177e4
LT		 5007
5008 return count;
5009}
5010
07d3f51f 5011static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 5012{
07d3f51f 5013 struct net_device *dev = dev_instance;
1da177e4 5014 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 5015 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5016 int handled = 0;
865c652d 5017 int status;
1da177e4 5018
f11a377b
DD		 5019 /* loop handling interrupts until we have no new ones or
5020 * we hit a invalid/hotplug case.
5021 */
865c652d 5022 status = RTL_R16(IntrStatus);
f11a377b
DD		 5023 while (status && status != 0xffff) {
5024 handled = 1;
1da177e4 5025
f11a377b
DD		 5026 /* Handle all of the error cases first. These will reset
5027 * the chip, so just exit the loop.
5028 */
5029 if (unlikely(!netif_running(dev))) {
5030 rtl8169_asic_down(ioaddr);
5031 break;
5032 }
1da177e4 5033
1519e57f
FR		 5034 if (unlikely(status & RxFIFOOver)) {
5035 switch (tp->mac_version) {
5036 /* Work around for rx fifo overflow */
5037 case RTL_GIGA_MAC_VER_11:
5038 case RTL_GIGA_MAC_VER_22:
5039 case RTL_GIGA_MAC_VER_26:
5040 netif_stop_queue(dev);
5041 rtl8169_tx_timeout(dev);
5042 goto done;
f60ac8e7
FR		 5043 /* Testers needed. */
5044 case RTL_GIGA_MAC_VER_17:
5045 case RTL_GIGA_MAC_VER_19:
5046 case RTL_GIGA_MAC_VER_20:
5047 case RTL_GIGA_MAC_VER_21:
5048 case RTL_GIGA_MAC_VER_23:
5049 case RTL_GIGA_MAC_VER_24:
5050 case RTL_GIGA_MAC_VER_27:
5051 case RTL_GIGA_MAC_VER_28:
4804b3b3 5052 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5053 /* Experimental science. Pktgen proof. */
5054 case RTL_GIGA_MAC_VER_12:
5055 case RTL_GIGA_MAC_VER_25:
5056 if (status == RxFIFOOver)
5057 goto done;
5058 break;
5059 default:
5060 break;
5061 }
f11a377b 5062 }
1da177e4 5063
f11a377b
DD		 5064 if (unlikely(status & SYSErr)) {
5065 rtl8169_pcierr_interrupt(dev);
5066 break;
5067 }
1da177e4 5068
f11a377b 5069 if (status & LinkChg)
e4fbce74 5070 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5071
f11a377b
DD		 5072 /* We need to see the lastest version of tp->intr_mask to
5073 * avoid ignoring an MSI interrupt and having to wait for
5074 * another event which may never come.
5075 */
5076 smp_rmb();
5077 if (status & tp->intr_mask & tp->napi_event) {
5078 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5079 tp->intr_mask = ~tp->napi_event;
5080
5081 if (likely(napi_schedule_prep(&tp->napi)))
5082 __napi_schedule(&tp->napi);
bf82c189
JP		 5083 else
5084 netif_info(tp, intr, dev,
5085 "interrupt %04x in poll\n", status);
f11a377b 5086 }
1da177e4 5087
f11a377b
DD		 5088 /* We only get a new MSI interrupt when all active irq
5089 * sources on the chip have been acknowledged. So, ack
5090 * everything we've seen and check if new sources have become
5091 * active to avoid blocking all interrupts from the chip.
5092 */
5093 RTL_W16(IntrStatus,
5094 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5095 status = RTL_R16(IntrStatus);
865c652d 5096 }
1519e57f 5097done:
1da177e4
LT		 5098 return IRQ_RETVAL(handled);
5099}
5100
bea3348e 5101static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5102{
bea3348e
SH		 5103 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5104 struct net_device *dev = tp->dev;
1da177e4 5105 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5106 int work_done;
1da177e4 5107
bea3348e 5108 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5109 rtl8169_tx_interrupt(dev, tp, ioaddr);
5110
bea3348e 5111 if (work_done < budget) {
288379f0 5112 napi_complete(napi);
f11a377b
DD		 5113
5114 /* We need for force the visibility of tp->intr_mask
5115 * for other CPUs, as we can loose an MSI interrupt
5116 * and potentially wait for a retransmit timeout if we don't.
5117 * The posted write to IntrMask is safe, as it will
5118 * eventually make it to the chip and we won't loose anything
5119 * until it does.
1da177e4 5120 */
f11a377b 5121 tp->intr_mask = 0xffff;
4c020a96 5122 wmb();
0e485150 5123 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5124 }
5125
bea3348e 5126 return work_done;
1da177e4 5127}
1da177e4 5128
523a6094
FR		 5129static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5130{
5131 struct rtl8169_private *tp = netdev_priv(dev);
5132
5133 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5134 return;
5135
5136 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5137 RTL_W32(RxMissed, 0);
5138}
5139
1da177e4
LT		 5140static void rtl8169_down(struct net_device *dev)
5141{
5142 struct rtl8169_private *tp = netdev_priv(dev);
5143 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5144
4876cc1e 5145 del_timer_sync(&tp->timer);
1da177e4
LT		 5146
5147 netif_stop_queue(dev);
5148
93dd79e8 5149 napi_disable(&tp->napi);
93dd79e8 5150
1da177e4
LT		 5151 spin_lock_irq(&tp->lock);
5152
5153 rtl8169_asic_down(ioaddr);
323bb685
SG		 5154 /*
5155 * At this point device interrupts can not be enabled in any function,
5156 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5157 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5158 */
523a6094 5159 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5160
5161 spin_unlock_irq(&tp->lock);
5162
5163 synchronize_irq(dev->irq);
5164
1da177e4 5165 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5166 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5167
1da177e4
LT		 5168 rtl8169_tx_clear(tp);
5169
5170 rtl8169_rx_clear(tp);
065c27c1 5171
5172 rtl_pll_power_down(tp);
1da177e4
LT		 5173}
5174
5175static int rtl8169_close(struct net_device *dev)
5176{
5177 struct rtl8169_private *tp = netdev_priv(dev);
5178 struct pci_dev *pdev = tp->pci_dev;
5179
e1759441
RW		 5180 pm_runtime_get_sync(&pdev->dev);
5181
cecb5fd7 5182 /* Update counters before going down */
355423d0
IV		 5183 rtl8169_update_counters(dev);
5184
1da177e4
LT		 5185 rtl8169_down(dev);
5186
5187 free_irq(dev->irq, dev);
5188
82553bb6
SG		 5189 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5190 tp->RxPhyAddr);
5191 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5192 tp->TxPhyAddr);
1da177e4
LT		 5193 tp->TxDescArray = NULL;
5194 tp->RxDescArray = NULL;
5195
e1759441
RW		 5196 pm_runtime_put_sync(&pdev->dev);
5197
1da177e4
LT		 5198 return 0;
5199}
5200
07ce4064 5201static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5202{
5203 struct rtl8169_private *tp = netdev_priv(dev);
5204 void __iomem *ioaddr = tp->mmio_addr;
5205 unsigned long flags;
5206 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5207 int rx_mode;
1da177e4
LT		 5208 u32 tmp = 0;
5209
5210 if (dev->flags & IFF_PROMISC) {
5211 /* Unconditionally log net taps. */
bf82c189 5212 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5213 rx_mode =
5214 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5215 AcceptAllPhys;
5216 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5217 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5218 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5219 /* Too many to filter perfectly -- accept all multicasts. */
5220 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5221 mc_filter[1] = mc_filter[0] = 0xffffffff;
5222 } else {
22bedad3 5223 struct netdev_hw_addr *ha;
07d3f51f 5224
1da177e4
LT		 5225 rx_mode = AcceptBroadcast | AcceptMyPhys;
5226 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5227 netdev_for_each_mc_addr(ha, dev) {
5228 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5229 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5230 rx_mode |= AcceptMulticast;
5231 }
5232 }
5233
5234 spin_lock_irqsave(&tp->lock, flags);
5235
5236 tmp = rtl8169_rx_config | rx_mode |
2b7b4318 5237 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
1da177e4 5238
f887cce8 5239 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5240 u32 data = mc_filter[0];
5241
5242 mc_filter[0] = swab32(mc_filter[1]);
5243 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5244 }
5245
1da177e4 5246 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5247 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5248
57a9f236
FR		 5249 RTL_W32(RxConfig, tmp);
5250
1da177e4
LT		 5251 spin_unlock_irqrestore(&tp->lock, flags);
5252}
5253
5254/**
5255 * rtl8169_get_stats - Get rtl8169 read/write statistics
5256 * @dev: The Ethernet Device to get statistics for
5257 *
5258 * Get TX/RX statistics for rtl8169
5259 */
5260static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5261{
5262 struct rtl8169_private *tp = netdev_priv(dev);
5263 void __iomem *ioaddr = tp->mmio_addr;
5264 unsigned long flags;
5265
5266 if (netif_running(dev)) {
5267 spin_lock_irqsave(&tp->lock, flags);
523a6094 5268 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5269 spin_unlock_irqrestore(&tp->lock, flags);
5270 }
5b0384f4 5271
cebf8cc7 5272 return &dev->stats;
1da177e4
LT		 5273}
5274
861ab440 5275static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5276{
065c27c1 5277 struct rtl8169_private *tp = netdev_priv(dev);
5278
5d06a99f 5279 if (!netif_running(dev))
861ab440 5280 return;
5d06a99f 5281
065c27c1 5282 rtl_pll_power_down(tp);
5283
5d06a99f
FR		 5284 netif_device_detach(dev);
5285 netif_stop_queue(dev);
861ab440
RW		 5286}
5287
5288#ifdef CONFIG_PM
5289
5290static int rtl8169_suspend(struct device *device)
5291{
5292 struct pci_dev *pdev = to_pci_dev(device);
5293 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5294
861ab440 5295 rtl8169_net_suspend(dev);
1371fa6d 5296
5d06a99f
FR		 5297 return 0;
5298}
5299
e1759441
RW		 5300static void __rtl8169_resume(struct net_device *dev)
5301{
065c27c1 5302 struct rtl8169_private *tp = netdev_priv(dev);
5303
e1759441 5304 netif_device_attach(dev);
065c27c1 5305
5306 rtl_pll_power_up(tp);
5307
e1759441
RW		 5308 rtl8169_schedule_work(dev, rtl8169_reset_task);
5309}
5310
861ab440 5311static int rtl8169_resume(struct device *device)
5d06a99f 5312{
861ab440 5313 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5314 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5315 struct rtl8169_private *tp = netdev_priv(dev);
5316
5317 rtl8169_init_phy(dev, tp);
5d06a99f 5318
e1759441
RW		 5319 if (netif_running(dev))
5320 __rtl8169_resume(dev);
5d06a99f 5321
e1759441
RW		 5322 return 0;
5323}
5324
5325static int rtl8169_runtime_suspend(struct device *device)
5326{
5327 struct pci_dev *pdev = to_pci_dev(device);
5328 struct net_device *dev = pci_get_drvdata(pdev);
5329 struct rtl8169_private *tp = netdev_priv(dev);
5330
5331 if (!tp->TxDescArray)
5332 return 0;
5333
5334 spin_lock_irq(&tp->lock);
5335 tp->saved_wolopts = __rtl8169_get_wol(tp);
5336 __rtl8169_set_wol(tp, WAKE_ANY);
5337 spin_unlock_irq(&tp->lock);
5338
5339 rtl8169_net_suspend(dev);
5340
5341 return 0;
5342}
5343
5344static int rtl8169_runtime_resume(struct device *device)
5345{
5346 struct pci_dev *pdev = to_pci_dev(device);
5347 struct net_device *dev = pci_get_drvdata(pdev);
5348 struct rtl8169_private *tp = netdev_priv(dev);
5349
5350 if (!tp->TxDescArray)
5351 return 0;
5352
5353 spin_lock_irq(&tp->lock);
5354 __rtl8169_set_wol(tp, tp->saved_wolopts);
5355 tp->saved_wolopts = 0;
5356 spin_unlock_irq(&tp->lock);
5357
fccec10b
SG		 5358 rtl8169_init_phy(dev, tp);
5359
e1759441 5360 __rtl8169_resume(dev);
5d06a99f 5361
5d06a99f
FR		 5362 return 0;
5363}
5364
e1759441
RW		 5365static int rtl8169_runtime_idle(struct device *device)
5366{
5367 struct pci_dev *pdev = to_pci_dev(device);
5368 struct net_device *dev = pci_get_drvdata(pdev);
5369 struct rtl8169_private *tp = netdev_priv(dev);
5370
e4fbce74 5371 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5372}
5373
47145210 5374static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 5375 .suspend = rtl8169_suspend,
5376 .resume = rtl8169_resume,
5377 .freeze = rtl8169_suspend,
5378 .thaw = rtl8169_resume,
5379 .poweroff = rtl8169_suspend,
5380 .restore = rtl8169_resume,
5381 .runtime_suspend = rtl8169_runtime_suspend,
5382 .runtime_resume = rtl8169_runtime_resume,
5383 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5384};
5385
5386#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5387
5388#else /* !CONFIG_PM */
5389
5390#define RTL8169_PM_OPS NULL
5391
5392#endif /* !CONFIG_PM */
5393
1765f95d
FR		 5394static void rtl_shutdown(struct pci_dev *pdev)
5395{
861ab440 5396 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5397 struct rtl8169_private *tp = netdev_priv(dev);
5398 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5399
5400 rtl8169_net_suspend(dev);
1765f95d 5401
cecb5fd7 5402 /* Restore original MAC address */
cc098dc7
IV		 5403 rtl_rar_set(tp, dev->perm_addr);
5404
4bb3f522 5405 spin_lock_irq(&tp->lock);
5406
5407 rtl8169_asic_down(ioaddr);
5408
5409 spin_unlock_irq(&tp->lock);
5410
861ab440 5411 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 5412 /* WoL fails with some 8168 when the receiver is disabled. */
5413 if (tp->features & RTL_FEATURE_WOL) {
5414 pci_clear_master(pdev);
5415
5416 RTL_W8(ChipCmd, CmdRxEnb);
5417 /* PCI commit */
5418 RTL_R8(ChipCmd);
5419 }
5420
861ab440
RW		 5421 pci_wake_from_d3(pdev, true);
5422 pci_set_power_state(pdev, PCI_D3hot);
5423 }
5424}
5d06a99f 5425
1da177e4
LT		 5426static struct pci_driver rtl8169_pci_driver = {
5427 .name = MODULENAME,
5428 .id_table = rtl8169_pci_tbl,
5429 .probe = rtl8169_init_one,
5430 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5431 .shutdown = rtl_shutdown,
861ab440 5432 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5433};
5434
07d3f51f 5435static int __init rtl8169_init_module(void)
1da177e4 5436{
29917620 5437 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5438}
5439
07d3f51f 5440static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5441{
5442 pci_unregister_driver(&rtl8169_pci_driver);
5443}
5444
5445module_init(rtl8169_init_module);
5446module_exit(rtl8169_cleanup_module);
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