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Commit | Line | Data |
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1da177e4 | 1 | /* |
07d3f51f FR |
2 | * r8169.c: RealTek 8169/8168/8101 ethernet driver. |
3 | * | |
4 | * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw> | |
5 | * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com> | |
6 | * Copyright (c) a lot of people too. Please respect their work. | |
7 | * | |
8 | * See MAINTAINERS file for support contact information. | |
1da177e4 LT |
9 | */ |
10 | ||
11 | #include <linux/module.h> | |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/netdevice.h> | |
15 | #include <linux/etherdevice.h> | |
16 | #include <linux/delay.h> | |
17 | #include <linux/ethtool.h> | |
18 | #include <linux/mii.h> | |
19 | #include <linux/if_vlan.h> | |
20 | #include <linux/crc32.h> | |
21 | #include <linux/in.h> | |
22 | #include <linux/ip.h> | |
23 | #include <linux/tcp.h> | |
24 | #include <linux/init.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | ||
99f252b0 | 27 | #include <asm/system.h> |
1da177e4 LT |
28 | #include <asm/io.h> |
29 | #include <asm/irq.h> | |
30 | ||
865c652d | 31 | #define RTL8169_VERSION "2.3LK-NAPI" |
1da177e4 LT |
32 | #define MODULENAME "r8169" |
33 | #define PFX MODULENAME ": " | |
34 | ||
35 | #ifdef RTL8169_DEBUG | |
36 | #define assert(expr) \ | |
5b0384f4 FR |
37 | if (!(expr)) { \ |
38 | printk( "Assertion failed! %s,%s,%s,line=%d\n", \ | |
b39d66a8 | 39 | #expr,__FILE__,__func__,__LINE__); \ |
5b0384f4 | 40 | } |
06fa7358 JP |
41 | #define dprintk(fmt, args...) \ |
42 | do { printk(KERN_DEBUG PFX fmt, ## args); } while (0) | |
1da177e4 LT |
43 | #else |
44 | #define assert(expr) do {} while (0) | |
45 | #define dprintk(fmt, args...) do {} while (0) | |
46 | #endif /* RTL8169_DEBUG */ | |
47 | ||
b57b7e5a | 48 | #define R8169_MSG_DEFAULT \ |
f0e837d9 | 49 | (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN) |
b57b7e5a | 50 | |
1da177e4 LT |
51 | #define TX_BUFFS_AVAIL(tp) \ |
52 | (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1) | |
53 | ||
1da177e4 | 54 | /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ |
f71e1309 | 55 | static const int max_interrupt_work = 20; |
1da177e4 LT |
56 | |
57 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). | |
58 | The RTL chips use a 64 element hash table based on the Ethernet CRC. */ | |
f71e1309 | 59 | static const int multicast_filter_limit = 32; |
1da177e4 LT |
60 | |
61 | /* MAC address length */ | |
62 | #define MAC_ADDR_LEN 6 | |
63 | ||
9c14ceaf | 64 | #define MAX_READ_REQUEST_SHIFT 12 |
1da177e4 LT |
65 | #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */ |
66 | #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
67 | #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */ | |
07d3f51f | 68 | #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */ |
1da177e4 LT |
69 | #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */ |
70 | #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */ | |
71 | #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */ | |
72 | ||
73 | #define R8169_REGS_SIZE 256 | |
74 | #define R8169_NAPI_WEIGHT 64 | |
75 | #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */ | |
76 | #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */ | |
77 | #define RX_BUF_SIZE 1536 /* Rx Buffer size */ | |
78 | #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc)) | |
79 | #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc)) | |
80 | ||
81 | #define RTL8169_TX_TIMEOUT (6*HZ) | |
82 | #define RTL8169_PHY_TIMEOUT (10*HZ) | |
83 | ||
e1564ec9 FR |
84 | #define RTL_EEPROM_SIG cpu_to_le32(0x8129) |
85 | #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff) | |
86 | #define RTL_EEPROM_SIG_ADDR 0x0000 | |
87 | ||
1da177e4 LT |
88 | /* write/read MMIO register */ |
89 | #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg)) | |
90 | #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg)) | |
91 | #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg)) | |
92 | #define RTL_R8(reg) readb (ioaddr + (reg)) | |
93 | #define RTL_R16(reg) readw (ioaddr + (reg)) | |
94 | #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg))) | |
95 | ||
96 | enum mac_version { | |
ba6eb6ee FR |
97 | RTL_GIGA_MAC_VER_01 = 0x01, // 8169 |
98 | RTL_GIGA_MAC_VER_02 = 0x02, // 8169S | |
99 | RTL_GIGA_MAC_VER_03 = 0x03, // 8110S | |
100 | RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB | |
101 | RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd | |
6dccd16b | 102 | RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe |
2857ffb7 FR |
103 | RTL_GIGA_MAC_VER_07 = 0x07, // 8102e |
104 | RTL_GIGA_MAC_VER_08 = 0x08, // 8102e | |
105 | RTL_GIGA_MAC_VER_09 = 0x09, // 8102e | |
106 | RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e | |
2dd99530 | 107 | RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb |
e3cf0cc0 FR |
108 | RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be |
109 | RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb | |
110 | RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ? | |
111 | RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ? | |
112 | RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec | |
113 | RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf | |
114 | RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP | |
115 | RTL_GIGA_MAC_VER_19 = 0x13, // 8168C | |
197ff761 | 116 | RTL_GIGA_MAC_VER_20 = 0x14, // 8168C |
6fb07058 | 117 | RTL_GIGA_MAC_VER_21 = 0x15, // 8168C |
ef3386f0 | 118 | RTL_GIGA_MAC_VER_22 = 0x16, // 8168C |
7f3e3d3a | 119 | RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP |
5b538df9 FR |
120 | RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP |
121 | RTL_GIGA_MAC_VER_25 = 0x19 // 8168D | |
1da177e4 LT |
122 | }; |
123 | ||
1da177e4 LT |
124 | #define _R(NAME,MAC,MASK) \ |
125 | { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK } | |
126 | ||
3c6bee1d | 127 | static const struct { |
1da177e4 LT |
128 | const char *name; |
129 | u8 mac_version; | |
130 | u32 RxConfigMask; /* Clears the bits supported by this chip */ | |
131 | } rtl_chip_info[] = { | |
ba6eb6ee FR |
132 | _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169 |
133 | _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S | |
134 | _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S | |
135 | _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB | |
136 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd | |
6dccd16b | 137 | _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe |
2857ffb7 FR |
138 | _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E |
139 | _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E | |
140 | _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E | |
141 | _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E | |
bcf0bf90 FR |
142 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E |
143 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E | |
144 | _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139 | |
145 | _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139 | |
e3cf0cc0 FR |
146 | _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139 |
147 | _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E | |
148 | _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E | |
149 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E | |
150 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E | |
197ff761 | 151 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E |
6fb07058 | 152 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E |
ef3386f0 | 153 | _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E |
7f3e3d3a | 154 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E |
5b538df9 FR |
155 | _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E |
156 | _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880) // PCI-E | |
1da177e4 LT |
157 | }; |
158 | #undef _R | |
159 | ||
bcf0bf90 FR |
160 | enum cfg_version { |
161 | RTL_CFG_0 = 0x00, | |
162 | RTL_CFG_1, | |
163 | RTL_CFG_2 | |
164 | }; | |
165 | ||
07ce4064 FR |
166 | static void rtl_hw_start_8169(struct net_device *); |
167 | static void rtl_hw_start_8168(struct net_device *); | |
168 | static void rtl_hw_start_8101(struct net_device *); | |
169 | ||
1da177e4 | 170 | static struct pci_device_id rtl8169_pci_tbl[] = { |
bcf0bf90 | 171 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 }, |
d2eed8cf | 172 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 }, |
d81bf551 | 173 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 }, |
07ce4064 | 174 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 }, |
bcf0bf90 FR |
175 | { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 }, |
176 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 }, | |
bc1660b5 | 177 | { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 }, |
bcf0bf90 FR |
178 | { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 }, |
179 | { PCI_VENDOR_ID_LINKSYS, 0x1032, | |
180 | PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 }, | |
11d2e282 CM |
181 | { 0x0001, 0x8168, |
182 | PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 }, | |
1da177e4 LT |
183 | {0,}, |
184 | }; | |
185 | ||
186 | MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl); | |
187 | ||
188 | static int rx_copybreak = 200; | |
189 | static int use_dac; | |
b57b7e5a SH |
190 | static struct { |
191 | u32 msg_enable; | |
192 | } debug = { -1 }; | |
1da177e4 | 193 | |
07d3f51f FR |
194 | enum rtl_registers { |
195 | MAC0 = 0, /* Ethernet hardware address. */ | |
773d2021 | 196 | MAC4 = 4, |
07d3f51f FR |
197 | MAR0 = 8, /* Multicast filter. */ |
198 | CounterAddrLow = 0x10, | |
199 | CounterAddrHigh = 0x14, | |
200 | TxDescStartAddrLow = 0x20, | |
201 | TxDescStartAddrHigh = 0x24, | |
202 | TxHDescStartAddrLow = 0x28, | |
203 | TxHDescStartAddrHigh = 0x2c, | |
204 | FLASH = 0x30, | |
205 | ERSR = 0x36, | |
206 | ChipCmd = 0x37, | |
207 | TxPoll = 0x38, | |
208 | IntrMask = 0x3c, | |
209 | IntrStatus = 0x3e, | |
210 | TxConfig = 0x40, | |
211 | RxConfig = 0x44, | |
212 | RxMissed = 0x4c, | |
213 | Cfg9346 = 0x50, | |
214 | Config0 = 0x51, | |
215 | Config1 = 0x52, | |
216 | Config2 = 0x53, | |
217 | Config3 = 0x54, | |
218 | Config4 = 0x55, | |
219 | Config5 = 0x56, | |
220 | MultiIntr = 0x5c, | |
221 | PHYAR = 0x60, | |
07d3f51f FR |
222 | PHYstatus = 0x6c, |
223 | RxMaxSize = 0xda, | |
224 | CPlusCmd = 0xe0, | |
225 | IntrMitigate = 0xe2, | |
226 | RxDescAddrLow = 0xe4, | |
227 | RxDescAddrHigh = 0xe8, | |
228 | EarlyTxThres = 0xec, | |
229 | FuncEvent = 0xf0, | |
230 | FuncEventMask = 0xf4, | |
231 | FuncPresetState = 0xf8, | |
232 | FuncForceEvent = 0xfc, | |
1da177e4 LT |
233 | }; |
234 | ||
f162a5d1 FR |
235 | enum rtl8110_registers { |
236 | TBICSR = 0x64, | |
237 | TBI_ANAR = 0x68, | |
238 | TBI_LPAR = 0x6a, | |
239 | }; | |
240 | ||
241 | enum rtl8168_8101_registers { | |
242 | CSIDR = 0x64, | |
243 | CSIAR = 0x68, | |
244 | #define CSIAR_FLAG 0x80000000 | |
245 | #define CSIAR_WRITE_CMD 0x80000000 | |
246 | #define CSIAR_BYTE_ENABLE 0x0f | |
247 | #define CSIAR_BYTE_ENABLE_SHIFT 12 | |
248 | #define CSIAR_ADDR_MASK 0x0fff | |
249 | ||
250 | EPHYAR = 0x80, | |
251 | #define EPHYAR_FLAG 0x80000000 | |
252 | #define EPHYAR_WRITE_CMD 0x80000000 | |
253 | #define EPHYAR_REG_MASK 0x1f | |
254 | #define EPHYAR_REG_SHIFT 16 | |
255 | #define EPHYAR_DATA_MASK 0xffff | |
256 | DBG_REG = 0xd1, | |
257 | #define FIX_NAK_1 (1 << 4) | |
258 | #define FIX_NAK_2 (1 << 3) | |
259 | }; | |
260 | ||
07d3f51f | 261 | enum rtl_register_content { |
1da177e4 | 262 | /* InterruptStatusBits */ |
07d3f51f FR |
263 | SYSErr = 0x8000, |
264 | PCSTimeout = 0x4000, | |
265 | SWInt = 0x0100, | |
266 | TxDescUnavail = 0x0080, | |
267 | RxFIFOOver = 0x0040, | |
268 | LinkChg = 0x0020, | |
269 | RxOverflow = 0x0010, | |
270 | TxErr = 0x0008, | |
271 | TxOK = 0x0004, | |
272 | RxErr = 0x0002, | |
273 | RxOK = 0x0001, | |
1da177e4 LT |
274 | |
275 | /* RxStatusDesc */ | |
9dccf611 FR |
276 | RxFOVF = (1 << 23), |
277 | RxRWT = (1 << 22), | |
278 | RxRES = (1 << 21), | |
279 | RxRUNT = (1 << 20), | |
280 | RxCRC = (1 << 19), | |
1da177e4 LT |
281 | |
282 | /* ChipCmdBits */ | |
07d3f51f FR |
283 | CmdReset = 0x10, |
284 | CmdRxEnb = 0x08, | |
285 | CmdTxEnb = 0x04, | |
286 | RxBufEmpty = 0x01, | |
1da177e4 | 287 | |
275391a4 FR |
288 | /* TXPoll register p.5 */ |
289 | HPQ = 0x80, /* Poll cmd on the high prio queue */ | |
290 | NPQ = 0x40, /* Poll cmd on the low prio queue */ | |
291 | FSWInt = 0x01, /* Forced software interrupt */ | |
292 | ||
1da177e4 | 293 | /* Cfg9346Bits */ |
07d3f51f FR |
294 | Cfg9346_Lock = 0x00, |
295 | Cfg9346_Unlock = 0xc0, | |
1da177e4 LT |
296 | |
297 | /* rx_mode_bits */ | |
07d3f51f FR |
298 | AcceptErr = 0x20, |
299 | AcceptRunt = 0x10, | |
300 | AcceptBroadcast = 0x08, | |
301 | AcceptMulticast = 0x04, | |
302 | AcceptMyPhys = 0x02, | |
303 | AcceptAllPhys = 0x01, | |
1da177e4 LT |
304 | |
305 | /* RxConfigBits */ | |
07d3f51f FR |
306 | RxCfgFIFOShift = 13, |
307 | RxCfgDMAShift = 8, | |
1da177e4 LT |
308 | |
309 | /* TxConfigBits */ | |
310 | TxInterFrameGapShift = 24, | |
311 | TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */ | |
312 | ||
5d06a99f | 313 | /* Config1 register p.24 */ |
f162a5d1 FR |
314 | LEDS1 = (1 << 7), |
315 | LEDS0 = (1 << 6), | |
fbac58fc | 316 | MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */ |
f162a5d1 FR |
317 | Speed_down = (1 << 4), |
318 | MEMMAP = (1 << 3), | |
319 | IOMAP = (1 << 2), | |
320 | VPD = (1 << 1), | |
5d06a99f FR |
321 | PMEnable = (1 << 0), /* Power Management Enable */ |
322 | ||
6dccd16b FR |
323 | /* Config2 register p. 25 */ |
324 | PCI_Clock_66MHz = 0x01, | |
325 | PCI_Clock_33MHz = 0x00, | |
326 | ||
61a4dcc2 FR |
327 | /* Config3 register p.25 */ |
328 | MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */ | |
329 | LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */ | |
f162a5d1 | 330 | Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */ |
61a4dcc2 | 331 | |
5d06a99f | 332 | /* Config5 register p.27 */ |
61a4dcc2 FR |
333 | BWF = (1 << 6), /* Accept Broadcast wakeup frame */ |
334 | MWF = (1 << 5), /* Accept Multicast wakeup frame */ | |
335 | UWF = (1 << 4), /* Accept Unicast wakeup frame */ | |
336 | LanWake = (1 << 1), /* LanWake enable/disable */ | |
5d06a99f FR |
337 | PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */ |
338 | ||
1da177e4 LT |
339 | /* TBICSR p.28 */ |
340 | TBIReset = 0x80000000, | |
341 | TBILoopback = 0x40000000, | |
342 | TBINwEnable = 0x20000000, | |
343 | TBINwRestart = 0x10000000, | |
344 | TBILinkOk = 0x02000000, | |
345 | TBINwComplete = 0x01000000, | |
346 | ||
347 | /* CPlusCmd p.31 */ | |
f162a5d1 FR |
348 | EnableBist = (1 << 15), // 8168 8101 |
349 | Mac_dbgo_oe = (1 << 14), // 8168 8101 | |
350 | Normal_mode = (1 << 13), // unused | |
351 | Force_half_dup = (1 << 12), // 8168 8101 | |
352 | Force_rxflow_en = (1 << 11), // 8168 8101 | |
353 | Force_txflow_en = (1 << 10), // 8168 8101 | |
354 | Cxpl_dbg_sel = (1 << 9), // 8168 8101 | |
355 | ASF = (1 << 8), // 8168 8101 | |
356 | PktCntrDisable = (1 << 7), // 8168 8101 | |
357 | Mac_dbgo_sel = 0x001c, // 8168 | |
1da177e4 LT |
358 | RxVlan = (1 << 6), |
359 | RxChkSum = (1 << 5), | |
360 | PCIDAC = (1 << 4), | |
361 | PCIMulRW = (1 << 3), | |
0e485150 FR |
362 | INTT_0 = 0x0000, // 8168 |
363 | INTT_1 = 0x0001, // 8168 | |
364 | INTT_2 = 0x0002, // 8168 | |
365 | INTT_3 = 0x0003, // 8168 | |
1da177e4 LT |
366 | |
367 | /* rtl8169_PHYstatus */ | |
07d3f51f FR |
368 | TBI_Enable = 0x80, |
369 | TxFlowCtrl = 0x40, | |
370 | RxFlowCtrl = 0x20, | |
371 | _1000bpsF = 0x10, | |
372 | _100bps = 0x08, | |
373 | _10bps = 0x04, | |
374 | LinkStatus = 0x02, | |
375 | FullDup = 0x01, | |
1da177e4 | 376 | |
1da177e4 | 377 | /* _TBICSRBit */ |
07d3f51f | 378 | TBILinkOK = 0x02000000, |
d4a3a0fc SH |
379 | |
380 | /* DumpCounterCommand */ | |
07d3f51f | 381 | CounterDump = 0x8, |
1da177e4 LT |
382 | }; |
383 | ||
07d3f51f | 384 | enum desc_status_bit { |
1da177e4 LT |
385 | DescOwn = (1 << 31), /* Descriptor is owned by NIC */ |
386 | RingEnd = (1 << 30), /* End of descriptor ring */ | |
387 | FirstFrag = (1 << 29), /* First segment of a packet */ | |
388 | LastFrag = (1 << 28), /* Final segment of a packet */ | |
389 | ||
390 | /* Tx private */ | |
391 | LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */ | |
392 | MSSShift = 16, /* MSS value position */ | |
393 | MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */ | |
394 | IPCS = (1 << 18), /* Calculate IP checksum */ | |
395 | UDPCS = (1 << 17), /* Calculate UDP/IP checksum */ | |
396 | TCPCS = (1 << 16), /* Calculate TCP/IP checksum */ | |
397 | TxVlanTag = (1 << 17), /* Add VLAN tag */ | |
398 | ||
399 | /* Rx private */ | |
400 | PID1 = (1 << 18), /* Protocol ID bit 1/2 */ | |
401 | PID0 = (1 << 17), /* Protocol ID bit 2/2 */ | |
402 | ||
403 | #define RxProtoUDP (PID1) | |
404 | #define RxProtoTCP (PID0) | |
405 | #define RxProtoIP (PID1 | PID0) | |
406 | #define RxProtoMask RxProtoIP | |
407 | ||
408 | IPFail = (1 << 16), /* IP checksum failed */ | |
409 | UDPFail = (1 << 15), /* UDP/IP checksum failed */ | |
410 | TCPFail = (1 << 14), /* TCP/IP checksum failed */ | |
411 | RxVlanTag = (1 << 16), /* VLAN tag available */ | |
412 | }; | |
413 | ||
414 | #define RsvdMask 0x3fffc000 | |
415 | ||
416 | struct TxDesc { | |
6cccd6e7 REB |
417 | __le32 opts1; |
418 | __le32 opts2; | |
419 | __le64 addr; | |
1da177e4 LT |
420 | }; |
421 | ||
422 | struct RxDesc { | |
6cccd6e7 REB |
423 | __le32 opts1; |
424 | __le32 opts2; | |
425 | __le64 addr; | |
1da177e4 LT |
426 | }; |
427 | ||
428 | struct ring_info { | |
429 | struct sk_buff *skb; | |
430 | u32 len; | |
431 | u8 __pad[sizeof(void *) - sizeof(u32)]; | |
432 | }; | |
433 | ||
f23e7fda | 434 | enum features { |
ccdffb9a FR |
435 | RTL_FEATURE_WOL = (1 << 0), |
436 | RTL_FEATURE_MSI = (1 << 1), | |
437 | RTL_FEATURE_GMII = (1 << 2), | |
f23e7fda FR |
438 | }; |
439 | ||
1da177e4 LT |
440 | struct rtl8169_private { |
441 | void __iomem *mmio_addr; /* memory map physical address */ | |
442 | struct pci_dev *pci_dev; /* Index of PCI device */ | |
c4028958 | 443 | struct net_device *dev; |
bea3348e | 444 | struct napi_struct napi; |
1da177e4 | 445 | spinlock_t lock; /* spin lock flag */ |
b57b7e5a | 446 | u32 msg_enable; |
1da177e4 LT |
447 | int chipset; |
448 | int mac_version; | |
1da177e4 LT |
449 | u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */ |
450 | u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */ | |
451 | u32 dirty_rx; | |
452 | u32 dirty_tx; | |
453 | struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */ | |
454 | struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */ | |
455 | dma_addr_t TxPhyAddr; | |
456 | dma_addr_t RxPhyAddr; | |
457 | struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */ | |
458 | struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */ | |
bcf0bf90 | 459 | unsigned align; |
1da177e4 LT |
460 | unsigned rx_buf_sz; |
461 | struct timer_list timer; | |
462 | u16 cp_cmd; | |
0e485150 FR |
463 | u16 intr_event; |
464 | u16 napi_event; | |
1da177e4 LT |
465 | u16 intr_mask; |
466 | int phy_auto_nego_reg; | |
467 | int phy_1000_ctrl_reg; | |
468 | #ifdef CONFIG_R8169_VLAN | |
469 | struct vlan_group *vlgrp; | |
470 | #endif | |
471 | int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex); | |
ccdffb9a | 472 | int (*get_settings)(struct net_device *, struct ethtool_cmd *); |
1da177e4 | 473 | void (*phy_reset_enable)(void __iomem *); |
07ce4064 | 474 | void (*hw_start)(struct net_device *); |
1da177e4 LT |
475 | unsigned int (*phy_reset_pending)(void __iomem *); |
476 | unsigned int (*link_ok)(void __iomem *); | |
9c14ceaf | 477 | int pcie_cap; |
c4028958 | 478 | struct delayed_work task; |
f23e7fda | 479 | unsigned features; |
ccdffb9a FR |
480 | |
481 | struct mii_if_info mii; | |
1da177e4 LT |
482 | }; |
483 | ||
979b6c13 | 484 | MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>"); |
1da177e4 | 485 | MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver"); |
1da177e4 | 486 | module_param(rx_copybreak, int, 0); |
1b7efd58 | 487 | MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames"); |
1da177e4 LT |
488 | module_param(use_dac, int, 0); |
489 | MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot."); | |
b57b7e5a SH |
490 | module_param_named(debug, debug.msg_enable, int, 0); |
491 | MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)"); | |
1da177e4 LT |
492 | MODULE_LICENSE("GPL"); |
493 | MODULE_VERSION(RTL8169_VERSION); | |
494 | ||
495 | static int rtl8169_open(struct net_device *dev); | |
496 | static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev); | |
7d12e780 | 497 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance); |
1da177e4 | 498 | static int rtl8169_init_ring(struct net_device *dev); |
07ce4064 | 499 | static void rtl_hw_start(struct net_device *dev); |
1da177e4 | 500 | static int rtl8169_close(struct net_device *dev); |
07ce4064 | 501 | static void rtl_set_rx_mode(struct net_device *dev); |
1da177e4 | 502 | static void rtl8169_tx_timeout(struct net_device *dev); |
4dcb7d33 | 503 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev); |
1da177e4 | 504 | static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *, |
bea3348e | 505 | void __iomem *, u32 budget); |
4dcb7d33 | 506 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu); |
1da177e4 | 507 | static void rtl8169_down(struct net_device *dev); |
99f252b0 | 508 | static void rtl8169_rx_clear(struct rtl8169_private *tp); |
bea3348e | 509 | static int rtl8169_poll(struct napi_struct *napi, int budget); |
1da177e4 | 510 | |
1da177e4 | 511 | static const unsigned int rtl8169_rx_config = |
5b0384f4 | 512 | (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift); |
1da177e4 | 513 | |
07d3f51f | 514 | static void mdio_write(void __iomem *ioaddr, int reg_addr, int value) |
1da177e4 LT |
515 | { |
516 | int i; | |
517 | ||
a6baf3af | 518 | RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff)); |
1da177e4 | 519 | |
2371408c | 520 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
521 | /* |
522 | * Check if the RTL8169 has completed writing to the specified | |
523 | * MII register. | |
524 | */ | |
5b0384f4 | 525 | if (!(RTL_R32(PHYAR) & 0x80000000)) |
1da177e4 | 526 | break; |
2371408c | 527 | udelay(25); |
1da177e4 LT |
528 | } |
529 | } | |
530 | ||
07d3f51f | 531 | static int mdio_read(void __iomem *ioaddr, int reg_addr) |
1da177e4 LT |
532 | { |
533 | int i, value = -1; | |
534 | ||
a6baf3af | 535 | RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16); |
1da177e4 | 536 | |
2371408c | 537 | for (i = 20; i > 0; i--) { |
07d3f51f FR |
538 | /* |
539 | * Check if the RTL8169 has completed retrieving data from | |
540 | * the specified MII register. | |
541 | */ | |
1da177e4 | 542 | if (RTL_R32(PHYAR) & 0x80000000) { |
a6baf3af | 543 | value = RTL_R32(PHYAR) & 0xffff; |
1da177e4 LT |
544 | break; |
545 | } | |
2371408c | 546 | udelay(25); |
1da177e4 LT |
547 | } |
548 | return value; | |
549 | } | |
550 | ||
dacf8154 FR |
551 | static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value) |
552 | { | |
553 | mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value); | |
554 | } | |
555 | ||
ccdffb9a FR |
556 | static void rtl_mdio_write(struct net_device *dev, int phy_id, int location, |
557 | int val) | |
558 | { | |
559 | struct rtl8169_private *tp = netdev_priv(dev); | |
560 | void __iomem *ioaddr = tp->mmio_addr; | |
561 | ||
562 | mdio_write(ioaddr, location, val); | |
563 | } | |
564 | ||
565 | static int rtl_mdio_read(struct net_device *dev, int phy_id, int location) | |
566 | { | |
567 | struct rtl8169_private *tp = netdev_priv(dev); | |
568 | void __iomem *ioaddr = tp->mmio_addr; | |
569 | ||
570 | return mdio_read(ioaddr, location); | |
571 | } | |
572 | ||
dacf8154 FR |
573 | static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value) |
574 | { | |
575 | unsigned int i; | |
576 | ||
577 | RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) | | |
578 | (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
579 | ||
580 | for (i = 0; i < 100; i++) { | |
581 | if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG)) | |
582 | break; | |
583 | udelay(10); | |
584 | } | |
585 | } | |
586 | ||
587 | static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr) | |
588 | { | |
589 | u16 value = 0xffff; | |
590 | unsigned int i; | |
591 | ||
592 | RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT); | |
593 | ||
594 | for (i = 0; i < 100; i++) { | |
595 | if (RTL_R32(EPHYAR) & EPHYAR_FLAG) { | |
596 | value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK; | |
597 | break; | |
598 | } | |
599 | udelay(10); | |
600 | } | |
601 | ||
602 | return value; | |
603 | } | |
604 | ||
605 | static void rtl_csi_write(void __iomem *ioaddr, int addr, int value) | |
606 | { | |
607 | unsigned int i; | |
608 | ||
609 | RTL_W32(CSIDR, value); | |
610 | RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) | | |
611 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
612 | ||
613 | for (i = 0; i < 100; i++) { | |
614 | if (!(RTL_R32(CSIAR) & CSIAR_FLAG)) | |
615 | break; | |
616 | udelay(10); | |
617 | } | |
618 | } | |
619 | ||
620 | static u32 rtl_csi_read(void __iomem *ioaddr, int addr) | |
621 | { | |
622 | u32 value = ~0x00; | |
623 | unsigned int i; | |
624 | ||
625 | RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) | | |
626 | CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT); | |
627 | ||
628 | for (i = 0; i < 100; i++) { | |
629 | if (RTL_R32(CSIAR) & CSIAR_FLAG) { | |
630 | value = RTL_R32(CSIDR); | |
631 | break; | |
632 | } | |
633 | udelay(10); | |
634 | } | |
635 | ||
636 | return value; | |
637 | } | |
638 | ||
1da177e4 LT |
639 | static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr) |
640 | { | |
641 | RTL_W16(IntrMask, 0x0000); | |
642 | ||
643 | RTL_W16(IntrStatus, 0xffff); | |
644 | } | |
645 | ||
646 | static void rtl8169_asic_down(void __iomem *ioaddr) | |
647 | { | |
648 | RTL_W8(ChipCmd, 0x00); | |
649 | rtl8169_irq_mask_and_ack(ioaddr); | |
650 | RTL_R16(CPlusCmd); | |
651 | } | |
652 | ||
653 | static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr) | |
654 | { | |
655 | return RTL_R32(TBICSR) & TBIReset; | |
656 | } | |
657 | ||
658 | static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr) | |
659 | { | |
64e4bfb4 | 660 | return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET; |
1da177e4 LT |
661 | } |
662 | ||
663 | static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr) | |
664 | { | |
665 | return RTL_R32(TBICSR) & TBILinkOk; | |
666 | } | |
667 | ||
668 | static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr) | |
669 | { | |
670 | return RTL_R8(PHYstatus) & LinkStatus; | |
671 | } | |
672 | ||
673 | static void rtl8169_tbi_reset_enable(void __iomem *ioaddr) | |
674 | { | |
675 | RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset); | |
676 | } | |
677 | ||
678 | static void rtl8169_xmii_reset_enable(void __iomem *ioaddr) | |
679 | { | |
680 | unsigned int val; | |
681 | ||
9e0db8ef FR |
682 | val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET; |
683 | mdio_write(ioaddr, MII_BMCR, val & 0xffff); | |
1da177e4 LT |
684 | } |
685 | ||
686 | static void rtl8169_check_link_status(struct net_device *dev, | |
07d3f51f FR |
687 | struct rtl8169_private *tp, |
688 | void __iomem *ioaddr) | |
1da177e4 LT |
689 | { |
690 | unsigned long flags; | |
691 | ||
692 | spin_lock_irqsave(&tp->lock, flags); | |
693 | if (tp->link_ok(ioaddr)) { | |
694 | netif_carrier_on(dev); | |
b57b7e5a SH |
695 | if (netif_msg_ifup(tp)) |
696 | printk(KERN_INFO PFX "%s: link up\n", dev->name); | |
697 | } else { | |
698 | if (netif_msg_ifdown(tp)) | |
699 | printk(KERN_INFO PFX "%s: link down\n", dev->name); | |
1da177e4 | 700 | netif_carrier_off(dev); |
b57b7e5a | 701 | } |
1da177e4 LT |
702 | spin_unlock_irqrestore(&tp->lock, flags); |
703 | } | |
704 | ||
61a4dcc2 FR |
705 | static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
706 | { | |
707 | struct rtl8169_private *tp = netdev_priv(dev); | |
708 | void __iomem *ioaddr = tp->mmio_addr; | |
709 | u8 options; | |
710 | ||
711 | wol->wolopts = 0; | |
712 | ||
713 | #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) | |
714 | wol->supported = WAKE_ANY; | |
715 | ||
716 | spin_lock_irq(&tp->lock); | |
717 | ||
718 | options = RTL_R8(Config1); | |
719 | if (!(options & PMEnable)) | |
720 | goto out_unlock; | |
721 | ||
722 | options = RTL_R8(Config3); | |
723 | if (options & LinkUp) | |
724 | wol->wolopts |= WAKE_PHY; | |
725 | if (options & MagicPacket) | |
726 | wol->wolopts |= WAKE_MAGIC; | |
727 | ||
728 | options = RTL_R8(Config5); | |
729 | if (options & UWF) | |
730 | wol->wolopts |= WAKE_UCAST; | |
731 | if (options & BWF) | |
5b0384f4 | 732 | wol->wolopts |= WAKE_BCAST; |
61a4dcc2 | 733 | if (options & MWF) |
5b0384f4 | 734 | wol->wolopts |= WAKE_MCAST; |
61a4dcc2 FR |
735 | |
736 | out_unlock: | |
737 | spin_unlock_irq(&tp->lock); | |
738 | } | |
739 | ||
740 | static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
741 | { | |
742 | struct rtl8169_private *tp = netdev_priv(dev); | |
743 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 744 | unsigned int i; |
61a4dcc2 FR |
745 | static struct { |
746 | u32 opt; | |
747 | u16 reg; | |
748 | u8 mask; | |
749 | } cfg[] = { | |
750 | { WAKE_ANY, Config1, PMEnable }, | |
751 | { WAKE_PHY, Config3, LinkUp }, | |
752 | { WAKE_MAGIC, Config3, MagicPacket }, | |
753 | { WAKE_UCAST, Config5, UWF }, | |
754 | { WAKE_BCAST, Config5, BWF }, | |
755 | { WAKE_MCAST, Config5, MWF }, | |
756 | { WAKE_ANY, Config5, LanWake } | |
757 | }; | |
758 | ||
759 | spin_lock_irq(&tp->lock); | |
760 | ||
761 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
762 | ||
763 | for (i = 0; i < ARRAY_SIZE(cfg); i++) { | |
764 | u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask; | |
765 | if (wol->wolopts & cfg[i].opt) | |
766 | options |= cfg[i].mask; | |
767 | RTL_W8(cfg[i].reg, options); | |
768 | } | |
769 | ||
770 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
771 | ||
f23e7fda FR |
772 | if (wol->wolopts) |
773 | tp->features |= RTL_FEATURE_WOL; | |
774 | else | |
775 | tp->features &= ~RTL_FEATURE_WOL; | |
8b76ab39 | 776 | device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts); |
61a4dcc2 FR |
777 | |
778 | spin_unlock_irq(&tp->lock); | |
779 | ||
780 | return 0; | |
781 | } | |
782 | ||
1da177e4 LT |
783 | static void rtl8169_get_drvinfo(struct net_device *dev, |
784 | struct ethtool_drvinfo *info) | |
785 | { | |
786 | struct rtl8169_private *tp = netdev_priv(dev); | |
787 | ||
788 | strcpy(info->driver, MODULENAME); | |
789 | strcpy(info->version, RTL8169_VERSION); | |
790 | strcpy(info->bus_info, pci_name(tp->pci_dev)); | |
791 | } | |
792 | ||
793 | static int rtl8169_get_regs_len(struct net_device *dev) | |
794 | { | |
795 | return R8169_REGS_SIZE; | |
796 | } | |
797 | ||
798 | static int rtl8169_set_speed_tbi(struct net_device *dev, | |
799 | u8 autoneg, u16 speed, u8 duplex) | |
800 | { | |
801 | struct rtl8169_private *tp = netdev_priv(dev); | |
802 | void __iomem *ioaddr = tp->mmio_addr; | |
803 | int ret = 0; | |
804 | u32 reg; | |
805 | ||
806 | reg = RTL_R32(TBICSR); | |
807 | if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) && | |
808 | (duplex == DUPLEX_FULL)) { | |
809 | RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart)); | |
810 | } else if (autoneg == AUTONEG_ENABLE) | |
811 | RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart); | |
812 | else { | |
b57b7e5a SH |
813 | if (netif_msg_link(tp)) { |
814 | printk(KERN_WARNING "%s: " | |
815 | "incorrect speed setting refused in TBI mode\n", | |
816 | dev->name); | |
817 | } | |
1da177e4 LT |
818 | ret = -EOPNOTSUPP; |
819 | } | |
820 | ||
821 | return ret; | |
822 | } | |
823 | ||
824 | static int rtl8169_set_speed_xmii(struct net_device *dev, | |
825 | u8 autoneg, u16 speed, u8 duplex) | |
826 | { | |
827 | struct rtl8169_private *tp = netdev_priv(dev); | |
828 | void __iomem *ioaddr = tp->mmio_addr; | |
829 | int auto_nego, giga_ctrl; | |
830 | ||
64e4bfb4 FR |
831 | auto_nego = mdio_read(ioaddr, MII_ADVERTISE); |
832 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | | |
833 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
834 | giga_ctrl = mdio_read(ioaddr, MII_CTRL1000); | |
835 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); | |
1da177e4 LT |
836 | |
837 | if (autoneg == AUTONEG_ENABLE) { | |
64e4bfb4 FR |
838 | auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL | |
839 | ADVERTISE_100HALF | ADVERTISE_100FULL); | |
840 | giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; | |
1da177e4 LT |
841 | } else { |
842 | if (speed == SPEED_10) | |
64e4bfb4 | 843 | auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL; |
1da177e4 | 844 | else if (speed == SPEED_100) |
64e4bfb4 | 845 | auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL; |
1da177e4 | 846 | else if (speed == SPEED_1000) |
64e4bfb4 | 847 | giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; |
1da177e4 LT |
848 | |
849 | if (duplex == DUPLEX_HALF) | |
64e4bfb4 | 850 | auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL); |
726ecdcf AG |
851 | |
852 | if (duplex == DUPLEX_FULL) | |
64e4bfb4 | 853 | auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF); |
bcf0bf90 FR |
854 | |
855 | /* This tweak comes straight from Realtek's driver. */ | |
856 | if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) && | |
e3cf0cc0 FR |
857 | ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
858 | (tp->mac_version == RTL_GIGA_MAC_VER_16))) { | |
64e4bfb4 | 859 | auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA; |
bcf0bf90 FR |
860 | } |
861 | } | |
862 | ||
2857ffb7 FR |
863 | /* The 8100e/8101e/8102e do Fast Ethernet only. */ |
864 | if ((tp->mac_version == RTL_GIGA_MAC_VER_07) || | |
865 | (tp->mac_version == RTL_GIGA_MAC_VER_08) || | |
866 | (tp->mac_version == RTL_GIGA_MAC_VER_09) || | |
867 | (tp->mac_version == RTL_GIGA_MAC_VER_10) || | |
868 | (tp->mac_version == RTL_GIGA_MAC_VER_13) || | |
bcf0bf90 | 869 | (tp->mac_version == RTL_GIGA_MAC_VER_14) || |
e3cf0cc0 FR |
870 | (tp->mac_version == RTL_GIGA_MAC_VER_15) || |
871 | (tp->mac_version == RTL_GIGA_MAC_VER_16)) { | |
64e4bfb4 | 872 | if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) && |
bcf0bf90 FR |
873 | netif_msg_link(tp)) { |
874 | printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n", | |
875 | dev->name); | |
876 | } | |
64e4bfb4 | 877 | giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); |
1da177e4 LT |
878 | } |
879 | ||
623a1593 FR |
880 | auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; |
881 | ||
a2de6b89 FR |
882 | if ((tp->mac_version == RTL_GIGA_MAC_VER_11) || |
883 | (tp->mac_version == RTL_GIGA_MAC_VER_12) || | |
884 | (tp->mac_version >= RTL_GIGA_MAC_VER_17)) { | |
885 | /* | |
886 | * Wake up the PHY. | |
887 | * Vendor specific (0x1f) and reserved (0x0e) MII registers. | |
888 | */ | |
2584fbc3 RS |
889 | mdio_write(ioaddr, 0x1f, 0x0000); |
890 | mdio_write(ioaddr, 0x0e, 0x0000); | |
891 | } | |
892 | ||
1da177e4 LT |
893 | tp->phy_auto_nego_reg = auto_nego; |
894 | tp->phy_1000_ctrl_reg = giga_ctrl; | |
895 | ||
64e4bfb4 FR |
896 | mdio_write(ioaddr, MII_ADVERTISE, auto_nego); |
897 | mdio_write(ioaddr, MII_CTRL1000, giga_ctrl); | |
898 | mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART); | |
1da177e4 LT |
899 | return 0; |
900 | } | |
901 | ||
902 | static int rtl8169_set_speed(struct net_device *dev, | |
903 | u8 autoneg, u16 speed, u8 duplex) | |
904 | { | |
905 | struct rtl8169_private *tp = netdev_priv(dev); | |
906 | int ret; | |
907 | ||
908 | ret = tp->set_speed(dev, autoneg, speed, duplex); | |
909 | ||
64e4bfb4 | 910 | if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
1da177e4 LT |
911 | mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT); |
912 | ||
913 | return ret; | |
914 | } | |
915 | ||
916 | static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
917 | { | |
918 | struct rtl8169_private *tp = netdev_priv(dev); | |
919 | unsigned long flags; | |
920 | int ret; | |
921 | ||
922 | spin_lock_irqsave(&tp->lock, flags); | |
923 | ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex); | |
924 | spin_unlock_irqrestore(&tp->lock, flags); | |
5b0384f4 | 925 | |
1da177e4 LT |
926 | return ret; |
927 | } | |
928 | ||
929 | static u32 rtl8169_get_rx_csum(struct net_device *dev) | |
930 | { | |
931 | struct rtl8169_private *tp = netdev_priv(dev); | |
932 | ||
933 | return tp->cp_cmd & RxChkSum; | |
934 | } | |
935 | ||
936 | static int rtl8169_set_rx_csum(struct net_device *dev, u32 data) | |
937 | { | |
938 | struct rtl8169_private *tp = netdev_priv(dev); | |
939 | void __iomem *ioaddr = tp->mmio_addr; | |
940 | unsigned long flags; | |
941 | ||
942 | spin_lock_irqsave(&tp->lock, flags); | |
943 | ||
944 | if (data) | |
945 | tp->cp_cmd |= RxChkSum; | |
946 | else | |
947 | tp->cp_cmd &= ~RxChkSum; | |
948 | ||
949 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
950 | RTL_R16(CPlusCmd); | |
951 | ||
952 | spin_unlock_irqrestore(&tp->lock, flags); | |
953 | ||
954 | return 0; | |
955 | } | |
956 | ||
957 | #ifdef CONFIG_R8169_VLAN | |
958 | ||
959 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, | |
960 | struct sk_buff *skb) | |
961 | { | |
962 | return (tp->vlgrp && vlan_tx_tag_present(skb)) ? | |
963 | TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00; | |
964 | } | |
965 | ||
966 | static void rtl8169_vlan_rx_register(struct net_device *dev, | |
967 | struct vlan_group *grp) | |
968 | { | |
969 | struct rtl8169_private *tp = netdev_priv(dev); | |
970 | void __iomem *ioaddr = tp->mmio_addr; | |
971 | unsigned long flags; | |
972 | ||
973 | spin_lock_irqsave(&tp->lock, flags); | |
974 | tp->vlgrp = grp; | |
975 | if (tp->vlgrp) | |
976 | tp->cp_cmd |= RxVlan; | |
977 | else | |
978 | tp->cp_cmd &= ~RxVlan; | |
979 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
980 | RTL_R16(CPlusCmd); | |
981 | spin_unlock_irqrestore(&tp->lock, flags); | |
982 | } | |
983 | ||
1da177e4 LT |
984 | static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, |
985 | struct sk_buff *skb) | |
986 | { | |
987 | u32 opts2 = le32_to_cpu(desc->opts2); | |
865c652d | 988 | struct vlan_group *vlgrp = tp->vlgrp; |
1da177e4 LT |
989 | int ret; |
990 | ||
865c652d FR |
991 | if (vlgrp && (opts2 & RxVlanTag)) { |
992 | vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff)); | |
1da177e4 LT |
993 | ret = 0; |
994 | } else | |
995 | ret = -1; | |
996 | desc->opts2 = 0; | |
997 | return ret; | |
998 | } | |
999 | ||
1000 | #else /* !CONFIG_R8169_VLAN */ | |
1001 | ||
1002 | static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp, | |
1003 | struct sk_buff *skb) | |
1004 | { | |
1005 | return 0; | |
1006 | } | |
1007 | ||
1008 | static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc, | |
1009 | struct sk_buff *skb) | |
1010 | { | |
1011 | return -1; | |
1012 | } | |
1013 | ||
1014 | #endif | |
1015 | ||
ccdffb9a | 1016 | static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1017 | { |
1018 | struct rtl8169_private *tp = netdev_priv(dev); | |
1019 | void __iomem *ioaddr = tp->mmio_addr; | |
1020 | u32 status; | |
1021 | ||
1022 | cmd->supported = | |
1023 | SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE; | |
1024 | cmd->port = PORT_FIBRE; | |
1025 | cmd->transceiver = XCVR_INTERNAL; | |
1026 | ||
1027 | status = RTL_R32(TBICSR); | |
1028 | cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0; | |
1029 | cmd->autoneg = !!(status & TBINwEnable); | |
1030 | ||
1031 | cmd->speed = SPEED_1000; | |
1032 | cmd->duplex = DUPLEX_FULL; /* Always set */ | |
ccdffb9a FR |
1033 | |
1034 | return 0; | |
1da177e4 LT |
1035 | } |
1036 | ||
ccdffb9a | 1037 | static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd) |
1da177e4 LT |
1038 | { |
1039 | struct rtl8169_private *tp = netdev_priv(dev); | |
ccdffb9a FR |
1040 | |
1041 | return mii_ethtool_gset(&tp->mii, cmd); | |
1da177e4 LT |
1042 | } |
1043 | ||
1044 | static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |
1045 | { | |
1046 | struct rtl8169_private *tp = netdev_priv(dev); | |
1047 | unsigned long flags; | |
ccdffb9a | 1048 | int rc; |
1da177e4 LT |
1049 | |
1050 | spin_lock_irqsave(&tp->lock, flags); | |
1051 | ||
ccdffb9a | 1052 | rc = tp->get_settings(dev, cmd); |
1da177e4 LT |
1053 | |
1054 | spin_unlock_irqrestore(&tp->lock, flags); | |
ccdffb9a | 1055 | return rc; |
1da177e4 LT |
1056 | } |
1057 | ||
1058 | static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
1059 | void *p) | |
1060 | { | |
5b0384f4 FR |
1061 | struct rtl8169_private *tp = netdev_priv(dev); |
1062 | unsigned long flags; | |
1da177e4 | 1063 | |
5b0384f4 FR |
1064 | if (regs->len > R8169_REGS_SIZE) |
1065 | regs->len = R8169_REGS_SIZE; | |
1da177e4 | 1066 | |
5b0384f4 FR |
1067 | spin_lock_irqsave(&tp->lock, flags); |
1068 | memcpy_fromio(p, tp->mmio_addr, regs->len); | |
1069 | spin_unlock_irqrestore(&tp->lock, flags); | |
1da177e4 LT |
1070 | } |
1071 | ||
b57b7e5a SH |
1072 | static u32 rtl8169_get_msglevel(struct net_device *dev) |
1073 | { | |
1074 | struct rtl8169_private *tp = netdev_priv(dev); | |
1075 | ||
1076 | return tp->msg_enable; | |
1077 | } | |
1078 | ||
1079 | static void rtl8169_set_msglevel(struct net_device *dev, u32 value) | |
1080 | { | |
1081 | struct rtl8169_private *tp = netdev_priv(dev); | |
1082 | ||
1083 | tp->msg_enable = value; | |
1084 | } | |
1085 | ||
d4a3a0fc SH |
1086 | static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = { |
1087 | "tx_packets", | |
1088 | "rx_packets", | |
1089 | "tx_errors", | |
1090 | "rx_errors", | |
1091 | "rx_missed", | |
1092 | "align_errors", | |
1093 | "tx_single_collisions", | |
1094 | "tx_multi_collisions", | |
1095 | "unicast", | |
1096 | "broadcast", | |
1097 | "multicast", | |
1098 | "tx_aborted", | |
1099 | "tx_underrun", | |
1100 | }; | |
1101 | ||
1102 | struct rtl8169_counters { | |
b1eab701 AV |
1103 | __le64 tx_packets; |
1104 | __le64 rx_packets; | |
1105 | __le64 tx_errors; | |
1106 | __le32 rx_errors; | |
1107 | __le16 rx_missed; | |
1108 | __le16 align_errors; | |
1109 | __le32 tx_one_collision; | |
1110 | __le32 tx_multi_collision; | |
1111 | __le64 rx_unicast; | |
1112 | __le64 rx_broadcast; | |
1113 | __le32 rx_multicast; | |
1114 | __le16 tx_aborted; | |
1115 | __le16 tx_underun; | |
d4a3a0fc SH |
1116 | }; |
1117 | ||
b9f2c044 | 1118 | static int rtl8169_get_sset_count(struct net_device *dev, int sset) |
d4a3a0fc | 1119 | { |
b9f2c044 JG |
1120 | switch (sset) { |
1121 | case ETH_SS_STATS: | |
1122 | return ARRAY_SIZE(rtl8169_gstrings); | |
1123 | default: | |
1124 | return -EOPNOTSUPP; | |
1125 | } | |
d4a3a0fc SH |
1126 | } |
1127 | ||
1128 | static void rtl8169_get_ethtool_stats(struct net_device *dev, | |
1129 | struct ethtool_stats *stats, u64 *data) | |
1130 | { | |
1131 | struct rtl8169_private *tp = netdev_priv(dev); | |
1132 | void __iomem *ioaddr = tp->mmio_addr; | |
1133 | struct rtl8169_counters *counters; | |
1134 | dma_addr_t paddr; | |
1135 | u32 cmd; | |
1136 | ||
1137 | ASSERT_RTNL(); | |
1138 | ||
1139 | counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr); | |
1140 | if (!counters) | |
1141 | return; | |
1142 | ||
1143 | RTL_W32(CounterAddrHigh, (u64)paddr >> 32); | |
1144 | cmd = (u64)paddr & DMA_32BIT_MASK; | |
1145 | RTL_W32(CounterAddrLow, cmd); | |
1146 | RTL_W32(CounterAddrLow, cmd | CounterDump); | |
1147 | ||
1148 | while (RTL_R32(CounterAddrLow) & CounterDump) { | |
1149 | if (msleep_interruptible(1)) | |
1150 | break; | |
1151 | } | |
1152 | ||
1153 | RTL_W32(CounterAddrLow, 0); | |
1154 | RTL_W32(CounterAddrHigh, 0); | |
1155 | ||
5b0384f4 | 1156 | data[0] = le64_to_cpu(counters->tx_packets); |
d4a3a0fc SH |
1157 | data[1] = le64_to_cpu(counters->rx_packets); |
1158 | data[2] = le64_to_cpu(counters->tx_errors); | |
1159 | data[3] = le32_to_cpu(counters->rx_errors); | |
1160 | data[4] = le16_to_cpu(counters->rx_missed); | |
1161 | data[5] = le16_to_cpu(counters->align_errors); | |
1162 | data[6] = le32_to_cpu(counters->tx_one_collision); | |
1163 | data[7] = le32_to_cpu(counters->tx_multi_collision); | |
1164 | data[8] = le64_to_cpu(counters->rx_unicast); | |
1165 | data[9] = le64_to_cpu(counters->rx_broadcast); | |
1166 | data[10] = le32_to_cpu(counters->rx_multicast); | |
1167 | data[11] = le16_to_cpu(counters->tx_aborted); | |
1168 | data[12] = le16_to_cpu(counters->tx_underun); | |
1169 | ||
1170 | pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr); | |
1171 | } | |
1172 | ||
1173 | static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
1174 | { | |
1175 | switch(stringset) { | |
1176 | case ETH_SS_STATS: | |
1177 | memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings)); | |
1178 | break; | |
1179 | } | |
1180 | } | |
1181 | ||
7282d491 | 1182 | static const struct ethtool_ops rtl8169_ethtool_ops = { |
1da177e4 LT |
1183 | .get_drvinfo = rtl8169_get_drvinfo, |
1184 | .get_regs_len = rtl8169_get_regs_len, | |
1185 | .get_link = ethtool_op_get_link, | |
1186 | .get_settings = rtl8169_get_settings, | |
1187 | .set_settings = rtl8169_set_settings, | |
b57b7e5a SH |
1188 | .get_msglevel = rtl8169_get_msglevel, |
1189 | .set_msglevel = rtl8169_set_msglevel, | |
1da177e4 LT |
1190 | .get_rx_csum = rtl8169_get_rx_csum, |
1191 | .set_rx_csum = rtl8169_set_rx_csum, | |
1da177e4 | 1192 | .set_tx_csum = ethtool_op_set_tx_csum, |
1da177e4 | 1193 | .set_sg = ethtool_op_set_sg, |
1da177e4 LT |
1194 | .set_tso = ethtool_op_set_tso, |
1195 | .get_regs = rtl8169_get_regs, | |
61a4dcc2 FR |
1196 | .get_wol = rtl8169_get_wol, |
1197 | .set_wol = rtl8169_set_wol, | |
d4a3a0fc | 1198 | .get_strings = rtl8169_get_strings, |
b9f2c044 | 1199 | .get_sset_count = rtl8169_get_sset_count, |
d4a3a0fc | 1200 | .get_ethtool_stats = rtl8169_get_ethtool_stats, |
1da177e4 LT |
1201 | }; |
1202 | ||
07d3f51f FR |
1203 | static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, |
1204 | int bitnum, int bitval) | |
1da177e4 LT |
1205 | { |
1206 | int val; | |
1207 | ||
1208 | val = mdio_read(ioaddr, reg); | |
1209 | val = (bitval == 1) ? | |
1210 | val | (bitval << bitnum) : val & ~(0x0001 << bitnum); | |
5b0384f4 | 1211 | mdio_write(ioaddr, reg, val & 0xffff); |
1da177e4 LT |
1212 | } |
1213 | ||
07d3f51f FR |
1214 | static void rtl8169_get_mac_version(struct rtl8169_private *tp, |
1215 | void __iomem *ioaddr) | |
1da177e4 | 1216 | { |
0e485150 FR |
1217 | /* |
1218 | * The driver currently handles the 8168Bf and the 8168Be identically | |
1219 | * but they can be identified more specifically through the test below | |
1220 | * if needed: | |
1221 | * | |
1222 | * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be | |
0127215c FR |
1223 | * |
1224 | * Same thing for the 8101Eb and the 8101Ec: | |
1225 | * | |
1226 | * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec | |
0e485150 | 1227 | */ |
1da177e4 LT |
1228 | const struct { |
1229 | u32 mask; | |
e3cf0cc0 | 1230 | u32 val; |
1da177e4 LT |
1231 | int mac_version; |
1232 | } mac_info[] = { | |
5b538df9 FR |
1233 | /* 8168D family. */ |
1234 | { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_25 }, | |
1235 | ||
ef808d50 | 1236 | /* 8168C family. */ |
7f3e3d3a | 1237 | { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 }, |
ef3386f0 | 1238 | { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 }, |
ef808d50 | 1239 | { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 }, |
7f3e3d3a | 1240 | { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 }, |
e3cf0cc0 FR |
1241 | { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 }, |
1242 | { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 }, | |
197ff761 | 1243 | { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 }, |
6fb07058 | 1244 | { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 }, |
ef808d50 | 1245 | { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 }, |
e3cf0cc0 FR |
1246 | |
1247 | /* 8168B family. */ | |
1248 | { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 }, | |
1249 | { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 }, | |
1250 | { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 }, | |
1251 | { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 }, | |
1252 | ||
1253 | /* 8101 family. */ | |
2857ffb7 FR |
1254 | { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 }, |
1255 | { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 }, | |
1256 | { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 }, | |
1257 | { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 }, | |
1258 | { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 }, | |
1259 | { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 }, | |
e3cf0cc0 | 1260 | { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 }, |
2857ffb7 | 1261 | { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 }, |
e3cf0cc0 | 1262 | { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 }, |
2857ffb7 FR |
1263 | { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 }, |
1264 | { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 }, | |
e3cf0cc0 FR |
1265 | { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 }, |
1266 | /* FIXME: where did these entries come from ? -- FR */ | |
1267 | { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 }, | |
1268 | { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 }, | |
1269 | ||
1270 | /* 8110 family. */ | |
1271 | { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 }, | |
1272 | { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 }, | |
1273 | { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 }, | |
1274 | { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 }, | |
1275 | { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 }, | |
1276 | { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 }, | |
1277 | ||
1278 | { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */ | |
1da177e4 LT |
1279 | }, *p = mac_info; |
1280 | u32 reg; | |
1281 | ||
e3cf0cc0 FR |
1282 | reg = RTL_R32(TxConfig); |
1283 | while ((reg & p->mask) != p->val) | |
1da177e4 LT |
1284 | p++; |
1285 | tp->mac_version = p->mac_version; | |
e3cf0cc0 FR |
1286 | |
1287 | if (p->mask == 0x00000000) { | |
1288 | struct pci_dev *pdev = tp->pci_dev; | |
1289 | ||
1290 | dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg); | |
1291 | } | |
1da177e4 LT |
1292 | } |
1293 | ||
1294 | static void rtl8169_print_mac_version(struct rtl8169_private *tp) | |
1295 | { | |
bcf0bf90 | 1296 | dprintk("mac_version = 0x%02x\n", tp->mac_version); |
1da177e4 LT |
1297 | } |
1298 | ||
867763c1 FR |
1299 | struct phy_reg { |
1300 | u16 reg; | |
1301 | u16 val; | |
1302 | }; | |
1303 | ||
1304 | static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len) | |
1305 | { | |
1306 | while (len-- > 0) { | |
1307 | mdio_write(ioaddr, regs->reg, regs->val); | |
1308 | regs++; | |
1309 | } | |
1310 | } | |
1311 | ||
5615d9f1 | 1312 | static void rtl8169s_hw_phy_config(void __iomem *ioaddr) |
1da177e4 | 1313 | { |
1da177e4 LT |
1314 | struct { |
1315 | u16 regs[5]; /* Beware of bit-sign propagation */ | |
1316 | } phy_magic[5] = { { | |
1317 | { 0x0000, //w 4 15 12 0 | |
1318 | 0x00a1, //w 3 15 0 00a1 | |
1319 | 0x0008, //w 2 15 0 0008 | |
1320 | 0x1020, //w 1 15 0 1020 | |
1321 | 0x1000 } },{ //w 0 15 0 1000 | |
1322 | { 0x7000, //w 4 15 12 7 | |
1323 | 0xff41, //w 3 15 0 ff41 | |
1324 | 0xde60, //w 2 15 0 de60 | |
1325 | 0x0140, //w 1 15 0 0140 | |
1326 | 0x0077 } },{ //w 0 15 0 0077 | |
1327 | { 0xa000, //w 4 15 12 a | |
1328 | 0xdf01, //w 3 15 0 df01 | |
1329 | 0xdf20, //w 2 15 0 df20 | |
1330 | 0xff95, //w 1 15 0 ff95 | |
1331 | 0xfa00 } },{ //w 0 15 0 fa00 | |
1332 | { 0xb000, //w 4 15 12 b | |
1333 | 0xff41, //w 3 15 0 ff41 | |
1334 | 0xde20, //w 2 15 0 de20 | |
1335 | 0x0140, //w 1 15 0 0140 | |
1336 | 0x00bb } },{ //w 0 15 0 00bb | |
1337 | { 0xf000, //w 4 15 12 f | |
1338 | 0xdf01, //w 3 15 0 df01 | |
1339 | 0xdf20, //w 2 15 0 df20 | |
1340 | 0xff95, //w 1 15 0 ff95 | |
1341 | 0xbf00 } //w 0 15 0 bf00 | |
1342 | } | |
1343 | }, *p = phy_magic; | |
07d3f51f | 1344 | unsigned int i; |
1da177e4 | 1345 | |
a441d7b6 FR |
1346 | mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1 |
1347 | mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000 | |
1348 | mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7 | |
1da177e4 LT |
1349 | rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 |
1350 | ||
1351 | for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) { | |
1352 | int val, pos = 4; | |
1353 | ||
1354 | val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff); | |
1355 | mdio_write(ioaddr, pos, val); | |
1356 | while (--pos >= 0) | |
1357 | mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff); | |
1358 | rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1 | |
1359 | rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0 | |
1360 | } | |
a441d7b6 | 1361 | mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0 |
1da177e4 LT |
1362 | } |
1363 | ||
5615d9f1 FR |
1364 | static void rtl8169sb_hw_phy_config(void __iomem *ioaddr) |
1365 | { | |
a441d7b6 FR |
1366 | struct phy_reg phy_reg_init[] = { |
1367 | { 0x1f, 0x0002 }, | |
1368 | { 0x01, 0x90d0 }, | |
1369 | { 0x1f, 0x0000 } | |
1370 | }; | |
1371 | ||
1372 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
5615d9f1 FR |
1373 | } |
1374 | ||
236b8082 FR |
1375 | static void rtl8168bb_hw_phy_config(void __iomem *ioaddr) |
1376 | { | |
1377 | struct phy_reg phy_reg_init[] = { | |
1378 | { 0x10, 0xf41b }, | |
1379 | { 0x1f, 0x0000 } | |
1380 | }; | |
1381 | ||
1382 | mdio_write(ioaddr, 0x1f, 0x0001); | |
1383 | mdio_patch(ioaddr, 0x16, 1 << 0); | |
1384 | ||
1385 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1386 | } | |
1387 | ||
1388 | static void rtl8168bef_hw_phy_config(void __iomem *ioaddr) | |
1389 | { | |
1390 | struct phy_reg phy_reg_init[] = { | |
1391 | { 0x1f, 0x0001 }, | |
1392 | { 0x10, 0xf41b }, | |
1393 | { 0x1f, 0x0000 } | |
1394 | }; | |
1395 | ||
1396 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1397 | } | |
1398 | ||
ef3386f0 | 1399 | static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr) |
867763c1 FR |
1400 | { |
1401 | struct phy_reg phy_reg_init[] = { | |
1402 | { 0x1f, 0x0000 }, | |
1403 | { 0x1d, 0x0f00 }, | |
1404 | { 0x1f, 0x0002 }, | |
1405 | { 0x0c, 0x1ec8 }, | |
1406 | { 0x1f, 0x0000 } | |
1407 | }; | |
1408 | ||
1409 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1410 | } | |
1411 | ||
ef3386f0 FR |
1412 | static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr) |
1413 | { | |
1414 | struct phy_reg phy_reg_init[] = { | |
1415 | { 0x1f, 0x0001 }, | |
1416 | { 0x1d, 0x3d98 }, | |
1417 | { 0x1f, 0x0000 } | |
1418 | }; | |
1419 | ||
1420 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1421 | mdio_patch(ioaddr, 0x14, 1 << 5); | |
1422 | mdio_patch(ioaddr, 0x0d, 1 << 5); | |
1423 | ||
1424 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1425 | } | |
1426 | ||
219a1e9d | 1427 | static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr) |
867763c1 FR |
1428 | { |
1429 | struct phy_reg phy_reg_init[] = { | |
a3f80671 FR |
1430 | { 0x1f, 0x0001 }, |
1431 | { 0x12, 0x2300 }, | |
867763c1 FR |
1432 | { 0x1f, 0x0002 }, |
1433 | { 0x00, 0x88d4 }, | |
1434 | { 0x01, 0x82b1 }, | |
1435 | { 0x03, 0x7002 }, | |
1436 | { 0x08, 0x9e30 }, | |
1437 | { 0x09, 0x01f0 }, | |
1438 | { 0x0a, 0x5500 }, | |
1439 | { 0x0c, 0x00c8 }, | |
1440 | { 0x1f, 0x0003 }, | |
1441 | { 0x12, 0xc096 }, | |
1442 | { 0x16, 0x000a }, | |
f50d4275 FR |
1443 | { 0x1f, 0x0000 }, |
1444 | { 0x1f, 0x0000 }, | |
1445 | { 0x09, 0x2000 }, | |
1446 | { 0x09, 0x0000 } | |
867763c1 FR |
1447 | }; |
1448 | ||
1449 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
f50d4275 FR |
1450 | |
1451 | mdio_patch(ioaddr, 0x14, 1 << 5); | |
1452 | mdio_patch(ioaddr, 0x0d, 1 << 5); | |
1453 | mdio_write(ioaddr, 0x1f, 0x0000); | |
867763c1 FR |
1454 | } |
1455 | ||
219a1e9d | 1456 | static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr) |
7da97ec9 FR |
1457 | { |
1458 | struct phy_reg phy_reg_init[] = { | |
f50d4275 | 1459 | { 0x1f, 0x0001 }, |
7da97ec9 | 1460 | { 0x12, 0x2300 }, |
f50d4275 FR |
1461 | { 0x03, 0x802f }, |
1462 | { 0x02, 0x4f02 }, | |
1463 | { 0x01, 0x0409 }, | |
1464 | { 0x00, 0xf099 }, | |
1465 | { 0x04, 0x9800 }, | |
1466 | { 0x04, 0x9000 }, | |
1467 | { 0x1d, 0x3d98 }, | |
7da97ec9 FR |
1468 | { 0x1f, 0x0002 }, |
1469 | { 0x0c, 0x7eb8 }, | |
f50d4275 FR |
1470 | { 0x06, 0x0761 }, |
1471 | { 0x1f, 0x0003 }, | |
1472 | { 0x16, 0x0f0a }, | |
7da97ec9 FR |
1473 | { 0x1f, 0x0000 } |
1474 | }; | |
1475 | ||
1476 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
f50d4275 FR |
1477 | |
1478 | mdio_patch(ioaddr, 0x16, 1 << 0); | |
1479 | mdio_patch(ioaddr, 0x14, 1 << 5); | |
1480 | mdio_patch(ioaddr, 0x0d, 1 << 5); | |
1481 | mdio_write(ioaddr, 0x1f, 0x0000); | |
7da97ec9 FR |
1482 | } |
1483 | ||
197ff761 FR |
1484 | static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr) |
1485 | { | |
1486 | struct phy_reg phy_reg_init[] = { | |
1487 | { 0x1f, 0x0001 }, | |
1488 | { 0x12, 0x2300 }, | |
1489 | { 0x1d, 0x3d98 }, | |
1490 | { 0x1f, 0x0002 }, | |
1491 | { 0x0c, 0x7eb8 }, | |
1492 | { 0x06, 0x5461 }, | |
1493 | { 0x1f, 0x0003 }, | |
1494 | { 0x16, 0x0f0a }, | |
1495 | { 0x1f, 0x0000 } | |
1496 | }; | |
1497 | ||
1498 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1499 | ||
1500 | mdio_patch(ioaddr, 0x16, 1 << 0); | |
1501 | mdio_patch(ioaddr, 0x14, 1 << 5); | |
1502 | mdio_patch(ioaddr, 0x0d, 1 << 5); | |
1503 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1504 | } | |
1505 | ||
6fb07058 FR |
1506 | static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr) |
1507 | { | |
1508 | rtl8168c_3_hw_phy_config(ioaddr); | |
1509 | } | |
1510 | ||
5b538df9 FR |
1511 | static void rtl8168d_hw_phy_config(void __iomem *ioaddr) |
1512 | { | |
1513 | struct phy_reg phy_reg_init_0[] = { | |
1514 | { 0x1f, 0x0001 }, | |
1515 | { 0x09, 0x2770 }, | |
1516 | { 0x08, 0x04d0 }, | |
1517 | { 0x0b, 0xad15 }, | |
1518 | { 0x0c, 0x5bf0 }, | |
1519 | { 0x1c, 0xf101 }, | |
1520 | { 0x1f, 0x0003 }, | |
1521 | { 0x14, 0x94d7 }, | |
1522 | { 0x12, 0xf4d6 }, | |
1523 | { 0x09, 0xca0f }, | |
1524 | { 0x1f, 0x0002 }, | |
1525 | { 0x0b, 0x0b10 }, | |
1526 | { 0x0c, 0xd1f7 }, | |
1527 | { 0x1f, 0x0002 }, | |
1528 | { 0x06, 0x5461 }, | |
1529 | { 0x1f, 0x0002 }, | |
1530 | { 0x05, 0x6662 }, | |
1531 | { 0x1f, 0x0000 }, | |
1532 | { 0x14, 0x0060 }, | |
1533 | { 0x1f, 0x0000 }, | |
1534 | { 0x0d, 0xf8a0 }, | |
1535 | { 0x1f, 0x0005 }, | |
1536 | { 0x05, 0xffc2 } | |
1537 | }; | |
1538 | ||
1539 | rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0)); | |
1540 | ||
1541 | if (mdio_read(ioaddr, 0x06) == 0xc400) { | |
1542 | struct phy_reg phy_reg_init_1[] = { | |
1543 | { 0x1f, 0x0005 }, | |
1544 | { 0x01, 0x0300 }, | |
1545 | { 0x1f, 0x0000 }, | |
1546 | { 0x11, 0x401c }, | |
1547 | { 0x16, 0x4100 }, | |
1548 | { 0x1f, 0x0005 }, | |
1549 | { 0x07, 0x0010 }, | |
1550 | { 0x05, 0x83dc }, | |
1551 | { 0x06, 0x087d }, | |
1552 | { 0x05, 0x8300 }, | |
1553 | { 0x06, 0x0101 }, | |
1554 | { 0x06, 0x05f8 }, | |
1555 | { 0x06, 0xf9fa }, | |
1556 | { 0x06, 0xfbef }, | |
1557 | { 0x06, 0x79e2 }, | |
1558 | { 0x06, 0x835f }, | |
1559 | { 0x06, 0xe0f8 }, | |
1560 | { 0x06, 0x9ae1 }, | |
1561 | { 0x06, 0xf89b }, | |
1562 | { 0x06, 0xef31 }, | |
1563 | { 0x06, 0x3b65 }, | |
1564 | { 0x06, 0xaa07 }, | |
1565 | { 0x06, 0x81e4 }, | |
1566 | { 0x06, 0xf89a }, | |
1567 | { 0x06, 0xe5f8 }, | |
1568 | { 0x06, 0x9baf }, | |
1569 | { 0x06, 0x06ae }, | |
1570 | { 0x05, 0x83dc }, | |
1571 | { 0x06, 0x8300 }, | |
1572 | }; | |
1573 | ||
1574 | rtl_phy_write(ioaddr, phy_reg_init_1, | |
1575 | ARRAY_SIZE(phy_reg_init_1)); | |
1576 | } | |
1577 | ||
1578 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1579 | } | |
1580 | ||
2857ffb7 FR |
1581 | static void rtl8102e_hw_phy_config(void __iomem *ioaddr) |
1582 | { | |
1583 | struct phy_reg phy_reg_init[] = { | |
1584 | { 0x1f, 0x0003 }, | |
1585 | { 0x08, 0x441d }, | |
1586 | { 0x01, 0x9100 }, | |
1587 | { 0x1f, 0x0000 } | |
1588 | }; | |
1589 | ||
1590 | mdio_write(ioaddr, 0x1f, 0x0000); | |
1591 | mdio_patch(ioaddr, 0x11, 1 << 12); | |
1592 | mdio_patch(ioaddr, 0x19, 1 << 13); | |
1593 | ||
1594 | rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init)); | |
1595 | } | |
1596 | ||
5615d9f1 FR |
1597 | static void rtl_hw_phy_config(struct net_device *dev) |
1598 | { | |
1599 | struct rtl8169_private *tp = netdev_priv(dev); | |
1600 | void __iomem *ioaddr = tp->mmio_addr; | |
1601 | ||
1602 | rtl8169_print_mac_version(tp); | |
1603 | ||
1604 | switch (tp->mac_version) { | |
1605 | case RTL_GIGA_MAC_VER_01: | |
1606 | break; | |
1607 | case RTL_GIGA_MAC_VER_02: | |
1608 | case RTL_GIGA_MAC_VER_03: | |
1609 | rtl8169s_hw_phy_config(ioaddr); | |
1610 | break; | |
1611 | case RTL_GIGA_MAC_VER_04: | |
1612 | rtl8169sb_hw_phy_config(ioaddr); | |
1613 | break; | |
2857ffb7 FR |
1614 | case RTL_GIGA_MAC_VER_07: |
1615 | case RTL_GIGA_MAC_VER_08: | |
1616 | case RTL_GIGA_MAC_VER_09: | |
1617 | rtl8102e_hw_phy_config(ioaddr); | |
1618 | break; | |
236b8082 FR |
1619 | case RTL_GIGA_MAC_VER_11: |
1620 | rtl8168bb_hw_phy_config(ioaddr); | |
1621 | break; | |
1622 | case RTL_GIGA_MAC_VER_12: | |
1623 | rtl8168bef_hw_phy_config(ioaddr); | |
1624 | break; | |
1625 | case RTL_GIGA_MAC_VER_17: | |
1626 | rtl8168bef_hw_phy_config(ioaddr); | |
1627 | break; | |
867763c1 | 1628 | case RTL_GIGA_MAC_VER_18: |
ef3386f0 | 1629 | rtl8168cp_1_hw_phy_config(ioaddr); |
867763c1 FR |
1630 | break; |
1631 | case RTL_GIGA_MAC_VER_19: | |
219a1e9d | 1632 | rtl8168c_1_hw_phy_config(ioaddr); |
867763c1 | 1633 | break; |
7da97ec9 | 1634 | case RTL_GIGA_MAC_VER_20: |
219a1e9d | 1635 | rtl8168c_2_hw_phy_config(ioaddr); |
7da97ec9 | 1636 | break; |
197ff761 FR |
1637 | case RTL_GIGA_MAC_VER_21: |
1638 | rtl8168c_3_hw_phy_config(ioaddr); | |
1639 | break; | |
6fb07058 FR |
1640 | case RTL_GIGA_MAC_VER_22: |
1641 | rtl8168c_4_hw_phy_config(ioaddr); | |
1642 | break; | |
ef3386f0 | 1643 | case RTL_GIGA_MAC_VER_23: |
7f3e3d3a | 1644 | case RTL_GIGA_MAC_VER_24: |
ef3386f0 FR |
1645 | rtl8168cp_2_hw_phy_config(ioaddr); |
1646 | break; | |
5b538df9 FR |
1647 | case RTL_GIGA_MAC_VER_25: |
1648 | rtl8168d_hw_phy_config(ioaddr); | |
1649 | break; | |
ef3386f0 | 1650 | |
5615d9f1 FR |
1651 | default: |
1652 | break; | |
1653 | } | |
1654 | } | |
1655 | ||
1da177e4 LT |
1656 | static void rtl8169_phy_timer(unsigned long __opaque) |
1657 | { | |
1658 | struct net_device *dev = (struct net_device *)__opaque; | |
1659 | struct rtl8169_private *tp = netdev_priv(dev); | |
1660 | struct timer_list *timer = &tp->timer; | |
1661 | void __iomem *ioaddr = tp->mmio_addr; | |
1662 | unsigned long timeout = RTL8169_PHY_TIMEOUT; | |
1663 | ||
bcf0bf90 | 1664 | assert(tp->mac_version > RTL_GIGA_MAC_VER_01); |
1da177e4 | 1665 | |
64e4bfb4 | 1666 | if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL)) |
1da177e4 LT |
1667 | return; |
1668 | ||
1669 | spin_lock_irq(&tp->lock); | |
1670 | ||
1671 | if (tp->phy_reset_pending(ioaddr)) { | |
5b0384f4 | 1672 | /* |
1da177e4 LT |
1673 | * A busy loop could burn quite a few cycles on nowadays CPU. |
1674 | * Let's delay the execution of the timer for a few ticks. | |
1675 | */ | |
1676 | timeout = HZ/10; | |
1677 | goto out_mod_timer; | |
1678 | } | |
1679 | ||
1680 | if (tp->link_ok(ioaddr)) | |
1681 | goto out_unlock; | |
1682 | ||
b57b7e5a SH |
1683 | if (netif_msg_link(tp)) |
1684 | printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name); | |
1da177e4 LT |
1685 | |
1686 | tp->phy_reset_enable(ioaddr); | |
1687 | ||
1688 | out_mod_timer: | |
1689 | mod_timer(timer, jiffies + timeout); | |
1690 | out_unlock: | |
1691 | spin_unlock_irq(&tp->lock); | |
1692 | } | |
1693 | ||
1694 | static inline void rtl8169_delete_timer(struct net_device *dev) | |
1695 | { | |
1696 | struct rtl8169_private *tp = netdev_priv(dev); | |
1697 | struct timer_list *timer = &tp->timer; | |
1698 | ||
e179bb7b | 1699 | if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
1da177e4 LT |
1700 | return; |
1701 | ||
1702 | del_timer_sync(timer); | |
1703 | } | |
1704 | ||
1705 | static inline void rtl8169_request_timer(struct net_device *dev) | |
1706 | { | |
1707 | struct rtl8169_private *tp = netdev_priv(dev); | |
1708 | struct timer_list *timer = &tp->timer; | |
1709 | ||
e179bb7b | 1710 | if (tp->mac_version <= RTL_GIGA_MAC_VER_01) |
1da177e4 LT |
1711 | return; |
1712 | ||
2efa53f3 | 1713 | mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT); |
1da177e4 LT |
1714 | } |
1715 | ||
1716 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1717 | /* | |
1718 | * Polling 'interrupt' - used by things like netconsole to send skbs | |
1719 | * without having to re-enable interrupts. It's not called while | |
1720 | * the interrupt routine is executing. | |
1721 | */ | |
1722 | static void rtl8169_netpoll(struct net_device *dev) | |
1723 | { | |
1724 | struct rtl8169_private *tp = netdev_priv(dev); | |
1725 | struct pci_dev *pdev = tp->pci_dev; | |
1726 | ||
1727 | disable_irq(pdev->irq); | |
7d12e780 | 1728 | rtl8169_interrupt(pdev->irq, dev); |
1da177e4 LT |
1729 | enable_irq(pdev->irq); |
1730 | } | |
1731 | #endif | |
1732 | ||
1733 | static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev, | |
1734 | void __iomem *ioaddr) | |
1735 | { | |
1736 | iounmap(ioaddr); | |
1737 | pci_release_regions(pdev); | |
1738 | pci_disable_device(pdev); | |
1739 | free_netdev(dev); | |
1740 | } | |
1741 | ||
bf793295 FR |
1742 | static void rtl8169_phy_reset(struct net_device *dev, |
1743 | struct rtl8169_private *tp) | |
1744 | { | |
1745 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 1746 | unsigned int i; |
bf793295 FR |
1747 | |
1748 | tp->phy_reset_enable(ioaddr); | |
1749 | for (i = 0; i < 100; i++) { | |
1750 | if (!tp->phy_reset_pending(ioaddr)) | |
1751 | return; | |
1752 | msleep(1); | |
1753 | } | |
1754 | if (netif_msg_link(tp)) | |
1755 | printk(KERN_ERR "%s: PHY reset failed.\n", dev->name); | |
1756 | } | |
1757 | ||
4ff96fa6 FR |
1758 | static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp) |
1759 | { | |
1760 | void __iomem *ioaddr = tp->mmio_addr; | |
4ff96fa6 | 1761 | |
5615d9f1 | 1762 | rtl_hw_phy_config(dev); |
4ff96fa6 | 1763 | |
77332894 MS |
1764 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) { |
1765 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); | |
1766 | RTL_W8(0x82, 0x01); | |
1767 | } | |
4ff96fa6 | 1768 | |
6dccd16b FR |
1769 | pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); |
1770 | ||
1771 | if (tp->mac_version <= RTL_GIGA_MAC_VER_06) | |
1772 | pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); | |
4ff96fa6 | 1773 | |
bcf0bf90 | 1774 | if (tp->mac_version == RTL_GIGA_MAC_VER_02) { |
4ff96fa6 FR |
1775 | dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n"); |
1776 | RTL_W8(0x82, 0x01); | |
1777 | dprintk("Set PHY Reg 0x0bh = 0x00h\n"); | |
1778 | mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0 | |
1779 | } | |
1780 | ||
bf793295 FR |
1781 | rtl8169_phy_reset(dev, tp); |
1782 | ||
901dda2b FR |
1783 | /* |
1784 | * rtl8169_set_speed_xmii takes good care of the Fast Ethernet | |
1785 | * only 8101. Don't panic. | |
1786 | */ | |
1787 | rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL); | |
4ff96fa6 FR |
1788 | |
1789 | if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp)) | |
1790 | printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name); | |
1791 | } | |
1792 | ||
773d2021 FR |
1793 | static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr) |
1794 | { | |
1795 | void __iomem *ioaddr = tp->mmio_addr; | |
1796 | u32 high; | |
1797 | u32 low; | |
1798 | ||
1799 | low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24); | |
1800 | high = addr[4] | (addr[5] << 8); | |
1801 | ||
1802 | spin_lock_irq(&tp->lock); | |
1803 | ||
1804 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
1805 | RTL_W32(MAC0, low); | |
1806 | RTL_W32(MAC4, high); | |
1807 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
1808 | ||
1809 | spin_unlock_irq(&tp->lock); | |
1810 | } | |
1811 | ||
1812 | static int rtl_set_mac_address(struct net_device *dev, void *p) | |
1813 | { | |
1814 | struct rtl8169_private *tp = netdev_priv(dev); | |
1815 | struct sockaddr *addr = p; | |
1816 | ||
1817 | if (!is_valid_ether_addr(addr->sa_data)) | |
1818 | return -EADDRNOTAVAIL; | |
1819 | ||
1820 | memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); | |
1821 | ||
1822 | rtl_rar_set(tp, dev->dev_addr); | |
1823 | ||
1824 | return 0; | |
1825 | } | |
1826 | ||
5f787a1a FR |
1827 | static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) |
1828 | { | |
1829 | struct rtl8169_private *tp = netdev_priv(dev); | |
1830 | struct mii_ioctl_data *data = if_mii(ifr); | |
1831 | ||
1832 | if (!netif_running(dev)) | |
1833 | return -ENODEV; | |
1834 | ||
1835 | switch (cmd) { | |
1836 | case SIOCGMIIPHY: | |
1837 | data->phy_id = 32; /* Internal PHY */ | |
1838 | return 0; | |
1839 | ||
1840 | case SIOCGMIIREG: | |
1841 | data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f); | |
1842 | return 0; | |
1843 | ||
1844 | case SIOCSMIIREG: | |
1845 | if (!capable(CAP_NET_ADMIN)) | |
1846 | return -EPERM; | |
1847 | mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in); | |
1848 | return 0; | |
1849 | } | |
1850 | return -EOPNOTSUPP; | |
1851 | } | |
1852 | ||
0e485150 FR |
1853 | static const struct rtl_cfg_info { |
1854 | void (*hw_start)(struct net_device *); | |
1855 | unsigned int region; | |
1856 | unsigned int align; | |
1857 | u16 intr_event; | |
1858 | u16 napi_event; | |
ccdffb9a | 1859 | unsigned features; |
0e485150 FR |
1860 | } rtl_cfg_infos [] = { |
1861 | [RTL_CFG_0] = { | |
1862 | .hw_start = rtl_hw_start_8169, | |
1863 | .region = 1, | |
e9f63f30 | 1864 | .align = 0, |
0e485150 FR |
1865 | .intr_event = SYSErr | LinkChg | RxOverflow | |
1866 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 1867 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
ccdffb9a | 1868 | .features = RTL_FEATURE_GMII |
0e485150 FR |
1869 | }, |
1870 | [RTL_CFG_1] = { | |
1871 | .hw_start = rtl_hw_start_8168, | |
1872 | .region = 2, | |
1873 | .align = 8, | |
1874 | .intr_event = SYSErr | LinkChg | RxOverflow | | |
1875 | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 1876 | .napi_event = TxErr | TxOK | RxOK | RxOverflow, |
ccdffb9a | 1877 | .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI |
0e485150 FR |
1878 | }, |
1879 | [RTL_CFG_2] = { | |
1880 | .hw_start = rtl_hw_start_8101, | |
1881 | .region = 2, | |
1882 | .align = 8, | |
1883 | .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout | | |
1884 | RxFIFOOver | TxErr | TxOK | RxOK | RxErr, | |
fbac58fc | 1885 | .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow, |
ccdffb9a | 1886 | .features = RTL_FEATURE_MSI |
0e485150 FR |
1887 | } |
1888 | }; | |
1889 | ||
fbac58fc FR |
1890 | /* Cfg9346_Unlock assumed. */ |
1891 | static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr, | |
1892 | const struct rtl_cfg_info *cfg) | |
1893 | { | |
1894 | unsigned msi = 0; | |
1895 | u8 cfg2; | |
1896 | ||
1897 | cfg2 = RTL_R8(Config2) & ~MSIEnable; | |
ccdffb9a | 1898 | if (cfg->features & RTL_FEATURE_MSI) { |
fbac58fc FR |
1899 | if (pci_enable_msi(pdev)) { |
1900 | dev_info(&pdev->dev, "no MSI. Back to INTx.\n"); | |
1901 | } else { | |
1902 | cfg2 |= MSIEnable; | |
1903 | msi = RTL_FEATURE_MSI; | |
1904 | } | |
1905 | } | |
1906 | RTL_W8(Config2, cfg2); | |
1907 | return msi; | |
1908 | } | |
1909 | ||
1910 | static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp) | |
1911 | { | |
1912 | if (tp->features & RTL_FEATURE_MSI) { | |
1913 | pci_disable_msi(pdev); | |
1914 | tp->features &= ~RTL_FEATURE_MSI; | |
1915 | } | |
1916 | } | |
1917 | ||
1da177e4 | 1918 | static int __devinit |
4ff96fa6 | 1919 | rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 1920 | { |
0e485150 FR |
1921 | const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data; |
1922 | const unsigned int region = cfg->region; | |
1da177e4 | 1923 | struct rtl8169_private *tp; |
ccdffb9a | 1924 | struct mii_if_info *mii; |
4ff96fa6 FR |
1925 | struct net_device *dev; |
1926 | void __iomem *ioaddr; | |
07d3f51f FR |
1927 | unsigned int i; |
1928 | int rc; | |
1da177e4 | 1929 | |
4ff96fa6 FR |
1930 | if (netif_msg_drv(&debug)) { |
1931 | printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n", | |
1932 | MODULENAME, RTL8169_VERSION); | |
1933 | } | |
1da177e4 | 1934 | |
1da177e4 | 1935 | dev = alloc_etherdev(sizeof (*tp)); |
4ff96fa6 | 1936 | if (!dev) { |
b57b7e5a | 1937 | if (netif_msg_drv(&debug)) |
9b91cf9d | 1938 | dev_err(&pdev->dev, "unable to alloc new ethernet\n"); |
4ff96fa6 FR |
1939 | rc = -ENOMEM; |
1940 | goto out; | |
1da177e4 LT |
1941 | } |
1942 | ||
1da177e4 LT |
1943 | SET_NETDEV_DEV(dev, &pdev->dev); |
1944 | tp = netdev_priv(dev); | |
c4028958 | 1945 | tp->dev = dev; |
21e197f2 | 1946 | tp->pci_dev = pdev; |
b57b7e5a | 1947 | tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT); |
1da177e4 | 1948 | |
ccdffb9a FR |
1949 | mii = &tp->mii; |
1950 | mii->dev = dev; | |
1951 | mii->mdio_read = rtl_mdio_read; | |
1952 | mii->mdio_write = rtl_mdio_write; | |
1953 | mii->phy_id_mask = 0x1f; | |
1954 | mii->reg_num_mask = 0x1f; | |
1955 | mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII); | |
1956 | ||
1da177e4 LT |
1957 | /* enable device (incl. PCI PM wakeup and hotplug setup) */ |
1958 | rc = pci_enable_device(pdev); | |
b57b7e5a | 1959 | if (rc < 0) { |
2e8a538d | 1960 | if (netif_msg_probe(tp)) |
9b91cf9d | 1961 | dev_err(&pdev->dev, "enable failure\n"); |
4ff96fa6 | 1962 | goto err_out_free_dev_1; |
1da177e4 LT |
1963 | } |
1964 | ||
1965 | rc = pci_set_mwi(pdev); | |
1966 | if (rc < 0) | |
4ff96fa6 | 1967 | goto err_out_disable_2; |
1da177e4 | 1968 | |
1da177e4 | 1969 | /* make sure PCI base addr 1 is MMIO */ |
bcf0bf90 | 1970 | if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) { |
4ff96fa6 | 1971 | if (netif_msg_probe(tp)) { |
9b91cf9d | 1972 | dev_err(&pdev->dev, |
bcf0bf90 FR |
1973 | "region #%d not an MMIO resource, aborting\n", |
1974 | region); | |
4ff96fa6 | 1975 | } |
1da177e4 | 1976 | rc = -ENODEV; |
4ff96fa6 | 1977 | goto err_out_mwi_3; |
1da177e4 | 1978 | } |
4ff96fa6 | 1979 | |
1da177e4 | 1980 | /* check for weird/broken PCI region reporting */ |
bcf0bf90 | 1981 | if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) { |
4ff96fa6 | 1982 | if (netif_msg_probe(tp)) { |
9b91cf9d | 1983 | dev_err(&pdev->dev, |
4ff96fa6 FR |
1984 | "Invalid PCI region size(s), aborting\n"); |
1985 | } | |
1da177e4 | 1986 | rc = -ENODEV; |
4ff96fa6 | 1987 | goto err_out_mwi_3; |
1da177e4 LT |
1988 | } |
1989 | ||
1990 | rc = pci_request_regions(pdev, MODULENAME); | |
b57b7e5a | 1991 | if (rc < 0) { |
2e8a538d | 1992 | if (netif_msg_probe(tp)) |
9b91cf9d | 1993 | dev_err(&pdev->dev, "could not request regions.\n"); |
4ff96fa6 | 1994 | goto err_out_mwi_3; |
1da177e4 LT |
1995 | } |
1996 | ||
1997 | tp->cp_cmd = PCIMulRW | RxChkSum; | |
1998 | ||
1999 | if ((sizeof(dma_addr_t) > 4) && | |
2000 | !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) { | |
2001 | tp->cp_cmd |= PCIDAC; | |
2002 | dev->features |= NETIF_F_HIGHDMA; | |
2003 | } else { | |
2004 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
2005 | if (rc < 0) { | |
4ff96fa6 | 2006 | if (netif_msg_probe(tp)) { |
9b91cf9d | 2007 | dev_err(&pdev->dev, |
4ff96fa6 FR |
2008 | "DMA configuration failed.\n"); |
2009 | } | |
2010 | goto err_out_free_res_4; | |
1da177e4 LT |
2011 | } |
2012 | } | |
2013 | ||
2014 | pci_set_master(pdev); | |
2015 | ||
2016 | /* ioremap MMIO region */ | |
bcf0bf90 | 2017 | ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE); |
4ff96fa6 | 2018 | if (!ioaddr) { |
b57b7e5a | 2019 | if (netif_msg_probe(tp)) |
9b91cf9d | 2020 | dev_err(&pdev->dev, "cannot remap MMIO, aborting\n"); |
1da177e4 | 2021 | rc = -EIO; |
4ff96fa6 | 2022 | goto err_out_free_res_4; |
1da177e4 LT |
2023 | } |
2024 | ||
9c14ceaf FR |
2025 | tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP); |
2026 | if (!tp->pcie_cap && netif_msg_probe(tp)) | |
2027 | dev_info(&pdev->dev, "no PCI Express capability\n"); | |
2028 | ||
1da177e4 LT |
2029 | /* Unneeded ? Don't mess with Mrs. Murphy. */ |
2030 | rtl8169_irq_mask_and_ack(ioaddr); | |
2031 | ||
2032 | /* Soft reset the chip. */ | |
2033 | RTL_W8(ChipCmd, CmdReset); | |
2034 | ||
2035 | /* Check that the chip has finished the reset. */ | |
07d3f51f | 2036 | for (i = 0; i < 100; i++) { |
1da177e4 LT |
2037 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
2038 | break; | |
b518fa8e | 2039 | msleep_interruptible(1); |
1da177e4 LT |
2040 | } |
2041 | ||
2042 | /* Identify chip attached to board */ | |
2043 | rtl8169_get_mac_version(tp, ioaddr); | |
1da177e4 LT |
2044 | |
2045 | rtl8169_print_mac_version(tp); | |
1da177e4 | 2046 | |
cee60c37 | 2047 | for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) { |
1da177e4 LT |
2048 | if (tp->mac_version == rtl_chip_info[i].mac_version) |
2049 | break; | |
2050 | } | |
cee60c37 | 2051 | if (i == ARRAY_SIZE(rtl_chip_info)) { |
1da177e4 | 2052 | /* Unknown chip: assume array element #0, original RTL-8169 */ |
b57b7e5a | 2053 | if (netif_msg_probe(tp)) { |
2e8a538d | 2054 | dev_printk(KERN_DEBUG, &pdev->dev, |
4ff96fa6 FR |
2055 | "unknown chip version, assuming %s\n", |
2056 | rtl_chip_info[0].name); | |
b57b7e5a | 2057 | } |
cee60c37 | 2058 | i = 0; |
1da177e4 LT |
2059 | } |
2060 | tp->chipset = i; | |
2061 | ||
5d06a99f FR |
2062 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
2063 | RTL_W8(Config1, RTL_R8(Config1) | PMEnable); | |
2064 | RTL_W8(Config5, RTL_R8(Config5) & PMEStatus); | |
20037fa4 BP |
2065 | if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0) |
2066 | tp->features |= RTL_FEATURE_WOL; | |
2067 | if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0) | |
2068 | tp->features |= RTL_FEATURE_WOL; | |
fbac58fc | 2069 | tp->features |= rtl_try_msi(pdev, ioaddr, cfg); |
5d06a99f FR |
2070 | RTL_W8(Cfg9346, Cfg9346_Lock); |
2071 | ||
66ec5d4f FR |
2072 | if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) && |
2073 | (RTL_R8(PHYstatus) & TBI_Enable)) { | |
1da177e4 LT |
2074 | tp->set_speed = rtl8169_set_speed_tbi; |
2075 | tp->get_settings = rtl8169_gset_tbi; | |
2076 | tp->phy_reset_enable = rtl8169_tbi_reset_enable; | |
2077 | tp->phy_reset_pending = rtl8169_tbi_reset_pending; | |
2078 | tp->link_ok = rtl8169_tbi_link_ok; | |
2079 | ||
64e4bfb4 | 2080 | tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */ |
1da177e4 LT |
2081 | } else { |
2082 | tp->set_speed = rtl8169_set_speed_xmii; | |
2083 | tp->get_settings = rtl8169_gset_xmii; | |
2084 | tp->phy_reset_enable = rtl8169_xmii_reset_enable; | |
2085 | tp->phy_reset_pending = rtl8169_xmii_reset_pending; | |
2086 | tp->link_ok = rtl8169_xmii_link_ok; | |
5f787a1a FR |
2087 | |
2088 | dev->do_ioctl = rtl8169_ioctl; | |
1da177e4 LT |
2089 | } |
2090 | ||
df58ef51 FR |
2091 | spin_lock_init(&tp->lock); |
2092 | ||
738e1e69 PV |
2093 | tp->mmio_addr = ioaddr; |
2094 | ||
7bf6bf48 | 2095 | /* Get MAC address */ |
1da177e4 LT |
2096 | for (i = 0; i < MAC_ADDR_LEN; i++) |
2097 | dev->dev_addr[i] = RTL_R8(MAC0 + i); | |
6d6525b7 | 2098 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
1da177e4 LT |
2099 | |
2100 | dev->open = rtl8169_open; | |
2101 | dev->hard_start_xmit = rtl8169_start_xmit; | |
2102 | dev->get_stats = rtl8169_get_stats; | |
2103 | SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops); | |
2104 | dev->stop = rtl8169_close; | |
2105 | dev->tx_timeout = rtl8169_tx_timeout; | |
07ce4064 | 2106 | dev->set_multicast_list = rtl_set_rx_mode; |
1da177e4 LT |
2107 | dev->watchdog_timeo = RTL8169_TX_TIMEOUT; |
2108 | dev->irq = pdev->irq; | |
2109 | dev->base_addr = (unsigned long) ioaddr; | |
2110 | dev->change_mtu = rtl8169_change_mtu; | |
773d2021 | 2111 | dev->set_mac_address = rtl_set_mac_address; |
1da177e4 | 2112 | |
bea3348e | 2113 | netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT); |
1da177e4 LT |
2114 | |
2115 | #ifdef CONFIG_R8169_VLAN | |
2116 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
2117 | dev->vlan_rx_register = rtl8169_vlan_rx_register; | |
1da177e4 LT |
2118 | #endif |
2119 | ||
2120 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2121 | dev->poll_controller = rtl8169_netpoll; | |
2122 | #endif | |
2123 | ||
2124 | tp->intr_mask = 0xffff; | |
0e485150 FR |
2125 | tp->align = cfg->align; |
2126 | tp->hw_start = cfg->hw_start; | |
2127 | tp->intr_event = cfg->intr_event; | |
2128 | tp->napi_event = cfg->napi_event; | |
1da177e4 | 2129 | |
2efa53f3 FR |
2130 | init_timer(&tp->timer); |
2131 | tp->timer.data = (unsigned long) dev; | |
2132 | tp->timer.function = rtl8169_phy_timer; | |
2133 | ||
1da177e4 | 2134 | rc = register_netdev(dev); |
4ff96fa6 | 2135 | if (rc < 0) |
fbac58fc | 2136 | goto err_out_msi_5; |
1da177e4 LT |
2137 | |
2138 | pci_set_drvdata(pdev, dev); | |
2139 | ||
b57b7e5a | 2140 | if (netif_msg_probe(tp)) { |
96b9709c FR |
2141 | u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff; |
2142 | ||
b57b7e5a SH |
2143 | printk(KERN_INFO "%s: %s at 0x%lx, " |
2144 | "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, " | |
96b9709c | 2145 | "XID %08x IRQ %d\n", |
b57b7e5a | 2146 | dev->name, |
bcf0bf90 | 2147 | rtl_chip_info[tp->chipset].name, |
b57b7e5a SH |
2148 | dev->base_addr, |
2149 | dev->dev_addr[0], dev->dev_addr[1], | |
2150 | dev->dev_addr[2], dev->dev_addr[3], | |
96b9709c | 2151 | dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq); |
b57b7e5a | 2152 | } |
1da177e4 | 2153 | |
4ff96fa6 | 2154 | rtl8169_init_phy(dev, tp); |
8b76ab39 | 2155 | device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL); |
1da177e4 | 2156 | |
4ff96fa6 FR |
2157 | out: |
2158 | return rc; | |
1da177e4 | 2159 | |
fbac58fc FR |
2160 | err_out_msi_5: |
2161 | rtl_disable_msi(pdev, tp); | |
4ff96fa6 FR |
2162 | iounmap(ioaddr); |
2163 | err_out_free_res_4: | |
2164 | pci_release_regions(pdev); | |
2165 | err_out_mwi_3: | |
2166 | pci_clear_mwi(pdev); | |
2167 | err_out_disable_2: | |
2168 | pci_disable_device(pdev); | |
2169 | err_out_free_dev_1: | |
2170 | free_netdev(dev); | |
2171 | goto out; | |
1da177e4 LT |
2172 | } |
2173 | ||
07d3f51f | 2174 | static void __devexit rtl8169_remove_one(struct pci_dev *pdev) |
1da177e4 LT |
2175 | { |
2176 | struct net_device *dev = pci_get_drvdata(pdev); | |
2177 | struct rtl8169_private *tp = netdev_priv(dev); | |
2178 | ||
eb2a021c FR |
2179 | flush_scheduled_work(); |
2180 | ||
1da177e4 | 2181 | unregister_netdev(dev); |
fbac58fc | 2182 | rtl_disable_msi(pdev, tp); |
1da177e4 LT |
2183 | rtl8169_release_board(pdev, dev, tp->mmio_addr); |
2184 | pci_set_drvdata(pdev, NULL); | |
2185 | } | |
2186 | ||
1da177e4 LT |
2187 | static void rtl8169_set_rxbufsize(struct rtl8169_private *tp, |
2188 | struct net_device *dev) | |
2189 | { | |
2190 | unsigned int mtu = dev->mtu; | |
2191 | ||
2192 | tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE; | |
2193 | } | |
2194 | ||
2195 | static int rtl8169_open(struct net_device *dev) | |
2196 | { | |
2197 | struct rtl8169_private *tp = netdev_priv(dev); | |
2198 | struct pci_dev *pdev = tp->pci_dev; | |
99f252b0 | 2199 | int retval = -ENOMEM; |
1da177e4 | 2200 | |
1da177e4 | 2201 | |
99f252b0 | 2202 | rtl8169_set_rxbufsize(tp, dev); |
1da177e4 LT |
2203 | |
2204 | /* | |
2205 | * Rx and Tx desscriptors needs 256 bytes alignment. | |
2206 | * pci_alloc_consistent provides more. | |
2207 | */ | |
2208 | tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES, | |
2209 | &tp->TxPhyAddr); | |
2210 | if (!tp->TxDescArray) | |
99f252b0 | 2211 | goto out; |
1da177e4 LT |
2212 | |
2213 | tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES, | |
2214 | &tp->RxPhyAddr); | |
2215 | if (!tp->RxDescArray) | |
99f252b0 | 2216 | goto err_free_tx_0; |
1da177e4 LT |
2217 | |
2218 | retval = rtl8169_init_ring(dev); | |
2219 | if (retval < 0) | |
99f252b0 | 2220 | goto err_free_rx_1; |
1da177e4 | 2221 | |
c4028958 | 2222 | INIT_DELAYED_WORK(&tp->task, NULL); |
1da177e4 | 2223 | |
99f252b0 FR |
2224 | smp_mb(); |
2225 | ||
fbac58fc FR |
2226 | retval = request_irq(dev->irq, rtl8169_interrupt, |
2227 | (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED, | |
99f252b0 FR |
2228 | dev->name, dev); |
2229 | if (retval < 0) | |
2230 | goto err_release_ring_2; | |
2231 | ||
bea3348e | 2232 | napi_enable(&tp->napi); |
bea3348e | 2233 | |
07ce4064 | 2234 | rtl_hw_start(dev); |
1da177e4 LT |
2235 | |
2236 | rtl8169_request_timer(dev); | |
2237 | ||
2238 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); | |
2239 | out: | |
2240 | return retval; | |
2241 | ||
99f252b0 FR |
2242 | err_release_ring_2: |
2243 | rtl8169_rx_clear(tp); | |
2244 | err_free_rx_1: | |
1da177e4 LT |
2245 | pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
2246 | tp->RxPhyAddr); | |
99f252b0 | 2247 | err_free_tx_0: |
1da177e4 LT |
2248 | pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, |
2249 | tp->TxPhyAddr); | |
1da177e4 LT |
2250 | goto out; |
2251 | } | |
2252 | ||
2253 | static void rtl8169_hw_reset(void __iomem *ioaddr) | |
2254 | { | |
2255 | /* Disable interrupts */ | |
2256 | rtl8169_irq_mask_and_ack(ioaddr); | |
2257 | ||
2258 | /* Reset the chipset */ | |
2259 | RTL_W8(ChipCmd, CmdReset); | |
2260 | ||
2261 | /* PCI commit */ | |
2262 | RTL_R8(ChipCmd); | |
2263 | } | |
2264 | ||
7f796d83 | 2265 | static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp) |
9cb427b6 FR |
2266 | { |
2267 | void __iomem *ioaddr = tp->mmio_addr; | |
2268 | u32 cfg = rtl8169_rx_config; | |
2269 | ||
2270 | cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); | |
2271 | RTL_W32(RxConfig, cfg); | |
2272 | ||
2273 | /* Set DMA burst size and Interframe Gap Time */ | |
2274 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
2275 | (InterFrameGap << TxInterFrameGapShift)); | |
2276 | } | |
2277 | ||
07ce4064 | 2278 | static void rtl_hw_start(struct net_device *dev) |
1da177e4 LT |
2279 | { |
2280 | struct rtl8169_private *tp = netdev_priv(dev); | |
2281 | void __iomem *ioaddr = tp->mmio_addr; | |
07d3f51f | 2282 | unsigned int i; |
1da177e4 LT |
2283 | |
2284 | /* Soft reset the chip. */ | |
2285 | RTL_W8(ChipCmd, CmdReset); | |
2286 | ||
2287 | /* Check that the chip has finished the reset. */ | |
07d3f51f | 2288 | for (i = 0; i < 100; i++) { |
1da177e4 LT |
2289 | if ((RTL_R8(ChipCmd) & CmdReset) == 0) |
2290 | break; | |
b518fa8e | 2291 | msleep_interruptible(1); |
1da177e4 LT |
2292 | } |
2293 | ||
07ce4064 FR |
2294 | tp->hw_start(dev); |
2295 | ||
07ce4064 FR |
2296 | netif_start_queue(dev); |
2297 | } | |
2298 | ||
2299 | ||
7f796d83 FR |
2300 | static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp, |
2301 | void __iomem *ioaddr) | |
2302 | { | |
2303 | /* | |
2304 | * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh | |
2305 | * register to be written before TxDescAddrLow to work. | |
2306 | * Switching from MMIO to I/O access fixes the issue as well. | |
2307 | */ | |
2308 | RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32); | |
2309 | RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK); | |
2310 | RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32); | |
2311 | RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK); | |
2312 | } | |
2313 | ||
2314 | static u16 rtl_rw_cpluscmd(void __iomem *ioaddr) | |
2315 | { | |
2316 | u16 cmd; | |
2317 | ||
2318 | cmd = RTL_R16(CPlusCmd); | |
2319 | RTL_W16(CPlusCmd, cmd); | |
2320 | return cmd; | |
2321 | } | |
2322 | ||
2323 | static void rtl_set_rx_max_size(void __iomem *ioaddr) | |
2324 | { | |
2325 | /* Low hurts. Let's disable the filtering. */ | |
2326 | RTL_W16(RxMaxSize, 16383); | |
2327 | } | |
2328 | ||
6dccd16b FR |
2329 | static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version) |
2330 | { | |
2331 | struct { | |
2332 | u32 mac_version; | |
2333 | u32 clk; | |
2334 | u32 val; | |
2335 | } cfg2_info [] = { | |
2336 | { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd | |
2337 | { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff }, | |
2338 | { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe | |
2339 | { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff } | |
2340 | }, *p = cfg2_info; | |
2341 | unsigned int i; | |
2342 | u32 clk; | |
2343 | ||
2344 | clk = RTL_R8(Config2) & PCI_Clock_66MHz; | |
cadf1855 | 2345 | for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) { |
6dccd16b FR |
2346 | if ((p->mac_version == mac_version) && (p->clk == clk)) { |
2347 | RTL_W32(0x7c, p->val); | |
2348 | break; | |
2349 | } | |
2350 | } | |
2351 | } | |
2352 | ||
07ce4064 FR |
2353 | static void rtl_hw_start_8169(struct net_device *dev) |
2354 | { | |
2355 | struct rtl8169_private *tp = netdev_priv(dev); | |
2356 | void __iomem *ioaddr = tp->mmio_addr; | |
2357 | struct pci_dev *pdev = tp->pci_dev; | |
07ce4064 | 2358 | |
9cb427b6 FR |
2359 | if (tp->mac_version == RTL_GIGA_MAC_VER_05) { |
2360 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW); | |
2361 | pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); | |
2362 | } | |
2363 | ||
1da177e4 | 2364 | RTL_W8(Cfg9346, Cfg9346_Unlock); |
9cb427b6 FR |
2365 | if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
2366 | (tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
2367 | (tp->mac_version == RTL_GIGA_MAC_VER_03) || | |
2368 | (tp->mac_version == RTL_GIGA_MAC_VER_04)) | |
2369 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
2370 | ||
1da177e4 LT |
2371 | RTL_W8(EarlyTxThres, EarlyTxThld); |
2372 | ||
7f796d83 | 2373 | rtl_set_rx_max_size(ioaddr); |
1da177e4 | 2374 | |
c946b304 FR |
2375 | if ((tp->mac_version == RTL_GIGA_MAC_VER_01) || |
2376 | (tp->mac_version == RTL_GIGA_MAC_VER_02) || | |
2377 | (tp->mac_version == RTL_GIGA_MAC_VER_03) || | |
2378 | (tp->mac_version == RTL_GIGA_MAC_VER_04)) | |
2379 | rtl_set_rx_tx_config_registers(tp); | |
1da177e4 | 2380 | |
7f796d83 | 2381 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; |
1da177e4 | 2382 | |
bcf0bf90 FR |
2383 | if ((tp->mac_version == RTL_GIGA_MAC_VER_02) || |
2384 | (tp->mac_version == RTL_GIGA_MAC_VER_03)) { | |
06fa7358 | 2385 | dprintk("Set MAC Reg C+CR Offset 0xE0. " |
1da177e4 | 2386 | "Bit-3 and bit-14 MUST be 1\n"); |
bcf0bf90 | 2387 | tp->cp_cmd |= (1 << 14); |
1da177e4 LT |
2388 | } |
2389 | ||
bcf0bf90 FR |
2390 | RTL_W16(CPlusCmd, tp->cp_cmd); |
2391 | ||
6dccd16b FR |
2392 | rtl8169_set_magic_reg(ioaddr, tp->mac_version); |
2393 | ||
1da177e4 LT |
2394 | /* |
2395 | * Undocumented corner. Supposedly: | |
2396 | * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets | |
2397 | */ | |
2398 | RTL_W16(IntrMitigate, 0x0000); | |
2399 | ||
7f796d83 | 2400 | rtl_set_rx_tx_desc_registers(tp, ioaddr); |
9cb427b6 | 2401 | |
c946b304 FR |
2402 | if ((tp->mac_version != RTL_GIGA_MAC_VER_01) && |
2403 | (tp->mac_version != RTL_GIGA_MAC_VER_02) && | |
2404 | (tp->mac_version != RTL_GIGA_MAC_VER_03) && | |
2405 | (tp->mac_version != RTL_GIGA_MAC_VER_04)) { | |
2406 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
2407 | rtl_set_rx_tx_config_registers(tp); | |
2408 | } | |
2409 | ||
1da177e4 | 2410 | RTL_W8(Cfg9346, Cfg9346_Lock); |
b518fa8e FR |
2411 | |
2412 | /* Initially a 10 us delay. Turned it into a PCI commit. - FR */ | |
2413 | RTL_R8(IntrMask); | |
1da177e4 LT |
2414 | |
2415 | RTL_W32(RxMissed, 0); | |
2416 | ||
07ce4064 | 2417 | rtl_set_rx_mode(dev); |
1da177e4 LT |
2418 | |
2419 | /* no early-rx interrupts */ | |
2420 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); | |
6dccd16b FR |
2421 | |
2422 | /* Enable all known interrupts by setting the interrupt mask. */ | |
0e485150 | 2423 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 2424 | } |
1da177e4 | 2425 | |
9c14ceaf | 2426 | static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force) |
458a9f61 | 2427 | { |
9c14ceaf FR |
2428 | struct net_device *dev = pci_get_drvdata(pdev); |
2429 | struct rtl8169_private *tp = netdev_priv(dev); | |
2430 | int cap = tp->pcie_cap; | |
2431 | ||
2432 | if (cap) { | |
2433 | u16 ctl; | |
458a9f61 | 2434 | |
9c14ceaf FR |
2435 | pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl); |
2436 | ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force; | |
2437 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl); | |
2438 | } | |
458a9f61 FR |
2439 | } |
2440 | ||
dacf8154 FR |
2441 | static void rtl_csi_access_enable(void __iomem *ioaddr) |
2442 | { | |
2443 | u32 csi; | |
2444 | ||
2445 | csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff; | |
2446 | rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000); | |
2447 | } | |
2448 | ||
2449 | struct ephy_info { | |
2450 | unsigned int offset; | |
2451 | u16 mask; | |
2452 | u16 bits; | |
2453 | }; | |
2454 | ||
2455 | static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len) | |
2456 | { | |
2457 | u16 w; | |
2458 | ||
2459 | while (len-- > 0) { | |
2460 | w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits; | |
2461 | rtl_ephy_write(ioaddr, e->offset, w); | |
2462 | e++; | |
2463 | } | |
2464 | } | |
2465 | ||
b726e493 FR |
2466 | static void rtl_disable_clock_request(struct pci_dev *pdev) |
2467 | { | |
2468 | struct net_device *dev = pci_get_drvdata(pdev); | |
2469 | struct rtl8169_private *tp = netdev_priv(dev); | |
2470 | int cap = tp->pcie_cap; | |
2471 | ||
2472 | if (cap) { | |
2473 | u16 ctl; | |
2474 | ||
2475 | pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl); | |
2476 | ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN; | |
2477 | pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl); | |
2478 | } | |
2479 | } | |
2480 | ||
2481 | #define R8168_CPCMD_QUIRK_MASK (\ | |
2482 | EnableBist | \ | |
2483 | Mac_dbgo_oe | \ | |
2484 | Force_half_dup | \ | |
2485 | Force_rxflow_en | \ | |
2486 | Force_txflow_en | \ | |
2487 | Cxpl_dbg_sel | \ | |
2488 | ASF | \ | |
2489 | PktCntrDisable | \ | |
2490 | Mac_dbgo_sel) | |
2491 | ||
219a1e9d FR |
2492 | static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev) |
2493 | { | |
b726e493 FR |
2494 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); |
2495 | ||
2496 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
2497 | ||
2e68ae44 FR |
2498 | rtl_tx_performance_tweak(pdev, |
2499 | (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
219a1e9d FR |
2500 | } |
2501 | ||
2502 | static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev) | |
2503 | { | |
2504 | rtl_hw_start_8168bb(ioaddr, pdev); | |
b726e493 FR |
2505 | |
2506 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2507 | ||
2508 | RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0)); | |
219a1e9d FR |
2509 | } |
2510 | ||
2511 | static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev) | |
2512 | { | |
b726e493 FR |
2513 | RTL_W8(Config1, RTL_R8(Config1) | Speed_down); |
2514 | ||
2515 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2516 | ||
219a1e9d | 2517 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); |
b726e493 FR |
2518 | |
2519 | rtl_disable_clock_request(pdev); | |
2520 | ||
2521 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
219a1e9d FR |
2522 | } |
2523 | ||
ef3386f0 | 2524 | static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev) |
219a1e9d | 2525 | { |
b726e493 FR |
2526 | static struct ephy_info e_info_8168cp[] = { |
2527 | { 0x01, 0, 0x0001 }, | |
2528 | { 0x02, 0x0800, 0x1000 }, | |
2529 | { 0x03, 0, 0x0042 }, | |
2530 | { 0x06, 0x0080, 0x0000 }, | |
2531 | { 0x07, 0, 0x2000 } | |
2532 | }; | |
2533 | ||
2534 | rtl_csi_access_enable(ioaddr); | |
2535 | ||
2536 | rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp)); | |
2537 | ||
219a1e9d FR |
2538 | __rtl_hw_start_8168cp(ioaddr, pdev); |
2539 | } | |
2540 | ||
ef3386f0 FR |
2541 | static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev) |
2542 | { | |
2543 | rtl_csi_access_enable(ioaddr); | |
2544 | ||
2545 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2546 | ||
2547 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2548 | ||
2549 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
2550 | } | |
2551 | ||
7f3e3d3a FR |
2552 | static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev) |
2553 | { | |
2554 | rtl_csi_access_enable(ioaddr); | |
2555 | ||
2556 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2557 | ||
2558 | /* Magic. */ | |
2559 | RTL_W8(DBG_REG, 0x20); | |
2560 | ||
2561 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2562 | ||
2563 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2564 | ||
2565 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
2566 | } | |
2567 | ||
219a1e9d FR |
2568 | static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev) |
2569 | { | |
b726e493 FR |
2570 | static struct ephy_info e_info_8168c_1[] = { |
2571 | { 0x02, 0x0800, 0x1000 }, | |
2572 | { 0x03, 0, 0x0002 }, | |
2573 | { 0x06, 0x0080, 0x0000 } | |
2574 | }; | |
2575 | ||
2576 | rtl_csi_access_enable(ioaddr); | |
2577 | ||
2578 | RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); | |
2579 | ||
2580 | rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1)); | |
2581 | ||
219a1e9d FR |
2582 | __rtl_hw_start_8168cp(ioaddr, pdev); |
2583 | } | |
2584 | ||
2585 | static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
2586 | { | |
b726e493 FR |
2587 | static struct ephy_info e_info_8168c_2[] = { |
2588 | { 0x01, 0, 0x0001 }, | |
2589 | { 0x03, 0x0400, 0x0220 } | |
2590 | }; | |
2591 | ||
2592 | rtl_csi_access_enable(ioaddr); | |
2593 | ||
2594 | rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2)); | |
2595 | ||
219a1e9d FR |
2596 | __rtl_hw_start_8168cp(ioaddr, pdev); |
2597 | } | |
2598 | ||
197ff761 FR |
2599 | static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev) |
2600 | { | |
2601 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
2602 | } | |
2603 | ||
6fb07058 FR |
2604 | static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev) |
2605 | { | |
2606 | rtl_csi_access_enable(ioaddr); | |
2607 | ||
2608 | __rtl_hw_start_8168cp(ioaddr, pdev); | |
2609 | } | |
2610 | ||
5b538df9 FR |
2611 | static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev) |
2612 | { | |
2613 | rtl_csi_access_enable(ioaddr); | |
2614 | ||
2615 | rtl_disable_clock_request(pdev); | |
2616 | ||
2617 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2618 | ||
2619 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2620 | ||
2621 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK); | |
2622 | } | |
2623 | ||
07ce4064 FR |
2624 | static void rtl_hw_start_8168(struct net_device *dev) |
2625 | { | |
2dd99530 FR |
2626 | struct rtl8169_private *tp = netdev_priv(dev); |
2627 | void __iomem *ioaddr = tp->mmio_addr; | |
0e485150 | 2628 | struct pci_dev *pdev = tp->pci_dev; |
2dd99530 FR |
2629 | |
2630 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
2631 | ||
2632 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2633 | ||
2634 | rtl_set_rx_max_size(ioaddr); | |
2635 | ||
0e485150 | 2636 | tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1; |
2dd99530 FR |
2637 | |
2638 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
2639 | ||
0e485150 | 2640 | RTL_W16(IntrMitigate, 0x5151); |
2dd99530 | 2641 | |
0e485150 FR |
2642 | /* Work around for RxFIFO overflow. */ |
2643 | if (tp->mac_version == RTL_GIGA_MAC_VER_11) { | |
2644 | tp->intr_event |= RxFIFOOver | PCSTimeout; | |
2645 | tp->intr_event &= ~RxOverflow; | |
2646 | } | |
2647 | ||
2648 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2dd99530 | 2649 | |
b8363901 FR |
2650 | rtl_set_rx_mode(dev); |
2651 | ||
2652 | RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) | | |
2653 | (InterFrameGap << TxInterFrameGapShift)); | |
2dd99530 FR |
2654 | |
2655 | RTL_R8(IntrMask); | |
2656 | ||
219a1e9d FR |
2657 | switch (tp->mac_version) { |
2658 | case RTL_GIGA_MAC_VER_11: | |
2659 | rtl_hw_start_8168bb(ioaddr, pdev); | |
2660 | break; | |
2661 | ||
2662 | case RTL_GIGA_MAC_VER_12: | |
2663 | case RTL_GIGA_MAC_VER_17: | |
2664 | rtl_hw_start_8168bef(ioaddr, pdev); | |
2665 | break; | |
2666 | ||
2667 | case RTL_GIGA_MAC_VER_18: | |
ef3386f0 | 2668 | rtl_hw_start_8168cp_1(ioaddr, pdev); |
219a1e9d FR |
2669 | break; |
2670 | ||
2671 | case RTL_GIGA_MAC_VER_19: | |
2672 | rtl_hw_start_8168c_1(ioaddr, pdev); | |
2673 | break; | |
2674 | ||
2675 | case RTL_GIGA_MAC_VER_20: | |
2676 | rtl_hw_start_8168c_2(ioaddr, pdev); | |
2677 | break; | |
2678 | ||
197ff761 FR |
2679 | case RTL_GIGA_MAC_VER_21: |
2680 | rtl_hw_start_8168c_3(ioaddr, pdev); | |
2681 | break; | |
2682 | ||
6fb07058 FR |
2683 | case RTL_GIGA_MAC_VER_22: |
2684 | rtl_hw_start_8168c_4(ioaddr, pdev); | |
2685 | break; | |
2686 | ||
ef3386f0 FR |
2687 | case RTL_GIGA_MAC_VER_23: |
2688 | rtl_hw_start_8168cp_2(ioaddr, pdev); | |
2689 | break; | |
2690 | ||
7f3e3d3a FR |
2691 | case RTL_GIGA_MAC_VER_24: |
2692 | rtl_hw_start_8168cp_3(ioaddr, pdev); | |
2693 | break; | |
2694 | ||
5b538df9 FR |
2695 | case RTL_GIGA_MAC_VER_25: |
2696 | rtl_hw_start_8168d(ioaddr, pdev); | |
2697 | break; | |
2698 | ||
219a1e9d FR |
2699 | default: |
2700 | printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n", | |
2701 | dev->name, tp->mac_version); | |
2702 | break; | |
2703 | } | |
2dd99530 | 2704 | |
0e485150 FR |
2705 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
2706 | ||
b8363901 FR |
2707 | RTL_W8(Cfg9346, Cfg9346_Lock); |
2708 | ||
2dd99530 | 2709 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000); |
6dccd16b | 2710 | |
0e485150 | 2711 | RTL_W16(IntrMask, tp->intr_event); |
07ce4064 | 2712 | } |
1da177e4 | 2713 | |
2857ffb7 FR |
2714 | #define R810X_CPCMD_QUIRK_MASK (\ |
2715 | EnableBist | \ | |
2716 | Mac_dbgo_oe | \ | |
2717 | Force_half_dup | \ | |
2718 | Force_half_dup | \ | |
2719 | Force_txflow_en | \ | |
2720 | Cxpl_dbg_sel | \ | |
2721 | ASF | \ | |
2722 | PktCntrDisable | \ | |
2723 | PCIDAC | \ | |
2724 | PCIMulRW) | |
2725 | ||
2726 | static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev) | |
2727 | { | |
2728 | static struct ephy_info e_info_8102e_1[] = { | |
2729 | { 0x01, 0, 0x6e65 }, | |
2730 | { 0x02, 0, 0x091f }, | |
2731 | { 0x03, 0, 0xc2f9 }, | |
2732 | { 0x06, 0, 0xafb5 }, | |
2733 | { 0x07, 0, 0x0e00 }, | |
2734 | { 0x19, 0, 0xec80 }, | |
2735 | { 0x01, 0, 0x2e65 }, | |
2736 | { 0x01, 0, 0x6e65 } | |
2737 | }; | |
2738 | u8 cfg1; | |
2739 | ||
2740 | rtl_csi_access_enable(ioaddr); | |
2741 | ||
2742 | RTL_W8(DBG_REG, FIX_NAK_1); | |
2743 | ||
2744 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2745 | ||
2746 | RTL_W8(Config1, | |
2747 | LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable); | |
2748 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2749 | ||
2750 | cfg1 = RTL_R8(Config1); | |
2751 | if ((cfg1 & LEDS0) && (cfg1 & LEDS1)) | |
2752 | RTL_W8(Config1, cfg1 & ~LEDS0); | |
2753 | ||
2754 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); | |
2755 | ||
2756 | rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1)); | |
2757 | } | |
2758 | ||
2759 | static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev) | |
2760 | { | |
2761 | rtl_csi_access_enable(ioaddr); | |
2762 | ||
2763 | rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT); | |
2764 | ||
2765 | RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable); | |
2766 | RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en); | |
2767 | ||
2768 | RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK); | |
2769 | } | |
2770 | ||
2771 | static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev) | |
2772 | { | |
2773 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
2774 | ||
2775 | rtl_ephy_write(ioaddr, 0x03, 0xc2f9); | |
2776 | } | |
2777 | ||
07ce4064 FR |
2778 | static void rtl_hw_start_8101(struct net_device *dev) |
2779 | { | |
cdf1a608 FR |
2780 | struct rtl8169_private *tp = netdev_priv(dev); |
2781 | void __iomem *ioaddr = tp->mmio_addr; | |
2782 | struct pci_dev *pdev = tp->pci_dev; | |
2783 | ||
e3cf0cc0 FR |
2784 | if ((tp->mac_version == RTL_GIGA_MAC_VER_13) || |
2785 | (tp->mac_version == RTL_GIGA_MAC_VER_16)) { | |
9c14ceaf FR |
2786 | int cap = tp->pcie_cap; |
2787 | ||
2788 | if (cap) { | |
2789 | pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, | |
2790 | PCI_EXP_DEVCTL_NOSNOOP_EN); | |
2791 | } | |
cdf1a608 FR |
2792 | } |
2793 | ||
2857ffb7 FR |
2794 | switch (tp->mac_version) { |
2795 | case RTL_GIGA_MAC_VER_07: | |
2796 | rtl_hw_start_8102e_1(ioaddr, pdev); | |
2797 | break; | |
2798 | ||
2799 | case RTL_GIGA_MAC_VER_08: | |
2800 | rtl_hw_start_8102e_3(ioaddr, pdev); | |
2801 | break; | |
2802 | ||
2803 | case RTL_GIGA_MAC_VER_09: | |
2804 | rtl_hw_start_8102e_2(ioaddr, pdev); | |
2805 | break; | |
cdf1a608 FR |
2806 | } |
2807 | ||
2808 | RTL_W8(Cfg9346, Cfg9346_Unlock); | |
2809 | ||
2810 | RTL_W8(EarlyTxThres, EarlyTxThld); | |
2811 | ||
2812 | rtl_set_rx_max_size(ioaddr); | |
2813 | ||
2814 | tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW; | |
2815 | ||
2816 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
2817 | ||
2818 | RTL_W16(IntrMitigate, 0x0000); | |
2819 | ||
2820 | rtl_set_rx_tx_desc_registers(tp, ioaddr); | |
2821 | ||
2822 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); | |
2823 | rtl_set_rx_tx_config_registers(tp); | |
2824 | ||
2825 | RTL_W8(Cfg9346, Cfg9346_Lock); | |
2826 | ||
2827 | RTL_R8(IntrMask); | |
2828 | ||
cdf1a608 FR |
2829 | rtl_set_rx_mode(dev); |
2830 | ||
0e485150 FR |
2831 | RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); |
2832 | ||
cdf1a608 | 2833 | RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000); |
6dccd16b | 2834 | |
0e485150 | 2835 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
2836 | } |
2837 | ||
2838 | static int rtl8169_change_mtu(struct net_device *dev, int new_mtu) | |
2839 | { | |
2840 | struct rtl8169_private *tp = netdev_priv(dev); | |
2841 | int ret = 0; | |
2842 | ||
2843 | if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu) | |
2844 | return -EINVAL; | |
2845 | ||
2846 | dev->mtu = new_mtu; | |
2847 | ||
2848 | if (!netif_running(dev)) | |
2849 | goto out; | |
2850 | ||
2851 | rtl8169_down(dev); | |
2852 | ||
2853 | rtl8169_set_rxbufsize(tp, dev); | |
2854 | ||
2855 | ret = rtl8169_init_ring(dev); | |
2856 | if (ret < 0) | |
2857 | goto out; | |
2858 | ||
bea3348e | 2859 | napi_enable(&tp->napi); |
1da177e4 | 2860 | |
07ce4064 | 2861 | rtl_hw_start(dev); |
1da177e4 LT |
2862 | |
2863 | rtl8169_request_timer(dev); | |
2864 | ||
2865 | out: | |
2866 | return ret; | |
2867 | } | |
2868 | ||
2869 | static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc) | |
2870 | { | |
95e0918d | 2871 | desc->addr = cpu_to_le64(0x0badbadbadbadbadull); |
1da177e4 LT |
2872 | desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask); |
2873 | } | |
2874 | ||
2875 | static void rtl8169_free_rx_skb(struct rtl8169_private *tp, | |
2876 | struct sk_buff **sk_buff, struct RxDesc *desc) | |
2877 | { | |
2878 | struct pci_dev *pdev = tp->pci_dev; | |
2879 | ||
2880 | pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz, | |
2881 | PCI_DMA_FROMDEVICE); | |
2882 | dev_kfree_skb(*sk_buff); | |
2883 | *sk_buff = NULL; | |
2884 | rtl8169_make_unusable_by_asic(desc); | |
2885 | } | |
2886 | ||
2887 | static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz) | |
2888 | { | |
2889 | u32 eor = le32_to_cpu(desc->opts1) & RingEnd; | |
2890 | ||
2891 | desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz); | |
2892 | } | |
2893 | ||
2894 | static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping, | |
2895 | u32 rx_buf_sz) | |
2896 | { | |
2897 | desc->addr = cpu_to_le64(mapping); | |
2898 | wmb(); | |
2899 | rtl8169_mark_to_asic(desc, rx_buf_sz); | |
2900 | } | |
2901 | ||
15d31758 SH |
2902 | static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev, |
2903 | struct net_device *dev, | |
2904 | struct RxDesc *desc, int rx_buf_sz, | |
2905 | unsigned int align) | |
1da177e4 LT |
2906 | { |
2907 | struct sk_buff *skb; | |
2908 | dma_addr_t mapping; | |
e9f63f30 | 2909 | unsigned int pad; |
1da177e4 | 2910 | |
e9f63f30 FR |
2911 | pad = align ? align : NET_IP_ALIGN; |
2912 | ||
2913 | skb = netdev_alloc_skb(dev, rx_buf_sz + pad); | |
1da177e4 LT |
2914 | if (!skb) |
2915 | goto err_out; | |
2916 | ||
e9f63f30 | 2917 | skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad); |
1da177e4 | 2918 | |
689be439 | 2919 | mapping = pci_map_single(pdev, skb->data, rx_buf_sz, |
1da177e4 LT |
2920 | PCI_DMA_FROMDEVICE); |
2921 | ||
2922 | rtl8169_map_to_asic(desc, mapping, rx_buf_sz); | |
1da177e4 | 2923 | out: |
15d31758 | 2924 | return skb; |
1da177e4 LT |
2925 | |
2926 | err_out: | |
1da177e4 LT |
2927 | rtl8169_make_unusable_by_asic(desc); |
2928 | goto out; | |
2929 | } | |
2930 | ||
2931 | static void rtl8169_rx_clear(struct rtl8169_private *tp) | |
2932 | { | |
07d3f51f | 2933 | unsigned int i; |
1da177e4 LT |
2934 | |
2935 | for (i = 0; i < NUM_RX_DESC; i++) { | |
2936 | if (tp->Rx_skbuff[i]) { | |
2937 | rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i, | |
2938 | tp->RxDescArray + i); | |
2939 | } | |
2940 | } | |
2941 | } | |
2942 | ||
2943 | static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev, | |
2944 | u32 start, u32 end) | |
2945 | { | |
2946 | u32 cur; | |
5b0384f4 | 2947 | |
4ae47c2d | 2948 | for (cur = start; end - cur != 0; cur++) { |
15d31758 SH |
2949 | struct sk_buff *skb; |
2950 | unsigned int i = cur % NUM_RX_DESC; | |
1da177e4 | 2951 | |
4ae47c2d FR |
2952 | WARN_ON((s32)(end - cur) < 0); |
2953 | ||
1da177e4 LT |
2954 | if (tp->Rx_skbuff[i]) |
2955 | continue; | |
bcf0bf90 | 2956 | |
15d31758 SH |
2957 | skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev, |
2958 | tp->RxDescArray + i, | |
2959 | tp->rx_buf_sz, tp->align); | |
2960 | if (!skb) | |
1da177e4 | 2961 | break; |
15d31758 SH |
2962 | |
2963 | tp->Rx_skbuff[i] = skb; | |
1da177e4 LT |
2964 | } |
2965 | return cur - start; | |
2966 | } | |
2967 | ||
2968 | static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc) | |
2969 | { | |
2970 | desc->opts1 |= cpu_to_le32(RingEnd); | |
2971 | } | |
2972 | ||
2973 | static void rtl8169_init_ring_indexes(struct rtl8169_private *tp) | |
2974 | { | |
2975 | tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0; | |
2976 | } | |
2977 | ||
2978 | static int rtl8169_init_ring(struct net_device *dev) | |
2979 | { | |
2980 | struct rtl8169_private *tp = netdev_priv(dev); | |
2981 | ||
2982 | rtl8169_init_ring_indexes(tp); | |
2983 | ||
2984 | memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info)); | |
2985 | memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *)); | |
2986 | ||
2987 | if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC) | |
2988 | goto err_out; | |
2989 | ||
2990 | rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1); | |
2991 | ||
2992 | return 0; | |
2993 | ||
2994 | err_out: | |
2995 | rtl8169_rx_clear(tp); | |
2996 | return -ENOMEM; | |
2997 | } | |
2998 | ||
2999 | static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb, | |
3000 | struct TxDesc *desc) | |
3001 | { | |
3002 | unsigned int len = tx_skb->len; | |
3003 | ||
3004 | pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE); | |
3005 | desc->opts1 = 0x00; | |
3006 | desc->opts2 = 0x00; | |
3007 | desc->addr = 0x00; | |
3008 | tx_skb->len = 0; | |
3009 | } | |
3010 | ||
3011 | static void rtl8169_tx_clear(struct rtl8169_private *tp) | |
3012 | { | |
3013 | unsigned int i; | |
3014 | ||
3015 | for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) { | |
3016 | unsigned int entry = i % NUM_TX_DESC; | |
3017 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
3018 | unsigned int len = tx_skb->len; | |
3019 | ||
3020 | if (len) { | |
3021 | struct sk_buff *skb = tx_skb->skb; | |
3022 | ||
3023 | rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, | |
3024 | tp->TxDescArray + entry); | |
3025 | if (skb) { | |
3026 | dev_kfree_skb(skb); | |
3027 | tx_skb->skb = NULL; | |
3028 | } | |
cebf8cc7 | 3029 | tp->dev->stats.tx_dropped++; |
1da177e4 LT |
3030 | } |
3031 | } | |
3032 | tp->cur_tx = tp->dirty_tx = 0; | |
3033 | } | |
3034 | ||
c4028958 | 3035 | static void rtl8169_schedule_work(struct net_device *dev, work_func_t task) |
1da177e4 LT |
3036 | { |
3037 | struct rtl8169_private *tp = netdev_priv(dev); | |
3038 | ||
c4028958 | 3039 | PREPARE_DELAYED_WORK(&tp->task, task); |
1da177e4 LT |
3040 | schedule_delayed_work(&tp->task, 4); |
3041 | } | |
3042 | ||
3043 | static void rtl8169_wait_for_quiescence(struct net_device *dev) | |
3044 | { | |
3045 | struct rtl8169_private *tp = netdev_priv(dev); | |
3046 | void __iomem *ioaddr = tp->mmio_addr; | |
3047 | ||
3048 | synchronize_irq(dev->irq); | |
3049 | ||
3050 | /* Wait for any pending NAPI task to complete */ | |
bea3348e | 3051 | napi_disable(&tp->napi); |
1da177e4 LT |
3052 | |
3053 | rtl8169_irq_mask_and_ack(ioaddr); | |
3054 | ||
d1d08d12 DM |
3055 | tp->intr_mask = 0xffff; |
3056 | RTL_W16(IntrMask, tp->intr_event); | |
bea3348e | 3057 | napi_enable(&tp->napi); |
1da177e4 LT |
3058 | } |
3059 | ||
c4028958 | 3060 | static void rtl8169_reinit_task(struct work_struct *work) |
1da177e4 | 3061 | { |
c4028958 DH |
3062 | struct rtl8169_private *tp = |
3063 | container_of(work, struct rtl8169_private, task.work); | |
3064 | struct net_device *dev = tp->dev; | |
1da177e4 LT |
3065 | int ret; |
3066 | ||
eb2a021c FR |
3067 | rtnl_lock(); |
3068 | ||
3069 | if (!netif_running(dev)) | |
3070 | goto out_unlock; | |
3071 | ||
3072 | rtl8169_wait_for_quiescence(dev); | |
3073 | rtl8169_close(dev); | |
1da177e4 LT |
3074 | |
3075 | ret = rtl8169_open(dev); | |
3076 | if (unlikely(ret < 0)) { | |
07d3f51f | 3077 | if (net_ratelimit() && netif_msg_drv(tp)) { |
53edbecd | 3078 | printk(KERN_ERR PFX "%s: reinit failure (status = %d)." |
07d3f51f | 3079 | " Rescheduling.\n", dev->name, ret); |
1da177e4 LT |
3080 | } |
3081 | rtl8169_schedule_work(dev, rtl8169_reinit_task); | |
3082 | } | |
eb2a021c FR |
3083 | |
3084 | out_unlock: | |
3085 | rtnl_unlock(); | |
1da177e4 LT |
3086 | } |
3087 | ||
c4028958 | 3088 | static void rtl8169_reset_task(struct work_struct *work) |
1da177e4 | 3089 | { |
c4028958 DH |
3090 | struct rtl8169_private *tp = |
3091 | container_of(work, struct rtl8169_private, task.work); | |
3092 | struct net_device *dev = tp->dev; | |
1da177e4 | 3093 | |
eb2a021c FR |
3094 | rtnl_lock(); |
3095 | ||
1da177e4 | 3096 | if (!netif_running(dev)) |
eb2a021c | 3097 | goto out_unlock; |
1da177e4 LT |
3098 | |
3099 | rtl8169_wait_for_quiescence(dev); | |
3100 | ||
bea3348e | 3101 | rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0); |
1da177e4 LT |
3102 | rtl8169_tx_clear(tp); |
3103 | ||
3104 | if (tp->dirty_rx == tp->cur_rx) { | |
3105 | rtl8169_init_ring_indexes(tp); | |
07ce4064 | 3106 | rtl_hw_start(dev); |
1da177e4 | 3107 | netif_wake_queue(dev); |
cebf8cc7 | 3108 | rtl8169_check_link_status(dev, tp, tp->mmio_addr); |
1da177e4 | 3109 | } else { |
07d3f51f | 3110 | if (net_ratelimit() && netif_msg_intr(tp)) { |
53edbecd | 3111 | printk(KERN_EMERG PFX "%s: Rx buffers shortage\n", |
07d3f51f | 3112 | dev->name); |
1da177e4 LT |
3113 | } |
3114 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
3115 | } | |
eb2a021c FR |
3116 | |
3117 | out_unlock: | |
3118 | rtnl_unlock(); | |
1da177e4 LT |
3119 | } |
3120 | ||
3121 | static void rtl8169_tx_timeout(struct net_device *dev) | |
3122 | { | |
3123 | struct rtl8169_private *tp = netdev_priv(dev); | |
3124 | ||
3125 | rtl8169_hw_reset(tp->mmio_addr); | |
3126 | ||
3127 | /* Let's wait a bit while any (async) irq lands on */ | |
3128 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
3129 | } | |
3130 | ||
3131 | static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb, | |
3132 | u32 opts1) | |
3133 | { | |
3134 | struct skb_shared_info *info = skb_shinfo(skb); | |
3135 | unsigned int cur_frag, entry; | |
a6343afb | 3136 | struct TxDesc * uninitialized_var(txd); |
1da177e4 LT |
3137 | |
3138 | entry = tp->cur_tx; | |
3139 | for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { | |
3140 | skb_frag_t *frag = info->frags + cur_frag; | |
3141 | dma_addr_t mapping; | |
3142 | u32 status, len; | |
3143 | void *addr; | |
3144 | ||
3145 | entry = (entry + 1) % NUM_TX_DESC; | |
3146 | ||
3147 | txd = tp->TxDescArray + entry; | |
3148 | len = frag->size; | |
3149 | addr = ((void *) page_address(frag->page)) + frag->page_offset; | |
3150 | mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE); | |
3151 | ||
3152 | /* anti gcc 2.95.3 bugware (sic) */ | |
3153 | status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
3154 | ||
3155 | txd->opts1 = cpu_to_le32(status); | |
3156 | txd->addr = cpu_to_le64(mapping); | |
3157 | ||
3158 | tp->tx_skb[entry].len = len; | |
3159 | } | |
3160 | ||
3161 | if (cur_frag) { | |
3162 | tp->tx_skb[entry].skb = skb; | |
3163 | txd->opts1 |= cpu_to_le32(LastFrag); | |
3164 | } | |
3165 | ||
3166 | return cur_frag; | |
3167 | } | |
3168 | ||
3169 | static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev) | |
3170 | { | |
3171 | if (dev->features & NETIF_F_TSO) { | |
7967168c | 3172 | u32 mss = skb_shinfo(skb)->gso_size; |
1da177e4 LT |
3173 | |
3174 | if (mss) | |
3175 | return LargeSend | ((mss & MSSMask) << MSSShift); | |
3176 | } | |
84fa7933 | 3177 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
eddc9ec5 | 3178 | const struct iphdr *ip = ip_hdr(skb); |
1da177e4 LT |
3179 | |
3180 | if (ip->protocol == IPPROTO_TCP) | |
3181 | return IPCS | TCPCS; | |
3182 | else if (ip->protocol == IPPROTO_UDP) | |
3183 | return IPCS | UDPCS; | |
3184 | WARN_ON(1); /* we need a WARN() */ | |
3185 | } | |
3186 | return 0; | |
3187 | } | |
3188 | ||
3189 | static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
3190 | { | |
3191 | struct rtl8169_private *tp = netdev_priv(dev); | |
3192 | unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC; | |
3193 | struct TxDesc *txd = tp->TxDescArray + entry; | |
3194 | void __iomem *ioaddr = tp->mmio_addr; | |
3195 | dma_addr_t mapping; | |
3196 | u32 status, len; | |
3197 | u32 opts1; | |
188f4af0 | 3198 | int ret = NETDEV_TX_OK; |
5b0384f4 | 3199 | |
1da177e4 | 3200 | if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) { |
b57b7e5a SH |
3201 | if (netif_msg_drv(tp)) { |
3202 | printk(KERN_ERR | |
3203 | "%s: BUG! Tx Ring full when queue awake!\n", | |
3204 | dev->name); | |
3205 | } | |
1da177e4 LT |
3206 | goto err_stop; |
3207 | } | |
3208 | ||
3209 | if (unlikely(le32_to_cpu(txd->opts1) & DescOwn)) | |
3210 | goto err_stop; | |
3211 | ||
3212 | opts1 = DescOwn | rtl8169_tso_csum(skb, dev); | |
3213 | ||
3214 | frags = rtl8169_xmit_frags(tp, skb, opts1); | |
3215 | if (frags) { | |
3216 | len = skb_headlen(skb); | |
3217 | opts1 |= FirstFrag; | |
3218 | } else { | |
3219 | len = skb->len; | |
3220 | ||
3221 | if (unlikely(len < ETH_ZLEN)) { | |
5b057c6b | 3222 | if (skb_padto(skb, ETH_ZLEN)) |
1da177e4 LT |
3223 | goto err_update_stats; |
3224 | len = ETH_ZLEN; | |
3225 | } | |
3226 | ||
3227 | opts1 |= FirstFrag | LastFrag; | |
3228 | tp->tx_skb[entry].skb = skb; | |
3229 | } | |
3230 | ||
3231 | mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE); | |
3232 | ||
3233 | tp->tx_skb[entry].len = len; | |
3234 | txd->addr = cpu_to_le64(mapping); | |
3235 | txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb)); | |
3236 | ||
3237 | wmb(); | |
3238 | ||
3239 | /* anti gcc 2.95.3 bugware (sic) */ | |
3240 | status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC)); | |
3241 | txd->opts1 = cpu_to_le32(status); | |
3242 | ||
3243 | dev->trans_start = jiffies; | |
3244 | ||
3245 | tp->cur_tx += frags + 1; | |
3246 | ||
3247 | smp_wmb(); | |
3248 | ||
275391a4 | 3249 | RTL_W8(TxPoll, NPQ); /* set polling bit */ |
1da177e4 LT |
3250 | |
3251 | if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) { | |
3252 | netif_stop_queue(dev); | |
3253 | smp_rmb(); | |
3254 | if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS) | |
3255 | netif_wake_queue(dev); | |
3256 | } | |
3257 | ||
3258 | out: | |
3259 | return ret; | |
3260 | ||
3261 | err_stop: | |
3262 | netif_stop_queue(dev); | |
188f4af0 | 3263 | ret = NETDEV_TX_BUSY; |
1da177e4 | 3264 | err_update_stats: |
cebf8cc7 | 3265 | dev->stats.tx_dropped++; |
1da177e4 LT |
3266 | goto out; |
3267 | } | |
3268 | ||
3269 | static void rtl8169_pcierr_interrupt(struct net_device *dev) | |
3270 | { | |
3271 | struct rtl8169_private *tp = netdev_priv(dev); | |
3272 | struct pci_dev *pdev = tp->pci_dev; | |
3273 | void __iomem *ioaddr = tp->mmio_addr; | |
3274 | u16 pci_status, pci_cmd; | |
3275 | ||
3276 | pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); | |
3277 | pci_read_config_word(pdev, PCI_STATUS, &pci_status); | |
3278 | ||
b57b7e5a SH |
3279 | if (netif_msg_intr(tp)) { |
3280 | printk(KERN_ERR | |
3281 | "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n", | |
3282 | dev->name, pci_cmd, pci_status); | |
3283 | } | |
1da177e4 LT |
3284 | |
3285 | /* | |
3286 | * The recovery sequence below admits a very elaborated explanation: | |
3287 | * - it seems to work; | |
d03902b8 FR |
3288 | * - I did not see what else could be done; |
3289 | * - it makes iop3xx happy. | |
1da177e4 LT |
3290 | * |
3291 | * Feel free to adjust to your needs. | |
3292 | */ | |
a27993f3 | 3293 | if (pdev->broken_parity_status) |
d03902b8 FR |
3294 | pci_cmd &= ~PCI_COMMAND_PARITY; |
3295 | else | |
3296 | pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY; | |
3297 | ||
3298 | pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); | |
1da177e4 LT |
3299 | |
3300 | pci_write_config_word(pdev, PCI_STATUS, | |
3301 | pci_status & (PCI_STATUS_DETECTED_PARITY | | |
3302 | PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT | | |
3303 | PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT)); | |
3304 | ||
3305 | /* The infamous DAC f*ckup only happens at boot time */ | |
3306 | if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) { | |
b57b7e5a SH |
3307 | if (netif_msg_intr(tp)) |
3308 | printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name); | |
1da177e4 LT |
3309 | tp->cp_cmd &= ~PCIDAC; |
3310 | RTL_W16(CPlusCmd, tp->cp_cmd); | |
3311 | dev->features &= ~NETIF_F_HIGHDMA; | |
1da177e4 LT |
3312 | } |
3313 | ||
3314 | rtl8169_hw_reset(ioaddr); | |
d03902b8 FR |
3315 | |
3316 | rtl8169_schedule_work(dev, rtl8169_reinit_task); | |
1da177e4 LT |
3317 | } |
3318 | ||
07d3f51f FR |
3319 | static void rtl8169_tx_interrupt(struct net_device *dev, |
3320 | struct rtl8169_private *tp, | |
3321 | void __iomem *ioaddr) | |
1da177e4 LT |
3322 | { |
3323 | unsigned int dirty_tx, tx_left; | |
3324 | ||
1da177e4 LT |
3325 | dirty_tx = tp->dirty_tx; |
3326 | smp_rmb(); | |
3327 | tx_left = tp->cur_tx - dirty_tx; | |
3328 | ||
3329 | while (tx_left > 0) { | |
3330 | unsigned int entry = dirty_tx % NUM_TX_DESC; | |
3331 | struct ring_info *tx_skb = tp->tx_skb + entry; | |
3332 | u32 len = tx_skb->len; | |
3333 | u32 status; | |
3334 | ||
3335 | rmb(); | |
3336 | status = le32_to_cpu(tp->TxDescArray[entry].opts1); | |
3337 | if (status & DescOwn) | |
3338 | break; | |
3339 | ||
cebf8cc7 FR |
3340 | dev->stats.tx_bytes += len; |
3341 | dev->stats.tx_packets++; | |
1da177e4 LT |
3342 | |
3343 | rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry); | |
3344 | ||
3345 | if (status & LastFrag) { | |
3346 | dev_kfree_skb_irq(tx_skb->skb); | |
3347 | tx_skb->skb = NULL; | |
3348 | } | |
3349 | dirty_tx++; | |
3350 | tx_left--; | |
3351 | } | |
3352 | ||
3353 | if (tp->dirty_tx != dirty_tx) { | |
3354 | tp->dirty_tx = dirty_tx; | |
3355 | smp_wmb(); | |
3356 | if (netif_queue_stopped(dev) && | |
3357 | (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) { | |
3358 | netif_wake_queue(dev); | |
3359 | } | |
d78ae2dc FR |
3360 | /* |
3361 | * 8168 hack: TxPoll requests are lost when the Tx packets are | |
3362 | * too close. Let's kick an extra TxPoll request when a burst | |
3363 | * of start_xmit activity is detected (if it is not detected, | |
3364 | * it is slow enough). -- FR | |
3365 | */ | |
3366 | smp_rmb(); | |
3367 | if (tp->cur_tx != dirty_tx) | |
3368 | RTL_W8(TxPoll, NPQ); | |
1da177e4 LT |
3369 | } |
3370 | } | |
3371 | ||
126fa4b9 FR |
3372 | static inline int rtl8169_fragmented_frame(u32 status) |
3373 | { | |
3374 | return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag); | |
3375 | } | |
3376 | ||
1da177e4 LT |
3377 | static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc) |
3378 | { | |
3379 | u32 opts1 = le32_to_cpu(desc->opts1); | |
3380 | u32 status = opts1 & RxProtoMask; | |
3381 | ||
3382 | if (((status == RxProtoTCP) && !(opts1 & TCPFail)) || | |
3383 | ((status == RxProtoUDP) && !(opts1 & UDPFail)) || | |
3384 | ((status == RxProtoIP) && !(opts1 & IPFail))) | |
3385 | skb->ip_summed = CHECKSUM_UNNECESSARY; | |
3386 | else | |
3387 | skb->ip_summed = CHECKSUM_NONE; | |
3388 | } | |
3389 | ||
07d3f51f FR |
3390 | static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff, |
3391 | struct rtl8169_private *tp, int pkt_size, | |
3392 | dma_addr_t addr) | |
1da177e4 | 3393 | { |
b449655f SH |
3394 | struct sk_buff *skb; |
3395 | bool done = false; | |
1da177e4 | 3396 | |
b449655f SH |
3397 | if (pkt_size >= rx_copybreak) |
3398 | goto out; | |
1da177e4 | 3399 | |
07d3f51f | 3400 | skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN); |
b449655f SH |
3401 | if (!skb) |
3402 | goto out; | |
3403 | ||
07d3f51f FR |
3404 | pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size, |
3405 | PCI_DMA_FROMDEVICE); | |
86402234 | 3406 | skb_reserve(skb, NET_IP_ALIGN); |
b449655f SH |
3407 | skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size); |
3408 | *sk_buff = skb; | |
3409 | done = true; | |
3410 | out: | |
3411 | return done; | |
1da177e4 LT |
3412 | } |
3413 | ||
07d3f51f FR |
3414 | static int rtl8169_rx_interrupt(struct net_device *dev, |
3415 | struct rtl8169_private *tp, | |
bea3348e | 3416 | void __iomem *ioaddr, u32 budget) |
1da177e4 LT |
3417 | { |
3418 | unsigned int cur_rx, rx_left; | |
3419 | unsigned int delta, count; | |
3420 | ||
1da177e4 LT |
3421 | cur_rx = tp->cur_rx; |
3422 | rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx; | |
865c652d | 3423 | rx_left = min(rx_left, budget); |
1da177e4 | 3424 | |
4dcb7d33 | 3425 | for (; rx_left > 0; rx_left--, cur_rx++) { |
1da177e4 | 3426 | unsigned int entry = cur_rx % NUM_RX_DESC; |
126fa4b9 | 3427 | struct RxDesc *desc = tp->RxDescArray + entry; |
1da177e4 LT |
3428 | u32 status; |
3429 | ||
3430 | rmb(); | |
126fa4b9 | 3431 | status = le32_to_cpu(desc->opts1); |
1da177e4 LT |
3432 | |
3433 | if (status & DescOwn) | |
3434 | break; | |
4dcb7d33 | 3435 | if (unlikely(status & RxRES)) { |
b57b7e5a SH |
3436 | if (netif_msg_rx_err(tp)) { |
3437 | printk(KERN_INFO | |
3438 | "%s: Rx ERROR. status = %08x\n", | |
3439 | dev->name, status); | |
3440 | } | |
cebf8cc7 | 3441 | dev->stats.rx_errors++; |
1da177e4 | 3442 | if (status & (RxRWT | RxRUNT)) |
cebf8cc7 | 3443 | dev->stats.rx_length_errors++; |
1da177e4 | 3444 | if (status & RxCRC) |
cebf8cc7 | 3445 | dev->stats.rx_crc_errors++; |
9dccf611 FR |
3446 | if (status & RxFOVF) { |
3447 | rtl8169_schedule_work(dev, rtl8169_reset_task); | |
cebf8cc7 | 3448 | dev->stats.rx_fifo_errors++; |
9dccf611 | 3449 | } |
126fa4b9 | 3450 | rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
1da177e4 | 3451 | } else { |
1da177e4 | 3452 | struct sk_buff *skb = tp->Rx_skbuff[entry]; |
b449655f | 3453 | dma_addr_t addr = le64_to_cpu(desc->addr); |
1da177e4 | 3454 | int pkt_size = (status & 0x00001FFF) - 4; |
b449655f | 3455 | struct pci_dev *pdev = tp->pci_dev; |
1da177e4 | 3456 | |
126fa4b9 FR |
3457 | /* |
3458 | * The driver does not support incoming fragmented | |
3459 | * frames. They are seen as a symptom of over-mtu | |
3460 | * sized frames. | |
3461 | */ | |
3462 | if (unlikely(rtl8169_fragmented_frame(status))) { | |
cebf8cc7 FR |
3463 | dev->stats.rx_dropped++; |
3464 | dev->stats.rx_length_errors++; | |
126fa4b9 | 3465 | rtl8169_mark_to_asic(desc, tp->rx_buf_sz); |
4dcb7d33 | 3466 | continue; |
126fa4b9 FR |
3467 | } |
3468 | ||
1da177e4 | 3469 | rtl8169_rx_csum(skb, desc); |
bcf0bf90 | 3470 | |
07d3f51f | 3471 | if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) { |
b449655f SH |
3472 | pci_dma_sync_single_for_device(pdev, addr, |
3473 | pkt_size, PCI_DMA_FROMDEVICE); | |
3474 | rtl8169_mark_to_asic(desc, tp->rx_buf_sz); | |
3475 | } else { | |
a866bbf6 | 3476 | pci_unmap_single(pdev, addr, tp->rx_buf_sz, |
b449655f | 3477 | PCI_DMA_FROMDEVICE); |
1da177e4 LT |
3478 | tp->Rx_skbuff[entry] = NULL; |
3479 | } | |
3480 | ||
1da177e4 LT |
3481 | skb_put(skb, pkt_size); |
3482 | skb->protocol = eth_type_trans(skb, dev); | |
3483 | ||
3484 | if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0) | |
865c652d | 3485 | netif_receive_skb(skb); |
1da177e4 | 3486 | |
cebf8cc7 FR |
3487 | dev->stats.rx_bytes += pkt_size; |
3488 | dev->stats.rx_packets++; | |
1da177e4 | 3489 | } |
6dccd16b FR |
3490 | |
3491 | /* Work around for AMD plateform. */ | |
95e0918d | 3492 | if ((desc->opts2 & cpu_to_le32(0xfffe000)) && |
6dccd16b FR |
3493 | (tp->mac_version == RTL_GIGA_MAC_VER_05)) { |
3494 | desc->opts2 = 0; | |
3495 | cur_rx++; | |
3496 | } | |
1da177e4 LT |
3497 | } |
3498 | ||
3499 | count = cur_rx - tp->cur_rx; | |
3500 | tp->cur_rx = cur_rx; | |
3501 | ||
3502 | delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx); | |
b57b7e5a | 3503 | if (!delta && count && netif_msg_intr(tp)) |
1da177e4 LT |
3504 | printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name); |
3505 | tp->dirty_rx += delta; | |
3506 | ||
3507 | /* | |
3508 | * FIXME: until there is periodic timer to try and refill the ring, | |
3509 | * a temporary shortage may definitely kill the Rx process. | |
3510 | * - disable the asic to try and avoid an overflow and kick it again | |
3511 | * after refill ? | |
3512 | * - how do others driver handle this condition (Uh oh...). | |
3513 | */ | |
b57b7e5a | 3514 | if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp)) |
1da177e4 LT |
3515 | printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name); |
3516 | ||
3517 | return count; | |
3518 | } | |
3519 | ||
07d3f51f | 3520 | static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance) |
1da177e4 | 3521 | { |
07d3f51f | 3522 | struct net_device *dev = dev_instance; |
1da177e4 | 3523 | struct rtl8169_private *tp = netdev_priv(dev); |
1da177e4 | 3524 | void __iomem *ioaddr = tp->mmio_addr; |
1da177e4 | 3525 | int handled = 0; |
865c652d | 3526 | int status; |
1da177e4 | 3527 | |
865c652d | 3528 | status = RTL_R16(IntrStatus); |
1da177e4 | 3529 | |
865c652d FR |
3530 | /* hotplug/major error/no more work/shared irq */ |
3531 | if ((status == 0xffff) || !status) | |
3532 | goto out; | |
1da177e4 | 3533 | |
865c652d | 3534 | handled = 1; |
1da177e4 | 3535 | |
865c652d FR |
3536 | if (unlikely(!netif_running(dev))) { |
3537 | rtl8169_asic_down(ioaddr); | |
3538 | goto out; | |
3539 | } | |
1da177e4 | 3540 | |
865c652d FR |
3541 | status &= tp->intr_mask; |
3542 | RTL_W16(IntrStatus, | |
3543 | (status & RxFIFOOver) ? (status | RxOverflow) : status); | |
1da177e4 | 3544 | |
865c652d FR |
3545 | if (!(status & tp->intr_event)) |
3546 | goto out; | |
0e485150 | 3547 | |
865c652d FR |
3548 | /* Work around for rx fifo overflow */ |
3549 | if (unlikely(status & RxFIFOOver) && | |
3550 | (tp->mac_version == RTL_GIGA_MAC_VER_11)) { | |
3551 | netif_stop_queue(dev); | |
3552 | rtl8169_tx_timeout(dev); | |
3553 | goto out; | |
3554 | } | |
1da177e4 | 3555 | |
865c652d FR |
3556 | if (unlikely(status & SYSErr)) { |
3557 | rtl8169_pcierr_interrupt(dev); | |
3558 | goto out; | |
3559 | } | |
1da177e4 | 3560 | |
865c652d FR |
3561 | if (status & LinkChg) |
3562 | rtl8169_check_link_status(dev, tp, ioaddr); | |
1da177e4 | 3563 | |
865c652d FR |
3564 | if (status & tp->napi_event) { |
3565 | RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event); | |
3566 | tp->intr_mask = ~tp->napi_event; | |
313b0305 | 3567 | |
bea3348e SH |
3568 | if (likely(netif_rx_schedule_prep(dev, &tp->napi))) |
3569 | __netif_rx_schedule(dev, &tp->napi); | |
865c652d FR |
3570 | else if (netif_msg_intr(tp)) { |
3571 | printk(KERN_INFO "%s: interrupt %04x in poll\n", | |
3572 | dev->name, status); | |
b57b7e5a | 3573 | } |
1da177e4 LT |
3574 | } |
3575 | out: | |
3576 | return IRQ_RETVAL(handled); | |
3577 | } | |
3578 | ||
bea3348e | 3579 | static int rtl8169_poll(struct napi_struct *napi, int budget) |
1da177e4 | 3580 | { |
bea3348e SH |
3581 | struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi); |
3582 | struct net_device *dev = tp->dev; | |
1da177e4 | 3583 | void __iomem *ioaddr = tp->mmio_addr; |
bea3348e | 3584 | int work_done; |
1da177e4 | 3585 | |
bea3348e | 3586 | work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget); |
1da177e4 LT |
3587 | rtl8169_tx_interrupt(dev, tp, ioaddr); |
3588 | ||
bea3348e SH |
3589 | if (work_done < budget) { |
3590 | netif_rx_complete(dev, napi); | |
1da177e4 LT |
3591 | tp->intr_mask = 0xffff; |
3592 | /* | |
3593 | * 20040426: the barrier is not strictly required but the | |
3594 | * behavior of the irq handler could be less predictable | |
3595 | * without it. Btw, the lack of flush for the posted pci | |
3596 | * write is safe - FR | |
3597 | */ | |
3598 | smp_wmb(); | |
0e485150 | 3599 | RTL_W16(IntrMask, tp->intr_event); |
1da177e4 LT |
3600 | } |
3601 | ||
bea3348e | 3602 | return work_done; |
1da177e4 | 3603 | } |
1da177e4 | 3604 | |
523a6094 FR |
3605 | static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr) |
3606 | { | |
3607 | struct rtl8169_private *tp = netdev_priv(dev); | |
3608 | ||
3609 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) | |
3610 | return; | |
3611 | ||
3612 | dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff); | |
3613 | RTL_W32(RxMissed, 0); | |
3614 | } | |
3615 | ||
1da177e4 LT |
3616 | static void rtl8169_down(struct net_device *dev) |
3617 | { | |
3618 | struct rtl8169_private *tp = netdev_priv(dev); | |
3619 | void __iomem *ioaddr = tp->mmio_addr; | |
733b736c | 3620 | unsigned int intrmask; |
1da177e4 LT |
3621 | |
3622 | rtl8169_delete_timer(dev); | |
3623 | ||
3624 | netif_stop_queue(dev); | |
3625 | ||
93dd79e8 | 3626 | napi_disable(&tp->napi); |
93dd79e8 | 3627 | |
1da177e4 LT |
3628 | core_down: |
3629 | spin_lock_irq(&tp->lock); | |
3630 | ||
3631 | rtl8169_asic_down(ioaddr); | |
3632 | ||
523a6094 | 3633 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
3634 | |
3635 | spin_unlock_irq(&tp->lock); | |
3636 | ||
3637 | synchronize_irq(dev->irq); | |
3638 | ||
1da177e4 | 3639 | /* Give a racing hard_start_xmit a few cycles to complete. */ |
fbd568a3 | 3640 | synchronize_sched(); /* FIXME: should this be synchronize_irq()? */ |
1da177e4 LT |
3641 | |
3642 | /* | |
3643 | * And now for the 50k$ question: are IRQ disabled or not ? | |
3644 | * | |
3645 | * Two paths lead here: | |
3646 | * 1) dev->close | |
3647 | * -> netif_running() is available to sync the current code and the | |
3648 | * IRQ handler. See rtl8169_interrupt for details. | |
3649 | * 2) dev->change_mtu | |
3650 | * -> rtl8169_poll can not be issued again and re-enable the | |
3651 | * interruptions. Let's simply issue the IRQ down sequence again. | |
733b736c AP |
3652 | * |
3653 | * No loop if hotpluged or major error (0xffff). | |
1da177e4 | 3654 | */ |
733b736c AP |
3655 | intrmask = RTL_R16(IntrMask); |
3656 | if (intrmask && (intrmask != 0xffff)) | |
1da177e4 LT |
3657 | goto core_down; |
3658 | ||
3659 | rtl8169_tx_clear(tp); | |
3660 | ||
3661 | rtl8169_rx_clear(tp); | |
3662 | } | |
3663 | ||
3664 | static int rtl8169_close(struct net_device *dev) | |
3665 | { | |
3666 | struct rtl8169_private *tp = netdev_priv(dev); | |
3667 | struct pci_dev *pdev = tp->pci_dev; | |
3668 | ||
3669 | rtl8169_down(dev); | |
3670 | ||
3671 | free_irq(dev->irq, dev); | |
3672 | ||
1da177e4 LT |
3673 | pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray, |
3674 | tp->RxPhyAddr); | |
3675 | pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray, | |
3676 | tp->TxPhyAddr); | |
3677 | tp->TxDescArray = NULL; | |
3678 | tp->RxDescArray = NULL; | |
3679 | ||
3680 | return 0; | |
3681 | } | |
3682 | ||
07ce4064 | 3683 | static void rtl_set_rx_mode(struct net_device *dev) |
1da177e4 LT |
3684 | { |
3685 | struct rtl8169_private *tp = netdev_priv(dev); | |
3686 | void __iomem *ioaddr = tp->mmio_addr; | |
3687 | unsigned long flags; | |
3688 | u32 mc_filter[2]; /* Multicast hash filter */ | |
07d3f51f | 3689 | int rx_mode; |
1da177e4 LT |
3690 | u32 tmp = 0; |
3691 | ||
3692 | if (dev->flags & IFF_PROMISC) { | |
3693 | /* Unconditionally log net taps. */ | |
b57b7e5a SH |
3694 | if (netif_msg_link(tp)) { |
3695 | printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", | |
3696 | dev->name); | |
3697 | } | |
1da177e4 LT |
3698 | rx_mode = |
3699 | AcceptBroadcast | AcceptMulticast | AcceptMyPhys | | |
3700 | AcceptAllPhys; | |
3701 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
3702 | } else if ((dev->mc_count > multicast_filter_limit) | |
3703 | || (dev->flags & IFF_ALLMULTI)) { | |
3704 | /* Too many to filter perfectly -- accept all multicasts. */ | |
3705 | rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys; | |
3706 | mc_filter[1] = mc_filter[0] = 0xffffffff; | |
3707 | } else { | |
3708 | struct dev_mc_list *mclist; | |
07d3f51f FR |
3709 | unsigned int i; |
3710 | ||
1da177e4 LT |
3711 | rx_mode = AcceptBroadcast | AcceptMyPhys; |
3712 | mc_filter[1] = mc_filter[0] = 0; | |
3713 | for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; | |
3714 | i++, mclist = mclist->next) { | |
3715 | int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26; | |
3716 | mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); | |
3717 | rx_mode |= AcceptMulticast; | |
3718 | } | |
3719 | } | |
3720 | ||
3721 | spin_lock_irqsave(&tp->lock, flags); | |
3722 | ||
3723 | tmp = rtl8169_rx_config | rx_mode | | |
3724 | (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask); | |
3725 | ||
f887cce8 | 3726 | if (tp->mac_version > RTL_GIGA_MAC_VER_06) { |
1087f4f4 FR |
3727 | u32 data = mc_filter[0]; |
3728 | ||
3729 | mc_filter[0] = swab32(mc_filter[1]); | |
3730 | mc_filter[1] = swab32(data); | |
bcf0bf90 FR |
3731 | } |
3732 | ||
1da177e4 LT |
3733 | RTL_W32(MAR0 + 0, mc_filter[0]); |
3734 | RTL_W32(MAR0 + 4, mc_filter[1]); | |
3735 | ||
57a9f236 FR |
3736 | RTL_W32(RxConfig, tmp); |
3737 | ||
1da177e4 LT |
3738 | spin_unlock_irqrestore(&tp->lock, flags); |
3739 | } | |
3740 | ||
3741 | /** | |
3742 | * rtl8169_get_stats - Get rtl8169 read/write statistics | |
3743 | * @dev: The Ethernet Device to get statistics for | |
3744 | * | |
3745 | * Get TX/RX statistics for rtl8169 | |
3746 | */ | |
3747 | static struct net_device_stats *rtl8169_get_stats(struct net_device *dev) | |
3748 | { | |
3749 | struct rtl8169_private *tp = netdev_priv(dev); | |
3750 | void __iomem *ioaddr = tp->mmio_addr; | |
3751 | unsigned long flags; | |
3752 | ||
3753 | if (netif_running(dev)) { | |
3754 | spin_lock_irqsave(&tp->lock, flags); | |
523a6094 | 3755 | rtl8169_rx_missed(dev, ioaddr); |
1da177e4 LT |
3756 | spin_unlock_irqrestore(&tp->lock, flags); |
3757 | } | |
5b0384f4 | 3758 | |
cebf8cc7 | 3759 | return &dev->stats; |
1da177e4 LT |
3760 | } |
3761 | ||
5d06a99f FR |
3762 | #ifdef CONFIG_PM |
3763 | ||
3764 | static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state) | |
3765 | { | |
3766 | struct net_device *dev = pci_get_drvdata(pdev); | |
3767 | struct rtl8169_private *tp = netdev_priv(dev); | |
3768 | void __iomem *ioaddr = tp->mmio_addr; | |
3769 | ||
3770 | if (!netif_running(dev)) | |
1371fa6d | 3771 | goto out_pci_suspend; |
5d06a99f FR |
3772 | |
3773 | netif_device_detach(dev); | |
3774 | netif_stop_queue(dev); | |
3775 | ||
3776 | spin_lock_irq(&tp->lock); | |
3777 | ||
3778 | rtl8169_asic_down(ioaddr); | |
3779 | ||
523a6094 | 3780 | rtl8169_rx_missed(dev, ioaddr); |
5d06a99f FR |
3781 | |
3782 | spin_unlock_irq(&tp->lock); | |
3783 | ||
1371fa6d | 3784 | out_pci_suspend: |
5d06a99f | 3785 | pci_save_state(pdev); |
f23e7fda FR |
3786 | pci_enable_wake(pdev, pci_choose_state(pdev, state), |
3787 | (tp->features & RTL_FEATURE_WOL) ? 1 : 0); | |
5d06a99f | 3788 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
1371fa6d | 3789 | |
5d06a99f FR |
3790 | return 0; |
3791 | } | |
3792 | ||
3793 | static int rtl8169_resume(struct pci_dev *pdev) | |
3794 | { | |
3795 | struct net_device *dev = pci_get_drvdata(pdev); | |
3796 | ||
1371fa6d FR |
3797 | pci_set_power_state(pdev, PCI_D0); |
3798 | pci_restore_state(pdev); | |
3799 | pci_enable_wake(pdev, PCI_D0, 0); | |
3800 | ||
5d06a99f FR |
3801 | if (!netif_running(dev)) |
3802 | goto out; | |
3803 | ||
3804 | netif_device_attach(dev); | |
3805 | ||
5d06a99f FR |
3806 | rtl8169_schedule_work(dev, rtl8169_reset_task); |
3807 | out: | |
3808 | return 0; | |
3809 | } | |
3810 | ||
1765f95d FR |
3811 | static void rtl_shutdown(struct pci_dev *pdev) |
3812 | { | |
3813 | rtl8169_suspend(pdev, PMSG_SUSPEND); | |
3814 | } | |
3815 | ||
5d06a99f FR |
3816 | #endif /* CONFIG_PM */ |
3817 | ||
1da177e4 LT |
3818 | static struct pci_driver rtl8169_pci_driver = { |
3819 | .name = MODULENAME, | |
3820 | .id_table = rtl8169_pci_tbl, | |
3821 | .probe = rtl8169_init_one, | |
3822 | .remove = __devexit_p(rtl8169_remove_one), | |
3823 | #ifdef CONFIG_PM | |
3824 | .suspend = rtl8169_suspend, | |
3825 | .resume = rtl8169_resume, | |
1765f95d | 3826 | .shutdown = rtl_shutdown, |
1da177e4 LT |
3827 | #endif |
3828 | }; | |
3829 | ||
07d3f51f | 3830 | static int __init rtl8169_init_module(void) |
1da177e4 | 3831 | { |
29917620 | 3832 | return pci_register_driver(&rtl8169_pci_driver); |
1da177e4 LT |
3833 | } |
3834 | ||
07d3f51f | 3835 | static void __exit rtl8169_cleanup_module(void) |
1da177e4 LT |
3836 | { |
3837 | pci_unregister_driver(&rtl8169_pci_driver); | |
3838 | } | |
3839 | ||
3840 | module_init(rtl8169_init_module); | |
3841 | module_exit(rtl8169_cleanup_module); |