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r8169: fix early spinlock use
[mirror_ubuntu-zesty-kernel.git] / drivers / net / r8169.c
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1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
26
99f252b0 27#include <asm/system.h>
1da177e4
LT		 28#include <asm/io.h>
29#include <asm/irq.h>
30
865c652d 31#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 32#define MODULENAME "r8169"
33#define PFX MODULENAME ": "
34
35#ifdef RTL8169_DEBUG
36#define assert(expr) \
5b0384f4
FR		 37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 39 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 40 }
06fa7358
JP		 41#define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 43#else
44#define assert(expr) do {} while (0)
45#define dprintk(fmt, args...) do {} while (0)
46#endif /* RTL8169_DEBUG */
47
b57b7e5a 48#define R8169_MSG_DEFAULT \
f0e837d9 49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 50
1da177e4
LT		 51#define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
1da177e4 54/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
f71e1309 55static const int max_interrupt_work = 20;
1da177e4
LT		 56
57/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
58 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 59static const int multicast_filter_limit = 32;
1da177e4
LT		 60
61/* MAC address length */
62#define MAC_ADDR_LEN 6
63
9c14ceaf 64#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 65#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
66#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
67#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
07d3f51f 68#define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
1da177e4
LT		 69#define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
84/* write/read MMIO register */
85#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88#define RTL_R8(reg) readb (ioaddr + (reg))
89#define RTL_R16(reg) readw (ioaddr + (reg))
90#define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92enum mac_version {
ba6eb6ee
FR		 93 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
94 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
95 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
96 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
97 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 98 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 99 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
100 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
101 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
102 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 103 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 104 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
105 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
106 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
107 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
108 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
109 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
110 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
111 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
112 RTL_GIGA_MAC_VER_20 = 0x14 // 8168C
1da177e4
LT		 113};
114
1da177e4
LT		 115#define _R(NAME,MAC,MASK) \
116 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
117
3c6bee1d 118static const struct {
1da177e4
LT		 119 const char *name;
120 u8 mac_version;
121 u32 RxConfigMask; /* Clears the bits supported by this chip */
122} rtl_chip_info[] = {
ba6eb6ee
FR		 123 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
124 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
125 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
126 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
127 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 128 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 129 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
130 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
131 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
132 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 133 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
134 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
135 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
136 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 137 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
138 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
139 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
140 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
141 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
142 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880) // PCI-E
1da177e4
LT		 143};
144#undef _R
145
bcf0bf90
FR		 146enum cfg_version {
147 RTL_CFG_0 = 0x00,
148 RTL_CFG_1,
149 RTL_CFG_2
150};
151
07ce4064
FR		 152static void rtl_hw_start_8169(struct net_device *);
153static void rtl_hw_start_8168(struct net_device *);
154static void rtl_hw_start_8101(struct net_device *);
155
1da177e4 156static struct pci_device_id rtl8169_pci_tbl[] = {
bcf0bf90 157 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 158 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 159 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 160 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 161 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
162 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 163 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 164 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
165 { PCI_VENDOR_ID_LINKSYS, 0x1032,
166 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 167 { 0x0001, 0x8168,
168 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 169 {0,},
170};
171
172MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
173
174static int rx_copybreak = 200;
175static int use_dac;
b57b7e5a
SH		 176static struct {
177 u32 msg_enable;
178} debug = { -1 };
1da177e4 179
07d3f51f
FR		 180enum rtl_registers {
181 MAC0 = 0, /* Ethernet hardware address. */
773d2021 182 MAC4 = 4,
07d3f51f
FR		 183 MAR0 = 8, /* Multicast filter. */
184 CounterAddrLow = 0x10,
185 CounterAddrHigh = 0x14,
186 TxDescStartAddrLow = 0x20,
187 TxDescStartAddrHigh = 0x24,
188 TxHDescStartAddrLow = 0x28,
189 TxHDescStartAddrHigh = 0x2c,
190 FLASH = 0x30,
191 ERSR = 0x36,
192 ChipCmd = 0x37,
193 TxPoll = 0x38,
194 IntrMask = 0x3c,
195 IntrStatus = 0x3e,
196 TxConfig = 0x40,
197 RxConfig = 0x44,
198 RxMissed = 0x4c,
199 Cfg9346 = 0x50,
200 Config0 = 0x51,
201 Config1 = 0x52,
202 Config2 = 0x53,
203 Config3 = 0x54,
204 Config4 = 0x55,
205 Config5 = 0x56,
206 MultiIntr = 0x5c,
207 PHYAR = 0x60,
07d3f51f
FR		 208 PHYstatus = 0x6c,
209 RxMaxSize = 0xda,
210 CPlusCmd = 0xe0,
211 IntrMitigate = 0xe2,
212 RxDescAddrLow = 0xe4,
213 RxDescAddrHigh = 0xe8,
214 EarlyTxThres = 0xec,
215 FuncEvent = 0xf0,
216 FuncEventMask = 0xf4,
217 FuncPresetState = 0xf8,
218 FuncForceEvent = 0xfc,
1da177e4
LT		 219};
220
f162a5d1
FR		 221enum rtl8110_registers {
222 TBICSR = 0x64,
223 TBI_ANAR = 0x68,
224 TBI_LPAR = 0x6a,
225};
226
227enum rtl8168_8101_registers {
228 CSIDR = 0x64,
229 CSIAR = 0x68,
230#define CSIAR_FLAG 0x80000000
231#define CSIAR_WRITE_CMD 0x80000000
232#define CSIAR_BYTE_ENABLE 0x0f
233#define CSIAR_BYTE_ENABLE_SHIFT 12
234#define CSIAR_ADDR_MASK 0x0fff
235
236 EPHYAR = 0x80,
237#define EPHYAR_FLAG 0x80000000
238#define EPHYAR_WRITE_CMD 0x80000000
239#define EPHYAR_REG_MASK 0x1f
240#define EPHYAR_REG_SHIFT 16
241#define EPHYAR_DATA_MASK 0xffff
242 DBG_REG = 0xd1,
243#define FIX_NAK_1 (1 << 4)
244#define FIX_NAK_2 (1 << 3)
245};
246
07d3f51f 247enum rtl_register_content {
1da177e4 248 /* InterruptStatusBits */
07d3f51f
FR		 249 SYSErr = 0x8000,
250 PCSTimeout = 0x4000,
251 SWInt = 0x0100,
252 TxDescUnavail = 0x0080,
253 RxFIFOOver = 0x0040,
254 LinkChg = 0x0020,
255 RxOverflow = 0x0010,
256 TxErr = 0x0008,
257 TxOK = 0x0004,
258 RxErr = 0x0002,
259 RxOK = 0x0001,
1da177e4
LT		 260
261 /* RxStatusDesc */
9dccf611
FR		 262 RxFOVF = (1 << 23),
263 RxRWT = (1 << 22),
264 RxRES = (1 << 21),
265 RxRUNT = (1 << 20),
266 RxCRC = (1 << 19),
1da177e4
LT		 267
268 /* ChipCmdBits */
07d3f51f
FR		 269 CmdReset = 0x10,
270 CmdRxEnb = 0x08,
271 CmdTxEnb = 0x04,
272 RxBufEmpty = 0x01,
1da177e4 273
275391a4
FR		 274 /* TXPoll register p.5 */
275 HPQ = 0x80, /* Poll cmd on the high prio queue */
276 NPQ = 0x40, /* Poll cmd on the low prio queue */
277 FSWInt = 0x01, /* Forced software interrupt */
278
1da177e4 279 /* Cfg9346Bits */
07d3f51f
FR		 280 Cfg9346_Lock = 0x00,
281 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 282
283 /* rx_mode_bits */
07d3f51f
FR		 284 AcceptErr = 0x20,
285 AcceptRunt = 0x10,
286 AcceptBroadcast = 0x08,
287 AcceptMulticast = 0x04,
288 AcceptMyPhys = 0x02,
289 AcceptAllPhys = 0x01,
1da177e4
LT		 290
291 /* RxConfigBits */
07d3f51f
FR		 292 RxCfgFIFOShift = 13,
293 RxCfgDMAShift = 8,
1da177e4
LT		 294
295 /* TxConfigBits */
296 TxInterFrameGapShift = 24,
297 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
298
5d06a99f 299 /* Config1 register p.24 */
f162a5d1
FR		 300 LEDS1 = (1 << 7),
301 LEDS0 = (1 << 6),
fbac58fc 302 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 303 Speed_down = (1 << 4),
304 MEMMAP = (1 << 3),
305 IOMAP = (1 << 2),
306 VPD = (1 << 1),
5d06a99f
FR		 307 PMEnable = (1 << 0), /* Power Management Enable */
308
6dccd16b
FR		 309 /* Config2 register p. 25 */
310 PCI_Clock_66MHz = 0x01,
311 PCI_Clock_33MHz = 0x00,
312
61a4dcc2
FR		 313 /* Config3 register p.25 */
314 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
315 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 316 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 317
5d06a99f 318 /* Config5 register p.27 */
61a4dcc2
FR		 319 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
320 MWF = (1 << 5), /* Accept Multicast wakeup frame */
321 UWF = (1 << 4), /* Accept Unicast wakeup frame */
322 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 323 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
324
1da177e4
LT		 325 /* TBICSR p.28 */
326 TBIReset = 0x80000000,
327 TBILoopback = 0x40000000,
328 TBINwEnable = 0x20000000,
329 TBINwRestart = 0x10000000,
330 TBILinkOk = 0x02000000,
331 TBINwComplete = 0x01000000,
332
333 /* CPlusCmd p.31 */
f162a5d1
FR		 334 EnableBist = (1 << 15), // 8168 8101
335 Mac_dbgo_oe = (1 << 14), // 8168 8101
336 Normal_mode = (1 << 13), // unused
337 Force_half_dup = (1 << 12), // 8168 8101
338 Force_rxflow_en = (1 << 11), // 8168 8101
339 Force_txflow_en = (1 << 10), // 8168 8101
340 Cxpl_dbg_sel = (1 << 9), // 8168 8101
341 ASF = (1 << 8), // 8168 8101
342 PktCntrDisable = (1 << 7), // 8168 8101
343 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 344 RxVlan = (1 << 6),
345 RxChkSum = (1 << 5),
346 PCIDAC = (1 << 4),
347 PCIMulRW = (1 << 3),
0e485150
FR		 348 INTT_0 = 0x0000, // 8168
349 INTT_1 = 0x0001, // 8168
350 INTT_2 = 0x0002, // 8168
351 INTT_3 = 0x0003, // 8168
1da177e4
LT		 352
353 /* rtl8169_PHYstatus */
07d3f51f
FR		 354 TBI_Enable = 0x80,
355 TxFlowCtrl = 0x40,
356 RxFlowCtrl = 0x20,
357 _1000bpsF = 0x10,
358 _100bps = 0x08,
359 _10bps = 0x04,
360 LinkStatus = 0x02,
361 FullDup = 0x01,
1da177e4 362
1da177e4 363 /* _TBICSRBit */
07d3f51f 364 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 365
366 /* DumpCounterCommand */
07d3f51f 367 CounterDump = 0x8,
1da177e4
LT		 368};
369
07d3f51f 370enum desc_status_bit {
1da177e4
LT		 371 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
372 RingEnd = (1 << 30), /* End of descriptor ring */
373 FirstFrag = (1 << 29), /* First segment of a packet */
374 LastFrag = (1 << 28), /* Final segment of a packet */
375
376 /* Tx private */
377 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
378 MSSShift = 16, /* MSS value position */
379 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
380 IPCS = (1 << 18), /* Calculate IP checksum */
381 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
382 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
383 TxVlanTag = (1 << 17), /* Add VLAN tag */
384
385 /* Rx private */
386 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
387 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
388
389#define RxProtoUDP (PID1)
390#define RxProtoTCP (PID0)
391#define RxProtoIP (PID1 | PID0)
392#define RxProtoMask RxProtoIP
393
394 IPFail = (1 << 16), /* IP checksum failed */
395 UDPFail = (1 << 15), /* UDP/IP checksum failed */
396 TCPFail = (1 << 14), /* TCP/IP checksum failed */
397 RxVlanTag = (1 << 16), /* VLAN tag available */
398};
399
400#define RsvdMask 0x3fffc000
401
402struct TxDesc {
6cccd6e7
REB		 403 __le32 opts1;
404 __le32 opts2;
405 __le64 addr;
1da177e4
LT		 406};
407
408struct RxDesc {
6cccd6e7
REB		 409 __le32 opts1;
410 __le32 opts2;
411 __le64 addr;
1da177e4
LT		 412};
413
414struct ring_info {
415 struct sk_buff *skb;
416 u32 len;
417 u8 __pad[sizeof(void *) - sizeof(u32)];
418};
419
f23e7fda 420enum features {
ccdffb9a
FR		 421 RTL_FEATURE_WOL = (1 << 0),
422 RTL_FEATURE_MSI = (1 << 1),
423 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 424};
425
1da177e4
LT		 426struct rtl8169_private {
427 void __iomem *mmio_addr; /* memory map physical address */
428 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 429 struct net_device *dev;
bea3348e 430 struct napi_struct napi;
1da177e4 431 spinlock_t lock; /* spin lock flag */
b57b7e5a 432 u32 msg_enable;
1da177e4
LT		 433 int chipset;
434 int mac_version;
1da177e4
LT		 435 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
436 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
437 u32 dirty_rx;
438 u32 dirty_tx;
439 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
440 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
441 dma_addr_t TxPhyAddr;
442 dma_addr_t RxPhyAddr;
443 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
444 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
bcf0bf90 445 unsigned align;
1da177e4
LT		 446 unsigned rx_buf_sz;
447 struct timer_list timer;
448 u16 cp_cmd;
0e485150
FR		 449 u16 intr_event;
450 u16 napi_event;
1da177e4
LT		 451 u16 intr_mask;
452 int phy_auto_nego_reg;
453 int phy_1000_ctrl_reg;
454#ifdef CONFIG_R8169_VLAN
455 struct vlan_group *vlgrp;
456#endif
457 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 458 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
1da177e4 459 void (*phy_reset_enable)(void __iomem *);
07ce4064 460 void (*hw_start)(struct net_device *);
1da177e4
LT		 461 unsigned int (*phy_reset_pending)(void __iomem *);
462 unsigned int (*link_ok)(void __iomem *);
9c14ceaf 463 int pcie_cap;
c4028958 464 struct delayed_work task;
f23e7fda 465 unsigned features;
ccdffb9a
FR		 466
467 struct mii_if_info mii;
1da177e4
LT		 468};
469
979b6c13 470MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 471MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 472module_param(rx_copybreak, int, 0);
1b7efd58 473MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
1da177e4
LT		 474module_param(use_dac, int, 0);
475MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 476module_param_named(debug, debug.msg_enable, int, 0);
477MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 478MODULE_LICENSE("GPL");
479MODULE_VERSION(RTL8169_VERSION);
480
481static int rtl8169_open(struct net_device *dev);
482static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
7d12e780 483static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 484static int rtl8169_init_ring(struct net_device *dev);
07ce4064 485static void rtl_hw_start(struct net_device *dev);
1da177e4 486static int rtl8169_close(struct net_device *dev);
07ce4064 487static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 488static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 489static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 490static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 491 void __iomem *, u32 budget);
4dcb7d33 492static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 493static void rtl8169_down(struct net_device *dev);
99f252b0 494static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 495static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 496
1da177e4 497static const unsigned int rtl8169_rx_config =
5b0384f4 498 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 499
07d3f51f 500static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 501{
502 int i;
503
a6baf3af 504 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 505
2371408c 506 for (i = 20; i > 0; i--) {
07d3f51f
FR		 507 /*
508 * Check if the RTL8169 has completed writing to the specified
509 * MII register.
510 */
5b0384f4 511 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 512 break;
2371408c 513 udelay(25);
1da177e4
LT		 514 }
515}
516
07d3f51f 517static int mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 518{
519 int i, value = -1;
520
a6baf3af 521 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 522
2371408c 523 for (i = 20; i > 0; i--) {
07d3f51f
FR		 524 /*
525 * Check if the RTL8169 has completed retrieving data from
526 * the specified MII register.
527 */
1da177e4 528 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 529 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 530 break;
531 }
2371408c 532 udelay(25);
1da177e4
LT		 533 }
534 return value;
535}
536
dacf8154
FR		 537static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
538{
539 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
540}
541
ccdffb9a
FR		 542static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
543 int val)
544{
545 struct rtl8169_private *tp = netdev_priv(dev);
546 void __iomem *ioaddr = tp->mmio_addr;
547
548 mdio_write(ioaddr, location, val);
549}
550
551static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
552{
553 struct rtl8169_private *tp = netdev_priv(dev);
554 void __iomem *ioaddr = tp->mmio_addr;
555
556 return mdio_read(ioaddr, location);
557}
558
dacf8154
FR		 559static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
560{
561 unsigned int i;
562
563 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
564 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
565
566 for (i = 0; i < 100; i++) {
567 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
568 break;
569 udelay(10);
570 }
571}
572
573static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
574{
575 u16 value = 0xffff;
576 unsigned int i;
577
578 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
579
580 for (i = 0; i < 100; i++) {
581 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
582 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
583 break;
584 }
585 udelay(10);
586 }
587
588 return value;
589}
590
591static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
592{
593 unsigned int i;
594
595 RTL_W32(CSIDR, value);
596 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
597 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
598
599 for (i = 0; i < 100; i++) {
600 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
601 break;
602 udelay(10);
603 }
604}
605
606static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
607{
608 u32 value = ~0x00;
609 unsigned int i;
610
611 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
612 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
613
614 for (i = 0; i < 100; i++) {
615 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
616 value = RTL_R32(CSIDR);
617 break;
618 }
619 udelay(10);
620 }
621
622 return value;
623}
624
1da177e4
LT		 625static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
626{
627 RTL_W16(IntrMask, 0x0000);
628
629 RTL_W16(IntrStatus, 0xffff);
630}
631
632static void rtl8169_asic_down(void __iomem *ioaddr)
633{
634 RTL_W8(ChipCmd, 0x00);
635 rtl8169_irq_mask_and_ack(ioaddr);
636 RTL_R16(CPlusCmd);
637}
638
639static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
640{
641 return RTL_R32(TBICSR) & TBIReset;
642}
643
644static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
645{
64e4bfb4 646 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 647}
648
649static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
650{
651 return RTL_R32(TBICSR) & TBILinkOk;
652}
653
654static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
655{
656 return RTL_R8(PHYstatus) & LinkStatus;
657}
658
659static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
660{
661 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
662}
663
664static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
665{
666 unsigned int val;
667
9e0db8ef
FR		 668 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
669 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
1da177e4
LT		 670}
671
672static void rtl8169_check_link_status(struct net_device *dev,
07d3f51f
FR		 673 struct rtl8169_private *tp,
674 void __iomem *ioaddr)
1da177e4
LT		 675{
676 unsigned long flags;
677
678 spin_lock_irqsave(&tp->lock, flags);
679 if (tp->link_ok(ioaddr)) {
680 netif_carrier_on(dev);
b57b7e5a
SH		 681 if (netif_msg_ifup(tp))
682 printk(KERN_INFO PFX "%s: link up\n", dev->name);
683 } else {
684 if (netif_msg_ifdown(tp))
685 printk(KERN_INFO PFX "%s: link down\n", dev->name);
1da177e4 686 netif_carrier_off(dev);
b57b7e5a 687 }
1da177e4
LT		 688 spin_unlock_irqrestore(&tp->lock, flags);
689}
690
61a4dcc2
FR		 691static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
692{
693 struct rtl8169_private *tp = netdev_priv(dev);
694 void __iomem *ioaddr = tp->mmio_addr;
695 u8 options;
696
697 wol->wolopts = 0;
698
699#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
700 wol->supported = WAKE_ANY;
701
702 spin_lock_irq(&tp->lock);
703
704 options = RTL_R8(Config1);
705 if (!(options & PMEnable))
706 goto out_unlock;
707
708 options = RTL_R8(Config3);
709 if (options & LinkUp)
710 wol->wolopts |= WAKE_PHY;
711 if (options & MagicPacket)
712 wol->wolopts |= WAKE_MAGIC;
713
714 options = RTL_R8(Config5);
715 if (options & UWF)
716 wol->wolopts |= WAKE_UCAST;
717 if (options & BWF)
5b0384f4 718 wol->wolopts |= WAKE_BCAST;
61a4dcc2 719 if (options & MWF)
5b0384f4 720 wol->wolopts |= WAKE_MCAST;
61a4dcc2
FR		 721
722out_unlock:
723 spin_unlock_irq(&tp->lock);
724}
725
726static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
727{
728 struct rtl8169_private *tp = netdev_priv(dev);
729 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 730 unsigned int i;
61a4dcc2
FR		 731 static struct {
732 u32 opt;
733 u16 reg;
734 u8 mask;
735 } cfg[] = {
736 { WAKE_ANY, Config1, PMEnable },
737 { WAKE_PHY, Config3, LinkUp },
738 { WAKE_MAGIC, Config3, MagicPacket },
739 { WAKE_UCAST, Config5, UWF },
740 { WAKE_BCAST, Config5, BWF },
741 { WAKE_MCAST, Config5, MWF },
742 { WAKE_ANY, Config5, LanWake }
743 };
744
745 spin_lock_irq(&tp->lock);
746
747 RTL_W8(Cfg9346, Cfg9346_Unlock);
748
749 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
750 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
751 if (wol->wolopts & cfg[i].opt)
752 options |= cfg[i].mask;
753 RTL_W8(cfg[i].reg, options);
754 }
755
756 RTL_W8(Cfg9346, Cfg9346_Lock);
757
f23e7fda
FR		 758 if (wol->wolopts)
759 tp->features |= RTL_FEATURE_WOL;
760 else
761 tp->features &= ~RTL_FEATURE_WOL;
8b76ab39 762 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
61a4dcc2
FR		 763
764 spin_unlock_irq(&tp->lock);
765
766 return 0;
767}
768
1da177e4
LT		 769static void rtl8169_get_drvinfo(struct net_device *dev,
770 struct ethtool_drvinfo *info)
771{
772 struct rtl8169_private *tp = netdev_priv(dev);
773
774 strcpy(info->driver, MODULENAME);
775 strcpy(info->version, RTL8169_VERSION);
776 strcpy(info->bus_info, pci_name(tp->pci_dev));
777}
778
779static int rtl8169_get_regs_len(struct net_device *dev)
780{
781 return R8169_REGS_SIZE;
782}
783
784static int rtl8169_set_speed_tbi(struct net_device *dev,
785 u8 autoneg, u16 speed, u8 duplex)
786{
787 struct rtl8169_private *tp = netdev_priv(dev);
788 void __iomem *ioaddr = tp->mmio_addr;
789 int ret = 0;
790 u32 reg;
791
792 reg = RTL_R32(TBICSR);
793 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
794 (duplex == DUPLEX_FULL)) {
795 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
796 } else if (autoneg == AUTONEG_ENABLE)
797 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
798 else {
b57b7e5a
SH		 799 if (netif_msg_link(tp)) {
800 printk(KERN_WARNING "%s: "
801 "incorrect speed setting refused in TBI mode\n",
802 dev->name);
803 }
1da177e4
LT		 804 ret = -EOPNOTSUPP;
805 }
806
807 return ret;
808}
809
810static int rtl8169_set_speed_xmii(struct net_device *dev,
811 u8 autoneg, u16 speed, u8 duplex)
812{
813 struct rtl8169_private *tp = netdev_priv(dev);
814 void __iomem *ioaddr = tp->mmio_addr;
815 int auto_nego, giga_ctrl;
816
64e4bfb4
FR		 817 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
818 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
819 ADVERTISE_100HALF | ADVERTISE_100FULL);
820 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
821 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 822
823 if (autoneg == AUTONEG_ENABLE) {
64e4bfb4
FR		 824 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
825 ADVERTISE_100HALF | ADVERTISE_100FULL);
826 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 827 } else {
828 if (speed == SPEED_10)
64e4bfb4 829 auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
1da177e4 830 else if (speed == SPEED_100)
64e4bfb4 831 auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
1da177e4 832 else if (speed == SPEED_1000)
64e4bfb4 833 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
1da177e4
LT		 834
835 if (duplex == DUPLEX_HALF)
64e4bfb4 836 auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
726ecdcf
AG		 837
838 if (duplex == DUPLEX_FULL)
64e4bfb4 839 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
bcf0bf90
FR		 840
841 /* This tweak comes straight from Realtek's driver. */
842 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
e3cf0cc0
FR		 843 ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
844 (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
64e4bfb4 845 auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
bcf0bf90
FR		 846 }
847 }
848
2857ffb7
FR		 849 /* The 8100e/8101e/8102e do Fast Ethernet only. */
850 if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
851 (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
852 (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
853 (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
854 (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
bcf0bf90 855 (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
e3cf0cc0
FR		 856 (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
857 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
64e4bfb4 858 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
bcf0bf90
FR		 859 netif_msg_link(tp)) {
860 printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
861 dev->name);
862 }
64e4bfb4 863 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1da177e4
LT		 864 }
865
623a1593
FR		 866 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
867
e3cf0cc0
FR		 868 if ((tp->mac_version == RTL_GIGA_MAC_VER_12) ||
869 (tp->mac_version == RTL_GIGA_MAC_VER_17)) {
2584fbc3
RS		 870 /* Vendor specific (0x1f) and reserved (0x0e) MII registers. */
871 mdio_write(ioaddr, 0x1f, 0x0000);
872 mdio_write(ioaddr, 0x0e, 0x0000);
873 }
874
1da177e4
LT		 875 tp->phy_auto_nego_reg = auto_nego;
876 tp->phy_1000_ctrl_reg = giga_ctrl;
877
64e4bfb4
FR		 878 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
879 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
880 mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1da177e4
LT		 881 return 0;
882}
883
884static int rtl8169_set_speed(struct net_device *dev,
885 u8 autoneg, u16 speed, u8 duplex)
886{
887 struct rtl8169_private *tp = netdev_priv(dev);
888 int ret;
889
890 ret = tp->set_speed(dev, autoneg, speed, duplex);
891
64e4bfb4 892 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 893 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
894
895 return ret;
896}
897
898static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
899{
900 struct rtl8169_private *tp = netdev_priv(dev);
901 unsigned long flags;
902 int ret;
903
904 spin_lock_irqsave(&tp->lock, flags);
905 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
906 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 907
1da177e4
LT		 908 return ret;
909}
910
911static u32 rtl8169_get_rx_csum(struct net_device *dev)
912{
913 struct rtl8169_private *tp = netdev_priv(dev);
914
915 return tp->cp_cmd & RxChkSum;
916}
917
918static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
919{
920 struct rtl8169_private *tp = netdev_priv(dev);
921 void __iomem *ioaddr = tp->mmio_addr;
922 unsigned long flags;
923
924 spin_lock_irqsave(&tp->lock, flags);
925
926 if (data)
927 tp->cp_cmd |= RxChkSum;
928 else
929 tp->cp_cmd &= ~RxChkSum;
930
931 RTL_W16(CPlusCmd, tp->cp_cmd);
932 RTL_R16(CPlusCmd);
933
934 spin_unlock_irqrestore(&tp->lock, flags);
935
936 return 0;
937}
938
939#ifdef CONFIG_R8169_VLAN
940
941static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
942 struct sk_buff *skb)
943{
944 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
945 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
946}
947
948static void rtl8169_vlan_rx_register(struct net_device *dev,
949 struct vlan_group *grp)
950{
951 struct rtl8169_private *tp = netdev_priv(dev);
952 void __iomem *ioaddr = tp->mmio_addr;
953 unsigned long flags;
954
955 spin_lock_irqsave(&tp->lock, flags);
956 tp->vlgrp = grp;
957 if (tp->vlgrp)
958 tp->cp_cmd |= RxVlan;
959 else
960 tp->cp_cmd &= ~RxVlan;
961 RTL_W16(CPlusCmd, tp->cp_cmd);
962 RTL_R16(CPlusCmd);
963 spin_unlock_irqrestore(&tp->lock, flags);
964}
965
1da177e4
LT		 966static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
967 struct sk_buff *skb)
968{
969 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 970 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 971 int ret;
972
865c652d
FR		 973 if (vlgrp && (opts2 & RxVlanTag)) {
974 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
1da177e4
LT		 975 ret = 0;
976 } else
977 ret = -1;
978 desc->opts2 = 0;
979 return ret;
980}
981
982#else /* !CONFIG_R8169_VLAN */
983
984static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
985 struct sk_buff *skb)
986{
987 return 0;
988}
989
990static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
991 struct sk_buff *skb)
992{
993 return -1;
994}
995
996#endif
997
ccdffb9a 998static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 999{
1000 struct rtl8169_private *tp = netdev_priv(dev);
1001 void __iomem *ioaddr = tp->mmio_addr;
1002 u32 status;
1003
1004 cmd->supported =
1005 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1006 cmd->port = PORT_FIBRE;
1007 cmd->transceiver = XCVR_INTERNAL;
1008
1009 status = RTL_R32(TBICSR);
1010 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1011 cmd->autoneg = !!(status & TBINwEnable);
1012
1013 cmd->speed = SPEED_1000;
1014 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1015
1016 return 0;
1da177e4
LT		 1017}
1018
ccdffb9a 1019static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1020{
1021 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1022
1023 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1024}
1025
1026static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1027{
1028 struct rtl8169_private *tp = netdev_priv(dev);
1029 unsigned long flags;
ccdffb9a 1030 int rc;
1da177e4
LT		 1031
1032 spin_lock_irqsave(&tp->lock, flags);
1033
ccdffb9a 1034 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1035
1036 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1037 return rc;
1da177e4
LT		 1038}
1039
1040static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1041 void *p)
1042{
5b0384f4
FR		 1043 struct rtl8169_private *tp = netdev_priv(dev);
1044 unsigned long flags;
1da177e4 1045
5b0384f4
FR		 1046 if (regs->len > R8169_REGS_SIZE)
1047 regs->len = R8169_REGS_SIZE;
1da177e4 1048
5b0384f4
FR		 1049 spin_lock_irqsave(&tp->lock, flags);
1050 memcpy_fromio(p, tp->mmio_addr, regs->len);
1051 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1052}
1053
b57b7e5a
SH		 1054static u32 rtl8169_get_msglevel(struct net_device *dev)
1055{
1056 struct rtl8169_private *tp = netdev_priv(dev);
1057
1058 return tp->msg_enable;
1059}
1060
1061static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1062{
1063 struct rtl8169_private *tp = netdev_priv(dev);
1064
1065 tp->msg_enable = value;
1066}
1067
d4a3a0fc
SH		 1068static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1069 "tx_packets",
1070 "rx_packets",
1071 "tx_errors",
1072 "rx_errors",
1073 "rx_missed",
1074 "align_errors",
1075 "tx_single_collisions",
1076 "tx_multi_collisions",
1077 "unicast",
1078 "broadcast",
1079 "multicast",
1080 "tx_aborted",
1081 "tx_underrun",
1082};
1083
1084struct rtl8169_counters {
b1eab701
AV		 1085 __le64 tx_packets;
1086 __le64 rx_packets;
1087 __le64 tx_errors;
1088 __le32 rx_errors;
1089 __le16 rx_missed;
1090 __le16 align_errors;
1091 __le32 tx_one_collision;
1092 __le32 tx_multi_collision;
1093 __le64 rx_unicast;
1094 __le64 rx_broadcast;
1095 __le32 rx_multicast;
1096 __le16 tx_aborted;
1097 __le16 tx_underun;
d4a3a0fc
SH		 1098};
1099
b9f2c044 1100static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1101{
b9f2c044
JG		 1102 switch (sset) {
1103 case ETH_SS_STATS:
1104 return ARRAY_SIZE(rtl8169_gstrings);
1105 default:
1106 return -EOPNOTSUPP;
1107 }
d4a3a0fc
SH		 1108}
1109
1110static void rtl8169_get_ethtool_stats(struct net_device *dev,
1111 struct ethtool_stats *stats, u64 *data)
1112{
1113 struct rtl8169_private *tp = netdev_priv(dev);
1114 void __iomem *ioaddr = tp->mmio_addr;
1115 struct rtl8169_counters *counters;
1116 dma_addr_t paddr;
1117 u32 cmd;
1118
1119 ASSERT_RTNL();
1120
1121 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1122 if (!counters)
1123 return;
1124
1125 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1126 cmd = (u64)paddr & DMA_32BIT_MASK;
1127 RTL_W32(CounterAddrLow, cmd);
1128 RTL_W32(CounterAddrLow, cmd | CounterDump);
1129
1130 while (RTL_R32(CounterAddrLow) & CounterDump) {
1131 if (msleep_interruptible(1))
1132 break;
1133 }
1134
1135 RTL_W32(CounterAddrLow, 0);
1136 RTL_W32(CounterAddrHigh, 0);
1137
5b0384f4 1138 data[0] = le64_to_cpu(counters->tx_packets);
d4a3a0fc
SH		 1139 data[1] = le64_to_cpu(counters->rx_packets);
1140 data[2] = le64_to_cpu(counters->tx_errors);
1141 data[3] = le32_to_cpu(counters->rx_errors);
1142 data[4] = le16_to_cpu(counters->rx_missed);
1143 data[5] = le16_to_cpu(counters->align_errors);
1144 data[6] = le32_to_cpu(counters->tx_one_collision);
1145 data[7] = le32_to_cpu(counters->tx_multi_collision);
1146 data[8] = le64_to_cpu(counters->rx_unicast);
1147 data[9] = le64_to_cpu(counters->rx_broadcast);
1148 data[10] = le32_to_cpu(counters->rx_multicast);
1149 data[11] = le16_to_cpu(counters->tx_aborted);
1150 data[12] = le16_to_cpu(counters->tx_underun);
1151
1152 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1153}
1154
1155static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1156{
1157 switch(stringset) {
1158 case ETH_SS_STATS:
1159 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1160 break;
1161 }
1162}
1163
7282d491 1164static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1165 .get_drvinfo = rtl8169_get_drvinfo,
1166 .get_regs_len = rtl8169_get_regs_len,
1167 .get_link = ethtool_op_get_link,
1168 .get_settings = rtl8169_get_settings,
1169 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1170 .get_msglevel = rtl8169_get_msglevel,
1171 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1172 .get_rx_csum = rtl8169_get_rx_csum,
1173 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1174 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1175 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1176 .set_tso = ethtool_op_set_tso,
1177 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1178 .get_wol = rtl8169_get_wol,
1179 .set_wol = rtl8169_set_wol,
d4a3a0fc 1180 .get_strings = rtl8169_get_strings,
b9f2c044 1181 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1182 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1183};
1184
07d3f51f
FR		 1185static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1186 int bitnum, int bitval)
1da177e4
LT		 1187{
1188 int val;
1189
1190 val = mdio_read(ioaddr, reg);
1191 val = (bitval == 1) ?
1192 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
5b0384f4 1193 mdio_write(ioaddr, reg, val & 0xffff);
1da177e4
LT		 1194}
1195
07d3f51f
FR		 1196static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1197 void __iomem *ioaddr)
1da177e4 1198{
0e485150
FR		 1199 /*
1200 * The driver currently handles the 8168Bf and the 8168Be identically
1201 * but they can be identified more specifically through the test below
1202 * if needed:
1203 *
1204 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1205 *
1206 * Same thing for the 8101Eb and the 8101Ec:
1207 *
1208 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1209 */
1da177e4
LT		 1210 const struct {
1211 u32 mask;
e3cf0cc0 1212 u32 val;
1da177e4
LT		 1213 int mac_version;
1214 } mac_info[] = {
e3cf0cc0
FR		 1215 /* 8168B family. */
1216 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1217 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1218 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1219 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_20 },
1220
1221 /* 8168B family. */
1222 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1223 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1224 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1225 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1226
1227 /* 8101 family. */
2857ffb7
FR		 1228 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1229 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1230 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1231 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1232 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1233 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1234 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1235 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1236 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1237 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1238 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1239 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1240 /* FIXME: where did these entries come from ? -- FR */
1241 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1242 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1243
1244 /* 8110 family. */
1245 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1246 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1247 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1248 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1249 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1250 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1251
1252 { 0x00000000, 0x00000000, RTL_GIGA_MAC_VER_01 } /* Catch-all */
1da177e4
LT		 1253 }, *p = mac_info;
1254 u32 reg;
1255
e3cf0cc0
FR		 1256 reg = RTL_R32(TxConfig);
1257 while ((reg & p->mask) != p->val)
1da177e4
LT		 1258 p++;
1259 tp->mac_version = p->mac_version;
e3cf0cc0
FR		 1260
1261 if (p->mask == 0x00000000) {
1262 struct pci_dev *pdev = tp->pci_dev;
1263
1264 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1265 }
1da177e4
LT		 1266}
1267
1268static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1269{
bcf0bf90 1270 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1271}
1272
867763c1
FR		 1273struct phy_reg {
1274 u16 reg;
1275 u16 val;
1276};
1277
1278static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1279{
1280 while (len-- > 0) {
1281 mdio_write(ioaddr, regs->reg, regs->val);
1282 regs++;
1283 }
1284}
1285
5615d9f1 1286static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1da177e4 1287{
1da177e4
LT		 1288 struct {
1289 u16 regs[5]; /* Beware of bit-sign propagation */
1290 } phy_magic[5] = { {
1291 { 0x0000, //w 4 15 12 0
1292 0x00a1, //w 3 15 0 00a1
1293 0x0008, //w 2 15 0 0008
1294 0x1020, //w 1 15 0 1020
1295 0x1000 } },{ //w 0 15 0 1000
1296 { 0x7000, //w 4 15 12 7
1297 0xff41, //w 3 15 0 ff41
1298 0xde60, //w 2 15 0 de60
1299 0x0140, //w 1 15 0 0140
1300 0x0077 } },{ //w 0 15 0 0077
1301 { 0xa000, //w 4 15 12 a
1302 0xdf01, //w 3 15 0 df01
1303 0xdf20, //w 2 15 0 df20
1304 0xff95, //w 1 15 0 ff95
1305 0xfa00 } },{ //w 0 15 0 fa00
1306 { 0xb000, //w 4 15 12 b
1307 0xff41, //w 3 15 0 ff41
1308 0xde20, //w 2 15 0 de20
1309 0x0140, //w 1 15 0 0140
1310 0x00bb } },{ //w 0 15 0 00bb
1311 { 0xf000, //w 4 15 12 f
1312 0xdf01, //w 3 15 0 df01
1313 0xdf20, //w 2 15 0 df20
1314 0xff95, //w 1 15 0 ff95
1315 0xbf00 } //w 0 15 0 bf00
1316 }
1317 }, *p = phy_magic;
07d3f51f 1318 unsigned int i;
1da177e4 1319
a441d7b6
FR		 1320 mdio_write(ioaddr, 0x1f, 0x0001); //w 31 2 0 1
1321 mdio_write(ioaddr, 0x15, 0x1000); //w 21 15 0 1000
1322 mdio_write(ioaddr, 0x18, 0x65c7); //w 24 15 0 65c7
1da177e4
LT		 1323 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1324
1325 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1326 int val, pos = 4;
1327
1328 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1329 mdio_write(ioaddr, pos, val);
1330 while (--pos >= 0)
1331 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1332 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1333 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1334 }
a441d7b6 1335 mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1da177e4
LT		 1336}
1337
5615d9f1
FR		 1338static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1339{
a441d7b6
FR		 1340 struct phy_reg phy_reg_init[] = {
1341 { 0x1f, 0x0002 },
1342 { 0x01, 0x90d0 },
1343 { 0x1f, 0x0000 }
1344 };
1345
1346 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1347}
1348
867763c1
FR		 1349static void rtl8168cp_hw_phy_config(void __iomem *ioaddr)
1350{
1351 struct phy_reg phy_reg_init[] = {
1352 { 0x1f, 0x0000 },
1353 { 0x1d, 0x0f00 },
1354 { 0x1f, 0x0002 },
1355 { 0x0c, 0x1ec8 },
1356 { 0x1f, 0x0000 }
1357 };
1358
1359 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1360}
1361
1362static void rtl8168c_hw_phy_config(void __iomem *ioaddr)
1363{
1364 struct phy_reg phy_reg_init[] = {
a3f80671
FR		 1365 { 0x1f, 0x0001 },
1366 { 0x12, 0x2300 },
867763c1
FR		 1367 { 0x1f, 0x0002 },
1368 { 0x00, 0x88d4 },
1369 { 0x01, 0x82b1 },
1370 { 0x03, 0x7002 },
1371 { 0x08, 0x9e30 },
1372 { 0x09, 0x01f0 },
1373 { 0x0a, 0x5500 },
1374 { 0x0c, 0x00c8 },
1375 { 0x1f, 0x0003 },
1376 { 0x12, 0xc096 },
1377 { 0x16, 0x000a },
1378 { 0x1f, 0x0000 }
1379 };
1380
1381 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1382}
1383
7da97ec9
FR		 1384static void rtl8168cx_hw_phy_config(void __iomem *ioaddr)
1385{
1386 struct phy_reg phy_reg_init[] = {
1387 { 0x1f, 0x0000 },
1388 { 0x12, 0x2300 },
1389 { 0x1f, 0x0003 },
1390 { 0x16, 0x0f0a },
1391 { 0x1f, 0x0000 },
1392 { 0x1f, 0x0002 },
1393 { 0x0c, 0x7eb8 },
1394 { 0x1f, 0x0000 }
1395 };
1396
1397 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1398}
1399
2857ffb7
FR		 1400static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1401{
1402 struct phy_reg phy_reg_init[] = {
1403 { 0x1f, 0x0003 },
1404 { 0x08, 0x441d },
1405 { 0x01, 0x9100 },
1406 { 0x1f, 0x0000 }
1407 };
1408
1409 mdio_write(ioaddr, 0x1f, 0x0000);
1410 mdio_patch(ioaddr, 0x11, 1 << 12);
1411 mdio_patch(ioaddr, 0x19, 1 << 13);
1412
1413 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1414}
1415
5615d9f1
FR		 1416static void rtl_hw_phy_config(struct net_device *dev)
1417{
1418 struct rtl8169_private *tp = netdev_priv(dev);
1419 void __iomem *ioaddr = tp->mmio_addr;
1420
1421 rtl8169_print_mac_version(tp);
1422
1423 switch (tp->mac_version) {
1424 case RTL_GIGA_MAC_VER_01:
1425 break;
1426 case RTL_GIGA_MAC_VER_02:
1427 case RTL_GIGA_MAC_VER_03:
1428 rtl8169s_hw_phy_config(ioaddr);
1429 break;
1430 case RTL_GIGA_MAC_VER_04:
1431 rtl8169sb_hw_phy_config(ioaddr);
1432 break;
2857ffb7
FR		 1433 case RTL_GIGA_MAC_VER_07:
1434 case RTL_GIGA_MAC_VER_08:
1435 case RTL_GIGA_MAC_VER_09:
1436 rtl8102e_hw_phy_config(ioaddr);
1437 break;
867763c1
FR		 1438 case RTL_GIGA_MAC_VER_18:
1439 rtl8168cp_hw_phy_config(ioaddr);
1440 break;
1441 case RTL_GIGA_MAC_VER_19:
1442 rtl8168c_hw_phy_config(ioaddr);
1443 break;
7da97ec9
FR		 1444 case RTL_GIGA_MAC_VER_20:
1445 rtl8168cx_hw_phy_config(ioaddr);
1446 break;
5615d9f1
FR		 1447 default:
1448 break;
1449 }
1450}
1451
1da177e4
LT		 1452static void rtl8169_phy_timer(unsigned long __opaque)
1453{
1454 struct net_device *dev = (struct net_device *)__opaque;
1455 struct rtl8169_private *tp = netdev_priv(dev);
1456 struct timer_list *timer = &tp->timer;
1457 void __iomem *ioaddr = tp->mmio_addr;
1458 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1459
bcf0bf90 1460 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 1461
64e4bfb4 1462 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1463 return;
1464
1465 spin_lock_irq(&tp->lock);
1466
1467 if (tp->phy_reset_pending(ioaddr)) {
5b0384f4 1468 /*
1da177e4
LT		 1469 * A busy loop could burn quite a few cycles on nowadays CPU.
1470 * Let's delay the execution of the timer for a few ticks.
1471 */
1472 timeout = HZ/10;
1473 goto out_mod_timer;
1474 }
1475
1476 if (tp->link_ok(ioaddr))
1477 goto out_unlock;
1478
b57b7e5a
SH		 1479 if (netif_msg_link(tp))
1480 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1da177e4
LT		 1481
1482 tp->phy_reset_enable(ioaddr);
1483
1484out_mod_timer:
1485 mod_timer(timer, jiffies + timeout);
1486out_unlock:
1487 spin_unlock_irq(&tp->lock);
1488}
1489
1490static inline void rtl8169_delete_timer(struct net_device *dev)
1491{
1492 struct rtl8169_private *tp = netdev_priv(dev);
1493 struct timer_list *timer = &tp->timer;
1494
e179bb7b 1495 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1496 return;
1497
1498 del_timer_sync(timer);
1499}
1500
1501static inline void rtl8169_request_timer(struct net_device *dev)
1502{
1503 struct rtl8169_private *tp = netdev_priv(dev);
1504 struct timer_list *timer = &tp->timer;
1505
e179bb7b 1506 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 1507 return;
1508
2efa53f3 1509 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 1510}
1511
1512#ifdef CONFIG_NET_POLL_CONTROLLER
1513/*
1514 * Polling 'interrupt' - used by things like netconsole to send skbs
1515 * without having to re-enable interrupts. It's not called while
1516 * the interrupt routine is executing.
1517 */
1518static void rtl8169_netpoll(struct net_device *dev)
1519{
1520 struct rtl8169_private *tp = netdev_priv(dev);
1521 struct pci_dev *pdev = tp->pci_dev;
1522
1523 disable_irq(pdev->irq);
7d12e780 1524 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 1525 enable_irq(pdev->irq);
1526}
1527#endif
1528
1529static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1530 void __iomem *ioaddr)
1531{
1532 iounmap(ioaddr);
1533 pci_release_regions(pdev);
1534 pci_disable_device(pdev);
1535 free_netdev(dev);
1536}
1537
bf793295
FR		 1538static void rtl8169_phy_reset(struct net_device *dev,
1539 struct rtl8169_private *tp)
1540{
1541 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1542 unsigned int i;
bf793295
FR		 1543
1544 tp->phy_reset_enable(ioaddr);
1545 for (i = 0; i < 100; i++) {
1546 if (!tp->phy_reset_pending(ioaddr))
1547 return;
1548 msleep(1);
1549 }
1550 if (netif_msg_link(tp))
1551 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1552}
1553
4ff96fa6
FR		 1554static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1555{
1556 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 1557
5615d9f1 1558 rtl_hw_phy_config(dev);
4ff96fa6 1559
77332894
MS		 1560 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1561 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1562 RTL_W8(0x82, 0x01);
1563 }
4ff96fa6 1564
6dccd16b
FR		 1565 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1566
1567 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1568 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 1569
bcf0bf90 1570 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 1571 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1572 RTL_W8(0x82, 0x01);
1573 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1574 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1575 }
1576
bf793295
FR		 1577 rtl8169_phy_reset(dev, tp);
1578
901dda2b
FR		 1579 /*
1580 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1581 * only 8101. Don't panic.
1582 */
1583 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6
FR		 1584
1585 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1586 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1587}
1588
773d2021
FR		 1589static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1590{
1591 void __iomem *ioaddr = tp->mmio_addr;
1592 u32 high;
1593 u32 low;
1594
1595 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1596 high = addr[4] | (addr[5] << 8);
1597
1598 spin_lock_irq(&tp->lock);
1599
1600 RTL_W8(Cfg9346, Cfg9346_Unlock);
1601 RTL_W32(MAC0, low);
1602 RTL_W32(MAC4, high);
1603 RTL_W8(Cfg9346, Cfg9346_Lock);
1604
1605 spin_unlock_irq(&tp->lock);
1606}
1607
1608static int rtl_set_mac_address(struct net_device *dev, void *p)
1609{
1610 struct rtl8169_private *tp = netdev_priv(dev);
1611 struct sockaddr *addr = p;
1612
1613 if (!is_valid_ether_addr(addr->sa_data))
1614 return -EADDRNOTAVAIL;
1615
1616 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1617
1618 rtl_rar_set(tp, dev->dev_addr);
1619
1620 return 0;
1621}
1622
5f787a1a
FR		 1623static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1624{
1625 struct rtl8169_private *tp = netdev_priv(dev);
1626 struct mii_ioctl_data *data = if_mii(ifr);
1627
1628 if (!netif_running(dev))
1629 return -ENODEV;
1630
1631 switch (cmd) {
1632 case SIOCGMIIPHY:
1633 data->phy_id = 32; /* Internal PHY */
1634 return 0;
1635
1636 case SIOCGMIIREG:
1637 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1638 return 0;
1639
1640 case SIOCSMIIREG:
1641 if (!capable(CAP_NET_ADMIN))
1642 return -EPERM;
1643 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1644 return 0;
1645 }
1646 return -EOPNOTSUPP;
1647}
1648
0e485150
FR		 1649static const struct rtl_cfg_info {
1650 void (*hw_start)(struct net_device *);
1651 unsigned int region;
1652 unsigned int align;
1653 u16 intr_event;
1654 u16 napi_event;
ccdffb9a 1655 unsigned features;
0e485150
FR		 1656} rtl_cfg_infos [] = {
1657 [RTL_CFG_0] = {
1658 .hw_start = rtl_hw_start_8169,
1659 .region = 1,
e9f63f30 1660 .align = 0,
0e485150
FR		 1661 .intr_event = SYSErr | LinkChg | RxOverflow |
1662 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1663 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1664 .features = RTL_FEATURE_GMII
0e485150
FR		 1665 },
1666 [RTL_CFG_1] = {
1667 .hw_start = rtl_hw_start_8168,
1668 .region = 2,
1669 .align = 8,
1670 .intr_event = SYSErr | LinkChg | RxOverflow |
1671 TxErr | TxOK | RxOK | RxErr,
fbac58fc 1672 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1673 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI
0e485150
FR		 1674 },
1675 [RTL_CFG_2] = {
1676 .hw_start = rtl_hw_start_8101,
1677 .region = 2,
1678 .align = 8,
1679 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1680 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 1681 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
ccdffb9a 1682 .features = RTL_FEATURE_MSI
0e485150
FR		 1683 }
1684};
1685
fbac58fc
FR		 1686/* Cfg9346_Unlock assumed. */
1687static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1688 const struct rtl_cfg_info *cfg)
1689{
1690 unsigned msi = 0;
1691 u8 cfg2;
1692
1693 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 1694 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 1695 if (pci_enable_msi(pdev)) {
1696 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1697 } else {
1698 cfg2 |= MSIEnable;
1699 msi = RTL_FEATURE_MSI;
1700 }
1701 }
1702 RTL_W8(Config2, cfg2);
1703 return msi;
1704}
1705
1706static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1707{
1708 if (tp->features & RTL_FEATURE_MSI) {
1709 pci_disable_msi(pdev);
1710 tp->features &= ~RTL_FEATURE_MSI;
1711 }
1712}
1713
7bf6bf48
IV		 1714static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1715{
1716 int ret, count = 100;
1717 u16 status = 0;
1718 u32 value;
1719
1720 ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1721 if (ret < 0)
1722 return ret;
1723
1724 do {
1725 udelay(10);
1726 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1727 if (ret < 0)
1728 return ret;
1729 } while (!(status & PCI_VPD_ADDR_F) && --count);
1730
1731 if (!(status & PCI_VPD_ADDR_F))
1732 return -ETIMEDOUT;
1733
1734 ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1735 if (ret < 0)
1736 return ret;
1737
1738 *val = cpu_to_le32(value);
1739
1740 return 0;
1741}
1742
1743static void rtl_init_mac_address(struct rtl8169_private *tp,
1744 void __iomem *ioaddr)
1745{
1746 struct pci_dev *pdev = tp->pci_dev;
1747 u8 cfg1;
1748 int vpd_cap;
1749 u8 mac[8];
1750 DECLARE_MAC_BUF(buf);
1751
1752 cfg1 = RTL_R8(Config1);
1753 if (!(cfg1 & VPD)) {
1754 dprintk("VPD access not enabled, enabling\n");
1755 RTL_W8(Cfg9346, Cfg9346_Unlock);
1756 RTL_W8(Config1, cfg1 | VPD);
1757 RTL_W8(Cfg9346, Cfg9346_Lock);
1758 }
1759
1760 vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1761 if (!vpd_cap)
1762 return;
1763
1764 /* MAC address is stored in EEPROM at offset 0x0e
1765 * Realtek says: "The VPD address does not have to be a DWORD-aligned
1766 * address as defined in the PCI 2.2 Specifications, but the VPD data
1767 * is always consecutive 4-byte data starting from the VPD address
1768 * specified."
1769 */
1770 if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1771 rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1772 dprintk("Reading MAC address from EEPROM failed\n");
1773 return;
1774 }
1775
1776 dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1777
1778 /* Write MAC address */
1779 rtl_rar_set(tp, mac);
1780}
1781
1da177e4 1782static int __devinit
4ff96fa6 1783rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 1784{
0e485150
FR		 1785 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1786 const unsigned int region = cfg->region;
1da177e4 1787 struct rtl8169_private *tp;
ccdffb9a 1788 struct mii_if_info *mii;
4ff96fa6
FR		 1789 struct net_device *dev;
1790 void __iomem *ioaddr;
07d3f51f
FR		 1791 unsigned int i;
1792 int rc;
1da177e4 1793
4ff96fa6
FR		 1794 if (netif_msg_drv(&debug)) {
1795 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1796 MODULENAME, RTL8169_VERSION);
1797 }
1da177e4 1798
1da177e4 1799 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 1800 if (!dev) {
b57b7e5a 1801 if (netif_msg_drv(&debug))
9b91cf9d 1802 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 1803 rc = -ENOMEM;
1804 goto out;
1da177e4
LT		 1805 }
1806
1da177e4
LT		 1807 SET_NETDEV_DEV(dev, &pdev->dev);
1808 tp = netdev_priv(dev);
c4028958 1809 tp->dev = dev;
21e197f2 1810 tp->pci_dev = pdev;
b57b7e5a 1811 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 1812
ccdffb9a
FR		 1813 mii = &tp->mii;
1814 mii->dev = dev;
1815 mii->mdio_read = rtl_mdio_read;
1816 mii->mdio_write = rtl_mdio_write;
1817 mii->phy_id_mask = 0x1f;
1818 mii->reg_num_mask = 0x1f;
1819 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
1820
1da177e4
LT		 1821 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1822 rc = pci_enable_device(pdev);
b57b7e5a 1823 if (rc < 0) {
2e8a538d 1824 if (netif_msg_probe(tp))
9b91cf9d 1825 dev_err(&pdev->dev, "enable failure\n");
4ff96fa6 1826 goto err_out_free_dev_1;
1da177e4
LT		 1827 }
1828
1829 rc = pci_set_mwi(pdev);
1830 if (rc < 0)
4ff96fa6 1831 goto err_out_disable_2;
1da177e4 1832
1da177e4 1833 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 1834 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
4ff96fa6 1835 if (netif_msg_probe(tp)) {
9b91cf9d 1836 dev_err(&pdev->dev,
bcf0bf90
FR		 1837 "region #%d not an MMIO resource, aborting\n",
1838 region);
4ff96fa6 1839 }
1da177e4 1840 rc = -ENODEV;
4ff96fa6 1841 goto err_out_mwi_3;
1da177e4 1842 }
4ff96fa6 1843
1da177e4 1844 /* check for weird/broken PCI region reporting */
bcf0bf90 1845 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
4ff96fa6 1846 if (netif_msg_probe(tp)) {
9b91cf9d 1847 dev_err(&pdev->dev,
4ff96fa6
FR		 1848 "Invalid PCI region size(s), aborting\n");
1849 }
1da177e4 1850 rc = -ENODEV;
4ff96fa6 1851 goto err_out_mwi_3;
1da177e4
LT		 1852 }
1853
1854 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 1855 if (rc < 0) {
2e8a538d 1856 if (netif_msg_probe(tp))
9b91cf9d 1857 dev_err(&pdev->dev, "could not request regions.\n");
4ff96fa6 1858 goto err_out_mwi_3;
1da177e4
LT		 1859 }
1860
1861 tp->cp_cmd = PCIMulRW | RxChkSum;
1862
1863 if ((sizeof(dma_addr_t) > 4) &&
1864 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1865 tp->cp_cmd |= PCIDAC;
1866 dev->features |= NETIF_F_HIGHDMA;
1867 } else {
1868 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1869 if (rc < 0) {
4ff96fa6 1870 if (netif_msg_probe(tp)) {
9b91cf9d 1871 dev_err(&pdev->dev,
4ff96fa6
FR		 1872 "DMA configuration failed.\n");
1873 }
1874 goto err_out_free_res_4;
1da177e4
LT		 1875 }
1876 }
1877
1878 pci_set_master(pdev);
1879
1880 /* ioremap MMIO region */
bcf0bf90 1881 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 1882 if (!ioaddr) {
b57b7e5a 1883 if (netif_msg_probe(tp))
9b91cf9d 1884 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
1da177e4 1885 rc = -EIO;
4ff96fa6 1886 goto err_out_free_res_4;
1da177e4
LT		 1887 }
1888
9c14ceaf
FR		 1889 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1890 if (!tp->pcie_cap && netif_msg_probe(tp))
1891 dev_info(&pdev->dev, "no PCI Express capability\n");
1892
1da177e4
LT		 1893 /* Unneeded ? Don't mess with Mrs. Murphy. */
1894 rtl8169_irq_mask_and_ack(ioaddr);
1895
1896 /* Soft reset the chip. */
1897 RTL_W8(ChipCmd, CmdReset);
1898
1899 /* Check that the chip has finished the reset. */
07d3f51f 1900 for (i = 0; i < 100; i++) {
1da177e4
LT		 1901 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1902 break;
b518fa8e 1903 msleep_interruptible(1);
1da177e4
LT		 1904 }
1905
1906 /* Identify chip attached to board */
1907 rtl8169_get_mac_version(tp, ioaddr);
1da177e4
LT		 1908
1909 rtl8169_print_mac_version(tp);
1da177e4 1910
cee60c37 1911 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 1912 if (tp->mac_version == rtl_chip_info[i].mac_version)
1913 break;
1914 }
cee60c37 1915 if (i == ARRAY_SIZE(rtl_chip_info)) {
1da177e4 1916 /* Unknown chip: assume array element #0, original RTL-8169 */
b57b7e5a 1917 if (netif_msg_probe(tp)) {
2e8a538d 1918 dev_printk(KERN_DEBUG, &pdev->dev,
4ff96fa6
FR		 1919 "unknown chip version, assuming %s\n",
1920 rtl_chip_info[0].name);
b57b7e5a 1921 }
cee60c37 1922 i = 0;
1da177e4
LT		 1923 }
1924 tp->chipset = i;
1925
5d06a99f
FR		 1926 RTL_W8(Cfg9346, Cfg9346_Unlock);
1927 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1928 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 1929 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
1930 tp->features |= RTL_FEATURE_WOL;
1931 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
1932 tp->features |= RTL_FEATURE_WOL;
fbac58fc 1933 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 1934 RTL_W8(Cfg9346, Cfg9346_Lock);
1935
66ec5d4f
FR		 1936 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
1937 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 1938 tp->set_speed = rtl8169_set_speed_tbi;
1939 tp->get_settings = rtl8169_gset_tbi;
1940 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1941 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1942 tp->link_ok = rtl8169_tbi_link_ok;
1943
64e4bfb4 1944 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 1945 } else {
1946 tp->set_speed = rtl8169_set_speed_xmii;
1947 tp->get_settings = rtl8169_gset_xmii;
1948 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1949 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1950 tp->link_ok = rtl8169_xmii_link_ok;
5f787a1a
FR		 1951
1952 dev->do_ioctl = rtl8169_ioctl;
1da177e4
LT		 1953 }
1954
df58ef51
FR		 1955 spin_lock_init(&tp->lock);
1956
7bf6bf48
IV		 1957 rtl_init_mac_address(tp, ioaddr);
1958
1959 /* Get MAC address */
1da177e4
LT		 1960 for (i = 0; i < MAC_ADDR_LEN; i++)
1961 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 1962 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4
LT		 1963
1964 dev->open = rtl8169_open;
1965 dev->hard_start_xmit = rtl8169_start_xmit;
1966 dev->get_stats = rtl8169_get_stats;
1967 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1968 dev->stop = rtl8169_close;
1969 dev->tx_timeout = rtl8169_tx_timeout;
07ce4064 1970 dev->set_multicast_list = rtl_set_rx_mode;
1da177e4
LT		 1971 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1972 dev->irq = pdev->irq;
1973 dev->base_addr = (unsigned long) ioaddr;
1974 dev->change_mtu = rtl8169_change_mtu;
773d2021 1975 dev->set_mac_address = rtl_set_mac_address;
1da177e4 1976
bea3348e 1977 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 1978
1979#ifdef CONFIG_R8169_VLAN
1980 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1981 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1da177e4
LT		 1982#endif
1983
1984#ifdef CONFIG_NET_POLL_CONTROLLER
1985 dev->poll_controller = rtl8169_netpoll;
1986#endif
1987
1988 tp->intr_mask = 0xffff;
1da177e4 1989 tp->mmio_addr = ioaddr;
0e485150
FR		 1990 tp->align = cfg->align;
1991 tp->hw_start = cfg->hw_start;
1992 tp->intr_event = cfg->intr_event;
1993 tp->napi_event = cfg->napi_event;
1da177e4 1994
2efa53f3
FR		 1995 init_timer(&tp->timer);
1996 tp->timer.data = (unsigned long) dev;
1997 tp->timer.function = rtl8169_phy_timer;
1998
1da177e4 1999 rc = register_netdev(dev);
4ff96fa6 2000 if (rc < 0)
fbac58fc 2001 goto err_out_msi_5;
1da177e4
LT		 2002
2003 pci_set_drvdata(pdev, dev);
2004
b57b7e5a 2005 if (netif_msg_probe(tp)) {
96b9709c
FR		 2006 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2007
b57b7e5a
SH		 2008 printk(KERN_INFO "%s: %s at 0x%lx, "
2009 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
96b9709c 2010 "XID %08x IRQ %d\n",
b57b7e5a 2011 dev->name,
bcf0bf90 2012 rtl_chip_info[tp->chipset].name,
b57b7e5a
SH		 2013 dev->base_addr,
2014 dev->dev_addr[0], dev->dev_addr[1],
2015 dev->dev_addr[2], dev->dev_addr[3],
96b9709c 2016 dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
b57b7e5a 2017 }
1da177e4 2018
4ff96fa6 2019 rtl8169_init_phy(dev, tp);
8b76ab39 2020 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 2021
4ff96fa6
FR		 2022out:
2023 return rc;
1da177e4 2024
fbac58fc
FR		 2025err_out_msi_5:
2026 rtl_disable_msi(pdev, tp);
4ff96fa6
FR		 2027 iounmap(ioaddr);
2028err_out_free_res_4:
2029 pci_release_regions(pdev);
2030err_out_mwi_3:
2031 pci_clear_mwi(pdev);
2032err_out_disable_2:
2033 pci_disable_device(pdev);
2034err_out_free_dev_1:
2035 free_netdev(dev);
2036 goto out;
1da177e4
LT		 2037}
2038
07d3f51f 2039static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 2040{
2041 struct net_device *dev = pci_get_drvdata(pdev);
2042 struct rtl8169_private *tp = netdev_priv(dev);
2043
eb2a021c
FR		 2044 flush_scheduled_work();
2045
1da177e4 2046 unregister_netdev(dev);
fbac58fc 2047 rtl_disable_msi(pdev, tp);
1da177e4
LT		 2048 rtl8169_release_board(pdev, dev, tp->mmio_addr);
2049 pci_set_drvdata(pdev, NULL);
2050}
2051
1da177e4
LT		 2052static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2053 struct net_device *dev)
2054{
2055 unsigned int mtu = dev->mtu;
2056
2057 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2058}
2059
2060static int rtl8169_open(struct net_device *dev)
2061{
2062 struct rtl8169_private *tp = netdev_priv(dev);
2063 struct pci_dev *pdev = tp->pci_dev;
99f252b0 2064 int retval = -ENOMEM;
1da177e4 2065
1da177e4 2066
99f252b0 2067 rtl8169_set_rxbufsize(tp, dev);
1da177e4
LT		 2068
2069 /*
2070 * Rx and Tx desscriptors needs 256 bytes alignment.
2071 * pci_alloc_consistent provides more.
2072 */
2073 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2074 &tp->TxPhyAddr);
2075 if (!tp->TxDescArray)
99f252b0 2076 goto out;
1da177e4
LT		 2077
2078 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2079 &tp->RxPhyAddr);
2080 if (!tp->RxDescArray)
99f252b0 2081 goto err_free_tx_0;
1da177e4
LT		 2082
2083 retval = rtl8169_init_ring(dev);
2084 if (retval < 0)
99f252b0 2085 goto err_free_rx_1;
1da177e4 2086
c4028958 2087 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 2088
99f252b0
FR		 2089 smp_mb();
2090
fbac58fc
FR		 2091 retval = request_irq(dev->irq, rtl8169_interrupt,
2092 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 2093 dev->name, dev);
2094 if (retval < 0)
2095 goto err_release_ring_2;
2096
bea3348e 2097 napi_enable(&tp->napi);
bea3348e 2098
07ce4064 2099 rtl_hw_start(dev);
1da177e4
LT		 2100
2101 rtl8169_request_timer(dev);
2102
2103 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2104out:
2105 return retval;
2106
99f252b0
FR		 2107err_release_ring_2:
2108 rtl8169_rx_clear(tp);
2109err_free_rx_1:
1da177e4
LT		 2110 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2111 tp->RxPhyAddr);
99f252b0 2112err_free_tx_0:
1da177e4
LT		 2113 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2114 tp->TxPhyAddr);
1da177e4
LT		 2115 goto out;
2116}
2117
2118static void rtl8169_hw_reset(void __iomem *ioaddr)
2119{
2120 /* Disable interrupts */
2121 rtl8169_irq_mask_and_ack(ioaddr);
2122
2123 /* Reset the chipset */
2124 RTL_W8(ChipCmd, CmdReset);
2125
2126 /* PCI commit */
2127 RTL_R8(ChipCmd);
2128}
2129
7f796d83 2130static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 2131{
2132 void __iomem *ioaddr = tp->mmio_addr;
2133 u32 cfg = rtl8169_rx_config;
2134
2135 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2136 RTL_W32(RxConfig, cfg);
2137
2138 /* Set DMA burst size and Interframe Gap Time */
2139 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2140 (InterFrameGap << TxInterFrameGapShift));
2141}
2142
07ce4064 2143static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 2144{
2145 struct rtl8169_private *tp = netdev_priv(dev);
2146 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 2147 unsigned int i;
1da177e4
LT		 2148
2149 /* Soft reset the chip. */
2150 RTL_W8(ChipCmd, CmdReset);
2151
2152 /* Check that the chip has finished the reset. */
07d3f51f 2153 for (i = 0; i < 100; i++) {
1da177e4
LT		 2154 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2155 break;
b518fa8e 2156 msleep_interruptible(1);
1da177e4
LT		 2157 }
2158
07ce4064
FR		 2159 tp->hw_start(dev);
2160
07ce4064
FR		 2161 netif_start_queue(dev);
2162}
2163
2164
7f796d83
FR		 2165static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2166 void __iomem *ioaddr)
2167{
2168 /*
2169 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2170 * register to be written before TxDescAddrLow to work.
2171 * Switching from MMIO to I/O access fixes the issue as well.
2172 */
2173 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2174 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2175 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2176 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2177}
2178
2179static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2180{
2181 u16 cmd;
2182
2183 cmd = RTL_R16(CPlusCmd);
2184 RTL_W16(CPlusCmd, cmd);
2185 return cmd;
2186}
2187
2188static void rtl_set_rx_max_size(void __iomem *ioaddr)
2189{
2190 /* Low hurts. Let's disable the filtering. */
2191 RTL_W16(RxMaxSize, 16383);
2192}
2193
6dccd16b
FR		 2194static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2195{
2196 struct {
2197 u32 mac_version;
2198 u32 clk;
2199 u32 val;
2200 } cfg2_info [] = {
2201 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2202 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2203 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2204 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2205 }, *p = cfg2_info;
2206 unsigned int i;
2207 u32 clk;
2208
2209 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 2210 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 2211 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2212 RTL_W32(0x7c, p->val);
2213 break;
2214 }
2215 }
2216}
2217
07ce4064
FR		 2218static void rtl_hw_start_8169(struct net_device *dev)
2219{
2220 struct rtl8169_private *tp = netdev_priv(dev);
2221 void __iomem *ioaddr = tp->mmio_addr;
2222 struct pci_dev *pdev = tp->pci_dev;
07ce4064 2223
9cb427b6
FR		 2224 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2225 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2226 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2227 }
2228
1da177e4 2229 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 2230 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2231 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2232 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2233 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2234 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2235
1da177e4
LT		 2236 RTL_W8(EarlyTxThres, EarlyTxThld);
2237
7f796d83 2238 rtl_set_rx_max_size(ioaddr);
1da177e4 2239
c946b304
FR		 2240 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2241 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2242 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2243 (tp->mac_version == RTL_GIGA_MAC_VER_04))
2244 rtl_set_rx_tx_config_registers(tp);
1da177e4 2245
7f796d83 2246 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 2247
bcf0bf90
FR		 2248 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2249 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 2250 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 2251 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 2252 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 2253 }
2254
bcf0bf90
FR		 2255 RTL_W16(CPlusCmd, tp->cp_cmd);
2256
6dccd16b
FR		 2257 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2258
1da177e4
LT		 2259 /*
2260 * Undocumented corner. Supposedly:
2261 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2262 */
2263 RTL_W16(IntrMitigate, 0x0000);
2264
7f796d83 2265 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 2266
c946b304
FR		 2267 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2268 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2269 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2270 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2271 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2272 rtl_set_rx_tx_config_registers(tp);
2273 }
2274
1da177e4 2275 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 2276
2277 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2278 RTL_R8(IntrMask);
1da177e4
LT		 2279
2280 RTL_W32(RxMissed, 0);
2281
07ce4064 2282 rtl_set_rx_mode(dev);
1da177e4
LT		 2283
2284 /* no early-rx interrupts */
2285 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 2286
2287 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 2288 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2289}
1da177e4 2290
9c14ceaf 2291static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 2292{
9c14ceaf
FR		 2293 struct net_device *dev = pci_get_drvdata(pdev);
2294 struct rtl8169_private *tp = netdev_priv(dev);
2295 int cap = tp->pcie_cap;
2296
2297 if (cap) {
2298 u16 ctl;
458a9f61 2299
9c14ceaf
FR		 2300 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2301 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2302 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2303 }
458a9f61
FR		 2304}
2305
dacf8154
FR		 2306static void rtl_csi_access_enable(void __iomem *ioaddr)
2307{
2308 u32 csi;
2309
2310 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2311 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2312}
2313
2314struct ephy_info {
2315 unsigned int offset;
2316 u16 mask;
2317 u16 bits;
2318};
2319
2320static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2321{
2322 u16 w;
2323
2324 while (len-- > 0) {
2325 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2326 rtl_ephy_write(ioaddr, e->offset, w);
2327 e++;
2328 }
2329}
2330
07ce4064
FR		 2331static void rtl_hw_start_8168(struct net_device *dev)
2332{
2dd99530
FR		 2333 struct rtl8169_private *tp = netdev_priv(dev);
2334 void __iomem *ioaddr = tp->mmio_addr;
0e485150 2335 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 2336
2337 RTL_W8(Cfg9346, Cfg9346_Unlock);
2338
2339 RTL_W8(EarlyTxThres, EarlyTxThld);
2340
2341 rtl_set_rx_max_size(ioaddr);
2342
0e485150
FR		 2343 rtl_set_rx_tx_config_registers(tp);
2344
2345 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 2346
2347 RTL_W16(CPlusCmd, tp->cp_cmd);
2348
9c14ceaf 2349 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2dd99530 2350
0e485150 2351 RTL_W16(IntrMitigate, 0x5151);
2dd99530 2352
0e485150
FR		 2353 /* Work around for RxFIFO overflow. */
2354 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2355 tp->intr_event |= RxFIFOOver | PCSTimeout;
2356 tp->intr_event &= ~RxOverflow;
2357 }
2358
2359 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530
FR		 2360
2361 RTL_W8(Cfg9346, Cfg9346_Lock);
2362
2363 RTL_R8(IntrMask);
2364
2dd99530
FR		 2365 rtl_set_rx_mode(dev);
2366
0e485150
FR		 2367 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2368
2dd99530 2369 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 2370
0e485150 2371 RTL_W16(IntrMask, tp->intr_event);
07ce4064 2372}
1da177e4 2373
2857ffb7
FR		 2374#define R810X_CPCMD_QUIRK_MASK (\
2375 EnableBist | \
2376 Mac_dbgo_oe | \
2377 Force_half_dup | \
2378 Force_half_dup | \
2379 Force_txflow_en | \
2380 Cxpl_dbg_sel | \
2381 ASF | \
2382 PktCntrDisable | \
2383 PCIDAC | \
2384 PCIMulRW)
2385
2386static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2387{
2388 static struct ephy_info e_info_8102e_1[] = {
2389 { 0x01, 0, 0x6e65 },
2390 { 0x02, 0, 0x091f },
2391 { 0x03, 0, 0xc2f9 },
2392 { 0x06, 0, 0xafb5 },
2393 { 0x07, 0, 0x0e00 },
2394 { 0x19, 0, 0xec80 },
2395 { 0x01, 0, 0x2e65 },
2396 { 0x01, 0, 0x6e65 }
2397 };
2398 u8 cfg1;
2399
2400 rtl_csi_access_enable(ioaddr);
2401
2402 RTL_W8(DBG_REG, FIX_NAK_1);
2403
2404 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2405
2406 RTL_W8(Config1,
2407 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2408 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2409
2410 cfg1 = RTL_R8(Config1);
2411 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2412 RTL_W8(Config1, cfg1 & ~LEDS0);
2413
2414 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2415
2416 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2417}
2418
2419static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2420{
2421 rtl_csi_access_enable(ioaddr);
2422
2423 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2424
2425 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2426 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2427
2428 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2429}
2430
2431static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2432{
2433 rtl_hw_start_8102e_2(ioaddr, pdev);
2434
2435 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2436}
2437
07ce4064
FR		 2438static void rtl_hw_start_8101(struct net_device *dev)
2439{
cdf1a608
FR		 2440 struct rtl8169_private *tp = netdev_priv(dev);
2441 void __iomem *ioaddr = tp->mmio_addr;
2442 struct pci_dev *pdev = tp->pci_dev;
2443
e3cf0cc0
FR		 2444 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2445 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 2446 int cap = tp->pcie_cap;
2447
2448 if (cap) {
2449 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2450 PCI_EXP_DEVCTL_NOSNOOP_EN);
2451 }
cdf1a608
FR		 2452 }
2453
2857ffb7
FR		 2454 switch (tp->mac_version) {
2455 case RTL_GIGA_MAC_VER_07:
2456 rtl_hw_start_8102e_1(ioaddr, pdev);
2457 break;
2458
2459 case RTL_GIGA_MAC_VER_08:
2460 rtl_hw_start_8102e_3(ioaddr, pdev);
2461 break;
2462
2463 case RTL_GIGA_MAC_VER_09:
2464 rtl_hw_start_8102e_2(ioaddr, pdev);
2465 break;
cdf1a608
FR		 2466 }
2467
2468 RTL_W8(Cfg9346, Cfg9346_Unlock);
2469
2470 RTL_W8(EarlyTxThres, EarlyTxThld);
2471
2472 rtl_set_rx_max_size(ioaddr);
2473
2474 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2475
2476 RTL_W16(CPlusCmd, tp->cp_cmd);
2477
2478 RTL_W16(IntrMitigate, 0x0000);
2479
2480 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2481
2482 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2483 rtl_set_rx_tx_config_registers(tp);
2484
2485 RTL_W8(Cfg9346, Cfg9346_Lock);
2486
2487 RTL_R8(IntrMask);
2488
cdf1a608
FR		 2489 rtl_set_rx_mode(dev);
2490
0e485150
FR		 2491 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2492
cdf1a608 2493 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 2494
0e485150 2495 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 2496}
2497
2498static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2499{
2500 struct rtl8169_private *tp = netdev_priv(dev);
2501 int ret = 0;
2502
2503 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2504 return -EINVAL;
2505
2506 dev->mtu = new_mtu;
2507
2508 if (!netif_running(dev))
2509 goto out;
2510
2511 rtl8169_down(dev);
2512
2513 rtl8169_set_rxbufsize(tp, dev);
2514
2515 ret = rtl8169_init_ring(dev);
2516 if (ret < 0)
2517 goto out;
2518
bea3348e 2519 napi_enable(&tp->napi);
1da177e4 2520
07ce4064 2521 rtl_hw_start(dev);
1da177e4
LT		 2522
2523 rtl8169_request_timer(dev);
2524
2525out:
2526 return ret;
2527}
2528
2529static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2530{
95e0918d 2531 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 2532 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2533}
2534
2535static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2536 struct sk_buff **sk_buff, struct RxDesc *desc)
2537{
2538 struct pci_dev *pdev = tp->pci_dev;
2539
2540 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2541 PCI_DMA_FROMDEVICE);
2542 dev_kfree_skb(*sk_buff);
2543 *sk_buff = NULL;
2544 rtl8169_make_unusable_by_asic(desc);
2545}
2546
2547static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2548{
2549 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2550
2551 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2552}
2553
2554static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2555 u32 rx_buf_sz)
2556{
2557 desc->addr = cpu_to_le64(mapping);
2558 wmb();
2559 rtl8169_mark_to_asic(desc, rx_buf_sz);
2560}
2561
15d31758
SH		 2562static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2563 struct net_device *dev,
2564 struct RxDesc *desc, int rx_buf_sz,
2565 unsigned int align)
1da177e4
LT		 2566{
2567 struct sk_buff *skb;
2568 dma_addr_t mapping;
e9f63f30 2569 unsigned int pad;
1da177e4 2570
e9f63f30
FR		 2571 pad = align ? align : NET_IP_ALIGN;
2572
2573 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
1da177e4
LT		 2574 if (!skb)
2575 goto err_out;
2576
e9f63f30 2577 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
1da177e4 2578
689be439 2579 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1da177e4
LT		 2580 PCI_DMA_FROMDEVICE);
2581
2582 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1da177e4 2583out:
15d31758 2584 return skb;
1da177e4
LT		 2585
2586err_out:
1da177e4
LT		 2587 rtl8169_make_unusable_by_asic(desc);
2588 goto out;
2589}
2590
2591static void rtl8169_rx_clear(struct rtl8169_private *tp)
2592{
07d3f51f 2593 unsigned int i;
1da177e4
LT		 2594
2595 for (i = 0; i < NUM_RX_DESC; i++) {
2596 if (tp->Rx_skbuff[i]) {
2597 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
2598 tp->RxDescArray + i);
2599 }
2600 }
2601}
2602
2603static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
2604 u32 start, u32 end)
2605{
2606 u32 cur;
5b0384f4 2607
4ae47c2d 2608 for (cur = start; end - cur != 0; cur++) {
15d31758
SH		 2609 struct sk_buff *skb;
2610 unsigned int i = cur % NUM_RX_DESC;
1da177e4 2611
4ae47c2d
FR		 2612 WARN_ON((s32)(end - cur) < 0);
2613
1da177e4
LT		 2614 if (tp->Rx_skbuff[i])
2615 continue;
bcf0bf90 2616
15d31758
SH		 2617 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
2618 tp->RxDescArray + i,
2619 tp->rx_buf_sz, tp->align);
2620 if (!skb)
1da177e4 2621 break;
15d31758
SH		 2622
2623 tp->Rx_skbuff[i] = skb;
1da177e4
LT		 2624 }
2625 return cur - start;
2626}
2627
2628static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
2629{
2630 desc->opts1 |= cpu_to_le32(RingEnd);
2631}
2632
2633static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2634{
2635 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
2636}
2637
2638static int rtl8169_init_ring(struct net_device *dev)
2639{
2640 struct rtl8169_private *tp = netdev_priv(dev);
2641
2642 rtl8169_init_ring_indexes(tp);
2643
2644 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
2645 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2646
2647 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2648 goto err_out;
2649
2650 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2651
2652 return 0;
2653
2654err_out:
2655 rtl8169_rx_clear(tp);
2656 return -ENOMEM;
2657}
2658
2659static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2660 struct TxDesc *desc)
2661{
2662 unsigned int len = tx_skb->len;
2663
2664 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2665 desc->opts1 = 0x00;
2666 desc->opts2 = 0x00;
2667 desc->addr = 0x00;
2668 tx_skb->len = 0;
2669}
2670
2671static void rtl8169_tx_clear(struct rtl8169_private *tp)
2672{
2673 unsigned int i;
2674
2675 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2676 unsigned int entry = i % NUM_TX_DESC;
2677 struct ring_info *tx_skb = tp->tx_skb + entry;
2678 unsigned int len = tx_skb->len;
2679
2680 if (len) {
2681 struct sk_buff *skb = tx_skb->skb;
2682
2683 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2684 tp->TxDescArray + entry);
2685 if (skb) {
2686 dev_kfree_skb(skb);
2687 tx_skb->skb = NULL;
2688 }
cebf8cc7 2689 tp->dev->stats.tx_dropped++;
1da177e4
LT		 2690 }
2691 }
2692 tp->cur_tx = tp->dirty_tx = 0;
2693}
2694
c4028958 2695static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 2696{
2697 struct rtl8169_private *tp = netdev_priv(dev);
2698
c4028958 2699 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 2700 schedule_delayed_work(&tp->task, 4);
2701}
2702
2703static void rtl8169_wait_for_quiescence(struct net_device *dev)
2704{
2705 struct rtl8169_private *tp = netdev_priv(dev);
2706 void __iomem *ioaddr = tp->mmio_addr;
2707
2708 synchronize_irq(dev->irq);
2709
2710 /* Wait for any pending NAPI task to complete */
bea3348e 2711 napi_disable(&tp->napi);
1da177e4
LT		 2712
2713 rtl8169_irq_mask_and_ack(ioaddr);
2714
d1d08d12
DM		 2715 tp->intr_mask = 0xffff;
2716 RTL_W16(IntrMask, tp->intr_event);
bea3348e 2717 napi_enable(&tp->napi);
1da177e4
LT		 2718}
2719
c4028958 2720static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 2721{
c4028958
DH		 2722 struct rtl8169_private *tp =
2723 container_of(work, struct rtl8169_private, task.work);
2724 struct net_device *dev = tp->dev;
1da177e4
LT		 2725 int ret;
2726
eb2a021c
FR		 2727 rtnl_lock();
2728
2729 if (!netif_running(dev))
2730 goto out_unlock;
2731
2732 rtl8169_wait_for_quiescence(dev);
2733 rtl8169_close(dev);
1da177e4
LT		 2734
2735 ret = rtl8169_open(dev);
2736 if (unlikely(ret < 0)) {
07d3f51f 2737 if (net_ratelimit() && netif_msg_drv(tp)) {
53edbecd 2738 printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
07d3f51f 2739 " Rescheduling.\n", dev->name, ret);
1da177e4
LT		 2740 }
2741 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2742 }
eb2a021c
FR		 2743
2744out_unlock:
2745 rtnl_unlock();
1da177e4
LT		 2746}
2747
c4028958 2748static void rtl8169_reset_task(struct work_struct *work)
1da177e4 2749{
c4028958
DH		 2750 struct rtl8169_private *tp =
2751 container_of(work, struct rtl8169_private, task.work);
2752 struct net_device *dev = tp->dev;
1da177e4 2753
eb2a021c
FR		 2754 rtnl_lock();
2755
1da177e4 2756 if (!netif_running(dev))
eb2a021c 2757 goto out_unlock;
1da177e4
LT		 2758
2759 rtl8169_wait_for_quiescence(dev);
2760
bea3348e 2761 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 2762 rtl8169_tx_clear(tp);
2763
2764 if (tp->dirty_rx == tp->cur_rx) {
2765 rtl8169_init_ring_indexes(tp);
07ce4064 2766 rtl_hw_start(dev);
1da177e4 2767 netif_wake_queue(dev);
cebf8cc7 2768 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 2769 } else {
07d3f51f 2770 if (net_ratelimit() && netif_msg_intr(tp)) {
53edbecd 2771 printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
07d3f51f 2772 dev->name);
1da177e4
LT		 2773 }
2774 rtl8169_schedule_work(dev, rtl8169_reset_task);
2775 }
eb2a021c
FR		 2776
2777out_unlock:
2778 rtnl_unlock();
1da177e4
LT		 2779}
2780
2781static void rtl8169_tx_timeout(struct net_device *dev)
2782{
2783 struct rtl8169_private *tp = netdev_priv(dev);
2784
2785 rtl8169_hw_reset(tp->mmio_addr);
2786
2787 /* Let's wait a bit while any (async) irq lands on */
2788 rtl8169_schedule_work(dev, rtl8169_reset_task);
2789}
2790
2791static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2792 u32 opts1)
2793{
2794 struct skb_shared_info *info = skb_shinfo(skb);
2795 unsigned int cur_frag, entry;
a6343afb 2796 struct TxDesc * uninitialized_var(txd);
1da177e4
LT		 2797
2798 entry = tp->cur_tx;
2799 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2800 skb_frag_t *frag = info->frags + cur_frag;
2801 dma_addr_t mapping;
2802 u32 status, len;
2803 void *addr;
2804
2805 entry = (entry + 1) % NUM_TX_DESC;
2806
2807 txd = tp->TxDescArray + entry;
2808 len = frag->size;
2809 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2810 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2811
2812 /* anti gcc 2.95.3 bugware (sic) */
2813 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2814
2815 txd->opts1 = cpu_to_le32(status);
2816 txd->addr = cpu_to_le64(mapping);
2817
2818 tp->tx_skb[entry].len = len;
2819 }
2820
2821 if (cur_frag) {
2822 tp->tx_skb[entry].skb = skb;
2823 txd->opts1 |= cpu_to_le32(LastFrag);
2824 }
2825
2826 return cur_frag;
2827}
2828
2829static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2830{
2831 if (dev->features & NETIF_F_TSO) {
7967168c 2832 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 2833
2834 if (mss)
2835 return LargeSend | ((mss & MSSMask) << MSSShift);
2836 }
84fa7933 2837 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 2838 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 2839
2840 if (ip->protocol == IPPROTO_TCP)
2841 return IPCS | TCPCS;
2842 else if (ip->protocol == IPPROTO_UDP)
2843 return IPCS | UDPCS;
2844 WARN_ON(1); /* we need a WARN() */
2845 }
2846 return 0;
2847}
2848
2849static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2850{
2851 struct rtl8169_private *tp = netdev_priv(dev);
2852 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2853 struct TxDesc *txd = tp->TxDescArray + entry;
2854 void __iomem *ioaddr = tp->mmio_addr;
2855 dma_addr_t mapping;
2856 u32 status, len;
2857 u32 opts1;
188f4af0 2858 int ret = NETDEV_TX_OK;
5b0384f4 2859
1da177e4 2860 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
b57b7e5a
SH		 2861 if (netif_msg_drv(tp)) {
2862 printk(KERN_ERR
2863 "%s: BUG! Tx Ring full when queue awake!\n",
2864 dev->name);
2865 }
1da177e4
LT		 2866 goto err_stop;
2867 }
2868
2869 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2870 goto err_stop;
2871
2872 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2873
2874 frags = rtl8169_xmit_frags(tp, skb, opts1);
2875 if (frags) {
2876 len = skb_headlen(skb);
2877 opts1 |= FirstFrag;
2878 } else {
2879 len = skb->len;
2880
2881 if (unlikely(len < ETH_ZLEN)) {
5b057c6b 2882 if (skb_padto(skb, ETH_ZLEN))
1da177e4
LT		 2883 goto err_update_stats;
2884 len = ETH_ZLEN;
2885 }
2886
2887 opts1 |= FirstFrag | LastFrag;
2888 tp->tx_skb[entry].skb = skb;
2889 }
2890
2891 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2892
2893 tp->tx_skb[entry].len = len;
2894 txd->addr = cpu_to_le64(mapping);
2895 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2896
2897 wmb();
2898
2899 /* anti gcc 2.95.3 bugware (sic) */
2900 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2901 txd->opts1 = cpu_to_le32(status);
2902
2903 dev->trans_start = jiffies;
2904
2905 tp->cur_tx += frags + 1;
2906
2907 smp_wmb();
2908
275391a4 2909 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 2910
2911 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2912 netif_stop_queue(dev);
2913 smp_rmb();
2914 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2915 netif_wake_queue(dev);
2916 }
2917
2918out:
2919 return ret;
2920
2921err_stop:
2922 netif_stop_queue(dev);
188f4af0 2923 ret = NETDEV_TX_BUSY;
1da177e4 2924err_update_stats:
cebf8cc7 2925 dev->stats.tx_dropped++;
1da177e4
LT		 2926 goto out;
2927}
2928
2929static void rtl8169_pcierr_interrupt(struct net_device *dev)
2930{
2931 struct rtl8169_private *tp = netdev_priv(dev);
2932 struct pci_dev *pdev = tp->pci_dev;
2933 void __iomem *ioaddr = tp->mmio_addr;
2934 u16 pci_status, pci_cmd;
2935
2936 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2937 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2938
b57b7e5a
SH		 2939 if (netif_msg_intr(tp)) {
2940 printk(KERN_ERR
2941 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2942 dev->name, pci_cmd, pci_status);
2943 }
1da177e4
LT		 2944
2945 /*
2946 * The recovery sequence below admits a very elaborated explanation:
2947 * - it seems to work;
d03902b8
FR		 2948 * - I did not see what else could be done;
2949 * - it makes iop3xx happy.
1da177e4
LT		 2950 *
2951 * Feel free to adjust to your needs.
2952 */
a27993f3 2953 if (pdev->broken_parity_status)
d03902b8
FR		 2954 pci_cmd &= ~PCI_COMMAND_PARITY;
2955 else
2956 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2957
2958 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 2959
2960 pci_write_config_word(pdev, PCI_STATUS,
2961 pci_status & (PCI_STATUS_DETECTED_PARITY |
2962 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2963 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2964
2965 /* The infamous DAC f*ckup only happens at boot time */
2966 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
b57b7e5a
SH		 2967 if (netif_msg_intr(tp))
2968 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
1da177e4
LT		 2969 tp->cp_cmd &= ~PCIDAC;
2970 RTL_W16(CPlusCmd, tp->cp_cmd);
2971 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 2972 }
2973
2974 rtl8169_hw_reset(ioaddr);
d03902b8
FR		 2975
2976 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 2977}
2978
07d3f51f
FR		 2979static void rtl8169_tx_interrupt(struct net_device *dev,
2980 struct rtl8169_private *tp,
2981 void __iomem *ioaddr)
1da177e4
LT		 2982{
2983 unsigned int dirty_tx, tx_left;
2984
1da177e4
LT		 2985 dirty_tx = tp->dirty_tx;
2986 smp_rmb();
2987 tx_left = tp->cur_tx - dirty_tx;
2988
2989 while (tx_left > 0) {
2990 unsigned int entry = dirty_tx % NUM_TX_DESC;
2991 struct ring_info *tx_skb = tp->tx_skb + entry;
2992 u32 len = tx_skb->len;
2993 u32 status;
2994
2995 rmb();
2996 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2997 if (status & DescOwn)
2998 break;
2999
cebf8cc7
FR		 3000 dev->stats.tx_bytes += len;
3001 dev->stats.tx_packets++;
1da177e4
LT		 3002
3003 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3004
3005 if (status & LastFrag) {
3006 dev_kfree_skb_irq(tx_skb->skb);
3007 tx_skb->skb = NULL;
3008 }
3009 dirty_tx++;
3010 tx_left--;
3011 }
3012
3013 if (tp->dirty_tx != dirty_tx) {
3014 tp->dirty_tx = dirty_tx;
3015 smp_wmb();
3016 if (netif_queue_stopped(dev) &&
3017 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3018 netif_wake_queue(dev);
3019 }
d78ae2dc
FR		 3020 /*
3021 * 8168 hack: TxPoll requests are lost when the Tx packets are
3022 * too close. Let's kick an extra TxPoll request when a burst
3023 * of start_xmit activity is detected (if it is not detected,
3024 * it is slow enough). -- FR
3025 */
3026 smp_rmb();
3027 if (tp->cur_tx != dirty_tx)
3028 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 3029 }
3030}
3031
126fa4b9
FR		 3032static inline int rtl8169_fragmented_frame(u32 status)
3033{
3034 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3035}
3036
1da177e4
LT		 3037static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3038{
3039 u32 opts1 = le32_to_cpu(desc->opts1);
3040 u32 status = opts1 & RxProtoMask;
3041
3042 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3043 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3044 ((status == RxProtoIP) && !(opts1 & IPFail)))
3045 skb->ip_summed = CHECKSUM_UNNECESSARY;
3046 else
3047 skb->ip_summed = CHECKSUM_NONE;
3048}
3049
07d3f51f
FR		 3050static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3051 struct rtl8169_private *tp, int pkt_size,
3052 dma_addr_t addr)
1da177e4 3053{
b449655f
SH		 3054 struct sk_buff *skb;
3055 bool done = false;
1da177e4 3056
b449655f
SH		 3057 if (pkt_size >= rx_copybreak)
3058 goto out;
1da177e4 3059
07d3f51f 3060 skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
b449655f
SH		 3061 if (!skb)
3062 goto out;
3063
07d3f51f
FR		 3064 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3065 PCI_DMA_FROMDEVICE);
86402234 3066 skb_reserve(skb, NET_IP_ALIGN);
b449655f
SH		 3067 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3068 *sk_buff = skb;
3069 done = true;
3070out:
3071 return done;
1da177e4
LT		 3072}
3073
07d3f51f
FR		 3074static int rtl8169_rx_interrupt(struct net_device *dev,
3075 struct rtl8169_private *tp,
bea3348e 3076 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 3077{
3078 unsigned int cur_rx, rx_left;
3079 unsigned int delta, count;
3080
1da177e4
LT		 3081 cur_rx = tp->cur_rx;
3082 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 3083 rx_left = min(rx_left, budget);
1da177e4 3084
4dcb7d33 3085 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 3086 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 3087 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 3088 u32 status;
3089
3090 rmb();
126fa4b9 3091 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 3092
3093 if (status & DescOwn)
3094 break;
4dcb7d33 3095 if (unlikely(status & RxRES)) {
b57b7e5a
SH		 3096 if (netif_msg_rx_err(tp)) {
3097 printk(KERN_INFO
3098 "%s: Rx ERROR. status = %08x\n",
3099 dev->name, status);
3100 }
cebf8cc7 3101 dev->stats.rx_errors++;
1da177e4 3102 if (status & (RxRWT | RxRUNT))
cebf8cc7 3103 dev->stats.rx_length_errors++;
1da177e4 3104 if (status & RxCRC)
cebf8cc7 3105 dev->stats.rx_crc_errors++;
9dccf611
FR		 3106 if (status & RxFOVF) {
3107 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 3108 dev->stats.rx_fifo_errors++;
9dccf611 3109 }
126fa4b9 3110 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
1da177e4 3111 } else {
1da177e4 3112 struct sk_buff *skb = tp->Rx_skbuff[entry];
b449655f 3113 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 3114 int pkt_size = (status & 0x00001FFF) - 4;
b449655f 3115 struct pci_dev *pdev = tp->pci_dev;
1da177e4 3116
126fa4b9
FR		 3117 /*
3118 * The driver does not support incoming fragmented
3119 * frames. They are seen as a symptom of over-mtu
3120 * sized frames.
3121 */
3122 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 3123 dev->stats.rx_dropped++;
3124 dev->stats.rx_length_errors++;
126fa4b9 3125 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4dcb7d33 3126 continue;
126fa4b9
FR		 3127 }
3128
1da177e4 3129 rtl8169_rx_csum(skb, desc);
bcf0bf90 3130
07d3f51f 3131 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
b449655f
SH		 3132 pci_dma_sync_single_for_device(pdev, addr,
3133 pkt_size, PCI_DMA_FROMDEVICE);
3134 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3135 } else {
a866bbf6 3136 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
b449655f 3137 PCI_DMA_FROMDEVICE);
1da177e4
LT		 3138 tp->Rx_skbuff[entry] = NULL;
3139 }
3140
1da177e4
LT		 3141 skb_put(skb, pkt_size);
3142 skb->protocol = eth_type_trans(skb, dev);
3143
3144 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
865c652d 3145 netif_receive_skb(skb);
1da177e4
LT		 3146
3147 dev->last_rx = jiffies;
cebf8cc7
FR		 3148 dev->stats.rx_bytes += pkt_size;
3149 dev->stats.rx_packets++;
1da177e4 3150 }
6dccd16b
FR		 3151
3152 /* Work around for AMD plateform. */
95e0918d 3153 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 3154 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3155 desc->opts2 = 0;
3156 cur_rx++;
3157 }
1da177e4
LT		 3158 }
3159
3160 count = cur_rx - tp->cur_rx;
3161 tp->cur_rx = cur_rx;
3162
3163 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
b57b7e5a 3164 if (!delta && count && netif_msg_intr(tp))
1da177e4
LT		 3165 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3166 tp->dirty_rx += delta;
3167
3168 /*
3169 * FIXME: until there is periodic timer to try and refill the ring,
3170 * a temporary shortage may definitely kill the Rx process.
3171 * - disable the asic to try and avoid an overflow and kick it again
3172 * after refill ?
3173 * - how do others driver handle this condition (Uh oh...).
3174 */
b57b7e5a 3175 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
1da177e4
LT		 3176 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3177
3178 return count;
3179}
3180
07d3f51f 3181static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 3182{
07d3f51f 3183 struct net_device *dev = dev_instance;
1da177e4 3184 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3185 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3186 int handled = 0;
865c652d 3187 int status;
1da177e4 3188
865c652d 3189 status = RTL_R16(IntrStatus);
1da177e4 3190
865c652d
FR		 3191 /* hotplug/major error/no more work/shared irq */
3192 if ((status == 0xffff) || !status)
3193 goto out;
1da177e4 3194
865c652d 3195 handled = 1;
1da177e4 3196
865c652d
FR		 3197 if (unlikely(!netif_running(dev))) {
3198 rtl8169_asic_down(ioaddr);
3199 goto out;
3200 }
1da177e4 3201
865c652d
FR		 3202 status &= tp->intr_mask;
3203 RTL_W16(IntrStatus,
3204 (status & RxFIFOOver) ? (status | RxOverflow) : status);
1da177e4 3205
865c652d
FR		 3206 if (!(status & tp->intr_event))
3207 goto out;
0e485150 3208
865c652d
FR		 3209 /* Work around for rx fifo overflow */
3210 if (unlikely(status & RxFIFOOver) &&
3211 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3212 netif_stop_queue(dev);
3213 rtl8169_tx_timeout(dev);
3214 goto out;
3215 }
1da177e4 3216
865c652d
FR		 3217 if (unlikely(status & SYSErr)) {
3218 rtl8169_pcierr_interrupt(dev);
3219 goto out;
3220 }
1da177e4 3221
865c652d
FR		 3222 if (status & LinkChg)
3223 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4 3224
865c652d
FR		 3225 if (status & tp->napi_event) {
3226 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3227 tp->intr_mask = ~tp->napi_event;
313b0305 3228
bea3348e
SH		 3229 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3230 __netif_rx_schedule(dev, &tp->napi);
865c652d
FR		 3231 else if (netif_msg_intr(tp)) {
3232 printk(KERN_INFO "%s: interrupt %04x in poll\n",
3233 dev->name, status);
b57b7e5a 3234 }
1da177e4
LT		 3235 }
3236out:
3237 return IRQ_RETVAL(handled);
3238}
3239
bea3348e 3240static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 3241{
bea3348e
SH		 3242 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3243 struct net_device *dev = tp->dev;
1da177e4 3244 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 3245 int work_done;
1da177e4 3246
bea3348e 3247 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 3248 rtl8169_tx_interrupt(dev, tp, ioaddr);
3249
bea3348e
SH		 3250 if (work_done < budget) {
3251 netif_rx_complete(dev, napi);
1da177e4
LT		 3252 tp->intr_mask = 0xffff;
3253 /*
3254 * 20040426: the barrier is not strictly required but the
3255 * behavior of the irq handler could be less predictable
3256 * without it. Btw, the lack of flush for the posted pci
3257 * write is safe - FR
3258 */
3259 smp_wmb();
0e485150 3260 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3261 }
3262
bea3348e 3263 return work_done;
1da177e4 3264}
1da177e4 3265
523a6094
FR		 3266static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3267{
3268 struct rtl8169_private *tp = netdev_priv(dev);
3269
3270 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3271 return;
3272
3273 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3274 RTL_W32(RxMissed, 0);
3275}
3276
1da177e4
LT		 3277static void rtl8169_down(struct net_device *dev)
3278{
3279 struct rtl8169_private *tp = netdev_priv(dev);
3280 void __iomem *ioaddr = tp->mmio_addr;
733b736c 3281 unsigned int intrmask;
1da177e4
LT		 3282
3283 rtl8169_delete_timer(dev);
3284
3285 netif_stop_queue(dev);
3286
93dd79e8 3287 napi_disable(&tp->napi);
93dd79e8 3288
1da177e4
LT		 3289core_down:
3290 spin_lock_irq(&tp->lock);
3291
3292 rtl8169_asic_down(ioaddr);
3293
523a6094 3294 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3295
3296 spin_unlock_irq(&tp->lock);
3297
3298 synchronize_irq(dev->irq);
3299
1da177e4 3300 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 3301 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4
LT		 3302
3303 /*
3304 * And now for the 50k$ question: are IRQ disabled or not ?
3305 *
3306 * Two paths lead here:
3307 * 1) dev->close
3308 * -> netif_running() is available to sync the current code and the
3309 * IRQ handler. See rtl8169_interrupt for details.
3310 * 2) dev->change_mtu
3311 * -> rtl8169_poll can not be issued again and re-enable the
3312 * interruptions. Let's simply issue the IRQ down sequence again.
733b736c
AP		 3313 *
3314 * No loop if hotpluged or major error (0xffff).
1da177e4 3315 */
733b736c
AP		 3316 intrmask = RTL_R16(IntrMask);
3317 if (intrmask && (intrmask != 0xffff))
1da177e4
LT		 3318 goto core_down;
3319
3320 rtl8169_tx_clear(tp);
3321
3322 rtl8169_rx_clear(tp);
3323}
3324
3325static int rtl8169_close(struct net_device *dev)
3326{
3327 struct rtl8169_private *tp = netdev_priv(dev);
3328 struct pci_dev *pdev = tp->pci_dev;
3329
3330 rtl8169_down(dev);
3331
3332 free_irq(dev->irq, dev);
3333
1da177e4
LT		 3334 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3335 tp->RxPhyAddr);
3336 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3337 tp->TxPhyAddr);
3338 tp->TxDescArray = NULL;
3339 tp->RxDescArray = NULL;
3340
3341 return 0;
3342}
3343
07ce4064 3344static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 3345{
3346 struct rtl8169_private *tp = netdev_priv(dev);
3347 void __iomem *ioaddr = tp->mmio_addr;
3348 unsigned long flags;
3349 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 3350 int rx_mode;
1da177e4
LT		 3351 u32 tmp = 0;
3352
3353 if (dev->flags & IFF_PROMISC) {
3354 /* Unconditionally log net taps. */
b57b7e5a
SH		 3355 if (netif_msg_link(tp)) {
3356 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3357 dev->name);
3358 }
1da177e4
LT		 3359 rx_mode =
3360 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3361 AcceptAllPhys;
3362 mc_filter[1] = mc_filter[0] = 0xffffffff;
3363 } else if ((dev->mc_count > multicast_filter_limit)
3364 || (dev->flags & IFF_ALLMULTI)) {
3365 /* Too many to filter perfectly -- accept all multicasts. */
3366 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3367 mc_filter[1] = mc_filter[0] = 0xffffffff;
3368 } else {
3369 struct dev_mc_list *mclist;
07d3f51f
FR		 3370 unsigned int i;
3371
1da177e4
LT		 3372 rx_mode = AcceptBroadcast | AcceptMyPhys;
3373 mc_filter[1] = mc_filter[0] = 0;
3374 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3375 i++, mclist = mclist->next) {
3376 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3377 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3378 rx_mode |= AcceptMulticast;
3379 }
3380 }
3381
3382 spin_lock_irqsave(&tp->lock, flags);
3383
3384 tmp = rtl8169_rx_config | rx_mode |
3385 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3386
f887cce8 3387 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 3388 u32 data = mc_filter[0];
3389
3390 mc_filter[0] = swab32(mc_filter[1]);
3391 mc_filter[1] = swab32(data);
bcf0bf90
FR		 3392 }
3393
1da177e4
LT		 3394 RTL_W32(MAR0 + 0, mc_filter[0]);
3395 RTL_W32(MAR0 + 4, mc_filter[1]);
3396
57a9f236
FR		 3397 RTL_W32(RxConfig, tmp);
3398
1da177e4
LT		 3399 spin_unlock_irqrestore(&tp->lock, flags);
3400}
3401
3402/**
3403 * rtl8169_get_stats - Get rtl8169 read/write statistics
3404 * @dev: The Ethernet Device to get statistics for
3405 *
3406 * Get TX/RX statistics for rtl8169
3407 */
3408static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3409{
3410 struct rtl8169_private *tp = netdev_priv(dev);
3411 void __iomem *ioaddr = tp->mmio_addr;
3412 unsigned long flags;
3413
3414 if (netif_running(dev)) {
3415 spin_lock_irqsave(&tp->lock, flags);
523a6094 3416 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 3417 spin_unlock_irqrestore(&tp->lock, flags);
3418 }
5b0384f4 3419
cebf8cc7 3420 return &dev->stats;
1da177e4
LT		 3421}
3422
5d06a99f
FR		 3423#ifdef CONFIG_PM
3424
3425static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3426{
3427 struct net_device *dev = pci_get_drvdata(pdev);
3428 struct rtl8169_private *tp = netdev_priv(dev);
3429 void __iomem *ioaddr = tp->mmio_addr;
3430
3431 if (!netif_running(dev))
1371fa6d 3432 goto out_pci_suspend;
5d06a99f
FR		 3433
3434 netif_device_detach(dev);
3435 netif_stop_queue(dev);
3436
3437 spin_lock_irq(&tp->lock);
3438
3439 rtl8169_asic_down(ioaddr);
3440
523a6094 3441 rtl8169_rx_missed(dev, ioaddr);
5d06a99f
FR		 3442
3443 spin_unlock_irq(&tp->lock);
3444
1371fa6d 3445out_pci_suspend:
5d06a99f 3446 pci_save_state(pdev);
f23e7fda
FR		 3447 pci_enable_wake(pdev, pci_choose_state(pdev, state),
3448 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
5d06a99f 3449 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1371fa6d 3450
5d06a99f
FR		 3451 return 0;
3452}
3453
3454static int rtl8169_resume(struct pci_dev *pdev)
3455{
3456 struct net_device *dev = pci_get_drvdata(pdev);
3457
1371fa6d
FR		 3458 pci_set_power_state(pdev, PCI_D0);
3459 pci_restore_state(pdev);
3460 pci_enable_wake(pdev, PCI_D0, 0);
3461
5d06a99f
FR		 3462 if (!netif_running(dev))
3463 goto out;
3464
3465 netif_device_attach(dev);
3466
5d06a99f
FR		 3467 rtl8169_schedule_work(dev, rtl8169_reset_task);
3468out:
3469 return 0;
3470}
3471
3472#endif /* CONFIG_PM */
3473
1da177e4
LT		 3474static struct pci_driver rtl8169_pci_driver = {
3475 .name = MODULENAME,
3476 .id_table = rtl8169_pci_tbl,
3477 .probe = rtl8169_init_one,
3478 .remove = __devexit_p(rtl8169_remove_one),
3479#ifdef CONFIG_PM
3480 .suspend = rtl8169_suspend,
3481 .resume = rtl8169_resume,
3482#endif
3483};
3484
07d3f51f 3485static int __init rtl8169_init_module(void)
1da177e4 3486{
29917620 3487 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 3488}
3489
07d3f51f 3490static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 3491{
3492 pci_unregister_driver(&rtl8169_pci_driver);
3493}
3494
3495module_init(rtl8169_init_module);
3496module_exit(rtl8169_cleanup_module);
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