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inet_diag: fix inet_diag_bc_audit()
[mirror_ubuntu-zesty-kernel.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
ba04c7c9 28#include <linux/pci-aspm.h>
70c71606 29#include <linux/prefetch.h>
1da177e4 30
99f252b0 31#include <asm/system.h>
1da177e4
LT		 32#include <asm/io.h>
33#include <asm/irq.h>
34
865c652d 35#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 36#define MODULENAME "r8169"
37#define PFX MODULENAME ": "
38
bca03d5f 39#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
40#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
01dc7fec 41#define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
42#define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
5a5e4443 43#define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
bca03d5f 44
1da177e4
LT		 45#ifdef RTL8169_DEBUG
46#define assert(expr) \
5b0384f4
FR		 47 if (!(expr)) { \
48 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 49 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 50 }
06fa7358
JP		 51#define dprintk(fmt, args...) \
52 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 53#else
54#define assert(expr) do {} while (0)
55#define dprintk(fmt, args...) do {} while (0)
56#endif /* RTL8169_DEBUG */
57
b57b7e5a 58#define R8169_MSG_DEFAULT \
f0e837d9 59 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 60
1da177e4
LT		 61#define TX_BUFFS_AVAIL(tp) \
62 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
63
1da177e4
LT		 64/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
65 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 66static const int multicast_filter_limit = 32;
1da177e4
LT		 67
68/* MAC address length */
69#define MAC_ADDR_LEN 6
70
9c14ceaf 71#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 72#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
73#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
74#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 75#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
76#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
77
78#define R8169_REGS_SIZE 256
79#define R8169_NAPI_WEIGHT 64
80#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
81#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
82#define RX_BUF_SIZE 1536 /* Rx Buffer size */
83#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
84#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
85
86#define RTL8169_TX_TIMEOUT (6*HZ)
87#define RTL8169_PHY_TIMEOUT (10*HZ)
88
ea8dbdd1 89#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
90#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 91#define RTL_EEPROM_SIG_ADDR 0x0000
92
1da177e4
LT		 93/* write/read MMIO register */
94#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
95#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
96#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
97#define RTL_R8(reg) readb (ioaddr + (reg))
98#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 99#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 100
101enum mac_version {
85bffe6c
FR		 102 RTL_GIGA_MAC_VER_01 = 0,
103 RTL_GIGA_MAC_VER_02,
104 RTL_GIGA_MAC_VER_03,
105 RTL_GIGA_MAC_VER_04,
106 RTL_GIGA_MAC_VER_05,
107 RTL_GIGA_MAC_VER_06,
108 RTL_GIGA_MAC_VER_07,
109 RTL_GIGA_MAC_VER_08,
110 RTL_GIGA_MAC_VER_09,
111 RTL_GIGA_MAC_VER_10,
112 RTL_GIGA_MAC_VER_11,
113 RTL_GIGA_MAC_VER_12,
114 RTL_GIGA_MAC_VER_13,
115 RTL_GIGA_MAC_VER_14,
116 RTL_GIGA_MAC_VER_15,
117 RTL_GIGA_MAC_VER_16,
118 RTL_GIGA_MAC_VER_17,
119 RTL_GIGA_MAC_VER_18,
120 RTL_GIGA_MAC_VER_19,
121 RTL_GIGA_MAC_VER_20,
122 RTL_GIGA_MAC_VER_21,
123 RTL_GIGA_MAC_VER_22,
124 RTL_GIGA_MAC_VER_23,
125 RTL_GIGA_MAC_VER_24,
126 RTL_GIGA_MAC_VER_25,
127 RTL_GIGA_MAC_VER_26,
128 RTL_GIGA_MAC_VER_27,
129 RTL_GIGA_MAC_VER_28,
130 RTL_GIGA_MAC_VER_29,
131 RTL_GIGA_MAC_VER_30,
132 RTL_GIGA_MAC_VER_31,
133 RTL_GIGA_MAC_VER_32,
134 RTL_GIGA_MAC_VER_33,
135 RTL_GIGA_MAC_NONE = 0xff,
1da177e4
LT		 136};
137
2b7b4318
FR		 138enum rtl_tx_desc_version {
139 RTL_TD_0 = 0,
140 RTL_TD_1 = 1,
141};
142
85bffe6c
FR		 143#define _R(NAME,TD,FW) \
144 { .name = NAME, .txd_version = TD, .fw_name = FW }
1da177e4 145
3c6bee1d 146static const struct {
1da177e4 147 const char *name;
2b7b4318 148 enum rtl_tx_desc_version txd_version;
953a12cc 149 const char *fw_name;
85bffe6c
FR		 150} rtl_chip_infos[] = {
151 /* PCI devices. */
152 [RTL_GIGA_MAC_VER_01] =
153 _R("RTL8169", RTL_TD_0, NULL),
154 [RTL_GIGA_MAC_VER_02] =
155 _R("RTL8169s", RTL_TD_0, NULL),
156 [RTL_GIGA_MAC_VER_03] =
157 _R("RTL8110s", RTL_TD_0, NULL),
158 [RTL_GIGA_MAC_VER_04] =
159 _R("RTL8169sb/8110sb", RTL_TD_0, NULL),
160 [RTL_GIGA_MAC_VER_05] =
161 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
162 [RTL_GIGA_MAC_VER_06] =
163 _R("RTL8169sc/8110sc", RTL_TD_0, NULL),
164 /* PCI-E devices. */
165 [RTL_GIGA_MAC_VER_07] =
166 _R("RTL8102e", RTL_TD_1, NULL),
167 [RTL_GIGA_MAC_VER_08] =
168 _R("RTL8102e", RTL_TD_1, NULL),
169 [RTL_GIGA_MAC_VER_09] =
170 _R("RTL8102e", RTL_TD_1, NULL),
171 [RTL_GIGA_MAC_VER_10] =
172 _R("RTL8101e", RTL_TD_0, NULL),
173 [RTL_GIGA_MAC_VER_11] =
174 _R("RTL8168b/8111b", RTL_TD_0, NULL),
175 [RTL_GIGA_MAC_VER_12] =
176 _R("RTL8168b/8111b", RTL_TD_0, NULL),
177 [RTL_GIGA_MAC_VER_13] =
178 _R("RTL8101e", RTL_TD_0, NULL),
179 [RTL_GIGA_MAC_VER_14] =
180 _R("RTL8100e", RTL_TD_0, NULL),
181 [RTL_GIGA_MAC_VER_15] =
182 _R("RTL8100e", RTL_TD_0, NULL),
183 [RTL_GIGA_MAC_VER_16] =
184 _R("RTL8101e", RTL_TD_0, NULL),
185 [RTL_GIGA_MAC_VER_17] =
186 _R("RTL8168b/8111b", RTL_TD_0, NULL),
187 [RTL_GIGA_MAC_VER_18] =
188 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
189 [RTL_GIGA_MAC_VER_19] =
190 _R("RTL8168c/8111c", RTL_TD_1, NULL),
191 [RTL_GIGA_MAC_VER_20] =
192 _R("RTL8168c/8111c", RTL_TD_1, NULL),
193 [RTL_GIGA_MAC_VER_21] =
194 _R("RTL8168c/8111c", RTL_TD_1, NULL),
195 [RTL_GIGA_MAC_VER_22] =
196 _R("RTL8168c/8111c", RTL_TD_1, NULL),
197 [RTL_GIGA_MAC_VER_23] =
198 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
199 [RTL_GIGA_MAC_VER_24] =
200 _R("RTL8168cp/8111cp", RTL_TD_1, NULL),
201 [RTL_GIGA_MAC_VER_25] =
202 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_1),
203 [RTL_GIGA_MAC_VER_26] =
204 _R("RTL8168d/8111d", RTL_TD_1, FIRMWARE_8168D_2),
205 [RTL_GIGA_MAC_VER_27] =
206 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
207 [RTL_GIGA_MAC_VER_28] =
208 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
209 [RTL_GIGA_MAC_VER_29] =
210 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
211 [RTL_GIGA_MAC_VER_30] =
212 _R("RTL8105e", RTL_TD_1, FIRMWARE_8105E_1),
213 [RTL_GIGA_MAC_VER_31] =
214 _R("RTL8168dp/8111dp", RTL_TD_1, NULL),
215 [RTL_GIGA_MAC_VER_32] =
216 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_1),
217 [RTL_GIGA_MAC_VER_33] =
218 _R("RTL8168e/8111e", RTL_TD_1, FIRMWARE_8168E_2)
953a12cc 219};
85bffe6c 220#undef _R
953a12cc 221
bcf0bf90
FR		 222enum cfg_version {
223 RTL_CFG_0 = 0x00,
224 RTL_CFG_1,
225 RTL_CFG_2
226};
227
07ce4064
FR		 228static void rtl_hw_start_8169(struct net_device *);
229static void rtl_hw_start_8168(struct net_device *);
230static void rtl_hw_start_8101(struct net_device *);
231
a3aa1884 232static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 233 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 234 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 235 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 236 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 237 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
238 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 239 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 240 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
241 { PCI_VENDOR_ID_LINKSYS, 0x1032,
242 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 243 { 0x0001, 0x8168,
244 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 245 {0,},
246};
247
248MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
249
6f0333b8 250static int rx_buf_sz = 16383;
4300e8c7 251static int use_dac;
b57b7e5a
SH		 252static struct {
253 u32 msg_enable;
254} debug = { -1 };
1da177e4 255
07d3f51f
FR		 256enum rtl_registers {
257 MAC0 = 0, /* Ethernet hardware address. */
773d2021 258 MAC4 = 4,
07d3f51f
FR		 259 MAR0 = 8, /* Multicast filter. */
260 CounterAddrLow = 0x10,
261 CounterAddrHigh = 0x14,
262 TxDescStartAddrLow = 0x20,
263 TxDescStartAddrHigh = 0x24,
264 TxHDescStartAddrLow = 0x28,
265 TxHDescStartAddrHigh = 0x2c,
266 FLASH = 0x30,
267 ERSR = 0x36,
268 ChipCmd = 0x37,
269 TxPoll = 0x38,
270 IntrMask = 0x3c,
271 IntrStatus = 0x3e,
272 TxConfig = 0x40,
273 RxConfig = 0x44,
2b7b4318
FR		 274
275#define RTL_RX_CONFIG_MASK 0xff7e1880u
276
07d3f51f
FR		 277 RxMissed = 0x4c,
278 Cfg9346 = 0x50,
279 Config0 = 0x51,
280 Config1 = 0x52,
281 Config2 = 0x53,
282 Config3 = 0x54,
283 Config4 = 0x55,
284 Config5 = 0x56,
285 MultiIntr = 0x5c,
286 PHYAR = 0x60,
07d3f51f
FR		 287 PHYstatus = 0x6c,
288 RxMaxSize = 0xda,
289 CPlusCmd = 0xe0,
290 IntrMitigate = 0xe2,
291 RxDescAddrLow = 0xe4,
292 RxDescAddrHigh = 0xe8,
f0298f81 293 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
294
295#define NoEarlyTx 0x3f /* Max value : no early transmit. */
296
297 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
298
299#define TxPacketMax (8064 >> 7)
300
07d3f51f
FR		 301 FuncEvent = 0xf0,
302 FuncEventMask = 0xf4,
303 FuncPresetState = 0xf8,
304 FuncForceEvent = 0xfc,
1da177e4
LT		 305};
306
f162a5d1
FR		 307enum rtl8110_registers {
308 TBICSR = 0x64,
309 TBI_ANAR = 0x68,
310 TBI_LPAR = 0x6a,
311};
312
313enum rtl8168_8101_registers {
314 CSIDR = 0x64,
315 CSIAR = 0x68,
316#define CSIAR_FLAG 0x80000000
317#define CSIAR_WRITE_CMD 0x80000000
318#define CSIAR_BYTE_ENABLE 0x0f
319#define CSIAR_BYTE_ENABLE_SHIFT 12
320#define CSIAR_ADDR_MASK 0x0fff
065c27c1 321 PMCH = 0x6f,
f162a5d1
FR		 322 EPHYAR = 0x80,
323#define EPHYAR_FLAG 0x80000000
324#define EPHYAR_WRITE_CMD 0x80000000
325#define EPHYAR_REG_MASK 0x1f
326#define EPHYAR_REG_SHIFT 16
327#define EPHYAR_DATA_MASK 0xffff
5a5e4443
HW		 328 DLLPR = 0xd0,
329#define PM_SWITCH (1 << 6)
f162a5d1
FR		 330 DBG_REG = 0xd1,
331#define FIX_NAK_1 (1 << 4)
332#define FIX_NAK_2 (1 << 3)
5a5e4443
HW		 333 TWSI = 0xd2,
334 MCU = 0xd3,
335#define EN_NDP (1 << 3)
336#define EN_OOB_RESET (1 << 2)
daf9df6d 337 EFUSEAR = 0xdc,
338#define EFUSEAR_FLAG 0x80000000
339#define EFUSEAR_WRITE_CMD 0x80000000
340#define EFUSEAR_READ_CMD 0x00000000
341#define EFUSEAR_REG_MASK 0x03ff
342#define EFUSEAR_REG_SHIFT 8
343#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 344};
345
c0e45c1c 346enum rtl8168_registers {
b646d900 347 ERIDR = 0x70,
348 ERIAR = 0x74,
349#define ERIAR_FLAG 0x80000000
350#define ERIAR_WRITE_CMD 0x80000000
351#define ERIAR_READ_CMD 0x00000000
352#define ERIAR_ADDR_BYTE_ALIGN 4
353#define ERIAR_EXGMAC 0
354#define ERIAR_MSIX 1
355#define ERIAR_ASF 2
356#define ERIAR_TYPE_SHIFT 16
357#define ERIAR_BYTEEN 0x0f
358#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 359 EPHY_RXER_NUM = 0x7c,
360 OCPDR = 0xb0, /* OCP GPHY access */
361#define OCPDR_WRITE_CMD 0x80000000
362#define OCPDR_READ_CMD 0x00000000
363#define OCPDR_REG_MASK 0x7f
364#define OCPDR_GPHY_REG_SHIFT 16
365#define OCPDR_DATA_MASK 0xffff
366 OCPAR = 0xb4,
367#define OCPAR_FLAG 0x80000000
368#define OCPAR_GPHY_WRITE_CMD 0x8000f060
369#define OCPAR_GPHY_READ_CMD 0x0000f060
01dc7fec 370 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
371 MISC = 0xf0, /* 8168e only. */
cecb5fd7 372#define TXPLA_RST (1 << 29)
c0e45c1c 373};
374
07d3f51f 375enum rtl_register_content {
1da177e4 376 /* InterruptStatusBits */
07d3f51f
FR		 377 SYSErr = 0x8000,
378 PCSTimeout = 0x4000,
379 SWInt = 0x0100,
380 TxDescUnavail = 0x0080,
381 RxFIFOOver = 0x0040,
382 LinkChg = 0x0020,
383 RxOverflow = 0x0010,
384 TxErr = 0x0008,
385 TxOK = 0x0004,
386 RxErr = 0x0002,
387 RxOK = 0x0001,
1da177e4
LT		 388
389 /* RxStatusDesc */
9dccf611
FR		 390 RxFOVF = (1 << 23),
391 RxRWT = (1 << 22),
392 RxRES = (1 << 21),
393 RxRUNT = (1 << 20),
394 RxCRC = (1 << 19),
1da177e4
LT		 395
396 /* ChipCmdBits */
07d3f51f
FR		 397 CmdReset = 0x10,
398 CmdRxEnb = 0x08,
399 CmdTxEnb = 0x04,
400 RxBufEmpty = 0x01,
1da177e4 401
275391a4
FR		 402 /* TXPoll register p.5 */
403 HPQ = 0x80, /* Poll cmd on the high prio queue */
404 NPQ = 0x40, /* Poll cmd on the low prio queue */
405 FSWInt = 0x01, /* Forced software interrupt */
406
1da177e4 407 /* Cfg9346Bits */
07d3f51f
FR		 408 Cfg9346_Lock = 0x00,
409 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 410
411 /* rx_mode_bits */
07d3f51f
FR		 412 AcceptErr = 0x20,
413 AcceptRunt = 0x10,
414 AcceptBroadcast = 0x08,
415 AcceptMulticast = 0x04,
416 AcceptMyPhys = 0x02,
417 AcceptAllPhys = 0x01,
1da177e4
LT		 418
419 /* RxConfigBits */
07d3f51f
FR		 420 RxCfgFIFOShift = 13,
421 RxCfgDMAShift = 8,
1da177e4
LT		 422
423 /* TxConfigBits */
424 TxInterFrameGapShift = 24,
425 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
426
5d06a99f 427 /* Config1 register p.24 */
f162a5d1
FR		 428 LEDS1 = (1 << 7),
429 LEDS0 = (1 << 6),
fbac58fc 430 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 431 Speed_down = (1 << 4),
432 MEMMAP = (1 << 3),
433 IOMAP = (1 << 2),
434 VPD = (1 << 1),
5d06a99f
FR		 435 PMEnable = (1 << 0), /* Power Management Enable */
436
6dccd16b
FR		 437 /* Config2 register p. 25 */
438 PCI_Clock_66MHz = 0x01,
439 PCI_Clock_33MHz = 0x00,
440
61a4dcc2
FR		 441 /* Config3 register p.25 */
442 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
443 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 444 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 445
5d06a99f 446 /* Config5 register p.27 */
61a4dcc2
FR		 447 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
448 MWF = (1 << 5), /* Accept Multicast wakeup frame */
449 UWF = (1 << 4), /* Accept Unicast wakeup frame */
cecb5fd7 450 Spi_en = (1 << 3),
61a4dcc2 451 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 452 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
453
1da177e4
LT		 454 /* TBICSR p.28 */
455 TBIReset = 0x80000000,
456 TBILoopback = 0x40000000,
457 TBINwEnable = 0x20000000,
458 TBINwRestart = 0x10000000,
459 TBILinkOk = 0x02000000,
460 TBINwComplete = 0x01000000,
461
462 /* CPlusCmd p.31 */
f162a5d1
FR		 463 EnableBist = (1 << 15), // 8168 8101
464 Mac_dbgo_oe = (1 << 14), // 8168 8101
465 Normal_mode = (1 << 13), // unused
466 Force_half_dup = (1 << 12), // 8168 8101
467 Force_rxflow_en = (1 << 11), // 8168 8101
468 Force_txflow_en = (1 << 10), // 8168 8101
469 Cxpl_dbg_sel = (1 << 9), // 8168 8101
470 ASF = (1 << 8), // 8168 8101
471 PktCntrDisable = (1 << 7), // 8168 8101
472 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 473 RxVlan = (1 << 6),
474 RxChkSum = (1 << 5),
475 PCIDAC = (1 << 4),
476 PCIMulRW = (1 << 3),
0e485150
FR		 477 INTT_0 = 0x0000, // 8168
478 INTT_1 = 0x0001, // 8168
479 INTT_2 = 0x0002, // 8168
480 INTT_3 = 0x0003, // 8168
1da177e4
LT		 481
482 /* rtl8169_PHYstatus */
07d3f51f
FR		 483 TBI_Enable = 0x80,
484 TxFlowCtrl = 0x40,
485 RxFlowCtrl = 0x20,
486 _1000bpsF = 0x10,
487 _100bps = 0x08,
488 _10bps = 0x04,
489 LinkStatus = 0x02,
490 FullDup = 0x01,
1da177e4 491
1da177e4 492 /* _TBICSRBit */
07d3f51f 493 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 494
495 /* DumpCounterCommand */
07d3f51f 496 CounterDump = 0x8,
1da177e4
LT		 497};
498
2b7b4318
FR		 499enum rtl_desc_bit {
500 /* First doubleword. */
1da177e4
LT		 501 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
502 RingEnd = (1 << 30), /* End of descriptor ring */
503 FirstFrag = (1 << 29), /* First segment of a packet */
504 LastFrag = (1 << 28), /* Final segment of a packet */
2b7b4318
FR		 505};
506
507/* Generic case. */
508enum rtl_tx_desc_bit {
509 /* First doubleword. */
510 TD_LSO = (1 << 27), /* Large Send Offload */
511#define TD_MSS_MAX 0x07ffu /* MSS value */
1da177e4 512
2b7b4318
FR		 513 /* Second doubleword. */
514 TxVlanTag = (1 << 17), /* Add VLAN tag */
515};
516
517/* 8169, 8168b and 810x except 8102e. */
518enum rtl_tx_desc_bit_0 {
519 /* First doubleword. */
520#define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
521 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
522 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
523 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
524};
525
526/* 8102e, 8168c and beyond. */
527enum rtl_tx_desc_bit_1 {
528 /* Second doubleword. */
529#define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
530 TD1_IP_CS = (1 << 29), /* Calculate IP checksum */
531 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
532 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
533};
1da177e4 534
2b7b4318
FR		 535static const struct rtl_tx_desc_info {
536 struct {
537 u32 udp;
538 u32 tcp;
539 } checksum;
540 u16 mss_shift;
541 u16 opts_offset;
542} tx_desc_info [] = {
543 [RTL_TD_0] = {
544 .checksum = {
545 .udp = TD0_IP_CS | TD0_UDP_CS,
546 .tcp = TD0_IP_CS | TD0_TCP_CS
547 },
548 .mss_shift = TD0_MSS_SHIFT,
549 .opts_offset = 0
550 },
551 [RTL_TD_1] = {
552 .checksum = {
553 .udp = TD1_IP_CS | TD1_UDP_CS,
554 .tcp = TD1_IP_CS | TD1_TCP_CS
555 },
556 .mss_shift = TD1_MSS_SHIFT,
557 .opts_offset = 1
558 }
559};
560
561enum rtl_rx_desc_bit {
1da177e4
LT		 562 /* Rx private */
563 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
564 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
565
566#define RxProtoUDP (PID1)
567#define RxProtoTCP (PID0)
568#define RxProtoIP (PID1 | PID0)
569#define RxProtoMask RxProtoIP
570
571 IPFail = (1 << 16), /* IP checksum failed */
572 UDPFail = (1 << 15), /* UDP/IP checksum failed */
573 TCPFail = (1 << 14), /* TCP/IP checksum failed */
574 RxVlanTag = (1 << 16), /* VLAN tag available */
575};
576
577#define RsvdMask 0x3fffc000
578
579struct TxDesc {
6cccd6e7
REB		 580 __le32 opts1;
581 __le32 opts2;
582 __le64 addr;
1da177e4
LT		 583};
584
585struct RxDesc {
6cccd6e7
REB		 586 __le32 opts1;
587 __le32 opts2;
588 __le64 addr;
1da177e4
LT		 589};
590
591struct ring_info {
592 struct sk_buff *skb;
593 u32 len;
594 u8 __pad[sizeof(void *) - sizeof(u32)];
595};
596
f23e7fda 597enum features {
ccdffb9a
FR		 598 RTL_FEATURE_WOL = (1 << 0),
599 RTL_FEATURE_MSI = (1 << 1),
600 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 601};
602
355423d0
IV		 603struct rtl8169_counters {
604 __le64 tx_packets;
605 __le64 rx_packets;
606 __le64 tx_errors;
607 __le32 rx_errors;
608 __le16 rx_missed;
609 __le16 align_errors;
610 __le32 tx_one_collision;
611 __le32 tx_multi_collision;
612 __le64 rx_unicast;
613 __le64 rx_broadcast;
614 __le32 rx_multicast;
615 __le16 tx_aborted;
616 __le16 tx_underun;
617};
618
1da177e4
LT		 619struct rtl8169_private {
620 void __iomem *mmio_addr; /* memory map physical address */
cecb5fd7 621 struct pci_dev *pci_dev;
c4028958 622 struct net_device *dev;
bea3348e 623 struct napi_struct napi;
cecb5fd7 624 spinlock_t lock;
b57b7e5a 625 u32 msg_enable;
2b7b4318
FR		 626 u16 txd_version;
627 u16 mac_version;
1da177e4
LT		 628 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
629 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
630 u32 dirty_rx;
631 u32 dirty_tx;
632 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
633 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
634 dma_addr_t TxPhyAddr;
635 dma_addr_t RxPhyAddr;
6f0333b8 636 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 637 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 638 struct timer_list timer;
639 u16 cp_cmd;
0e485150
FR		 640 u16 intr_event;
641 u16 napi_event;
1da177e4 642 u16 intr_mask;
c0e45c1c 643
644 struct mdio_ops {
645 void (*write)(void __iomem *, int, int);
646 int (*read)(void __iomem *, int);
647 } mdio_ops;
648
065c27c1 649 struct pll_power_ops {
650 void (*down)(struct rtl8169_private *);
651 void (*up)(struct rtl8169_private *);
652 } pll_power_ops;
653
54405cde 654 int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
ccdffb9a 655 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 656 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 657 void (*hw_start)(struct net_device *);
4da19633 658 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 659 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 660 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 661 int pcie_cap;
c4028958 662 struct delayed_work task;
f23e7fda 663 unsigned features;
ccdffb9a
FR		 664
665 struct mii_if_info mii;
355423d0 666 struct rtl8169_counters counters;
e1759441 667 u32 saved_wolopts;
f1e02ed1 668
669 const struct firmware *fw;
953a12cc 670#define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN);
1da177e4
LT		 671};
672
979b6c13 673MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 674MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 675module_param(use_dac, int, 0);
4300e8c7 676MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 677module_param_named(debug, debug.msg_enable, int, 0);
678MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 679MODULE_LICENSE("GPL");
680MODULE_VERSION(RTL8169_VERSION);
bca03d5f 681MODULE_FIRMWARE(FIRMWARE_8168D_1);
682MODULE_FIRMWARE(FIRMWARE_8168D_2);
01dc7fec 683MODULE_FIRMWARE(FIRMWARE_8168E_1);
684MODULE_FIRMWARE(FIRMWARE_8168E_2);
5a5e4443 685MODULE_FIRMWARE(FIRMWARE_8105E_1);
1da177e4
LT		 686
687static int rtl8169_open(struct net_device *dev);
61357325
SH		 688static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
689 struct net_device *dev);
7d12e780 690static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 691static int rtl8169_init_ring(struct net_device *dev);
07ce4064 692static void rtl_hw_start(struct net_device *dev);
1da177e4 693static int rtl8169_close(struct net_device *dev);
07ce4064 694static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 695static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 696static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 697static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 698 void __iomem *, u32 budget);
4dcb7d33 699static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 700static void rtl8169_down(struct net_device *dev);
99f252b0 701static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 702static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 703
1da177e4 704static const unsigned int rtl8169_rx_config =
5b0384f4 705 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 706
b646d900 707static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
708{
709 void __iomem *ioaddr = tp->mmio_addr;
710 int i;
711
712 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
713 for (i = 0; i < 20; i++) {
714 udelay(100);
715 if (RTL_R32(OCPAR) & OCPAR_FLAG)
716 break;
717 }
718 return RTL_R32(OCPDR);
719}
720
721static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
722{
723 void __iomem *ioaddr = tp->mmio_addr;
724 int i;
725
726 RTL_W32(OCPDR, data);
727 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
728 for (i = 0; i < 20; i++) {
729 udelay(100);
730 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
731 break;
732 }
733}
734
fac5b3ca 735static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 736{
fac5b3ca 737 void __iomem *ioaddr = tp->mmio_addr;
b646d900 738 int i;
739
740 RTL_W8(ERIDR, cmd);
741 RTL_W32(ERIAR, 0x800010e8);
742 msleep(2);
743 for (i = 0; i < 5; i++) {
744 udelay(100);
745 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
746 break;
747 }
748
fac5b3ca 749 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 750}
751
752#define OOB_CMD_RESET 0x00
753#define OOB_CMD_DRIVER_START 0x05
754#define OOB_CMD_DRIVER_STOP 0x06
755
cecb5fd7
FR		 756static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
757{
758 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
759}
760
b646d900 761static void rtl8168_driver_start(struct rtl8169_private *tp)
762{
cecb5fd7 763 u16 reg;
b646d900 764 int i;
765
766 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
767
cecb5fd7 768 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 769
b646d900 770 for (i = 0; i < 10; i++) {
771 msleep(10);
4804b3b3 772 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
b646d900 773 break;
774 }
775}
776
777static void rtl8168_driver_stop(struct rtl8169_private *tp)
778{
cecb5fd7 779 u16 reg;
b646d900 780 int i;
781
782 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
783
cecb5fd7 784 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 785
b646d900 786 for (i = 0; i < 10; i++) {
787 msleep(10);
4804b3b3 788 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
b646d900 789 break;
790 }
791}
792
4804b3b3 793static int r8168dp_check_dash(struct rtl8169_private *tp)
794{
cecb5fd7 795 u16 reg = rtl8168_get_ocp_reg(tp);
4804b3b3 796
cecb5fd7 797 return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
4804b3b3 798}
b646d900 799
4da19633 800static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 801{
802 int i;
803
a6baf3af 804 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 805
2371408c 806 for (i = 20; i > 0; i--) {
07d3f51f
FR		 807 /*
808 * Check if the RTL8169 has completed writing to the specified
809 * MII register.
810 */
5b0384f4 811 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 812 break;
2371408c 813 udelay(25);
1da177e4 814 }
024a07ba 815 /*
81a95f04
TT		 816 * According to hardware specs a 20us delay is required after write
817 * complete indication, but before sending next command.
024a07ba 818 */
81a95f04 819 udelay(20);
1da177e4
LT		 820}
821
4da19633 822static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 823{
824 int i, value = -1;
825
a6baf3af 826 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 827
2371408c 828 for (i = 20; i > 0; i--) {
07d3f51f
FR		 829 /*
830 * Check if the RTL8169 has completed retrieving data from
831 * the specified MII register.
832 */
1da177e4 833 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 834 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 835 break;
836 }
2371408c 837 udelay(25);
1da177e4 838 }
81a95f04
TT		 839 /*
840 * According to hardware specs a 20us delay is required after read
841 * complete indication, but before sending next command.
842 */
843 udelay(20);
844
1da177e4
LT		 845 return value;
846}
847
c0e45c1c 848static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
849{
850 int i;
851
852 RTL_W32(OCPDR, data |
853 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
854 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
855 RTL_W32(EPHY_RXER_NUM, 0);
856
857 for (i = 0; i < 100; i++) {
858 mdelay(1);
859 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
860 break;
861 }
862}
863
864static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
865{
866 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
867 (value & OCPDR_DATA_MASK));
868}
869
870static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
871{
872 int i;
873
874 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
875
876 mdelay(1);
877 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
878 RTL_W32(EPHY_RXER_NUM, 0);
879
880 for (i = 0; i < 100; i++) {
881 mdelay(1);
882 if (RTL_R32(OCPAR) & OCPAR_FLAG)
883 break;
884 }
885
886 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
887}
888
e6de30d6 889#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
890
891static void r8168dp_2_mdio_start(void __iomem *ioaddr)
892{
893 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
894}
895
896static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
897{
898 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
899}
900
901static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
902{
903 r8168dp_2_mdio_start(ioaddr);
904
905 r8169_mdio_write(ioaddr, reg_addr, value);
906
907 r8168dp_2_mdio_stop(ioaddr);
908}
909
910static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
911{
912 int value;
913
914 r8168dp_2_mdio_start(ioaddr);
915
916 value = r8169_mdio_read(ioaddr, reg_addr);
917
918 r8168dp_2_mdio_stop(ioaddr);
919
920 return value;
921}
922
4da19633 923static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 924{
c0e45c1c 925 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 926}
927
4da19633 928static int rtl_readphy(struct rtl8169_private *tp, int location)
929{
c0e45c1c 930 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 931}
932
933static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
934{
935 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
936}
937
938static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 939{
940 int val;
941
4da19633 942 val = rtl_readphy(tp, reg_addr);
943 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 944}
945
ccdffb9a
FR		 946static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
947 int val)
948{
949 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 950
4da19633 951 rtl_writephy(tp, location, val);
ccdffb9a
FR		 952}
953
954static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
955{
956 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 957
4da19633 958 return rtl_readphy(tp, location);
ccdffb9a
FR		 959}
960
dacf8154
FR		 961static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
962{
963 unsigned int i;
964
965 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
966 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
967
968 for (i = 0; i < 100; i++) {
969 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
970 break;
971 udelay(10);
972 }
973}
974
975static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
976{
977 u16 value = 0xffff;
978 unsigned int i;
979
980 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
981
982 for (i = 0; i < 100; i++) {
983 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
984 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
985 break;
986 }
987 udelay(10);
988 }
989
990 return value;
991}
992
993static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
994{
995 unsigned int i;
996
997 RTL_W32(CSIDR, value);
998 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
999 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1000
1001 for (i = 0; i < 100; i++) {
1002 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1003 break;
1004 udelay(10);
1005 }
1006}
1007
1008static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1009{
1010 u32 value = ~0x00;
1011 unsigned int i;
1012
1013 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1014 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1015
1016 for (i = 0; i < 100; i++) {
1017 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1018 value = RTL_R32(CSIDR);
1019 break;
1020 }
1021 udelay(10);
1022 }
1023
1024 return value;
1025}
1026
daf9df6d 1027static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1028{
1029 u8 value = 0xff;
1030 unsigned int i;
1031
1032 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1033
1034 for (i = 0; i < 300; i++) {
1035 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1036 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1037 break;
1038 }
1039 udelay(100);
1040 }
1041
1042 return value;
1043}
1044
1da177e4
LT		 1045static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1046{
1047 RTL_W16(IntrMask, 0x0000);
1048
1049 RTL_W16(IntrStatus, 0xffff);
1050}
1051
1052static void rtl8169_asic_down(void __iomem *ioaddr)
1053{
1054 RTL_W8(ChipCmd, 0x00);
1055 rtl8169_irq_mask_and_ack(ioaddr);
1056 RTL_R16(CPlusCmd);
1057}
1058
4da19633 1059static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 1060{
4da19633 1061 void __iomem *ioaddr = tp->mmio_addr;
1062
1da177e4
LT		 1063 return RTL_R32(TBICSR) & TBIReset;
1064}
1065
4da19633 1066static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 1067{
4da19633 1068 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 1069}
1070
1071static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1072{
1073 return RTL_R32(TBICSR) & TBILinkOk;
1074}
1075
1076static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1077{
1078 return RTL_R8(PHYstatus) & LinkStatus;
1079}
1080
4da19633 1081static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 1082{
4da19633 1083 void __iomem *ioaddr = tp->mmio_addr;
1084
1da177e4
LT		 1085 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1086}
1087
4da19633 1088static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 1089{
1090 unsigned int val;
1091
4da19633 1092 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1093 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 1094}
1095
e4fbce74 1096static void __rtl8169_check_link_status(struct net_device *dev,
cecb5fd7
FR		 1097 struct rtl8169_private *tp,
1098 void __iomem *ioaddr, bool pm)
1da177e4
LT		 1099{
1100 unsigned long flags;
1101
1102 spin_lock_irqsave(&tp->lock, flags);
1103 if (tp->link_ok(ioaddr)) {
e1759441 1104 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 1105 if (pm)
1106 pm_request_resume(&tp->pci_dev->dev);
1da177e4 1107 netif_carrier_on(dev);
1519e57f
FR		 1108 if (net_ratelimit())
1109 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 1110 } else {
1da177e4 1111 netif_carrier_off(dev);
bf82c189 1112 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 1113 if (pm)
1114 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 1115 }
1da177e4
LT		 1116 spin_unlock_irqrestore(&tp->lock, flags);
1117}
1118
e4fbce74
RW		 1119static void rtl8169_check_link_status(struct net_device *dev,
1120 struct rtl8169_private *tp,
1121 void __iomem *ioaddr)
1122{
1123 __rtl8169_check_link_status(dev, tp, ioaddr, false);
1124}
1125
e1759441
RW		 1126#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1127
1128static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 1129{
61a4dcc2
FR		 1130 void __iomem *ioaddr = tp->mmio_addr;
1131 u8 options;
e1759441 1132 u32 wolopts = 0;
61a4dcc2
FR		 1133
1134 options = RTL_R8(Config1);
1135 if (!(options & PMEnable))
e1759441 1136 return 0;
61a4dcc2
FR		 1137
1138 options = RTL_R8(Config3);
1139 if (options & LinkUp)
e1759441 1140 wolopts |= WAKE_PHY;
61a4dcc2 1141 if (options & MagicPacket)
e1759441 1142 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1143
1144 options = RTL_R8(Config5);
1145 if (options & UWF)
e1759441 1146 wolopts |= WAKE_UCAST;
61a4dcc2 1147 if (options & BWF)
e1759441 1148 wolopts |= WAKE_BCAST;
61a4dcc2 1149 if (options & MWF)
e1759441 1150 wolopts |= WAKE_MCAST;
61a4dcc2 1151
e1759441 1152 return wolopts;
61a4dcc2
FR		 1153}
1154
e1759441 1155static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1156{
1157 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1158
1159 spin_lock_irq(&tp->lock);
1160
1161 wol->supported = WAKE_ANY;
1162 wol->wolopts = __rtl8169_get_wol(tp);
1163
1164 spin_unlock_irq(&tp->lock);
1165}
1166
1167static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1168{
61a4dcc2 1169 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1170 unsigned int i;
350f7596 1171 static const struct {
61a4dcc2
FR		 1172 u32 opt;
1173 u16 reg;
1174 u8 mask;
1175 } cfg[] = {
1176 { WAKE_ANY, Config1, PMEnable },
1177 { WAKE_PHY, Config3, LinkUp },
1178 { WAKE_MAGIC, Config3, MagicPacket },
1179 { WAKE_UCAST, Config5, UWF },
1180 { WAKE_BCAST, Config5, BWF },
1181 { WAKE_MCAST, Config5, MWF },
1182 { WAKE_ANY, Config5, LanWake }
1183 };
1184
61a4dcc2
FR		 1185 RTL_W8(Cfg9346, Cfg9346_Unlock);
1186
1187 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1188 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1189 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1190 options |= cfg[i].mask;
1191 RTL_W8(cfg[i].reg, options);
1192 }
1193
1194 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1195}
1196
1197static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1198{
1199 struct rtl8169_private *tp = netdev_priv(dev);
1200
1201 spin_lock_irq(&tp->lock);
61a4dcc2 1202
f23e7fda
FR		 1203 if (wol->wolopts)
1204 tp->features |= RTL_FEATURE_WOL;
1205 else
1206 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1207 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1208 spin_unlock_irq(&tp->lock);
1209
ea80907f 1210 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1211
61a4dcc2
FR		 1212 return 0;
1213}
1214
31bd204f
FR		 1215static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1216{
85bffe6c 1217 return rtl_chip_infos[tp->mac_version].fw_name;
31bd204f
FR		 1218}
1219
1da177e4
LT		 1220static void rtl8169_get_drvinfo(struct net_device *dev,
1221 struct ethtool_drvinfo *info)
1222{
1223 struct rtl8169_private *tp = netdev_priv(dev);
1224
1225 strcpy(info->driver, MODULENAME);
1226 strcpy(info->version, RTL8169_VERSION);
1227 strcpy(info->bus_info, pci_name(tp->pci_dev));
31bd204f
FR		 1228 strncpy(info->fw_version, IS_ERR_OR_NULL(tp->fw) ? "N/A" :
1229 rtl_lookup_firmware_name(tp), sizeof(info->fw_version) - 1);
1da177e4
LT		 1230}
1231
1232static int rtl8169_get_regs_len(struct net_device *dev)
1233{
1234 return R8169_REGS_SIZE;
1235}
1236
1237static int rtl8169_set_speed_tbi(struct net_device *dev,
54405cde 1238 u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1da177e4
LT		 1239{
1240 struct rtl8169_private *tp = netdev_priv(dev);
1241 void __iomem *ioaddr = tp->mmio_addr;
1242 int ret = 0;
1243 u32 reg;
1244
1245 reg = RTL_R32(TBICSR);
1246 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1247 (duplex == DUPLEX_FULL)) {
1248 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1249 } else if (autoneg == AUTONEG_ENABLE)
1250 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1251 else {
bf82c189
JP		 1252 netif_warn(tp, link, dev,
1253 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1254 ret = -EOPNOTSUPP;
1255 }
1256
1257 return ret;
1258}
1259
1260static int rtl8169_set_speed_xmii(struct net_device *dev,
54405cde 1261 u8 autoneg, u16 speed, u8 duplex, u32 adv)
1da177e4
LT		 1262{
1263 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1264 int giga_ctrl, bmcr;
54405cde 1265 int rc = -EINVAL;
1da177e4 1266
716b50a3 1267 rtl_writephy(tp, 0x1f, 0x0000);
1da177e4
LT		 1268
1269 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1270 int auto_nego;
1271
4da19633 1272 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
54405cde
ON		 1273 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1274 ADVERTISE_100HALF | ADVERTISE_100FULL);
1275
1276 if (adv & ADVERTISED_10baseT_Half)
1277 auto_nego |= ADVERTISE_10HALF;
1278 if (adv & ADVERTISED_10baseT_Full)
1279 auto_nego |= ADVERTISE_10FULL;
1280 if (adv & ADVERTISED_100baseT_Half)
1281 auto_nego |= ADVERTISE_100HALF;
1282 if (adv & ADVERTISED_100baseT_Full)
1283 auto_nego |= ADVERTISE_100FULL;
1284
3577aa1b 1285 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1286
4da19633 1287 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1288 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1289
3577aa1b 1290 /* The 8100e/8101e/8102e do Fast Ethernet only. */
826e6cbd 1291 if (tp->mii.supports_gmii) {
54405cde
ON		 1292 if (adv & ADVERTISED_1000baseT_Half)
1293 giga_ctrl |= ADVERTISE_1000HALF;
1294 if (adv & ADVERTISED_1000baseT_Full)
1295 giga_ctrl |= ADVERTISE_1000FULL;
1296 } else if (adv & (ADVERTISED_1000baseT_Half |
1297 ADVERTISED_1000baseT_Full)) {
bf82c189
JP		 1298 netif_info(tp, link, dev,
1299 "PHY does not support 1000Mbps\n");
54405cde 1300 goto out;
bcf0bf90 1301 }
1da177e4 1302
3577aa1b 1303 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1304
4da19633 1305 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1306 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1307 } else {
1308 giga_ctrl = 0;
1309
1310 if (speed == SPEED_10)
1311 bmcr = 0;
1312 else if (speed == SPEED_100)
1313 bmcr = BMCR_SPEED100;
1314 else
54405cde 1315 goto out;
3577aa1b 1316
1317 if (duplex == DUPLEX_FULL)
1318 bmcr |= BMCR_FULLDPLX;
2584fbc3
RS		 1319 }
1320
4da19633 1321 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1322
cecb5fd7
FR		 1323 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1324 tp->mac_version == RTL_GIGA_MAC_VER_03) {
3577aa1b 1325 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1326 rtl_writephy(tp, 0x17, 0x2138);
1327 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1328 } else {
4da19633 1329 rtl_writephy(tp, 0x17, 0x2108);
1330 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1331 }
1332 }
1333
54405cde
ON		 1334 rc = 0;
1335out:
1336 return rc;
1da177e4
LT		 1337}
1338
1339static int rtl8169_set_speed(struct net_device *dev,
54405cde 1340 u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1da177e4
LT		 1341{
1342 struct rtl8169_private *tp = netdev_priv(dev);
1343 int ret;
1344
54405cde 1345 ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
4876cc1e
FR		 1346 if (ret < 0)
1347 goto out;
1da177e4 1348
4876cc1e
FR		 1349 if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1350 (advertising & ADVERTISED_1000baseT_Full)) {
1da177e4 1351 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
4876cc1e
FR		 1352 }
1353out:
1da177e4
LT		 1354 return ret;
1355}
1356
1357static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1358{
1359 struct rtl8169_private *tp = netdev_priv(dev);
1360 unsigned long flags;
1361 int ret;
1362
4876cc1e
FR		 1363 del_timer_sync(&tp->timer);
1364
1da177e4 1365 spin_lock_irqsave(&tp->lock, flags);
cecb5fd7 1366 ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
25db0338 1367 cmd->duplex, cmd->advertising);
1da177e4 1368 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1369
1da177e4
LT		 1370 return ret;
1371}
1372
350fb32a 1373static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1da177e4 1374{
2b7b4318 1375 if (dev->mtu > TD_MSS_MAX)
350fb32a 1376 features &= ~NETIF_F_ALL_TSO;
1da177e4 1377
350fb32a 1378 return features;
1da177e4
LT		 1379}
1380
350fb32a 1381static int rtl8169_set_features(struct net_device *dev, u32 features)
1da177e4
LT		 1382{
1383 struct rtl8169_private *tp = netdev_priv(dev);
1384 void __iomem *ioaddr = tp->mmio_addr;
1385 unsigned long flags;
1386
1387 spin_lock_irqsave(&tp->lock, flags);
1388
350fb32a 1389 if (features & NETIF_F_RXCSUM)
1da177e4
LT		 1390 tp->cp_cmd |= RxChkSum;
1391 else
1392 tp->cp_cmd &= ~RxChkSum;
1393
350fb32a
MM		 1394 if (dev->features & NETIF_F_HW_VLAN_RX)
1395 tp->cp_cmd |= RxVlan;
1396 else
1397 tp->cp_cmd &= ~RxVlan;
1398
1da177e4
LT		 1399 RTL_W16(CPlusCmd, tp->cp_cmd);
1400 RTL_R16(CPlusCmd);
1401
1402 spin_unlock_irqrestore(&tp->lock, flags);
1403
1404 return 0;
1405}
1406
1da177e4
LT		 1407static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1408 struct sk_buff *skb)
1409{
eab6d18d 1410 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1411 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1412}
1413
7a8fc77b 1414static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1da177e4
LT		 1415{
1416 u32 opts2 = le32_to_cpu(desc->opts2);
1da177e4 1417
7a8fc77b
FR		 1418 if (opts2 & RxVlanTag)
1419 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
2edae08e 1420
1da177e4 1421 desc->opts2 = 0;
1da177e4
LT		 1422}
1423
ccdffb9a 1424static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1425{
1426 struct rtl8169_private *tp = netdev_priv(dev);
1427 void __iomem *ioaddr = tp->mmio_addr;
1428 u32 status;
1429
1430 cmd->supported =
1431 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1432 cmd->port = PORT_FIBRE;
1433 cmd->transceiver = XCVR_INTERNAL;
1434
1435 status = RTL_R32(TBICSR);
1436 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1437 cmd->autoneg = !!(status & TBINwEnable);
1438
70739497 1439 ethtool_cmd_speed_set(cmd, SPEED_1000);
1da177e4 1440 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1441
1442 return 0;
1da177e4
LT		 1443}
1444
ccdffb9a 1445static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1446{
1447 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1448
1449 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1450}
1451
1452static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1453{
1454 struct rtl8169_private *tp = netdev_priv(dev);
1455 unsigned long flags;
ccdffb9a 1456 int rc;
1da177e4
LT		 1457
1458 spin_lock_irqsave(&tp->lock, flags);
1459
ccdffb9a 1460 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1461
1462 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1463 return rc;
1da177e4
LT		 1464}
1465
1466static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1467 void *p)
1468{
5b0384f4
FR		 1469 struct rtl8169_private *tp = netdev_priv(dev);
1470 unsigned long flags;
1da177e4 1471
5b0384f4
FR		 1472 if (regs->len > R8169_REGS_SIZE)
1473 regs->len = R8169_REGS_SIZE;
1da177e4 1474
5b0384f4
FR		 1475 spin_lock_irqsave(&tp->lock, flags);
1476 memcpy_fromio(p, tp->mmio_addr, regs->len);
1477 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1478}
1479
b57b7e5a
SH		 1480static u32 rtl8169_get_msglevel(struct net_device *dev)
1481{
1482 struct rtl8169_private *tp = netdev_priv(dev);
1483
1484 return tp->msg_enable;
1485}
1486
1487static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1488{
1489 struct rtl8169_private *tp = netdev_priv(dev);
1490
1491 tp->msg_enable = value;
1492}
1493
d4a3a0fc
SH		 1494static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1495 "tx_packets",
1496 "rx_packets",
1497 "tx_errors",
1498 "rx_errors",
1499 "rx_missed",
1500 "align_errors",
1501 "tx_single_collisions",
1502 "tx_multi_collisions",
1503 "unicast",
1504 "broadcast",
1505 "multicast",
1506 "tx_aborted",
1507 "tx_underrun",
1508};
1509
b9f2c044 1510static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1511{
b9f2c044
JG		 1512 switch (sset) {
1513 case ETH_SS_STATS:
1514 return ARRAY_SIZE(rtl8169_gstrings);
1515 default:
1516 return -EOPNOTSUPP;
1517 }
d4a3a0fc
SH		 1518}
1519
355423d0 1520static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1521{
1522 struct rtl8169_private *tp = netdev_priv(dev);
1523 void __iomem *ioaddr = tp->mmio_addr;
cecb5fd7 1524 struct device *d = &tp->pci_dev->dev;
d4a3a0fc
SH		 1525 struct rtl8169_counters *counters;
1526 dma_addr_t paddr;
1527 u32 cmd;
355423d0 1528 int wait = 1000;
d4a3a0fc 1529
355423d0
IV		 1530 /*
1531 * Some chips are unable to dump tally counters when the receiver
1532 * is disabled.
1533 */
1534 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1535 return;
d4a3a0fc 1536
48addcc9 1537 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1538 if (!counters)
1539 return;
1540
1541 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1542 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1543 RTL_W32(CounterAddrLow, cmd);
1544 RTL_W32(CounterAddrLow, cmd | CounterDump);
1545
355423d0
IV		 1546 while (wait--) {
1547 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
355423d0 1548 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1549 break;
355423d0
IV		 1550 }
1551 udelay(10);
d4a3a0fc
SH		 1552 }
1553
1554 RTL_W32(CounterAddrLow, 0);
1555 RTL_W32(CounterAddrHigh, 0);
1556
48addcc9 1557 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1558}
1559
355423d0
IV		 1560static void rtl8169_get_ethtool_stats(struct net_device *dev,
1561 struct ethtool_stats *stats, u64 *data)
1562{
1563 struct rtl8169_private *tp = netdev_priv(dev);
1564
1565 ASSERT_RTNL();
1566
1567 rtl8169_update_counters(dev);
1568
1569 data[0] = le64_to_cpu(tp->counters.tx_packets);
1570 data[1] = le64_to_cpu(tp->counters.rx_packets);
1571 data[2] = le64_to_cpu(tp->counters.tx_errors);
1572 data[3] = le32_to_cpu(tp->counters.rx_errors);
1573 data[4] = le16_to_cpu(tp->counters.rx_missed);
1574 data[5] = le16_to_cpu(tp->counters.align_errors);
1575 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1576 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1577 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1578 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1579 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1580 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1581 data[12] = le16_to_cpu(tp->counters.tx_underun);
1582}
1583
d4a3a0fc
SH		 1584static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1585{
1586 switch(stringset) {
1587 case ETH_SS_STATS:
1588 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1589 break;
1590 }
1591}
1592
7282d491 1593static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1594 .get_drvinfo = rtl8169_get_drvinfo,
1595 .get_regs_len = rtl8169_get_regs_len,
1596 .get_link = ethtool_op_get_link,
1597 .get_settings = rtl8169_get_settings,
1598 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1599 .get_msglevel = rtl8169_get_msglevel,
1600 .set_msglevel = rtl8169_set_msglevel,
1da177e4 1601 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1602 .get_wol = rtl8169_get_wol,
1603 .set_wol = rtl8169_set_wol,
d4a3a0fc 1604 .get_strings = rtl8169_get_strings,
b9f2c044 1605 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1606 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1607};
1608
07d3f51f 1609static void rtl8169_get_mac_version(struct rtl8169_private *tp,
5d320a20 1610 struct net_device *dev, u8 default_version)
1da177e4 1611{
5d320a20 1612 void __iomem *ioaddr = tp->mmio_addr;
0e485150
FR		 1613 /*
1614 * The driver currently handles the 8168Bf and the 8168Be identically
1615 * but they can be identified more specifically through the test below
1616 * if needed:
1617 *
1618 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1619 *
1620 * Same thing for the 8101Eb and the 8101Ec:
1621 *
1622 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1623 */
350f7596 1624 static const struct {
1da177e4 1625 u32 mask;
e3cf0cc0 1626 u32 val;
1da177e4
LT		 1627 int mac_version;
1628 } mac_info[] = {
01dc7fec 1629 /* 8168E family. */
1630 { 0x7cf00000, 0x2c200000, RTL_GIGA_MAC_VER_33 },
1631 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
1632 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
1633
5b538df9 1634 /* 8168D family. */
daf9df6d 1635 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1636 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1637 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1638
e6de30d6 1639 /* 8168DP family. */
1640 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1641 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
4804b3b3 1642 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
e6de30d6 1643
ef808d50 1644 /* 8168C family. */
17c99297 1645 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1646 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1647 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1648 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1649 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1650 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1651 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1652 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1653 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1654
1655 /* 8168B family. */
1656 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1657 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1658 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1659 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1660
1661 /* 8101 family. */
36a0e6c2 1662 { 0x7cf00000, 0x40b00000, RTL_GIGA_MAC_VER_30 },
5a5e4443
HW		 1663 { 0x7cf00000, 0x40a00000, RTL_GIGA_MAC_VER_30 },
1664 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
1665 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2857ffb7
FR		 1666 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1667 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1668 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1669 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1670 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1671 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1672 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1673 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1674 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1675 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1676 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1677 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1678 /* FIXME: where did these entries come from ? -- FR */
1679 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1680 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1681
1682 /* 8110 family. */
1683 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1684 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1685 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1686 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1687 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1688 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1689
f21b75e9
JD		 1690 /* Catch-all */
1691 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1692 }, *p = mac_info;
1693 u32 reg;
1694
e3cf0cc0
FR		 1695 reg = RTL_R32(TxConfig);
1696 while ((reg & p->mask) != p->val)
1da177e4
LT		 1697 p++;
1698 tp->mac_version = p->mac_version;
5d320a20
FR		 1699
1700 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1701 netif_notice(tp, probe, dev,
1702 "unknown MAC, using family default\n");
1703 tp->mac_version = default_version;
1704 }
1da177e4
LT		 1705}
1706
1707static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1708{
bcf0bf90 1709 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1710}
1711
867763c1
FR		 1712struct phy_reg {
1713 u16 reg;
1714 u16 val;
1715};
1716
4da19633 1717static void rtl_writephy_batch(struct rtl8169_private *tp,
1718 const struct phy_reg *regs, int len)
867763c1
FR		 1719{
1720 while (len-- > 0) {
4da19633 1721 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1722 regs++;
1723 }
1724}
1725
bca03d5f 1726#define PHY_READ 0x00000000
1727#define PHY_DATA_OR 0x10000000
1728#define PHY_DATA_AND 0x20000000
1729#define PHY_BJMPN 0x30000000
1730#define PHY_READ_EFUSE 0x40000000
1731#define PHY_READ_MAC_BYTE 0x50000000
1732#define PHY_WRITE_MAC_BYTE 0x60000000
1733#define PHY_CLEAR_READCOUNT 0x70000000
1734#define PHY_WRITE 0x80000000
1735#define PHY_READCOUNT_EQ_SKIP 0x90000000
1736#define PHY_COMP_EQ_SKIPN 0xa0000000
1737#define PHY_COMP_NEQ_SKIPN 0xb0000000
1738#define PHY_WRITE_PREVIOUS 0xc0000000
1739#define PHY_SKIPN 0xd0000000
1740#define PHY_DELAY_MS 0xe0000000
1741#define PHY_WRITE_ERI_WORD 0xf0000000
1742
1743static void
1744rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1745{
bca03d5f 1746 __le32 *phytable = (__le32 *)fw->data;
1747 struct net_device *dev = tp->dev;
42b82dc1 1748 size_t index, fw_size = fw->size / sizeof(*phytable);
1749 u32 predata, count;
bca03d5f 1750
1751 if (fw->size % sizeof(*phytable)) {
1752 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1753 return;
1754 }
1755
42b82dc1 1756 for (index = 0; index < fw_size; index++) {
1757 u32 action = le32_to_cpu(phytable[index]);
1758 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1759
42b82dc1 1760 switch(action & 0xf0000000) {
1761 case PHY_READ:
1762 case PHY_DATA_OR:
1763 case PHY_DATA_AND:
1764 case PHY_READ_EFUSE:
1765 case PHY_CLEAR_READCOUNT:
1766 case PHY_WRITE:
1767 case PHY_WRITE_PREVIOUS:
1768 case PHY_DELAY_MS:
1769 break;
1770
1771 case PHY_BJMPN:
1772 if (regno > index) {
1773 netif_err(tp, probe, tp->dev,
cecb5fd7 1774 "Out of range of firmware\n");
42b82dc1 1775 return;
1776 }
1777 break;
1778 case PHY_READCOUNT_EQ_SKIP:
1779 if (index + 2 >= fw_size) {
1780 netif_err(tp, probe, tp->dev,
cecb5fd7 1781 "Out of range of firmware\n");
42b82dc1 1782 return;
1783 }
1784 break;
1785 case PHY_COMP_EQ_SKIPN:
1786 case PHY_COMP_NEQ_SKIPN:
1787 case PHY_SKIPN:
1788 if (index + 1 + regno >= fw_size) {
1789 netif_err(tp, probe, tp->dev,
cecb5fd7 1790 "Out of range of firmware\n");
42b82dc1 1791 return;
1792 }
bca03d5f 1793 break;
1794
42b82dc1 1795 case PHY_READ_MAC_BYTE:
1796 case PHY_WRITE_MAC_BYTE:
1797 case PHY_WRITE_ERI_WORD:
1798 default:
1799 netif_err(tp, probe, tp->dev,
1800 "Invalid action 0x%08x\n", action);
bca03d5f 1801 return;
1802 }
1803 }
1804
42b82dc1 1805 predata = 0;
1806 count = 0;
1807
1808 for (index = 0; index < fw_size; ) {
1809 u32 action = le32_to_cpu(phytable[index]);
bca03d5f 1810 u32 data = action & 0x0000ffff;
42b82dc1 1811 u32 regno = (action & 0x0fff0000) >> 16;
1812
1813 if (!action)
1814 break;
bca03d5f 1815
1816 switch(action & 0xf0000000) {
42b82dc1 1817 case PHY_READ:
1818 predata = rtl_readphy(tp, regno);
1819 count++;
1820 index++;
1821 break;
1822 case PHY_DATA_OR:
1823 predata |= data;
1824 index++;
1825 break;
1826 case PHY_DATA_AND:
1827 predata &= data;
1828 index++;
1829 break;
1830 case PHY_BJMPN:
1831 index -= regno;
1832 break;
1833 case PHY_READ_EFUSE:
1834 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1835 index++;
1836 break;
1837 case PHY_CLEAR_READCOUNT:
1838 count = 0;
1839 index++;
1840 break;
bca03d5f 1841 case PHY_WRITE:
42b82dc1 1842 rtl_writephy(tp, regno, data);
1843 index++;
1844 break;
1845 case PHY_READCOUNT_EQ_SKIP:
cecb5fd7 1846 index += (count == data) ? 2 : 1;
bca03d5f 1847 break;
42b82dc1 1848 case PHY_COMP_EQ_SKIPN:
1849 if (predata == data)
1850 index += regno;
1851 index++;
1852 break;
1853 case PHY_COMP_NEQ_SKIPN:
1854 if (predata != data)
1855 index += regno;
1856 index++;
1857 break;
1858 case PHY_WRITE_PREVIOUS:
1859 rtl_writephy(tp, regno, predata);
1860 index++;
1861 break;
1862 case PHY_SKIPN:
1863 index += regno + 1;
1864 break;
1865 case PHY_DELAY_MS:
1866 mdelay(data);
1867 index++;
1868 break;
1869
1870 case PHY_READ_MAC_BYTE:
1871 case PHY_WRITE_MAC_BYTE:
1872 case PHY_WRITE_ERI_WORD:
bca03d5f 1873 default:
1874 BUG();
1875 }
1876 }
1877}
1878
f1e02ed1 1879static void rtl_release_firmware(struct rtl8169_private *tp)
1880{
953a12cc
FR		 1881 if (!IS_ERR_OR_NULL(tp->fw))
1882 release_firmware(tp->fw);
1883 tp->fw = RTL_FIRMWARE_UNKNOWN;
f1e02ed1 1884}
1885
953a12cc 1886static void rtl_apply_firmware(struct rtl8169_private *tp)
f1e02ed1 1887{
953a12cc 1888 const struct firmware *fw = tp->fw;
f1e02ed1 1889
1890 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
953a12cc
FR		 1891 if (!IS_ERR_OR_NULL(fw))
1892 rtl_phy_write_fw(tp, fw);
1893}
1894
1895static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1896{
1897 if (rtl_readphy(tp, reg) != val)
1898 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1899 else
1900 rtl_apply_firmware(tp);
f1e02ed1 1901}
1902
4da19633 1903static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1904{
350f7596 1905 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1906 { 0x1f, 0x0001 },
1907 { 0x06, 0x006e },
1908 { 0x08, 0x0708 },
1909 { 0x15, 0x4000 },
1910 { 0x18, 0x65c7 },
1da177e4 1911
0b9b571d 1912 { 0x1f, 0x0001 },
1913 { 0x03, 0x00a1 },
1914 { 0x02, 0x0008 },
1915 { 0x01, 0x0120 },
1916 { 0x00, 0x1000 },
1917 { 0x04, 0x0800 },
1918 { 0x04, 0x0000 },
1da177e4 1919
0b9b571d 1920 { 0x03, 0xff41 },
1921 { 0x02, 0xdf60 },
1922 { 0x01, 0x0140 },
1923 { 0x00, 0x0077 },
1924 { 0x04, 0x7800 },
1925 { 0x04, 0x7000 },
1926
1927 { 0x03, 0x802f },
1928 { 0x02, 0x4f02 },
1929 { 0x01, 0x0409 },
1930 { 0x00, 0xf0f9 },
1931 { 0x04, 0x9800 },
1932 { 0x04, 0x9000 },
1933
1934 { 0x03, 0xdf01 },
1935 { 0x02, 0xdf20 },
1936 { 0x01, 0xff95 },
1937 { 0x00, 0xba00 },
1938 { 0x04, 0xa800 },
1939 { 0x04, 0xa000 },
1940
1941 { 0x03, 0xff41 },
1942 { 0x02, 0xdf20 },
1943 { 0x01, 0x0140 },
1944 { 0x00, 0x00bb },
1945 { 0x04, 0xb800 },
1946 { 0x04, 0xb000 },
1947
1948 { 0x03, 0xdf41 },
1949 { 0x02, 0xdc60 },
1950 { 0x01, 0x6340 },
1951 { 0x00, 0x007d },
1952 { 0x04, 0xd800 },
1953 { 0x04, 0xd000 },
1954
1955 { 0x03, 0xdf01 },
1956 { 0x02, 0xdf20 },
1957 { 0x01, 0x100a },
1958 { 0x00, 0xa0ff },
1959 { 0x04, 0xf800 },
1960 { 0x04, 0xf000 },
1961
1962 { 0x1f, 0x0000 },
1963 { 0x0b, 0x0000 },
1964 { 0x00, 0x9200 }
1965 };
1da177e4 1966
4da19633 1967 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1968}
1969
4da19633 1970static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1971{
350f7596 1972 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1973 { 0x1f, 0x0002 },
1974 { 0x01, 0x90d0 },
1975 { 0x1f, 0x0000 }
1976 };
1977
4da19633 1978 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1979}
1980
4da19633 1981static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1982{
1983 struct pci_dev *pdev = tp->pci_dev;
1984 u16 vendor_id, device_id;
1985
1986 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1987 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1988
1989 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1990 return;
1991
4da19633 1992 rtl_writephy(tp, 0x1f, 0x0001);
1993 rtl_writephy(tp, 0x10, 0xf01b);
1994 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1995}
1996
4da19633 1997static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1998{
350f7596 1999 static const struct phy_reg phy_reg_init[] = {
2e955856 2000 { 0x1f, 0x0001 },
2001 { 0x04, 0x0000 },
2002 { 0x03, 0x00a1 },
2003 { 0x02, 0x0008 },
2004 { 0x01, 0x0120 },
2005 { 0x00, 0x1000 },
2006 { 0x04, 0x0800 },
2007 { 0x04, 0x9000 },
2008 { 0x03, 0x802f },
2009 { 0x02, 0x4f02 },
2010 { 0x01, 0x0409 },
2011 { 0x00, 0xf099 },
2012 { 0x04, 0x9800 },
2013 { 0x04, 0xa000 },
2014 { 0x03, 0xdf01 },
2015 { 0x02, 0xdf20 },
2016 { 0x01, 0xff95 },
2017 { 0x00, 0xba00 },
2018 { 0x04, 0xa800 },
2019 { 0x04, 0xf000 },
2020 { 0x03, 0xdf01 },
2021 { 0x02, 0xdf20 },
2022 { 0x01, 0x101a },
2023 { 0x00, 0xa0ff },
2024 { 0x04, 0xf800 },
2025 { 0x04, 0x0000 },
2026 { 0x1f, 0x0000 },
2027
2028 { 0x1f, 0x0001 },
2029 { 0x10, 0xf41b },
2030 { 0x14, 0xfb54 },
2031 { 0x18, 0xf5c7 },
2032 { 0x1f, 0x0000 },
2033
2034 { 0x1f, 0x0001 },
2035 { 0x17, 0x0cc0 },
2036 { 0x1f, 0x0000 }
2037 };
2038
4da19633 2039 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 2040
4da19633 2041 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 2042}
2043
4da19633 2044static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 2045{
350f7596 2046 static const struct phy_reg phy_reg_init[] = {
8c7006aa 2047 { 0x1f, 0x0001 },
2048 { 0x04, 0x0000 },
2049 { 0x03, 0x00a1 },
2050 { 0x02, 0x0008 },
2051 { 0x01, 0x0120 },
2052 { 0x00, 0x1000 },
2053 { 0x04, 0x0800 },
2054 { 0x04, 0x9000 },
2055 { 0x03, 0x802f },
2056 { 0x02, 0x4f02 },
2057 { 0x01, 0x0409 },
2058 { 0x00, 0xf099 },
2059 { 0x04, 0x9800 },
2060 { 0x04, 0xa000 },
2061 { 0x03, 0xdf01 },
2062 { 0x02, 0xdf20 },
2063 { 0x01, 0xff95 },
2064 { 0x00, 0xba00 },
2065 { 0x04, 0xa800 },
2066 { 0x04, 0xf000 },
2067 { 0x03, 0xdf01 },
2068 { 0x02, 0xdf20 },
2069 { 0x01, 0x101a },
2070 { 0x00, 0xa0ff },
2071 { 0x04, 0xf800 },
2072 { 0x04, 0x0000 },
2073 { 0x1f, 0x0000 },
2074
2075 { 0x1f, 0x0001 },
2076 { 0x0b, 0x8480 },
2077 { 0x1f, 0x0000 },
2078
2079 { 0x1f, 0x0001 },
2080 { 0x18, 0x67c7 },
2081 { 0x04, 0x2000 },
2082 { 0x03, 0x002f },
2083 { 0x02, 0x4360 },
2084 { 0x01, 0x0109 },
2085 { 0x00, 0x3022 },
2086 { 0x04, 0x2800 },
2087 { 0x1f, 0x0000 },
2088
2089 { 0x1f, 0x0001 },
2090 { 0x17, 0x0cc0 },
2091 { 0x1f, 0x0000 }
2092 };
2093
4da19633 2094 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 2095}
2096
4da19633 2097static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 2098{
350f7596 2099 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2100 { 0x10, 0xf41b },
2101 { 0x1f, 0x0000 }
2102 };
2103
4da19633 2104 rtl_writephy(tp, 0x1f, 0x0001);
2105 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 2106
4da19633 2107 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2108}
2109
4da19633 2110static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2111{
350f7596 2112 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2113 { 0x1f, 0x0001 },
2114 { 0x10, 0xf41b },
2115 { 0x1f, 0x0000 }
2116 };
2117
4da19633 2118 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2119}
2120
4da19633 2121static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2122{
350f7596 2123 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2124 { 0x1f, 0x0000 },
2125 { 0x1d, 0x0f00 },
2126 { 0x1f, 0x0002 },
2127 { 0x0c, 0x1ec8 },
2128 { 0x1f, 0x0000 }
2129 };
2130
4da19633 2131 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2132}
2133
4da19633 2134static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2135{
350f7596 2136 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2137 { 0x1f, 0x0001 },
2138 { 0x1d, 0x3d98 },
2139 { 0x1f, 0x0000 }
2140 };
2141
4da19633 2142 rtl_writephy(tp, 0x1f, 0x0000);
2143 rtl_patchphy(tp, 0x14, 1 << 5);
2144 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2145
4da19633 2146 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2147}
2148
4da19633 2149static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2150{
350f7596 2151 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2152 { 0x1f, 0x0001 },
2153 { 0x12, 0x2300 },
867763c1
FR		 2154 { 0x1f, 0x0002 },
2155 { 0x00, 0x88d4 },
2156 { 0x01, 0x82b1 },
2157 { 0x03, 0x7002 },
2158 { 0x08, 0x9e30 },
2159 { 0x09, 0x01f0 },
2160 { 0x0a, 0x5500 },
2161 { 0x0c, 0x00c8 },
2162 { 0x1f, 0x0003 },
2163 { 0x12, 0xc096 },
2164 { 0x16, 0x000a },
f50d4275
FR		 2165 { 0x1f, 0x0000 },
2166 { 0x1f, 0x0000 },
2167 { 0x09, 0x2000 },
2168 { 0x09, 0x0000 }
867763c1
FR		 2169 };
2170
4da19633 2171 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2172
4da19633 2173 rtl_patchphy(tp, 0x14, 1 << 5);
2174 rtl_patchphy(tp, 0x0d, 1 << 5);
2175 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2176}
2177
4da19633 2178static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2179{
350f7596 2180 static const struct phy_reg phy_reg_init[] = {
f50d4275 2181 { 0x1f, 0x0001 },
7da97ec9 2182 { 0x12, 0x2300 },
f50d4275
FR		 2183 { 0x03, 0x802f },
2184 { 0x02, 0x4f02 },
2185 { 0x01, 0x0409 },
2186 { 0x00, 0xf099 },
2187 { 0x04, 0x9800 },
2188 { 0x04, 0x9000 },
2189 { 0x1d, 0x3d98 },
7da97ec9
FR		 2190 { 0x1f, 0x0002 },
2191 { 0x0c, 0x7eb8 },
f50d4275
FR		 2192 { 0x06, 0x0761 },
2193 { 0x1f, 0x0003 },
2194 { 0x16, 0x0f0a },
7da97ec9
FR		 2195 { 0x1f, 0x0000 }
2196 };
2197
4da19633 2198 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2199
4da19633 2200 rtl_patchphy(tp, 0x16, 1 << 0);
2201 rtl_patchphy(tp, 0x14, 1 << 5);
2202 rtl_patchphy(tp, 0x0d, 1 << 5);
2203 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2204}
2205
4da19633 2206static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2207{
350f7596 2208 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2209 { 0x1f, 0x0001 },
2210 { 0x12, 0x2300 },
2211 { 0x1d, 0x3d98 },
2212 { 0x1f, 0x0002 },
2213 { 0x0c, 0x7eb8 },
2214 { 0x06, 0x5461 },
2215 { 0x1f, 0x0003 },
2216 { 0x16, 0x0f0a },
2217 { 0x1f, 0x0000 }
2218 };
2219
4da19633 2220 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2221
4da19633 2222 rtl_patchphy(tp, 0x16, 1 << 0);
2223 rtl_patchphy(tp, 0x14, 1 << 5);
2224 rtl_patchphy(tp, 0x0d, 1 << 5);
2225 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2226}
2227
4da19633 2228static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2229{
4da19633 2230 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2231}
2232
bca03d5f 2233static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2234{
350f7596 2235 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2236 /* Channel Estimation */
5b538df9 2237 { 0x1f, 0x0001 },
daf9df6d 2238 { 0x06, 0x4064 },
2239 { 0x07, 0x2863 },
2240 { 0x08, 0x059c },
2241 { 0x09, 0x26b4 },
2242 { 0x0a, 0x6a19 },
2243 { 0x0b, 0xdcc8 },
2244 { 0x10, 0xf06d },
2245 { 0x14, 0x7f68 },
2246 { 0x18, 0x7fd9 },
2247 { 0x1c, 0xf0ff },
2248 { 0x1d, 0x3d9c },
5b538df9 2249 { 0x1f, 0x0003 },
daf9df6d 2250 { 0x12, 0xf49f },
2251 { 0x13, 0x070b },
2252 { 0x1a, 0x05ad },
bca03d5f 2253 { 0x14, 0x94c0 },
2254
2255 /*
2256 * Tx Error Issue
cecb5fd7 2257 * Enhance line driver power
bca03d5f 2258 */
5b538df9 2259 { 0x1f, 0x0002 },
daf9df6d 2260 { 0x06, 0x5561 },
2261 { 0x1f, 0x0005 },
2262 { 0x05, 0x8332 },
bca03d5f 2263 { 0x06, 0x5561 },
2264
2265 /*
2266 * Can not link to 1Gbps with bad cable
2267 * Decrease SNR threshold form 21.07dB to 19.04dB
2268 */
2269 { 0x1f, 0x0001 },
2270 { 0x17, 0x0cc0 },
daf9df6d 2271
5b538df9 2272 { 0x1f, 0x0000 },
bca03d5f 2273 { 0x0d, 0xf880 }
daf9df6d 2274 };
bca03d5f 2275 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2276
4da19633 2277 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2278
bca03d5f 2279 /*
2280 * Rx Error Issue
2281 * Fine Tune Switching regulator parameter
2282 */
4da19633 2283 rtl_writephy(tp, 0x1f, 0x0002);
2284 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2285 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2286
daf9df6d 2287 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2288 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2289 { 0x1f, 0x0002 },
2290 { 0x05, 0x669a },
2291 { 0x1f, 0x0005 },
2292 { 0x05, 0x8330 },
2293 { 0x06, 0x669a },
2294 { 0x1f, 0x0002 }
2295 };
2296 int val;
2297
4da19633 2298 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2299
4da19633 2300 val = rtl_readphy(tp, 0x0d);
daf9df6d 2301
2302 if ((val & 0x00ff) != 0x006c) {
350f7596 2303 static const u32 set[] = {
daf9df6d 2304 0x0065, 0x0066, 0x0067, 0x0068,
2305 0x0069, 0x006a, 0x006b, 0x006c
2306 };
2307 int i;
2308
4da19633 2309 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2310
2311 val &= 0xff00;
2312 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2313 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2314 }
2315 } else {
350f7596 2316 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2317 { 0x1f, 0x0002 },
2318 { 0x05, 0x6662 },
2319 { 0x1f, 0x0005 },
2320 { 0x05, 0x8330 },
2321 { 0x06, 0x6662 }
2322 };
2323
4da19633 2324 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2325 }
2326
bca03d5f 2327 /* RSET couple improve */
4da19633 2328 rtl_writephy(tp, 0x1f, 0x0002);
2329 rtl_patchphy(tp, 0x0d, 0x0300);
2330 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2331
bca03d5f 2332 /* Fine tune PLL performance */
4da19633 2333 rtl_writephy(tp, 0x1f, 0x0002);
2334 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2335 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2336
4da19633 2337 rtl_writephy(tp, 0x1f, 0x0005);
2338 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2339
2340 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
bca03d5f 2341
4da19633 2342 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2343}
2344
bca03d5f 2345static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2346{
350f7596 2347 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2348 /* Channel Estimation */
daf9df6d 2349 { 0x1f, 0x0001 },
2350 { 0x06, 0x4064 },
2351 { 0x07, 0x2863 },
2352 { 0x08, 0x059c },
2353 { 0x09, 0x26b4 },
2354 { 0x0a, 0x6a19 },
2355 { 0x0b, 0xdcc8 },
2356 { 0x10, 0xf06d },
2357 { 0x14, 0x7f68 },
2358 { 0x18, 0x7fd9 },
2359 { 0x1c, 0xf0ff },
2360 { 0x1d, 0x3d9c },
2361 { 0x1f, 0x0003 },
2362 { 0x12, 0xf49f },
2363 { 0x13, 0x070b },
2364 { 0x1a, 0x05ad },
2365 { 0x14, 0x94c0 },
2366
bca03d5f 2367 /*
2368 * Tx Error Issue
cecb5fd7 2369 * Enhance line driver power
bca03d5f 2370 */
daf9df6d 2371 { 0x1f, 0x0002 },
2372 { 0x06, 0x5561 },
2373 { 0x1f, 0x0005 },
2374 { 0x05, 0x8332 },
bca03d5f 2375 { 0x06, 0x5561 },
2376
2377 /*
2378 * Can not link to 1Gbps with bad cable
2379 * Decrease SNR threshold form 21.07dB to 19.04dB
2380 */
2381 { 0x1f, 0x0001 },
2382 { 0x17, 0x0cc0 },
daf9df6d 2383
2384 { 0x1f, 0x0000 },
bca03d5f 2385 { 0x0d, 0xf880 }
5b538df9 2386 };
bca03d5f 2387 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2388
4da19633 2389 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2390
daf9df6d 2391 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2392 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2393 { 0x1f, 0x0002 },
2394 { 0x05, 0x669a },
5b538df9 2395 { 0x1f, 0x0005 },
daf9df6d 2396 { 0x05, 0x8330 },
2397 { 0x06, 0x669a },
2398
2399 { 0x1f, 0x0002 }
2400 };
2401 int val;
2402
4da19633 2403 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2404
4da19633 2405 val = rtl_readphy(tp, 0x0d);
daf9df6d 2406 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2407 static const u32 set[] = {
daf9df6d 2408 0x0065, 0x0066, 0x0067, 0x0068,
2409 0x0069, 0x006a, 0x006b, 0x006c
2410 };
2411 int i;
2412
4da19633 2413 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2414
2415 val &= 0xff00;
2416 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2417 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2418 }
2419 } else {
350f7596 2420 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2421 { 0x1f, 0x0002 },
2422 { 0x05, 0x2642 },
5b538df9 2423 { 0x1f, 0x0005 },
daf9df6d 2424 { 0x05, 0x8330 },
2425 { 0x06, 0x2642 }
5b538df9
FR		 2426 };
2427
4da19633 2428 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2429 }
2430
bca03d5f 2431 /* Fine tune PLL performance */
4da19633 2432 rtl_writephy(tp, 0x1f, 0x0002);
2433 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2434 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2435
bca03d5f 2436 /* Switching regulator Slew rate */
4da19633 2437 rtl_writephy(tp, 0x1f, 0x0002);
2438 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2439
4da19633 2440 rtl_writephy(tp, 0x1f, 0x0005);
2441 rtl_writephy(tp, 0x05, 0x001b);
953a12cc
FR		 2442
2443 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
bca03d5f 2444
4da19633 2445 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2446}
2447
4da19633 2448static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2449{
350f7596 2450 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2451 { 0x1f, 0x0002 },
2452 { 0x10, 0x0008 },
2453 { 0x0d, 0x006c },
2454
2455 { 0x1f, 0x0000 },
2456 { 0x0d, 0xf880 },
2457
2458 { 0x1f, 0x0001 },
2459 { 0x17, 0x0cc0 },
2460
2461 { 0x1f, 0x0001 },
2462 { 0x0b, 0xa4d8 },
2463 { 0x09, 0x281c },
2464 { 0x07, 0x2883 },
2465 { 0x0a, 0x6b35 },
2466 { 0x1d, 0x3da4 },
2467 { 0x1c, 0xeffd },
2468 { 0x14, 0x7f52 },
2469 { 0x18, 0x7fc6 },
2470 { 0x08, 0x0601 },
2471 { 0x06, 0x4063 },
2472 { 0x10, 0xf074 },
2473 { 0x1f, 0x0003 },
2474 { 0x13, 0x0789 },
2475 { 0x12, 0xf4bd },
2476 { 0x1a, 0x04fd },
2477 { 0x14, 0x84b0 },
2478 { 0x1f, 0x0000 },
2479 { 0x00, 0x9200 },
2480
2481 { 0x1f, 0x0005 },
2482 { 0x01, 0x0340 },
2483 { 0x1f, 0x0001 },
2484 { 0x04, 0x4000 },
2485 { 0x03, 0x1d21 },
2486 { 0x02, 0x0c32 },
2487 { 0x01, 0x0200 },
2488 { 0x00, 0x5554 },
2489 { 0x04, 0x4800 },
2490 { 0x04, 0x4000 },
2491 { 0x04, 0xf000 },
2492 { 0x03, 0xdf01 },
2493 { 0x02, 0xdf20 },
2494 { 0x01, 0x101a },
2495 { 0x00, 0xa0ff },
2496 { 0x04, 0xf800 },
2497 { 0x04, 0xf000 },
2498 { 0x1f, 0x0000 },
2499
2500 { 0x1f, 0x0007 },
2501 { 0x1e, 0x0023 },
2502 { 0x16, 0x0000 },
2503 { 0x1f, 0x0000 }
2504 };
2505
4da19633 2506 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2507}
2508
e6de30d6 2509static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2510{
2511 static const struct phy_reg phy_reg_init[] = {
2512 { 0x1f, 0x0001 },
2513 { 0x17, 0x0cc0 },
2514
2515 { 0x1f, 0x0007 },
2516 { 0x1e, 0x002d },
2517 { 0x18, 0x0040 },
2518 { 0x1f, 0x0000 }
2519 };
2520
2521 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2522 rtl_patchphy(tp, 0x0d, 1 << 5);
2523}
2524
01dc7fec 2525static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2526{
2527 static const struct phy_reg phy_reg_init[] = {
2528 /* Enable Delay cap */
2529 { 0x1f, 0x0005 },
2530 { 0x05, 0x8b80 },
2531 { 0x06, 0xc896 },
2532 { 0x1f, 0x0000 },
2533
2534 /* Channel estimation fine tune */
2535 { 0x1f, 0x0001 },
2536 { 0x0b, 0x6c20 },
2537 { 0x07, 0x2872 },
2538 { 0x1c, 0xefff },
2539 { 0x1f, 0x0003 },
2540 { 0x14, 0x6420 },
2541 { 0x1f, 0x0000 },
2542
2543 /* Update PFM & 10M TX idle timer */
2544 { 0x1f, 0x0007 },
2545 { 0x1e, 0x002f },
2546 { 0x15, 0x1919 },
2547 { 0x1f, 0x0000 },
2548
2549 { 0x1f, 0x0007 },
2550 { 0x1e, 0x00ac },
2551 { 0x18, 0x0006 },
2552 { 0x1f, 0x0000 }
2553 };
2554
15ecd039
FR		 2555 rtl_apply_firmware(tp);
2556
01dc7fec 2557 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2558
2559 /* DCO enable for 10M IDLE Power */
2560 rtl_writephy(tp, 0x1f, 0x0007);
2561 rtl_writephy(tp, 0x1e, 0x0023);
2562 rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2563 rtl_writephy(tp, 0x1f, 0x0000);
2564
2565 /* For impedance matching */
2566 rtl_writephy(tp, 0x1f, 0x0002);
2567 rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
cecb5fd7 2568 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 2569
2570 /* PHY auto speed down */
2571 rtl_writephy(tp, 0x1f, 0x0007);
2572 rtl_writephy(tp, 0x1e, 0x002d);
2573 rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2574 rtl_writephy(tp, 0x1f, 0x0000);
2575 rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2576
2577 rtl_writephy(tp, 0x1f, 0x0005);
2578 rtl_writephy(tp, 0x05, 0x8b86);
2579 rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2580 rtl_writephy(tp, 0x1f, 0x0000);
2581
2582 rtl_writephy(tp, 0x1f, 0x0005);
2583 rtl_writephy(tp, 0x05, 0x8b85);
2584 rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2585 rtl_writephy(tp, 0x1f, 0x0007);
2586 rtl_writephy(tp, 0x1e, 0x0020);
2587 rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2588 rtl_writephy(tp, 0x1f, 0x0006);
2589 rtl_writephy(tp, 0x00, 0x5a00);
2590 rtl_writephy(tp, 0x1f, 0x0000);
2591 rtl_writephy(tp, 0x0d, 0x0007);
2592 rtl_writephy(tp, 0x0e, 0x003c);
2593 rtl_writephy(tp, 0x0d, 0x4007);
2594 rtl_writephy(tp, 0x0e, 0x0000);
2595 rtl_writephy(tp, 0x0d, 0x0000);
2596}
2597
4da19633 2598static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2599{
350f7596 2600 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2601 { 0x1f, 0x0003 },
2602 { 0x08, 0x441d },
2603 { 0x01, 0x9100 },
2604 { 0x1f, 0x0000 }
2605 };
2606
4da19633 2607 rtl_writephy(tp, 0x1f, 0x0000);
2608 rtl_patchphy(tp, 0x11, 1 << 12);
2609 rtl_patchphy(tp, 0x19, 1 << 13);
2610 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2611
4da19633 2612 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2613}
2614
5a5e4443
HW		 2615static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2616{
2617 static const struct phy_reg phy_reg_init[] = {
2618 { 0x1f, 0x0005 },
2619 { 0x1a, 0x0000 },
2620 { 0x1f, 0x0000 },
2621
2622 { 0x1f, 0x0004 },
2623 { 0x1c, 0x0000 },
2624 { 0x1f, 0x0000 },
2625
2626 { 0x1f, 0x0001 },
2627 { 0x15, 0x7701 },
2628 { 0x1f, 0x0000 }
2629 };
2630
2631 /* Disable ALDPS before ram code */
2632 rtl_writephy(tp, 0x1f, 0x0000);
2633 rtl_writephy(tp, 0x18, 0x0310);
2634 msleep(100);
2635
953a12cc 2636 rtl_apply_firmware(tp);
5a5e4443
HW		 2637
2638 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2639}
2640
5615d9f1
FR		 2641static void rtl_hw_phy_config(struct net_device *dev)
2642{
2643 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2644
2645 rtl8169_print_mac_version(tp);
2646
2647 switch (tp->mac_version) {
2648 case RTL_GIGA_MAC_VER_01:
2649 break;
2650 case RTL_GIGA_MAC_VER_02:
2651 case RTL_GIGA_MAC_VER_03:
4da19633 2652 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2653 break;
2654 case RTL_GIGA_MAC_VER_04:
4da19633 2655 rtl8169sb_hw_phy_config(tp);
5615d9f1 2656 break;
2e955856 2657 case RTL_GIGA_MAC_VER_05:
4da19633 2658 rtl8169scd_hw_phy_config(tp);
2e955856 2659 break;
8c7006aa 2660 case RTL_GIGA_MAC_VER_06:
4da19633 2661 rtl8169sce_hw_phy_config(tp);
8c7006aa 2662 break;
2857ffb7
FR		 2663 case RTL_GIGA_MAC_VER_07:
2664 case RTL_GIGA_MAC_VER_08:
2665 case RTL_GIGA_MAC_VER_09:
4da19633 2666 rtl8102e_hw_phy_config(tp);
2857ffb7 2667 break;
236b8082 2668 case RTL_GIGA_MAC_VER_11:
4da19633 2669 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2670 break;
2671 case RTL_GIGA_MAC_VER_12:
4da19633 2672 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2673 break;
2674 case RTL_GIGA_MAC_VER_17:
4da19633 2675 rtl8168bef_hw_phy_config(tp);
236b8082 2676 break;
867763c1 2677 case RTL_GIGA_MAC_VER_18:
4da19633 2678 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2679 break;
2680 case RTL_GIGA_MAC_VER_19:
4da19633 2681 rtl8168c_1_hw_phy_config(tp);
867763c1 2682 break;
7da97ec9 2683 case RTL_GIGA_MAC_VER_20:
4da19633 2684 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2685 break;
197ff761 2686 case RTL_GIGA_MAC_VER_21:
4da19633 2687 rtl8168c_3_hw_phy_config(tp);
197ff761 2688 break;
6fb07058 2689 case RTL_GIGA_MAC_VER_22:
4da19633 2690 rtl8168c_4_hw_phy_config(tp);
6fb07058 2691 break;
ef3386f0 2692 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2693 case RTL_GIGA_MAC_VER_24:
4da19633 2694 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2695 break;
5b538df9 2696 case RTL_GIGA_MAC_VER_25:
bca03d5f 2697 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2698 break;
2699 case RTL_GIGA_MAC_VER_26:
bca03d5f 2700 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2701 break;
2702 case RTL_GIGA_MAC_VER_27:
4da19633 2703 rtl8168d_3_hw_phy_config(tp);
5b538df9 2704 break;
e6de30d6 2705 case RTL_GIGA_MAC_VER_28:
2706 rtl8168d_4_hw_phy_config(tp);
2707 break;
5a5e4443
HW		 2708 case RTL_GIGA_MAC_VER_29:
2709 case RTL_GIGA_MAC_VER_30:
2710 rtl8105e_hw_phy_config(tp);
2711 break;
cecb5fd7
FR		 2712 case RTL_GIGA_MAC_VER_31:
2713 /* None. */
2714 break;
01dc7fec 2715 case RTL_GIGA_MAC_VER_32:
01dc7fec 2716 case RTL_GIGA_MAC_VER_33:
15ecd039 2717 rtl8168e_hw_phy_config(tp);
01dc7fec 2718 break;
ef3386f0 2719
5615d9f1
FR		 2720 default:
2721 break;
2722 }
2723}
2724
1da177e4
LT		 2725static void rtl8169_phy_timer(unsigned long __opaque)
2726{
2727 struct net_device *dev = (struct net_device *)__opaque;
2728 struct rtl8169_private *tp = netdev_priv(dev);
2729 struct timer_list *timer = &tp->timer;
2730 void __iomem *ioaddr = tp->mmio_addr;
2731 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2732
bcf0bf90 2733 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2734
1da177e4
LT		 2735 spin_lock_irq(&tp->lock);
2736
4da19633 2737 if (tp->phy_reset_pending(tp)) {
5b0384f4 2738 /*
1da177e4
LT		 2739 * A busy loop could burn quite a few cycles on nowadays CPU.
2740 * Let's delay the execution of the timer for a few ticks.
2741 */
2742 timeout = HZ/10;
2743 goto out_mod_timer;
2744 }
2745
2746 if (tp->link_ok(ioaddr))
2747 goto out_unlock;
2748
bf82c189 2749 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2750
4da19633 2751 tp->phy_reset_enable(tp);
1da177e4
LT		 2752
2753out_mod_timer:
2754 mod_timer(timer, jiffies + timeout);
2755out_unlock:
2756 spin_unlock_irq(&tp->lock);
2757}
2758
1da177e4
LT		 2759#ifdef CONFIG_NET_POLL_CONTROLLER
2760/*
2761 * Polling 'interrupt' - used by things like netconsole to send skbs
2762 * without having to re-enable interrupts. It's not called while
2763 * the interrupt routine is executing.
2764 */
2765static void rtl8169_netpoll(struct net_device *dev)
2766{
2767 struct rtl8169_private *tp = netdev_priv(dev);
2768 struct pci_dev *pdev = tp->pci_dev;
2769
2770 disable_irq(pdev->irq);
7d12e780 2771 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2772 enable_irq(pdev->irq);
2773}
2774#endif
2775
2776static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2777 void __iomem *ioaddr)
2778{
2779 iounmap(ioaddr);
2780 pci_release_regions(pdev);
87aeec76 2781 pci_clear_mwi(pdev);
1da177e4
LT		 2782 pci_disable_device(pdev);
2783 free_netdev(dev);
2784}
2785
bf793295
FR		 2786static void rtl8169_phy_reset(struct net_device *dev,
2787 struct rtl8169_private *tp)
2788{
07d3f51f 2789 unsigned int i;
bf793295 2790
4da19633 2791 tp->phy_reset_enable(tp);
bf793295 2792 for (i = 0; i < 100; i++) {
4da19633 2793 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2794 return;
2795 msleep(1);
2796 }
bf82c189 2797 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2798}
2799
4ff96fa6
FR		 2800static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2801{
2802 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2803
5615d9f1 2804 rtl_hw_phy_config(dev);
4ff96fa6 2805
77332894
MS		 2806 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2807 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2808 RTL_W8(0x82, 0x01);
2809 }
4ff96fa6 2810
6dccd16b
FR		 2811 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2812
2813 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2814 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2815
bcf0bf90 2816 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2817 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2818 RTL_W8(0x82, 0x01);
2819 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2820 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2821 }
2822
bf793295
FR		 2823 rtl8169_phy_reset(dev, tp);
2824
54405cde 2825 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
cecb5fd7
FR		 2826 ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2827 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2828 (tp->mii.supports_gmii ?
2829 ADVERTISED_1000baseT_Half |
2830 ADVERTISED_1000baseT_Full : 0));
4ff96fa6 2831
bf82c189
JP		 2832 if (RTL_R8(PHYstatus) & TBI_Enable)
2833 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2834}
2835
773d2021
FR		 2836static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2837{
2838 void __iomem *ioaddr = tp->mmio_addr;
2839 u32 high;
2840 u32 low;
2841
2842 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2843 high = addr[4] | (addr[5] << 8);
2844
2845 spin_lock_irq(&tp->lock);
2846
2847 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2848
773d2021 2849 RTL_W32(MAC4, high);
908ba2bf 2850 RTL_R32(MAC4);
2851
78f1cd02 2852 RTL_W32(MAC0, low);
908ba2bf 2853 RTL_R32(MAC0);
2854
773d2021
FR		 2855 RTL_W8(Cfg9346, Cfg9346_Lock);
2856
2857 spin_unlock_irq(&tp->lock);
2858}
2859
2860static int rtl_set_mac_address(struct net_device *dev, void *p)
2861{
2862 struct rtl8169_private *tp = netdev_priv(dev);
2863 struct sockaddr *addr = p;
2864
2865 if (!is_valid_ether_addr(addr->sa_data))
2866 return -EADDRNOTAVAIL;
2867
2868 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2869
2870 rtl_rar_set(tp, dev->dev_addr);
2871
2872 return 0;
2873}
2874
5f787a1a
FR		 2875static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2876{
2877 struct rtl8169_private *tp = netdev_priv(dev);
2878 struct mii_ioctl_data *data = if_mii(ifr);
2879
8b4ab28d
FR		 2880 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2881}
5f787a1a 2882
cecb5fd7
FR		 2883static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2884 struct mii_ioctl_data *data, int cmd)
8b4ab28d 2885{
5f787a1a
FR		 2886 switch (cmd) {
2887 case SIOCGMIIPHY:
2888 data->phy_id = 32; /* Internal PHY */
2889 return 0;
2890
2891 case SIOCGMIIREG:
4da19633 2892 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2893 return 0;
2894
2895 case SIOCSMIIREG:
4da19633 2896 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2897 return 0;
2898 }
2899 return -EOPNOTSUPP;
2900}
2901
8b4ab28d
FR		 2902static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2903{
2904 return -EOPNOTSUPP;
2905}
2906
0e485150
FR		 2907static const struct rtl_cfg_info {
2908 void (*hw_start)(struct net_device *);
2909 unsigned int region;
2910 unsigned int align;
2911 u16 intr_event;
2912 u16 napi_event;
ccdffb9a 2913 unsigned features;
f21b75e9 2914 u8 default_ver;
0e485150
FR		 2915} rtl_cfg_infos [] = {
2916 [RTL_CFG_0] = {
2917 .hw_start = rtl_hw_start_8169,
2918 .region = 1,
e9f63f30 2919 .align = 0,
0e485150
FR		 2920 .intr_event = SYSErr | LinkChg | RxOverflow |
2921 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2922 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2923 .features = RTL_FEATURE_GMII,
2924 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2925 },
2926 [RTL_CFG_1] = {
2927 .hw_start = rtl_hw_start_8168,
2928 .region = 2,
2929 .align = 8,
53f57357 2930 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2931 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2932 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2933 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2934 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2935 },
2936 [RTL_CFG_2] = {
2937 .hw_start = rtl_hw_start_8101,
2938 .region = 2,
2939 .align = 8,
2940 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2941 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2942 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2943 .features = RTL_FEATURE_MSI,
2944 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2945 }
2946};
2947
fbac58fc
FR		 2948/* Cfg9346_Unlock assumed. */
2949static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2950 const struct rtl_cfg_info *cfg)
2951{
2952 unsigned msi = 0;
2953 u8 cfg2;
2954
2955 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2956 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2957 if (pci_enable_msi(pdev)) {
2958 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2959 } else {
2960 cfg2 |= MSIEnable;
2961 msi = RTL_FEATURE_MSI;
2962 }
2963 }
2964 RTL_W8(Config2, cfg2);
2965 return msi;
2966}
2967
2968static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2969{
2970 if (tp->features & RTL_FEATURE_MSI) {
2971 pci_disable_msi(pdev);
2972 tp->features &= ~RTL_FEATURE_MSI;
2973 }
2974}
2975
8b4ab28d
FR		 2976static const struct net_device_ops rtl8169_netdev_ops = {
2977 .ndo_open = rtl8169_open,
2978 .ndo_stop = rtl8169_close,
2979 .ndo_get_stats = rtl8169_get_stats,
00829823 2980 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2981 .ndo_tx_timeout = rtl8169_tx_timeout,
2982 .ndo_validate_addr = eth_validate_addr,
2983 .ndo_change_mtu = rtl8169_change_mtu,
350fb32a
MM		 2984 .ndo_fix_features = rtl8169_fix_features,
2985 .ndo_set_features = rtl8169_set_features,
8b4ab28d
FR		 2986 .ndo_set_mac_address = rtl_set_mac_address,
2987 .ndo_do_ioctl = rtl8169_ioctl,
2988 .ndo_set_multicast_list = rtl_set_rx_mode,
8b4ab28d
FR		 2989#ifdef CONFIG_NET_POLL_CONTROLLER
2990 .ndo_poll_controller = rtl8169_netpoll,
2991#endif
2992
2993};
2994
c0e45c1c 2995static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2996{
2997 struct mdio_ops *ops = &tp->mdio_ops;
2998
2999 switch (tp->mac_version) {
3000 case RTL_GIGA_MAC_VER_27:
3001 ops->write = r8168dp_1_mdio_write;
3002 ops->read = r8168dp_1_mdio_read;
3003 break;
e6de30d6 3004 case RTL_GIGA_MAC_VER_28:
4804b3b3 3005 case RTL_GIGA_MAC_VER_31:
e6de30d6 3006 ops->write = r8168dp_2_mdio_write;
3007 ops->read = r8168dp_2_mdio_read;
3008 break;
c0e45c1c 3009 default:
3010 ops->write = r8169_mdio_write;
3011 ops->read = r8169_mdio_read;
3012 break;
3013 }
3014}
3015
065c27c1 3016static void r810x_phy_power_down(struct rtl8169_private *tp)
3017{
3018 rtl_writephy(tp, 0x1f, 0x0000);
3019 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3020}
3021
3022static void r810x_phy_power_up(struct rtl8169_private *tp)
3023{
3024 rtl_writephy(tp, 0x1f, 0x0000);
3025 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3026}
3027
3028static void r810x_pll_power_down(struct rtl8169_private *tp)
3029{
3030 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3031 rtl_writephy(tp, 0x1f, 0x0000);
3032 rtl_writephy(tp, MII_BMCR, 0x0000);
3033 return;
3034 }
3035
3036 r810x_phy_power_down(tp);
3037}
3038
3039static void r810x_pll_power_up(struct rtl8169_private *tp)
3040{
3041 r810x_phy_power_up(tp);
3042}
3043
3044static void r8168_phy_power_up(struct rtl8169_private *tp)
3045{
3046 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3047 switch (tp->mac_version) {
3048 case RTL_GIGA_MAC_VER_11:
3049 case RTL_GIGA_MAC_VER_12:
3050 case RTL_GIGA_MAC_VER_17:
3051 case RTL_GIGA_MAC_VER_18:
3052 case RTL_GIGA_MAC_VER_19:
3053 case RTL_GIGA_MAC_VER_20:
3054 case RTL_GIGA_MAC_VER_21:
3055 case RTL_GIGA_MAC_VER_22:
3056 case RTL_GIGA_MAC_VER_23:
3057 case RTL_GIGA_MAC_VER_24:
3058 case RTL_GIGA_MAC_VER_25:
3059 case RTL_GIGA_MAC_VER_26:
3060 case RTL_GIGA_MAC_VER_27:
3061 case RTL_GIGA_MAC_VER_28:
3062 case RTL_GIGA_MAC_VER_31:
3063 rtl_writephy(tp, 0x0e, 0x0000);
3064 break;
3065 default:
3066 break;
3067 }
065c27c1 3068 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3069}
3070
3071static void r8168_phy_power_down(struct rtl8169_private *tp)
3072{
3073 rtl_writephy(tp, 0x1f, 0x0000);
01dc7fec 3074 switch (tp->mac_version) {
3075 case RTL_GIGA_MAC_VER_32:
3076 case RTL_GIGA_MAC_VER_33:
3077 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3078 break;
3079
3080 case RTL_GIGA_MAC_VER_11:
3081 case RTL_GIGA_MAC_VER_12:
3082 case RTL_GIGA_MAC_VER_17:
3083 case RTL_GIGA_MAC_VER_18:
3084 case RTL_GIGA_MAC_VER_19:
3085 case RTL_GIGA_MAC_VER_20:
3086 case RTL_GIGA_MAC_VER_21:
3087 case RTL_GIGA_MAC_VER_22:
3088 case RTL_GIGA_MAC_VER_23:
3089 case RTL_GIGA_MAC_VER_24:
3090 case RTL_GIGA_MAC_VER_25:
3091 case RTL_GIGA_MAC_VER_26:
3092 case RTL_GIGA_MAC_VER_27:
3093 case RTL_GIGA_MAC_VER_28:
3094 case RTL_GIGA_MAC_VER_31:
3095 rtl_writephy(tp, 0x0e, 0x0200);
3096 default:
3097 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3098 break;
3099 }
065c27c1 3100}
3101
3102static void r8168_pll_power_down(struct rtl8169_private *tp)
3103{
3104 void __iomem *ioaddr = tp->mmio_addr;
3105
cecb5fd7
FR		 3106 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3107 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3108 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3109 r8168dp_check_dash(tp)) {
065c27c1 3110 return;
5d2e1957 3111 }
065c27c1 3112
cecb5fd7
FR		 3113 if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3114 tp->mac_version == RTL_GIGA_MAC_VER_24) &&
065c27c1 3115 (RTL_R16(CPlusCmd) & ASF)) {
3116 return;
3117 }
3118
01dc7fec 3119 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3120 tp->mac_version == RTL_GIGA_MAC_VER_33)
3121 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3122
065c27c1 3123 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3124 rtl_writephy(tp, 0x1f, 0x0000);
3125 rtl_writephy(tp, MII_BMCR, 0x0000);
3126
3127 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3128 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3129 return;
3130 }
3131
3132 r8168_phy_power_down(tp);
3133
3134 switch (tp->mac_version) {
3135 case RTL_GIGA_MAC_VER_25:
3136 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3137 case RTL_GIGA_MAC_VER_27:
3138 case RTL_GIGA_MAC_VER_28:
4804b3b3 3139 case RTL_GIGA_MAC_VER_31:
01dc7fec 3140 case RTL_GIGA_MAC_VER_32:
3141 case RTL_GIGA_MAC_VER_33:
065c27c1 3142 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3143 break;
3144 }
3145}
3146
3147static void r8168_pll_power_up(struct rtl8169_private *tp)
3148{
3149 void __iomem *ioaddr = tp->mmio_addr;
3150
cecb5fd7
FR		 3151 if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3152 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3153 tp->mac_version == RTL_GIGA_MAC_VER_31) &&
4804b3b3 3154 r8168dp_check_dash(tp)) {
065c27c1 3155 return;
5d2e1957 3156 }
065c27c1 3157
3158 switch (tp->mac_version) {
3159 case RTL_GIGA_MAC_VER_25:
3160 case RTL_GIGA_MAC_VER_26:
5d2e1957
HW		 3161 case RTL_GIGA_MAC_VER_27:
3162 case RTL_GIGA_MAC_VER_28:
4804b3b3 3163 case RTL_GIGA_MAC_VER_31:
01dc7fec 3164 case RTL_GIGA_MAC_VER_32:
3165 case RTL_GIGA_MAC_VER_33:
065c27c1 3166 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3167 break;
3168 }
3169
3170 r8168_phy_power_up(tp);
3171}
3172
3173static void rtl_pll_power_op(struct rtl8169_private *tp,
3174 void (*op)(struct rtl8169_private *))
3175{
3176 if (op)
3177 op(tp);
3178}
3179
3180static void rtl_pll_power_down(struct rtl8169_private *tp)
3181{
3182 rtl_pll_power_op(tp, tp->pll_power_ops.down);
3183}
3184
3185static void rtl_pll_power_up(struct rtl8169_private *tp)
3186{
3187 rtl_pll_power_op(tp, tp->pll_power_ops.up);
3188}
3189
3190static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3191{
3192 struct pll_power_ops *ops = &tp->pll_power_ops;
3193
3194 switch (tp->mac_version) {
3195 case RTL_GIGA_MAC_VER_07:
3196 case RTL_GIGA_MAC_VER_08:
3197 case RTL_GIGA_MAC_VER_09:
3198 case RTL_GIGA_MAC_VER_10:
3199 case RTL_GIGA_MAC_VER_16:
5a5e4443
HW		 3200 case RTL_GIGA_MAC_VER_29:
3201 case RTL_GIGA_MAC_VER_30:
065c27c1 3202 ops->down = r810x_pll_power_down;
3203 ops->up = r810x_pll_power_up;
3204 break;
3205
3206 case RTL_GIGA_MAC_VER_11:
3207 case RTL_GIGA_MAC_VER_12:
3208 case RTL_GIGA_MAC_VER_17:
3209 case RTL_GIGA_MAC_VER_18:
3210 case RTL_GIGA_MAC_VER_19:
3211 case RTL_GIGA_MAC_VER_20:
3212 case RTL_GIGA_MAC_VER_21:
3213 case RTL_GIGA_MAC_VER_22:
3214 case RTL_GIGA_MAC_VER_23:
3215 case RTL_GIGA_MAC_VER_24:
3216 case RTL_GIGA_MAC_VER_25:
3217 case RTL_GIGA_MAC_VER_26:
3218 case RTL_GIGA_MAC_VER_27:
e6de30d6 3219 case RTL_GIGA_MAC_VER_28:
4804b3b3 3220 case RTL_GIGA_MAC_VER_31:
01dc7fec 3221 case RTL_GIGA_MAC_VER_32:
3222 case RTL_GIGA_MAC_VER_33:
065c27c1 3223 ops->down = r8168_pll_power_down;
3224 ops->up = r8168_pll_power_up;
3225 break;
3226
3227 default:
3228 ops->down = NULL;
3229 ops->up = NULL;
3230 break;
3231 }
3232}
3233
6f43adc8
FR		 3234static void rtl_hw_reset(struct rtl8169_private *tp)
3235{
3236 void __iomem *ioaddr = tp->mmio_addr;
3237 int i;
3238
3239 /* Soft reset the chip. */
3240 RTL_W8(ChipCmd, CmdReset);
3241
3242 /* Check that the chip has finished the reset. */
3243 for (i = 0; i < 100; i++) {
3244 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3245 break;
3246 msleep_interruptible(1);
3247 }
3248}
3249
1da177e4 3250static int __devinit
4ff96fa6 3251rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 3252{
0e485150
FR		 3253 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3254 const unsigned int region = cfg->region;
1da177e4 3255 struct rtl8169_private *tp;
ccdffb9a 3256 struct mii_if_info *mii;
4ff96fa6
FR		 3257 struct net_device *dev;
3258 void __iomem *ioaddr;
2b7b4318 3259 int chipset, i;
07d3f51f 3260 int rc;
1da177e4 3261
4ff96fa6
FR		 3262 if (netif_msg_drv(&debug)) {
3263 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3264 MODULENAME, RTL8169_VERSION);
3265 }
1da177e4 3266
1da177e4 3267 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 3268 if (!dev) {
b57b7e5a 3269 if (netif_msg_drv(&debug))
9b91cf9d 3270 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 3271 rc = -ENOMEM;
3272 goto out;
1da177e4
LT		 3273 }
3274
1da177e4 3275 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 3276 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3277 tp = netdev_priv(dev);
c4028958 3278 tp->dev = dev;
21e197f2 3279 tp->pci_dev = pdev;
b57b7e5a 3280 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3281
ccdffb9a
FR		 3282 mii = &tp->mii;
3283 mii->dev = dev;
3284 mii->mdio_read = rtl_mdio_read;
3285 mii->mdio_write = rtl_mdio_write;
3286 mii->phy_id_mask = 0x1f;
3287 mii->reg_num_mask = 0x1f;
3288 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3289
ba04c7c9
SG		 3290 /* disable ASPM completely as that cause random device stop working
3291 * problems as well as full system hangs for some PCIe devices users */
3292 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3293 PCIE_LINK_STATE_CLKPM);
3294
1da177e4
LT		 3295 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3296 rc = pci_enable_device(pdev);
b57b7e5a 3297 if (rc < 0) {
bf82c189 3298 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3299 goto err_out_free_dev_1;
1da177e4
LT		 3300 }
3301
87aeec76 3302 if (pci_set_mwi(pdev) < 0)
3303 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3304
1da177e4 3305 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3306 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3307 netif_err(tp, probe, dev,
3308 "region #%d not an MMIO resource, aborting\n",
3309 region);
1da177e4 3310 rc = -ENODEV;
87aeec76 3311 goto err_out_mwi_2;
1da177e4 3312 }
4ff96fa6 3313
1da177e4 3314 /* check for weird/broken PCI region reporting */
bcf0bf90 3315 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3316 netif_err(tp, probe, dev,
3317 "Invalid PCI region size(s), aborting\n");
1da177e4 3318 rc = -ENODEV;
87aeec76 3319 goto err_out_mwi_2;
1da177e4
LT		 3320 }
3321
3322 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3323 if (rc < 0) {
bf82c189 3324 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3325 goto err_out_mwi_2;
1da177e4
LT		 3326 }
3327
d24e9aaf 3328 tp->cp_cmd = RxChkSum;
1da177e4
LT		 3329
3330 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3331 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3332 tp->cp_cmd |= PCIDAC;
3333 dev->features |= NETIF_F_HIGHDMA;
3334 } else {
284901a9 3335 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3336 if (rc < 0) {
bf82c189 3337 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3338 goto err_out_free_res_3;
1da177e4
LT		 3339 }
3340 }
3341
1da177e4 3342 /* ioremap MMIO region */
bcf0bf90 3343 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3344 if (!ioaddr) {
bf82c189 3345 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3346 rc = -EIO;
87aeec76 3347 goto err_out_free_res_3;
1da177e4 3348 }
6f43adc8 3349 tp->mmio_addr = ioaddr;
1da177e4 3350
4300e8c7
DM		 3351 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3352 if (!tp->pcie_cap)
3353 netif_info(tp, probe, dev, "no PCI Express capability\n");
3354
d78ad8cb 3355 RTL_W16(IntrMask, 0x0000);
1da177e4 3356
6f43adc8 3357 rtl_hw_reset(tp);
1da177e4 3358
d78ad8cb
KW		 3359 RTL_W16(IntrStatus, 0xffff);
3360
ca52efd5 3361 pci_set_master(pdev);
3362
1da177e4 3363 /* Identify chip attached to board */
5d320a20 3364 rtl8169_get_mac_version(tp, dev, cfg->default_ver);
1da177e4 3365
7a8fc77b
FR		 3366 /*
3367 * Pretend we are using VLANs; This bypasses a nasty bug where
3368 * Interrupts stop flowing on high load on 8110SCd controllers.
3369 */
3370 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3371 tp->cp_cmd |= RxVlan;
3372
c0e45c1c 3373 rtl_init_mdio_ops(tp);
065c27c1 3374 rtl_init_pll_power_ops(tp);
c0e45c1c 3375
1da177e4 3376 rtl8169_print_mac_version(tp);
1da177e4 3377
85bffe6c
FR		 3378 chipset = tp->mac_version;
3379 tp->txd_version = rtl_chip_infos[chipset].txd_version;
1da177e4 3380
5d06a99f
FR		 3381 RTL_W8(Cfg9346, Cfg9346_Unlock);
3382 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3383 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3384 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3385 tp->features |= RTL_FEATURE_WOL;
3386 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3387 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3388 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3389 RTL_W8(Cfg9346, Cfg9346_Lock);
3390
66ec5d4f
FR		 3391 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3392 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3393 tp->set_speed = rtl8169_set_speed_tbi;
3394 tp->get_settings = rtl8169_gset_tbi;
3395 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3396 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3397 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3398 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4
LT		 3399 } else {
3400 tp->set_speed = rtl8169_set_speed_xmii;
3401 tp->get_settings = rtl8169_gset_xmii;
3402 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3403 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3404 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3405 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3406 }
3407
df58ef51
FR		 3408 spin_lock_init(&tp->lock);
3409
7bf6bf48 3410 /* Get MAC address */
1da177e4
LT		 3411 for (i = 0; i < MAC_ADDR_LEN; i++)
3412 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3413 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3414
1da177e4 3415 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3416 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3417 dev->irq = pdev->irq;
3418 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3419
bea3348e 3420 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4 3421
350fb32a
MM		 3422 /* don't enable SG, IP_CSUM and TSO by default - it might not work
3423 * properly for all devices */
3424 dev->features |= NETIF_F_RXCSUM |
3425 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3426
3427 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3428 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3429 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3430 NETIF_F_HIGHDMA;
3431
3432 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3433 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3434 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
1da177e4
LT		 3435
3436 tp->intr_mask = 0xffff;
0e485150
FR		 3437 tp->hw_start = cfg->hw_start;
3438 tp->intr_event = cfg->intr_event;
3439 tp->napi_event = cfg->napi_event;
1da177e4 3440
2efa53f3
FR		 3441 init_timer(&tp->timer);
3442 tp->timer.data = (unsigned long) dev;
3443 tp->timer.function = rtl8169_phy_timer;
3444
953a12cc
FR		 3445 tp->fw = RTL_FIRMWARE_UNKNOWN;
3446
1da177e4 3447 rc = register_netdev(dev);
4ff96fa6 3448 if (rc < 0)
87aeec76 3449 goto err_out_msi_4;
1da177e4
LT		 3450
3451 pci_set_drvdata(pdev, dev);
3452
bf82c189 3453 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
85bffe6c 3454 rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
bf82c189 3455 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3456
cecb5fd7
FR		 3457 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3458 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3459 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3460 rtl8168_driver_start(tp);
e6de30d6 3461 }
b646d900 3462
8b76ab39 3463 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3464
f3ec4f87
AS		 3465 if (pci_dev_run_wake(pdev))
3466 pm_runtime_put_noidle(&pdev->dev);
e1759441 3467
0d672e9f
IV		 3468 netif_carrier_off(dev);
3469
4ff96fa6
FR		 3470out:
3471 return rc;
1da177e4 3472
87aeec76 3473err_out_msi_4:
fbac58fc 3474 rtl_disable_msi(pdev, tp);
4ff96fa6 3475 iounmap(ioaddr);
87aeec76 3476err_out_free_res_3:
4ff96fa6 3477 pci_release_regions(pdev);
87aeec76 3478err_out_mwi_2:
4ff96fa6 3479 pci_clear_mwi(pdev);
4ff96fa6
FR		 3480 pci_disable_device(pdev);
3481err_out_free_dev_1:
3482 free_netdev(dev);
3483 goto out;
1da177e4
LT		 3484}
3485
07d3f51f 3486static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3487{
3488 struct net_device *dev = pci_get_drvdata(pdev);
3489 struct rtl8169_private *tp = netdev_priv(dev);
3490
cecb5fd7
FR		 3491 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3492 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3493 tp->mac_version == RTL_GIGA_MAC_VER_31) {
b646d900 3494 rtl8168_driver_stop(tp);
e6de30d6 3495 }
b646d900 3496
23f333a2 3497 cancel_delayed_work_sync(&tp->task);
eb2a021c 3498
1da177e4 3499 unregister_netdev(dev);
cc098dc7 3500
953a12cc
FR		 3501 rtl_release_firmware(tp);
3502
f3ec4f87
AS		 3503 if (pci_dev_run_wake(pdev))
3504 pm_runtime_get_noresume(&pdev->dev);
e1759441 3505
cc098dc7
IV		 3506 /* restore original MAC address */
3507 rtl_rar_set(tp, dev->perm_addr);
3508
fbac58fc 3509 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3510 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3511 pci_set_drvdata(pdev, NULL);
3512}
3513
953a12cc
FR		 3514static void rtl_request_firmware(struct rtl8169_private *tp)
3515{
953a12cc 3516 /* Return early if the firmware is already loaded / cached. */
31bd204f
FR		 3517 if (IS_ERR(tp->fw)) {
3518 const char *name;
953a12cc 3519
31bd204f
FR		 3520 name = rtl_lookup_firmware_name(tp);
3521 if (name) {
953a12cc
FR		 3522 int rc;
3523
3524 rc = request_firmware(&tp->fw, name, &tp->pci_dev->dev);
31bd204f
FR		 3525 if (rc >= 0)
3526 return;
3527
3528 netif_warn(tp, ifup, tp->dev, "unable to load "
3529 "firmware patch %s (%d)\n", name, rc);
953a12cc 3530 }
31bd204f 3531 tp->fw = NULL;
953a12cc 3532 }
953a12cc
FR		 3533}
3534
1da177e4
LT		 3535static int rtl8169_open(struct net_device *dev)
3536{
3537 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3538 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3539 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3540 int retval = -ENOMEM;
1da177e4 3541
e1759441 3542 pm_runtime_get_sync(&pdev->dev);
1da177e4 3543
1da177e4
LT		 3544 /*
3545 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3546 * dma_alloc_coherent provides more.
1da177e4 3547 */
82553bb6
SG		 3548 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3549 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3550 if (!tp->TxDescArray)
e1759441 3551 goto err_pm_runtime_put;
1da177e4 3552
82553bb6
SG		 3553 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3554 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3555 if (!tp->RxDescArray)
99f252b0 3556 goto err_free_tx_0;
1da177e4
LT		 3557
3558 retval = rtl8169_init_ring(dev);
3559 if (retval < 0)
99f252b0 3560 goto err_free_rx_1;
1da177e4 3561
c4028958 3562 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3563
99f252b0
FR		 3564 smp_mb();
3565
953a12cc
FR		 3566 rtl_request_firmware(tp);
3567
fbac58fc
FR		 3568 retval = request_irq(dev->irq, rtl8169_interrupt,
3569 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3570 dev->name, dev);
3571 if (retval < 0)
953a12cc 3572 goto err_release_fw_2;
99f252b0 3573
bea3348e 3574 napi_enable(&tp->napi);
bea3348e 3575
eee3a96c 3576 rtl8169_init_phy(dev, tp);
3577
350fb32a 3578 rtl8169_set_features(dev, dev->features);
eee3a96c 3579
065c27c1 3580 rtl_pll_power_up(tp);
3581
07ce4064 3582 rtl_hw_start(dev);
1da177e4 3583
e1759441
RW		 3584 tp->saved_wolopts = 0;
3585 pm_runtime_put_noidle(&pdev->dev);
3586
eee3a96c 3587 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3588out:
3589 return retval;
3590
953a12cc
FR		 3591err_release_fw_2:
3592 rtl_release_firmware(tp);
99f252b0
FR		 3593 rtl8169_rx_clear(tp);
3594err_free_rx_1:
82553bb6
SG		 3595 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3596 tp->RxPhyAddr);
e1759441 3597 tp->RxDescArray = NULL;
99f252b0 3598err_free_tx_0:
82553bb6
SG		 3599 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3600 tp->TxPhyAddr);
e1759441
RW		 3601 tp->TxDescArray = NULL;
3602err_pm_runtime_put:
3603 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3604 goto out;
3605}
3606
e6de30d6 3607static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3608{
e6de30d6 3609 void __iomem *ioaddr = tp->mmio_addr;
3610
1da177e4
LT		 3611 /* Disable interrupts */
3612 rtl8169_irq_mask_and_ack(ioaddr);
3613
5d2e1957 3614 if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
4804b3b3 3615 tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3616 tp->mac_version == RTL_GIGA_MAC_VER_31) {
e6de30d6 3617 while (RTL_R8(TxPoll) & NPQ)
3618 udelay(20);
3619
3620 }
3621
1da177e4
LT		 3622 /* Reset the chipset */
3623 RTL_W8(ChipCmd, CmdReset);
3624
3625 /* PCI commit */
3626 RTL_R8(ChipCmd);
3627}
3628
7f796d83 3629static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3630{
3631 void __iomem *ioaddr = tp->mmio_addr;
3632 u32 cfg = rtl8169_rx_config;
3633
2b7b4318 3634 cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
9cb427b6
FR		 3635 RTL_W32(RxConfig, cfg);
3636
3637 /* Set DMA burst size and Interframe Gap Time */
3638 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3639 (InterFrameGap << TxInterFrameGapShift));
3640}
3641
07ce4064 3642static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3643{
3644 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 3645
6f43adc8 3646 rtl_hw_reset(tp);
1da177e4 3647
07ce4064
FR		 3648 tp->hw_start(dev);
3649
07ce4064
FR		 3650 netif_start_queue(dev);
3651}
3652
7f796d83
FR		 3653static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3654 void __iomem *ioaddr)
3655{
3656 /*
3657 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3658 * register to be written before TxDescAddrLow to work.
3659 * Switching from MMIO to I/O access fixes the issue as well.
3660 */
3661 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3662 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3663 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3664 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3665}
3666
3667static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3668{
3669 u16 cmd;
3670
3671 cmd = RTL_R16(CPlusCmd);
3672 RTL_W16(CPlusCmd, cmd);
3673 return cmd;
3674}
3675
fdd7b4c3 3676static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3677{
3678 /* Low hurts. Let's disable the filtering. */
207d6e87 3679 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3680}
3681
6dccd16b
FR		 3682static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3683{
350f7596 3684 static const struct {
6dccd16b
FR		 3685 u32 mac_version;
3686 u32 clk;
3687 u32 val;
3688 } cfg2_info [] = {
3689 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3690 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3691 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3692 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3693 }, *p = cfg2_info;
3694 unsigned int i;
3695 u32 clk;
3696
3697 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3698 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3699 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3700 RTL_W32(0x7c, p->val);
3701 break;
3702 }
3703 }
3704}
3705
07ce4064
FR		 3706static void rtl_hw_start_8169(struct net_device *dev)
3707{
3708 struct rtl8169_private *tp = netdev_priv(dev);
3709 void __iomem *ioaddr = tp->mmio_addr;
3710 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3711
9cb427b6
FR		 3712 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3713 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3714 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3715 }
3716
1da177e4 3717 RTL_W8(Cfg9346, Cfg9346_Unlock);
cecb5fd7
FR		 3718 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3719 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3720 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3721 tp->mac_version == RTL_GIGA_MAC_VER_04)
9cb427b6
FR		 3722 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3723
f0298f81 3724 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3725
6f0333b8 3726 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3727
cecb5fd7
FR		 3728 if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3729 tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3730 tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3731 tp->mac_version == RTL_GIGA_MAC_VER_04)
c946b304 3732 rtl_set_rx_tx_config_registers(tp);
1da177e4 3733
7f796d83 3734 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3735
cecb5fd7
FR		 3736 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3737 tp->mac_version == RTL_GIGA_MAC_VER_03) {
06fa7358 3738 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3739 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3740 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3741 }
3742
bcf0bf90
FR		 3743 RTL_W16(CPlusCmd, tp->cp_cmd);
3744
6dccd16b
FR		 3745 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3746
1da177e4
LT		 3747 /*
3748 * Undocumented corner. Supposedly:
3749 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3750 */
3751 RTL_W16(IntrMitigate, 0x0000);
3752
7f796d83 3753 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3754
cecb5fd7
FR		 3755 if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3756 tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3757 tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3758 tp->mac_version != RTL_GIGA_MAC_VER_04) {
c946b304
FR		 3759 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3760 rtl_set_rx_tx_config_registers(tp);
3761 }
3762
1da177e4 3763 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3764
3765 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3766 RTL_R8(IntrMask);
1da177e4
LT		 3767
3768 RTL_W32(RxMissed, 0);
3769
07ce4064 3770 rtl_set_rx_mode(dev);
1da177e4
LT		 3771
3772 /* no early-rx interrupts */
3773 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3774
3775 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3776 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3777}
1da177e4 3778
9c14ceaf 3779static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3780{
9c14ceaf
FR		 3781 struct net_device *dev = pci_get_drvdata(pdev);
3782 struct rtl8169_private *tp = netdev_priv(dev);
3783 int cap = tp->pcie_cap;
3784
3785 if (cap) {
3786 u16 ctl;
458a9f61 3787
9c14ceaf
FR		 3788 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3789 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3790 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3791 }
458a9f61
FR		 3792}
3793
650e8d5d 3794static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3795{
3796 u32 csi;
3797
3798 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3799 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3800}
3801
e6de30d6 3802static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3803{
3804 rtl_csi_access_enable(ioaddr, 0x17000000);
3805}
3806
650e8d5d 3807static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3808{
3809 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3810}
3811
3812struct ephy_info {
3813 unsigned int offset;
3814 u16 mask;
3815 u16 bits;
3816};
3817
350f7596 3818static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3819{
3820 u16 w;
3821
3822 while (len-- > 0) {
3823 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3824 rtl_ephy_write(ioaddr, e->offset, w);
3825 e++;
3826 }
3827}
3828
b726e493
FR		 3829static void rtl_disable_clock_request(struct pci_dev *pdev)
3830{
3831 struct net_device *dev = pci_get_drvdata(pdev);
3832 struct rtl8169_private *tp = netdev_priv(dev);
3833 int cap = tp->pcie_cap;
3834
3835 if (cap) {
3836 u16 ctl;
3837
3838 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3839 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3840 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3841 }
3842}
3843
e6de30d6 3844static void rtl_enable_clock_request(struct pci_dev *pdev)
3845{
3846 struct net_device *dev = pci_get_drvdata(pdev);
3847 struct rtl8169_private *tp = netdev_priv(dev);
3848 int cap = tp->pcie_cap;
3849
3850 if (cap) {
3851 u16 ctl;
3852
3853 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3854 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3855 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3856 }
3857}
3858
b726e493
FR		 3859#define R8168_CPCMD_QUIRK_MASK (\
3860 EnableBist | \
3861 Mac_dbgo_oe | \
3862 Force_half_dup | \
3863 Force_rxflow_en | \
3864 Force_txflow_en | \
3865 Cxpl_dbg_sel | \
3866 ASF | \
3867 PktCntrDisable | \
3868 Mac_dbgo_sel)
3869
219a1e9d
FR		 3870static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3871{
b726e493
FR		 3872 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3873
3874 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3875
2e68ae44
FR		 3876 rtl_tx_performance_tweak(pdev,
3877 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3878}
3879
3880static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3881{
3882 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3883
f0298f81 3884 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3885
3886 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3887}
3888
3889static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3890{
b726e493
FR		 3891 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3892
3893 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3894
219a1e9d 3895 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3896
3897 rtl_disable_clock_request(pdev);
3898
3899 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3900}
3901
ef3386f0 3902static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3903{
350f7596 3904 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3905 { 0x01, 0, 0x0001 },
3906 { 0x02, 0x0800, 0x1000 },
3907 { 0x03, 0, 0x0042 },
3908 { 0x06, 0x0080, 0x0000 },
3909 { 0x07, 0, 0x2000 }
3910 };
3911
650e8d5d 3912 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3913
3914 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3915
219a1e9d
FR		 3916 __rtl_hw_start_8168cp(ioaddr, pdev);
3917}
3918
ef3386f0
FR		 3919static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3920{
650e8d5d 3921 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3922
3923 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3924
3925 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3926
3927 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3928}
3929
7f3e3d3a
FR		 3930static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3931{
650e8d5d 3932 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3933
3934 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3935
3936 /* Magic. */
3937 RTL_W8(DBG_REG, 0x20);
3938
f0298f81 3939 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3940
3941 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3942
3943 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3944}
3945
219a1e9d
FR		 3946static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3947{
350f7596 3948 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3949 { 0x02, 0x0800, 0x1000 },
3950 { 0x03, 0, 0x0002 },
3951 { 0x06, 0x0080, 0x0000 }
3952 };
3953
650e8d5d 3954 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3955
3956 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3957
3958 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3959
219a1e9d
FR		 3960 __rtl_hw_start_8168cp(ioaddr, pdev);
3961}
3962
3963static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3964{
350f7596 3965 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3966 { 0x01, 0, 0x0001 },
3967 { 0x03, 0x0400, 0x0220 }
3968 };
3969
650e8d5d 3970 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3971
3972 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3973
219a1e9d
FR		 3974 __rtl_hw_start_8168cp(ioaddr, pdev);
3975}
3976
197ff761
FR		 3977static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3978{
3979 rtl_hw_start_8168c_2(ioaddr, pdev);
3980}
3981
6fb07058
FR		 3982static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3983{
650e8d5d 3984 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 3985
3986 __rtl_hw_start_8168cp(ioaddr, pdev);
3987}
3988
5b538df9
FR		 3989static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3990{
650e8d5d 3991 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 3992
3993 rtl_disable_clock_request(pdev);
3994
f0298f81 3995 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 3996
3997 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3998
3999 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4000}
4001
4804b3b3 4002static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4003{
4004 rtl_csi_access_enable_1(ioaddr);
4005
4006 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4007
4008 RTL_W8(MaxTxPacketSize, TxPacketMax);
4009
4010 rtl_disable_clock_request(pdev);
4011}
4012
e6de30d6 4013static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4014{
4015 static const struct ephy_info e_info_8168d_4[] = {
4016 { 0x0b, ~0, 0x48 },
4017 { 0x19, 0x20, 0x50 },
4018 { 0x0c, ~0, 0x20 }
4019 };
4020 int i;
4021
4022 rtl_csi_access_enable_1(ioaddr);
4023
4024 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4025
4026 RTL_W8(MaxTxPacketSize, TxPacketMax);
4027
4028 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4029 const struct ephy_info *e = e_info_8168d_4 + i;
4030 u16 w;
4031
4032 w = rtl_ephy_read(ioaddr, e->offset);
4033 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4034 }
4035
4036 rtl_enable_clock_request(pdev);
4037}
4038
01dc7fec 4039static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4040{
4041 static const struct ephy_info e_info_8168e[] = {
4042 { 0x00, 0x0200, 0x0100 },
4043 { 0x00, 0x0000, 0x0004 },
4044 { 0x06, 0x0002, 0x0001 },
4045 { 0x06, 0x0000, 0x0030 },
4046 { 0x07, 0x0000, 0x2000 },
4047 { 0x00, 0x0000, 0x0020 },
4048 { 0x03, 0x5800, 0x2000 },
4049 { 0x03, 0x0000, 0x0001 },
4050 { 0x01, 0x0800, 0x1000 },
4051 { 0x07, 0x0000, 0x4000 },
4052 { 0x1e, 0x0000, 0x2000 },
4053 { 0x19, 0xffff, 0xfe6c },
4054 { 0x0a, 0x0000, 0x0040 }
4055 };
4056
4057 rtl_csi_access_enable_2(ioaddr);
4058
4059 rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4060
4061 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4062
4063 RTL_W8(MaxTxPacketSize, TxPacketMax);
4064
4065 rtl_disable_clock_request(pdev);
4066
4067 /* Reset tx FIFO pointer */
cecb5fd7
FR		 4068 RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4069 RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
01dc7fec 4070
cecb5fd7 4071 RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
01dc7fec 4072}
4073
07ce4064
FR		 4074static void rtl_hw_start_8168(struct net_device *dev)
4075{
2dd99530
FR		 4076 struct rtl8169_private *tp = netdev_priv(dev);
4077 void __iomem *ioaddr = tp->mmio_addr;
0e485150 4078 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 4079
4080 RTL_W8(Cfg9346, Cfg9346_Unlock);
4081
f0298f81 4082 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 4083
6f0333b8 4084 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 4085
0e485150 4086 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 4087
4088 RTL_W16(CPlusCmd, tp->cp_cmd);
4089
0e485150 4090 RTL_W16(IntrMitigate, 0x5151);
2dd99530 4091
0e485150 4092 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 4093 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4094 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 4095 tp->intr_event |= RxFIFOOver | PCSTimeout;
4096 tp->intr_event &= ~RxOverflow;
4097 }
4098
4099 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 4100
b8363901
FR		 4101 rtl_set_rx_mode(dev);
4102
4103 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4104 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 4105
4106 RTL_R8(IntrMask);
4107
219a1e9d
FR		 4108 switch (tp->mac_version) {
4109 case RTL_GIGA_MAC_VER_11:
4110 rtl_hw_start_8168bb(ioaddr, pdev);
4804b3b3 4111 break;
219a1e9d
FR		 4112
4113 case RTL_GIGA_MAC_VER_12:
4114 case RTL_GIGA_MAC_VER_17:
4115 rtl_hw_start_8168bef(ioaddr, pdev);
4804b3b3 4116 break;
219a1e9d
FR		 4117
4118 case RTL_GIGA_MAC_VER_18:
ef3386f0 4119 rtl_hw_start_8168cp_1(ioaddr, pdev);
4804b3b3 4120 break;
219a1e9d
FR		 4121
4122 case RTL_GIGA_MAC_VER_19:
4123 rtl_hw_start_8168c_1(ioaddr, pdev);
4804b3b3 4124 break;
219a1e9d
FR		 4125
4126 case RTL_GIGA_MAC_VER_20:
4127 rtl_hw_start_8168c_2(ioaddr, pdev);
4804b3b3 4128 break;
219a1e9d 4129
197ff761
FR		 4130 case RTL_GIGA_MAC_VER_21:
4131 rtl_hw_start_8168c_3(ioaddr, pdev);
4804b3b3 4132 break;
197ff761 4133
6fb07058
FR		 4134 case RTL_GIGA_MAC_VER_22:
4135 rtl_hw_start_8168c_4(ioaddr, pdev);
4804b3b3 4136 break;
6fb07058 4137
ef3386f0
FR		 4138 case RTL_GIGA_MAC_VER_23:
4139 rtl_hw_start_8168cp_2(ioaddr, pdev);
4804b3b3 4140 break;
ef3386f0 4141
7f3e3d3a
FR		 4142 case RTL_GIGA_MAC_VER_24:
4143 rtl_hw_start_8168cp_3(ioaddr, pdev);
4804b3b3 4144 break;
7f3e3d3a 4145
5b538df9 4146 case RTL_GIGA_MAC_VER_25:
daf9df6d 4147 case RTL_GIGA_MAC_VER_26:
4148 case RTL_GIGA_MAC_VER_27:
5b538df9 4149 rtl_hw_start_8168d(ioaddr, pdev);
4804b3b3 4150 break;
5b538df9 4151
e6de30d6 4152 case RTL_GIGA_MAC_VER_28:
4153 rtl_hw_start_8168d_4(ioaddr, pdev);
4804b3b3 4154 break;
cecb5fd7 4155
4804b3b3 4156 case RTL_GIGA_MAC_VER_31:
4157 rtl_hw_start_8168dp(ioaddr, pdev);
4158 break;
4159
01dc7fec 4160 case RTL_GIGA_MAC_VER_32:
4161 case RTL_GIGA_MAC_VER_33:
4162 rtl_hw_start_8168e(ioaddr, pdev);
4163 break;
e6de30d6 4164
219a1e9d
FR		 4165 default:
4166 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4167 dev->name, tp->mac_version);
4804b3b3 4168 break;
219a1e9d 4169 }
2dd99530 4170
0e485150
FR		 4171 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4172
b8363901
FR		 4173 RTL_W8(Cfg9346, Cfg9346_Lock);
4174
2dd99530 4175 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 4176
0e485150 4177 RTL_W16(IntrMask, tp->intr_event);
07ce4064 4178}
1da177e4 4179
2857ffb7
FR		 4180#define R810X_CPCMD_QUIRK_MASK (\
4181 EnableBist | \
4182 Mac_dbgo_oe | \
4183 Force_half_dup | \
5edcc537 4184 Force_rxflow_en | \
2857ffb7
FR		 4185 Force_txflow_en | \
4186 Cxpl_dbg_sel | \
4187 ASF | \
4188 PktCntrDisable | \
d24e9aaf 4189 Mac_dbgo_sel)
2857ffb7
FR		 4190
4191static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4192{
350f7596 4193 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 4194 { 0x01, 0, 0x6e65 },
4195 { 0x02, 0, 0x091f },
4196 { 0x03, 0, 0xc2f9 },
4197 { 0x06, 0, 0xafb5 },
4198 { 0x07, 0, 0x0e00 },
4199 { 0x19, 0, 0xec80 },
4200 { 0x01, 0, 0x2e65 },
4201 { 0x01, 0, 0x6e65 }
4202 };
4203 u8 cfg1;
4204
650e8d5d 4205 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4206
4207 RTL_W8(DBG_REG, FIX_NAK_1);
4208
4209 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4210
4211 RTL_W8(Config1,
4212 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4213 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4214
4215 cfg1 = RTL_R8(Config1);
4216 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4217 RTL_W8(Config1, cfg1 & ~LEDS0);
4218
2857ffb7
FR		 4219 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4220}
4221
4222static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4223{
650e8d5d 4224 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 4225
4226 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4227
4228 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4229 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2857ffb7
FR		 4230}
4231
4232static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4233{
4234 rtl_hw_start_8102e_2(ioaddr, pdev);
4235
4236 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4237}
4238
5a5e4443
HW		 4239static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4240{
4241 static const struct ephy_info e_info_8105e_1[] = {
4242 { 0x07, 0, 0x4000 },
4243 { 0x19, 0, 0x0200 },
4244 { 0x19, 0, 0x0020 },
4245 { 0x1e, 0, 0x2000 },
4246 { 0x03, 0, 0x0001 },
4247 { 0x19, 0, 0x0100 },
4248 { 0x19, 0, 0x0004 },
4249 { 0x0a, 0, 0x0020 }
4250 };
4251
cecb5fd7 4252 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5a5e4443
HW		 4253 RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4254
cecb5fd7 4255 /* Disable Early Tally Counter */
5a5e4443
HW		 4256 RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4257
4258 RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4259 RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4260
4261 rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4262}
4263
4264static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4265{
4266 rtl_hw_start_8105e_1(ioaddr, pdev);
4267 rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4268}
4269
07ce4064
FR		 4270static void rtl_hw_start_8101(struct net_device *dev)
4271{
cdf1a608
FR		 4272 struct rtl8169_private *tp = netdev_priv(dev);
4273 void __iomem *ioaddr = tp->mmio_addr;
4274 struct pci_dev *pdev = tp->pci_dev;
4275
cecb5fd7
FR		 4276 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4277 tp->mac_version == RTL_GIGA_MAC_VER_16) {
9c14ceaf
FR		 4278 int cap = tp->pcie_cap;
4279
4280 if (cap) {
4281 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4282 PCI_EXP_DEVCTL_NOSNOOP_EN);
4283 }
cdf1a608
FR		 4284 }
4285
d24e9aaf
HW		 4286 RTL_W8(Cfg9346, Cfg9346_Unlock);
4287
2857ffb7
FR		 4288 switch (tp->mac_version) {
4289 case RTL_GIGA_MAC_VER_07:
4290 rtl_hw_start_8102e_1(ioaddr, pdev);
4291 break;
4292
4293 case RTL_GIGA_MAC_VER_08:
4294 rtl_hw_start_8102e_3(ioaddr, pdev);
4295 break;
4296
4297 case RTL_GIGA_MAC_VER_09:
4298 rtl_hw_start_8102e_2(ioaddr, pdev);
4299 break;
5a5e4443
HW		 4300
4301 case RTL_GIGA_MAC_VER_29:
4302 rtl_hw_start_8105e_1(ioaddr, pdev);
4303 break;
4304 case RTL_GIGA_MAC_VER_30:
4305 rtl_hw_start_8105e_2(ioaddr, pdev);
4306 break;
cdf1a608
FR		 4307 }
4308
d24e9aaf 4309 RTL_W8(Cfg9346, Cfg9346_Lock);
cdf1a608 4310
f0298f81 4311 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 4312
6f0333b8 4313 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608 4314
d24e9aaf 4315 tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
cdf1a608
FR		 4316 RTL_W16(CPlusCmd, tp->cp_cmd);
4317
4318 RTL_W16(IntrMitigate, 0x0000);
4319
4320 rtl_set_rx_tx_desc_registers(tp, ioaddr);
4321
4322 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4323 rtl_set_rx_tx_config_registers(tp);
4324
cdf1a608
FR		 4325 RTL_R8(IntrMask);
4326
cdf1a608
FR		 4327 rtl_set_rx_mode(dev);
4328
4329 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 4330
0e485150 4331 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4332}
4333
4334static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4335{
1da177e4
LT		 4336 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4337 return -EINVAL;
4338
4339 dev->mtu = new_mtu;
350fb32a
MM		 4340 netdev_update_features(dev);
4341
323bb685 4342 return 0;
1da177e4
LT		 4343}
4344
4345static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4346{
95e0918d 4347 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 4348 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4349}
4350
6f0333b8
ED		 4351static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4352 void **data_buff, struct RxDesc *desc)
1da177e4 4353{
48addcc9 4354 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 4355 DMA_FROM_DEVICE);
48addcc9 4356
6f0333b8
ED		 4357 kfree(*data_buff);
4358 *data_buff = NULL;
1da177e4
LT		 4359 rtl8169_make_unusable_by_asic(desc);
4360}
4361
4362static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4363{
4364 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4365
4366 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4367}
4368
4369static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4370 u32 rx_buf_sz)
4371{
4372 desc->addr = cpu_to_le64(mapping);
4373 wmb();
4374 rtl8169_mark_to_asic(desc, rx_buf_sz);
4375}
4376
6f0333b8
ED		 4377static inline void *rtl8169_align(void *data)
4378{
4379 return (void *)ALIGN((long)data, 16);
4380}
4381
0ecbe1ca
SG		 4382static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4383 struct RxDesc *desc)
1da177e4 4384{
6f0333b8 4385 void *data;
1da177e4 4386 dma_addr_t mapping;
48addcc9 4387 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4388 struct net_device *dev = tp->dev;
6f0333b8 4389 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4390
6f0333b8
ED		 4391 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4392 if (!data)
4393 return NULL;
e9f63f30 4394
6f0333b8
ED		 4395 if (rtl8169_align(data) != data) {
4396 kfree(data);
4397 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4398 if (!data)
4399 return NULL;
4400 }
3eafe507 4401
48addcc9 4402 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4403 DMA_FROM_DEVICE);
d827d86b
SG		 4404 if (unlikely(dma_mapping_error(d, mapping))) {
4405 if (net_ratelimit())
4406 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4407 goto err_out;
d827d86b 4408 }
1da177e4
LT		 4409
4410 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4411 return data;
3eafe507
SG		 4412
4413err_out:
4414 kfree(data);
4415 return NULL;
1da177e4
LT		 4416}
4417
4418static void rtl8169_rx_clear(struct rtl8169_private *tp)
4419{
07d3f51f 4420 unsigned int i;
1da177e4
LT		 4421
4422 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4423 if (tp->Rx_databuff[i]) {
4424 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4425 tp->RxDescArray + i);
4426 }
4427 }
4428}
4429
0ecbe1ca 4430static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4431{
0ecbe1ca
SG		 4432 desc->opts1 |= cpu_to_le32(RingEnd);
4433}
5b0384f4 4434
0ecbe1ca
SG		 4435static int rtl8169_rx_fill(struct rtl8169_private *tp)
4436{
4437 unsigned int i;
1da177e4 4438
0ecbe1ca
SG		 4439 for (i = 0; i < NUM_RX_DESC; i++) {
4440 void *data;
4ae47c2d 4441
6f0333b8 4442 if (tp->Rx_databuff[i])
1da177e4 4443 continue;
bcf0bf90 4444
0ecbe1ca 4445 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4446 if (!data) {
4447 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4448 goto err_out;
6f0333b8
ED		 4449 }
4450 tp->Rx_databuff[i] = data;
1da177e4 4451 }
1da177e4 4452
0ecbe1ca
SG		 4453 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4454 return 0;
4455
4456err_out:
4457 rtl8169_rx_clear(tp);
4458 return -ENOMEM;
1da177e4
LT		 4459}
4460
4461static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4462{
4463 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4464}
4465
4466static int rtl8169_init_ring(struct net_device *dev)
4467{
4468 struct rtl8169_private *tp = netdev_priv(dev);
4469
4470 rtl8169_init_ring_indexes(tp);
4471
4472 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4473 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4474
0ecbe1ca 4475 return rtl8169_rx_fill(tp);
1da177e4
LT		 4476}
4477
48addcc9 4478static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4479 struct TxDesc *desc)
4480{
4481 unsigned int len = tx_skb->len;
4482
48addcc9
SG		 4483 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4484
1da177e4
LT		 4485 desc->opts1 = 0x00;
4486 desc->opts2 = 0x00;
4487 desc->addr = 0x00;
4488 tx_skb->len = 0;
4489}
4490
3eafe507
SG		 4491static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4492 unsigned int n)
1da177e4
LT		 4493{
4494 unsigned int i;
4495
3eafe507
SG		 4496 for (i = 0; i < n; i++) {
4497 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4498 struct ring_info *tx_skb = tp->tx_skb + entry;
4499 unsigned int len = tx_skb->len;
4500
4501 if (len) {
4502 struct sk_buff *skb = tx_skb->skb;
4503
48addcc9 4504 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4505 tp->TxDescArray + entry);
4506 if (skb) {
cac4b22f 4507 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4508 dev_kfree_skb(skb);
4509 tx_skb->skb = NULL;
4510 }
1da177e4
LT		 4511 }
4512 }
3eafe507
SG		 4513}
4514
4515static void rtl8169_tx_clear(struct rtl8169_private *tp)
4516{
4517 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4518 tp->cur_tx = tp->dirty_tx = 0;
4519}
4520
c4028958 4521static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4522{
4523 struct rtl8169_private *tp = netdev_priv(dev);
4524
c4028958 4525 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4526 schedule_delayed_work(&tp->task, 4);
4527}
4528
4529static void rtl8169_wait_for_quiescence(struct net_device *dev)
4530{
4531 struct rtl8169_private *tp = netdev_priv(dev);
4532 void __iomem *ioaddr = tp->mmio_addr;
4533
4534 synchronize_irq(dev->irq);
4535
4536 /* Wait for any pending NAPI task to complete */
bea3348e 4537 napi_disable(&tp->napi);
1da177e4
LT		 4538
4539 rtl8169_irq_mask_and_ack(ioaddr);
4540
d1d08d12
DM		 4541 tp->intr_mask = 0xffff;
4542 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4543 napi_enable(&tp->napi);
1da177e4
LT		 4544}
4545
c4028958 4546static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4547{
c4028958
DH		 4548 struct rtl8169_private *tp =
4549 container_of(work, struct rtl8169_private, task.work);
4550 struct net_device *dev = tp->dev;
1da177e4
LT		 4551 int ret;
4552
eb2a021c
FR		 4553 rtnl_lock();
4554
4555 if (!netif_running(dev))
4556 goto out_unlock;
4557
4558 rtl8169_wait_for_quiescence(dev);
4559 rtl8169_close(dev);
1da177e4
LT		 4560
4561 ret = rtl8169_open(dev);
4562 if (unlikely(ret < 0)) {
bf82c189
JP		 4563 if (net_ratelimit())
4564 netif_err(tp, drv, dev,
4565 "reinit failure (status = %d). Rescheduling\n",
4566 ret);
1da177e4
LT		 4567 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4568 }
eb2a021c
FR		 4569
4570out_unlock:
4571 rtnl_unlock();
1da177e4
LT		 4572}
4573
c4028958 4574static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4575{
c4028958
DH		 4576 struct rtl8169_private *tp =
4577 container_of(work, struct rtl8169_private, task.work);
4578 struct net_device *dev = tp->dev;
56de414c 4579 int i;
1da177e4 4580
eb2a021c
FR		 4581 rtnl_lock();
4582
1da177e4 4583 if (!netif_running(dev))
eb2a021c 4584 goto out_unlock;
1da177e4
LT		 4585
4586 rtl8169_wait_for_quiescence(dev);
4587
56de414c
FR		 4588 for (i = 0; i < NUM_RX_DESC; i++)
4589 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4590
1da177e4
LT		 4591 rtl8169_tx_clear(tp);
4592
56de414c
FR		 4593 rtl8169_init_ring_indexes(tp);
4594 rtl_hw_start(dev);
4595 netif_wake_queue(dev);
4596 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
eb2a021c
FR		 4597
4598out_unlock:
4599 rtnl_unlock();
1da177e4
LT		 4600}
4601
4602static void rtl8169_tx_timeout(struct net_device *dev)
4603{
4604 struct rtl8169_private *tp = netdev_priv(dev);
4605
e6de30d6 4606 rtl8169_hw_reset(tp);
1da177e4
LT		 4607
4608 /* Let's wait a bit while any (async) irq lands on */
4609 rtl8169_schedule_work(dev, rtl8169_reset_task);
4610}
4611
4612static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2b7b4318 4613 u32 *opts)
1da177e4
LT		 4614{
4615 struct skb_shared_info *info = skb_shinfo(skb);
4616 unsigned int cur_frag, entry;
a6343afb 4617 struct TxDesc * uninitialized_var(txd);
48addcc9 4618 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4619
4620 entry = tp->cur_tx;
4621 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4622 skb_frag_t *frag = info->frags + cur_frag;
4623 dma_addr_t mapping;
4624 u32 status, len;
4625 void *addr;
4626
4627 entry = (entry + 1) % NUM_TX_DESC;
4628
4629 txd = tp->TxDescArray + entry;
4630 len = frag->size;
4631 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4632 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4633 if (unlikely(dma_mapping_error(d, mapping))) {
4634 if (net_ratelimit())
4635 netif_err(tp, drv, tp->dev,
4636 "Failed to map TX fragments DMA!\n");
3eafe507 4637 goto err_out;
d827d86b 4638 }
1da177e4 4639
cecb5fd7 4640 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318
FR		 4641 status = opts[0] | len |
4642 (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4643
4644 txd->opts1 = cpu_to_le32(status);
2b7b4318 4645 txd->opts2 = cpu_to_le32(opts[1]);
1da177e4
LT		 4646 txd->addr = cpu_to_le64(mapping);
4647
4648 tp->tx_skb[entry].len = len;
4649 }
4650
4651 if (cur_frag) {
4652 tp->tx_skb[entry].skb = skb;
4653 txd->opts1 |= cpu_to_le32(LastFrag);
4654 }
4655
4656 return cur_frag;
3eafe507
SG		 4657
4658err_out:
4659 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4660 return -EIO;
1da177e4
LT		 4661}
4662
2b7b4318
FR		 4663static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4664 struct sk_buff *skb, u32 *opts)
1da177e4 4665{
2b7b4318 4666 const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
350fb32a 4667 u32 mss = skb_shinfo(skb)->gso_size;
2b7b4318 4668 int offset = info->opts_offset;
350fb32a 4669
2b7b4318
FR		 4670 if (mss) {
4671 opts[0] |= TD_LSO;
4672 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4673 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4674 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4675
4676 if (ip->protocol == IPPROTO_TCP)
2b7b4318 4677 opts[offset] |= info->checksum.tcp;
1da177e4 4678 else if (ip->protocol == IPPROTO_UDP)
2b7b4318
FR		 4679 opts[offset] |= info->checksum.udp;
4680 else
4681 WARN_ON_ONCE(1);
1da177e4 4682 }
1da177e4
LT		 4683}
4684
61357325
SH		 4685static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4686 struct net_device *dev)
1da177e4
LT		 4687{
4688 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4689 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4690 struct TxDesc *txd = tp->TxDescArray + entry;
4691 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4692 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4693 dma_addr_t mapping;
4694 u32 status, len;
2b7b4318 4695 u32 opts[2];
3eafe507 4696 int frags;
5b0384f4 4697
1da177e4 4698 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4699 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4700 goto err_stop_0;
1da177e4
LT		 4701 }
4702
4703 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4704 goto err_stop_0;
4705
4706 len = skb_headlen(skb);
48addcc9 4707 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4708 if (unlikely(dma_mapping_error(d, mapping))) {
4709 if (net_ratelimit())
4710 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4711 goto err_dma_0;
d827d86b 4712 }
3eafe507
SG		 4713
4714 tp->tx_skb[entry].len = len;
4715 txd->addr = cpu_to_le64(mapping);
1da177e4 4716
2b7b4318
FR		 4717 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4718 opts[0] = DescOwn;
1da177e4 4719
2b7b4318
FR		 4720 rtl8169_tso_csum(tp, skb, opts);
4721
4722 frags = rtl8169_xmit_frags(tp, skb, opts);
3eafe507
SG		 4723 if (frags < 0)
4724 goto err_dma_1;
4725 else if (frags)
2b7b4318 4726 opts[0] |= FirstFrag;
3eafe507 4727 else {
2b7b4318 4728 opts[0] |= FirstFrag | LastFrag;
1da177e4
LT		 4729 tp->tx_skb[entry].skb = skb;
4730 }
4731
2b7b4318
FR		 4732 txd->opts2 = cpu_to_le32(opts[1]);
4733
1da177e4
LT		 4734 wmb();
4735
cecb5fd7 4736 /* Anti gcc 2.95.3 bugware (sic) */
2b7b4318 4737 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
1da177e4
LT		 4738 txd->opts1 = cpu_to_le32(status);
4739
1da177e4
LT		 4740 tp->cur_tx += frags + 1;
4741
4c020a96 4742 wmb();
1da177e4 4743
cecb5fd7 4744 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4745
4746 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4747 netif_stop_queue(dev);
4748 smp_rmb();
4749 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4750 netif_wake_queue(dev);
4751 }
4752
61357325 4753 return NETDEV_TX_OK;
1da177e4 4754
3eafe507 4755err_dma_1:
48addcc9 4756 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4757err_dma_0:
4758 dev_kfree_skb(skb);
4759 dev->stats.tx_dropped++;
4760 return NETDEV_TX_OK;
4761
4762err_stop_0:
1da177e4 4763 netif_stop_queue(dev);
cebf8cc7 4764 dev->stats.tx_dropped++;
61357325 4765 return NETDEV_TX_BUSY;
1da177e4
LT		 4766}
4767
4768static void rtl8169_pcierr_interrupt(struct net_device *dev)
4769{
4770 struct rtl8169_private *tp = netdev_priv(dev);
4771 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4772 u16 pci_status, pci_cmd;
4773
4774 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4775 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4776
bf82c189
JP		 4777 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4778 pci_cmd, pci_status);
1da177e4
LT		 4779
4780 /*
4781 * The recovery sequence below admits a very elaborated explanation:
4782 * - it seems to work;
d03902b8
FR		 4783 * - I did not see what else could be done;
4784 * - it makes iop3xx happy.
1da177e4
LT		 4785 *
4786 * Feel free to adjust to your needs.
4787 */
a27993f3 4788 if (pdev->broken_parity_status)
d03902b8
FR		 4789 pci_cmd &= ~PCI_COMMAND_PARITY;
4790 else
4791 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4792
4793 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4794
4795 pci_write_config_word(pdev, PCI_STATUS,
4796 pci_status & (PCI_STATUS_DETECTED_PARITY |
4797 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4798 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4799
4800 /* The infamous DAC f*ckup only happens at boot time */
4801 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4802 void __iomem *ioaddr = tp->mmio_addr;
4803
bf82c189 4804 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4805 tp->cp_cmd &= ~PCIDAC;
4806 RTL_W16(CPlusCmd, tp->cp_cmd);
4807 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4808 }
4809
e6de30d6 4810 rtl8169_hw_reset(tp);
d03902b8
FR		 4811
4812 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4813}
4814
07d3f51f
FR		 4815static void rtl8169_tx_interrupt(struct net_device *dev,
4816 struct rtl8169_private *tp,
4817 void __iomem *ioaddr)
1da177e4
LT		 4818{
4819 unsigned int dirty_tx, tx_left;
4820
1da177e4
LT		 4821 dirty_tx = tp->dirty_tx;
4822 smp_rmb();
4823 tx_left = tp->cur_tx - dirty_tx;
4824
4825 while (tx_left > 0) {
4826 unsigned int entry = dirty_tx % NUM_TX_DESC;
4827 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4828 u32 status;
4829
4830 rmb();
4831 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4832 if (status & DescOwn)
4833 break;
4834
48addcc9
SG		 4835 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4836 tp->TxDescArray + entry);
1da177e4 4837 if (status & LastFrag) {
cac4b22f
SG		 4838 dev->stats.tx_packets++;
4839 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4840 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4841 tx_skb->skb = NULL;
4842 }
4843 dirty_tx++;
4844 tx_left--;
4845 }
4846
4847 if (tp->dirty_tx != dirty_tx) {
4848 tp->dirty_tx = dirty_tx;
4849 smp_wmb();
4850 if (netif_queue_stopped(dev) &&
4851 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4852 netif_wake_queue(dev);
4853 }
d78ae2dc
FR		 4854 /*
4855 * 8168 hack: TxPoll requests are lost when the Tx packets are
4856 * too close. Let's kick an extra TxPoll request when a burst
4857 * of start_xmit activity is detected (if it is not detected,
4858 * it is slow enough). -- FR
4859 */
4860 smp_rmb();
4861 if (tp->cur_tx != dirty_tx)
4862 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4863 }
4864}
4865
126fa4b9
FR		 4866static inline int rtl8169_fragmented_frame(u32 status)
4867{
4868 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4869}
4870
adea1ac7 4871static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4872{
1da177e4
LT		 4873 u32 status = opts1 & RxProtoMask;
4874
4875 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4876 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4877 skb->ip_summed = CHECKSUM_UNNECESSARY;
4878 else
bc8acf2c 4879 skb_checksum_none_assert(skb);
1da177e4
LT		 4880}
4881
6f0333b8
ED		 4882static struct sk_buff *rtl8169_try_rx_copy(void *data,
4883 struct rtl8169_private *tp,
4884 int pkt_size,
4885 dma_addr_t addr)
1da177e4 4886{
b449655f 4887 struct sk_buff *skb;
48addcc9 4888 struct device *d = &tp->pci_dev->dev;
b449655f 4889
6f0333b8 4890 data = rtl8169_align(data);
48addcc9 4891 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4892 prefetch(data);
4893 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4894 if (skb)
4895 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4896 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4897
6f0333b8 4898 return skb;
1da177e4
LT		 4899}
4900
07d3f51f
FR		 4901static int rtl8169_rx_interrupt(struct net_device *dev,
4902 struct rtl8169_private *tp,
bea3348e 4903 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4904{
4905 unsigned int cur_rx, rx_left;
6f0333b8 4906 unsigned int count;
1da177e4 4907
1da177e4
LT		 4908 cur_rx = tp->cur_rx;
4909 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4910 rx_left = min(rx_left, budget);
1da177e4 4911
4dcb7d33 4912 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4913 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4914 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4915 u32 status;
4916
4917 rmb();
126fa4b9 4918 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4919
4920 if (status & DescOwn)
4921 break;
4dcb7d33 4922 if (unlikely(status & RxRES)) {
bf82c189
JP		 4923 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4924 status);
cebf8cc7 4925 dev->stats.rx_errors++;
1da177e4 4926 if (status & (RxRWT | RxRUNT))
cebf8cc7 4927 dev->stats.rx_length_errors++;
1da177e4 4928 if (status & RxCRC)
cebf8cc7 4929 dev->stats.rx_crc_errors++;
9dccf611
FR		 4930 if (status & RxFOVF) {
4931 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4932 dev->stats.rx_fifo_errors++;
9dccf611 4933 }
6f0333b8 4934 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4935 } else {
6f0333b8 4936 struct sk_buff *skb;
b449655f 4937 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4938 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4939
126fa4b9
FR		 4940 /*
4941 * The driver does not support incoming fragmented
4942 * frames. They are seen as a symptom of over-mtu
4943 * sized frames.
4944 */
4945 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4946 dev->stats.rx_dropped++;
4947 dev->stats.rx_length_errors++;
6f0333b8 4948 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4949 continue;
126fa4b9
FR		 4950 }
4951
6f0333b8
ED		 4952 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4953 tp, pkt_size, addr);
4954 rtl8169_mark_to_asic(desc, rx_buf_sz);
4955 if (!skb) {
4956 dev->stats.rx_dropped++;
4957 continue;
1da177e4
LT		 4958 }
4959
adea1ac7 4960 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4961 skb_put(skb, pkt_size);
4962 skb->protocol = eth_type_trans(skb, dev);
4963
7a8fc77b
FR		 4964 rtl8169_rx_vlan_tag(desc, skb);
4965
56de414c 4966 napi_gro_receive(&tp->napi, skb);
1da177e4 4967
cebf8cc7
FR		 4968 dev->stats.rx_bytes += pkt_size;
4969 dev->stats.rx_packets++;
1da177e4 4970 }
6dccd16b
FR		 4971
4972 /* Work around for AMD plateform. */
95e0918d 4973 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4974 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4975 desc->opts2 = 0;
4976 cur_rx++;
4977 }
1da177e4
LT		 4978 }
4979
4980 count = cur_rx - tp->cur_rx;
4981 tp->cur_rx = cur_rx;
4982
6f0333b8 4983 tp->dirty_rx += count;
1da177e4
LT		 4984
4985 return count;
4986}
4987
07d3f51f 4988static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4989{
07d3f51f 4990 struct net_device *dev = dev_instance;
1da177e4 4991 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4992 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4993 int handled = 0;
865c652d 4994 int status;
1da177e4 4995
f11a377b
DD		 4996 /* loop handling interrupts until we have no new ones or
4997 * we hit a invalid/hotplug case.
4998 */
865c652d 4999 status = RTL_R16(IntrStatus);
f11a377b
DD		 5000 while (status && status != 0xffff) {
5001 handled = 1;
1da177e4 5002
f11a377b
DD		 5003 /* Handle all of the error cases first. These will reset
5004 * the chip, so just exit the loop.
5005 */
5006 if (unlikely(!netif_running(dev))) {
5007 rtl8169_asic_down(ioaddr);
5008 break;
5009 }
1da177e4 5010
1519e57f
FR		 5011 if (unlikely(status & RxFIFOOver)) {
5012 switch (tp->mac_version) {
5013 /* Work around for rx fifo overflow */
5014 case RTL_GIGA_MAC_VER_11:
5015 case RTL_GIGA_MAC_VER_22:
5016 case RTL_GIGA_MAC_VER_26:
5017 netif_stop_queue(dev);
5018 rtl8169_tx_timeout(dev);
5019 goto done;
f60ac8e7
FR		 5020 /* Testers needed. */
5021 case RTL_GIGA_MAC_VER_17:
5022 case RTL_GIGA_MAC_VER_19:
5023 case RTL_GIGA_MAC_VER_20:
5024 case RTL_GIGA_MAC_VER_21:
5025 case RTL_GIGA_MAC_VER_23:
5026 case RTL_GIGA_MAC_VER_24:
5027 case RTL_GIGA_MAC_VER_27:
5028 case RTL_GIGA_MAC_VER_28:
4804b3b3 5029 case RTL_GIGA_MAC_VER_31:
1519e57f
FR		 5030 /* Experimental science. Pktgen proof. */
5031 case RTL_GIGA_MAC_VER_12:
5032 case RTL_GIGA_MAC_VER_25:
5033 if (status == RxFIFOOver)
5034 goto done;
5035 break;
5036 default:
5037 break;
5038 }
f11a377b 5039 }
1da177e4 5040
f11a377b
DD		 5041 if (unlikely(status & SYSErr)) {
5042 rtl8169_pcierr_interrupt(dev);
5043 break;
5044 }
1da177e4 5045
f11a377b 5046 if (status & LinkChg)
e4fbce74 5047 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 5048
f11a377b
DD		 5049 /* We need to see the lastest version of tp->intr_mask to
5050 * avoid ignoring an MSI interrupt and having to wait for
5051 * another event which may never come.
5052 */
5053 smp_rmb();
5054 if (status & tp->intr_mask & tp->napi_event) {
5055 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5056 tp->intr_mask = ~tp->napi_event;
5057
5058 if (likely(napi_schedule_prep(&tp->napi)))
5059 __napi_schedule(&tp->napi);
bf82c189
JP		 5060 else
5061 netif_info(tp, intr, dev,
5062 "interrupt %04x in poll\n", status);
f11a377b 5063 }
1da177e4 5064
f11a377b
DD		 5065 /* We only get a new MSI interrupt when all active irq
5066 * sources on the chip have been acknowledged. So, ack
5067 * everything we've seen and check if new sources have become
5068 * active to avoid blocking all interrupts from the chip.
5069 */
5070 RTL_W16(IntrStatus,
5071 (status & RxFIFOOver) ? (status | RxOverflow) : status);
5072 status = RTL_R16(IntrStatus);
865c652d 5073 }
1519e57f 5074done:
1da177e4
LT		 5075 return IRQ_RETVAL(handled);
5076}
5077
bea3348e 5078static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 5079{
bea3348e
SH		 5080 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5081 struct net_device *dev = tp->dev;
1da177e4 5082 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 5083 int work_done;
1da177e4 5084
bea3348e 5085 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 5086 rtl8169_tx_interrupt(dev, tp, ioaddr);
5087
bea3348e 5088 if (work_done < budget) {
288379f0 5089 napi_complete(napi);
f11a377b
DD		 5090
5091 /* We need for force the visibility of tp->intr_mask
5092 * for other CPUs, as we can loose an MSI interrupt
5093 * and potentially wait for a retransmit timeout if we don't.
5094 * The posted write to IntrMask is safe, as it will
5095 * eventually make it to the chip and we won't loose anything
5096 * until it does.
1da177e4 5097 */
f11a377b 5098 tp->intr_mask = 0xffff;
4c020a96 5099 wmb();
0e485150 5100 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 5101 }
5102
bea3348e 5103 return work_done;
1da177e4 5104}
1da177e4 5105
523a6094
FR		 5106static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5107{
5108 struct rtl8169_private *tp = netdev_priv(dev);
5109
5110 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5111 return;
5112
5113 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5114 RTL_W32(RxMissed, 0);
5115}
5116
1da177e4
LT		 5117static void rtl8169_down(struct net_device *dev)
5118{
5119 struct rtl8169_private *tp = netdev_priv(dev);
5120 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 5121
4876cc1e 5122 del_timer_sync(&tp->timer);
1da177e4
LT		 5123
5124 netif_stop_queue(dev);
5125
93dd79e8 5126 napi_disable(&tp->napi);
93dd79e8 5127
1da177e4
LT		 5128 spin_lock_irq(&tp->lock);
5129
5130 rtl8169_asic_down(ioaddr);
323bb685
SG		 5131 /*
5132 * At this point device interrupts can not be enabled in any function,
5133 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5134 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5135 */
523a6094 5136 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5137
5138 spin_unlock_irq(&tp->lock);
5139
5140 synchronize_irq(dev->irq);
5141
1da177e4 5142 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 5143 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 5144
1da177e4
LT		 5145 rtl8169_tx_clear(tp);
5146
5147 rtl8169_rx_clear(tp);
065c27c1 5148
5149 rtl_pll_power_down(tp);
1da177e4
LT		 5150}
5151
5152static int rtl8169_close(struct net_device *dev)
5153{
5154 struct rtl8169_private *tp = netdev_priv(dev);
5155 struct pci_dev *pdev = tp->pci_dev;
5156
e1759441
RW		 5157 pm_runtime_get_sync(&pdev->dev);
5158
cecb5fd7 5159 /* Update counters before going down */
355423d0
IV		 5160 rtl8169_update_counters(dev);
5161
1da177e4
LT		 5162 rtl8169_down(dev);
5163
5164 free_irq(dev->irq, dev);
5165
82553bb6
SG		 5166 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5167 tp->RxPhyAddr);
5168 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5169 tp->TxPhyAddr);
1da177e4
LT		 5170 tp->TxDescArray = NULL;
5171 tp->RxDescArray = NULL;
5172
e1759441
RW		 5173 pm_runtime_put_sync(&pdev->dev);
5174
1da177e4
LT		 5175 return 0;
5176}
5177
07ce4064 5178static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 5179{
5180 struct rtl8169_private *tp = netdev_priv(dev);
5181 void __iomem *ioaddr = tp->mmio_addr;
5182 unsigned long flags;
5183 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 5184 int rx_mode;
1da177e4
LT		 5185 u32 tmp = 0;
5186
5187 if (dev->flags & IFF_PROMISC) {
5188 /* Unconditionally log net taps. */
bf82c189 5189 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 5190 rx_mode =
5191 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5192 AcceptAllPhys;
5193 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 5194 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 5195 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 5196 /* Too many to filter perfectly -- accept all multicasts. */
5197 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5198 mc_filter[1] = mc_filter[0] = 0xffffffff;
5199 } else {
22bedad3 5200 struct netdev_hw_addr *ha;
07d3f51f 5201
1da177e4
LT		 5202 rx_mode = AcceptBroadcast | AcceptMyPhys;
5203 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 5204 netdev_for_each_mc_addr(ha, dev) {
5205 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 5206 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5207 rx_mode |= AcceptMulticast;
5208 }
5209 }
5210
5211 spin_lock_irqsave(&tp->lock, flags);
5212
5213 tmp = rtl8169_rx_config | rx_mode |
2b7b4318 5214 (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
1da177e4 5215
f887cce8 5216 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 5217 u32 data = mc_filter[0];
5218
5219 mc_filter[0] = swab32(mc_filter[1]);
5220 mc_filter[1] = swab32(data);
bcf0bf90
FR		 5221 }
5222
1da177e4 5223 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 5224 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 5225
57a9f236
FR		 5226 RTL_W32(RxConfig, tmp);
5227
1da177e4
LT		 5228 spin_unlock_irqrestore(&tp->lock, flags);
5229}
5230
5231/**
5232 * rtl8169_get_stats - Get rtl8169 read/write statistics
5233 * @dev: The Ethernet Device to get statistics for
5234 *
5235 * Get TX/RX statistics for rtl8169
5236 */
5237static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5238{
5239 struct rtl8169_private *tp = netdev_priv(dev);
5240 void __iomem *ioaddr = tp->mmio_addr;
5241 unsigned long flags;
5242
5243 if (netif_running(dev)) {
5244 spin_lock_irqsave(&tp->lock, flags);
523a6094 5245 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 5246 spin_unlock_irqrestore(&tp->lock, flags);
5247 }
5b0384f4 5248
cebf8cc7 5249 return &dev->stats;
1da177e4
LT		 5250}
5251
861ab440 5252static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 5253{
065c27c1 5254 struct rtl8169_private *tp = netdev_priv(dev);
5255
5d06a99f 5256 if (!netif_running(dev))
861ab440 5257 return;
5d06a99f 5258
065c27c1 5259 rtl_pll_power_down(tp);
5260
5d06a99f
FR		 5261 netif_device_detach(dev);
5262 netif_stop_queue(dev);
861ab440
RW		 5263}
5264
5265#ifdef CONFIG_PM
5266
5267static int rtl8169_suspend(struct device *device)
5268{
5269 struct pci_dev *pdev = to_pci_dev(device);
5270 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 5271
861ab440 5272 rtl8169_net_suspend(dev);
1371fa6d 5273
5d06a99f
FR		 5274 return 0;
5275}
5276
e1759441
RW		 5277static void __rtl8169_resume(struct net_device *dev)
5278{
065c27c1 5279 struct rtl8169_private *tp = netdev_priv(dev);
5280
e1759441 5281 netif_device_attach(dev);
065c27c1 5282
5283 rtl_pll_power_up(tp);
5284
e1759441
RW		 5285 rtl8169_schedule_work(dev, rtl8169_reset_task);
5286}
5287
861ab440 5288static int rtl8169_resume(struct device *device)
5d06a99f 5289{
861ab440 5290 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 5291 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 5292 struct rtl8169_private *tp = netdev_priv(dev);
5293
5294 rtl8169_init_phy(dev, tp);
5d06a99f 5295
e1759441
RW		 5296 if (netif_running(dev))
5297 __rtl8169_resume(dev);
5d06a99f 5298
e1759441
RW		 5299 return 0;
5300}
5301
5302static int rtl8169_runtime_suspend(struct device *device)
5303{
5304 struct pci_dev *pdev = to_pci_dev(device);
5305 struct net_device *dev = pci_get_drvdata(pdev);
5306 struct rtl8169_private *tp = netdev_priv(dev);
5307
5308 if (!tp->TxDescArray)
5309 return 0;
5310
5311 spin_lock_irq(&tp->lock);
5312 tp->saved_wolopts = __rtl8169_get_wol(tp);
5313 __rtl8169_set_wol(tp, WAKE_ANY);
5314 spin_unlock_irq(&tp->lock);
5315
5316 rtl8169_net_suspend(dev);
5317
5318 return 0;
5319}
5320
5321static int rtl8169_runtime_resume(struct device *device)
5322{
5323 struct pci_dev *pdev = to_pci_dev(device);
5324 struct net_device *dev = pci_get_drvdata(pdev);
5325 struct rtl8169_private *tp = netdev_priv(dev);
5326
5327 if (!tp->TxDescArray)
5328 return 0;
5329
5330 spin_lock_irq(&tp->lock);
5331 __rtl8169_set_wol(tp, tp->saved_wolopts);
5332 tp->saved_wolopts = 0;
5333 spin_unlock_irq(&tp->lock);
5334
fccec10b
SG		 5335 rtl8169_init_phy(dev, tp);
5336
e1759441 5337 __rtl8169_resume(dev);
5d06a99f 5338
5d06a99f
FR		 5339 return 0;
5340}
5341
e1759441
RW		 5342static int rtl8169_runtime_idle(struct device *device)
5343{
5344 struct pci_dev *pdev = to_pci_dev(device);
5345 struct net_device *dev = pci_get_drvdata(pdev);
5346 struct rtl8169_private *tp = netdev_priv(dev);
5347
e4fbce74 5348 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 5349}
5350
47145210 5351static const struct dev_pm_ops rtl8169_pm_ops = {
cecb5fd7
FR		 5352 .suspend = rtl8169_suspend,
5353 .resume = rtl8169_resume,
5354 .freeze = rtl8169_suspend,
5355 .thaw = rtl8169_resume,
5356 .poweroff = rtl8169_suspend,
5357 .restore = rtl8169_resume,
5358 .runtime_suspend = rtl8169_runtime_suspend,
5359 .runtime_resume = rtl8169_runtime_resume,
5360 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 5361};
5362
5363#define RTL8169_PM_OPS (&rtl8169_pm_ops)
5364
5365#else /* !CONFIG_PM */
5366
5367#define RTL8169_PM_OPS NULL
5368
5369#endif /* !CONFIG_PM */
5370
1765f95d
FR		 5371static void rtl_shutdown(struct pci_dev *pdev)
5372{
861ab440 5373 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5374 struct rtl8169_private *tp = netdev_priv(dev);
5375 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5376
5377 rtl8169_net_suspend(dev);
1765f95d 5378
cecb5fd7 5379 /* Restore original MAC address */
cc098dc7
IV		 5380 rtl_rar_set(tp, dev->perm_addr);
5381
4bb3f522 5382 spin_lock_irq(&tp->lock);
5383
5384 rtl8169_asic_down(ioaddr);
5385
5386 spin_unlock_irq(&tp->lock);
5387
861ab440 5388 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 5389 /* WoL fails with some 8168 when the receiver is disabled. */
5390 if (tp->features & RTL_FEATURE_WOL) {
5391 pci_clear_master(pdev);
5392
5393 RTL_W8(ChipCmd, CmdRxEnb);
5394 /* PCI commit */
5395 RTL_R8(ChipCmd);
5396 }
5397
861ab440
RW		 5398 pci_wake_from_d3(pdev, true);
5399 pci_set_power_state(pdev, PCI_D3hot);
5400 }
5401}
5d06a99f 5402
1da177e4
LT		 5403static struct pci_driver rtl8169_pci_driver = {
5404 .name = MODULENAME,
5405 .id_table = rtl8169_pci_tbl,
5406 .probe = rtl8169_init_one,
5407 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5408 .shutdown = rtl_shutdown,
861ab440 5409 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5410};
5411
07d3f51f 5412static int __init rtl8169_init_module(void)
1da177e4 5413{
29917620 5414 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5415}
5416
07d3f51f 5417static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5418{
5419 pci_unregister_driver(&rtl8169_pci_driver);
5420}
5421
5422module_init(rtl8169_init_module);
5423module_exit(rtl8169_cleanup_module);
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