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r8169: fix incorrect args to oob notify.
[mirror_ubuntu-eoan-kernel.git] / drivers / net / r8169.c
CommitLineData
1da177e4 1/*
07d3f51f
FR		 2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
1da177e4
LT		 9 */
10
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/pci.h>
14#include <linux/netdevice.h>
15#include <linux/etherdevice.h>
16#include <linux/delay.h>
17#include <linux/ethtool.h>
18#include <linux/mii.h>
19#include <linux/if_vlan.h>
20#include <linux/crc32.h>
21#include <linux/in.h>
22#include <linux/ip.h>
23#include <linux/tcp.h>
24#include <linux/init.h>
25#include <linux/dma-mapping.h>
e1759441 26#include <linux/pm_runtime.h>
bca03d5f 27#include <linux/firmware.h>
1da177e4 28
99f252b0 29#include <asm/system.h>
1da177e4
LT		 30#include <asm/io.h>
31#include <asm/irq.h>
32
865c652d 33#define RTL8169_VERSION "2.3LK-NAPI"
1da177e4
LT		 34#define MODULENAME "r8169"
35#define PFX MODULENAME ": "
36
bca03d5f 37#define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38#define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39
1da177e4
LT		 40#ifdef RTL8169_DEBUG
41#define assert(expr) \
5b0384f4
FR		 42 if (!(expr)) { \
43 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
b39d66a8 44 #expr,__FILE__,__func__,__LINE__); \
5b0384f4 45 }
06fa7358
JP		 46#define dprintk(fmt, args...) \
47 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
1da177e4
LT		 48#else
49#define assert(expr) do {} while (0)
50#define dprintk(fmt, args...) do {} while (0)
51#endif /* RTL8169_DEBUG */
52
b57b7e5a 53#define R8169_MSG_DEFAULT \
f0e837d9 54 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
b57b7e5a 55
1da177e4
LT		 56#define TX_BUFFS_AVAIL(tp) \
57 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
58
1da177e4
LT		 59/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
60 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
f71e1309 61static const int multicast_filter_limit = 32;
1da177e4
LT		 62
63/* MAC address length */
64#define MAC_ADDR_LEN 6
65
9c14ceaf 66#define MAX_READ_REQUEST_SHIFT 12
1da177e4
LT		 67#define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
68#define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
69#define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
1da177e4
LT		 70#define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
71#define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
72
73#define R8169_REGS_SIZE 256
74#define R8169_NAPI_WEIGHT 64
75#define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
76#define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
77#define RX_BUF_SIZE 1536 /* Rx Buffer size */
78#define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79#define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81#define RTL8169_TX_TIMEOUT (6*HZ)
82#define RTL8169_PHY_TIMEOUT (10*HZ)
83
ea8dbdd1 84#define RTL_EEPROM_SIG cpu_to_le32(0x8129)
85#define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
e1564ec9
FR		 86#define RTL_EEPROM_SIG_ADDR 0x0000
87
1da177e4
LT		 88/* write/read MMIO register */
89#define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
90#define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
91#define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
92#define RTL_R8(reg) readb (ioaddr + (reg))
93#define RTL_R16(reg) readw (ioaddr + (reg))
06f555f3 94#define RTL_R32(reg) readl (ioaddr + (reg))
1da177e4
LT		 95
96enum mac_version {
f21b75e9 97 RTL_GIGA_MAC_NONE = 0x00,
ba6eb6ee
FR		 98 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
99 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
100 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
101 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
102 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
6dccd16b 103 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
2857ffb7
FR		 104 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
105 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
106 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
107 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
2dd99530 108 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
e3cf0cc0
FR		 109 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
110 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
111 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
112 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
113 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
114 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
115 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
116 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
197ff761 117 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
6fb07058 118 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
ef3386f0 119 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
7f3e3d3a 120 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
5b538df9 121 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
daf9df6d 122 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
123 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
e6de30d6 124 RTL_GIGA_MAC_VER_27 = 0x1b, // 8168DP
125 RTL_GIGA_MAC_VER_28 = 0x1c, // 8168DP
1da177e4
LT		 126};
127
1da177e4
LT		 128#define _R(NAME,MAC,MASK) \
129 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
130
3c6bee1d 131static const struct {
1da177e4
LT		 132 const char *name;
133 u8 mac_version;
134 u32 RxConfigMask; /* Clears the bits supported by this chip */
135} rtl_chip_info[] = {
ba6eb6ee
FR		 136 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
137 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
138 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
139 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
140 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
6dccd16b 141 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
2857ffb7
FR		 142 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
143 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
144 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
145 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
bcf0bf90
FR		 146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
147 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
148 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
149 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
e3cf0cc0
FR		 150 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
151 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
152 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
154 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
197ff761 155 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
6fb07058 156 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
ef3386f0 157 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
7f3e3d3a 158 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
5b538df9 159 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
daf9df6d 160 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
161 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
e6de30d6 162 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880), // PCI-E
163 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_28, 0xff7e1880) // PCI-E
1da177e4
LT		 164};
165#undef _R
166
bcf0bf90
FR		 167enum cfg_version {
168 RTL_CFG_0 = 0x00,
169 RTL_CFG_1,
170 RTL_CFG_2
171};
172
07ce4064
FR		 173static void rtl_hw_start_8169(struct net_device *);
174static void rtl_hw_start_8168(struct net_device *);
175static void rtl_hw_start_8101(struct net_device *);
176
a3aa1884 177static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
bcf0bf90 178 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
d2eed8cf 179 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
d81bf551 180 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
07ce4064 181 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
bcf0bf90
FR		 182 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
183 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
bc1660b5 184 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
bcf0bf90
FR		 185 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
186 { PCI_VENDOR_ID_LINKSYS, 0x1032,
187 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
11d2e282
CM		 188 { 0x0001, 0x8168,
189 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
1da177e4
LT		 190 {0,},
191};
192
193MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
194
6f0333b8 195static int rx_buf_sz = 16383;
4300e8c7 196static int use_dac;
b57b7e5a
SH		 197static struct {
198 u32 msg_enable;
199} debug = { -1 };
1da177e4 200
07d3f51f
FR		 201enum rtl_registers {
202 MAC0 = 0, /* Ethernet hardware address. */
773d2021 203 MAC4 = 4,
07d3f51f
FR		 204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3c,
216 IntrStatus = 0x3e,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4c,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5c,
228 PHYAR = 0x60,
07d3f51f
FR		 229 PHYstatus = 0x6c,
230 RxMaxSize = 0xda,
231 CPlusCmd = 0xe0,
232 IntrMitigate = 0xe2,
233 RxDescAddrLow = 0xe4,
234 RxDescAddrHigh = 0xe8,
f0298f81 235 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
236
237#define NoEarlyTx 0x3f /* Max value : no early transmit. */
238
239 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
240
241#define TxPacketMax (8064 >> 7)
242
07d3f51f
FR		 243 FuncEvent = 0xf0,
244 FuncEventMask = 0xf4,
245 FuncPresetState = 0xf8,
246 FuncForceEvent = 0xfc,
1da177e4
LT		 247};
248
f162a5d1
FR		 249enum rtl8110_registers {
250 TBICSR = 0x64,
251 TBI_ANAR = 0x68,
252 TBI_LPAR = 0x6a,
253};
254
255enum rtl8168_8101_registers {
256 CSIDR = 0x64,
257 CSIAR = 0x68,
258#define CSIAR_FLAG 0x80000000
259#define CSIAR_WRITE_CMD 0x80000000
260#define CSIAR_BYTE_ENABLE 0x0f
261#define CSIAR_BYTE_ENABLE_SHIFT 12
262#define CSIAR_ADDR_MASK 0x0fff
065c27c1 263 PMCH = 0x6f,
f162a5d1
FR		 264 EPHYAR = 0x80,
265#define EPHYAR_FLAG 0x80000000
266#define EPHYAR_WRITE_CMD 0x80000000
267#define EPHYAR_REG_MASK 0x1f
268#define EPHYAR_REG_SHIFT 16
269#define EPHYAR_DATA_MASK 0xffff
270 DBG_REG = 0xd1,
271#define FIX_NAK_1 (1 << 4)
272#define FIX_NAK_2 (1 << 3)
daf9df6d 273 EFUSEAR = 0xdc,
274#define EFUSEAR_FLAG 0x80000000
275#define EFUSEAR_WRITE_CMD 0x80000000
276#define EFUSEAR_READ_CMD 0x00000000
277#define EFUSEAR_REG_MASK 0x03ff
278#define EFUSEAR_REG_SHIFT 8
279#define EFUSEAR_DATA_MASK 0xff
f162a5d1
FR		 280};
281
c0e45c1c 282enum rtl8168_registers {
b646d900 283 ERIDR = 0x70,
284 ERIAR = 0x74,
285#define ERIAR_FLAG 0x80000000
286#define ERIAR_WRITE_CMD 0x80000000
287#define ERIAR_READ_CMD 0x00000000
288#define ERIAR_ADDR_BYTE_ALIGN 4
289#define ERIAR_EXGMAC 0
290#define ERIAR_MSIX 1
291#define ERIAR_ASF 2
292#define ERIAR_TYPE_SHIFT 16
293#define ERIAR_BYTEEN 0x0f
294#define ERIAR_BYTEEN_SHIFT 12
c0e45c1c 295 EPHY_RXER_NUM = 0x7c,
296 OCPDR = 0xb0, /* OCP GPHY access */
297#define OCPDR_WRITE_CMD 0x80000000
298#define OCPDR_READ_CMD 0x00000000
299#define OCPDR_REG_MASK 0x7f
300#define OCPDR_GPHY_REG_SHIFT 16
301#define OCPDR_DATA_MASK 0xffff
302 OCPAR = 0xb4,
303#define OCPAR_FLAG 0x80000000
304#define OCPAR_GPHY_WRITE_CMD 0x8000f060
305#define OCPAR_GPHY_READ_CMD 0x0000f060
e6de30d6 306 RDSAR1 = 0xd0 /* 8168c only. Undocumented on 8168dp */
c0e45c1c 307};
308
07d3f51f 309enum rtl_register_content {
1da177e4 310 /* InterruptStatusBits */
07d3f51f
FR		 311 SYSErr = 0x8000,
312 PCSTimeout = 0x4000,
313 SWInt = 0x0100,
314 TxDescUnavail = 0x0080,
315 RxFIFOOver = 0x0040,
316 LinkChg = 0x0020,
317 RxOverflow = 0x0010,
318 TxErr = 0x0008,
319 TxOK = 0x0004,
320 RxErr = 0x0002,
321 RxOK = 0x0001,
1da177e4
LT		 322
323 /* RxStatusDesc */
9dccf611
FR		 324 RxFOVF = (1 << 23),
325 RxRWT = (1 << 22),
326 RxRES = (1 << 21),
327 RxRUNT = (1 << 20),
328 RxCRC = (1 << 19),
1da177e4
LT		 329
330 /* ChipCmdBits */
07d3f51f
FR		 331 CmdReset = 0x10,
332 CmdRxEnb = 0x08,
333 CmdTxEnb = 0x04,
334 RxBufEmpty = 0x01,
1da177e4 335
275391a4
FR		 336 /* TXPoll register p.5 */
337 HPQ = 0x80, /* Poll cmd on the high prio queue */
338 NPQ = 0x40, /* Poll cmd on the low prio queue */
339 FSWInt = 0x01, /* Forced software interrupt */
340
1da177e4 341 /* Cfg9346Bits */
07d3f51f
FR		 342 Cfg9346_Lock = 0x00,
343 Cfg9346_Unlock = 0xc0,
1da177e4
LT		 344
345 /* rx_mode_bits */
07d3f51f
FR		 346 AcceptErr = 0x20,
347 AcceptRunt = 0x10,
348 AcceptBroadcast = 0x08,
349 AcceptMulticast = 0x04,
350 AcceptMyPhys = 0x02,
351 AcceptAllPhys = 0x01,
1da177e4
LT		 352
353 /* RxConfigBits */
07d3f51f
FR		 354 RxCfgFIFOShift = 13,
355 RxCfgDMAShift = 8,
1da177e4
LT		 356
357 /* TxConfigBits */
358 TxInterFrameGapShift = 24,
359 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
360
5d06a99f 361 /* Config1 register p.24 */
f162a5d1
FR		 362 LEDS1 = (1 << 7),
363 LEDS0 = (1 << 6),
fbac58fc 364 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
f162a5d1
FR		 365 Speed_down = (1 << 4),
366 MEMMAP = (1 << 3),
367 IOMAP = (1 << 2),
368 VPD = (1 << 1),
5d06a99f
FR		 369 PMEnable = (1 << 0), /* Power Management Enable */
370
6dccd16b
FR		 371 /* Config2 register p. 25 */
372 PCI_Clock_66MHz = 0x01,
373 PCI_Clock_33MHz = 0x00,
374
61a4dcc2
FR		 375 /* Config3 register p.25 */
376 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
377 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
f162a5d1 378 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
61a4dcc2 379
5d06a99f 380 /* Config5 register p.27 */
61a4dcc2
FR		 381 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
382 MWF = (1 << 5), /* Accept Multicast wakeup frame */
383 UWF = (1 << 4), /* Accept Unicast wakeup frame */
384 LanWake = (1 << 1), /* LanWake enable/disable */
5d06a99f
FR		 385 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
386
1da177e4
LT		 387 /* TBICSR p.28 */
388 TBIReset = 0x80000000,
389 TBILoopback = 0x40000000,
390 TBINwEnable = 0x20000000,
391 TBINwRestart = 0x10000000,
392 TBILinkOk = 0x02000000,
393 TBINwComplete = 0x01000000,
394
395 /* CPlusCmd p.31 */
f162a5d1
FR		 396 EnableBist = (1 << 15), // 8168 8101
397 Mac_dbgo_oe = (1 << 14), // 8168 8101
398 Normal_mode = (1 << 13), // unused
399 Force_half_dup = (1 << 12), // 8168 8101
400 Force_rxflow_en = (1 << 11), // 8168 8101
401 Force_txflow_en = (1 << 10), // 8168 8101
402 Cxpl_dbg_sel = (1 << 9), // 8168 8101
403 ASF = (1 << 8), // 8168 8101
404 PktCntrDisable = (1 << 7), // 8168 8101
405 Mac_dbgo_sel = 0x001c, // 8168
1da177e4
LT		 406 RxVlan = (1 << 6),
407 RxChkSum = (1 << 5),
408 PCIDAC = (1 << 4),
409 PCIMulRW = (1 << 3),
0e485150
FR		 410 INTT_0 = 0x0000, // 8168
411 INTT_1 = 0x0001, // 8168
412 INTT_2 = 0x0002, // 8168
413 INTT_3 = 0x0003, // 8168
1da177e4
LT		 414
415 /* rtl8169_PHYstatus */
07d3f51f
FR		 416 TBI_Enable = 0x80,
417 TxFlowCtrl = 0x40,
418 RxFlowCtrl = 0x20,
419 _1000bpsF = 0x10,
420 _100bps = 0x08,
421 _10bps = 0x04,
422 LinkStatus = 0x02,
423 FullDup = 0x01,
1da177e4 424
1da177e4 425 /* _TBICSRBit */
07d3f51f 426 TBILinkOK = 0x02000000,
d4a3a0fc
SH		 427
428 /* DumpCounterCommand */
07d3f51f 429 CounterDump = 0x8,
1da177e4
LT		 430};
431
07d3f51f 432enum desc_status_bit {
1da177e4
LT		 433 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
434 RingEnd = (1 << 30), /* End of descriptor ring */
435 FirstFrag = (1 << 29), /* First segment of a packet */
436 LastFrag = (1 << 28), /* Final segment of a packet */
437
438 /* Tx private */
439 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
440 MSSShift = 16, /* MSS value position */
441 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
442 IPCS = (1 << 18), /* Calculate IP checksum */
443 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
444 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
445 TxVlanTag = (1 << 17), /* Add VLAN tag */
446
447 /* Rx private */
448 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
449 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
450
451#define RxProtoUDP (PID1)
452#define RxProtoTCP (PID0)
453#define RxProtoIP (PID1 | PID0)
454#define RxProtoMask RxProtoIP
455
456 IPFail = (1 << 16), /* IP checksum failed */
457 UDPFail = (1 << 15), /* UDP/IP checksum failed */
458 TCPFail = (1 << 14), /* TCP/IP checksum failed */
459 RxVlanTag = (1 << 16), /* VLAN tag available */
460};
461
462#define RsvdMask 0x3fffc000
463
464struct TxDesc {
6cccd6e7
REB		 465 __le32 opts1;
466 __le32 opts2;
467 __le64 addr;
1da177e4
LT		 468};
469
470struct RxDesc {
6cccd6e7
REB		 471 __le32 opts1;
472 __le32 opts2;
473 __le64 addr;
1da177e4
LT		 474};
475
476struct ring_info {
477 struct sk_buff *skb;
478 u32 len;
479 u8 __pad[sizeof(void *) - sizeof(u32)];
480};
481
f23e7fda 482enum features {
ccdffb9a
FR		 483 RTL_FEATURE_WOL = (1 << 0),
484 RTL_FEATURE_MSI = (1 << 1),
485 RTL_FEATURE_GMII = (1 << 2),
f23e7fda
FR		 486};
487
355423d0
IV		 488struct rtl8169_counters {
489 __le64 tx_packets;
490 __le64 rx_packets;
491 __le64 tx_errors;
492 __le32 rx_errors;
493 __le16 rx_missed;
494 __le16 align_errors;
495 __le32 tx_one_collision;
496 __le32 tx_multi_collision;
497 __le64 rx_unicast;
498 __le64 rx_broadcast;
499 __le32 rx_multicast;
500 __le16 tx_aborted;
501 __le16 tx_underun;
502};
503
1da177e4
LT		 504struct rtl8169_private {
505 void __iomem *mmio_addr; /* memory map physical address */
506 struct pci_dev *pci_dev; /* Index of PCI device */
c4028958 507 struct net_device *dev;
bea3348e 508 struct napi_struct napi;
1da177e4 509 spinlock_t lock; /* spin lock flag */
b57b7e5a 510 u32 msg_enable;
1da177e4
LT		 511 int chipset;
512 int mac_version;
1da177e4
LT		 513 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
514 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
515 u32 dirty_rx;
516 u32 dirty_tx;
517 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
518 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
519 dma_addr_t TxPhyAddr;
520 dma_addr_t RxPhyAddr;
6f0333b8 521 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
1da177e4 522 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
1da177e4
LT		 523 struct timer_list timer;
524 u16 cp_cmd;
0e485150
FR		 525 u16 intr_event;
526 u16 napi_event;
1da177e4 527 u16 intr_mask;
1da177e4
LT		 528 int phy_1000_ctrl_reg;
529#ifdef CONFIG_R8169_VLAN
530 struct vlan_group *vlgrp;
531#endif
c0e45c1c 532
533 struct mdio_ops {
534 void (*write)(void __iomem *, int, int);
535 int (*read)(void __iomem *, int);
536 } mdio_ops;
537
065c27c1 538 struct pll_power_ops {
539 void (*down)(struct rtl8169_private *);
540 void (*up)(struct rtl8169_private *);
541 } pll_power_ops;
542
1da177e4 543 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
ccdffb9a 544 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
4da19633 545 void (*phy_reset_enable)(struct rtl8169_private *tp);
07ce4064 546 void (*hw_start)(struct net_device *);
4da19633 547 unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
1da177e4 548 unsigned int (*link_ok)(void __iomem *);
8b4ab28d 549 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
9c14ceaf 550 int pcie_cap;
c4028958 551 struct delayed_work task;
f23e7fda 552 unsigned features;
ccdffb9a
FR		 553
554 struct mii_if_info mii;
355423d0 555 struct rtl8169_counters counters;
e1759441 556 u32 saved_wolopts;
f1e02ed1 557
558 const struct firmware *fw;
1da177e4
LT		 559};
560
979b6c13 561MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
1da177e4 562MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
1da177e4 563module_param(use_dac, int, 0);
4300e8c7 564MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
b57b7e5a
SH		 565module_param_named(debug, debug.msg_enable, int, 0);
566MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
1da177e4
LT		 567MODULE_LICENSE("GPL");
568MODULE_VERSION(RTL8169_VERSION);
bca03d5f 569MODULE_FIRMWARE(FIRMWARE_8168D_1);
570MODULE_FIRMWARE(FIRMWARE_8168D_2);
1da177e4
LT		 571
572static int rtl8169_open(struct net_device *dev);
61357325
SH		 573static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
574 struct net_device *dev);
7d12e780 575static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
1da177e4 576static int rtl8169_init_ring(struct net_device *dev);
07ce4064 577static void rtl_hw_start(struct net_device *dev);
1da177e4 578static int rtl8169_close(struct net_device *dev);
07ce4064 579static void rtl_set_rx_mode(struct net_device *dev);
1da177e4 580static void rtl8169_tx_timeout(struct net_device *dev);
4dcb7d33 581static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
1da177e4 582static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
bea3348e 583 void __iomem *, u32 budget);
4dcb7d33 584static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
1da177e4 585static void rtl8169_down(struct net_device *dev);
99f252b0 586static void rtl8169_rx_clear(struct rtl8169_private *tp);
bea3348e 587static int rtl8169_poll(struct napi_struct *napi, int budget);
1da177e4 588
1da177e4 589static const unsigned int rtl8169_rx_config =
5b0384f4 590 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
1da177e4 591
b646d900 592static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
593{
594 void __iomem *ioaddr = tp->mmio_addr;
595 int i;
596
597 RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
598 for (i = 0; i < 20; i++) {
599 udelay(100);
600 if (RTL_R32(OCPAR) & OCPAR_FLAG)
601 break;
602 }
603 return RTL_R32(OCPDR);
604}
605
606static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
607{
608 void __iomem *ioaddr = tp->mmio_addr;
609 int i;
610
611 RTL_W32(OCPDR, data);
612 RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
613 for (i = 0; i < 20; i++) {
614 udelay(100);
615 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
616 break;
617 }
618}
619
fac5b3ca 620static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
b646d900 621{
fac5b3ca 622 void __iomem *ioaddr = tp->mmio_addr;
b646d900 623 int i;
624
625 RTL_W8(ERIDR, cmd);
626 RTL_W32(ERIAR, 0x800010e8);
627 msleep(2);
628 for (i = 0; i < 5; i++) {
629 udelay(100);
630 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
631 break;
632 }
633
fac5b3ca 634 ocp_write(tp, 0x1, 0x30, 0x00000001);
b646d900 635}
636
637#define OOB_CMD_RESET 0x00
638#define OOB_CMD_DRIVER_START 0x05
639#define OOB_CMD_DRIVER_STOP 0x06
640
641static void rtl8168_driver_start(struct rtl8169_private *tp)
642{
643 int i;
644
645 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
646
647 for (i = 0; i < 10; i++) {
648 msleep(10);
649 if (ocp_read(tp, 0x0f, 0x0010) & 0x00000800)
650 break;
651 }
652}
653
654static void rtl8168_driver_stop(struct rtl8169_private *tp)
655{
656 int i;
657
658 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
659
660 for (i = 0; i < 10; i++) {
661 msleep(10);
662 if ((ocp_read(tp, 0x0f, 0x0010) & 0x00000800) == 0)
663 break;
664 }
665}
666
667
4da19633 668static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
1da177e4
LT		 669{
670 int i;
671
a6baf3af 672 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
1da177e4 673
2371408c 674 for (i = 20; i > 0; i--) {
07d3f51f
FR		 675 /*
676 * Check if the RTL8169 has completed writing to the specified
677 * MII register.
678 */
5b0384f4 679 if (!(RTL_R32(PHYAR) & 0x80000000))
1da177e4 680 break;
2371408c 681 udelay(25);
1da177e4 682 }
024a07ba 683 /*
81a95f04
TT		 684 * According to hardware specs a 20us delay is required after write
685 * complete indication, but before sending next command.
024a07ba 686 */
81a95f04 687 udelay(20);
1da177e4
LT		 688}
689
4da19633 690static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
1da177e4
LT		 691{
692 int i, value = -1;
693
a6baf3af 694 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
1da177e4 695
2371408c 696 for (i = 20; i > 0; i--) {
07d3f51f
FR		 697 /*
698 * Check if the RTL8169 has completed retrieving data from
699 * the specified MII register.
700 */
1da177e4 701 if (RTL_R32(PHYAR) & 0x80000000) {
a6baf3af 702 value = RTL_R32(PHYAR) & 0xffff;
1da177e4
LT		 703 break;
704 }
2371408c 705 udelay(25);
1da177e4 706 }
81a95f04
TT		 707 /*
708 * According to hardware specs a 20us delay is required after read
709 * complete indication, but before sending next command.
710 */
711 udelay(20);
712
1da177e4
LT		 713 return value;
714}
715
c0e45c1c 716static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
717{
718 int i;
719
720 RTL_W32(OCPDR, data |
721 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
722 RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
723 RTL_W32(EPHY_RXER_NUM, 0);
724
725 for (i = 0; i < 100; i++) {
726 mdelay(1);
727 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
728 break;
729 }
730}
731
732static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
733{
734 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
735 (value & OCPDR_DATA_MASK));
736}
737
738static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
739{
740 int i;
741
742 r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
743
744 mdelay(1);
745 RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
746 RTL_W32(EPHY_RXER_NUM, 0);
747
748 for (i = 0; i < 100; i++) {
749 mdelay(1);
750 if (RTL_R32(OCPAR) & OCPAR_FLAG)
751 break;
752 }
753
754 return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
755}
756
e6de30d6 757#define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
758
759static void r8168dp_2_mdio_start(void __iomem *ioaddr)
760{
761 RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
762}
763
764static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
765{
766 RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
767}
768
769static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
770{
771 r8168dp_2_mdio_start(ioaddr);
772
773 r8169_mdio_write(ioaddr, reg_addr, value);
774
775 r8168dp_2_mdio_stop(ioaddr);
776}
777
778static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
779{
780 int value;
781
782 r8168dp_2_mdio_start(ioaddr);
783
784 value = r8169_mdio_read(ioaddr, reg_addr);
785
786 r8168dp_2_mdio_stop(ioaddr);
787
788 return value;
789}
790
4da19633 791static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
dacf8154 792{
c0e45c1c 793 tp->mdio_ops.write(tp->mmio_addr, location, val);
dacf8154
FR		 794}
795
4da19633 796static int rtl_readphy(struct rtl8169_private *tp, int location)
797{
c0e45c1c 798 return tp->mdio_ops.read(tp->mmio_addr, location);
4da19633 799}
800
801static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
802{
803 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
804}
805
806static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
daf9df6d 807{
808 int val;
809
4da19633 810 val = rtl_readphy(tp, reg_addr);
811 rtl_writephy(tp, reg_addr, (val | p) & ~m);
daf9df6d 812}
813
ccdffb9a
FR		 814static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
815 int val)
816{
817 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 818
4da19633 819 rtl_writephy(tp, location, val);
ccdffb9a
FR		 820}
821
822static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
823{
824 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a 825
4da19633 826 return rtl_readphy(tp, location);
ccdffb9a
FR		 827}
828
dacf8154
FR		 829static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
830{
831 unsigned int i;
832
833 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
834 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
835
836 for (i = 0; i < 100; i++) {
837 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
838 break;
839 udelay(10);
840 }
841}
842
843static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
844{
845 u16 value = 0xffff;
846 unsigned int i;
847
848 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
849
850 for (i = 0; i < 100; i++) {
851 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
852 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
853 break;
854 }
855 udelay(10);
856 }
857
858 return value;
859}
860
861static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
862{
863 unsigned int i;
864
865 RTL_W32(CSIDR, value);
866 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
867 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
868
869 for (i = 0; i < 100; i++) {
870 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
871 break;
872 udelay(10);
873 }
874}
875
876static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
877{
878 u32 value = ~0x00;
879 unsigned int i;
880
881 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
882 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
883
884 for (i = 0; i < 100; i++) {
885 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
886 value = RTL_R32(CSIDR);
887 break;
888 }
889 udelay(10);
890 }
891
892 return value;
893}
894
daf9df6d 895static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
896{
897 u8 value = 0xff;
898 unsigned int i;
899
900 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
901
902 for (i = 0; i < 300; i++) {
903 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
904 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
905 break;
906 }
907 udelay(100);
908 }
909
910 return value;
911}
912
1da177e4
LT		 913static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
914{
915 RTL_W16(IntrMask, 0x0000);
916
917 RTL_W16(IntrStatus, 0xffff);
918}
919
920static void rtl8169_asic_down(void __iomem *ioaddr)
921{
922 RTL_W8(ChipCmd, 0x00);
923 rtl8169_irq_mask_and_ack(ioaddr);
924 RTL_R16(CPlusCmd);
925}
926
4da19633 927static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1da177e4 928{
4da19633 929 void __iomem *ioaddr = tp->mmio_addr;
930
1da177e4
LT		 931 return RTL_R32(TBICSR) & TBIReset;
932}
933
4da19633 934static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1da177e4 935{
4da19633 936 return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1da177e4
LT		 937}
938
939static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
940{
941 return RTL_R32(TBICSR) & TBILinkOk;
942}
943
944static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
945{
946 return RTL_R8(PHYstatus) & LinkStatus;
947}
948
4da19633 949static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1da177e4 950{
4da19633 951 void __iomem *ioaddr = tp->mmio_addr;
952
1da177e4
LT		 953 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
954}
955
4da19633 956static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1da177e4
LT		 957{
958 unsigned int val;
959
4da19633 960 val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
961 rtl_writephy(tp, MII_BMCR, val & 0xffff);
1da177e4
LT		 962}
963
e4fbce74 964static void __rtl8169_check_link_status(struct net_device *dev,
07d3f51f 965 struct rtl8169_private *tp,
e4fbce74
RW		 966 void __iomem *ioaddr,
967 bool pm)
1da177e4
LT		 968{
969 unsigned long flags;
970
971 spin_lock_irqsave(&tp->lock, flags);
972 if (tp->link_ok(ioaddr)) {
e1759441 973 /* This is to cancel a scheduled suspend if there's one. */
e4fbce74
RW		 974 if (pm)
975 pm_request_resume(&tp->pci_dev->dev);
1da177e4 976 netif_carrier_on(dev);
1519e57f
FR		 977 if (net_ratelimit())
978 netif_info(tp, ifup, dev, "link up\n");
b57b7e5a 979 } else {
1da177e4 980 netif_carrier_off(dev);
bf82c189 981 netif_info(tp, ifdown, dev, "link down\n");
e4fbce74
RW		 982 if (pm)
983 pm_schedule_suspend(&tp->pci_dev->dev, 100);
b57b7e5a 984 }
1da177e4
LT		 985 spin_unlock_irqrestore(&tp->lock, flags);
986}
987
e4fbce74
RW		 988static void rtl8169_check_link_status(struct net_device *dev,
989 struct rtl8169_private *tp,
990 void __iomem *ioaddr)
991{
992 __rtl8169_check_link_status(dev, tp, ioaddr, false);
993}
994
e1759441
RW		 995#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
996
997static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
61a4dcc2 998{
61a4dcc2
FR		 999 void __iomem *ioaddr = tp->mmio_addr;
1000 u8 options;
e1759441 1001 u32 wolopts = 0;
61a4dcc2
FR		 1002
1003 options = RTL_R8(Config1);
1004 if (!(options & PMEnable))
e1759441 1005 return 0;
61a4dcc2
FR		 1006
1007 options = RTL_R8(Config3);
1008 if (options & LinkUp)
e1759441 1009 wolopts |= WAKE_PHY;
61a4dcc2 1010 if (options & MagicPacket)
e1759441 1011 wolopts |= WAKE_MAGIC;
61a4dcc2
FR		 1012
1013 options = RTL_R8(Config5);
1014 if (options & UWF)
e1759441 1015 wolopts |= WAKE_UCAST;
61a4dcc2 1016 if (options & BWF)
e1759441 1017 wolopts |= WAKE_BCAST;
61a4dcc2 1018 if (options & MWF)
e1759441 1019 wolopts |= WAKE_MCAST;
61a4dcc2 1020
e1759441 1021 return wolopts;
61a4dcc2
FR		 1022}
1023
e1759441 1024static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
61a4dcc2
FR		 1025{
1026 struct rtl8169_private *tp = netdev_priv(dev);
e1759441
RW		 1027
1028 spin_lock_irq(&tp->lock);
1029
1030 wol->supported = WAKE_ANY;
1031 wol->wolopts = __rtl8169_get_wol(tp);
1032
1033 spin_unlock_irq(&tp->lock);
1034}
1035
1036static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1037{
61a4dcc2 1038 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 1039 unsigned int i;
350f7596 1040 static const struct {
61a4dcc2
FR		 1041 u32 opt;
1042 u16 reg;
1043 u8 mask;
1044 } cfg[] = {
1045 { WAKE_ANY, Config1, PMEnable },
1046 { WAKE_PHY, Config3, LinkUp },
1047 { WAKE_MAGIC, Config3, MagicPacket },
1048 { WAKE_UCAST, Config5, UWF },
1049 { WAKE_BCAST, Config5, BWF },
1050 { WAKE_MCAST, Config5, MWF },
1051 { WAKE_ANY, Config5, LanWake }
1052 };
1053
61a4dcc2
FR		 1054 RTL_W8(Cfg9346, Cfg9346_Unlock);
1055
1056 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1057 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
e1759441 1058 if (wolopts & cfg[i].opt)
61a4dcc2
FR		 1059 options |= cfg[i].mask;
1060 RTL_W8(cfg[i].reg, options);
1061 }
1062
1063 RTL_W8(Cfg9346, Cfg9346_Lock);
e1759441
RW		 1064}
1065
1066static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1067{
1068 struct rtl8169_private *tp = netdev_priv(dev);
1069
1070 spin_lock_irq(&tp->lock);
61a4dcc2 1071
f23e7fda
FR		 1072 if (wol->wolopts)
1073 tp->features |= RTL_FEATURE_WOL;
1074 else
1075 tp->features &= ~RTL_FEATURE_WOL;
e1759441 1076 __rtl8169_set_wol(tp, wol->wolopts);
61a4dcc2
FR		 1077 spin_unlock_irq(&tp->lock);
1078
ea80907f 1079 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1080
61a4dcc2
FR		 1081 return 0;
1082}
1083
1da177e4
LT		 1084static void rtl8169_get_drvinfo(struct net_device *dev,
1085 struct ethtool_drvinfo *info)
1086{
1087 struct rtl8169_private *tp = netdev_priv(dev);
1088
1089 strcpy(info->driver, MODULENAME);
1090 strcpy(info->version, RTL8169_VERSION);
1091 strcpy(info->bus_info, pci_name(tp->pci_dev));
1092}
1093
1094static int rtl8169_get_regs_len(struct net_device *dev)
1095{
1096 return R8169_REGS_SIZE;
1097}
1098
1099static int rtl8169_set_speed_tbi(struct net_device *dev,
1100 u8 autoneg, u16 speed, u8 duplex)
1101{
1102 struct rtl8169_private *tp = netdev_priv(dev);
1103 void __iomem *ioaddr = tp->mmio_addr;
1104 int ret = 0;
1105 u32 reg;
1106
1107 reg = RTL_R32(TBICSR);
1108 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1109 (duplex == DUPLEX_FULL)) {
1110 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1111 } else if (autoneg == AUTONEG_ENABLE)
1112 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1113 else {
bf82c189
JP		 1114 netif_warn(tp, link, dev,
1115 "incorrect speed setting refused in TBI mode\n");
1da177e4
LT		 1116 ret = -EOPNOTSUPP;
1117 }
1118
1119 return ret;
1120}
1121
1122static int rtl8169_set_speed_xmii(struct net_device *dev,
1123 u8 autoneg, u16 speed, u8 duplex)
1124{
1125 struct rtl8169_private *tp = netdev_priv(dev);
3577aa1b 1126 int giga_ctrl, bmcr;
1da177e4
LT		 1127
1128 if (autoneg == AUTONEG_ENABLE) {
3577aa1b 1129 int auto_nego;
1130
4da19633 1131 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
64e4bfb4
FR		 1132 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1133 ADVERTISE_100HALF | ADVERTISE_100FULL);
3577aa1b 1134 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1da177e4 1135
4da19633 1136 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
3577aa1b 1137 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
bcf0bf90 1138
3577aa1b 1139 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1140 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
1141 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
1142 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
1143 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
1144 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
1145 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
1146 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
1147 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
1148 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
bf82c189
JP		 1149 } else {
1150 netif_info(tp, link, dev,
1151 "PHY does not support 1000Mbps\n");
bcf0bf90 1152 }
1da177e4 1153
3577aa1b 1154 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1155
1156 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
1157 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
1158 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
1159 /*
1160 * Wake up the PHY.
1161 * Vendor specific (0x1f) and reserved (0x0e) MII
1162 * registers.
1163 */
4da19633 1164 rtl_writephy(tp, 0x1f, 0x0000);
1165 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1166 }
1167
4da19633 1168 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1169 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
3577aa1b 1170 } else {
1171 giga_ctrl = 0;
1172
1173 if (speed == SPEED_10)
1174 bmcr = 0;
1175 else if (speed == SPEED_100)
1176 bmcr = BMCR_SPEED100;
1177 else
1178 return -EINVAL;
1179
1180 if (duplex == DUPLEX_FULL)
1181 bmcr |= BMCR_FULLDPLX;
623a1593 1182
4da19633 1183 rtl_writephy(tp, 0x1f, 0x0000);
2584fbc3
RS		 1184 }
1185
1da177e4
LT		 1186 tp->phy_1000_ctrl_reg = giga_ctrl;
1187
4da19633 1188 rtl_writephy(tp, MII_BMCR, bmcr);
3577aa1b 1189
1190 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
1191 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
1192 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
4da19633 1193 rtl_writephy(tp, 0x17, 0x2138);
1194 rtl_writephy(tp, 0x0e, 0x0260);
3577aa1b 1195 } else {
4da19633 1196 rtl_writephy(tp, 0x17, 0x2108);
1197 rtl_writephy(tp, 0x0e, 0x0000);
3577aa1b 1198 }
1199 }
1200
1da177e4
LT		 1201 return 0;
1202}
1203
1204static int rtl8169_set_speed(struct net_device *dev,
1205 u8 autoneg, u16 speed, u8 duplex)
1206{
1207 struct rtl8169_private *tp = netdev_priv(dev);
1208 int ret;
1209
1210 ret = tp->set_speed(dev, autoneg, speed, duplex);
1211
64e4bfb4 1212 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 1213 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1214
1215 return ret;
1216}
1217
1218static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1219{
1220 struct rtl8169_private *tp = netdev_priv(dev);
1221 unsigned long flags;
1222 int ret;
1223
1224 spin_lock_irqsave(&tp->lock, flags);
1225 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
1226 spin_unlock_irqrestore(&tp->lock, flags);
5b0384f4 1227
1da177e4
LT		 1228 return ret;
1229}
1230
1231static u32 rtl8169_get_rx_csum(struct net_device *dev)
1232{
1233 struct rtl8169_private *tp = netdev_priv(dev);
1234
1235 return tp->cp_cmd & RxChkSum;
1236}
1237
1238static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1239{
1240 struct rtl8169_private *tp = netdev_priv(dev);
1241 void __iomem *ioaddr = tp->mmio_addr;
1242 unsigned long flags;
1243
1244 spin_lock_irqsave(&tp->lock, flags);
1245
1246 if (data)
1247 tp->cp_cmd |= RxChkSum;
1248 else
1249 tp->cp_cmd &= ~RxChkSum;
1250
1251 RTL_W16(CPlusCmd, tp->cp_cmd);
1252 RTL_R16(CPlusCmd);
1253
1254 spin_unlock_irqrestore(&tp->lock, flags);
1255
1256 return 0;
1257}
1258
1259#ifdef CONFIG_R8169_VLAN
1260
1261static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1262 struct sk_buff *skb)
1263{
eab6d18d 1264 return (vlan_tx_tag_present(skb)) ?
1da177e4
LT		 1265 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1266}
1267
1268static void rtl8169_vlan_rx_register(struct net_device *dev,
1269 struct vlan_group *grp)
1270{
1271 struct rtl8169_private *tp = netdev_priv(dev);
1272 void __iomem *ioaddr = tp->mmio_addr;
1273 unsigned long flags;
1274
1275 spin_lock_irqsave(&tp->lock, flags);
1276 tp->vlgrp = grp;
05af2142
SW		 1277 /*
1278 * Do not disable RxVlan on 8110SCd.
1279 */
1280 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1da177e4
LT		 1281 tp->cp_cmd |= RxVlan;
1282 else
1283 tp->cp_cmd &= ~RxVlan;
1284 RTL_W16(CPlusCmd, tp->cp_cmd);
1285 RTL_R16(CPlusCmd);
1286 spin_unlock_irqrestore(&tp->lock, flags);
1287}
1288
1da177e4 1289static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1290 struct sk_buff *skb, int polling)
1da177e4
LT		 1291{
1292 u32 opts2 = le32_to_cpu(desc->opts2);
865c652d 1293 struct vlan_group *vlgrp = tp->vlgrp;
1da177e4
LT		 1294 int ret;
1295
865c652d 1296 if (vlgrp && (opts2 & RxVlanTag)) {
2edae08e
ED		 1297 u16 vtag = swab16(opts2 & 0xffff);
1298
1299 if (likely(polling))
1300 vlan_gro_receive(&tp->napi, vlgrp, vtag, skb);
1301 else
1302 __vlan_hwaccel_rx(skb, vlgrp, vtag, polling);
1da177e4
LT		 1303 ret = 0;
1304 } else
1305 ret = -1;
1306 desc->opts2 = 0;
1307 return ret;
1308}
1309
1310#else /* !CONFIG_R8169_VLAN */
1311
1312static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1313 struct sk_buff *skb)
1314{
1315 return 0;
1316}
1317
1318static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
630b943c 1319 struct sk_buff *skb, int polling)
1da177e4
LT		 1320{
1321 return -1;
1322}
1323
1324#endif
1325
ccdffb9a 1326static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1327{
1328 struct rtl8169_private *tp = netdev_priv(dev);
1329 void __iomem *ioaddr = tp->mmio_addr;
1330 u32 status;
1331
1332 cmd->supported =
1333 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1334 cmd->port = PORT_FIBRE;
1335 cmd->transceiver = XCVR_INTERNAL;
1336
1337 status = RTL_R32(TBICSR);
1338 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1339 cmd->autoneg = !!(status & TBINwEnable);
1340
1341 cmd->speed = SPEED_1000;
1342 cmd->duplex = DUPLEX_FULL; /* Always set */
ccdffb9a
FR		 1343
1344 return 0;
1da177e4
LT		 1345}
1346
ccdffb9a 1347static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1da177e4
LT		 1348{
1349 struct rtl8169_private *tp = netdev_priv(dev);
ccdffb9a
FR		 1350
1351 return mii_ethtool_gset(&tp->mii, cmd);
1da177e4
LT		 1352}
1353
1354static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1355{
1356 struct rtl8169_private *tp = netdev_priv(dev);
1357 unsigned long flags;
ccdffb9a 1358 int rc;
1da177e4
LT		 1359
1360 spin_lock_irqsave(&tp->lock, flags);
1361
ccdffb9a 1362 rc = tp->get_settings(dev, cmd);
1da177e4
LT		 1363
1364 spin_unlock_irqrestore(&tp->lock, flags);
ccdffb9a 1365 return rc;
1da177e4
LT		 1366}
1367
1368static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1369 void *p)
1370{
5b0384f4
FR		 1371 struct rtl8169_private *tp = netdev_priv(dev);
1372 unsigned long flags;
1da177e4 1373
5b0384f4
FR		 1374 if (regs->len > R8169_REGS_SIZE)
1375 regs->len = R8169_REGS_SIZE;
1da177e4 1376
5b0384f4
FR		 1377 spin_lock_irqsave(&tp->lock, flags);
1378 memcpy_fromio(p, tp->mmio_addr, regs->len);
1379 spin_unlock_irqrestore(&tp->lock, flags);
1da177e4
LT		 1380}
1381
b57b7e5a
SH		 1382static u32 rtl8169_get_msglevel(struct net_device *dev)
1383{
1384 struct rtl8169_private *tp = netdev_priv(dev);
1385
1386 return tp->msg_enable;
1387}
1388
1389static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1390{
1391 struct rtl8169_private *tp = netdev_priv(dev);
1392
1393 tp->msg_enable = value;
1394}
1395
d4a3a0fc
SH		 1396static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1397 "tx_packets",
1398 "rx_packets",
1399 "tx_errors",
1400 "rx_errors",
1401 "rx_missed",
1402 "align_errors",
1403 "tx_single_collisions",
1404 "tx_multi_collisions",
1405 "unicast",
1406 "broadcast",
1407 "multicast",
1408 "tx_aborted",
1409 "tx_underrun",
1410};
1411
b9f2c044 1412static int rtl8169_get_sset_count(struct net_device *dev, int sset)
d4a3a0fc 1413{
b9f2c044
JG		 1414 switch (sset) {
1415 case ETH_SS_STATS:
1416 return ARRAY_SIZE(rtl8169_gstrings);
1417 default:
1418 return -EOPNOTSUPP;
1419 }
d4a3a0fc
SH		 1420}
1421
355423d0 1422static void rtl8169_update_counters(struct net_device *dev)
d4a3a0fc
SH		 1423{
1424 struct rtl8169_private *tp = netdev_priv(dev);
1425 void __iomem *ioaddr = tp->mmio_addr;
1426 struct rtl8169_counters *counters;
1427 dma_addr_t paddr;
1428 u32 cmd;
355423d0 1429 int wait = 1000;
48addcc9 1430 struct device *d = &tp->pci_dev->dev;
d4a3a0fc 1431
355423d0
IV		 1432 /*
1433 * Some chips are unable to dump tally counters when the receiver
1434 * is disabled.
1435 */
1436 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1437 return;
d4a3a0fc 1438
48addcc9 1439 counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
d4a3a0fc
SH		 1440 if (!counters)
1441 return;
1442
1443 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
284901a9 1444 cmd = (u64)paddr & DMA_BIT_MASK(32);
d4a3a0fc
SH		 1445 RTL_W32(CounterAddrLow, cmd);
1446 RTL_W32(CounterAddrLow, cmd | CounterDump);
1447
355423d0
IV		 1448 while (wait--) {
1449 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1450 /* copy updated counters */
1451 memcpy(&tp->counters, counters, sizeof(*counters));
d4a3a0fc 1452 break;
355423d0
IV		 1453 }
1454 udelay(10);
d4a3a0fc
SH		 1455 }
1456
1457 RTL_W32(CounterAddrLow, 0);
1458 RTL_W32(CounterAddrHigh, 0);
1459
48addcc9 1460 dma_free_coherent(d, sizeof(*counters), counters, paddr);
d4a3a0fc
SH		 1461}
1462
355423d0
IV		 1463static void rtl8169_get_ethtool_stats(struct net_device *dev,
1464 struct ethtool_stats *stats, u64 *data)
1465{
1466 struct rtl8169_private *tp = netdev_priv(dev);
1467
1468 ASSERT_RTNL();
1469
1470 rtl8169_update_counters(dev);
1471
1472 data[0] = le64_to_cpu(tp->counters.tx_packets);
1473 data[1] = le64_to_cpu(tp->counters.rx_packets);
1474 data[2] = le64_to_cpu(tp->counters.tx_errors);
1475 data[3] = le32_to_cpu(tp->counters.rx_errors);
1476 data[4] = le16_to_cpu(tp->counters.rx_missed);
1477 data[5] = le16_to_cpu(tp->counters.align_errors);
1478 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1479 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1480 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1481 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1482 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1483 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1484 data[12] = le16_to_cpu(tp->counters.tx_underun);
1485}
1486
d4a3a0fc
SH		 1487static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1488{
1489 switch(stringset) {
1490 case ETH_SS_STATS:
1491 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1492 break;
1493 }
1494}
1495
7282d491 1496static const struct ethtool_ops rtl8169_ethtool_ops = {
1da177e4
LT		 1497 .get_drvinfo = rtl8169_get_drvinfo,
1498 .get_regs_len = rtl8169_get_regs_len,
1499 .get_link = ethtool_op_get_link,
1500 .get_settings = rtl8169_get_settings,
1501 .set_settings = rtl8169_set_settings,
b57b7e5a
SH		 1502 .get_msglevel = rtl8169_get_msglevel,
1503 .set_msglevel = rtl8169_set_msglevel,
1da177e4
LT		 1504 .get_rx_csum = rtl8169_get_rx_csum,
1505 .set_rx_csum = rtl8169_set_rx_csum,
1da177e4 1506 .set_tx_csum = ethtool_op_set_tx_csum,
1da177e4 1507 .set_sg = ethtool_op_set_sg,
1da177e4
LT		 1508 .set_tso = ethtool_op_set_tso,
1509 .get_regs = rtl8169_get_regs,
61a4dcc2
FR		 1510 .get_wol = rtl8169_get_wol,
1511 .set_wol = rtl8169_set_wol,
d4a3a0fc 1512 .get_strings = rtl8169_get_strings,
b9f2c044 1513 .get_sset_count = rtl8169_get_sset_count,
d4a3a0fc 1514 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1da177e4
LT		 1515};
1516
07d3f51f
FR		 1517static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1518 void __iomem *ioaddr)
1da177e4 1519{
0e485150
FR		 1520 /*
1521 * The driver currently handles the 8168Bf and the 8168Be identically
1522 * but they can be identified more specifically through the test below
1523 * if needed:
1524 *
1525 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
0127215c
FR		 1526 *
1527 * Same thing for the 8101Eb and the 8101Ec:
1528 *
1529 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
0e485150 1530 */
350f7596 1531 static const struct {
1da177e4 1532 u32 mask;
e3cf0cc0 1533 u32 val;
1da177e4
LT		 1534 int mac_version;
1535 } mac_info[] = {
5b538df9 1536 /* 8168D family. */
daf9df6d 1537 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1538 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
daf9df6d 1539 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
5b538df9 1540
e6de30d6 1541 /* 8168DP family. */
1542 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1543 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
1544
ef808d50 1545 /* 8168C family. */
17c99297 1546 { 0x7cf00000, 0x3cb00000, RTL_GIGA_MAC_VER_24 },
ef3386f0 1547 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
ef808d50 1548 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
7f3e3d3a 1549 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
e3cf0cc0
FR		 1550 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1551 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
197ff761 1552 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
6fb07058 1553 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
ef808d50 1554 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
e3cf0cc0
FR		 1555
1556 /* 8168B family. */
1557 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1558 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1559 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1560 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1561
1562 /* 8101 family. */
2857ffb7
FR		 1563 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1564 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1565 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1566 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1567 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1568 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
e3cf0cc0 1569 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2857ffb7 1570 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
e3cf0cc0 1571 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2857ffb7
FR		 1572 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1573 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
e3cf0cc0
FR		 1574 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1575 /* FIXME: where did these entries come from ? -- FR */
1576 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1577 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1578
1579 /* 8110 family. */
1580 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1581 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1582 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1583 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1584 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1585 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1586
f21b75e9
JD		 1587 /* Catch-all */
1588 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1da177e4
LT		 1589 }, *p = mac_info;
1590 u32 reg;
1591
e3cf0cc0
FR		 1592 reg = RTL_R32(TxConfig);
1593 while ((reg & p->mask) != p->val)
1da177e4
LT		 1594 p++;
1595 tp->mac_version = p->mac_version;
1596}
1597
1598static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1599{
bcf0bf90 1600 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1da177e4
LT		 1601}
1602
867763c1
FR		 1603struct phy_reg {
1604 u16 reg;
1605 u16 val;
1606};
1607
4da19633 1608static void rtl_writephy_batch(struct rtl8169_private *tp,
1609 const struct phy_reg *regs, int len)
867763c1
FR		 1610{
1611 while (len-- > 0) {
4da19633 1612 rtl_writephy(tp, regs->reg, regs->val);
867763c1
FR		 1613 regs++;
1614 }
1615}
1616
bca03d5f 1617#define PHY_READ 0x00000000
1618#define PHY_DATA_OR 0x10000000
1619#define PHY_DATA_AND 0x20000000
1620#define PHY_BJMPN 0x30000000
1621#define PHY_READ_EFUSE 0x40000000
1622#define PHY_READ_MAC_BYTE 0x50000000
1623#define PHY_WRITE_MAC_BYTE 0x60000000
1624#define PHY_CLEAR_READCOUNT 0x70000000
1625#define PHY_WRITE 0x80000000
1626#define PHY_READCOUNT_EQ_SKIP 0x90000000
1627#define PHY_COMP_EQ_SKIPN 0xa0000000
1628#define PHY_COMP_NEQ_SKIPN 0xb0000000
1629#define PHY_WRITE_PREVIOUS 0xc0000000
1630#define PHY_SKIPN 0xd0000000
1631#define PHY_DELAY_MS 0xe0000000
1632#define PHY_WRITE_ERI_WORD 0xf0000000
1633
1634static void
1635rtl_phy_write_fw(struct rtl8169_private *tp, const struct firmware *fw)
1636{
bca03d5f 1637 __le32 *phytable = (__le32 *)fw->data;
1638 struct net_device *dev = tp->dev;
42b82dc1 1639 size_t index, fw_size = fw->size / sizeof(*phytable);
1640 u32 predata, count;
bca03d5f 1641
1642 if (fw->size % sizeof(*phytable)) {
1643 netif_err(tp, probe, dev, "odd sized firmware %zd\n", fw->size);
1644 return;
1645 }
1646
42b82dc1 1647 for (index = 0; index < fw_size; index++) {
1648 u32 action = le32_to_cpu(phytable[index]);
1649 u32 regno = (action & 0x0fff0000) >> 16;
bca03d5f 1650
42b82dc1 1651 switch(action & 0xf0000000) {
1652 case PHY_READ:
1653 case PHY_DATA_OR:
1654 case PHY_DATA_AND:
1655 case PHY_READ_EFUSE:
1656 case PHY_CLEAR_READCOUNT:
1657 case PHY_WRITE:
1658 case PHY_WRITE_PREVIOUS:
1659 case PHY_DELAY_MS:
1660 break;
1661
1662 case PHY_BJMPN:
1663 if (regno > index) {
1664 netif_err(tp, probe, tp->dev,
1665 "Out of range of firmware\n");
1666 return;
1667 }
1668 break;
1669 case PHY_READCOUNT_EQ_SKIP:
1670 if (index + 2 >= fw_size) {
1671 netif_err(tp, probe, tp->dev,
1672 "Out of range of firmware\n");
1673 return;
1674 }
1675 break;
1676 case PHY_COMP_EQ_SKIPN:
1677 case PHY_COMP_NEQ_SKIPN:
1678 case PHY_SKIPN:
1679 if (index + 1 + regno >= fw_size) {
1680 netif_err(tp, probe, tp->dev,
1681 "Out of range of firmware\n");
1682 return;
1683 }
bca03d5f 1684 break;
1685
42b82dc1 1686 case PHY_READ_MAC_BYTE:
1687 case PHY_WRITE_MAC_BYTE:
1688 case PHY_WRITE_ERI_WORD:
1689 default:
1690 netif_err(tp, probe, tp->dev,
1691 "Invalid action 0x%08x\n", action);
bca03d5f 1692 return;
1693 }
1694 }
1695
42b82dc1 1696 predata = 0;
1697 count = 0;
1698
1699 for (index = 0; index < fw_size; ) {
1700 u32 action = le32_to_cpu(phytable[index]);
bca03d5f 1701 u32 data = action & 0x0000ffff;
42b82dc1 1702 u32 regno = (action & 0x0fff0000) >> 16;
1703
1704 if (!action)
1705 break;
bca03d5f 1706
1707 switch(action & 0xf0000000) {
42b82dc1 1708 case PHY_READ:
1709 predata = rtl_readphy(tp, regno);
1710 count++;
1711 index++;
1712 break;
1713 case PHY_DATA_OR:
1714 predata |= data;
1715 index++;
1716 break;
1717 case PHY_DATA_AND:
1718 predata &= data;
1719 index++;
1720 break;
1721 case PHY_BJMPN:
1722 index -= regno;
1723 break;
1724 case PHY_READ_EFUSE:
1725 predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1726 index++;
1727 break;
1728 case PHY_CLEAR_READCOUNT:
1729 count = 0;
1730 index++;
1731 break;
bca03d5f 1732 case PHY_WRITE:
42b82dc1 1733 rtl_writephy(tp, regno, data);
1734 index++;
1735 break;
1736 case PHY_READCOUNT_EQ_SKIP:
1737 if (count == data)
1738 index += 2;
1739 else
1740 index += 1;
bca03d5f 1741 break;
42b82dc1 1742 case PHY_COMP_EQ_SKIPN:
1743 if (predata == data)
1744 index += regno;
1745 index++;
1746 break;
1747 case PHY_COMP_NEQ_SKIPN:
1748 if (predata != data)
1749 index += regno;
1750 index++;
1751 break;
1752 case PHY_WRITE_PREVIOUS:
1753 rtl_writephy(tp, regno, predata);
1754 index++;
1755 break;
1756 case PHY_SKIPN:
1757 index += regno + 1;
1758 break;
1759 case PHY_DELAY_MS:
1760 mdelay(data);
1761 index++;
1762 break;
1763
1764 case PHY_READ_MAC_BYTE:
1765 case PHY_WRITE_MAC_BYTE:
1766 case PHY_WRITE_ERI_WORD:
bca03d5f 1767 default:
1768 BUG();
1769 }
1770 }
1771}
1772
f1e02ed1 1773static void rtl_release_firmware(struct rtl8169_private *tp)
1774{
1775 release_firmware(tp->fw);
1776 tp->fw = NULL;
1777}
1778
1779static int rtl_apply_firmware(struct rtl8169_private *tp, const char *fw_name)
1780{
1781 const struct firmware **fw = &tp->fw;
1782 int rc = !*fw;
1783
1784 if (rc) {
1785 rc = request_firmware(fw, fw_name, &tp->pci_dev->dev);
1786 if (rc < 0)
1787 goto out;
1788 }
1789
1790 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1791 rtl_phy_write_fw(tp, *fw);
1792out:
1793 return rc;
1794}
1795
4da19633 1796static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
1da177e4 1797{
350f7596 1798 static const struct phy_reg phy_reg_init[] = {
0b9b571d 1799 { 0x1f, 0x0001 },
1800 { 0x06, 0x006e },
1801 { 0x08, 0x0708 },
1802 { 0x15, 0x4000 },
1803 { 0x18, 0x65c7 },
1da177e4 1804
0b9b571d 1805 { 0x1f, 0x0001 },
1806 { 0x03, 0x00a1 },
1807 { 0x02, 0x0008 },
1808 { 0x01, 0x0120 },
1809 { 0x00, 0x1000 },
1810 { 0x04, 0x0800 },
1811 { 0x04, 0x0000 },
1da177e4 1812
0b9b571d 1813 { 0x03, 0xff41 },
1814 { 0x02, 0xdf60 },
1815 { 0x01, 0x0140 },
1816 { 0x00, 0x0077 },
1817 { 0x04, 0x7800 },
1818 { 0x04, 0x7000 },
1819
1820 { 0x03, 0x802f },
1821 { 0x02, 0x4f02 },
1822 { 0x01, 0x0409 },
1823 { 0x00, 0xf0f9 },
1824 { 0x04, 0x9800 },
1825 { 0x04, 0x9000 },
1826
1827 { 0x03, 0xdf01 },
1828 { 0x02, 0xdf20 },
1829 { 0x01, 0xff95 },
1830 { 0x00, 0xba00 },
1831 { 0x04, 0xa800 },
1832 { 0x04, 0xa000 },
1833
1834 { 0x03, 0xff41 },
1835 { 0x02, 0xdf20 },
1836 { 0x01, 0x0140 },
1837 { 0x00, 0x00bb },
1838 { 0x04, 0xb800 },
1839 { 0x04, 0xb000 },
1840
1841 { 0x03, 0xdf41 },
1842 { 0x02, 0xdc60 },
1843 { 0x01, 0x6340 },
1844 { 0x00, 0x007d },
1845 { 0x04, 0xd800 },
1846 { 0x04, 0xd000 },
1847
1848 { 0x03, 0xdf01 },
1849 { 0x02, 0xdf20 },
1850 { 0x01, 0x100a },
1851 { 0x00, 0xa0ff },
1852 { 0x04, 0xf800 },
1853 { 0x04, 0xf000 },
1854
1855 { 0x1f, 0x0000 },
1856 { 0x0b, 0x0000 },
1857 { 0x00, 0x9200 }
1858 };
1da177e4 1859
4da19633 1860 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1da177e4
LT		 1861}
1862
4da19633 1863static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
5615d9f1 1864{
350f7596 1865 static const struct phy_reg phy_reg_init[] = {
a441d7b6
FR		 1866 { 0x1f, 0x0002 },
1867 { 0x01, 0x90d0 },
1868 { 0x1f, 0x0000 }
1869 };
1870
4da19633 1871 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5615d9f1
FR		 1872}
1873
4da19633 1874static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2e955856 1875{
1876 struct pci_dev *pdev = tp->pci_dev;
1877 u16 vendor_id, device_id;
1878
1879 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1880 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1881
1882 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1883 return;
1884
4da19633 1885 rtl_writephy(tp, 0x1f, 0x0001);
1886 rtl_writephy(tp, 0x10, 0xf01b);
1887 rtl_writephy(tp, 0x1f, 0x0000);
2e955856 1888}
1889
4da19633 1890static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2e955856 1891{
350f7596 1892 static const struct phy_reg phy_reg_init[] = {
2e955856 1893 { 0x1f, 0x0001 },
1894 { 0x04, 0x0000 },
1895 { 0x03, 0x00a1 },
1896 { 0x02, 0x0008 },
1897 { 0x01, 0x0120 },
1898 { 0x00, 0x1000 },
1899 { 0x04, 0x0800 },
1900 { 0x04, 0x9000 },
1901 { 0x03, 0x802f },
1902 { 0x02, 0x4f02 },
1903 { 0x01, 0x0409 },
1904 { 0x00, 0xf099 },
1905 { 0x04, 0x9800 },
1906 { 0x04, 0xa000 },
1907 { 0x03, 0xdf01 },
1908 { 0x02, 0xdf20 },
1909 { 0x01, 0xff95 },
1910 { 0x00, 0xba00 },
1911 { 0x04, 0xa800 },
1912 { 0x04, 0xf000 },
1913 { 0x03, 0xdf01 },
1914 { 0x02, 0xdf20 },
1915 { 0x01, 0x101a },
1916 { 0x00, 0xa0ff },
1917 { 0x04, 0xf800 },
1918 { 0x04, 0x0000 },
1919 { 0x1f, 0x0000 },
1920
1921 { 0x1f, 0x0001 },
1922 { 0x10, 0xf41b },
1923 { 0x14, 0xfb54 },
1924 { 0x18, 0xf5c7 },
1925 { 0x1f, 0x0000 },
1926
1927 { 0x1f, 0x0001 },
1928 { 0x17, 0x0cc0 },
1929 { 0x1f, 0x0000 }
1930 };
1931
4da19633 1932 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2e955856 1933
4da19633 1934 rtl8169scd_hw_phy_config_quirk(tp);
2e955856 1935}
1936
4da19633 1937static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
8c7006aa 1938{
350f7596 1939 static const struct phy_reg phy_reg_init[] = {
8c7006aa 1940 { 0x1f, 0x0001 },
1941 { 0x04, 0x0000 },
1942 { 0x03, 0x00a1 },
1943 { 0x02, 0x0008 },
1944 { 0x01, 0x0120 },
1945 { 0x00, 0x1000 },
1946 { 0x04, 0x0800 },
1947 { 0x04, 0x9000 },
1948 { 0x03, 0x802f },
1949 { 0x02, 0x4f02 },
1950 { 0x01, 0x0409 },
1951 { 0x00, 0xf099 },
1952 { 0x04, 0x9800 },
1953 { 0x04, 0xa000 },
1954 { 0x03, 0xdf01 },
1955 { 0x02, 0xdf20 },
1956 { 0x01, 0xff95 },
1957 { 0x00, 0xba00 },
1958 { 0x04, 0xa800 },
1959 { 0x04, 0xf000 },
1960 { 0x03, 0xdf01 },
1961 { 0x02, 0xdf20 },
1962 { 0x01, 0x101a },
1963 { 0x00, 0xa0ff },
1964 { 0x04, 0xf800 },
1965 { 0x04, 0x0000 },
1966 { 0x1f, 0x0000 },
1967
1968 { 0x1f, 0x0001 },
1969 { 0x0b, 0x8480 },
1970 { 0x1f, 0x0000 },
1971
1972 { 0x1f, 0x0001 },
1973 { 0x18, 0x67c7 },
1974 { 0x04, 0x2000 },
1975 { 0x03, 0x002f },
1976 { 0x02, 0x4360 },
1977 { 0x01, 0x0109 },
1978 { 0x00, 0x3022 },
1979 { 0x04, 0x2800 },
1980 { 0x1f, 0x0000 },
1981
1982 { 0x1f, 0x0001 },
1983 { 0x17, 0x0cc0 },
1984 { 0x1f, 0x0000 }
1985 };
1986
4da19633 1987 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
8c7006aa 1988}
1989
4da19633 1990static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
236b8082 1991{
350f7596 1992 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 1993 { 0x10, 0xf41b },
1994 { 0x1f, 0x0000 }
1995 };
1996
4da19633 1997 rtl_writephy(tp, 0x1f, 0x0001);
1998 rtl_patchphy(tp, 0x16, 1 << 0);
236b8082 1999
4da19633 2000 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2001}
2002
4da19633 2003static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
236b8082 2004{
350f7596 2005 static const struct phy_reg phy_reg_init[] = {
236b8082
FR		 2006 { 0x1f, 0x0001 },
2007 { 0x10, 0xf41b },
2008 { 0x1f, 0x0000 }
2009 };
2010
4da19633 2011 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
236b8082
FR		 2012}
2013
4da19633 2014static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2015{
350f7596 2016 static const struct phy_reg phy_reg_init[] = {
867763c1
FR		 2017 { 0x1f, 0x0000 },
2018 { 0x1d, 0x0f00 },
2019 { 0x1f, 0x0002 },
2020 { 0x0c, 0x1ec8 },
2021 { 0x1f, 0x0000 }
2022 };
2023
4da19633 2024 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
867763c1
FR		 2025}
2026
4da19633 2027static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
ef3386f0 2028{
350f7596 2029 static const struct phy_reg phy_reg_init[] = {
ef3386f0
FR		 2030 { 0x1f, 0x0001 },
2031 { 0x1d, 0x3d98 },
2032 { 0x1f, 0x0000 }
2033 };
2034
4da19633 2035 rtl_writephy(tp, 0x1f, 0x0000);
2036 rtl_patchphy(tp, 0x14, 1 << 5);
2037 rtl_patchphy(tp, 0x0d, 1 << 5);
ef3386f0 2038
4da19633 2039 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
ef3386f0
FR		 2040}
2041
4da19633 2042static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
867763c1 2043{
350f7596 2044 static const struct phy_reg phy_reg_init[] = {
a3f80671
FR		 2045 { 0x1f, 0x0001 },
2046 { 0x12, 0x2300 },
867763c1
FR		 2047 { 0x1f, 0x0002 },
2048 { 0x00, 0x88d4 },
2049 { 0x01, 0x82b1 },
2050 { 0x03, 0x7002 },
2051 { 0x08, 0x9e30 },
2052 { 0x09, 0x01f0 },
2053 { 0x0a, 0x5500 },
2054 { 0x0c, 0x00c8 },
2055 { 0x1f, 0x0003 },
2056 { 0x12, 0xc096 },
2057 { 0x16, 0x000a },
f50d4275
FR		 2058 { 0x1f, 0x0000 },
2059 { 0x1f, 0x0000 },
2060 { 0x09, 0x2000 },
2061 { 0x09, 0x0000 }
867763c1
FR		 2062 };
2063
4da19633 2064 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2065
4da19633 2066 rtl_patchphy(tp, 0x14, 1 << 5);
2067 rtl_patchphy(tp, 0x0d, 1 << 5);
2068 rtl_writephy(tp, 0x1f, 0x0000);
867763c1
FR		 2069}
2070
4da19633 2071static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
7da97ec9 2072{
350f7596 2073 static const struct phy_reg phy_reg_init[] = {
f50d4275 2074 { 0x1f, 0x0001 },
7da97ec9 2075 { 0x12, 0x2300 },
f50d4275
FR		 2076 { 0x03, 0x802f },
2077 { 0x02, 0x4f02 },
2078 { 0x01, 0x0409 },
2079 { 0x00, 0xf099 },
2080 { 0x04, 0x9800 },
2081 { 0x04, 0x9000 },
2082 { 0x1d, 0x3d98 },
7da97ec9
FR		 2083 { 0x1f, 0x0002 },
2084 { 0x0c, 0x7eb8 },
f50d4275
FR		 2085 { 0x06, 0x0761 },
2086 { 0x1f, 0x0003 },
2087 { 0x16, 0x0f0a },
7da97ec9
FR		 2088 { 0x1f, 0x0000 }
2089 };
2090
4da19633 2091 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
f50d4275 2092
4da19633 2093 rtl_patchphy(tp, 0x16, 1 << 0);
2094 rtl_patchphy(tp, 0x14, 1 << 5);
2095 rtl_patchphy(tp, 0x0d, 1 << 5);
2096 rtl_writephy(tp, 0x1f, 0x0000);
7da97ec9
FR		 2097}
2098
4da19633 2099static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
197ff761 2100{
350f7596 2101 static const struct phy_reg phy_reg_init[] = {
197ff761
FR		 2102 { 0x1f, 0x0001 },
2103 { 0x12, 0x2300 },
2104 { 0x1d, 0x3d98 },
2105 { 0x1f, 0x0002 },
2106 { 0x0c, 0x7eb8 },
2107 { 0x06, 0x5461 },
2108 { 0x1f, 0x0003 },
2109 { 0x16, 0x0f0a },
2110 { 0x1f, 0x0000 }
2111 };
2112
4da19633 2113 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
197ff761 2114
4da19633 2115 rtl_patchphy(tp, 0x16, 1 << 0);
2116 rtl_patchphy(tp, 0x14, 1 << 5);
2117 rtl_patchphy(tp, 0x0d, 1 << 5);
2118 rtl_writephy(tp, 0x1f, 0x0000);
197ff761
FR		 2119}
2120
4da19633 2121static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
6fb07058 2122{
4da19633 2123 rtl8168c_3_hw_phy_config(tp);
6fb07058
FR		 2124}
2125
bca03d5f 2126static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
5b538df9 2127{
350f7596 2128 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2129 /* Channel Estimation */
5b538df9 2130 { 0x1f, 0x0001 },
daf9df6d 2131 { 0x06, 0x4064 },
2132 { 0x07, 0x2863 },
2133 { 0x08, 0x059c },
2134 { 0x09, 0x26b4 },
2135 { 0x0a, 0x6a19 },
2136 { 0x0b, 0xdcc8 },
2137 { 0x10, 0xf06d },
2138 { 0x14, 0x7f68 },
2139 { 0x18, 0x7fd9 },
2140 { 0x1c, 0xf0ff },
2141 { 0x1d, 0x3d9c },
5b538df9 2142 { 0x1f, 0x0003 },
daf9df6d 2143 { 0x12, 0xf49f },
2144 { 0x13, 0x070b },
2145 { 0x1a, 0x05ad },
bca03d5f 2146 { 0x14, 0x94c0 },
2147
2148 /*
2149 * Tx Error Issue
2150 * enhance line driver power
2151 */
5b538df9 2152 { 0x1f, 0x0002 },
daf9df6d 2153 { 0x06, 0x5561 },
2154 { 0x1f, 0x0005 },
2155 { 0x05, 0x8332 },
bca03d5f 2156 { 0x06, 0x5561 },
2157
2158 /*
2159 * Can not link to 1Gbps with bad cable
2160 * Decrease SNR threshold form 21.07dB to 19.04dB
2161 */
2162 { 0x1f, 0x0001 },
2163 { 0x17, 0x0cc0 },
daf9df6d 2164
5b538df9 2165 { 0x1f, 0x0000 },
bca03d5f 2166 { 0x0d, 0xf880 }
daf9df6d 2167 };
bca03d5f 2168 void __iomem *ioaddr = tp->mmio_addr;
daf9df6d 2169
4da19633 2170 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
daf9df6d 2171
bca03d5f 2172 /*
2173 * Rx Error Issue
2174 * Fine Tune Switching regulator parameter
2175 */
4da19633 2176 rtl_writephy(tp, 0x1f, 0x0002);
2177 rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2178 rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
daf9df6d 2179
daf9df6d 2180 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2181 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2182 { 0x1f, 0x0002 },
2183 { 0x05, 0x669a },
2184 { 0x1f, 0x0005 },
2185 { 0x05, 0x8330 },
2186 { 0x06, 0x669a },
2187 { 0x1f, 0x0002 }
2188 };
2189 int val;
2190
4da19633 2191 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2192
4da19633 2193 val = rtl_readphy(tp, 0x0d);
daf9df6d 2194
2195 if ((val & 0x00ff) != 0x006c) {
350f7596 2196 static const u32 set[] = {
daf9df6d 2197 0x0065, 0x0066, 0x0067, 0x0068,
2198 0x0069, 0x006a, 0x006b, 0x006c
2199 };
2200 int i;
2201
4da19633 2202 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2203
2204 val &= 0xff00;
2205 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2206 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2207 }
2208 } else {
350f7596 2209 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2210 { 0x1f, 0x0002 },
2211 { 0x05, 0x6662 },
2212 { 0x1f, 0x0005 },
2213 { 0x05, 0x8330 },
2214 { 0x06, 0x6662 }
2215 };
2216
4da19633 2217 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2218 }
2219
bca03d5f 2220 /* RSET couple improve */
4da19633 2221 rtl_writephy(tp, 0x1f, 0x0002);
2222 rtl_patchphy(tp, 0x0d, 0x0300);
2223 rtl_patchphy(tp, 0x0f, 0x0010);
daf9df6d 2224
bca03d5f 2225 /* Fine tune PLL performance */
4da19633 2226 rtl_writephy(tp, 0x1f, 0x0002);
2227 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2228 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2229
4da19633 2230 rtl_writephy(tp, 0x1f, 0x0005);
2231 rtl_writephy(tp, 0x05, 0x001b);
f1e02ed1 2232 if ((rtl_readphy(tp, 0x06) != 0xbf00) ||
2233 (rtl_apply_firmware(tp, FIRMWARE_8168D_1) < 0)) {
bca03d5f 2234 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2235 }
2236
4da19633 2237 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2238}
2239
bca03d5f 2240static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2241{
350f7596 2242 static const struct phy_reg phy_reg_init_0[] = {
bca03d5f 2243 /* Channel Estimation */
daf9df6d 2244 { 0x1f, 0x0001 },
2245 { 0x06, 0x4064 },
2246 { 0x07, 0x2863 },
2247 { 0x08, 0x059c },
2248 { 0x09, 0x26b4 },
2249 { 0x0a, 0x6a19 },
2250 { 0x0b, 0xdcc8 },
2251 { 0x10, 0xf06d },
2252 { 0x14, 0x7f68 },
2253 { 0x18, 0x7fd9 },
2254 { 0x1c, 0xf0ff },
2255 { 0x1d, 0x3d9c },
2256 { 0x1f, 0x0003 },
2257 { 0x12, 0xf49f },
2258 { 0x13, 0x070b },
2259 { 0x1a, 0x05ad },
2260 { 0x14, 0x94c0 },
2261
bca03d5f 2262 /*
2263 * Tx Error Issue
2264 * enhance line driver power
2265 */
daf9df6d 2266 { 0x1f, 0x0002 },
2267 { 0x06, 0x5561 },
2268 { 0x1f, 0x0005 },
2269 { 0x05, 0x8332 },
bca03d5f 2270 { 0x06, 0x5561 },
2271
2272 /*
2273 * Can not link to 1Gbps with bad cable
2274 * Decrease SNR threshold form 21.07dB to 19.04dB
2275 */
2276 { 0x1f, 0x0001 },
2277 { 0x17, 0x0cc0 },
daf9df6d 2278
2279 { 0x1f, 0x0000 },
bca03d5f 2280 { 0x0d, 0xf880 }
5b538df9 2281 };
bca03d5f 2282 void __iomem *ioaddr = tp->mmio_addr;
5b538df9 2283
4da19633 2284 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
5b538df9 2285
daf9df6d 2286 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
350f7596 2287 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2288 { 0x1f, 0x0002 },
2289 { 0x05, 0x669a },
5b538df9 2290 { 0x1f, 0x0005 },
daf9df6d 2291 { 0x05, 0x8330 },
2292 { 0x06, 0x669a },
2293
2294 { 0x1f, 0x0002 }
2295 };
2296 int val;
2297
4da19633 2298 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
daf9df6d 2299
4da19633 2300 val = rtl_readphy(tp, 0x0d);
daf9df6d 2301 if ((val & 0x00ff) != 0x006c) {
b6bc7650 2302 static const u32 set[] = {
daf9df6d 2303 0x0065, 0x0066, 0x0067, 0x0068,
2304 0x0069, 0x006a, 0x006b, 0x006c
2305 };
2306 int i;
2307
4da19633 2308 rtl_writephy(tp, 0x1f, 0x0002);
daf9df6d 2309
2310 val &= 0xff00;
2311 for (i = 0; i < ARRAY_SIZE(set); i++)
4da19633 2312 rtl_writephy(tp, 0x0d, val | set[i]);
daf9df6d 2313 }
2314 } else {
350f7596 2315 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2316 { 0x1f, 0x0002 },
2317 { 0x05, 0x2642 },
5b538df9 2318 { 0x1f, 0x0005 },
daf9df6d 2319 { 0x05, 0x8330 },
2320 { 0x06, 0x2642 }
5b538df9
FR		 2321 };
2322
4da19633 2323 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2324 }
2325
bca03d5f 2326 /* Fine tune PLL performance */
4da19633 2327 rtl_writephy(tp, 0x1f, 0x0002);
2328 rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2329 rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
daf9df6d 2330
bca03d5f 2331 /* Switching regulator Slew rate */
4da19633 2332 rtl_writephy(tp, 0x1f, 0x0002);
2333 rtl_patchphy(tp, 0x0f, 0x0017);
daf9df6d 2334
4da19633 2335 rtl_writephy(tp, 0x1f, 0x0005);
2336 rtl_writephy(tp, 0x05, 0x001b);
f1e02ed1 2337 if ((rtl_readphy(tp, 0x06) != 0xb300) ||
2338 (rtl_apply_firmware(tp, FIRMWARE_8168D_2) < 0)) {
bca03d5f 2339 netif_warn(tp, probe, tp->dev, "unable to apply firmware patch\n");
2340 }
2341
4da19633 2342 rtl_writephy(tp, 0x1f, 0x0000);
daf9df6d 2343}
2344
4da19633 2345static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
daf9df6d 2346{
350f7596 2347 static const struct phy_reg phy_reg_init[] = {
daf9df6d 2348 { 0x1f, 0x0002 },
2349 { 0x10, 0x0008 },
2350 { 0x0d, 0x006c },
2351
2352 { 0x1f, 0x0000 },
2353 { 0x0d, 0xf880 },
2354
2355 { 0x1f, 0x0001 },
2356 { 0x17, 0x0cc0 },
2357
2358 { 0x1f, 0x0001 },
2359 { 0x0b, 0xa4d8 },
2360 { 0x09, 0x281c },
2361 { 0x07, 0x2883 },
2362 { 0x0a, 0x6b35 },
2363 { 0x1d, 0x3da4 },
2364 { 0x1c, 0xeffd },
2365 { 0x14, 0x7f52 },
2366 { 0x18, 0x7fc6 },
2367 { 0x08, 0x0601 },
2368 { 0x06, 0x4063 },
2369 { 0x10, 0xf074 },
2370 { 0x1f, 0x0003 },
2371 { 0x13, 0x0789 },
2372 { 0x12, 0xf4bd },
2373 { 0x1a, 0x04fd },
2374 { 0x14, 0x84b0 },
2375 { 0x1f, 0x0000 },
2376 { 0x00, 0x9200 },
2377
2378 { 0x1f, 0x0005 },
2379 { 0x01, 0x0340 },
2380 { 0x1f, 0x0001 },
2381 { 0x04, 0x4000 },
2382 { 0x03, 0x1d21 },
2383 { 0x02, 0x0c32 },
2384 { 0x01, 0x0200 },
2385 { 0x00, 0x5554 },
2386 { 0x04, 0x4800 },
2387 { 0x04, 0x4000 },
2388 { 0x04, 0xf000 },
2389 { 0x03, 0xdf01 },
2390 { 0x02, 0xdf20 },
2391 { 0x01, 0x101a },
2392 { 0x00, 0xa0ff },
2393 { 0x04, 0xf800 },
2394 { 0x04, 0xf000 },
2395 { 0x1f, 0x0000 },
2396
2397 { 0x1f, 0x0007 },
2398 { 0x1e, 0x0023 },
2399 { 0x16, 0x0000 },
2400 { 0x1f, 0x0000 }
2401 };
2402
4da19633 2403 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
5b538df9
FR		 2404}
2405
e6de30d6 2406static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2407{
2408 static const struct phy_reg phy_reg_init[] = {
2409 { 0x1f, 0x0001 },
2410 { 0x17, 0x0cc0 },
2411
2412 { 0x1f, 0x0007 },
2413 { 0x1e, 0x002d },
2414 { 0x18, 0x0040 },
2415 { 0x1f, 0x0000 }
2416 };
2417
2418 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2419 rtl_patchphy(tp, 0x0d, 1 << 5);
2420}
2421
4da19633 2422static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2857ffb7 2423{
350f7596 2424 static const struct phy_reg phy_reg_init[] = {
2857ffb7
FR		 2425 { 0x1f, 0x0003 },
2426 { 0x08, 0x441d },
2427 { 0x01, 0x9100 },
2428 { 0x1f, 0x0000 }
2429 };
2430
4da19633 2431 rtl_writephy(tp, 0x1f, 0x0000);
2432 rtl_patchphy(tp, 0x11, 1 << 12);
2433 rtl_patchphy(tp, 0x19, 1 << 13);
2434 rtl_patchphy(tp, 0x10, 1 << 15);
2857ffb7 2435
4da19633 2436 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2857ffb7
FR		 2437}
2438
5615d9f1
FR		 2439static void rtl_hw_phy_config(struct net_device *dev)
2440{
2441 struct rtl8169_private *tp = netdev_priv(dev);
5615d9f1
FR		 2442
2443 rtl8169_print_mac_version(tp);
2444
2445 switch (tp->mac_version) {
2446 case RTL_GIGA_MAC_VER_01:
2447 break;
2448 case RTL_GIGA_MAC_VER_02:
2449 case RTL_GIGA_MAC_VER_03:
4da19633 2450 rtl8169s_hw_phy_config(tp);
5615d9f1
FR		 2451 break;
2452 case RTL_GIGA_MAC_VER_04:
4da19633 2453 rtl8169sb_hw_phy_config(tp);
5615d9f1 2454 break;
2e955856 2455 case RTL_GIGA_MAC_VER_05:
4da19633 2456 rtl8169scd_hw_phy_config(tp);
2e955856 2457 break;
8c7006aa 2458 case RTL_GIGA_MAC_VER_06:
4da19633 2459 rtl8169sce_hw_phy_config(tp);
8c7006aa 2460 break;
2857ffb7
FR		 2461 case RTL_GIGA_MAC_VER_07:
2462 case RTL_GIGA_MAC_VER_08:
2463 case RTL_GIGA_MAC_VER_09:
4da19633 2464 rtl8102e_hw_phy_config(tp);
2857ffb7 2465 break;
236b8082 2466 case RTL_GIGA_MAC_VER_11:
4da19633 2467 rtl8168bb_hw_phy_config(tp);
236b8082
FR		 2468 break;
2469 case RTL_GIGA_MAC_VER_12:
4da19633 2470 rtl8168bef_hw_phy_config(tp);
236b8082
FR		 2471 break;
2472 case RTL_GIGA_MAC_VER_17:
4da19633 2473 rtl8168bef_hw_phy_config(tp);
236b8082 2474 break;
867763c1 2475 case RTL_GIGA_MAC_VER_18:
4da19633 2476 rtl8168cp_1_hw_phy_config(tp);
867763c1
FR		 2477 break;
2478 case RTL_GIGA_MAC_VER_19:
4da19633 2479 rtl8168c_1_hw_phy_config(tp);
867763c1 2480 break;
7da97ec9 2481 case RTL_GIGA_MAC_VER_20:
4da19633 2482 rtl8168c_2_hw_phy_config(tp);
7da97ec9 2483 break;
197ff761 2484 case RTL_GIGA_MAC_VER_21:
4da19633 2485 rtl8168c_3_hw_phy_config(tp);
197ff761 2486 break;
6fb07058 2487 case RTL_GIGA_MAC_VER_22:
4da19633 2488 rtl8168c_4_hw_phy_config(tp);
6fb07058 2489 break;
ef3386f0 2490 case RTL_GIGA_MAC_VER_23:
7f3e3d3a 2491 case RTL_GIGA_MAC_VER_24:
4da19633 2492 rtl8168cp_2_hw_phy_config(tp);
ef3386f0 2493 break;
5b538df9 2494 case RTL_GIGA_MAC_VER_25:
bca03d5f 2495 rtl8168d_1_hw_phy_config(tp);
daf9df6d 2496 break;
2497 case RTL_GIGA_MAC_VER_26:
bca03d5f 2498 rtl8168d_2_hw_phy_config(tp);
daf9df6d 2499 break;
2500 case RTL_GIGA_MAC_VER_27:
4da19633 2501 rtl8168d_3_hw_phy_config(tp);
5b538df9 2502 break;
e6de30d6 2503 case RTL_GIGA_MAC_VER_28:
2504 rtl8168d_4_hw_phy_config(tp);
2505 break;
ef3386f0 2506
5615d9f1
FR		 2507 default:
2508 break;
2509 }
2510}
2511
1da177e4
LT		 2512static void rtl8169_phy_timer(unsigned long __opaque)
2513{
2514 struct net_device *dev = (struct net_device *)__opaque;
2515 struct rtl8169_private *tp = netdev_priv(dev);
2516 struct timer_list *timer = &tp->timer;
2517 void __iomem *ioaddr = tp->mmio_addr;
2518 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2519
bcf0bf90 2520 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1da177e4 2521
64e4bfb4 2522 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1da177e4
LT		 2523 return;
2524
2525 spin_lock_irq(&tp->lock);
2526
4da19633 2527 if (tp->phy_reset_pending(tp)) {
5b0384f4 2528 /*
1da177e4
LT		 2529 * A busy loop could burn quite a few cycles on nowadays CPU.
2530 * Let's delay the execution of the timer for a few ticks.
2531 */
2532 timeout = HZ/10;
2533 goto out_mod_timer;
2534 }
2535
2536 if (tp->link_ok(ioaddr))
2537 goto out_unlock;
2538
bf82c189 2539 netif_warn(tp, link, dev, "PHY reset until link up\n");
1da177e4 2540
4da19633 2541 tp->phy_reset_enable(tp);
1da177e4
LT		 2542
2543out_mod_timer:
2544 mod_timer(timer, jiffies + timeout);
2545out_unlock:
2546 spin_unlock_irq(&tp->lock);
2547}
2548
2549static inline void rtl8169_delete_timer(struct net_device *dev)
2550{
2551 struct rtl8169_private *tp = netdev_priv(dev);
2552 struct timer_list *timer = &tp->timer;
2553
e179bb7b 2554 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2555 return;
2556
2557 del_timer_sync(timer);
2558}
2559
2560static inline void rtl8169_request_timer(struct net_device *dev)
2561{
2562 struct rtl8169_private *tp = netdev_priv(dev);
2563 struct timer_list *timer = &tp->timer;
2564
e179bb7b 2565 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1da177e4
LT		 2566 return;
2567
2efa53f3 2568 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1da177e4
LT		 2569}
2570
2571#ifdef CONFIG_NET_POLL_CONTROLLER
2572/*
2573 * Polling 'interrupt' - used by things like netconsole to send skbs
2574 * without having to re-enable interrupts. It's not called while
2575 * the interrupt routine is executing.
2576 */
2577static void rtl8169_netpoll(struct net_device *dev)
2578{
2579 struct rtl8169_private *tp = netdev_priv(dev);
2580 struct pci_dev *pdev = tp->pci_dev;
2581
2582 disable_irq(pdev->irq);
7d12e780 2583 rtl8169_interrupt(pdev->irq, dev);
1da177e4
LT		 2584 enable_irq(pdev->irq);
2585}
2586#endif
2587
2588static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2589 void __iomem *ioaddr)
2590{
2591 iounmap(ioaddr);
2592 pci_release_regions(pdev);
87aeec76 2593 pci_clear_mwi(pdev);
1da177e4
LT		 2594 pci_disable_device(pdev);
2595 free_netdev(dev);
2596}
2597
bf793295
FR		 2598static void rtl8169_phy_reset(struct net_device *dev,
2599 struct rtl8169_private *tp)
2600{
07d3f51f 2601 unsigned int i;
bf793295 2602
4da19633 2603 tp->phy_reset_enable(tp);
bf793295 2604 for (i = 0; i < 100; i++) {
4da19633 2605 if (!tp->phy_reset_pending(tp))
bf793295
FR		 2606 return;
2607 msleep(1);
2608 }
bf82c189 2609 netif_err(tp, link, dev, "PHY reset failed\n");
bf793295
FR		 2610}
2611
4ff96fa6
FR		 2612static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2613{
2614 void __iomem *ioaddr = tp->mmio_addr;
4ff96fa6 2615
5615d9f1 2616 rtl_hw_phy_config(dev);
4ff96fa6 2617
77332894
MS		 2618 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2619 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2620 RTL_W8(0x82, 0x01);
2621 }
4ff96fa6 2622
6dccd16b
FR		 2623 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2624
2625 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2626 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4ff96fa6 2627
bcf0bf90 2628 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4ff96fa6
FR		 2629 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2630 RTL_W8(0x82, 0x01);
2631 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
4da19633 2632 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4ff96fa6
FR		 2633 }
2634
bf793295
FR		 2635 rtl8169_phy_reset(dev, tp);
2636
901dda2b
FR		 2637 /*
2638 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2639 * only 8101. Don't panic.
2640 */
2641 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
4ff96fa6 2642
bf82c189
JP		 2643 if (RTL_R8(PHYstatus) & TBI_Enable)
2644 netif_info(tp, link, dev, "TBI auto-negotiating\n");
4ff96fa6
FR		 2645}
2646
773d2021
FR		 2647static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2648{
2649 void __iomem *ioaddr = tp->mmio_addr;
2650 u32 high;
2651 u32 low;
2652
2653 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2654 high = addr[4] | (addr[5] << 8);
2655
2656 spin_lock_irq(&tp->lock);
2657
2658 RTL_W8(Cfg9346, Cfg9346_Unlock);
908ba2bf 2659
773d2021 2660 RTL_W32(MAC4, high);
908ba2bf 2661 RTL_R32(MAC4);
2662
78f1cd02 2663 RTL_W32(MAC0, low);
908ba2bf 2664 RTL_R32(MAC0);
2665
773d2021
FR		 2666 RTL_W8(Cfg9346, Cfg9346_Lock);
2667
2668 spin_unlock_irq(&tp->lock);
2669}
2670
2671static int rtl_set_mac_address(struct net_device *dev, void *p)
2672{
2673 struct rtl8169_private *tp = netdev_priv(dev);
2674 struct sockaddr *addr = p;
2675
2676 if (!is_valid_ether_addr(addr->sa_data))
2677 return -EADDRNOTAVAIL;
2678
2679 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2680
2681 rtl_rar_set(tp, dev->dev_addr);
2682
2683 return 0;
2684}
2685
5f787a1a
FR		 2686static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2687{
2688 struct rtl8169_private *tp = netdev_priv(dev);
2689 struct mii_ioctl_data *data = if_mii(ifr);
2690
8b4ab28d
FR		 2691 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2692}
5f787a1a 2693
8b4ab28d
FR		 2694static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2695{
5f787a1a
FR		 2696 switch (cmd) {
2697 case SIOCGMIIPHY:
2698 data->phy_id = 32; /* Internal PHY */
2699 return 0;
2700
2701 case SIOCGMIIREG:
4da19633 2702 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
5f787a1a
FR		 2703 return 0;
2704
2705 case SIOCSMIIREG:
4da19633 2706 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
5f787a1a
FR		 2707 return 0;
2708 }
2709 return -EOPNOTSUPP;
2710}
2711
8b4ab28d
FR		 2712static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2713{
2714 return -EOPNOTSUPP;
2715}
2716
0e485150
FR		 2717static const struct rtl_cfg_info {
2718 void (*hw_start)(struct net_device *);
2719 unsigned int region;
2720 unsigned int align;
2721 u16 intr_event;
2722 u16 napi_event;
ccdffb9a 2723 unsigned features;
f21b75e9 2724 u8 default_ver;
0e485150
FR		 2725} rtl_cfg_infos [] = {
2726 [RTL_CFG_0] = {
2727 .hw_start = rtl_hw_start_8169,
2728 .region = 1,
e9f63f30 2729 .align = 0,
0e485150
FR		 2730 .intr_event = SYSErr | LinkChg | RxOverflow |
2731 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2732 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2733 .features = RTL_FEATURE_GMII,
2734 .default_ver = RTL_GIGA_MAC_VER_01,
0e485150
FR		 2735 },
2736 [RTL_CFG_1] = {
2737 .hw_start = rtl_hw_start_8168,
2738 .region = 2,
2739 .align = 8,
53f57357 2740 .intr_event = SYSErr | LinkChg | RxOverflow |
0e485150 2741 TxErr | TxOK | RxOK | RxErr,
fbac58fc 2742 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2743 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2744 .default_ver = RTL_GIGA_MAC_VER_11,
0e485150
FR		 2745 },
2746 [RTL_CFG_2] = {
2747 .hw_start = rtl_hw_start_8101,
2748 .region = 2,
2749 .align = 8,
2750 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2751 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
fbac58fc 2752 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
f21b75e9
JD		 2753 .features = RTL_FEATURE_MSI,
2754 .default_ver = RTL_GIGA_MAC_VER_13,
0e485150
FR		 2755 }
2756};
2757
fbac58fc
FR		 2758/* Cfg9346_Unlock assumed. */
2759static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2760 const struct rtl_cfg_info *cfg)
2761{
2762 unsigned msi = 0;
2763 u8 cfg2;
2764
2765 cfg2 = RTL_R8(Config2) & ~MSIEnable;
ccdffb9a 2766 if (cfg->features & RTL_FEATURE_MSI) {
fbac58fc
FR		 2767 if (pci_enable_msi(pdev)) {
2768 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2769 } else {
2770 cfg2 |= MSIEnable;
2771 msi = RTL_FEATURE_MSI;
2772 }
2773 }
2774 RTL_W8(Config2, cfg2);
2775 return msi;
2776}
2777
2778static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2779{
2780 if (tp->features & RTL_FEATURE_MSI) {
2781 pci_disable_msi(pdev);
2782 tp->features &= ~RTL_FEATURE_MSI;
2783 }
2784}
2785
8b4ab28d
FR		 2786static const struct net_device_ops rtl8169_netdev_ops = {
2787 .ndo_open = rtl8169_open,
2788 .ndo_stop = rtl8169_close,
2789 .ndo_get_stats = rtl8169_get_stats,
00829823 2790 .ndo_start_xmit = rtl8169_start_xmit,
8b4ab28d
FR		 2791 .ndo_tx_timeout = rtl8169_tx_timeout,
2792 .ndo_validate_addr = eth_validate_addr,
2793 .ndo_change_mtu = rtl8169_change_mtu,
2794 .ndo_set_mac_address = rtl_set_mac_address,
2795 .ndo_do_ioctl = rtl8169_ioctl,
2796 .ndo_set_multicast_list = rtl_set_rx_mode,
2797#ifdef CONFIG_R8169_VLAN
2798 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2799#endif
2800#ifdef CONFIG_NET_POLL_CONTROLLER
2801 .ndo_poll_controller = rtl8169_netpoll,
2802#endif
2803
2804};
2805
c0e45c1c 2806static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
2807{
2808 struct mdio_ops *ops = &tp->mdio_ops;
2809
2810 switch (tp->mac_version) {
2811 case RTL_GIGA_MAC_VER_27:
2812 ops->write = r8168dp_1_mdio_write;
2813 ops->read = r8168dp_1_mdio_read;
2814 break;
e6de30d6 2815 case RTL_GIGA_MAC_VER_28:
2816 ops->write = r8168dp_2_mdio_write;
2817 ops->read = r8168dp_2_mdio_read;
2818 break;
c0e45c1c 2819 default:
2820 ops->write = r8169_mdio_write;
2821 ops->read = r8169_mdio_read;
2822 break;
2823 }
2824}
2825
065c27c1 2826static void r810x_phy_power_down(struct rtl8169_private *tp)
2827{
2828 rtl_writephy(tp, 0x1f, 0x0000);
2829 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2830}
2831
2832static void r810x_phy_power_up(struct rtl8169_private *tp)
2833{
2834 rtl_writephy(tp, 0x1f, 0x0000);
2835 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2836}
2837
2838static void r810x_pll_power_down(struct rtl8169_private *tp)
2839{
2840 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2841 rtl_writephy(tp, 0x1f, 0x0000);
2842 rtl_writephy(tp, MII_BMCR, 0x0000);
2843 return;
2844 }
2845
2846 r810x_phy_power_down(tp);
2847}
2848
2849static void r810x_pll_power_up(struct rtl8169_private *tp)
2850{
2851 r810x_phy_power_up(tp);
2852}
2853
2854static void r8168_phy_power_up(struct rtl8169_private *tp)
2855{
2856 rtl_writephy(tp, 0x1f, 0x0000);
2857 rtl_writephy(tp, 0x0e, 0x0000);
2858 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
2859}
2860
2861static void r8168_phy_power_down(struct rtl8169_private *tp)
2862{
2863 rtl_writephy(tp, 0x1f, 0x0000);
2864 rtl_writephy(tp, 0x0e, 0x0200);
2865 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
2866}
2867
2868static void r8168_pll_power_down(struct rtl8169_private *tp)
2869{
2870 void __iomem *ioaddr = tp->mmio_addr;
2871
2872 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2873 return;
2874
2875 if (((tp->mac_version == RTL_GIGA_MAC_VER_23) ||
2876 (tp->mac_version == RTL_GIGA_MAC_VER_24)) &&
2877 (RTL_R16(CPlusCmd) & ASF)) {
2878 return;
2879 }
2880
2881 if (__rtl8169_get_wol(tp) & WAKE_ANY) {
2882 rtl_writephy(tp, 0x1f, 0x0000);
2883 rtl_writephy(tp, MII_BMCR, 0x0000);
2884
2885 RTL_W32(RxConfig, RTL_R32(RxConfig) |
2886 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
2887 return;
2888 }
2889
2890 r8168_phy_power_down(tp);
2891
2892 switch (tp->mac_version) {
2893 case RTL_GIGA_MAC_VER_25:
2894 case RTL_GIGA_MAC_VER_26:
2895 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
2896 break;
2897 }
2898}
2899
2900static void r8168_pll_power_up(struct rtl8169_private *tp)
2901{
2902 void __iomem *ioaddr = tp->mmio_addr;
2903
2904 if (tp->mac_version == RTL_GIGA_MAC_VER_27)
2905 return;
2906
2907 switch (tp->mac_version) {
2908 case RTL_GIGA_MAC_VER_25:
2909 case RTL_GIGA_MAC_VER_26:
2910 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
2911 break;
2912 }
2913
2914 r8168_phy_power_up(tp);
2915}
2916
2917static void rtl_pll_power_op(struct rtl8169_private *tp,
2918 void (*op)(struct rtl8169_private *))
2919{
2920 if (op)
2921 op(tp);
2922}
2923
2924static void rtl_pll_power_down(struct rtl8169_private *tp)
2925{
2926 rtl_pll_power_op(tp, tp->pll_power_ops.down);
2927}
2928
2929static void rtl_pll_power_up(struct rtl8169_private *tp)
2930{
2931 rtl_pll_power_op(tp, tp->pll_power_ops.up);
2932}
2933
2934static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
2935{
2936 struct pll_power_ops *ops = &tp->pll_power_ops;
2937
2938 switch (tp->mac_version) {
2939 case RTL_GIGA_MAC_VER_07:
2940 case RTL_GIGA_MAC_VER_08:
2941 case RTL_GIGA_MAC_VER_09:
2942 case RTL_GIGA_MAC_VER_10:
2943 case RTL_GIGA_MAC_VER_16:
2944 ops->down = r810x_pll_power_down;
2945 ops->up = r810x_pll_power_up;
2946 break;
2947
2948 case RTL_GIGA_MAC_VER_11:
2949 case RTL_GIGA_MAC_VER_12:
2950 case RTL_GIGA_MAC_VER_17:
2951 case RTL_GIGA_MAC_VER_18:
2952 case RTL_GIGA_MAC_VER_19:
2953 case RTL_GIGA_MAC_VER_20:
2954 case RTL_GIGA_MAC_VER_21:
2955 case RTL_GIGA_MAC_VER_22:
2956 case RTL_GIGA_MAC_VER_23:
2957 case RTL_GIGA_MAC_VER_24:
2958 case RTL_GIGA_MAC_VER_25:
2959 case RTL_GIGA_MAC_VER_26:
2960 case RTL_GIGA_MAC_VER_27:
e6de30d6 2961 case RTL_GIGA_MAC_VER_28:
065c27c1 2962 ops->down = r8168_pll_power_down;
2963 ops->up = r8168_pll_power_up;
2964 break;
2965
2966 default:
2967 ops->down = NULL;
2968 ops->up = NULL;
2969 break;
2970 }
2971}
2972
1da177e4 2973static int __devinit
4ff96fa6 2974rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1da177e4 2975{
0e485150
FR		 2976 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2977 const unsigned int region = cfg->region;
1da177e4 2978 struct rtl8169_private *tp;
ccdffb9a 2979 struct mii_if_info *mii;
4ff96fa6
FR		 2980 struct net_device *dev;
2981 void __iomem *ioaddr;
07d3f51f
FR		 2982 unsigned int i;
2983 int rc;
1da177e4 2984
4ff96fa6
FR		 2985 if (netif_msg_drv(&debug)) {
2986 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
2987 MODULENAME, RTL8169_VERSION);
2988 }
1da177e4 2989
1da177e4 2990 dev = alloc_etherdev(sizeof (*tp));
4ff96fa6 2991 if (!dev) {
b57b7e5a 2992 if (netif_msg_drv(&debug))
9b91cf9d 2993 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
4ff96fa6
FR		 2994 rc = -ENOMEM;
2995 goto out;
1da177e4
LT		 2996 }
2997
1da177e4 2998 SET_NETDEV_DEV(dev, &pdev->dev);
8b4ab28d 2999 dev->netdev_ops = &rtl8169_netdev_ops;
1da177e4 3000 tp = netdev_priv(dev);
c4028958 3001 tp->dev = dev;
21e197f2 3002 tp->pci_dev = pdev;
b57b7e5a 3003 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1da177e4 3004
ccdffb9a
FR		 3005 mii = &tp->mii;
3006 mii->dev = dev;
3007 mii->mdio_read = rtl_mdio_read;
3008 mii->mdio_write = rtl_mdio_write;
3009 mii->phy_id_mask = 0x1f;
3010 mii->reg_num_mask = 0x1f;
3011 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3012
1da177e4
LT		 3013 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3014 rc = pci_enable_device(pdev);
b57b7e5a 3015 if (rc < 0) {
bf82c189 3016 netif_err(tp, probe, dev, "enable failure\n");
4ff96fa6 3017 goto err_out_free_dev_1;
1da177e4
LT		 3018 }
3019
87aeec76 3020 if (pci_set_mwi(pdev) < 0)
3021 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
1da177e4 3022
1da177e4 3023 /* make sure PCI base addr 1 is MMIO */
bcf0bf90 3024 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
bf82c189
JP		 3025 netif_err(tp, probe, dev,
3026 "region #%d not an MMIO resource, aborting\n",
3027 region);
1da177e4 3028 rc = -ENODEV;
87aeec76 3029 goto err_out_mwi_2;
1da177e4 3030 }
4ff96fa6 3031
1da177e4 3032 /* check for weird/broken PCI region reporting */
bcf0bf90 3033 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
bf82c189
JP		 3034 netif_err(tp, probe, dev,
3035 "Invalid PCI region size(s), aborting\n");
1da177e4 3036 rc = -ENODEV;
87aeec76 3037 goto err_out_mwi_2;
1da177e4
LT		 3038 }
3039
3040 rc = pci_request_regions(pdev, MODULENAME);
b57b7e5a 3041 if (rc < 0) {
bf82c189 3042 netif_err(tp, probe, dev, "could not request regions\n");
87aeec76 3043 goto err_out_mwi_2;
1da177e4
LT		 3044 }
3045
3046 tp->cp_cmd = PCIMulRW | RxChkSum;
3047
3048 if ((sizeof(dma_addr_t) > 4) &&
4300e8c7 3049 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
1da177e4
LT		 3050 tp->cp_cmd |= PCIDAC;
3051 dev->features |= NETIF_F_HIGHDMA;
3052 } else {
284901a9 3053 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1da177e4 3054 if (rc < 0) {
bf82c189 3055 netif_err(tp, probe, dev, "DMA configuration failed\n");
87aeec76 3056 goto err_out_free_res_3;
1da177e4
LT		 3057 }
3058 }
3059
1da177e4 3060 /* ioremap MMIO region */
bcf0bf90 3061 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
4ff96fa6 3062 if (!ioaddr) {
bf82c189 3063 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
1da177e4 3064 rc = -EIO;
87aeec76 3065 goto err_out_free_res_3;
1da177e4
LT		 3066 }
3067
4300e8c7
DM		 3068 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3069 if (!tp->pcie_cap)
3070 netif_info(tp, probe, dev, "no PCI Express capability\n");
3071
d78ad8cb 3072 RTL_W16(IntrMask, 0x0000);
1da177e4
LT		 3073
3074 /* Soft reset the chip. */
3075 RTL_W8(ChipCmd, CmdReset);
3076
3077 /* Check that the chip has finished the reset. */
07d3f51f 3078 for (i = 0; i < 100; i++) {
1da177e4
LT		 3079 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3080 break;
b518fa8e 3081 msleep_interruptible(1);
1da177e4
LT		 3082 }
3083
d78ad8cb
KW		 3084 RTL_W16(IntrStatus, 0xffff);
3085
ca52efd5 3086 pci_set_master(pdev);
3087
1da177e4
LT		 3088 /* Identify chip attached to board */
3089 rtl8169_get_mac_version(tp, ioaddr);
1da177e4 3090
c0e45c1c 3091 rtl_init_mdio_ops(tp);
065c27c1 3092 rtl_init_pll_power_ops(tp);
c0e45c1c 3093
f21b75e9
JD		 3094 /* Use appropriate default if unknown */
3095 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
bf82c189
JP		 3096 netif_notice(tp, probe, dev,
3097 "unknown MAC, using family default\n");
f21b75e9
JD		 3098 tp->mac_version = cfg->default_ver;
3099 }
3100
1da177e4 3101 rtl8169_print_mac_version(tp);
1da177e4 3102
cee60c37 3103 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
1da177e4
LT		 3104 if (tp->mac_version == rtl_chip_info[i].mac_version)
3105 break;
3106 }
cee60c37 3107 if (i == ARRAY_SIZE(rtl_chip_info)) {
f21b75e9
JD		 3108 dev_err(&pdev->dev,
3109 "driver bug, MAC version not found in rtl_chip_info\n");
87aeec76 3110 goto err_out_msi_4;
1da177e4
LT		 3111 }
3112 tp->chipset = i;
3113
5d06a99f
FR		 3114 RTL_W8(Cfg9346, Cfg9346_Unlock);
3115 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3116 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
20037fa4
BP		 3117 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3118 tp->features |= RTL_FEATURE_WOL;
3119 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3120 tp->features |= RTL_FEATURE_WOL;
fbac58fc 3121 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
5d06a99f
FR		 3122 RTL_W8(Cfg9346, Cfg9346_Lock);
3123
66ec5d4f
FR		 3124 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3125 (RTL_R8(PHYstatus) & TBI_Enable)) {
1da177e4
LT		 3126 tp->set_speed = rtl8169_set_speed_tbi;
3127 tp->get_settings = rtl8169_gset_tbi;
3128 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3129 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3130 tp->link_ok = rtl8169_tbi_link_ok;
8b4ab28d 3131 tp->do_ioctl = rtl_tbi_ioctl;
1da177e4 3132
64e4bfb4 3133 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
1da177e4
LT		 3134 } else {
3135 tp->set_speed = rtl8169_set_speed_xmii;
3136 tp->get_settings = rtl8169_gset_xmii;
3137 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3138 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3139 tp->link_ok = rtl8169_xmii_link_ok;
8b4ab28d 3140 tp->do_ioctl = rtl_xmii_ioctl;
1da177e4
LT		 3141 }
3142
df58ef51
FR		 3143 spin_lock_init(&tp->lock);
3144
738e1e69
PV		 3145 tp->mmio_addr = ioaddr;
3146
7bf6bf48 3147 /* Get MAC address */
1da177e4
LT		 3148 for (i = 0; i < MAC_ADDR_LEN; i++)
3149 dev->dev_addr[i] = RTL_R8(MAC0 + i);
6d6525b7 3150 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1da177e4 3151
1da177e4 3152 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1da177e4
LT		 3153 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3154 dev->irq = pdev->irq;
3155 dev->base_addr = (unsigned long) ioaddr;
1da177e4 3156
bea3348e 3157 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
1da177e4
LT		 3158
3159#ifdef CONFIG_R8169_VLAN
3160 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1da177e4 3161#endif
2edae08e 3162 dev->features |= NETIF_F_GRO;
1da177e4
LT		 3163
3164 tp->intr_mask = 0xffff;
0e485150
FR		 3165 tp->hw_start = cfg->hw_start;
3166 tp->intr_event = cfg->intr_event;
3167 tp->napi_event = cfg->napi_event;
1da177e4 3168
2efa53f3
FR		 3169 init_timer(&tp->timer);
3170 tp->timer.data = (unsigned long) dev;
3171 tp->timer.function = rtl8169_phy_timer;
3172
1da177e4 3173 rc = register_netdev(dev);
4ff96fa6 3174 if (rc < 0)
87aeec76 3175 goto err_out_msi_4;
1da177e4
LT		 3176
3177 pci_set_drvdata(pdev, dev);
3178
bf82c189
JP		 3179 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3180 rtl_chip_info[tp->chipset].name,
3181 dev->base_addr, dev->dev_addr,
3182 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
1da177e4 3183
e6de30d6 3184 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3185 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
b646d900 3186 rtl8168_driver_start(tp);
e6de30d6 3187 }
b646d900 3188
8b76ab39 3189 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
1da177e4 3190
f3ec4f87
AS		 3191 if (pci_dev_run_wake(pdev))
3192 pm_runtime_put_noidle(&pdev->dev);
e1759441 3193
0d672e9f
IV		 3194 netif_carrier_off(dev);
3195
4ff96fa6
FR		 3196out:
3197 return rc;
1da177e4 3198
87aeec76 3199err_out_msi_4:
fbac58fc 3200 rtl_disable_msi(pdev, tp);
4ff96fa6 3201 iounmap(ioaddr);
87aeec76 3202err_out_free_res_3:
4ff96fa6 3203 pci_release_regions(pdev);
87aeec76 3204err_out_mwi_2:
4ff96fa6 3205 pci_clear_mwi(pdev);
4ff96fa6
FR		 3206 pci_disable_device(pdev);
3207err_out_free_dev_1:
3208 free_netdev(dev);
3209 goto out;
1da177e4
LT		 3210}
3211
07d3f51f 3212static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
1da177e4
LT		 3213{
3214 struct net_device *dev = pci_get_drvdata(pdev);
3215 struct rtl8169_private *tp = netdev_priv(dev);
3216
e6de30d6 3217 if ((tp->mac_version == RTL_GIGA_MAC_VER_27) ||
3218 (tp->mac_version == RTL_GIGA_MAC_VER_28)) {
b646d900 3219 rtl8168_driver_stop(tp);
e6de30d6 3220 }
b646d900 3221
23f333a2 3222 cancel_delayed_work_sync(&tp->task);
eb2a021c 3223
f1e02ed1 3224 rtl_release_firmware(tp);
3225
1da177e4 3226 unregister_netdev(dev);
cc098dc7 3227
f3ec4f87
AS		 3228 if (pci_dev_run_wake(pdev))
3229 pm_runtime_get_noresume(&pdev->dev);
e1759441 3230
cc098dc7
IV		 3231 /* restore original MAC address */
3232 rtl_rar_set(tp, dev->perm_addr);
3233
fbac58fc 3234 rtl_disable_msi(pdev, tp);
1da177e4
LT		 3235 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3236 pci_set_drvdata(pdev, NULL);
3237}
3238
1da177e4
LT		 3239static int rtl8169_open(struct net_device *dev)
3240{
3241 struct rtl8169_private *tp = netdev_priv(dev);
eee3a96c 3242 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 3243 struct pci_dev *pdev = tp->pci_dev;
99f252b0 3244 int retval = -ENOMEM;
1da177e4 3245
e1759441 3246 pm_runtime_get_sync(&pdev->dev);
1da177e4 3247
1da177e4
LT		 3248 /*
3249 * Rx and Tx desscriptors needs 256 bytes alignment.
82553bb6 3250 * dma_alloc_coherent provides more.
1da177e4 3251 */
82553bb6
SG		 3252 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3253 &tp->TxPhyAddr, GFP_KERNEL);
1da177e4 3254 if (!tp->TxDescArray)
e1759441 3255 goto err_pm_runtime_put;
1da177e4 3256
82553bb6
SG		 3257 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3258 &tp->RxPhyAddr, GFP_KERNEL);
1da177e4 3259 if (!tp->RxDescArray)
99f252b0 3260 goto err_free_tx_0;
1da177e4
LT		 3261
3262 retval = rtl8169_init_ring(dev);
3263 if (retval < 0)
99f252b0 3264 goto err_free_rx_1;
1da177e4 3265
c4028958 3266 INIT_DELAYED_WORK(&tp->task, NULL);
1da177e4 3267
99f252b0
FR		 3268 smp_mb();
3269
fbac58fc
FR		 3270 retval = request_irq(dev->irq, rtl8169_interrupt,
3271 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
99f252b0
FR		 3272 dev->name, dev);
3273 if (retval < 0)
3274 goto err_release_ring_2;
3275
bea3348e 3276 napi_enable(&tp->napi);
bea3348e 3277
eee3a96c 3278 rtl8169_init_phy(dev, tp);
3279
3280 /*
3281 * Pretend we are using VLANs; This bypasses a nasty bug where
3282 * Interrupts stop flowing on high load on 8110SCd controllers.
3283 */
3284 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3285 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3286
065c27c1 3287 rtl_pll_power_up(tp);
3288
07ce4064 3289 rtl_hw_start(dev);
1da177e4
LT		 3290
3291 rtl8169_request_timer(dev);
3292
e1759441
RW		 3293 tp->saved_wolopts = 0;
3294 pm_runtime_put_noidle(&pdev->dev);
3295
eee3a96c 3296 rtl8169_check_link_status(dev, tp, ioaddr);
1da177e4
LT		 3297out:
3298 return retval;
3299
99f252b0
FR		 3300err_release_ring_2:
3301 rtl8169_rx_clear(tp);
3302err_free_rx_1:
82553bb6
SG		 3303 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3304 tp->RxPhyAddr);
e1759441 3305 tp->RxDescArray = NULL;
99f252b0 3306err_free_tx_0:
82553bb6
SG		 3307 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3308 tp->TxPhyAddr);
e1759441
RW		 3309 tp->TxDescArray = NULL;
3310err_pm_runtime_put:
3311 pm_runtime_put_noidle(&pdev->dev);
1da177e4
LT		 3312 goto out;
3313}
3314
e6de30d6 3315static void rtl8169_hw_reset(struct rtl8169_private *tp)
1da177e4 3316{
e6de30d6 3317 void __iomem *ioaddr = tp->mmio_addr;
3318
1da177e4
LT		 3319 /* Disable interrupts */
3320 rtl8169_irq_mask_and_ack(ioaddr);
3321
e6de30d6 3322 if (tp->mac_version == RTL_GIGA_MAC_VER_28) {
3323 while (RTL_R8(TxPoll) & NPQ)
3324 udelay(20);
3325
3326 }
3327
1da177e4
LT		 3328 /* Reset the chipset */
3329 RTL_W8(ChipCmd, CmdReset);
3330
3331 /* PCI commit */
3332 RTL_R8(ChipCmd);
3333}
3334
7f796d83 3335static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
9cb427b6
FR		 3336{
3337 void __iomem *ioaddr = tp->mmio_addr;
3338 u32 cfg = rtl8169_rx_config;
3339
3340 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3341 RTL_W32(RxConfig, cfg);
3342
3343 /* Set DMA burst size and Interframe Gap Time */
3344 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3345 (InterFrameGap << TxInterFrameGapShift));
3346}
3347
07ce4064 3348static void rtl_hw_start(struct net_device *dev)
1da177e4
LT		 3349{
3350 struct rtl8169_private *tp = netdev_priv(dev);
3351 void __iomem *ioaddr = tp->mmio_addr;
07d3f51f 3352 unsigned int i;
1da177e4
LT		 3353
3354 /* Soft reset the chip. */
3355 RTL_W8(ChipCmd, CmdReset);
3356
3357 /* Check that the chip has finished the reset. */
07d3f51f 3358 for (i = 0; i < 100; i++) {
1da177e4
LT		 3359 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3360 break;
b518fa8e 3361 msleep_interruptible(1);
1da177e4
LT		 3362 }
3363
07ce4064
FR		 3364 tp->hw_start(dev);
3365
07ce4064
FR		 3366 netif_start_queue(dev);
3367}
3368
3369
7f796d83
FR		 3370static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3371 void __iomem *ioaddr)
3372{
3373 /*
3374 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3375 * register to be written before TxDescAddrLow to work.
3376 * Switching from MMIO to I/O access fixes the issue as well.
3377 */
3378 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
284901a9 3379 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
7f796d83 3380 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
284901a9 3381 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
7f796d83
FR		 3382}
3383
3384static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3385{
3386 u16 cmd;
3387
3388 cmd = RTL_R16(CPlusCmd);
3389 RTL_W16(CPlusCmd, cmd);
3390 return cmd;
3391}
3392
fdd7b4c3 3393static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
7f796d83
FR		 3394{
3395 /* Low hurts. Let's disable the filtering. */
207d6e87 3396 RTL_W16(RxMaxSize, rx_buf_sz + 1);
7f796d83
FR		 3397}
3398
6dccd16b
FR		 3399static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3400{
350f7596 3401 static const struct {
6dccd16b
FR		 3402 u32 mac_version;
3403 u32 clk;
3404 u32 val;
3405 } cfg2_info [] = {
3406 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3407 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3408 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3409 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3410 }, *p = cfg2_info;
3411 unsigned int i;
3412 u32 clk;
3413
3414 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
cadf1855 3415 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
6dccd16b
FR		 3416 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3417 RTL_W32(0x7c, p->val);
3418 break;
3419 }
3420 }
3421}
3422
07ce4064
FR		 3423static void rtl_hw_start_8169(struct net_device *dev)
3424{
3425 struct rtl8169_private *tp = netdev_priv(dev);
3426 void __iomem *ioaddr = tp->mmio_addr;
3427 struct pci_dev *pdev = tp->pci_dev;
07ce4064 3428
9cb427b6
FR		 3429 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3430 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3431 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3432 }
3433
1da177e4 3434 RTL_W8(Cfg9346, Cfg9346_Unlock);
9cb427b6
FR		 3435 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3436 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3437 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3438 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3439 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3440
f0298f81 3441 RTL_W8(EarlyTxThres, NoEarlyTx);
1da177e4 3442
6f0333b8 3443 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
1da177e4 3444
c946b304
FR		 3445 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3446 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3447 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3448 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3449 rtl_set_rx_tx_config_registers(tp);
1da177e4 3450
7f796d83 3451 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
1da177e4 3452
bcf0bf90
FR		 3453 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3454 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
06fa7358 3455 dprintk("Set MAC Reg C+CR Offset 0xE0. "
1da177e4 3456 "Bit-3 and bit-14 MUST be 1\n");
bcf0bf90 3457 tp->cp_cmd |= (1 << 14);
1da177e4
LT		 3458 }
3459
bcf0bf90
FR		 3460 RTL_W16(CPlusCmd, tp->cp_cmd);
3461
6dccd16b
FR		 3462 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3463
1da177e4
LT		 3464 /*
3465 * Undocumented corner. Supposedly:
3466 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3467 */
3468 RTL_W16(IntrMitigate, 0x0000);
3469
7f796d83 3470 rtl_set_rx_tx_desc_registers(tp, ioaddr);
9cb427b6 3471
c946b304
FR		 3472 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3473 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3474 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3475 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3476 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3477 rtl_set_rx_tx_config_registers(tp);
3478 }
3479
1da177e4 3480 RTL_W8(Cfg9346, Cfg9346_Lock);
b518fa8e
FR		 3481
3482 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3483 RTL_R8(IntrMask);
1da177e4
LT		 3484
3485 RTL_W32(RxMissed, 0);
3486
07ce4064 3487 rtl_set_rx_mode(dev);
1da177e4
LT		 3488
3489 /* no early-rx interrupts */
3490 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b
FR		 3491
3492 /* Enable all known interrupts by setting the interrupt mask. */
0e485150 3493 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3494}
1da177e4 3495
9c14ceaf 3496static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
458a9f61 3497{
9c14ceaf
FR		 3498 struct net_device *dev = pci_get_drvdata(pdev);
3499 struct rtl8169_private *tp = netdev_priv(dev);
3500 int cap = tp->pcie_cap;
3501
3502 if (cap) {
3503 u16 ctl;
458a9f61 3504
9c14ceaf
FR		 3505 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3506 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3507 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3508 }
458a9f61
FR		 3509}
3510
650e8d5d 3511static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
dacf8154
FR		 3512{
3513 u32 csi;
3514
3515 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
650e8d5d 3516 rtl_csi_write(ioaddr, 0x070c, csi | bits);
3517}
3518
e6de30d6 3519static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3520{
3521 rtl_csi_access_enable(ioaddr, 0x17000000);
3522}
3523
650e8d5d 3524static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3525{
3526 rtl_csi_access_enable(ioaddr, 0x27000000);
dacf8154
FR		 3527}
3528
3529struct ephy_info {
3530 unsigned int offset;
3531 u16 mask;
3532 u16 bits;
3533};
3534
350f7596 3535static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
dacf8154
FR		 3536{
3537 u16 w;
3538
3539 while (len-- > 0) {
3540 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3541 rtl_ephy_write(ioaddr, e->offset, w);
3542 e++;
3543 }
3544}
3545
b726e493
FR		 3546static void rtl_disable_clock_request(struct pci_dev *pdev)
3547{
3548 struct net_device *dev = pci_get_drvdata(pdev);
3549 struct rtl8169_private *tp = netdev_priv(dev);
3550 int cap = tp->pcie_cap;
3551
3552 if (cap) {
3553 u16 ctl;
3554
3555 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3556 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3557 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3558 }
3559}
3560
e6de30d6 3561static void rtl_enable_clock_request(struct pci_dev *pdev)
3562{
3563 struct net_device *dev = pci_get_drvdata(pdev);
3564 struct rtl8169_private *tp = netdev_priv(dev);
3565 int cap = tp->pcie_cap;
3566
3567 if (cap) {
3568 u16 ctl;
3569
3570 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3571 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3572 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3573 }
3574}
3575
b726e493
FR		 3576#define R8168_CPCMD_QUIRK_MASK (\
3577 EnableBist | \
3578 Mac_dbgo_oe | \
3579 Force_half_dup | \
3580 Force_rxflow_en | \
3581 Force_txflow_en | \
3582 Cxpl_dbg_sel | \
3583 ASF | \
3584 PktCntrDisable | \
3585 Mac_dbgo_sel)
3586
219a1e9d
FR		 3587static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3588{
b726e493
FR		 3589 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3590
3591 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3592
2e68ae44
FR		 3593 rtl_tx_performance_tweak(pdev,
3594 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
219a1e9d
FR		 3595}
3596
3597static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3598{
3599 rtl_hw_start_8168bb(ioaddr, pdev);
b726e493 3600
f0298f81 3601 RTL_W8(MaxTxPacketSize, TxPacketMax);
b726e493
FR		 3602
3603 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
219a1e9d
FR		 3604}
3605
3606static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3607{
b726e493
FR		 3608 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3609
3610 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3611
219a1e9d 3612 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
b726e493
FR		 3613
3614 rtl_disable_clock_request(pdev);
3615
3616 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
219a1e9d
FR		 3617}
3618
ef3386f0 3619static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
219a1e9d 3620{
350f7596 3621 static const struct ephy_info e_info_8168cp[] = {
b726e493
FR		 3622 { 0x01, 0, 0x0001 },
3623 { 0x02, 0x0800, 0x1000 },
3624 { 0x03, 0, 0x0042 },
3625 { 0x06, 0x0080, 0x0000 },
3626 { 0x07, 0, 0x2000 }
3627 };
3628
650e8d5d 3629 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3630
3631 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3632
219a1e9d
FR		 3633 __rtl_hw_start_8168cp(ioaddr, pdev);
3634}
3635
ef3386f0
FR		 3636static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3637{
650e8d5d 3638 rtl_csi_access_enable_2(ioaddr);
ef3386f0
FR		 3639
3640 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3641
3642 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3643
3644 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3645}
3646
7f3e3d3a
FR		 3647static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3648{
650e8d5d 3649 rtl_csi_access_enable_2(ioaddr);
7f3e3d3a
FR		 3650
3651 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3652
3653 /* Magic. */
3654 RTL_W8(DBG_REG, 0x20);
3655
f0298f81 3656 RTL_W8(MaxTxPacketSize, TxPacketMax);
7f3e3d3a
FR		 3657
3658 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3659
3660 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3661}
3662
219a1e9d
FR		 3663static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3664{
350f7596 3665 static const struct ephy_info e_info_8168c_1[] = {
b726e493
FR		 3666 { 0x02, 0x0800, 0x1000 },
3667 { 0x03, 0, 0x0002 },
3668 { 0x06, 0x0080, 0x0000 }
3669 };
3670
650e8d5d 3671 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3672
3673 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3674
3675 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3676
219a1e9d
FR		 3677 __rtl_hw_start_8168cp(ioaddr, pdev);
3678}
3679
3680static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3681{
350f7596 3682 static const struct ephy_info e_info_8168c_2[] = {
b726e493
FR		 3683 { 0x01, 0, 0x0001 },
3684 { 0x03, 0x0400, 0x0220 }
3685 };
3686
650e8d5d 3687 rtl_csi_access_enable_2(ioaddr);
b726e493
FR		 3688
3689 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3690
219a1e9d
FR		 3691 __rtl_hw_start_8168cp(ioaddr, pdev);
3692}
3693
197ff761
FR		 3694static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3695{
3696 rtl_hw_start_8168c_2(ioaddr, pdev);
3697}
3698
6fb07058
FR		 3699static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3700{
650e8d5d 3701 rtl_csi_access_enable_2(ioaddr);
6fb07058
FR		 3702
3703 __rtl_hw_start_8168cp(ioaddr, pdev);
3704}
3705
5b538df9
FR		 3706static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3707{
650e8d5d 3708 rtl_csi_access_enable_2(ioaddr);
5b538df9
FR		 3709
3710 rtl_disable_clock_request(pdev);
3711
f0298f81 3712 RTL_W8(MaxTxPacketSize, TxPacketMax);
5b538df9
FR		 3713
3714 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3715
3716 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3717}
3718
e6de30d6 3719static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
3720{
3721 static const struct ephy_info e_info_8168d_4[] = {
3722 { 0x0b, ~0, 0x48 },
3723 { 0x19, 0x20, 0x50 },
3724 { 0x0c, ~0, 0x20 }
3725 };
3726 int i;
3727
3728 rtl_csi_access_enable_1(ioaddr);
3729
3730 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3731
3732 RTL_W8(MaxTxPacketSize, TxPacketMax);
3733
3734 for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
3735 const struct ephy_info *e = e_info_8168d_4 + i;
3736 u16 w;
3737
3738 w = rtl_ephy_read(ioaddr, e->offset);
3739 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
3740 }
3741
3742 rtl_enable_clock_request(pdev);
3743}
3744
07ce4064
FR		 3745static void rtl_hw_start_8168(struct net_device *dev)
3746{
2dd99530
FR		 3747 struct rtl8169_private *tp = netdev_priv(dev);
3748 void __iomem *ioaddr = tp->mmio_addr;
0e485150 3749 struct pci_dev *pdev = tp->pci_dev;
2dd99530
FR		 3750
3751 RTL_W8(Cfg9346, Cfg9346_Unlock);
3752
f0298f81 3753 RTL_W8(MaxTxPacketSize, TxPacketMax);
2dd99530 3754
6f0333b8 3755 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
2dd99530 3756
0e485150 3757 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2dd99530
FR		 3758
3759 RTL_W16(CPlusCmd, tp->cp_cmd);
3760
0e485150 3761 RTL_W16(IntrMitigate, 0x5151);
2dd99530 3762
0e485150 3763 /* Work around for RxFIFO overflow. */
b5ba6d12
IV		 3764 if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
3765 tp->mac_version == RTL_GIGA_MAC_VER_22) {
0e485150
FR		 3766 tp->intr_event |= RxFIFOOver | PCSTimeout;
3767 tp->intr_event &= ~RxOverflow;
3768 }
3769
3770 rtl_set_rx_tx_desc_registers(tp, ioaddr);
2dd99530 3771
b8363901
FR		 3772 rtl_set_rx_mode(dev);
3773
3774 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3775 (InterFrameGap << TxInterFrameGapShift));
2dd99530
FR		 3776
3777 RTL_R8(IntrMask);
3778
219a1e9d
FR		 3779 switch (tp->mac_version) {
3780 case RTL_GIGA_MAC_VER_11:
3781 rtl_hw_start_8168bb(ioaddr, pdev);
3782 break;
3783
3784 case RTL_GIGA_MAC_VER_12:
3785 case RTL_GIGA_MAC_VER_17:
3786 rtl_hw_start_8168bef(ioaddr, pdev);
3787 break;
3788
3789 case RTL_GIGA_MAC_VER_18:
ef3386f0 3790 rtl_hw_start_8168cp_1(ioaddr, pdev);
219a1e9d
FR		 3791 break;
3792
3793 case RTL_GIGA_MAC_VER_19:
3794 rtl_hw_start_8168c_1(ioaddr, pdev);
3795 break;
3796
3797 case RTL_GIGA_MAC_VER_20:
3798 rtl_hw_start_8168c_2(ioaddr, pdev);
3799 break;
3800
197ff761
FR		 3801 case RTL_GIGA_MAC_VER_21:
3802 rtl_hw_start_8168c_3(ioaddr, pdev);
3803 break;
3804
6fb07058
FR		 3805 case RTL_GIGA_MAC_VER_22:
3806 rtl_hw_start_8168c_4(ioaddr, pdev);
3807 break;
3808
ef3386f0
FR		 3809 case RTL_GIGA_MAC_VER_23:
3810 rtl_hw_start_8168cp_2(ioaddr, pdev);
3811 break;
3812
7f3e3d3a
FR		 3813 case RTL_GIGA_MAC_VER_24:
3814 rtl_hw_start_8168cp_3(ioaddr, pdev);
3815 break;
3816
5b538df9 3817 case RTL_GIGA_MAC_VER_25:
daf9df6d 3818 case RTL_GIGA_MAC_VER_26:
3819 case RTL_GIGA_MAC_VER_27:
5b538df9
FR		 3820 rtl_hw_start_8168d(ioaddr, pdev);
3821 break;
3822
e6de30d6 3823 case RTL_GIGA_MAC_VER_28:
3824 rtl_hw_start_8168d_4(ioaddr, pdev);
3825 break;
3826
219a1e9d
FR		 3827 default:
3828 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3829 dev->name, tp->mac_version);
3830 break;
3831 }
2dd99530 3832
0e485150
FR		 3833 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3834
b8363901
FR		 3835 RTL_W8(Cfg9346, Cfg9346_Lock);
3836
2dd99530 3837 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
6dccd16b 3838
0e485150 3839 RTL_W16(IntrMask, tp->intr_event);
07ce4064 3840}
1da177e4 3841
2857ffb7
FR		 3842#define R810X_CPCMD_QUIRK_MASK (\
3843 EnableBist | \
3844 Mac_dbgo_oe | \
3845 Force_half_dup | \
5edcc537 3846 Force_rxflow_en | \
2857ffb7
FR		 3847 Force_txflow_en | \
3848 Cxpl_dbg_sel | \
3849 ASF | \
3850 PktCntrDisable | \
3851 PCIDAC | \
3852 PCIMulRW)
3853
3854static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3855{
350f7596 3856 static const struct ephy_info e_info_8102e_1[] = {
2857ffb7
FR		 3857 { 0x01, 0, 0x6e65 },
3858 { 0x02, 0, 0x091f },
3859 { 0x03, 0, 0xc2f9 },
3860 { 0x06, 0, 0xafb5 },
3861 { 0x07, 0, 0x0e00 },
3862 { 0x19, 0, 0xec80 },
3863 { 0x01, 0, 0x2e65 },
3864 { 0x01, 0, 0x6e65 }
3865 };
3866 u8 cfg1;
3867
650e8d5d 3868 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 3869
3870 RTL_W8(DBG_REG, FIX_NAK_1);
3871
3872 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3873
3874 RTL_W8(Config1,
3875 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3876 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3877
3878 cfg1 = RTL_R8(Config1);
3879 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3880 RTL_W8(Config1, cfg1 & ~LEDS0);
3881
3882 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3883
3884 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3885}
3886
3887static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3888{
650e8d5d 3889 rtl_csi_access_enable_2(ioaddr);
2857ffb7
FR		 3890
3891 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3892
3893 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3894 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3895
3896 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3897}
3898
3899static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3900{
3901 rtl_hw_start_8102e_2(ioaddr, pdev);
3902
3903 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3904}
3905
07ce4064
FR		 3906static void rtl_hw_start_8101(struct net_device *dev)
3907{
cdf1a608
FR		 3908 struct rtl8169_private *tp = netdev_priv(dev);
3909 void __iomem *ioaddr = tp->mmio_addr;
3910 struct pci_dev *pdev = tp->pci_dev;
3911
e3cf0cc0
FR		 3912 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3913 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
9c14ceaf
FR		 3914 int cap = tp->pcie_cap;
3915
3916 if (cap) {
3917 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3918 PCI_EXP_DEVCTL_NOSNOOP_EN);
3919 }
cdf1a608
FR		 3920 }
3921
2857ffb7
FR		 3922 switch (tp->mac_version) {
3923 case RTL_GIGA_MAC_VER_07:
3924 rtl_hw_start_8102e_1(ioaddr, pdev);
3925 break;
3926
3927 case RTL_GIGA_MAC_VER_08:
3928 rtl_hw_start_8102e_3(ioaddr, pdev);
3929 break;
3930
3931 case RTL_GIGA_MAC_VER_09:
3932 rtl_hw_start_8102e_2(ioaddr, pdev);
3933 break;
cdf1a608
FR		 3934 }
3935
3936 RTL_W8(Cfg9346, Cfg9346_Unlock);
3937
f0298f81 3938 RTL_W8(MaxTxPacketSize, TxPacketMax);
cdf1a608 3939
6f0333b8 3940 rtl_set_rx_max_size(ioaddr, rx_buf_sz);
cdf1a608
FR		 3941
3942 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3943
3944 RTL_W16(CPlusCmd, tp->cp_cmd);
3945
3946 RTL_W16(IntrMitigate, 0x0000);
3947
3948 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3949
3950 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3951 rtl_set_rx_tx_config_registers(tp);
3952
3953 RTL_W8(Cfg9346, Cfg9346_Lock);
3954
3955 RTL_R8(IntrMask);
3956
cdf1a608
FR		 3957 rtl_set_rx_mode(dev);
3958
0e485150
FR		 3959 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3960
cdf1a608 3961 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
6dccd16b 3962
0e485150 3963 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 3964}
3965
3966static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3967{
1da177e4
LT		 3968 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3969 return -EINVAL;
3970
3971 dev->mtu = new_mtu;
323bb685 3972 return 0;
1da177e4
LT		 3973}
3974
3975static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3976{
95e0918d 3977 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
1da177e4
LT		 3978 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3979}
3980
6f0333b8
ED		 3981static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
3982 void **data_buff, struct RxDesc *desc)
1da177e4 3983{
48addcc9 3984 dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
231aee63 3985 DMA_FROM_DEVICE);
48addcc9 3986
6f0333b8
ED		 3987 kfree(*data_buff);
3988 *data_buff = NULL;
1da177e4
LT		 3989 rtl8169_make_unusable_by_asic(desc);
3990}
3991
3992static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3993{
3994 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3995
3996 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3997}
3998
3999static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4000 u32 rx_buf_sz)
4001{
4002 desc->addr = cpu_to_le64(mapping);
4003 wmb();
4004 rtl8169_mark_to_asic(desc, rx_buf_sz);
4005}
4006
6f0333b8
ED		 4007static inline void *rtl8169_align(void *data)
4008{
4009 return (void *)ALIGN((long)data, 16);
4010}
4011
0ecbe1ca
SG		 4012static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4013 struct RxDesc *desc)
1da177e4 4014{
6f0333b8 4015 void *data;
1da177e4 4016 dma_addr_t mapping;
48addcc9 4017 struct device *d = &tp->pci_dev->dev;
0ecbe1ca 4018 struct net_device *dev = tp->dev;
6f0333b8 4019 int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
1da177e4 4020
6f0333b8
ED		 4021 data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4022 if (!data)
4023 return NULL;
e9f63f30 4024
6f0333b8
ED		 4025 if (rtl8169_align(data) != data) {
4026 kfree(data);
4027 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4028 if (!data)
4029 return NULL;
4030 }
3eafe507 4031
48addcc9 4032 mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
231aee63 4033 DMA_FROM_DEVICE);
d827d86b
SG		 4034 if (unlikely(dma_mapping_error(d, mapping))) {
4035 if (net_ratelimit())
4036 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
3eafe507 4037 goto err_out;
d827d86b 4038 }
1da177e4
LT		 4039
4040 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
6f0333b8 4041 return data;
3eafe507
SG		 4042
4043err_out:
4044 kfree(data);
4045 return NULL;
1da177e4
LT		 4046}
4047
4048static void rtl8169_rx_clear(struct rtl8169_private *tp)
4049{
07d3f51f 4050 unsigned int i;
1da177e4
LT		 4051
4052 for (i = 0; i < NUM_RX_DESC; i++) {
6f0333b8
ED		 4053 if (tp->Rx_databuff[i]) {
4054 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
1da177e4
LT		 4055 tp->RxDescArray + i);
4056 }
4057 }
4058}
4059
0ecbe1ca 4060static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1da177e4 4061{
0ecbe1ca
SG		 4062 desc->opts1 |= cpu_to_le32(RingEnd);
4063}
5b0384f4 4064
0ecbe1ca
SG		 4065static int rtl8169_rx_fill(struct rtl8169_private *tp)
4066{
4067 unsigned int i;
1da177e4 4068
0ecbe1ca
SG		 4069 for (i = 0; i < NUM_RX_DESC; i++) {
4070 void *data;
4ae47c2d 4071
6f0333b8 4072 if (tp->Rx_databuff[i])
1da177e4 4073 continue;
bcf0bf90 4074
0ecbe1ca 4075 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
6f0333b8
ED		 4076 if (!data) {
4077 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
0ecbe1ca 4078 goto err_out;
6f0333b8
ED		 4079 }
4080 tp->Rx_databuff[i] = data;
1da177e4 4081 }
1da177e4 4082
0ecbe1ca
SG		 4083 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4084 return 0;
4085
4086err_out:
4087 rtl8169_rx_clear(tp);
4088 return -ENOMEM;
1da177e4
LT		 4089}
4090
4091static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4092{
4093 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4094}
4095
4096static int rtl8169_init_ring(struct net_device *dev)
4097{
4098 struct rtl8169_private *tp = netdev_priv(dev);
4099
4100 rtl8169_init_ring_indexes(tp);
4101
4102 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
6f0333b8 4103 memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
1da177e4 4104
0ecbe1ca 4105 return rtl8169_rx_fill(tp);
1da177e4
LT		 4106}
4107
48addcc9 4108static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
1da177e4
LT		 4109 struct TxDesc *desc)
4110{
4111 unsigned int len = tx_skb->len;
4112
48addcc9
SG		 4113 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4114
1da177e4
LT		 4115 desc->opts1 = 0x00;
4116 desc->opts2 = 0x00;
4117 desc->addr = 0x00;
4118 tx_skb->len = 0;
4119}
4120
3eafe507
SG		 4121static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4122 unsigned int n)
1da177e4
LT		 4123{
4124 unsigned int i;
4125
3eafe507
SG		 4126 for (i = 0; i < n; i++) {
4127 unsigned int entry = (start + i) % NUM_TX_DESC;
1da177e4
LT		 4128 struct ring_info *tx_skb = tp->tx_skb + entry;
4129 unsigned int len = tx_skb->len;
4130
4131 if (len) {
4132 struct sk_buff *skb = tx_skb->skb;
4133
48addcc9 4134 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
1da177e4
LT		 4135 tp->TxDescArray + entry);
4136 if (skb) {
cac4b22f 4137 tp->dev->stats.tx_dropped++;
1da177e4
LT		 4138 dev_kfree_skb(skb);
4139 tx_skb->skb = NULL;
4140 }
1da177e4
LT		 4141 }
4142 }
3eafe507
SG		 4143}
4144
4145static void rtl8169_tx_clear(struct rtl8169_private *tp)
4146{
4147 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
1da177e4
LT		 4148 tp->cur_tx = tp->dirty_tx = 0;
4149}
4150
c4028958 4151static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
1da177e4
LT		 4152{
4153 struct rtl8169_private *tp = netdev_priv(dev);
4154
c4028958 4155 PREPARE_DELAYED_WORK(&tp->task, task);
1da177e4
LT		 4156 schedule_delayed_work(&tp->task, 4);
4157}
4158
4159static void rtl8169_wait_for_quiescence(struct net_device *dev)
4160{
4161 struct rtl8169_private *tp = netdev_priv(dev);
4162 void __iomem *ioaddr = tp->mmio_addr;
4163
4164 synchronize_irq(dev->irq);
4165
4166 /* Wait for any pending NAPI task to complete */
bea3348e 4167 napi_disable(&tp->napi);
1da177e4
LT		 4168
4169 rtl8169_irq_mask_and_ack(ioaddr);
4170
d1d08d12
DM		 4171 tp->intr_mask = 0xffff;
4172 RTL_W16(IntrMask, tp->intr_event);
bea3348e 4173 napi_enable(&tp->napi);
1da177e4
LT		 4174}
4175
c4028958 4176static void rtl8169_reinit_task(struct work_struct *work)
1da177e4 4177{
c4028958
DH		 4178 struct rtl8169_private *tp =
4179 container_of(work, struct rtl8169_private, task.work);
4180 struct net_device *dev = tp->dev;
1da177e4
LT		 4181 int ret;
4182
eb2a021c
FR		 4183 rtnl_lock();
4184
4185 if (!netif_running(dev))
4186 goto out_unlock;
4187
4188 rtl8169_wait_for_quiescence(dev);
4189 rtl8169_close(dev);
1da177e4
LT		 4190
4191 ret = rtl8169_open(dev);
4192 if (unlikely(ret < 0)) {
bf82c189
JP		 4193 if (net_ratelimit())
4194 netif_err(tp, drv, dev,
4195 "reinit failure (status = %d). Rescheduling\n",
4196 ret);
1da177e4
LT		 4197 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4198 }
eb2a021c
FR		 4199
4200out_unlock:
4201 rtnl_unlock();
1da177e4
LT		 4202}
4203
c4028958 4204static void rtl8169_reset_task(struct work_struct *work)
1da177e4 4205{
c4028958
DH		 4206 struct rtl8169_private *tp =
4207 container_of(work, struct rtl8169_private, task.work);
4208 struct net_device *dev = tp->dev;
1da177e4 4209
eb2a021c
FR		 4210 rtnl_lock();
4211
1da177e4 4212 if (!netif_running(dev))
eb2a021c 4213 goto out_unlock;
1da177e4
LT		 4214
4215 rtl8169_wait_for_quiescence(dev);
4216
bea3348e 4217 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
1da177e4
LT		 4218 rtl8169_tx_clear(tp);
4219
4220 if (tp->dirty_rx == tp->cur_rx) {
4221 rtl8169_init_ring_indexes(tp);
07ce4064 4222 rtl_hw_start(dev);
1da177e4 4223 netif_wake_queue(dev);
cebf8cc7 4224 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1da177e4 4225 } else {
bf82c189
JP		 4226 if (net_ratelimit())
4227 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
1da177e4
LT		 4228 rtl8169_schedule_work(dev, rtl8169_reset_task);
4229 }
eb2a021c
FR		 4230
4231out_unlock:
4232 rtnl_unlock();
1da177e4
LT		 4233}
4234
4235static void rtl8169_tx_timeout(struct net_device *dev)
4236{
4237 struct rtl8169_private *tp = netdev_priv(dev);
4238
e6de30d6 4239 rtl8169_hw_reset(tp);
1da177e4
LT		 4240
4241 /* Let's wait a bit while any (async) irq lands on */
4242 rtl8169_schedule_work(dev, rtl8169_reset_task);
4243}
4244
4245static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4246 u32 opts1)
4247{
4248 struct skb_shared_info *info = skb_shinfo(skb);
4249 unsigned int cur_frag, entry;
a6343afb 4250 struct TxDesc * uninitialized_var(txd);
48addcc9 4251 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4252
4253 entry = tp->cur_tx;
4254 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4255 skb_frag_t *frag = info->frags + cur_frag;
4256 dma_addr_t mapping;
4257 u32 status, len;
4258 void *addr;
4259
4260 entry = (entry + 1) % NUM_TX_DESC;
4261
4262 txd = tp->TxDescArray + entry;
4263 len = frag->size;
4264 addr = ((void *) page_address(frag->page)) + frag->page_offset;
48addcc9 4265 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
d827d86b
SG		 4266 if (unlikely(dma_mapping_error(d, mapping))) {
4267 if (net_ratelimit())
4268 netif_err(tp, drv, tp->dev,
4269 "Failed to map TX fragments DMA!\n");
3eafe507 4270 goto err_out;
d827d86b 4271 }
1da177e4
LT		 4272
4273 /* anti gcc 2.95.3 bugware (sic) */
4274 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4275
4276 txd->opts1 = cpu_to_le32(status);
4277 txd->addr = cpu_to_le64(mapping);
4278
4279 tp->tx_skb[entry].len = len;
4280 }
4281
4282 if (cur_frag) {
4283 tp->tx_skb[entry].skb = skb;
4284 txd->opts1 |= cpu_to_le32(LastFrag);
4285 }
4286
4287 return cur_frag;
3eafe507
SG		 4288
4289err_out:
4290 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4291 return -EIO;
1da177e4
LT		 4292}
4293
4294static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4295{
4296 if (dev->features & NETIF_F_TSO) {
7967168c 4297 u32 mss = skb_shinfo(skb)->gso_size;
1da177e4
LT		 4298
4299 if (mss)
4300 return LargeSend | ((mss & MSSMask) << MSSShift);
4301 }
84fa7933 4302 if (skb->ip_summed == CHECKSUM_PARTIAL) {
eddc9ec5 4303 const struct iphdr *ip = ip_hdr(skb);
1da177e4
LT		 4304
4305 if (ip->protocol == IPPROTO_TCP)
4306 return IPCS | TCPCS;
4307 else if (ip->protocol == IPPROTO_UDP)
4308 return IPCS | UDPCS;
4309 WARN_ON(1); /* we need a WARN() */
4310 }
4311 return 0;
4312}
4313
61357325
SH		 4314static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4315 struct net_device *dev)
1da177e4
LT		 4316{
4317 struct rtl8169_private *tp = netdev_priv(dev);
3eafe507 4318 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
1da177e4
LT		 4319 struct TxDesc *txd = tp->TxDescArray + entry;
4320 void __iomem *ioaddr = tp->mmio_addr;
48addcc9 4321 struct device *d = &tp->pci_dev->dev;
1da177e4
LT		 4322 dma_addr_t mapping;
4323 u32 status, len;
4324 u32 opts1;
3eafe507 4325 int frags;
5b0384f4 4326
1da177e4 4327 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
bf82c189 4328 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
3eafe507 4329 goto err_stop_0;
1da177e4
LT		 4330 }
4331
4332 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3eafe507
SG		 4333 goto err_stop_0;
4334
4335 len = skb_headlen(skb);
48addcc9 4336 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
d827d86b
SG		 4337 if (unlikely(dma_mapping_error(d, mapping))) {
4338 if (net_ratelimit())
4339 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
3eafe507 4340 goto err_dma_0;
d827d86b 4341 }
3eafe507
SG		 4342
4343 tp->tx_skb[entry].len = len;
4344 txd->addr = cpu_to_le64(mapping);
4345 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
1da177e4
LT		 4346
4347 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4348
4349 frags = rtl8169_xmit_frags(tp, skb, opts1);
3eafe507
SG		 4350 if (frags < 0)
4351 goto err_dma_1;
4352 else if (frags)
1da177e4 4353 opts1 |= FirstFrag;
3eafe507 4354 else {
1da177e4
LT		 4355 opts1 |= FirstFrag | LastFrag;
4356 tp->tx_skb[entry].skb = skb;
4357 }
4358
1da177e4
LT		 4359 wmb();
4360
4361 /* anti gcc 2.95.3 bugware (sic) */
4362 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4363 txd->opts1 = cpu_to_le32(status);
4364
1da177e4
LT		 4365 tp->cur_tx += frags + 1;
4366
4c020a96 4367 wmb();
1da177e4 4368
275391a4 4369 RTL_W8(TxPoll, NPQ); /* set polling bit */
1da177e4
LT		 4370
4371 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4372 netif_stop_queue(dev);
4373 smp_rmb();
4374 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4375 netif_wake_queue(dev);
4376 }
4377
61357325 4378 return NETDEV_TX_OK;
1da177e4 4379
3eafe507 4380err_dma_1:
48addcc9 4381 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
3eafe507
SG		 4382err_dma_0:
4383 dev_kfree_skb(skb);
4384 dev->stats.tx_dropped++;
4385 return NETDEV_TX_OK;
4386
4387err_stop_0:
1da177e4 4388 netif_stop_queue(dev);
cebf8cc7 4389 dev->stats.tx_dropped++;
61357325 4390 return NETDEV_TX_BUSY;
1da177e4
LT		 4391}
4392
4393static void rtl8169_pcierr_interrupt(struct net_device *dev)
4394{
4395 struct rtl8169_private *tp = netdev_priv(dev);
4396 struct pci_dev *pdev = tp->pci_dev;
1da177e4
LT		 4397 u16 pci_status, pci_cmd;
4398
4399 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4400 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4401
bf82c189
JP		 4402 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4403 pci_cmd, pci_status);
1da177e4
LT		 4404
4405 /*
4406 * The recovery sequence below admits a very elaborated explanation:
4407 * - it seems to work;
d03902b8
FR		 4408 * - I did not see what else could be done;
4409 * - it makes iop3xx happy.
1da177e4
LT		 4410 *
4411 * Feel free to adjust to your needs.
4412 */
a27993f3 4413 if (pdev->broken_parity_status)
d03902b8
FR		 4414 pci_cmd &= ~PCI_COMMAND_PARITY;
4415 else
4416 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4417
4418 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1da177e4
LT		 4419
4420 pci_write_config_word(pdev, PCI_STATUS,
4421 pci_status & (PCI_STATUS_DETECTED_PARITY |
4422 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4423 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4424
4425 /* The infamous DAC f*ckup only happens at boot time */
4426 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
e6de30d6 4427 void __iomem *ioaddr = tp->mmio_addr;
4428
bf82c189 4429 netif_info(tp, intr, dev, "disabling PCI DAC\n");
1da177e4
LT		 4430 tp->cp_cmd &= ~PCIDAC;
4431 RTL_W16(CPlusCmd, tp->cp_cmd);
4432 dev->features &= ~NETIF_F_HIGHDMA;
1da177e4
LT		 4433 }
4434
e6de30d6 4435 rtl8169_hw_reset(tp);
d03902b8
FR		 4436
4437 rtl8169_schedule_work(dev, rtl8169_reinit_task);
1da177e4
LT		 4438}
4439
07d3f51f
FR		 4440static void rtl8169_tx_interrupt(struct net_device *dev,
4441 struct rtl8169_private *tp,
4442 void __iomem *ioaddr)
1da177e4
LT		 4443{
4444 unsigned int dirty_tx, tx_left;
4445
1da177e4
LT		 4446 dirty_tx = tp->dirty_tx;
4447 smp_rmb();
4448 tx_left = tp->cur_tx - dirty_tx;
4449
4450 while (tx_left > 0) {
4451 unsigned int entry = dirty_tx % NUM_TX_DESC;
4452 struct ring_info *tx_skb = tp->tx_skb + entry;
1da177e4
LT		 4453 u32 status;
4454
4455 rmb();
4456 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4457 if (status & DescOwn)
4458 break;
4459
48addcc9
SG		 4460 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4461 tp->TxDescArray + entry);
1da177e4 4462 if (status & LastFrag) {
cac4b22f
SG		 4463 dev->stats.tx_packets++;
4464 dev->stats.tx_bytes += tx_skb->skb->len;
87433bfc 4465 dev_kfree_skb(tx_skb->skb);
1da177e4
LT		 4466 tx_skb->skb = NULL;
4467 }
4468 dirty_tx++;
4469 tx_left--;
4470 }
4471
4472 if (tp->dirty_tx != dirty_tx) {
4473 tp->dirty_tx = dirty_tx;
4474 smp_wmb();
4475 if (netif_queue_stopped(dev) &&
4476 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4477 netif_wake_queue(dev);
4478 }
d78ae2dc
FR		 4479 /*
4480 * 8168 hack: TxPoll requests are lost when the Tx packets are
4481 * too close. Let's kick an extra TxPoll request when a burst
4482 * of start_xmit activity is detected (if it is not detected,
4483 * it is slow enough). -- FR
4484 */
4485 smp_rmb();
4486 if (tp->cur_tx != dirty_tx)
4487 RTL_W8(TxPoll, NPQ);
1da177e4
LT		 4488 }
4489}
4490
126fa4b9
FR		 4491static inline int rtl8169_fragmented_frame(u32 status)
4492{
4493 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4494}
4495
adea1ac7 4496static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
1da177e4 4497{
1da177e4
LT		 4498 u32 status = opts1 & RxProtoMask;
4499
4500 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
d5d3ebe3 4501 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
1da177e4
LT		 4502 skb->ip_summed = CHECKSUM_UNNECESSARY;
4503 else
bc8acf2c 4504 skb_checksum_none_assert(skb);
1da177e4
LT		 4505}
4506
6f0333b8
ED		 4507static struct sk_buff *rtl8169_try_rx_copy(void *data,
4508 struct rtl8169_private *tp,
4509 int pkt_size,
4510 dma_addr_t addr)
1da177e4 4511{
b449655f 4512 struct sk_buff *skb;
48addcc9 4513 struct device *d = &tp->pci_dev->dev;
b449655f 4514
6f0333b8 4515 data = rtl8169_align(data);
48addcc9 4516 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6f0333b8
ED		 4517 prefetch(data);
4518 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4519 if (skb)
4520 memcpy(skb->data, data, pkt_size);
48addcc9
SG		 4521 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
4522
6f0333b8 4523 return skb;
1da177e4
LT		 4524}
4525
630b943c
ED		 4526/*
4527 * Warning : rtl8169_rx_interrupt() might be called :
4528 * 1) from NAPI (softirq) context
4529 * (polling = 1 : we should call netif_receive_skb())
4530 * 2) from process context (rtl8169_reset_task())
4531 * (polling = 0 : we must call netif_rx() instead)
4532 */
07d3f51f
FR		 4533static int rtl8169_rx_interrupt(struct net_device *dev,
4534 struct rtl8169_private *tp,
bea3348e 4535 void __iomem *ioaddr, u32 budget)
1da177e4
LT		 4536{
4537 unsigned int cur_rx, rx_left;
6f0333b8 4538 unsigned int count;
630b943c 4539 int polling = (budget != ~(u32)0) ? 1 : 0;
1da177e4 4540
1da177e4
LT		 4541 cur_rx = tp->cur_rx;
4542 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
865c652d 4543 rx_left = min(rx_left, budget);
1da177e4 4544
4dcb7d33 4545 for (; rx_left > 0; rx_left--, cur_rx++) {
1da177e4 4546 unsigned int entry = cur_rx % NUM_RX_DESC;
126fa4b9 4547 struct RxDesc *desc = tp->RxDescArray + entry;
1da177e4
LT		 4548 u32 status;
4549
4550 rmb();
126fa4b9 4551 status = le32_to_cpu(desc->opts1);
1da177e4
LT		 4552
4553 if (status & DescOwn)
4554 break;
4dcb7d33 4555 if (unlikely(status & RxRES)) {
bf82c189
JP		 4556 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4557 status);
cebf8cc7 4558 dev->stats.rx_errors++;
1da177e4 4559 if (status & (RxRWT | RxRUNT))
cebf8cc7 4560 dev->stats.rx_length_errors++;
1da177e4 4561 if (status & RxCRC)
cebf8cc7 4562 dev->stats.rx_crc_errors++;
9dccf611
FR		 4563 if (status & RxFOVF) {
4564 rtl8169_schedule_work(dev, rtl8169_reset_task);
cebf8cc7 4565 dev->stats.rx_fifo_errors++;
9dccf611 4566 }
6f0333b8 4567 rtl8169_mark_to_asic(desc, rx_buf_sz);
1da177e4 4568 } else {
6f0333b8 4569 struct sk_buff *skb;
b449655f 4570 dma_addr_t addr = le64_to_cpu(desc->addr);
1da177e4 4571 int pkt_size = (status & 0x00001FFF) - 4;
1da177e4 4572
126fa4b9
FR		 4573 /*
4574 * The driver does not support incoming fragmented
4575 * frames. They are seen as a symptom of over-mtu
4576 * sized frames.
4577 */
4578 if (unlikely(rtl8169_fragmented_frame(status))) {
cebf8cc7
FR		 4579 dev->stats.rx_dropped++;
4580 dev->stats.rx_length_errors++;
6f0333b8 4581 rtl8169_mark_to_asic(desc, rx_buf_sz);
4dcb7d33 4582 continue;
126fa4b9
FR		 4583 }
4584
6f0333b8
ED		 4585 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
4586 tp, pkt_size, addr);
4587 rtl8169_mark_to_asic(desc, rx_buf_sz);
4588 if (!skb) {
4589 dev->stats.rx_dropped++;
4590 continue;
1da177e4
LT		 4591 }
4592
adea1ac7 4593 rtl8169_rx_csum(skb, status);
1da177e4
LT		 4594 skb_put(skb, pkt_size);
4595 skb->protocol = eth_type_trans(skb, dev);
4596
630b943c
ED		 4597 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4598 if (likely(polling))
2edae08e 4599 napi_gro_receive(&tp->napi, skb);
630b943c
ED		 4600 else
4601 netif_rx(skb);
4602 }
1da177e4 4603
cebf8cc7
FR		 4604 dev->stats.rx_bytes += pkt_size;
4605 dev->stats.rx_packets++;
1da177e4 4606 }
6dccd16b
FR		 4607
4608 /* Work around for AMD plateform. */
95e0918d 4609 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
6dccd16b
FR		 4610 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4611 desc->opts2 = 0;
4612 cur_rx++;
4613 }
1da177e4
LT		 4614 }
4615
4616 count = cur_rx - tp->cur_rx;
4617 tp->cur_rx = cur_rx;
4618
6f0333b8 4619 tp->dirty_rx += count;
1da177e4
LT		 4620
4621 return count;
4622}
4623
07d3f51f 4624static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
1da177e4 4625{
07d3f51f 4626 struct net_device *dev = dev_instance;
1da177e4 4627 struct rtl8169_private *tp = netdev_priv(dev);
1da177e4 4628 void __iomem *ioaddr = tp->mmio_addr;
1da177e4 4629 int handled = 0;
865c652d 4630 int status;
1da177e4 4631
f11a377b
DD		 4632 /* loop handling interrupts until we have no new ones or
4633 * we hit a invalid/hotplug case.
4634 */
865c652d 4635 status = RTL_R16(IntrStatus);
f11a377b
DD		 4636 while (status && status != 0xffff) {
4637 handled = 1;
1da177e4 4638
f11a377b
DD		 4639 /* Handle all of the error cases first. These will reset
4640 * the chip, so just exit the loop.
4641 */
4642 if (unlikely(!netif_running(dev))) {
4643 rtl8169_asic_down(ioaddr);
4644 break;
4645 }
1da177e4 4646
1519e57f
FR		 4647 if (unlikely(status & RxFIFOOver)) {
4648 switch (tp->mac_version) {
4649 /* Work around for rx fifo overflow */
4650 case RTL_GIGA_MAC_VER_11:
4651 case RTL_GIGA_MAC_VER_22:
4652 case RTL_GIGA_MAC_VER_26:
4653 netif_stop_queue(dev);
4654 rtl8169_tx_timeout(dev);
4655 goto done;
f60ac8e7
FR		 4656 /* Testers needed. */
4657 case RTL_GIGA_MAC_VER_17:
4658 case RTL_GIGA_MAC_VER_19:
4659 case RTL_GIGA_MAC_VER_20:
4660 case RTL_GIGA_MAC_VER_21:
4661 case RTL_GIGA_MAC_VER_23:
4662 case RTL_GIGA_MAC_VER_24:
4663 case RTL_GIGA_MAC_VER_27:
4664 case RTL_GIGA_MAC_VER_28:
1519e57f
FR		 4665 /* Experimental science. Pktgen proof. */
4666 case RTL_GIGA_MAC_VER_12:
4667 case RTL_GIGA_MAC_VER_25:
4668 if (status == RxFIFOOver)
4669 goto done;
4670 break;
4671 default:
4672 break;
4673 }
f11a377b 4674 }
1da177e4 4675
f11a377b
DD		 4676 if (unlikely(status & SYSErr)) {
4677 rtl8169_pcierr_interrupt(dev);
4678 break;
4679 }
1da177e4 4680
f11a377b 4681 if (status & LinkChg)
e4fbce74 4682 __rtl8169_check_link_status(dev, tp, ioaddr, true);
0e485150 4683
f11a377b
DD		 4684 /* We need to see the lastest version of tp->intr_mask to
4685 * avoid ignoring an MSI interrupt and having to wait for
4686 * another event which may never come.
4687 */
4688 smp_rmb();
4689 if (status & tp->intr_mask & tp->napi_event) {
4690 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4691 tp->intr_mask = ~tp->napi_event;
4692
4693 if (likely(napi_schedule_prep(&tp->napi)))
4694 __napi_schedule(&tp->napi);
bf82c189
JP		 4695 else
4696 netif_info(tp, intr, dev,
4697 "interrupt %04x in poll\n", status);
f11a377b 4698 }
1da177e4 4699
f11a377b
DD		 4700 /* We only get a new MSI interrupt when all active irq
4701 * sources on the chip have been acknowledged. So, ack
4702 * everything we've seen and check if new sources have become
4703 * active to avoid blocking all interrupts from the chip.
4704 */
4705 RTL_W16(IntrStatus,
4706 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4707 status = RTL_R16(IntrStatus);
865c652d 4708 }
1519e57f 4709done:
1da177e4
LT		 4710 return IRQ_RETVAL(handled);
4711}
4712
bea3348e 4713static int rtl8169_poll(struct napi_struct *napi, int budget)
1da177e4 4714{
bea3348e
SH		 4715 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4716 struct net_device *dev = tp->dev;
1da177e4 4717 void __iomem *ioaddr = tp->mmio_addr;
bea3348e 4718 int work_done;
1da177e4 4719
bea3348e 4720 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
1da177e4
LT		 4721 rtl8169_tx_interrupt(dev, tp, ioaddr);
4722
bea3348e 4723 if (work_done < budget) {
288379f0 4724 napi_complete(napi);
f11a377b
DD		 4725
4726 /* We need for force the visibility of tp->intr_mask
4727 * for other CPUs, as we can loose an MSI interrupt
4728 * and potentially wait for a retransmit timeout if we don't.
4729 * The posted write to IntrMask is safe, as it will
4730 * eventually make it to the chip and we won't loose anything
4731 * until it does.
1da177e4 4732 */
f11a377b 4733 tp->intr_mask = 0xffff;
4c020a96 4734 wmb();
0e485150 4735 RTL_W16(IntrMask, tp->intr_event);
1da177e4
LT		 4736 }
4737
bea3348e 4738 return work_done;
1da177e4 4739}
1da177e4 4740
523a6094
FR		 4741static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4742{
4743 struct rtl8169_private *tp = netdev_priv(dev);
4744
4745 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4746 return;
4747
4748 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4749 RTL_W32(RxMissed, 0);
4750}
4751
1da177e4
LT		 4752static void rtl8169_down(struct net_device *dev)
4753{
4754 struct rtl8169_private *tp = netdev_priv(dev);
4755 void __iomem *ioaddr = tp->mmio_addr;
1da177e4
LT		 4756
4757 rtl8169_delete_timer(dev);
4758
4759 netif_stop_queue(dev);
4760
93dd79e8 4761 napi_disable(&tp->napi);
93dd79e8 4762
1da177e4
LT		 4763 spin_lock_irq(&tp->lock);
4764
4765 rtl8169_asic_down(ioaddr);
323bb685
SG		 4766 /*
4767 * At this point device interrupts can not be enabled in any function,
4768 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
4769 * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
4770 */
523a6094 4771 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4772
4773 spin_unlock_irq(&tp->lock);
4774
4775 synchronize_irq(dev->irq);
4776
1da177e4 4777 /* Give a racing hard_start_xmit a few cycles to complete. */
fbd568a3 4778 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
1da177e4 4779
1da177e4
LT		 4780 rtl8169_tx_clear(tp);
4781
4782 rtl8169_rx_clear(tp);
065c27c1 4783
4784 rtl_pll_power_down(tp);
1da177e4
LT		 4785}
4786
4787static int rtl8169_close(struct net_device *dev)
4788{
4789 struct rtl8169_private *tp = netdev_priv(dev);
4790 struct pci_dev *pdev = tp->pci_dev;
4791
e1759441
RW		 4792 pm_runtime_get_sync(&pdev->dev);
4793
355423d0
IV		 4794 /* update counters before going down */
4795 rtl8169_update_counters(dev);
4796
1da177e4
LT		 4797 rtl8169_down(dev);
4798
4799 free_irq(dev->irq, dev);
4800
82553bb6
SG		 4801 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4802 tp->RxPhyAddr);
4803 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4804 tp->TxPhyAddr);
1da177e4
LT		 4805 tp->TxDescArray = NULL;
4806 tp->RxDescArray = NULL;
4807
e1759441
RW		 4808 pm_runtime_put_sync(&pdev->dev);
4809
1da177e4
LT		 4810 return 0;
4811}
4812
07ce4064 4813static void rtl_set_rx_mode(struct net_device *dev)
1da177e4
LT		 4814{
4815 struct rtl8169_private *tp = netdev_priv(dev);
4816 void __iomem *ioaddr = tp->mmio_addr;
4817 unsigned long flags;
4818 u32 mc_filter[2]; /* Multicast hash filter */
07d3f51f 4819 int rx_mode;
1da177e4
LT		 4820 u32 tmp = 0;
4821
4822 if (dev->flags & IFF_PROMISC) {
4823 /* Unconditionally log net taps. */
bf82c189 4824 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
1da177e4
LT		 4825 rx_mode =
4826 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4827 AcceptAllPhys;
4828 mc_filter[1] = mc_filter[0] = 0xffffffff;
4cd24eaf 4829 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
8e95a202 4830 (dev->flags & IFF_ALLMULTI)) {
1da177e4
LT		 4831 /* Too many to filter perfectly -- accept all multicasts. */
4832 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4833 mc_filter[1] = mc_filter[0] = 0xffffffff;
4834 } else {
22bedad3 4835 struct netdev_hw_addr *ha;
07d3f51f 4836
1da177e4
LT		 4837 rx_mode = AcceptBroadcast | AcceptMyPhys;
4838 mc_filter[1] = mc_filter[0] = 0;
22bedad3
JP		 4839 netdev_for_each_mc_addr(ha, dev) {
4840 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1da177e4
LT		 4841 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4842 rx_mode |= AcceptMulticast;
4843 }
4844 }
4845
4846 spin_lock_irqsave(&tp->lock, flags);
4847
4848 tmp = rtl8169_rx_config | rx_mode |
4849 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4850
f887cce8 4851 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
1087f4f4
FR		 4852 u32 data = mc_filter[0];
4853
4854 mc_filter[0] = swab32(mc_filter[1]);
4855 mc_filter[1] = swab32(data);
bcf0bf90
FR		 4856 }
4857
1da177e4 4858 RTL_W32(MAR0 + 4, mc_filter[1]);
78f1cd02 4859 RTL_W32(MAR0 + 0, mc_filter[0]);
1da177e4 4860
57a9f236
FR		 4861 RTL_W32(RxConfig, tmp);
4862
1da177e4
LT		 4863 spin_unlock_irqrestore(&tp->lock, flags);
4864}
4865
4866/**
4867 * rtl8169_get_stats - Get rtl8169 read/write statistics
4868 * @dev: The Ethernet Device to get statistics for
4869 *
4870 * Get TX/RX statistics for rtl8169
4871 */
4872static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4873{
4874 struct rtl8169_private *tp = netdev_priv(dev);
4875 void __iomem *ioaddr = tp->mmio_addr;
4876 unsigned long flags;
4877
4878 if (netif_running(dev)) {
4879 spin_lock_irqsave(&tp->lock, flags);
523a6094 4880 rtl8169_rx_missed(dev, ioaddr);
1da177e4
LT		 4881 spin_unlock_irqrestore(&tp->lock, flags);
4882 }
5b0384f4 4883
cebf8cc7 4884 return &dev->stats;
1da177e4
LT		 4885}
4886
861ab440 4887static void rtl8169_net_suspend(struct net_device *dev)
5d06a99f 4888{
065c27c1 4889 struct rtl8169_private *tp = netdev_priv(dev);
4890
5d06a99f 4891 if (!netif_running(dev))
861ab440 4892 return;
5d06a99f 4893
065c27c1 4894 rtl_pll_power_down(tp);
4895
5d06a99f
FR		 4896 netif_device_detach(dev);
4897 netif_stop_queue(dev);
861ab440
RW		 4898}
4899
4900#ifdef CONFIG_PM
4901
4902static int rtl8169_suspend(struct device *device)
4903{
4904 struct pci_dev *pdev = to_pci_dev(device);
4905 struct net_device *dev = pci_get_drvdata(pdev);
5d06a99f 4906
861ab440 4907 rtl8169_net_suspend(dev);
1371fa6d 4908
5d06a99f
FR		 4909 return 0;
4910}
4911
e1759441
RW		 4912static void __rtl8169_resume(struct net_device *dev)
4913{
065c27c1 4914 struct rtl8169_private *tp = netdev_priv(dev);
4915
e1759441 4916 netif_device_attach(dev);
065c27c1 4917
4918 rtl_pll_power_up(tp);
4919
e1759441
RW		 4920 rtl8169_schedule_work(dev, rtl8169_reset_task);
4921}
4922
861ab440 4923static int rtl8169_resume(struct device *device)
5d06a99f 4924{
861ab440 4925 struct pci_dev *pdev = to_pci_dev(device);
5d06a99f 4926 struct net_device *dev = pci_get_drvdata(pdev);
fccec10b
SG		 4927 struct rtl8169_private *tp = netdev_priv(dev);
4928
4929 rtl8169_init_phy(dev, tp);
5d06a99f 4930
e1759441
RW		 4931 if (netif_running(dev))
4932 __rtl8169_resume(dev);
5d06a99f 4933
e1759441
RW		 4934 return 0;
4935}
4936
4937static int rtl8169_runtime_suspend(struct device *device)
4938{
4939 struct pci_dev *pdev = to_pci_dev(device);
4940 struct net_device *dev = pci_get_drvdata(pdev);
4941 struct rtl8169_private *tp = netdev_priv(dev);
4942
4943 if (!tp->TxDescArray)
4944 return 0;
4945
4946 spin_lock_irq(&tp->lock);
4947 tp->saved_wolopts = __rtl8169_get_wol(tp);
4948 __rtl8169_set_wol(tp, WAKE_ANY);
4949 spin_unlock_irq(&tp->lock);
4950
4951 rtl8169_net_suspend(dev);
4952
4953 return 0;
4954}
4955
4956static int rtl8169_runtime_resume(struct device *device)
4957{
4958 struct pci_dev *pdev = to_pci_dev(device);
4959 struct net_device *dev = pci_get_drvdata(pdev);
4960 struct rtl8169_private *tp = netdev_priv(dev);
4961
4962 if (!tp->TxDescArray)
4963 return 0;
4964
4965 spin_lock_irq(&tp->lock);
4966 __rtl8169_set_wol(tp, tp->saved_wolopts);
4967 tp->saved_wolopts = 0;
4968 spin_unlock_irq(&tp->lock);
4969
fccec10b
SG		 4970 rtl8169_init_phy(dev, tp);
4971
e1759441 4972 __rtl8169_resume(dev);
5d06a99f 4973
5d06a99f
FR		 4974 return 0;
4975}
4976
e1759441
RW		 4977static int rtl8169_runtime_idle(struct device *device)
4978{
4979 struct pci_dev *pdev = to_pci_dev(device);
4980 struct net_device *dev = pci_get_drvdata(pdev);
4981 struct rtl8169_private *tp = netdev_priv(dev);
4982
e4fbce74 4983 return tp->TxDescArray ? -EBUSY : 0;
e1759441
RW		 4984}
4985
47145210 4986static const struct dev_pm_ops rtl8169_pm_ops = {
861ab440
RW		 4987 .suspend = rtl8169_suspend,
4988 .resume = rtl8169_resume,
4989 .freeze = rtl8169_suspend,
4990 .thaw = rtl8169_resume,
4991 .poweroff = rtl8169_suspend,
4992 .restore = rtl8169_resume,
e1759441
RW		 4993 .runtime_suspend = rtl8169_runtime_suspend,
4994 .runtime_resume = rtl8169_runtime_resume,
4995 .runtime_idle = rtl8169_runtime_idle,
861ab440
RW		 4996};
4997
4998#define RTL8169_PM_OPS (&rtl8169_pm_ops)
4999
5000#else /* !CONFIG_PM */
5001
5002#define RTL8169_PM_OPS NULL
5003
5004#endif /* !CONFIG_PM */
5005
1765f95d
FR		 5006static void rtl_shutdown(struct pci_dev *pdev)
5007{
861ab440 5008 struct net_device *dev = pci_get_drvdata(pdev);
4bb3f522 5009 struct rtl8169_private *tp = netdev_priv(dev);
5010 void __iomem *ioaddr = tp->mmio_addr;
861ab440
RW		 5011
5012 rtl8169_net_suspend(dev);
1765f95d 5013
cc098dc7
IV		 5014 /* restore original MAC address */
5015 rtl_rar_set(tp, dev->perm_addr);
5016
4bb3f522 5017 spin_lock_irq(&tp->lock);
5018
5019 rtl8169_asic_down(ioaddr);
5020
5021 spin_unlock_irq(&tp->lock);
5022
861ab440 5023 if (system_state == SYSTEM_POWER_OFF) {
ca52efd5 5024 /* WoL fails with some 8168 when the receiver is disabled. */
5025 if (tp->features & RTL_FEATURE_WOL) {
5026 pci_clear_master(pdev);
5027
5028 RTL_W8(ChipCmd, CmdRxEnb);
5029 /* PCI commit */
5030 RTL_R8(ChipCmd);
5031 }
5032
861ab440
RW		 5033 pci_wake_from_d3(pdev, true);
5034 pci_set_power_state(pdev, PCI_D3hot);
5035 }
5036}
5d06a99f 5037
1da177e4
LT		 5038static struct pci_driver rtl8169_pci_driver = {
5039 .name = MODULENAME,
5040 .id_table = rtl8169_pci_tbl,
5041 .probe = rtl8169_init_one,
5042 .remove = __devexit_p(rtl8169_remove_one),
1765f95d 5043 .shutdown = rtl_shutdown,
861ab440 5044 .driver.pm = RTL8169_PM_OPS,
1da177e4
LT		 5045};
5046
07d3f51f 5047static int __init rtl8169_init_module(void)
1da177e4 5048{
29917620 5049 return pci_register_driver(&rtl8169_pci_driver);
1da177e4
LT		 5050}
5051
07d3f51f 5052static void __exit rtl8169_cleanup_module(void)
1da177e4
LT		 5053{
5054 pci_unregister_driver(&rtl8169_pci_driver);
5055}
5056
5057module_init(rtl8169_init_module);
5058module_exit(rtl8169_cleanup_module);
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