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[mirror_ubuntu-bionic-kernel.git] / drivers / net / s2io.c
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1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
eccb8628 40 * 2(MSI_X). Default value is '0(INTA)'
9dc737a7
AR		 41 * lro: Specifies whether to enable Large Receive Offload (LRO) or not.
42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
1da177e4
LT		 53 ************************************************************************/
54
1da177e4
LT		 55#include <linux/module.h>
56#include <linux/types.h>
57#include <linux/errno.h>
58#include <linux/ioport.h>
59#include <linux/pci.h>
1e7f0bd8 60#include <linux/dma-mapping.h>
1da177e4
LT		 61#include <linux/kernel.h>
62#include <linux/netdevice.h>
63#include <linux/etherdevice.h>
64#include <linux/skbuff.h>
65#include <linux/init.h>
66#include <linux/delay.h>
67#include <linux/stddef.h>
68#include <linux/ioctl.h>
69#include <linux/timex.h>
1da177e4 70#include <linux/ethtool.h>
1da177e4 71#include <linux/workqueue.h>
be3a6b02 72#include <linux/if_vlan.h>
7d3d0439
RA		 73#include <linux/ip.h>
74#include <linux/tcp.h>
75#include <net/tcp.h>
1da177e4 76
1da177e4
LT		 77#include <asm/system.h>
78#include <asm/uaccess.h>
20346722 79#include <asm/io.h>
fe931395 80#include <asm/div64.h>
330ce0de 81#include <asm/irq.h>
1da177e4
LT		 82
83/* local include */
84#include "s2io.h"
85#include "s2io-regs.h"
86
573608e4 87#define DRV_VERSION "2.0.25.1"
6c1792f4 88
1da177e4 89/* S2io Driver name & version. */
20346722 90static char s2io_driver_name[] = "Neterion";
6c1792f4 91static char s2io_driver_version[] = DRV_VERSION;
1da177e4 92
6d517a27
VP		 93static int rxd_size[2] = {32,48};
94static int rxd_count[2] = {127,85};
da6971d8 95
1ee6dd77 96static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 97{
98 int ret;
99
100 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
101 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
102
103 return ret;
104}
105
20346722 106/*
1da177e4
LT		 107 * Cards with following subsystem_id have a link state indication
108 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109 * macro below identifies these cards given the subsystem_id.
110 */
541ae68f
K		 111#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112 (dev_type == XFRAME_I_DEVICE) ? \
113 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 115
116#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
119#define PANIC 1
120#define LOW 2
1ee6dd77 121static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
1da177e4 122{
1ee6dd77 123 struct mac_info *mac_control;
20346722
K		 124
125 mac_control = &sp->mac_control;
863c11a9
AR		 126 if (rxb_size <= rxd_count[sp->rxd_mode])
127 return PANIC;
128 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
129 return LOW;
130 return 0;
1da177e4
LT		 131}
132
133/* Ethtool related variables and Macros. */
134static char s2io_gstrings[][ETH_GSTRING_LEN] = {
135 "Register test\t(offline)",
136 "Eeprom test\t(offline)",
137 "Link test\t(online)",
138 "RLDRAM test\t(offline)",
139 "BIST Test\t(offline)"
140};
141
fa1f0cb3 142static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 143 {"tmac_frms"},
144 {"tmac_data_octets"},
145 {"tmac_drop_frms"},
146 {"tmac_mcst_frms"},
147 {"tmac_bcst_frms"},
148 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 149 {"tmac_ttl_octets"},
150 {"tmac_ucst_frms"},
151 {"tmac_nucst_frms"},
1da177e4 152 {"tmac_any_err_frms"},
bd1034f0 153 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 154 {"tmac_vld_ip_octets"},
155 {"tmac_vld_ip"},
156 {"tmac_drop_ip"},
157 {"tmac_icmp"},
158 {"tmac_rst_tcp"},
159 {"tmac_tcp"},
160 {"tmac_udp"},
161 {"rmac_vld_frms"},
162 {"rmac_data_octets"},
163 {"rmac_fcs_err_frms"},
164 {"rmac_drop_frms"},
165 {"rmac_vld_mcst_frms"},
166 {"rmac_vld_bcst_frms"},
167 {"rmac_in_rng_len_err_frms"},
bd1034f0 168 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 169 {"rmac_long_frms"},
170 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 171 {"rmac_unsup_ctrl_frms"},
172 {"rmac_ttl_octets"},
173 {"rmac_accepted_ucst_frms"},
174 {"rmac_accepted_nucst_frms"},
1da177e4 175 {"rmac_discarded_frms"},
bd1034f0
AR		 176 {"rmac_drop_events"},
177 {"rmac_ttl_less_fb_octets"},
178 {"rmac_ttl_frms"},
1da177e4
LT		 179 {"rmac_usized_frms"},
180 {"rmac_osized_frms"},
181 {"rmac_frag_frms"},
182 {"rmac_jabber_frms"},
bd1034f0
AR		 183 {"rmac_ttl_64_frms"},
184 {"rmac_ttl_65_127_frms"},
185 {"rmac_ttl_128_255_frms"},
186 {"rmac_ttl_256_511_frms"},
187 {"rmac_ttl_512_1023_frms"},
188 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 189 {"rmac_ip"},
190 {"rmac_ip_octets"},
191 {"rmac_hdr_err_ip"},
192 {"rmac_drop_ip"},
193 {"rmac_icmp"},
194 {"rmac_tcp"},
195 {"rmac_udp"},
196 {"rmac_err_drp_udp"},
bd1034f0
AR		 197 {"rmac_xgmii_err_sym"},
198 {"rmac_frms_q0"},
199 {"rmac_frms_q1"},
200 {"rmac_frms_q2"},
201 {"rmac_frms_q3"},
202 {"rmac_frms_q4"},
203 {"rmac_frms_q5"},
204 {"rmac_frms_q6"},
205 {"rmac_frms_q7"},
206 {"rmac_full_q0"},
207 {"rmac_full_q1"},
208 {"rmac_full_q2"},
209 {"rmac_full_q3"},
210 {"rmac_full_q4"},
211 {"rmac_full_q5"},
212 {"rmac_full_q6"},
213 {"rmac_full_q7"},
1da177e4 214 {"rmac_pause_cnt"},
bd1034f0
AR		 215 {"rmac_xgmii_data_err_cnt"},
216 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 217 {"rmac_accepted_ip"},
218 {"rmac_err_tcp"},
bd1034f0
AR		 219 {"rd_req_cnt"},
220 {"new_rd_req_cnt"},
221 {"new_rd_req_rtry_cnt"},
222 {"rd_rtry_cnt"},
223 {"wr_rtry_rd_ack_cnt"},
224 {"wr_req_cnt"},
225 {"new_wr_req_cnt"},
226 {"new_wr_req_rtry_cnt"},
227 {"wr_rtry_cnt"},
228 {"wr_disc_cnt"},
229 {"rd_rtry_wr_ack_cnt"},
230 {"txp_wr_cnt"},
231 {"txd_rd_cnt"},
232 {"txd_wr_cnt"},
233 {"rxd_rd_cnt"},
234 {"rxd_wr_cnt"},
235 {"txf_rd_cnt"},
fa1f0cb3
SS		 236 {"rxf_wr_cnt"}
237};
238
239static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 240 {"rmac_ttl_1519_4095_frms"},
241 {"rmac_ttl_4096_8191_frms"},
242 {"rmac_ttl_8192_max_frms"},
243 {"rmac_ttl_gt_max_frms"},
244 {"rmac_osized_alt_frms"},
245 {"rmac_jabber_alt_frms"},
246 {"rmac_gt_max_alt_frms"},
247 {"rmac_vlan_frms"},
248 {"rmac_len_discard"},
249 {"rmac_fcs_discard"},
250 {"rmac_pf_discard"},
251 {"rmac_da_discard"},
252 {"rmac_red_discard"},
253 {"rmac_rts_discard"},
254 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 255 {"link_fault_cnt"}
256};
257
258static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 259 {"\n DRIVER STATISTICS"},
260 {"single_bit_ecc_errs"},
261 {"double_bit_ecc_errs"},
bd1034f0
AR		 262 {"parity_err_cnt"},
263 {"serious_err_cnt"},
264 {"soft_reset_cnt"},
265 {"fifo_full_cnt"},
266 {"ring_full_cnt"},
267 ("alarm_transceiver_temp_high"),
268 ("alarm_transceiver_temp_low"),
269 ("alarm_laser_bias_current_high"),
270 ("alarm_laser_bias_current_low"),
271 ("alarm_laser_output_power_high"),
272 ("alarm_laser_output_power_low"),
273 ("warn_transceiver_temp_high"),
274 ("warn_transceiver_temp_low"),
275 ("warn_laser_bias_current_high"),
276 ("warn_laser_bias_current_low"),
277 ("warn_laser_output_power_high"),
278 ("warn_laser_output_power_low"),
7d3d0439
RA		 279 ("lro_aggregated_pkts"),
280 ("lro_flush_both_count"),
281 ("lro_out_of_sequence_pkts"),
282 ("lro_flush_due_to_max_pkts"),
283 ("lro_avg_aggr_pkts"),
c53d4945 284 ("mem_alloc_fail_cnt"),
491abf25 285 ("pci_map_fail_cnt"),
491976b2
SH		 286 ("watchdog_timer_cnt"),
287 ("mem_allocated"),
288 ("mem_freed"),
289 ("link_up_cnt"),
290 ("link_down_cnt"),
291 ("link_up_time"),
292 ("link_down_time"),
293 ("tx_tcode_buf_abort_cnt"),
294 ("tx_tcode_desc_abort_cnt"),
295 ("tx_tcode_parity_err_cnt"),
296 ("tx_tcode_link_loss_cnt"),
297 ("tx_tcode_list_proc_err_cnt"),
298 ("rx_tcode_parity_err_cnt"),
299 ("rx_tcode_abort_cnt"),
300 ("rx_tcode_parity_abort_cnt"),
301 ("rx_tcode_rda_fail_cnt"),
302 ("rx_tcode_unkn_prot_cnt"),
303 ("rx_tcode_fcs_err_cnt"),
304 ("rx_tcode_buf_size_err_cnt"),
305 ("rx_tcode_rxd_corrupt_cnt"),
306 ("rx_tcode_unkn_err_cnt")
1da177e4
LT		 307};
308
fa1f0cb3
SS		 309#define S2IO_XENA_STAT_LEN sizeof(ethtool_xena_stats_keys)/ ETH_GSTRING_LEN
310#define S2IO_ENHANCED_STAT_LEN sizeof(ethtool_enhanced_stats_keys)/ \
311 ETH_GSTRING_LEN
312#define S2IO_DRIVER_STAT_LEN sizeof(ethtool_driver_stats_keys)/ ETH_GSTRING_LEN
313
314#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
315#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
316
317#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
318#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4
LT		 319
320#define S2IO_TEST_LEN sizeof(s2io_gstrings) / ETH_GSTRING_LEN
321#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
322
25fff88e
K		 323#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
324 init_timer(&timer); \
325 timer.function = handle; \
326 timer.data = (unsigned long) arg; \
327 mod_timer(&timer, (jiffies + exp)) \
328
be3a6b02
K		 329/* Add the vlan */
330static void s2io_vlan_rx_register(struct net_device *dev,
331 struct vlan_group *grp)
332{
1ee6dd77 333 struct s2io_nic *nic = dev->priv;
be3a6b02
K		 334 unsigned long flags;
335
336 spin_lock_irqsave(&nic->tx_lock, flags);
337 nic->vlgrp = grp;
338 spin_unlock_irqrestore(&nic->tx_lock, flags);
339}
340
926930b2 341/* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
7b490343 342static int vlan_strip_flag;
926930b2 343
20346722 344/*
1da177e4
LT		 345 * Constants to be programmed into the Xena's registers, to configure
346 * the XAUI.
347 */
348
1da177e4 349#define END_SIGN 0x0
f71e1309 350static const u64 herc_act_dtx_cfg[] = {
541ae68f 351 /* Set address */
e960fc5c 352 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 353 /* Write data */
e960fc5c 354 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 355 /* Set address */
356 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
357 /* Write data */
358 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
359 /* Set address */
e960fc5c 360 0x801205150D440000ULL, 0x801205150D4400E0ULL,
361 /* Write data */
362 0x801205150D440004ULL, 0x801205150D4400E4ULL,
363 /* Set address */
541ae68f
K		 364 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
365 /* Write data */
366 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
367 /* Done */
368 END_SIGN
369};
370
f71e1309 371static const u64 xena_dtx_cfg[] = {
c92ca04b 372 /* Set address */
1da177e4 373 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 374 /* Write data */
375 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
376 /* Set address */
377 0x8001051500000000ULL, 0x80010515000000E0ULL,
378 /* Write data */
379 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
380 /* Set address */
1da177e4 381 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 382 /* Write data */
383 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 384 END_SIGN
385};
386
20346722 387/*
1da177e4
LT		 388 * Constants for Fixing the MacAddress problem seen mostly on
389 * Alpha machines.
390 */
f71e1309 391static const u64 fix_mac[] = {
1da177e4
LT		 392 0x0060000000000000ULL, 0x0060600000000000ULL,
393 0x0040600000000000ULL, 0x0000600000000000ULL,
394 0x0020600000000000ULL, 0x0060600000000000ULL,
395 0x0020600000000000ULL, 0x0060600000000000ULL,
396 0x0020600000000000ULL, 0x0060600000000000ULL,
397 0x0020600000000000ULL, 0x0060600000000000ULL,
398 0x0020600000000000ULL, 0x0060600000000000ULL,
399 0x0020600000000000ULL, 0x0060600000000000ULL,
400 0x0020600000000000ULL, 0x0060600000000000ULL,
401 0x0020600000000000ULL, 0x0060600000000000ULL,
402 0x0020600000000000ULL, 0x0060600000000000ULL,
403 0x0020600000000000ULL, 0x0060600000000000ULL,
404 0x0020600000000000ULL, 0x0000600000000000ULL,
405 0x0040600000000000ULL, 0x0060600000000000ULL,
406 END_SIGN
407};
408
b41477f3
AR		 409MODULE_LICENSE("GPL");
410MODULE_VERSION(DRV_VERSION);
411
412
1da177e4 413/* Module Loadable parameters. */
b41477f3
AR		 414S2IO_PARM_INT(tx_fifo_num, 1);
415S2IO_PARM_INT(rx_ring_num, 1);
416
417
418S2IO_PARM_INT(rx_ring_mode, 1);
419S2IO_PARM_INT(use_continuous_tx_intrs, 1);
420S2IO_PARM_INT(rmac_pause_time, 0x100);
421S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
422S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
423S2IO_PARM_INT(shared_splits, 0);
424S2IO_PARM_INT(tmac_util_period, 5);
425S2IO_PARM_INT(rmac_util_period, 5);
426S2IO_PARM_INT(bimodal, 0);
427S2IO_PARM_INT(l3l4hdr_size, 128);
303bcb4b 428/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 429S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 430/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
b41477f3 431S2IO_PARM_INT(intr_type, 0);
7d3d0439 432/* Large receive offload feature */
b41477f3 433S2IO_PARM_INT(lro, 0);
7d3d0439
RA		 434/* Max pkts to be aggregated by LRO at one time. If not specified,
435 * aggregation happens until we hit max IP pkt size(64K)
436 */
b41477f3 437S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 438S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 439
440S2IO_PARM_INT(napi, 1);
441S2IO_PARM_INT(ufo, 0);
926930b2 442S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 443
444static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
445 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
446static unsigned int rx_ring_sz[MAX_RX_RINGS] =
447 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
448static unsigned int rts_frm_len[MAX_RX_RINGS] =
449 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
450
451module_param_array(tx_fifo_len, uint, NULL, 0);
452module_param_array(rx_ring_sz, uint, NULL, 0);
453module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 454
20346722 455/*
1da177e4 456 * S2IO device table.
20346722 457 * This table lists all the devices that this driver supports.
1da177e4
LT		 458 */
459static struct pci_device_id s2io_tbl[] __devinitdata = {
460 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
461 PCI_ANY_ID, PCI_ANY_ID},
462 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
463 PCI_ANY_ID, PCI_ANY_ID},
464 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722
K		 465 PCI_ANY_ID, PCI_ANY_ID},
466 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
467 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 468 {0,}
469};
470
471MODULE_DEVICE_TABLE(pci, s2io_tbl);
472
d796fdb7
LV		 473static struct pci_error_handlers s2io_err_handler = {
474 .error_detected = s2io_io_error_detected,
475 .slot_reset = s2io_io_slot_reset,
476 .resume = s2io_io_resume,
477};
478
1da177e4
LT		 479static struct pci_driver s2io_driver = {
480 .name = "S2IO",
481 .id_table = s2io_tbl,
482 .probe = s2io_init_nic,
483 .remove = __devexit_p(s2io_rem_nic),
d796fdb7 484 .err_handler = &s2io_err_handler,
1da177e4
LT		 485};
486
487/* A simplifier macro used both by init and free shared_mem Fns(). */
488#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
489
490/**
491 * init_shared_mem - Allocation and Initialization of Memory
492 * @nic: Device private variable.
20346722
K		 493 * Description: The function allocates all the memory areas shared
494 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 495 * Rx descriptors and the statistics block.
496 */
497
498static int init_shared_mem(struct s2io_nic *nic)
499{
500 u32 size;
501 void *tmp_v_addr, *tmp_v_addr_next;
502 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 503 struct RxD_block *pre_rxd_blk = NULL;
372cc597 504 int i, j, blk_cnt;
1da177e4
LT		 505 int lst_size, lst_per_page;
506 struct net_device *dev = nic->dev;
8ae418cf 507 unsigned long tmp;
1ee6dd77 508 struct buffAdd *ba;
1da177e4 509
1ee6dd77 510 struct mac_info *mac_control;
1da177e4 511 struct config_param *config;
491976b2 512 unsigned long long mem_allocated = 0;
1da177e4
LT		 513
514 mac_control = &nic->mac_control;
515 config = &nic->config;
516
517
518 /* Allocation and initialization of TXDLs in FIOFs */
519 size = 0;
520 for (i = 0; i < config->tx_fifo_num; i++) {
521 size += config->tx_cfg[i].fifo_len;
522 }
523 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 524 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 525 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 526 return -EINVAL;
1da177e4
LT		 527 }
528
1ee6dd77 529 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 530 lst_per_page = PAGE_SIZE / lst_size;
531
532 for (i = 0; i < config->tx_fifo_num; i++) {
533 int fifo_len = config->tx_cfg[i].fifo_len;
1ee6dd77 534 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
20346722
K		 535 mac_control->fifos[i].list_info = kmalloc(list_holder_size,
536 GFP_KERNEL);
537 if (!mac_control->fifos[i].list_info) {
0c61ed5f 538 DBG_PRINT(INFO_DBG,
1da177e4
LT		 539 "Malloc failed for list_info\n");
540 return -ENOMEM;
541 }
491976b2 542 mem_allocated += list_holder_size;
20346722 543 memset(mac_control->fifos[i].list_info, 0, list_holder_size);
1da177e4
LT		 544 }
545 for (i = 0; i < config->tx_fifo_num; i++) {
546 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
547 lst_per_page);
20346722
K		 548 mac_control->fifos[i].tx_curr_put_info.offset = 0;
549 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 550 config->tx_cfg[i].fifo_len - 1;
20346722
K		 551 mac_control->fifos[i].tx_curr_get_info.offset = 0;
552 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 553 config->tx_cfg[i].fifo_len - 1;
20346722
K		 554 mac_control->fifos[i].fifo_no = i;
555 mac_control->fifos[i].nic = nic;
fed5eccd 556 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
20346722 557
1da177e4
LT		 558 for (j = 0; j < page_num; j++) {
559 int k = 0;
560 dma_addr_t tmp_p;
561 void *tmp_v;
562 tmp_v = pci_alloc_consistent(nic->pdev,
563 PAGE_SIZE, &tmp_p);
564 if (!tmp_v) {
0c61ed5f 565 DBG_PRINT(INFO_DBG,
1da177e4 566 "pci_alloc_consistent ");
0c61ed5f 567 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 568 return -ENOMEM;
569 }
776bd20f 570 /* If we got a zero DMA address(can happen on
571 * certain platforms like PPC), reallocate.
572 * Store virtual address of page we don't want,
573 * to be freed later.
574 */
575 if (!tmp_p) {
576 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 577 DBG_PRINT(INIT_DBG,
776bd20f 578 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 579 DBG_PRINT(INIT_DBG,
6b4d617d 580 "Virtual address %p\n", tmp_v);
776bd20f 581 tmp_v = pci_alloc_consistent(nic->pdev,
582 PAGE_SIZE, &tmp_p);
583 if (!tmp_v) {
0c61ed5f 584 DBG_PRINT(INFO_DBG,
776bd20f 585 "pci_alloc_consistent ");
0c61ed5f 586 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
776bd20f 587 return -ENOMEM;
588 }
491976b2 589 mem_allocated += PAGE_SIZE;
776bd20f 590 }
1da177e4
LT		 591 while (k < lst_per_page) {
592 int l = (j * lst_per_page) + k;
593 if (l == config->tx_cfg[i].fifo_len)
20346722
K		 594 break;
595 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 596 tmp_v + (k * lst_size);
20346722 597 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 598 tmp_p + (k * lst_size);
599 k++;
600 }
601 }
602 }
1da177e4 603
4384247b 604 nic->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
fed5eccd
AR		 605 if (!nic->ufo_in_band_v)
606 return -ENOMEM;
491976b2 607 mem_allocated += (size * sizeof(u64));
fed5eccd 608
1da177e4
LT		 609 /* Allocation and initialization of RXDs in Rings */
610 size = 0;
611 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 612 if (config->rx_cfg[i].num_rxd %
613 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 614 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
615 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
616 i);
617 DBG_PRINT(ERR_DBG, "RxDs per Block");
618 return FAILURE;
619 }
620 size += config->rx_cfg[i].num_rxd;
20346722 621 mac_control->rings[i].block_count =
da6971d8
AR		 622 config->rx_cfg[i].num_rxd /
623 (rxd_count[nic->rxd_mode] + 1 );
624 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
625 mac_control->rings[i].block_count;
1da177e4 626 }
da6971d8 627 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 628 size = (size * (sizeof(struct RxD1)));
da6971d8 629 else
1ee6dd77 630 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 631
632 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 633 mac_control->rings[i].rx_curr_get_info.block_index = 0;
634 mac_control->rings[i].rx_curr_get_info.offset = 0;
635 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 636 config->rx_cfg[i].num_rxd - 1;
20346722
K		 637 mac_control->rings[i].rx_curr_put_info.block_index = 0;
638 mac_control->rings[i].rx_curr_put_info.offset = 0;
639 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 640 config->rx_cfg[i].num_rxd - 1;
20346722
K		 641 mac_control->rings[i].nic = nic;
642 mac_control->rings[i].ring_no = i;
643
da6971d8
AR		 644 blk_cnt = config->rx_cfg[i].num_rxd /
645 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 646 /* Allocating all the Rx blocks */
647 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 648 struct rx_block_info *rx_blocks;
da6971d8
AR		 649 int l;
650
651 rx_blocks = &mac_control->rings[i].rx_blocks[j];
652 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 653 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
654 &tmp_p_addr);
655 if (tmp_v_addr == NULL) {
656 /*
20346722
K		 657 * In case of failure, free_shared_mem()
658 * is called, which should free any
659 * memory that was alloced till the
1da177e4
LT		 660 * failure happened.
661 */
da6971d8 662 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 663 return -ENOMEM;
664 }
491976b2 665 mem_allocated += size;
1da177e4 666 memset(tmp_v_addr, 0, size);
da6971d8
AR		 667 rx_blocks->block_virt_addr = tmp_v_addr;
668 rx_blocks->block_dma_addr = tmp_p_addr;
1ee6dd77 669 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
da6971d8
AR		 670 rxd_count[nic->rxd_mode],
671 GFP_KERNEL);
372cc597
SS		 672 if (!rx_blocks->rxds)
673 return -ENOMEM;
491976b2
SH		 674 mem_allocated +=
675 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
da6971d8
AR		 676 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
677 rx_blocks->rxds[l].virt_addr =
678 rx_blocks->block_virt_addr +
679 (rxd_size[nic->rxd_mode] * l);
680 rx_blocks->rxds[l].dma_addr =
681 rx_blocks->block_dma_addr +
682 (rxd_size[nic->rxd_mode] * l);
683 }
1da177e4
LT		 684 }
685 /* Interlinking all Rx Blocks */
686 for (j = 0; j < blk_cnt; j++) {
20346722
K		 687 tmp_v_addr =
688 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 689 tmp_v_addr_next =
20346722 690 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 691 blk_cnt].block_virt_addr;
20346722
K		 692 tmp_p_addr =
693 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 694 tmp_p_addr_next =
20346722 695 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 696 blk_cnt].block_dma_addr;
697
1ee6dd77 698 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 699 pre_rxd_blk->reserved_2_pNext_RxD_block =
700 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 701 pre_rxd_blk->pNext_RxD_Blk_physical =
702 (u64) tmp_p_addr_next;
703 }
704 }
6d517a27 705 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 706 /*
707 * Allocation of Storages for buffer addresses in 2BUFF mode
708 * and the buffers as well.
709 */
710 for (i = 0; i < config->rx_ring_num; i++) {
711 blk_cnt = config->rx_cfg[i].num_rxd /
712 (rxd_count[nic->rxd_mode]+ 1);
713 mac_control->rings[i].ba =
1ee6dd77 714 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
1da177e4 715 GFP_KERNEL);
da6971d8 716 if (!mac_control->rings[i].ba)
1da177e4 717 return -ENOMEM;
491976b2 718 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
da6971d8
AR		 719 for (j = 0; j < blk_cnt; j++) {
720 int k = 0;
721 mac_control->rings[i].ba[j] =
1ee6dd77 722 kmalloc((sizeof(struct buffAdd) *
da6971d8
AR		 723 (rxd_count[nic->rxd_mode] + 1)),
724 GFP_KERNEL);
725 if (!mac_control->rings[i].ba[j])
1da177e4 726 return -ENOMEM;
491976b2
SH		 727 mem_allocated += (sizeof(struct buffAdd) * \
728 (rxd_count[nic->rxd_mode] + 1));
da6971d8
AR		 729 while (k != rxd_count[nic->rxd_mode]) {
730 ba = &mac_control->rings[i].ba[j][k];
731
732 ba->ba_0_org = (void *) kmalloc
733 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
734 if (!ba->ba_0_org)
735 return -ENOMEM;
491976b2
SH		 736 mem_allocated +=
737 (BUF0_LEN + ALIGN_SIZE);
da6971d8
AR		 738 tmp = (unsigned long)ba->ba_0_org;
739 tmp += ALIGN_SIZE;
740 tmp &= ~((unsigned long) ALIGN_SIZE);
741 ba->ba_0 = (void *) tmp;
742
743 ba->ba_1_org = (void *) kmalloc
744 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
745 if (!ba->ba_1_org)
746 return -ENOMEM;
491976b2
SH		 747 mem_allocated
748 += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 749 tmp = (unsigned long) ba->ba_1_org;
750 tmp += ALIGN_SIZE;
751 tmp &= ~((unsigned long) ALIGN_SIZE);
752 ba->ba_1 = (void *) tmp;
753 k++;
754 }
1da177e4
LT		 755 }
756 }
757 }
1da177e4
LT		 758
759 /* Allocation and initialization of Statistics block */
1ee6dd77 760 size = sizeof(struct stat_block);
1da177e4
LT		 761 mac_control->stats_mem = pci_alloc_consistent
762 (nic->pdev, size, &mac_control->stats_mem_phy);
763
764 if (!mac_control->stats_mem) {
20346722
K		 765 /*
766 * In case of failure, free_shared_mem() is called, which
767 * should free any memory that was alloced till the
1da177e4
LT		 768 * failure happened.
769 */
770 return -ENOMEM;
771 }
491976b2 772 mem_allocated += size;
1da177e4
LT		 773 mac_control->stats_mem_sz = size;
774
775 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 776 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 777 memset(tmp_v_addr, 0, size);
1da177e4
LT		 778 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
779 (unsigned long long) tmp_p_addr);
491976b2 780 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 781 return SUCCESS;
782}
783
20346722
K		 784/**
785 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 786 * @nic: Device private variable.
787 * Description: This function is to free all memory locations allocated by
788 * the init_shared_mem() function and return it to the kernel.
789 */
790
791static void free_shared_mem(struct s2io_nic *nic)
792{
793 int i, j, blk_cnt, size;
491976b2 794 u32 ufo_size = 0;
1da177e4
LT		 795 void *tmp_v_addr;
796 dma_addr_t tmp_p_addr;
1ee6dd77 797 struct mac_info *mac_control;
1da177e4
LT		 798 struct config_param *config;
799 int lst_size, lst_per_page;
8910b49f 800 struct net_device *dev;
491976b2 801 int page_num = 0;
1da177e4
LT		 802
803 if (!nic)
804 return;
805
8910b49f
MG		 806 dev = nic->dev;
807
1da177e4
LT		 808 mac_control = &nic->mac_control;
809 config = &nic->config;
810
1ee6dd77 811 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 812 lst_per_page = PAGE_SIZE / lst_size;
813
814 for (i = 0; i < config->tx_fifo_num; i++) {
491976b2
SH		 815 ufo_size += config->tx_cfg[i].fifo_len;
816 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
817 lst_per_page);
1da177e4
LT		 818 for (j = 0; j < page_num; j++) {
819 int mem_blks = (j * lst_per_page);
776bd20f 820 if (!mac_control->fifos[i].list_info)
6aa20a22 821 return;
776bd20f 822 if (!mac_control->fifos[i].list_info[mem_blks].
823 list_virt_addr)
1da177e4
LT		 824 break;
825 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722
K		 826 mac_control->fifos[i].
827 list_info[mem_blks].
1da177e4 828 list_virt_addr,
20346722
K		 829 mac_control->fifos[i].
830 list_info[mem_blks].
1da177e4 831 list_phy_addr);
491976b2
SH		 832 nic->mac_control.stats_info->sw_stat.mem_freed
833 += PAGE_SIZE;
1da177e4 834 }
776bd20f 835 /* If we got a zero DMA address during allocation,
836 * free the page now
837 */
838 if (mac_control->zerodma_virt_addr) {
839 pci_free_consistent(nic->pdev, PAGE_SIZE,
840 mac_control->zerodma_virt_addr,
841 (dma_addr_t)0);
6aa20a22 842 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 843 "%s: Freeing TxDL with zero DMA addr. ",
844 dev->name);
845 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
846 mac_control->zerodma_virt_addr);
491976b2
SH		 847 nic->mac_control.stats_info->sw_stat.mem_freed
848 += PAGE_SIZE;
776bd20f 849 }
20346722 850 kfree(mac_control->fifos[i].list_info);
491976b2
SH		 851 nic->mac_control.stats_info->sw_stat.mem_freed +=
852 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1da177e4
LT		 853 }
854
1da177e4 855 size = SIZE_OF_BLOCK;
1da177e4 856 for (i = 0; i < config->rx_ring_num; i++) {
20346722 857 blk_cnt = mac_control->rings[i].block_count;
1da177e4 858 for (j = 0; j < blk_cnt; j++) {
20346722
K		 859 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
860 block_virt_addr;
861 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
862 block_dma_addr;
1da177e4
LT		 863 if (tmp_v_addr == NULL)
864 break;
865 pci_free_consistent(nic->pdev, size,
866 tmp_v_addr, tmp_p_addr);
491976b2 867 nic->mac_control.stats_info->sw_stat.mem_freed += size;
da6971d8 868 kfree(mac_control->rings[i].rx_blocks[j].rxds);
491976b2
SH		 869 nic->mac_control.stats_info->sw_stat.mem_freed +=
870 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1da177e4
LT		 871 }
872 }
873
6d517a27 874 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 875 /* Freeing buffer storage addresses in 2BUFF mode. */
876 for (i = 0; i < config->rx_ring_num; i++) {
877 blk_cnt = config->rx_cfg[i].num_rxd /
878 (rxd_count[nic->rxd_mode] + 1);
879 for (j = 0; j < blk_cnt; j++) {
880 int k = 0;
881 if (!mac_control->rings[i].ba[j])
882 continue;
883 while (k != rxd_count[nic->rxd_mode]) {
1ee6dd77 884 struct buffAdd *ba =
da6971d8
AR		 885 &mac_control->rings[i].ba[j][k];
886 kfree(ba->ba_0_org);
491976b2
SH		 887 nic->mac_control.stats_info->sw_stat.\
888 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 889 kfree(ba->ba_1_org);
491976b2
SH		 890 nic->mac_control.stats_info->sw_stat.\
891 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 892 k++;
893 }
894 kfree(mac_control->rings[i].ba[j]);
491976b2
SH		 895 nic->mac_control.stats_info->sw_stat.mem_freed += (sizeof(struct buffAdd) *
896 (rxd_count[nic->rxd_mode] + 1));
1da177e4 897 }
da6971d8 898 kfree(mac_control->rings[i].ba);
491976b2
SH		 899 nic->mac_control.stats_info->sw_stat.mem_freed +=
900 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 901 }
1da177e4 902 }
1da177e4
LT		 903
904 if (mac_control->stats_mem) {
905 pci_free_consistent(nic->pdev,
906 mac_control->stats_mem_sz,
907 mac_control->stats_mem,
908 mac_control->stats_mem_phy);
491976b2
SH		 909 nic->mac_control.stats_info->sw_stat.mem_freed +=
910 mac_control->stats_mem_sz;
1da177e4 911 }
491976b2 912 if (nic->ufo_in_band_v) {
fed5eccd 913 kfree(nic->ufo_in_band_v);
491976b2
SH		 914 nic->mac_control.stats_info->sw_stat.mem_freed
915 += (ufo_size * sizeof(u64));
916 }
1da177e4
LT		 917}
918
541ae68f
K		 919/**
920 * s2io_verify_pci_mode -
921 */
922
1ee6dd77 923static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 924{
1ee6dd77 925 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 926 register u64 val64 = 0;
927 int mode;
928
929 val64 = readq(&bar0->pci_mode);
930 mode = (u8)GET_PCI_MODE(val64);
931
932 if ( val64 & PCI_MODE_UNKNOWN_MODE)
933 return -1; /* Unknown PCI mode */
934 return mode;
935}
936
c92ca04b
AR		 937#define NEC_VENID 0x1033
938#define NEC_DEVID 0x0125
939static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
940{
941 struct pci_dev *tdev = NULL;
26d36b64
AC		 942 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
943 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
c92ca04b 944 if (tdev->bus == s2io_pdev->bus->parent)
26d36b64 945 pci_dev_put(tdev);
c92ca04b
AR		 946 return 1;
947 }
948 }
949 return 0;
950}
541ae68f 951
7b32a312 952static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 953/**
954 * s2io_print_pci_mode -
955 */
1ee6dd77 956static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 957{
1ee6dd77 958 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 959 register u64 val64 = 0;
960 int mode;
961 struct config_param *config = &nic->config;
962
963 val64 = readq(&bar0->pci_mode);
964 mode = (u8)GET_PCI_MODE(val64);
965
966 if ( val64 & PCI_MODE_UNKNOWN_MODE)
967 return -1; /* Unknown PCI mode */
968
c92ca04b
AR		 969 config->bus_speed = bus_speed[mode];
970
971 if (s2io_on_nec_bridge(nic->pdev)) {
972 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
973 nic->dev->name);
974 return mode;
975 }
976
541ae68f
K		 977 if (val64 & PCI_MODE_32_BITS) {
978 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
979 } else {
980 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
981 }
982
983 switch(mode) {
984 case PCI_MODE_PCI_33:
985 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f
K		 986 break;
987 case PCI_MODE_PCI_66:
988 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f
K		 989 break;
990 case PCI_MODE_PCIX_M1_66:
991 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f
K		 992 break;
993 case PCI_MODE_PCIX_M1_100:
994 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f
K		 995 break;
996 case PCI_MODE_PCIX_M1_133:
997 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f
K		 998 break;
999 case PCI_MODE_PCIX_M2_66:
1000 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f
K		 1001 break;
1002 case PCI_MODE_PCIX_M2_100:
1003 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f
K		 1004 break;
1005 case PCI_MODE_PCIX_M2_133:
1006 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f
K		 1007 break;
1008 default:
1009 return -1; /* Unsupported bus speed */
1010 }
1011
1012 return mode;
1013}
1014
20346722
K		 1015/**
1016 * init_nic - Initialization of hardware
1da177e4 1017 * @nic: device peivate variable
20346722
K		 1018 * Description: The function sequentially configures every block
1019 * of the H/W from their reset values.
1020 * Return Value: SUCCESS on success and
1da177e4
LT		 1021 * '-1' on failure (endian settings incorrect).
1022 */
1023
1024static int init_nic(struct s2io_nic *nic)
1025{
1ee6dd77 1026 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1027 struct net_device *dev = nic->dev;
1028 register u64 val64 = 0;
1029 void __iomem *add;
1030 u32 time;
1031 int i, j;
1ee6dd77 1032 struct mac_info *mac_control;
1da177e4 1033 struct config_param *config;
c92ca04b 1034 int dtx_cnt = 0;
1da177e4 1035 unsigned long long mem_share;
20346722 1036 int mem_size;
1da177e4
LT		 1037
1038 mac_control = &nic->mac_control;
1039 config = &nic->config;
1040
5e25b9dd 1041 /* to set the swapper controle on the card */
20346722 1042 if(s2io_set_swapper(nic)) {
1da177e4
LT		 1043 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
1044 return -1;
1045 }
1046
541ae68f
K		 1047 /*
1048 * Herc requires EOI to be removed from reset before XGXS, so..
1049 */
1050 if (nic->device_type & XFRAME_II_DEVICE) {
1051 val64 = 0xA500000000ULL;
1052 writeq(val64, &bar0->sw_reset);
1053 msleep(500);
1054 val64 = readq(&bar0->sw_reset);
1055 }
1056
1da177e4
LT		 1057 /* Remove XGXS from reset state */
1058 val64 = 0;
1059 writeq(val64, &bar0->sw_reset);
1da177e4 1060 msleep(500);
20346722 1061 val64 = readq(&bar0->sw_reset);
1da177e4
LT		 1062
1063 /* Enable Receiving broadcasts */
1064 add = &bar0->mac_cfg;
1065 val64 = readq(&bar0->mac_cfg);
1066 val64 |= MAC_RMAC_BCAST_ENABLE;
1067 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1068 writel((u32) val64, add);
1069 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1070 writel((u32) (val64 >> 32), (add + 4));
1071
1072 /* Read registers in all blocks */
1073 val64 = readq(&bar0->mac_int_mask);
1074 val64 = readq(&bar0->mc_int_mask);
1075 val64 = readq(&bar0->xgxs_int_mask);
1076
1077 /* Set MTU */
1078 val64 = dev->mtu;
1079 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1080
541ae68f
K		 1081 if (nic->device_type & XFRAME_II_DEVICE) {
1082 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1083 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1084 &bar0->dtx_control, UF);
541ae68f
K		 1085 if (dtx_cnt & 0x1)
1086 msleep(1); /* Necessary!! */
1da177e4
LT		 1087 dtx_cnt++;
1088 }
541ae68f 1089 } else {
c92ca04b
AR		 1090 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1091 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1092 &bar0->dtx_control, UF);
1093 val64 = readq(&bar0->dtx_control);
1094 dtx_cnt++;
1da177e4
LT		 1095 }
1096 }
1097
1098 /* Tx DMA Initialization */
1099 val64 = 0;
1100 writeq(val64, &bar0->tx_fifo_partition_0);
1101 writeq(val64, &bar0->tx_fifo_partition_1);
1102 writeq(val64, &bar0->tx_fifo_partition_2);
1103 writeq(val64, &bar0->tx_fifo_partition_3);
1104
1105
1106 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1107 val64 |=
1108 vBIT(config->tx_cfg[i].fifo_len - 1, ((i * 32) + 19),
1109 13) | vBIT(config->tx_cfg[i].fifo_priority,
1110 ((i * 32) + 5), 3);
1111
1112 if (i == (config->tx_fifo_num - 1)) {
1113 if (i % 2 == 0)
1114 i++;
1115 }
1116
1117 switch (i) {
1118 case 1:
1119 writeq(val64, &bar0->tx_fifo_partition_0);
1120 val64 = 0;
1121 break;
1122 case 3:
1123 writeq(val64, &bar0->tx_fifo_partition_1);
1124 val64 = 0;
1125 break;
1126 case 5:
1127 writeq(val64, &bar0->tx_fifo_partition_2);
1128 val64 = 0;
1129 break;
1130 case 7:
1131 writeq(val64, &bar0->tx_fifo_partition_3);
1132 break;
1133 }
1134 }
1135
5e25b9dd
K		 1136 /*
1137 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1138 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1139 */
541ae68f 1140 if ((nic->device_type == XFRAME_I_DEVICE) &&
44c10138 1141 (nic->pdev->revision < 4))
5e25b9dd
K		 1142 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1143
1da177e4
LT		 1144 val64 = readq(&bar0->tx_fifo_partition_0);
1145 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1146 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1147
20346722
K		 1148 /*
1149 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1150 * integrity checking.
1151 */
1152 val64 = readq(&bar0->tx_pa_cfg);
1153 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1154 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1155 writeq(val64, &bar0->tx_pa_cfg);
1156
1157 /* Rx DMA intialization. */
1158 val64 = 0;
1159 for (i = 0; i < config->rx_ring_num; i++) {
1160 val64 |=
1161 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1162 3);
1163 }
1164 writeq(val64, &bar0->rx_queue_priority);
1165
20346722
K		 1166 /*
1167 * Allocating equal share of memory to all the
1da177e4
LT		 1168 * configured Rings.
1169 */
1170 val64 = 0;
541ae68f
K		 1171 if (nic->device_type & XFRAME_II_DEVICE)
1172 mem_size = 32;
1173 else
1174 mem_size = 64;
1175
1da177e4
LT		 1176 for (i = 0; i < config->rx_ring_num; i++) {
1177 switch (i) {
1178 case 0:
20346722
K		 1179 mem_share = (mem_size / config->rx_ring_num +
1180 mem_size % config->rx_ring_num);
1da177e4
LT		 1181 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1182 continue;
1183 case 1:
20346722 1184 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1185 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1186 continue;
1187 case 2:
20346722 1188 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1189 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1190 continue;
1191 case 3:
20346722 1192 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1193 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1194 continue;
1195 case 4:
20346722 1196 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1197 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1198 continue;
1199 case 5:
20346722 1200 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1201 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1202 continue;
1203 case 6:
20346722 1204 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1205 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1206 continue;
1207 case 7:
20346722 1208 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1209 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1210 continue;
1211 }
1212 }
1213 writeq(val64, &bar0->rx_queue_cfg);
1214
20346722 1215 /*
5e25b9dd
K		 1216 * Filling Tx round robin registers
1217 * as per the number of FIFOs
1da177e4 1218 */
5e25b9dd
K		 1219 switch (config->tx_fifo_num) {
1220 case 1:
1221 val64 = 0x0000000000000000ULL;
1222 writeq(val64, &bar0->tx_w_round_robin_0);
1223 writeq(val64, &bar0->tx_w_round_robin_1);
1224 writeq(val64, &bar0->tx_w_round_robin_2);
1225 writeq(val64, &bar0->tx_w_round_robin_3);
1226 writeq(val64, &bar0->tx_w_round_robin_4);
1227 break;
1228 case 2:
1229 val64 = 0x0000010000010000ULL;
1230 writeq(val64, &bar0->tx_w_round_robin_0);
1231 val64 = 0x0100000100000100ULL;
1232 writeq(val64, &bar0->tx_w_round_robin_1);
1233 val64 = 0x0001000001000001ULL;
1234 writeq(val64, &bar0->tx_w_round_robin_2);
1235 val64 = 0x0000010000010000ULL;
1236 writeq(val64, &bar0->tx_w_round_robin_3);
1237 val64 = 0x0100000000000000ULL;
1238 writeq(val64, &bar0->tx_w_round_robin_4);
1239 break;
1240 case 3:
1241 val64 = 0x0001000102000001ULL;
1242 writeq(val64, &bar0->tx_w_round_robin_0);
1243 val64 = 0x0001020000010001ULL;
1244 writeq(val64, &bar0->tx_w_round_robin_1);
1245 val64 = 0x0200000100010200ULL;
1246 writeq(val64, &bar0->tx_w_round_robin_2);
1247 val64 = 0x0001000102000001ULL;
1248 writeq(val64, &bar0->tx_w_round_robin_3);
1249 val64 = 0x0001020000000000ULL;
1250 writeq(val64, &bar0->tx_w_round_robin_4);
1251 break;
1252 case 4:
1253 val64 = 0x0001020300010200ULL;
1254 writeq(val64, &bar0->tx_w_round_robin_0);
1255 val64 = 0x0100000102030001ULL;
1256 writeq(val64, &bar0->tx_w_round_robin_1);
1257 val64 = 0x0200010000010203ULL;
1258 writeq(val64, &bar0->tx_w_round_robin_2);
1259 val64 = 0x0001020001000001ULL;
1260 writeq(val64, &bar0->tx_w_round_robin_3);
1261 val64 = 0x0203000100000000ULL;
1262 writeq(val64, &bar0->tx_w_round_robin_4);
1263 break;
1264 case 5:
1265 val64 = 0x0001000203000102ULL;
1266 writeq(val64, &bar0->tx_w_round_robin_0);
1267 val64 = 0x0001020001030004ULL;
1268 writeq(val64, &bar0->tx_w_round_robin_1);
1269 val64 = 0x0001000203000102ULL;
1270 writeq(val64, &bar0->tx_w_round_robin_2);
1271 val64 = 0x0001020001030004ULL;
1272 writeq(val64, &bar0->tx_w_round_robin_3);
1273 val64 = 0x0001000000000000ULL;
1274 writeq(val64, &bar0->tx_w_round_robin_4);
1275 break;
1276 case 6:
1277 val64 = 0x0001020304000102ULL;
1278 writeq(val64, &bar0->tx_w_round_robin_0);
1279 val64 = 0x0304050001020001ULL;
1280 writeq(val64, &bar0->tx_w_round_robin_1);
1281 val64 = 0x0203000100000102ULL;
1282 writeq(val64, &bar0->tx_w_round_robin_2);
1283 val64 = 0x0304000102030405ULL;
1284 writeq(val64, &bar0->tx_w_round_robin_3);
1285 val64 = 0x0001000200000000ULL;
1286 writeq(val64, &bar0->tx_w_round_robin_4);
1287 break;
1288 case 7:
1289 val64 = 0x0001020001020300ULL;
1290 writeq(val64, &bar0->tx_w_round_robin_0);
1291 val64 = 0x0102030400010203ULL;
1292 writeq(val64, &bar0->tx_w_round_robin_1);
1293 val64 = 0x0405060001020001ULL;
1294 writeq(val64, &bar0->tx_w_round_robin_2);
1295 val64 = 0x0304050000010200ULL;
1296 writeq(val64, &bar0->tx_w_round_robin_3);
1297 val64 = 0x0102030000000000ULL;
1298 writeq(val64, &bar0->tx_w_round_robin_4);
1299 break;
1300 case 8:
1301 val64 = 0x0001020300040105ULL;
1302 writeq(val64, &bar0->tx_w_round_robin_0);
1303 val64 = 0x0200030106000204ULL;
1304 writeq(val64, &bar0->tx_w_round_robin_1);
1305 val64 = 0x0103000502010007ULL;
1306 writeq(val64, &bar0->tx_w_round_robin_2);
1307 val64 = 0x0304010002060500ULL;
1308 writeq(val64, &bar0->tx_w_round_robin_3);
1309 val64 = 0x0103020400000000ULL;
1310 writeq(val64, &bar0->tx_w_round_robin_4);
1311 break;
1312 }
1313
b41477f3 1314 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1315 val64 = readq(&bar0->tx_fifo_partition_0);
1316 val64 |= (TX_FIFO_PARTITION_EN);
1317 writeq(val64, &bar0->tx_fifo_partition_0);
1318
5e25b9dd
K		 1319 /* Filling the Rx round robin registers as per the
1320 * number of Rings and steering based on QoS.
1321 */
1322 switch (config->rx_ring_num) {
1323 case 1:
1324 val64 = 0x8080808080808080ULL;
1325 writeq(val64, &bar0->rts_qos_steering);
1326 break;
1327 case 2:
1328 val64 = 0x0000010000010000ULL;
1329 writeq(val64, &bar0->rx_w_round_robin_0);
1330 val64 = 0x0100000100000100ULL;
1331 writeq(val64, &bar0->rx_w_round_robin_1);
1332 val64 = 0x0001000001000001ULL;
1333 writeq(val64, &bar0->rx_w_round_robin_2);
1334 val64 = 0x0000010000010000ULL;
1335 writeq(val64, &bar0->rx_w_round_robin_3);
1336 val64 = 0x0100000000000000ULL;
1337 writeq(val64, &bar0->rx_w_round_robin_4);
1338
1339 val64 = 0x8080808040404040ULL;
1340 writeq(val64, &bar0->rts_qos_steering);
1341 break;
1342 case 3:
1343 val64 = 0x0001000102000001ULL;
1344 writeq(val64, &bar0->rx_w_round_robin_0);
1345 val64 = 0x0001020000010001ULL;
1346 writeq(val64, &bar0->rx_w_round_robin_1);
1347 val64 = 0x0200000100010200ULL;
1348 writeq(val64, &bar0->rx_w_round_robin_2);
1349 val64 = 0x0001000102000001ULL;
1350 writeq(val64, &bar0->rx_w_round_robin_3);
1351 val64 = 0x0001020000000000ULL;
1352 writeq(val64, &bar0->rx_w_round_robin_4);
1353
1354 val64 = 0x8080804040402020ULL;
1355 writeq(val64, &bar0->rts_qos_steering);
1356 break;
1357 case 4:
1358 val64 = 0x0001020300010200ULL;
1359 writeq(val64, &bar0->rx_w_round_robin_0);
1360 val64 = 0x0100000102030001ULL;
1361 writeq(val64, &bar0->rx_w_round_robin_1);
1362 val64 = 0x0200010000010203ULL;
1363 writeq(val64, &bar0->rx_w_round_robin_2);
6aa20a22 1364 val64 = 0x0001020001000001ULL;
5e25b9dd
K		 1365 writeq(val64, &bar0->rx_w_round_robin_3);
1366 val64 = 0x0203000100000000ULL;
1367 writeq(val64, &bar0->rx_w_round_robin_4);
1368
1369 val64 = 0x8080404020201010ULL;
1370 writeq(val64, &bar0->rts_qos_steering);
1371 break;
1372 case 5:
1373 val64 = 0x0001000203000102ULL;
1374 writeq(val64, &bar0->rx_w_round_robin_0);
1375 val64 = 0x0001020001030004ULL;
1376 writeq(val64, &bar0->rx_w_round_robin_1);
1377 val64 = 0x0001000203000102ULL;
1378 writeq(val64, &bar0->rx_w_round_robin_2);
1379 val64 = 0x0001020001030004ULL;
1380 writeq(val64, &bar0->rx_w_round_robin_3);
1381 val64 = 0x0001000000000000ULL;
1382 writeq(val64, &bar0->rx_w_round_robin_4);
1383
1384 val64 = 0x8080404020201008ULL;
1385 writeq(val64, &bar0->rts_qos_steering);
1386 break;
1387 case 6:
1388 val64 = 0x0001020304000102ULL;
1389 writeq(val64, &bar0->rx_w_round_robin_0);
1390 val64 = 0x0304050001020001ULL;
1391 writeq(val64, &bar0->rx_w_round_robin_1);
1392 val64 = 0x0203000100000102ULL;
1393 writeq(val64, &bar0->rx_w_round_robin_2);
1394 val64 = 0x0304000102030405ULL;
1395 writeq(val64, &bar0->rx_w_round_robin_3);
1396 val64 = 0x0001000200000000ULL;
1397 writeq(val64, &bar0->rx_w_round_robin_4);
1398
1399 val64 = 0x8080404020100804ULL;
1400 writeq(val64, &bar0->rts_qos_steering);
1401 break;
1402 case 7:
1403 val64 = 0x0001020001020300ULL;
1404 writeq(val64, &bar0->rx_w_round_robin_0);
1405 val64 = 0x0102030400010203ULL;
1406 writeq(val64, &bar0->rx_w_round_robin_1);
1407 val64 = 0x0405060001020001ULL;
1408 writeq(val64, &bar0->rx_w_round_robin_2);
1409 val64 = 0x0304050000010200ULL;
1410 writeq(val64, &bar0->rx_w_round_robin_3);
1411 val64 = 0x0102030000000000ULL;
1412 writeq(val64, &bar0->rx_w_round_robin_4);
1413
1414 val64 = 0x8080402010080402ULL;
1415 writeq(val64, &bar0->rts_qos_steering);
1416 break;
1417 case 8:
1418 val64 = 0x0001020300040105ULL;
1419 writeq(val64, &bar0->rx_w_round_robin_0);
1420 val64 = 0x0200030106000204ULL;
1421 writeq(val64, &bar0->rx_w_round_robin_1);
1422 val64 = 0x0103000502010007ULL;
1423 writeq(val64, &bar0->rx_w_round_robin_2);
1424 val64 = 0x0304010002060500ULL;
1425 writeq(val64, &bar0->rx_w_round_robin_3);
1426 val64 = 0x0103020400000000ULL;
1427 writeq(val64, &bar0->rx_w_round_robin_4);
1428
1429 val64 = 0x8040201008040201ULL;
1430 writeq(val64, &bar0->rts_qos_steering);
1431 break;
1432 }
1da177e4
LT		 1433
1434 /* UDP Fix */
1435 val64 = 0;
20346722 1436 for (i = 0; i < 8; i++)
1da177e4
LT		 1437 writeq(val64, &bar0->rts_frm_len_n[i]);
1438
5e25b9dd
K		 1439 /* Set the default rts frame length for the rings configured */
1440 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1441 for (i = 0 ; i < config->rx_ring_num ; i++)
1442 writeq(val64, &bar0->rts_frm_len_n[i]);
1443
1444 /* Set the frame length for the configured rings
1445 * desired by the user
1446 */
1447 for (i = 0; i < config->rx_ring_num; i++) {
1448 /* If rts_frm_len[i] == 0 then it is assumed that user not
1449 * specified frame length steering.
1450 * If the user provides the frame length then program
1451 * the rts_frm_len register for those values or else
1452 * leave it as it is.
1453 */
1454 if (rts_frm_len[i] != 0) {
1455 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1456 &bar0->rts_frm_len_n[i]);
1457 }
1458 }
926930b2 1459
9fc93a41
SS		 1460 /* Disable differentiated services steering logic */
1461 for (i = 0; i < 64; i++) {
1462 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1463 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1464 dev->name);
1465 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
1466 return FAILURE;
1467 }
1468 }
1469
20346722 1470 /* Program statistics memory */
1da177e4 1471 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1472
541ae68f
K		 1473 if (nic->device_type == XFRAME_II_DEVICE) {
1474 val64 = STAT_BC(0x320);
1475 writeq(val64, &bar0->stat_byte_cnt);
1476 }
1477
20346722 1478 /*
1da177e4
LT		 1479 * Initializing the sampling rate for the device to calculate the
1480 * bandwidth utilization.
1481 */
1482 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1483 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1484 writeq(val64, &bar0->mac_link_util);
1485
1486
20346722
K		 1487 /*
1488 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1489 * Scheme.
1490 */
20346722
K		 1491 /*
1492 * TTI Initialization. Default Tx timer gets us about
1da177e4
LT		 1493 * 250 interrupts per sec. Continuous interrupts are enabled
1494 * by default.
1495 */
541ae68f
K		 1496 if (nic->device_type == XFRAME_II_DEVICE) {
1497 int count = (nic->config.bus_speed * 125)/2;
1498 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1499 } else {
1500
1501 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1502 }
1503 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1da177e4 1504 TTI_DATA1_MEM_TX_URNG_B(0x10) |
5e25b9dd 1505 TTI_DATA1_MEM_TX_URNG_C(0x30) | TTI_DATA1_MEM_TX_TIMER_AC_EN;
541ae68f
K		 1506 if (use_continuous_tx_intrs)
1507 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1da177e4
LT		 1508 writeq(val64, &bar0->tti_data1_mem);
1509
1510 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1511 TTI_DATA2_MEM_TX_UFC_B(0x20) |
19a60522 1512 TTI_DATA2_MEM_TX_UFC_C(0x40) | TTI_DATA2_MEM_TX_UFC_D(0x80);
1da177e4
LT		 1513 writeq(val64, &bar0->tti_data2_mem);
1514
1515 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1516 writeq(val64, &bar0->tti_command_mem);
1517
20346722 1518 /*
1da177e4
LT		 1519 * Once the operation completes, the Strobe bit of the command
1520 * register will be reset. We poll for this particular condition
1521 * We wait for a maximum of 500ms for the operation to complete,
1522 * if it's not complete by then we return error.
1523 */
1524 time = 0;
1525 while (TRUE) {
1526 val64 = readq(&bar0->tti_command_mem);
1527 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1528 break;
1529 }
1530 if (time > 10) {
1531 DBG_PRINT(ERR_DBG, "%s: TTI init Failed\n",
1532 dev->name);
1533 return -1;
1534 }
1535 msleep(50);
1536 time++;
1537 }
1538
b6e3f982
K		 1539 if (nic->config.bimodal) {
1540 int k = 0;
1541 for (k = 0; k < config->rx_ring_num; k++) {
1542 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD;
1543 val64 |= TTI_CMD_MEM_OFFSET(0x38+k);
1544 writeq(val64, &bar0->tti_command_mem);
541ae68f 1545
541ae68f 1546 /*
b6e3f982
K		 1547 * Once the operation completes, the Strobe bit of the command
1548 * register will be reset. We poll for this particular condition
1549 * We wait for a maximum of 500ms for the operation to complete,
1550 * if it's not complete by then we return error.
1551 */
1552 time = 0;
1553 while (TRUE) {
1554 val64 = readq(&bar0->tti_command_mem);
1555 if (!(val64 & TTI_CMD_MEM_STROBE_NEW_CMD)) {
1556 break;
1557 }
1558 if (time > 10) {
1559 DBG_PRINT(ERR_DBG,
1560 "%s: TTI init Failed\n",
1561 dev->name);
1562 return -1;
1563 }
1564 time++;
1565 msleep(50);
1566 }
1567 }
541ae68f 1568 } else {
1da177e4 1569
b6e3f982
K		 1570 /* RTI Initialization */
1571 if (nic->device_type == XFRAME_II_DEVICE) {
1572 /*
1573 * Programmed to generate Apprx 500 Intrs per
1574 * second
1575 */
1576 int count = (nic->config.bus_speed * 125)/4;
1577 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1578 } else {
1579 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1580 }
1581 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1582 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1583 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1da177e4 1584
b6e3f982 1585 writeq(val64, &bar0->rti_data1_mem);
1da177e4 1586
b6e3f982 1587 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
cc6e7c44
RA		 1588 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1589 if (nic->intr_type == MSI_X)
1590 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1591 RTI_DATA2_MEM_RX_UFC_D(0x40));
1592 else
1593 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1594 RTI_DATA2_MEM_RX_UFC_D(0x80));
b6e3f982 1595 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1596
b6e3f982
K		 1597 for (i = 0; i < config->rx_ring_num; i++) {
1598 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1599 | RTI_CMD_MEM_OFFSET(i);
1600 writeq(val64, &bar0->rti_command_mem);
1601
1602 /*
1603 * Once the operation completes, the Strobe bit of the
1604 * command register will be reset. We poll for this
1605 * particular condition. We wait for a maximum of 500ms
1606 * for the operation to complete, if it's not complete
1607 * by then we return error.
1608 */
1609 time = 0;
1610 while (TRUE) {
1611 val64 = readq(&bar0->rti_command_mem);
1612 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD)) {
1613 break;
1614 }
1615 if (time > 10) {
1616 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1617 dev->name);
1618 return -1;
1619 }
1620 time++;
1621 msleep(50);
1622 }
1da177e4 1623 }
1da177e4
LT		 1624 }
1625
20346722
K		 1626 /*
1627 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1628 * the 8 Queues on Rx side.
1629 */
1630 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1631 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1632
1633 /* Disable RMAC PAD STRIPPING */
509a2671 1634 add = &bar0->mac_cfg;
1da177e4
LT		 1635 val64 = readq(&bar0->mac_cfg);
1636 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1637 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1638 writel((u32) (val64), add);
1639 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1640 writel((u32) (val64 >> 32), (add + 4));
1641 val64 = readq(&bar0->mac_cfg);
1642
7d3d0439
RA		 1643 /* Enable FCS stripping by adapter */
1644 add = &bar0->mac_cfg;
1645 val64 = readq(&bar0->mac_cfg);
1646 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1647 if (nic->device_type == XFRAME_II_DEVICE)
1648 writeq(val64, &bar0->mac_cfg);
1649 else {
1650 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1651 writel((u32) (val64), add);
1652 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1653 writel((u32) (val64 >> 32), (add + 4));
1654 }
1655
20346722
K		 1656 /*
1657 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1658 * generated by xena.
1659 */
1660 val64 = readq(&bar0->rmac_pause_cfg);
1661 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1662 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1663 writeq(val64, &bar0->rmac_pause_cfg);
1664
20346722 1665 /*
1da177e4
LT		 1666 * Set the Threshold Limit for Generating the pause frame
1667 * If the amount of data in any Queue exceeds ratio of
1668 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1669 * pause frame is generated
1670 */
1671 val64 = 0;
1672 for (i = 0; i < 4; i++) {
1673 val64 |=
1674 (((u64) 0xFF00 | nic->mac_control.
1675 mc_pause_threshold_q0q3)
1676 << (i * 2 * 8));
1677 }
1678 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1679
1680 val64 = 0;
1681 for (i = 0; i < 4; i++) {
1682 val64 |=
1683 (((u64) 0xFF00 | nic->mac_control.
1684 mc_pause_threshold_q4q7)
1685 << (i * 2 * 8));
1686 }
1687 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1688
20346722
K		 1689 /*
1690 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1691 * exceeded the limit pointed by shared_splits
1692 */
1693 val64 = readq(&bar0->pic_control);
1694 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1695 writeq(val64, &bar0->pic_control);
1696
863c11a9
AR		 1697 if (nic->config.bus_speed == 266) {
1698 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1699 writeq(0x0, &bar0->read_retry_delay);
1700 writeq(0x0, &bar0->write_retry_delay);
1701 }
1702
541ae68f
K		 1703 /*
1704 * Programming the Herc to split every write transaction
1705 * that does not start on an ADB to reduce disconnects.
1706 */
1707 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1708 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1709 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1710 writeq(val64, &bar0->misc_control);
1711 val64 = readq(&bar0->pic_control2);
1712 val64 &= ~(BIT(13)|BIT(14)|BIT(15));
1713 writeq(val64, &bar0->pic_control2);
541ae68f 1714 }
c92ca04b
AR		 1715 if (strstr(nic->product_name, "CX4")) {
1716 val64 = TMAC_AVG_IPG(0x17);
1717 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1718 }
1719
1da177e4
LT		 1720 return SUCCESS;
1721}
a371a07d
K		 1722#define LINK_UP_DOWN_INTERRUPT 1
1723#define MAC_RMAC_ERR_TIMER 2
1724
1ee6dd77 1725static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1726{
cc6e7c44
RA		 1727 if (nic->intr_type != INTA)
1728 return MAC_RMAC_ERR_TIMER;
a371a07d
K		 1729 if (nic->device_type == XFRAME_II_DEVICE)
1730 return LINK_UP_DOWN_INTERRUPT;
1731 else
1732 return MAC_RMAC_ERR_TIMER;
1733}
1da177e4 1734
20346722
K		 1735/**
1736 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 1737 * @nic: device private variable,
1738 * @mask: A mask indicating which Intr block must be modified and,
1739 * @flag: A flag indicating whether to enable or disable the Intrs.
1740 * Description: This function will either disable or enable the interrupts
20346722
K		 1741 * depending on the flag argument. The mask argument can be used to
1742 * enable/disable any Intr block.
1da177e4
LT		 1743 * Return Value: NONE.
1744 */
1745
1746static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1747{
1ee6dd77 1748 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1749 register u64 val64 = 0, temp64 = 0;
1750
1751 /* Top level interrupt classification */
1752 /* PIC Interrupts */
1753 if ((mask & (TX_PIC_INTR | RX_PIC_INTR))) {
1754 /* Enable PIC Intrs in the general intr mask register */
a113ae06 1755 val64 = TXPIC_INT_M;
1da177e4
LT		 1756 if (flag == ENABLE_INTRS) {
1757 temp64 = readq(&bar0->general_int_mask);
1758 temp64 &= ~((u64) val64);
1759 writeq(temp64, &bar0->general_int_mask);
20346722 1760 /*
a371a07d 1761 * If Hercules adapter enable GPIO otherwise
b41477f3 1762 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 1763 * interrupts for now.
1764 * TODO
1da177e4 1765 */
a371a07d
K		 1766 if (s2io_link_fault_indication(nic) ==
1767 LINK_UP_DOWN_INTERRUPT ) {
1768 temp64 = readq(&bar0->pic_int_mask);
1769 temp64 &= ~((u64) PIC_INT_GPIO);
1770 writeq(temp64, &bar0->pic_int_mask);
1771 temp64 = readq(&bar0->gpio_int_mask);
1772 temp64 &= ~((u64) GPIO_INT_MASK_LINK_UP);
1773 writeq(temp64, &bar0->gpio_int_mask);
1774 } else {
1775 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1776 }
20346722 1777 /*
1da177e4
LT		 1778 * No MSI Support is available presently, so TTI and
1779 * RTI interrupts are also disabled.
1780 */
1781 } else if (flag == DISABLE_INTRS) {
20346722
K		 1782 /*
1783 * Disable PIC Intrs in the general
1784 * intr mask register
1da177e4
LT		 1785 */
1786 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1787 temp64 = readq(&bar0->general_int_mask);
1788 val64 |= temp64;
1789 writeq(val64, &bar0->general_int_mask);
1790 }
1791 }
1792
1da177e4
LT		 1793 /* MAC Interrupts */
1794 /* Enabling/Disabling MAC interrupts */
1795 if (mask & (TX_MAC_INTR | RX_MAC_INTR)) {
1796 val64 = TXMAC_INT_M | RXMAC_INT_M;
1797 if (flag == ENABLE_INTRS) {
1798 temp64 = readq(&bar0->general_int_mask);
1799 temp64 &= ~((u64) val64);
1800 writeq(temp64, &bar0->general_int_mask);
20346722
K		 1801 /*
1802 * All MAC block error interrupts are disabled for now
1da177e4
LT		 1803 * TODO
1804 */
1da177e4 1805 } else if (flag == DISABLE_INTRS) {
20346722
K		 1806 /*
1807 * Disable MAC Intrs in the general intr mask register
1da177e4
LT		 1808 */
1809 writeq(DISABLE_ALL_INTRS, &bar0->mac_int_mask);
1810 writeq(DISABLE_ALL_INTRS,
1811 &bar0->mac_rmac_err_mask);
1812
1813 temp64 = readq(&bar0->general_int_mask);
1814 val64 |= temp64;
1815 writeq(val64, &bar0->general_int_mask);
1816 }
1817 }
1818
1da177e4
LT		 1819 /* Tx traffic interrupts */
1820 if (mask & TX_TRAFFIC_INTR) {
1821 val64 = TXTRAFFIC_INT_M;
1822 if (flag == ENABLE_INTRS) {
1823 temp64 = readq(&bar0->general_int_mask);
1824 temp64 &= ~((u64) val64);
1825 writeq(temp64, &bar0->general_int_mask);
20346722 1826 /*
1da177e4 1827 * Enable all the Tx side interrupts
20346722 1828 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 1829 */
1830 writeq(0x0, &bar0->tx_traffic_mask);
1831 } else if (flag == DISABLE_INTRS) {
20346722
K		 1832 /*
1833 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 1834 * register.
1835 */
1836 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1837 temp64 = readq(&bar0->general_int_mask);
1838 val64 |= temp64;
1839 writeq(val64, &bar0->general_int_mask);
1840 }
1841 }
1842
1843 /* Rx traffic interrupts */
1844 if (mask & RX_TRAFFIC_INTR) {
1845 val64 = RXTRAFFIC_INT_M;
1846 if (flag == ENABLE_INTRS) {
1847 temp64 = readq(&bar0->general_int_mask);
1848 temp64 &= ~((u64) val64);
1849 writeq(temp64, &bar0->general_int_mask);
1850 /* writing 0 Enables all 8 RX interrupt levels */
1851 writeq(0x0, &bar0->rx_traffic_mask);
1852 } else if (flag == DISABLE_INTRS) {
20346722
K		 1853 /*
1854 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 1855 * register.
1856 */
1857 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1858 temp64 = readq(&bar0->general_int_mask);
1859 val64 |= temp64;
1860 writeq(val64, &bar0->general_int_mask);
1861 }
1862 }
1863}
1864
19a60522
SS		 1865/**
1866 * verify_pcc_quiescent- Checks for PCC quiescent state
1867 * Return: 1 If PCC is quiescence
1868 * 0 If PCC is not quiescence
1869 */
1ee6dd77 1870static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 1871{
19a60522 1872 int ret = 0, herc;
1ee6dd77 1873 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 1874 u64 val64 = readq(&bar0->adapter_status);
1875
1876 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722
K		 1877
1878 if (flag == FALSE) {
44c10138 1879 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 1880 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 1881 ret = 1;
19a60522
SS		 1882 } else {
1883 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 1884 ret = 1;
20346722
K		 1885 }
1886 } else {
44c10138 1887 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 1888 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 1889 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 1890 ret = 1;
5e25b9dd
K		 1891 } else {
1892 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 1893 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 1894 ret = 1;
20346722
K		 1895 }
1896 }
1897
1898 return ret;
1899}
1900/**
1901 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 1902 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 1903 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 1904 * differs and the calling function passes the input argument flag to
1905 * indicate this.
20346722 1906 * Return: 1 If xena is quiescence
1da177e4
LT		 1907 * 0 If Xena is not quiescence
1908 */
1909
1ee6dd77 1910static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 1911{
19a60522 1912 int mode;
1ee6dd77 1913 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 1914 u64 val64 = readq(&bar0->adapter_status);
1915 mode = s2io_verify_pci_mode(sp);
1da177e4 1916
19a60522
SS		 1917 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
1918 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
1919 return 0;
1920 }
1921 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
1922 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
1923 return 0;
1924 }
1925 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
1926 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
1927 return 0;
1928 }
1929 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
1930 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
1931 return 0;
1932 }
1933 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
1934 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
1935 return 0;
1936 }
1937 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
1938 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
1939 return 0;
1940 }
1941 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
1942 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
1943 return 0;
1944 }
1945 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
1946 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
1947 return 0;
1da177e4
LT		 1948 }
1949
19a60522
SS		 1950 /*
1951 * In PCI 33 mode, the P_PLL is not used, and therefore,
1952 * the the P_PLL_LOCK bit in the adapter_status register will
1953 * not be asserted.
1954 */
1955 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
1956 sp->device_type == XFRAME_II_DEVICE && mode !=
1957 PCI_MODE_PCI_33) {
1958 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
1959 return 0;
1960 }
1961 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
1962 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
1963 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
1964 return 0;
1965 }
1966 return 1;
1da177e4
LT		 1967}
1968
1969/**
1970 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
1971 * @sp: Pointer to device specifc structure
20346722 1972 * Description :
1da177e4
LT		 1973 * New procedure to clear mac address reading problems on Alpha platforms
1974 *
1975 */
1976
1ee6dd77 1977static void fix_mac_address(struct s2io_nic * sp)
1da177e4 1978{
1ee6dd77 1979 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 1980 u64 val64;
1981 int i = 0;
1982
1983 while (fix_mac[i] != END_SIGN) {
1984 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 1985 udelay(10);
1da177e4
LT		 1986 val64 = readq(&bar0->gpio_control);
1987 }
1988}
1989
1990/**
20346722 1991 * start_nic - Turns the device on
1da177e4 1992 * @nic : device private variable.
20346722
K		 1993 * Description:
1994 * This function actually turns the device on. Before this function is
1995 * called,all Registers are configured from their reset states
1996 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 1997 * calling this function, the device interrupts are cleared and the NIC is
1998 * literally switched on by writing into the adapter control register.
20346722 1999 * Return Value:
1da177e4
LT		 2000 * SUCCESS on success and -1 on failure.
2001 */
2002
2003static int start_nic(struct s2io_nic *nic)
2004{
1ee6dd77 2005 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2006 struct net_device *dev = nic->dev;
2007 register u64 val64 = 0;
20346722 2008 u16 subid, i;
1ee6dd77 2009 struct mac_info *mac_control;
1da177e4
LT		 2010 struct config_param *config;
2011
2012 mac_control = &nic->mac_control;
2013 config = &nic->config;
2014
2015 /* PRC Initialization and configuration */
2016 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2017 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 2018 &bar0->prc_rxd0_n[i]);
2019
2020 val64 = readq(&bar0->prc_ctrl_n[i]);
b6e3f982
K		 2021 if (nic->config.bimodal)
2022 val64 |= PRC_CTRL_BIMODAL_INTERRUPT;
da6971d8
AR		 2023 if (nic->rxd_mode == RXD_MODE_1)
2024 val64 |= PRC_CTRL_RC_ENABLED;
2025 else
2026 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2027 if (nic->device_type == XFRAME_II_DEVICE)
2028 val64 |= PRC_CTRL_GROUP_READS;
2029 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2030 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2031 writeq(val64, &bar0->prc_ctrl_n[i]);
2032 }
2033
da6971d8
AR		 2034 if (nic->rxd_mode == RXD_MODE_3B) {
2035 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2036 val64 = readq(&bar0->rx_pa_cfg);
2037 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2038 writeq(val64, &bar0->rx_pa_cfg);
2039 }
1da177e4 2040
926930b2
SS		 2041 if (vlan_tag_strip == 0) {
2042 val64 = readq(&bar0->rx_pa_cfg);
2043 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2044 writeq(val64, &bar0->rx_pa_cfg);
2045 vlan_strip_flag = 0;
2046 }
2047
20346722 2048 /*
1da177e4
LT		 2049 * Enabling MC-RLDRAM. After enabling the device, we timeout
2050 * for around 100ms, which is approximately the time required
2051 * for the device to be ready for operation.
2052 */
2053 val64 = readq(&bar0->mc_rldram_mrs);
2054 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2055 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2056 val64 = readq(&bar0->mc_rldram_mrs);
2057
20346722 2058 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2059
2060 /* Enabling ECC Protection. */
2061 val64 = readq(&bar0->adapter_control);
2062 val64 &= ~ADAPTER_ECC_EN;
2063 writeq(val64, &bar0->adapter_control);
2064
20346722
K		 2065 /*
2066 * Clearing any possible Link state change interrupts that
1da177e4
LT		 2067 * could have popped up just before Enabling the card.
2068 */
2069 val64 = readq(&bar0->mac_rmac_err_reg);
2070 if (val64)
2071 writeq(val64, &bar0->mac_rmac_err_reg);
2072
20346722
K		 2073 /*
2074 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2075 * it.
2076 */
2077 val64 = readq(&bar0->adapter_status);
19a60522 2078 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2079 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2080 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2081 (unsigned long long) val64);
2082 return FAILURE;
2083 }
2084
20346722 2085 /*
1da177e4 2086 * With some switches, link might be already up at this point.
20346722
K		 2087 * Because of this weird behavior, when we enable laser,
2088 * we may not get link. We need to handle this. We cannot
2089 * figure out which switch is misbehaving. So we are forced to
2090 * make a global change.
1da177e4
LT		 2091 */
2092
2093 /* Enabling Laser. */
2094 val64 = readq(&bar0->adapter_control);
2095 val64 |= ADAPTER_EOI_TX_ON;
2096 writeq(val64, &bar0->adapter_control);
2097
c92ca04b
AR		 2098 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2099 /*
2100 * Dont see link state interrupts initally on some switches,
2101 * so directly scheduling the link state task here.
2102 */
2103 schedule_work(&nic->set_link_task);
2104 }
1da177e4
LT		 2105 /* SXE-002: Initialize link and activity LED */
2106 subid = nic->pdev->subsystem_device;
541ae68f
K		 2107 if (((subid & 0xFF) >= 0x07) &&
2108 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2109 val64 = readq(&bar0->gpio_control);
2110 val64 |= 0x0000800000000000ULL;
2111 writeq(val64, &bar0->gpio_control);
2112 val64 = 0x0411040400000000ULL;
509a2671 2113 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2114 }
2115
1da177e4
LT		 2116 return SUCCESS;
2117}
fed5eccd
AR		 2118/**
2119 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2120 */
1ee6dd77
RB		 2121static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2122 TxD *txdlp, int get_off)
fed5eccd 2123{
1ee6dd77 2124 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2125 struct sk_buff *skb;
1ee6dd77 2126 struct TxD *txds;
fed5eccd
AR		 2127 u16 j, frg_cnt;
2128
2129 txds = txdlp;
26b7625c 2130 if (txds->Host_Control == (u64)(long)nic->ufo_in_band_v) {
fed5eccd
AR		 2131 pci_unmap_single(nic->pdev, (dma_addr_t)
2132 txds->Buffer_Pointer, sizeof(u64),
2133 PCI_DMA_TODEVICE);
2134 txds++;
2135 }
2136
2137 skb = (struct sk_buff *) ((unsigned long)
2138 txds->Host_Control);
2139 if (!skb) {
1ee6dd77 2140 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2141 return NULL;
2142 }
2143 pci_unmap_single(nic->pdev, (dma_addr_t)
2144 txds->Buffer_Pointer,
2145 skb->len - skb->data_len,
2146 PCI_DMA_TODEVICE);
2147 frg_cnt = skb_shinfo(skb)->nr_frags;
2148 if (frg_cnt) {
2149 txds++;
2150 for (j = 0; j < frg_cnt; j++, txds++) {
2151 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2152 if (!txds->Buffer_Pointer)
2153 break;
6aa20a22 2154 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2155 txds->Buffer_Pointer,
2156 frag->size, PCI_DMA_TODEVICE);
2157 }
2158 }
1ee6dd77 2159 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2160 return(skb);
2161}
1da177e4 2162
20346722
K		 2163/**
2164 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2165 * @nic : device private variable.
20346722 2166 * Description:
1da177e4 2167 * Free all queued Tx buffers.
20346722 2168 * Return Value: void
1da177e4
LT		 2169*/
2170
2171static void free_tx_buffers(struct s2io_nic *nic)
2172{
2173 struct net_device *dev = nic->dev;
2174 struct sk_buff *skb;
1ee6dd77 2175 struct TxD *txdp;
1da177e4 2176 int i, j;
1ee6dd77 2177 struct mac_info *mac_control;
1da177e4 2178 struct config_param *config;
fed5eccd 2179 int cnt = 0;
1da177e4
LT		 2180
2181 mac_control = &nic->mac_control;
2182 config = &nic->config;
2183
2184 for (i = 0; i < config->tx_fifo_num; i++) {
2185 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
491976b2
SH		 2186 txdp = (struct TxD *) \
2187 mac_control->fifos[i].list_info[j].list_virt_addr;
fed5eccd
AR		 2188 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2189 if (skb) {
491976b2
SH		 2190 nic->mac_control.stats_info->sw_stat.mem_freed
2191 += skb->truesize;
fed5eccd
AR		 2192 dev_kfree_skb(skb);
2193 cnt++;
1da177e4 2194 }
1da177e4
LT		 2195 }
2196 DBG_PRINT(INTR_DBG,
2197 "%s:forcibly freeing %d skbs on FIFO%d\n",
2198 dev->name, cnt, i);
20346722
K		 2199 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2200 mac_control->fifos[i].tx_curr_put_info.offset = 0;
1da177e4
LT		 2201 }
2202}
2203
20346722
K		 2204/**
2205 * stop_nic - To stop the nic
1da177e4 2206 * @nic ; device private variable.
20346722
K		 2207 * Description:
2208 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2209 * function does. This function is called to stop the device.
2210 * Return Value:
2211 * void.
2212 */
2213
2214static void stop_nic(struct s2io_nic *nic)
2215{
1ee6dd77 2216 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2217 register u64 val64 = 0;
5d3213cc 2218 u16 interruptible;
1ee6dd77 2219 struct mac_info *mac_control;
1da177e4
LT		 2220 struct config_param *config;
2221
2222 mac_control = &nic->mac_control;
2223 config = &nic->config;
2224
2225 /* Disable all interrupts */
e960fc5c 2226 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
a371a07d
K		 2227 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
2228 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
1da177e4
LT		 2229 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2230
5d3213cc
AR		 2231 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2232 val64 = readq(&bar0->adapter_control);
2233 val64 &= ~(ADAPTER_CNTL_EN);
2234 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2235}
2236
20346722
K		 2237/**
2238 * fill_rx_buffers - Allocates the Rx side skbs
1da177e4 2239 * @nic: device private variable
20346722
K		 2240 * @ring_no: ring number
2241 * Description:
1da177e4
LT		 2242 * The function allocates Rx side skbs and puts the physical
2243 * address of these buffers into the RxD buffer pointers, so that the NIC
2244 * can DMA the received frame into these locations.
2245 * The NIC supports 3 receive modes, viz
2246 * 1. single buffer,
2247 * 2. three buffer and
2248 * 3. Five buffer modes.
20346722
K		 2249 * Each mode defines how many fragments the received frame will be split
2250 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2251 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2252 * is split into 3 fragments. As of now only single buffer mode is
2253 * supported.
2254 * Return Value:
2255 * SUCCESS on success or an appropriate -ve value on failure.
2256 */
2257
ac1f60db 2258static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1da177e4
LT		 2259{
2260 struct net_device *dev = nic->dev;
2261 struct sk_buff *skb;
1ee6dd77 2262 struct RxD_t *rxdp;
1da177e4 2263 int off, off1, size, block_no, block_no1;
1da177e4 2264 u32 alloc_tab = 0;
20346722 2265 u32 alloc_cnt;
1ee6dd77 2266 struct mac_info *mac_control;
1da177e4 2267 struct config_param *config;
20346722 2268 u64 tmp;
1ee6dd77 2269 struct buffAdd *ba;
1da177e4 2270 unsigned long flags;
1ee6dd77 2271 struct RxD_t *first_rxdp = NULL;
363dc367 2272 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
6d517a27
VP		 2273 struct RxD1 *rxdp1;
2274 struct RxD3 *rxdp3;
491abf25 2275 struct swStat *stats = &nic->mac_control.stats_info->sw_stat;
1da177e4
LT		 2276
2277 mac_control = &nic->mac_control;
2278 config = &nic->config;
20346722
K		 2279 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2280 atomic_read(&nic->rx_bufs_left[ring_no]);
1da177e4 2281
5d3213cc 2282 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
863c11a9 2283 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1da177e4 2284 while (alloc_tab < alloc_cnt) {
20346722 2285 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2286 block_index;
20346722 2287 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1da177e4 2288
da6971d8
AR		 2289 rxdp = mac_control->rings[ring_no].
2290 rx_blocks[block_no].rxds[off].virt_addr;
2291
2292 if ((block_no == block_no1) && (off == off1) &&
2293 (rxdp->Host_Control)) {
2294 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2295 dev->name);
1da177e4
LT		 2296 DBG_PRINT(INTR_DBG, " info equated\n");
2297 goto end;
2298 }
da6971d8 2299 if (off && (off == rxd_count[nic->rxd_mode])) {
20346722 2300 mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2301 block_index++;
da6971d8
AR		 2302 if (mac_control->rings[ring_no].rx_curr_put_info.
2303 block_index == mac_control->rings[ring_no].
2304 block_count)
2305 mac_control->rings[ring_no].rx_curr_put_info.
2306 block_index = 0;
2307 block_no = mac_control->rings[ring_no].
2308 rx_curr_put_info.block_index;
2309 if (off == rxd_count[nic->rxd_mode])
2310 off = 0;
20346722 2311 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8
AR		 2312 offset = off;
2313 rxdp = mac_control->rings[ring_no].
2314 rx_blocks[block_no].block_virt_addr;
1da177e4
LT		 2315 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2316 dev->name, rxdp);
2317 }
db874e65
SS		 2318 if(!napi) {
2319 spin_lock_irqsave(&nic->put_lock, flags);
2320 mac_control->rings[ring_no].put_pos =
2321 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2322 spin_unlock_irqrestore(&nic->put_lock, flags);
2323 } else {
2324 mac_control->rings[ring_no].put_pos =
2325 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2326 }
da6971d8 2327 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
6d517a27 2328 ((nic->rxd_mode == RXD_MODE_3B) &&
da6971d8 2329 (rxdp->Control_2 & BIT(0)))) {
20346722 2330 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8 2331 offset = off;
1da177e4
LT		 2332 goto end;
2333 }
da6971d8
AR		 2334 /* calculate size of skb based on ring mode */
2335 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2336 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2337 if (nic->rxd_mode == RXD_MODE_1)
2338 size += NET_IP_ALIGN;
da6971d8 2339 else
6d517a27 2340 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2341
da6971d8
AR		 2342 /* allocate skb */
2343 skb = dev_alloc_skb(size);
2344 if(!skb) {
0c61ed5f
RV		 2345 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2346 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b
K		 2347 if (first_rxdp) {
2348 wmb();
2349 first_rxdp->Control_1 |= RXD_OWN_XENA;
2350 }
c53d4945
SH		 2351 nic->mac_control.stats_info->sw_stat. \
2352 mem_alloc_fail_cnt++;
da6971d8
AR		 2353 return -ENOMEM ;
2354 }
491976b2
SH		 2355 nic->mac_control.stats_info->sw_stat.mem_allocated
2356 += skb->truesize;
da6971d8
AR		 2357 if (nic->rxd_mode == RXD_MODE_1) {
2358 /* 1 buffer mode - normal operation mode */
6d517a27 2359 rxdp1 = (struct RxD1*)rxdp;
1ee6dd77 2360 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2361 skb_reserve(skb, NET_IP_ALIGN);
6d517a27 2362 rxdp1->Buffer0_ptr = pci_map_single
863c11a9
AR		 2363 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2364 PCI_DMA_FROMDEVICE);
491abf25
VP		 2365 if( (rxdp1->Buffer0_ptr == 0) ||
2366 (rxdp1->Buffer0_ptr ==
2367 DMA_ERROR_CODE))
2368 goto pci_map_failed;
2369
491976b2
SH		 2370 rxdp->Control_2 =
2371 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
da6971d8 2372
6d517a27 2373 } else if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8 2374 /*
6d517a27
VP		 2375 * 2 buffer mode -
2376 * 2 buffer mode provides 128
da6971d8 2377 * byte aligned receive buffers.
da6971d8
AR		 2378 */
2379
6d517a27 2380 rxdp3 = (struct RxD3*)rxdp;
491976b2 2381 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2382 Buffer0_ptr = rxdp3->Buffer0_ptr;
2383 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2384 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2385 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2386 rxdp3->Buffer0_ptr = Buffer0_ptr;
2387 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2388
da6971d8
AR		 2389 ba = &mac_control->rings[ring_no].ba[block_no][off];
2390 skb_reserve(skb, BUF0_LEN);
2391 tmp = (u64)(unsigned long) skb->data;
2392 tmp += ALIGN_SIZE;
2393 tmp &= ~ALIGN_SIZE;
2394 skb->data = (void *) (unsigned long)tmp;
27a884dc 2395 skb_reset_tail_pointer(skb);
da6971d8 2396
6d517a27
VP		 2397 if (!(rxdp3->Buffer0_ptr))
2398 rxdp3->Buffer0_ptr =
75c30b13 2399 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
da6971d8 2400 PCI_DMA_FROMDEVICE);
75c30b13
AR		 2401 else
2402 pci_dma_sync_single_for_device(nic->pdev,
6d517a27 2403 (dma_addr_t) rxdp3->Buffer0_ptr,
75c30b13 2404 BUF0_LEN, PCI_DMA_FROMDEVICE);
491abf25
VP		 2405 if( (rxdp3->Buffer0_ptr == 0) ||
2406 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2407 goto pci_map_failed;
2408
da6971d8
AR		 2409 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2410 if (nic->rxd_mode == RXD_MODE_3B) {
2411 /* Two buffer mode */
2412
2413 /*
6aa20a22 2414 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2415 * L4 payload
2416 */
6d517a27 2417 rxdp3->Buffer2_ptr = pci_map_single
da6971d8
AR		 2418 (nic->pdev, skb->data, dev->mtu + 4,
2419 PCI_DMA_FROMDEVICE);
2420
491abf25
VP		 2421 if( (rxdp3->Buffer2_ptr == 0) ||
2422 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2423 goto pci_map_failed;
2424
2425 rxdp3->Buffer1_ptr =
6aa20a22 2426 pci_map_single(nic->pdev,
75c30b13
AR		 2427 ba->ba_1, BUF1_LEN,
2428 PCI_DMA_FROMDEVICE);
491abf25
VP		 2429 if( (rxdp3->Buffer1_ptr == 0) ||
2430 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2431 pci_unmap_single
2432 (nic->pdev,
3e847423 2433 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 2434 dev->mtu + 4,
2435 PCI_DMA_FROMDEVICE);
2436 goto pci_map_failed;
75c30b13 2437 }
da6971d8
AR		 2438 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2439 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2440 (dev->mtu + 4);
da6971d8
AR		 2441 }
2442 rxdp->Control_2 |= BIT(0);
1da177e4 2443 }
1da177e4 2444 rxdp->Host_Control = (unsigned long) (skb);
303bcb4b
K		 2445 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2446 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2447 off++;
da6971d8
AR		 2448 if (off == (rxd_count[nic->rxd_mode] + 1))
2449 off = 0;
20346722 2450 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
20346722 2451
da6971d8 2452 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2453 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2454 if (first_rxdp) {
2455 wmb();
2456 first_rxdp->Control_1 |= RXD_OWN_XENA;
2457 }
2458 first_rxdp = rxdp;
2459 }
1da177e4
LT		 2460 atomic_inc(&nic->rx_bufs_left[ring_no]);
2461 alloc_tab++;
2462 }
2463
2464 end:
303bcb4b
K		 2465 /* Transfer ownership of first descriptor to adapter just before
2466 * exiting. Before that, use memory barrier so that ownership
2467 * and other fields are seen by adapter correctly.
2468 */
2469 if (first_rxdp) {
2470 wmb();
2471 first_rxdp->Control_1 |= RXD_OWN_XENA;
2472 }
2473
1da177e4 2474 return SUCCESS;
491abf25
VP		 2475pci_map_failed:
2476 stats->pci_map_fail_cnt++;
2477 stats->mem_freed += skb->truesize;
2478 dev_kfree_skb_irq(skb);
2479 return -ENOMEM;
1da177e4
LT		 2480}
2481
da6971d8
AR		 2482static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2483{
2484 struct net_device *dev = sp->dev;
2485 int j;
2486 struct sk_buff *skb;
1ee6dd77
RB		 2487 struct RxD_t *rxdp;
2488 struct mac_info *mac_control;
2489 struct buffAdd *ba;
6d517a27
VP		 2490 struct RxD1 *rxdp1;
2491 struct RxD3 *rxdp3;
da6971d8
AR		 2492
2493 mac_control = &sp->mac_control;
2494 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2495 rxdp = mac_control->rings[ring_no].
2496 rx_blocks[blk].rxds[j].virt_addr;
2497 skb = (struct sk_buff *)
2498 ((unsigned long) rxdp->Host_Control);
2499 if (!skb) {
2500 continue;
2501 }
2502 if (sp->rxd_mode == RXD_MODE_1) {
6d517a27 2503 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2504 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2505 rxdp1->Buffer0_ptr,
2506 dev->mtu +
2507 HEADER_ETHERNET_II_802_3_SIZE
2508 + HEADER_802_2_SIZE +
2509 HEADER_SNAP_SIZE,
2510 PCI_DMA_FROMDEVICE);
1ee6dd77 2511 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2512 } else if(sp->rxd_mode == RXD_MODE_3B) {
6d517a27 2513 rxdp3 = (struct RxD3*)rxdp;
da6971d8
AR		 2514 ba = &mac_control->rings[ring_no].
2515 ba[blk][j];
2516 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2517 rxdp3->Buffer0_ptr,
2518 BUF0_LEN,
da6971d8
AR		 2519 PCI_DMA_FROMDEVICE);
2520 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2521 rxdp3->Buffer1_ptr,
2522 BUF1_LEN,
da6971d8
AR		 2523 PCI_DMA_FROMDEVICE);
2524 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2525 rxdp3->Buffer2_ptr,
2526 dev->mtu + 4,
da6971d8 2527 PCI_DMA_FROMDEVICE);
1ee6dd77 2528 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2529 }
491976b2 2530 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8
AR		 2531 dev_kfree_skb(skb);
2532 atomic_dec(&sp->rx_bufs_left[ring_no]);
2533 }
2534}
2535
1da177e4 2536/**
20346722 2537 * free_rx_buffers - Frees all Rx buffers
1da177e4 2538 * @sp: device private variable.
20346722 2539 * Description:
1da177e4
LT		 2540 * This function will free all Rx buffers allocated by host.
2541 * Return Value:
2542 * NONE.
2543 */
2544
2545static void free_rx_buffers(struct s2io_nic *sp)
2546{
2547 struct net_device *dev = sp->dev;
da6971d8 2548 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2549 struct mac_info *mac_control;
1da177e4 2550 struct config_param *config;
1da177e4
LT		 2551
2552 mac_control = &sp->mac_control;
2553 config = &sp->config;
2554
2555 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2556 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2557 free_rxd_blk(sp,i,blk);
1da177e4 2558
20346722
K		 2559 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2560 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2561 mac_control->rings[i].rx_curr_put_info.offset = 0;
2562 mac_control->rings[i].rx_curr_get_info.offset = 0;
1da177e4
LT		 2563 atomic_set(&sp->rx_bufs_left[i], 0);
2564 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2565 dev->name, buf_cnt, i);
2566 }
2567}
2568
2569/**
2570 * s2io_poll - Rx interrupt handler for NAPI support
2571 * @dev : pointer to the device structure.
20346722 2572 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2573 * during one pass through the 'Poll" function.
2574 * Description:
2575 * Comes into picture only if NAPI support has been incorporated. It does
2576 * the same thing that rx_intr_handler does, but not in a interrupt context
2577 * also It will process only a given number of packets.
2578 * Return value:
2579 * 0 on success and 1 if there are No Rx packets to be processed.
2580 */
2581
1da177e4
LT		 2582static int s2io_poll(struct net_device *dev, int *budget)
2583{
1ee6dd77 2584 struct s2io_nic *nic = dev->priv;
20346722 2585 int pkt_cnt = 0, org_pkts_to_process;
1ee6dd77 2586 struct mac_info *mac_control;
1da177e4 2587 struct config_param *config;
1ee6dd77 2588 struct XENA_dev_config __iomem *bar0 = nic->bar0;
20346722 2589 int i;
1da177e4 2590
7ba013ac 2591 atomic_inc(&nic->isr_cnt);
1da177e4
LT		 2592 mac_control = &nic->mac_control;
2593 config = &nic->config;
2594
20346722
K		 2595 nic->pkts_to_process = *budget;
2596 if (nic->pkts_to_process > dev->quota)
2597 nic->pkts_to_process = dev->quota;
2598 org_pkts_to_process = nic->pkts_to_process;
1da177e4 2599
19a60522
SS		 2600 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2601 readl(&bar0->rx_traffic_int);
1da177e4
LT		 2602
2603 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 2604 rx_intr_handler(&mac_control->rings[i]);
2605 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2606 if (!nic->pkts_to_process) {
2607 /* Quota for the current iteration has been met */
2608 goto no_rx;
1da177e4 2609 }
1da177e4
LT		 2610 }
2611 if (!pkt_cnt)
2612 pkt_cnt = 1;
2613
2614 dev->quota -= pkt_cnt;
2615 *budget -= pkt_cnt;
2616 netif_rx_complete(dev);
2617
2618 for (i = 0; i < config->rx_ring_num; i++) {
2619 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2620 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2621 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2622 break;
2623 }
2624 }
2625 /* Re enable the Rx interrupts. */
c92ca04b 2626 writeq(0x0, &bar0->rx_traffic_mask);
19a60522 2627 readl(&bar0->rx_traffic_mask);
7ba013ac 2628 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2629 return 0;
2630
20346722 2631no_rx:
1da177e4
LT		 2632 dev->quota -= pkt_cnt;
2633 *budget -= pkt_cnt;
2634
2635 for (i = 0; i < config->rx_ring_num; i++) {
2636 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2637 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2638 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2639 break;
2640 }
2641 }
7ba013ac 2642 atomic_dec(&nic->isr_cnt);
1da177e4
LT		 2643 return 1;
2644}
20346722 2645
b41477f3 2646#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2647/**
b41477f3 2648 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2649 * @dev : pointer to the device structure.
2650 * Description:
b41477f3
AR		 2651 * This function will be called by upper layer to check for events on the
2652 * interface in situations where interrupts are disabled. It is used for
2653 * specific in-kernel networking tasks, such as remote consoles and kernel
2654 * debugging over the network (example netdump in RedHat).
612eff0e 2655 */
612eff0e
BH		 2656static void s2io_netpoll(struct net_device *dev)
2657{
1ee6dd77
RB		 2658 struct s2io_nic *nic = dev->priv;
2659 struct mac_info *mac_control;
612eff0e 2660 struct config_param *config;
1ee6dd77 2661 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2662 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2663 int i;
2664
d796fdb7
LV		 2665 if (pci_channel_offline(nic->pdev))
2666 return;
2667
612eff0e
BH		 2668 disable_irq(dev->irq);
2669
2670 atomic_inc(&nic->isr_cnt);
2671 mac_control = &nic->mac_control;
2672 config = &nic->config;
2673
612eff0e 2674 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2675 writeq(val64, &bar0->tx_traffic_int);
2676
6aa20a22 2677 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2678 * run out of skbs and will fail and eventually netpoll application such
2679 * as netdump will fail.
2680 */
2681 for (i = 0; i < config->tx_fifo_num; i++)
2682 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2683
b41477f3 2684 /* check for received packet and indicate up to network */
612eff0e
BH		 2685 for (i = 0; i < config->rx_ring_num; i++)
2686 rx_intr_handler(&mac_control->rings[i]);
2687
2688 for (i = 0; i < config->rx_ring_num; i++) {
2689 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2690 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2691 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2692 break;
2693 }
2694 }
2695 atomic_dec(&nic->isr_cnt);
2696 enable_irq(dev->irq);
2697 return;
2698}
2699#endif
2700
20346722 2701/**
1da177e4
LT		 2702 * rx_intr_handler - Rx interrupt handler
2703 * @nic: device private variable.
20346722
K		 2704 * Description:
2705 * If the interrupt is because of a received frame or if the
1da177e4 2706 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2707 * called. It picks out the RxD at which place the last Rx processing had
2708 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2709 * the offset.
2710 * Return Value:
2711 * NONE.
2712 */
1ee6dd77 2713static void rx_intr_handler(struct ring_info *ring_data)
1da177e4 2714{
1ee6dd77 2715 struct s2io_nic *nic = ring_data->nic;
1da177e4 2716 struct net_device *dev = (struct net_device *) nic->dev;
da6971d8 2717 int get_block, put_block, put_offset;
1ee6dd77
RB		 2718 struct rx_curr_get_info get_info, put_info;
2719 struct RxD_t *rxdp;
1da177e4 2720 struct sk_buff *skb;
20346722 2721 int pkt_cnt = 0;
7d3d0439 2722 int i;
6d517a27
VP		 2723 struct RxD1* rxdp1;
2724 struct RxD3* rxdp3;
7d3d0439 2725
7ba013ac
K		 2726 spin_lock(&nic->rx_lock);
2727 if (atomic_read(&nic->card_state) == CARD_DOWN) {
776bd20f 2728 DBG_PRINT(INTR_DBG, "%s: %s going down for reset\n",
7ba013ac
K		 2729 __FUNCTION__, dev->name);
2730 spin_unlock(&nic->rx_lock);
776bd20f 2731 return;
7ba013ac
K		 2732 }
2733
20346722
K		 2734 get_info = ring_data->rx_curr_get_info;
2735 get_block = get_info.block_index;
1ee6dd77 2736 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2737 put_block = put_info.block_index;
da6971d8 2738 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65
SS		 2739 if (!napi) {
2740 spin_lock(&nic->put_lock);
2741 put_offset = ring_data->put_pos;
2742 spin_unlock(&nic->put_lock);
2743 } else
2744 put_offset = ring_data->put_pos;
2745
da6971d8 2746 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2747 /*
2748 * If your are next to put index then it's
2749 * FIFO full condition
2750 */
da6971d8
AR		 2751 if ((get_block == put_block) &&
2752 (get_info.offset + 1) == put_info.offset) {
75c30b13 2753 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
da6971d8
AR		 2754 break;
2755 }
20346722
K		 2756 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2757 if (skb == NULL) {
2758 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2759 dev->name);
2760 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
7ba013ac 2761 spin_unlock(&nic->rx_lock);
20346722 2762 return;
1da177e4 2763 }
da6971d8 2764 if (nic->rxd_mode == RXD_MODE_1) {
6d517a27 2765 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2766 pci_unmap_single(nic->pdev, (dma_addr_t)
6d517a27
VP		 2767 rxdp1->Buffer0_ptr,
2768 dev->mtu +
2769 HEADER_ETHERNET_II_802_3_SIZE +
2770 HEADER_802_2_SIZE +
2771 HEADER_SNAP_SIZE,
2772 PCI_DMA_FROMDEVICE);
da6971d8 2773 } else if (nic->rxd_mode == RXD_MODE_3B) {
6d517a27 2774 rxdp3 = (struct RxD3*)rxdp;
75c30b13 2775 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
6d517a27
VP		 2776 rxdp3->Buffer0_ptr,
2777 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8 2778 pci_unmap_single(nic->pdev, (dma_addr_t)
6d517a27
VP		 2779 rxdp3->Buffer2_ptr,
2780 dev->mtu + 4,
2781 PCI_DMA_FROMDEVICE);
da6971d8 2782 }
863c11a9 2783 prefetch(skb->data);
20346722
K		 2784 rx_osm_handler(ring_data, rxdp);
2785 get_info.offset++;
da6971d8
AR		 2786 ring_data->rx_curr_get_info.offset = get_info.offset;
2787 rxdp = ring_data->rx_blocks[get_block].
2788 rxds[get_info.offset].virt_addr;
2789 if (get_info.offset == rxd_count[nic->rxd_mode]) {
20346722 2790 get_info.offset = 0;
da6971d8 2791 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 2792 get_block++;
da6971d8
AR		 2793 if (get_block == ring_data->block_count)
2794 get_block = 0;
2795 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 2796 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2797 }
1da177e4 2798
20346722 2799 nic->pkts_to_process -= 1;
db874e65 2800 if ((napi) && (!nic->pkts_to_process))
20346722 2801 break;
20346722 2802 pkt_cnt++;
1da177e4
LT		 2803 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2804 break;
2805 }
7d3d0439
RA		 2806 if (nic->lro) {
2807 /* Clear all LRO sessions before exiting */
2808 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 2809 struct lro *lro = &nic->lro0_n[i];
7d3d0439
RA		 2810 if (lro->in_use) {
2811 update_L3L4_header(nic, lro);
2812 queue_rx_frame(lro->parent);
2813 clear_lro_session(lro);
2814 }
2815 }
2816 }
2817
7ba013ac 2818 spin_unlock(&nic->rx_lock);
1da177e4 2819}
20346722
K		 2820
2821/**
1da177e4
LT		 2822 * tx_intr_handler - Transmit interrupt handler
2823 * @nic : device private variable
20346722
K		 2824 * Description:
2825 * If an interrupt was raised to indicate DMA complete of the
2826 * Tx packet, this function is called. It identifies the last TxD
2827 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 2828 * DMA'ed into the NICs internal memory.
2829 * Return Value:
2830 * NONE
2831 */
2832
1ee6dd77 2833static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 2834{
1ee6dd77 2835 struct s2io_nic *nic = fifo_data->nic;
1da177e4 2836 struct net_device *dev = (struct net_device *) nic->dev;
1ee6dd77 2837 struct tx_curr_get_info get_info, put_info;
1da177e4 2838 struct sk_buff *skb;
1ee6dd77 2839 struct TxD *txdlp;
f9046eb3 2840 u8 err_mask;
1da177e4 2841
20346722 2842 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 2843 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2844 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722
K		 2845 list_virt_addr;
2846 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2847 (get_info.offset != put_info.offset) &&
2848 (txdlp->Host_Control)) {
2849 /* Check for TxD errors */
2850 if (txdlp->Control_1 & TXD_T_CODE) {
2851 unsigned long long err;
2852 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 2853 if (err & 0x1) {
2854 nic->mac_control.stats_info->sw_stat.
2855 parity_err_cnt++;
2856 }
491976b2
SH		 2857
2858 /* update t_code statistics */
f9046eb3
OH		 2859 err_mask = err >> 48;
2860 switch(err_mask) {
491976b2
SH		 2861 case 2:
2862 nic->mac_control.stats_info->sw_stat.
2863 tx_buf_abort_cnt++;
2864 break;
2865
2866 case 3:
2867 nic->mac_control.stats_info->sw_stat.
2868 tx_desc_abort_cnt++;
2869 break;
2870
2871 case 7:
2872 nic->mac_control.stats_info->sw_stat.
2873 tx_parity_err_cnt++;
2874 break;
2875
2876 case 10:
2877 nic->mac_control.stats_info->sw_stat.
2878 tx_link_loss_cnt++;
2879 break;
2880
2881 case 15:
2882 nic->mac_control.stats_info->sw_stat.
2883 tx_list_proc_err_cnt++;
2884 break;
2885 }
20346722 2886 }
1da177e4 2887
fed5eccd 2888 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722
K		 2889 if (skb == NULL) {
2890 DBG_PRINT(ERR_DBG, "%s: Null skb ",
2891 __FUNCTION__);
2892 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
2893 return;
2894 }
2895
20346722 2896 /* Updating the statistics block */
20346722 2897 nic->stats.tx_bytes += skb->len;
491976b2 2898 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722
K		 2899 dev_kfree_skb_irq(skb);
2900
2901 get_info.offset++;
863c11a9
AR		 2902 if (get_info.offset == get_info.fifo_len + 1)
2903 get_info.offset = 0;
1ee6dd77 2904 txdlp = (struct TxD *) fifo_data->list_info
20346722
K		 2905 [get_info.offset].list_virt_addr;
2906 fifo_data->tx_curr_get_info.offset =
2907 get_info.offset;
1da177e4
LT		 2908 }
2909
2910 spin_lock(&nic->tx_lock);
2911 if (netif_queue_stopped(dev))
2912 netif_wake_queue(dev);
2913 spin_unlock(&nic->tx_lock);
2914}
2915
bd1034f0
AR		 2916/**
2917 * s2io_mdio_write - Function to write in to MDIO registers
2918 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2919 * @addr : address value
2920 * @value : data value
2921 * @dev : pointer to net_device structure
2922 * Description:
2923 * This function is used to write values to the MDIO registers
2924 * NONE
2925 */
2926static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
2927{
2928 u64 val64 = 0x0;
1ee6dd77
RB		 2929 struct s2io_nic *sp = dev->priv;
2930 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2931
2932 //address transaction
2933 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2934 | MDIO_MMD_DEV_ADDR(mmd_type)
2935 | MDIO_MMS_PRT_ADDR(0x0);
2936 writeq(val64, &bar0->mdio_control);
2937 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2938 writeq(val64, &bar0->mdio_control);
2939 udelay(100);
2940
2941 //Data transaction
2942 val64 = 0x0;
2943 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2944 | MDIO_MMD_DEV_ADDR(mmd_type)
2945 | MDIO_MMS_PRT_ADDR(0x0)
2946 | MDIO_MDIO_DATA(value)
2947 | MDIO_OP(MDIO_OP_WRITE_TRANS);
2948 writeq(val64, &bar0->mdio_control);
2949 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2950 writeq(val64, &bar0->mdio_control);
2951 udelay(100);
2952
2953 val64 = 0x0;
2954 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2955 | MDIO_MMD_DEV_ADDR(mmd_type)
2956 | MDIO_MMS_PRT_ADDR(0x0)
2957 | MDIO_OP(MDIO_OP_READ_TRANS);
2958 writeq(val64, &bar0->mdio_control);
2959 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2960 writeq(val64, &bar0->mdio_control);
2961 udelay(100);
2962
2963}
2964
2965/**
2966 * s2io_mdio_read - Function to write in to MDIO registers
2967 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
2968 * @addr : address value
2969 * @dev : pointer to net_device structure
2970 * Description:
2971 * This function is used to read values to the MDIO registers
2972 * NONE
2973 */
2974static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
2975{
2976 u64 val64 = 0x0;
2977 u64 rval64 = 0x0;
1ee6dd77
RB		 2978 struct s2io_nic *sp = dev->priv;
2979 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 2980
2981 /* address transaction */
2982 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2983 | MDIO_MMD_DEV_ADDR(mmd_type)
2984 | MDIO_MMS_PRT_ADDR(0x0);
2985 writeq(val64, &bar0->mdio_control);
2986 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2987 writeq(val64, &bar0->mdio_control);
2988 udelay(100);
2989
2990 /* Data transaction */
2991 val64 = 0x0;
2992 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
2993 | MDIO_MMD_DEV_ADDR(mmd_type)
2994 | MDIO_MMS_PRT_ADDR(0x0)
2995 | MDIO_OP(MDIO_OP_READ_TRANS);
2996 writeq(val64, &bar0->mdio_control);
2997 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
2998 writeq(val64, &bar0->mdio_control);
2999 udelay(100);
3000
3001 /* Read the value from regs */
3002 rval64 = readq(&bar0->mdio_control);
3003 rval64 = rval64 & 0xFFFF0000;
3004 rval64 = rval64 >> 16;
3005 return rval64;
3006}
3007/**
3008 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3009 * @counter : couter value to be updated
3010 * @flag : flag to indicate the status
3011 * @type : counter type
3012 * Description:
3013 * This function is to check the status of the xpak counters value
3014 * NONE
3015 */
3016
3017static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3018{
3019 u64 mask = 0x3;
3020 u64 val64;
3021 int i;
3022 for(i = 0; i <index; i++)
3023 mask = mask << 0x2;
3024
3025 if(flag > 0)
3026 {
3027 *counter = *counter + 1;
3028 val64 = *regs_stat & mask;
3029 val64 = val64 >> (index * 0x2);
3030 val64 = val64 + 1;
3031 if(val64 == 3)
3032 {
3033 switch(type)
3034 {
3035 case 1:
3036 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3037 "service. Excessive temperatures may "
3038 "result in premature transceiver "
3039 "failure \n");
3040 break;
3041 case 2:
3042 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3043 "service Excessive bias currents may "
3044 "indicate imminent laser diode "
3045 "failure \n");
3046 break;
3047 case 3:
3048 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3049 "service Excessive laser output "
3050 "power may saturate far-end "
3051 "receiver\n");
3052 break;
3053 default:
3054 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3055 "type \n");
3056 }
3057 val64 = 0x0;
3058 }
3059 val64 = val64 << (index * 0x2);
3060 *regs_stat = (*regs_stat & (~mask)) | (val64);
3061
3062 } else {
3063 *regs_stat = *regs_stat & (~mask);
3064 }
3065}
3066
3067/**
3068 * s2io_updt_xpak_counter - Function to update the xpak counters
3069 * @dev : pointer to net_device struct
3070 * Description:
3071 * This function is to upate the status of the xpak counters value
3072 * NONE
3073 */
3074static void s2io_updt_xpak_counter(struct net_device *dev)
3075{
3076 u16 flag = 0x0;
3077 u16 type = 0x0;
3078 u16 val16 = 0x0;
3079 u64 val64 = 0x0;
3080 u64 addr = 0x0;
3081
1ee6dd77
RB		 3082 struct s2io_nic *sp = dev->priv;
3083 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3084
3085 /* Check the communication with the MDIO slave */
3086 addr = 0x0000;
3087 val64 = 0x0;
3088 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3089 if((val64 == 0xFFFF) || (val64 == 0x0000))
3090 {
3091 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3092 "Returned %llx\n", (unsigned long long)val64);
3093 return;
3094 }
3095
3096 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3097 if(val64 != 0x2040)
3098 {
3099 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3100 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3101 (unsigned long long)val64);
3102 return;
3103 }
3104
3105 /* Loading the DOM register to MDIO register */
3106 addr = 0xA100;
3107 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3108 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3109
3110 /* Reading the Alarm flags */
3111 addr = 0xA070;
3112 val64 = 0x0;
3113 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3114
3115 flag = CHECKBIT(val64, 0x7);
3116 type = 1;
3117 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3118 &stat_info->xpak_stat.xpak_regs_stat,
3119 0x0, flag, type);
3120
3121 if(CHECKBIT(val64, 0x6))
3122 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3123
3124 flag = CHECKBIT(val64, 0x3);
3125 type = 2;
3126 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3127 &stat_info->xpak_stat.xpak_regs_stat,
3128 0x2, flag, type);
3129
3130 if(CHECKBIT(val64, 0x2))
3131 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3132
3133 flag = CHECKBIT(val64, 0x1);
3134 type = 3;
3135 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3136 &stat_info->xpak_stat.xpak_regs_stat,
3137 0x4, flag, type);
3138
3139 if(CHECKBIT(val64, 0x0))
3140 stat_info->xpak_stat.alarm_laser_output_power_low++;
3141
3142 /* Reading the Warning flags */
3143 addr = 0xA074;
3144 val64 = 0x0;
3145 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3146
3147 if(CHECKBIT(val64, 0x7))
3148 stat_info->xpak_stat.warn_transceiver_temp_high++;
3149
3150 if(CHECKBIT(val64, 0x6))
3151 stat_info->xpak_stat.warn_transceiver_temp_low++;
3152
3153 if(CHECKBIT(val64, 0x3))
3154 stat_info->xpak_stat.warn_laser_bias_current_high++;
3155
3156 if(CHECKBIT(val64, 0x2))
3157 stat_info->xpak_stat.warn_laser_bias_current_low++;
3158
3159 if(CHECKBIT(val64, 0x1))
3160 stat_info->xpak_stat.warn_laser_output_power_high++;
3161
3162 if(CHECKBIT(val64, 0x0))
3163 stat_info->xpak_stat.warn_laser_output_power_low++;
3164}
3165
20346722 3166/**
1da177e4
LT		 3167 * alarm_intr_handler - Alarm Interrrupt handler
3168 * @nic: device private variable
20346722 3169 * Description: If the interrupt was neither because of Rx packet or Tx
1da177e4 3170 * complete, this function is called. If the interrupt was to indicate
20346722
K		 3171 * a loss of link, the OSM link status handler is invoked for any other
3172 * alarm interrupt the block that raised the interrupt is displayed
1da177e4
LT		 3173 * and a H/W reset is issued.
3174 * Return Value:
3175 * NONE
3176*/
3177
3178static void alarm_intr_handler(struct s2io_nic *nic)
3179{
3180 struct net_device *dev = (struct net_device *) nic->dev;
1ee6dd77 3181 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 3182 register u64 val64 = 0, err_reg = 0;
bd1034f0
AR		 3183 u64 cnt;
3184 int i;
372cc597
SS		 3185 if (atomic_read(&nic->card_state) == CARD_DOWN)
3186 return;
d796fdb7
LV		 3187 if (pci_channel_offline(nic->pdev))
3188 return;
bd1034f0
AR		 3189 nic->mac_control.stats_info->sw_stat.ring_full_cnt = 0;
3190 /* Handling the XPAK counters update */
3191 if(nic->mac_control.stats_info->xpak_stat.xpak_timer_count < 72000) {
3192 /* waiting for an hour */
3193 nic->mac_control.stats_info->xpak_stat.xpak_timer_count++;
3194 } else {
3195 s2io_updt_xpak_counter(dev);
3196 /* reset the count to zero */
3197 nic->mac_control.stats_info->xpak_stat.xpak_timer_count = 0;
3198 }
1da177e4
LT		 3199
3200 /* Handling link status change error Intr */
a371a07d
K		 3201 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
3202 err_reg = readq(&bar0->mac_rmac_err_reg);
3203 writeq(err_reg, &bar0->mac_rmac_err_reg);
3204 if (err_reg & RMAC_LINK_STATE_CHANGE_INT) {
3205 schedule_work(&nic->set_link_task);
3206 }
1da177e4
LT		 3207 }
3208
5e25b9dd
K		 3209 /* Handling Ecc errors */
3210 val64 = readq(&bar0->mc_err_reg);
3211 writeq(val64, &bar0->mc_err_reg);
3212 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
3213 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
7ba013ac
K		 3214 nic->mac_control.stats_info->sw_stat.
3215 double_ecc_errs++;
776bd20f 3216 DBG_PRINT(INIT_DBG, "%s: Device indicates ",
5e25b9dd 3217 dev->name);
776bd20f 3218 DBG_PRINT(INIT_DBG, "double ECC error!!\n");
e960fc5c 3219 if (nic->device_type != XFRAME_II_DEVICE) {
776bd20f 3220 /* Reset XframeI only if critical error */
3221 if (val64 & (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
3222 MC_ERR_REG_MIRI_ECC_DB_ERR_1)) {
3223 netif_stop_queue(dev);
3224 schedule_work(&nic->rst_timer_task);
bd1034f0
AR		 3225 nic->mac_control.stats_info->sw_stat.
3226 soft_reset_cnt++;
776bd20f 3227 }
e960fc5c 3228 }
5e25b9dd 3229 } else {
7ba013ac
K		 3230 nic->mac_control.stats_info->sw_stat.
3231 single_ecc_errs++;
5e25b9dd
K		 3232 }
3233 }
3234
1da177e4
LT		 3235 /* In case of a serious error, the device will be Reset. */
3236 val64 = readq(&bar0->serr_source);
3237 if (val64 & SERR_SOURCE_ANY) {
bd1034f0 3238 nic->mac_control.stats_info->sw_stat.serious_err_cnt++;
1da177e4 3239 DBG_PRINT(ERR_DBG, "%s: Device indicates ", dev->name);
6aa20a22 3240 DBG_PRINT(ERR_DBG, "serious error %llx!!\n",
776bd20f 3241 (unsigned long long)val64);
1da177e4
LT		 3242 netif_stop_queue(dev);
3243 schedule_work(&nic->rst_timer_task);
bd1034f0 3244 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 3245 }
3246
3247 /*
3248 * Also as mentioned in the latest Errata sheets if the PCC_FB_ECC
3249 * Error occurs, the adapter will be recycled by disabling the
20346722 3250 * adapter enable bit and enabling it again after the device
1da177e4
LT		 3251 * becomes Quiescent.
3252 */
3253 val64 = readq(&bar0->pcc_err_reg);
3254 writeq(val64, &bar0->pcc_err_reg);
3255 if (val64 & PCC_FB_ECC_DB_ERR) {
3256 u64 ac = readq(&bar0->adapter_control);
3257 ac &= ~(ADAPTER_CNTL_EN);
3258 writeq(ac, &bar0->adapter_control);
3259 ac = readq(&bar0->adapter_control);
3260 schedule_work(&nic->set_link_task);
3261 }
bd1034f0
AR		 3262 /* Check for data parity error */
3263 val64 = readq(&bar0->pic_int_status);
3264 if (val64 & PIC_INT_GPIO) {
3265 val64 = readq(&bar0->gpio_int_reg);
3266 if (val64 & GPIO_INT_REG_DP_ERR_INT) {
3267 nic->mac_control.stats_info->sw_stat.parity_err_cnt++;
3268 schedule_work(&nic->rst_timer_task);
3269 nic->mac_control.stats_info->sw_stat.soft_reset_cnt++;
3270 }
3271 }
3272
3273 /* Check for ring full counter */
3274 if (nic->device_type & XFRAME_II_DEVICE) {
3275 val64 = readq(&bar0->ring_bump_counter1);
3276 for (i=0; i<4; i++) {
3277 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3278 cnt >>= 64 - ((i+1)*16);
3279 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3280 += cnt;
3281 }
3282
3283 val64 = readq(&bar0->ring_bump_counter2);
3284 for (i=0; i<4; i++) {
3285 cnt = ( val64 & vBIT(0xFFFF,(i*16),16));
3286 cnt >>= 64 - ((i+1)*16);
3287 nic->mac_control.stats_info->sw_stat.ring_full_cnt
3288 += cnt;
3289 }
3290 }
1da177e4
LT		 3291
3292 /* Other type of interrupts are not being handled now, TODO */
3293}
3294
20346722 3295/**
1da177e4 3296 * wait_for_cmd_complete - waits for a command to complete.
20346722 3297 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3298 * s2io_nic structure.
20346722
K		 3299 * Description: Function that waits for a command to Write into RMAC
3300 * ADDR DATA registers to be completed and returns either success or
3301 * error depending on whether the command was complete or not.
1da177e4
LT		 3302 * Return value:
3303 * SUCCESS on success and FAILURE on failure.
3304 */
3305
9fc93a41
SS		 3306static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3307 int bit_state)
1da177e4 3308{
9fc93a41 3309 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3310 u64 val64;
3311
9fc93a41
SS		 3312 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3313 return FAILURE;
3314
3315 do {
c92ca04b 3316 val64 = readq(addr);
9fc93a41
SS		 3317 if (bit_state == S2IO_BIT_RESET) {
3318 if (!(val64 & busy_bit)) {
3319 ret = SUCCESS;
3320 break;
3321 }
3322 } else {
3323 if (!(val64 & busy_bit)) {
3324 ret = SUCCESS;
3325 break;
3326 }
1da177e4 3327 }
c92ca04b
AR		 3328
3329 if(in_interrupt())
9fc93a41 3330 mdelay(delay);
c92ca04b 3331 else
9fc93a41 3332 msleep(delay);
c92ca04b 3333
9fc93a41
SS		 3334 if (++cnt >= 10)
3335 delay = 50;
3336 } while (cnt < 20);
1da177e4
LT		 3337 return ret;
3338}
19a60522
SS		 3339/*
3340 * check_pci_device_id - Checks if the device id is supported
3341 * @id : device id
3342 * Description: Function to check if the pci device id is supported by driver.
3343 * Return value: Actual device id if supported else PCI_ANY_ID
3344 */
3345static u16 check_pci_device_id(u16 id)
3346{
3347 switch (id) {
3348 case PCI_DEVICE_ID_HERC_WIN:
3349 case PCI_DEVICE_ID_HERC_UNI:
3350 return XFRAME_II_DEVICE;
3351 case PCI_DEVICE_ID_S2IO_UNI:
3352 case PCI_DEVICE_ID_S2IO_WIN:
3353 return XFRAME_I_DEVICE;
3354 default:
3355 return PCI_ANY_ID;
3356 }
3357}
1da177e4 3358
20346722
K		 3359/**
3360 * s2io_reset - Resets the card.
1da177e4
LT		 3361 * @sp : private member of the device structure.
3362 * Description: Function to Reset the card. This function then also
20346722 3363 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3364 * the card reset also resets the configuration space.
3365 * Return value:
3366 * void.
3367 */
3368
1ee6dd77 3369static void s2io_reset(struct s2io_nic * sp)
1da177e4 3370{
1ee6dd77 3371 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3372 u64 val64;
5e25b9dd 3373 u16 subid, pci_cmd;
19a60522
SS		 3374 int i;
3375 u16 val16;
491976b2
SH		 3376 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3377 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3378
19a60522
SS		 3379 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3380 __FUNCTION__, sp->dev->name);
1da177e4 3381
0b1f7ebe 3382 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3383 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3384
1da177e4
LT		 3385 val64 = SW_RESET_ALL;
3386 writeq(val64, &bar0->sw_reset);
c92ca04b
AR		 3387 if (strstr(sp->product_name, "CX4")) {
3388 msleep(750);
3389 }
19a60522
SS		 3390 msleep(250);
3391 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3392
19a60522
SS		 3393 /* Restore the PCI state saved during initialization. */
3394 pci_restore_state(sp->pdev);
3395 pci_read_config_word(sp->pdev, 0x2, &val16);
3396 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3397 break;
3398 msleep(200);
3399 }
1da177e4 3400
19a60522
SS		 3401 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3402 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3403 }
3404
3405 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3406
3407 s2io_init_pci(sp);
1da177e4 3408
20346722
K		 3409 /* Set swapper to enable I/O register access */
3410 s2io_set_swapper(sp);
3411
cc6e7c44
RA		 3412 /* Restore the MSIX table entries from local variables */
3413 restore_xmsi_data(sp);
3414
5e25b9dd 3415 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3416 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3417 /* Clear "detected parity error" bit */
303bcb4b 3418 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3419
303bcb4b
K		 3420 /* Clearing PCIX Ecc status register */
3421 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3422
303bcb4b
K		 3423 /* Clearing PCI_STATUS error reflected here */
3424 writeq(BIT(62), &bar0->txpic_int_reg);
3425 }
5e25b9dd 3426
20346722
K		 3427 /* Reset device statistics maintained by OS */
3428 memset(&sp->stats, 0, sizeof (struct net_device_stats));
491976b2
SH		 3429
3430 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3431 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3432 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3433 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3434 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3435 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3436 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3437 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3438 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3439 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3440 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3441 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3442 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3443 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3444 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3445 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3446 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3447 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3448 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3449
1da177e4
LT		 3450 /* SXE-002: Configure link and activity LED to turn it off */
3451 subid = sp->pdev->subsystem_device;
541ae68f
K		 3452 if (((subid & 0xFF) >= 0x07) &&
3453 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3454 val64 = readq(&bar0->gpio_control);
3455 val64 |= 0x0000800000000000ULL;
3456 writeq(val64, &bar0->gpio_control);
3457 val64 = 0x0411040400000000ULL;
509a2671 3458 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3459 }
3460
541ae68f
K		 3461 /*
3462 * Clear spurious ECC interrupts that would have occured on
3463 * XFRAME II cards after reset.
3464 */
3465 if (sp->device_type == XFRAME_II_DEVICE) {
3466 val64 = readq(&bar0->pcc_err_reg);
3467 writeq(val64, &bar0->pcc_err_reg);
3468 }
3469
d8d70caf
SS		 3470 /* restore the previously assigned mac address */
3471 s2io_set_mac_addr(sp->dev, (u8 *)&sp->def_mac_addr[0].mac_addr);
3472
1da177e4
LT		 3473 sp->device_enabled_once = FALSE;
3474}
3475
3476/**
20346722
K		 3477 * s2io_set_swapper - to set the swapper controle on the card
3478 * @sp : private member of the device structure,
1da177e4 3479 * pointer to the s2io_nic structure.
20346722 3480 * Description: Function to set the swapper control on the card
1da177e4
LT		 3481 * correctly depending on the 'endianness' of the system.
3482 * Return value:
3483 * SUCCESS on success and FAILURE on failure.
3484 */
3485
1ee6dd77 3486static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3487{
3488 struct net_device *dev = sp->dev;
1ee6dd77 3489 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3490 u64 val64, valt, valr;
3491
20346722 3492 /*
1da177e4
LT		 3493 * Set proper endian settings and verify the same by reading
3494 * the PIF Feed-back register.
3495 */
3496
3497 val64 = readq(&bar0->pif_rd_swapper_fb);
3498 if (val64 != 0x0123456789ABCDEFULL) {
3499 int i = 0;
3500 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3501 0x8100008181000081ULL, /* FE=1, SE=0 */
3502 0x4200004242000042ULL, /* FE=0, SE=1 */
3503 0}; /* FE=0, SE=0 */
3504
3505 while(i<4) {
3506 writeq(value[i], &bar0->swapper_ctrl);
3507 val64 = readq(&bar0->pif_rd_swapper_fb);
3508 if (val64 == 0x0123456789ABCDEFULL)
3509 break;
3510 i++;
3511 }
3512 if (i == 4) {
3513 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3514 dev->name);
3515 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3516 (unsigned long long) val64);
3517 return FAILURE;
3518 }
3519 valr = value[i];
3520 } else {
3521 valr = readq(&bar0->swapper_ctrl);
3522 }
3523
3524 valt = 0x0123456789ABCDEFULL;
3525 writeq(valt, &bar0->xmsi_address);
3526 val64 = readq(&bar0->xmsi_address);
3527
3528 if(val64 != valt) {
3529 int i = 0;
3530 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3531 0x0081810000818100ULL, /* FE=1, SE=0 */
3532 0x0042420000424200ULL, /* FE=0, SE=1 */
3533 0}; /* FE=0, SE=0 */
3534
3535 while(i<4) {
3536 writeq((value[i] | valr), &bar0->swapper_ctrl);
3537 writeq(valt, &bar0->xmsi_address);
3538 val64 = readq(&bar0->xmsi_address);
3539 if(val64 == valt)
3540 break;
3541 i++;
3542 }
3543 if(i == 4) {
20346722 3544 unsigned long long x = val64;
1da177e4 3545 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3546 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3547 return FAILURE;
3548 }
3549 }
3550 val64 = readq(&bar0->swapper_ctrl);
3551 val64 &= 0xFFFF000000000000ULL;
3552
3553#ifdef __BIG_ENDIAN
20346722
K		 3554 /*
3555 * The device by default set to a big endian format, so a
1da177e4
LT		 3556 * big endian driver need not set anything.
3557 */
3558 val64 |= (SWAPPER_CTRL_TXP_FE |
3559 SWAPPER_CTRL_TXP_SE |
3560 SWAPPER_CTRL_TXD_R_FE |
3561 SWAPPER_CTRL_TXD_W_FE |
3562 SWAPPER_CTRL_TXF_R_FE |
3563 SWAPPER_CTRL_RXD_R_FE |
3564 SWAPPER_CTRL_RXD_W_FE |
3565 SWAPPER_CTRL_RXF_W_FE |
3566 SWAPPER_CTRL_XMSI_FE |
1da177e4 3567 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
92383340 3568 if (sp->intr_type == INTA)
cc6e7c44 3569 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3570 writeq(val64, &bar0->swapper_ctrl);
3571#else
20346722 3572 /*
1da177e4 3573 * Initially we enable all bits to make it accessible by the
20346722 3574 * driver, then we selectively enable only those bits that
1da177e4
LT		 3575 * we want to set.
3576 */
3577 val64 |= (SWAPPER_CTRL_TXP_FE |
3578 SWAPPER_CTRL_TXP_SE |
3579 SWAPPER_CTRL_TXD_R_FE |
3580 SWAPPER_CTRL_TXD_R_SE |
3581 SWAPPER_CTRL_TXD_W_FE |
3582 SWAPPER_CTRL_TXD_W_SE |
3583 SWAPPER_CTRL_TXF_R_FE |
3584 SWAPPER_CTRL_RXD_R_FE |
3585 SWAPPER_CTRL_RXD_R_SE |
3586 SWAPPER_CTRL_RXD_W_FE |
3587 SWAPPER_CTRL_RXD_W_SE |
3588 SWAPPER_CTRL_RXF_W_FE |
3589 SWAPPER_CTRL_XMSI_FE |
1da177e4 3590 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
cc6e7c44
RA		 3591 if (sp->intr_type == INTA)
3592 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3593 writeq(val64, &bar0->swapper_ctrl);
3594#endif
3595 val64 = readq(&bar0->swapper_ctrl);
3596
20346722
K		 3597 /*
3598 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3599 * feedback register.
3600 */
3601 val64 = readq(&bar0->pif_rd_swapper_fb);
3602 if (val64 != 0x0123456789ABCDEFULL) {
3603 /* Endian settings are incorrect, calls for another dekko. */
3604 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3605 dev->name);
3606 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3607 (unsigned long long) val64);
3608 return FAILURE;
3609 }
3610
3611 return SUCCESS;
3612}
3613
1ee6dd77 3614static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3615{
1ee6dd77 3616 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3617 u64 val64;
3618 int ret = 0, cnt = 0;
3619
3620 do {
3621 val64 = readq(&bar0->xmsi_access);
3622 if (!(val64 & BIT(15)))
3623 break;
3624 mdelay(1);
3625 cnt++;
3626 } while(cnt < 5);
3627 if (cnt == 5) {
3628 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3629 ret = 1;
3630 }
3631
3632 return ret;
3633}
3634
1ee6dd77 3635static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3636{
1ee6dd77 3637 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3638 u64 val64;
3639 int i;
3640
75c30b13 3641 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3642 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3643 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3644 val64 = (BIT(7) | BIT(15) | vBIT(i, 26, 6));
3645 writeq(val64, &bar0->xmsi_access);
3646 if (wait_for_msix_trans(nic, i)) {
3647 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3648 continue;
3649 }
3650 }
3651}
3652
1ee6dd77 3653static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3654{
1ee6dd77 3655 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3656 u64 val64, addr, data;
3657 int i;
3658
3659 /* Store and display */
75c30b13 3660 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3661 val64 = (BIT(15) | vBIT(i, 26, 6));
3662 writeq(val64, &bar0->xmsi_access);
3663 if (wait_for_msix_trans(nic, i)) {
3664 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3665 continue;
3666 }
3667 addr = readq(&bar0->xmsi_address);
3668 data = readq(&bar0->xmsi_data);
3669 if (addr && data) {
3670 nic->msix_info[i].addr = addr;
3671 nic->msix_info[i].data = data;
3672 }
3673 }
3674}
3675
1ee6dd77 3676static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3677{
1ee6dd77 3678 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3679 u64 tx_mat, rx_mat;
3680 u16 msi_control; /* Temp variable */
3681 int ret, i, j, msix_indx = 1;
3682
3683 nic->entries = kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct msix_entry),
3684 GFP_KERNEL);
3685 if (nic->entries == NULL) {
491976b2
SH		 3686 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3687 __FUNCTION__);
c53d4945 3688 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3689 return -ENOMEM;
3690 }
491976b2
SH		 3691 nic->mac_control.stats_info->sw_stat.mem_allocated
3692 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3693 memset(nic->entries, 0,MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3694
3695 nic->s2io_entries =
3696 kmalloc(MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry),
3697 GFP_KERNEL);
3698 if (nic->s2io_entries == NULL) {
491976b2
SH		 3699 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3700 __FUNCTION__);
c53d4945 3701 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3702 kfree(nic->entries);
491976b2
SH		 3703 nic->mac_control.stats_info->sw_stat.mem_freed
3704 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3705 return -ENOMEM;
3706 }
491976b2
SH		 3707 nic->mac_control.stats_info->sw_stat.mem_allocated
3708 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3709 memset(nic->s2io_entries, 0,
3710 MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3711
3712 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3713 nic->entries[i].entry = i;
3714 nic->s2io_entries[i].entry = i;
3715 nic->s2io_entries[i].arg = NULL;
3716 nic->s2io_entries[i].in_use = 0;
3717 }
3718
3719 tx_mat = readq(&bar0->tx_mat0_n[0]);
3720 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3721 tx_mat |= TX_MAT_SET(i, msix_indx);
3722 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3723 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3724 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3725 }
3726 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3727
3728 if (!nic->config.bimodal) {
3729 rx_mat = readq(&bar0->rx_mat);
3730 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3731 rx_mat |= RX_MAT_SET(j, msix_indx);
491976b2
SH		 3732 nic->s2io_entries[msix_indx].arg
3733 = &nic->mac_control.rings[j];
cc6e7c44
RA		 3734 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3735 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3736 }
3737 writeq(rx_mat, &bar0->rx_mat);
3738 } else {
3739 tx_mat = readq(&bar0->tx_mat0_n[7]);
3740 for (j=0; j<nic->config.rx_ring_num; j++, msix_indx++) {
3741 tx_mat |= TX_MAT_SET(i, msix_indx);
491976b2
SH		 3742 nic->s2io_entries[msix_indx].arg
3743 = &nic->mac_control.rings[j];
cc6e7c44
RA		 3744 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3745 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3746 }
3747 writeq(tx_mat, &bar0->tx_mat0_n[7]);
3748 }
3749
c92ca04b 3750 nic->avail_msix_vectors = 0;
cc6e7c44 3751 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
c92ca04b
AR		 3752 /* We fail init if error or we get less vectors than min required */
3753 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3754 nic->avail_msix_vectors = ret;
3755 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3756 }
cc6e7c44
RA		 3757 if (ret) {
3758 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3759 kfree(nic->entries);
491976b2
SH		 3760 nic->mac_control.stats_info->sw_stat.mem_freed
3761 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44 3762 kfree(nic->s2io_entries);
491976b2
SH		 3763 nic->mac_control.stats_info->sw_stat.mem_freed
3764 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3765 nic->entries = NULL;
3766 nic->s2io_entries = NULL;
c92ca04b 3767 nic->avail_msix_vectors = 0;
cc6e7c44
RA		 3768 return -ENOMEM;
3769 }
c92ca04b
AR		 3770 if (!nic->avail_msix_vectors)
3771 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
cc6e7c44
RA		 3772
3773 /*
3774 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3775 * in the herc NIC. (Temp change, needs to be removed later)
3776 */
3777 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3778 msi_control |= 0x1; /* Enable MSI */
3779 pci_write_config_word(nic->pdev, 0x42, msi_control);
3780
3781 return 0;
3782}
3783
1da177e4
LT		 3784/* ********************************************************* *
3785 * Functions defined below concern the OS part of the driver *
3786 * ********************************************************* */
3787
20346722 3788/**
1da177e4
LT		 3789 * s2io_open - open entry point of the driver
3790 * @dev : pointer to the device structure.
3791 * Description:
3792 * This function is the open entry point of the driver. It mainly calls a
3793 * function to allocate Rx buffers and inserts them into the buffer
20346722 3794 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3795 * Return value:
3796 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3797 * file on failure.
3798 */
3799
ac1f60db 3800static int s2io_open(struct net_device *dev)
1da177e4 3801{
1ee6dd77 3802 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3803 int err = 0;
3804
20346722
K		 3805 /*
3806 * Make sure you have link off by default every time
1da177e4
LT		 3807 * Nic is initialized
3808 */
3809 netif_carrier_off(dev);
0b1f7ebe 3810 sp->last_link_state = 0;
1da177e4
LT		 3811
3812 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3813 err = s2io_card_up(sp);
3814 if (err) {
1da177e4
LT		 3815 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3816 dev->name);
e6a8fee2 3817 goto hw_init_failed;
1da177e4
LT		 3818 }
3819
3820 if (s2io_set_mac_addr(dev, dev->dev_addr) == FAILURE) {
3821 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 3822 s2io_card_down(sp);
20346722 3823 err = -ENODEV;
e6a8fee2 3824 goto hw_init_failed;
1da177e4
LT		 3825 }
3826
3827 netif_start_queue(dev);
3828 return 0;
20346722 3829
20346722 3830hw_init_failed:
cc6e7c44 3831 if (sp->intr_type == MSI_X) {
491976b2 3832 if (sp->entries) {
cc6e7c44 3833 kfree(sp->entries);
491976b2
SH		 3834 sp->mac_control.stats_info->sw_stat.mem_freed
3835 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3836 }
3837 if (sp->s2io_entries) {
cc6e7c44 3838 kfree(sp->s2io_entries);
491976b2
SH		 3839 sp->mac_control.stats_info->sw_stat.mem_freed
3840 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3841 }
cc6e7c44 3842 }
20346722 3843 return err;
1da177e4
LT		 3844}
3845
3846/**
3847 * s2io_close -close entry point of the driver
3848 * @dev : device pointer.
3849 * Description:
3850 * This is the stop entry point of the driver. It needs to undo exactly
3851 * whatever was done by the open entry point,thus it's usually referred to
3852 * as the close function.Among other things this function mainly stops the
3853 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3854 * Return value:
3855 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3856 * file on failure.
3857 */
3858
ac1f60db 3859static int s2io_close(struct net_device *dev)
1da177e4 3860{
1ee6dd77 3861 struct s2io_nic *sp = dev->priv;
cc6e7c44 3862
1da177e4
LT		 3863 netif_stop_queue(dev);
3864 /* Reset card, kill tasklet and free Tx and Rx buffers. */
e6a8fee2 3865 s2io_card_down(sp);
cc6e7c44 3866
1da177e4
LT		 3867 return 0;
3868}
3869
3870/**
3871 * s2io_xmit - Tx entry point of te driver
3872 * @skb : the socket buffer containing the Tx data.
3873 * @dev : device pointer.
3874 * Description :
3875 * This function is the Tx entry point of the driver. S2IO NIC supports
3876 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
3877 * NOTE: when device cant queue the pkt,just the trans_start variable will
3878 * not be upadted.
3879 * Return value:
3880 * 0 on success & 1 on failure.
3881 */
3882
ac1f60db 3883static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 3884{
1ee6dd77 3885 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3886 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
3887 register u64 val64;
1ee6dd77
RB		 3888 struct TxD *txdp;
3889 struct TxFIFO_element __iomem *tx_fifo;
1da177e4 3890 unsigned long flags;
be3a6b02
K		 3891 u16 vlan_tag = 0;
3892 int vlan_priority = 0;
1ee6dd77 3893 struct mac_info *mac_control;
1da177e4 3894 struct config_param *config;
75c30b13 3895 int offload_type;
491abf25 3896 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 3897
3898 mac_control = &sp->mac_control;
3899 config = &sp->config;
3900
20346722 3901 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 3902
3903 if (unlikely(skb->len <= 0)) {
3904 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
3905 dev_kfree_skb_any(skb);
3906 return 0;
3907}
3908
1da177e4 3909 spin_lock_irqsave(&sp->tx_lock, flags);
1da177e4 3910 if (atomic_read(&sp->card_state) == CARD_DOWN) {
20346722 3911 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4
LT		 3912 dev->name);
3913 spin_unlock_irqrestore(&sp->tx_lock, flags);
20346722
K		 3914 dev_kfree_skb(skb);
3915 return 0;
1da177e4
LT		 3916 }
3917
3918 queue = 0;
be3a6b02
K		 3919 /* Get Fifo number to Transmit based on vlan priority */
3920 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3921 vlan_tag = vlan_tx_tag_get(skb);
3922 vlan_priority = vlan_tag >> 13;
3923 queue = config->fifo_mapping[vlan_priority];
3924 }
3925
20346722
K		 3926 put_off = (u16) mac_control->fifos[queue].tx_curr_put_info.offset;
3927 get_off = (u16) mac_control->fifos[queue].tx_curr_get_info.offset;
1ee6dd77 3928 txdp = (struct TxD *) mac_control->fifos[queue].list_info[put_off].
20346722
K		 3929 list_virt_addr;
3930
3931 queue_len = mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
1da177e4 3932 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 3933 if (txdp->Host_Control ||
3934 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 3935 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
1da177e4
LT		 3936 netif_stop_queue(dev);
3937 dev_kfree_skb(skb);
3938 spin_unlock_irqrestore(&sp->tx_lock, flags);
3939 return 0;
3940 }
0b1f7ebe 3941
75c30b13 3942 offload_type = s2io_offload_type(skb);
75c30b13 3943 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 3944 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 3945 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 3946 }
84fa7933 3947 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 3948 txdp->Control_2 |=
3949 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
3950 TXD_TX_CKO_UDP_EN);
3951 }
fed5eccd
AR		 3952 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
3953 txdp->Control_1 |= TXD_LIST_OWN_XENA;
1da177e4 3954 txdp->Control_2 |= config->tx_intr_type;
d8892c6e 3955
be3a6b02
K		 3956 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
3957 txdp->Control_2 |= TXD_VLAN_ENABLE;
3958 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
3959 }
3960
fed5eccd 3961 frg_len = skb->len - skb->data_len;
75c30b13 3962 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 3963 int ufo_size;
3964
75c30b13 3965 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 3966 ufo_size &= ~7;
3967 txdp->Control_1 |= TXD_UFO_EN;
3968 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
3969 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
3970#ifdef __BIG_ENDIAN
3971 sp->ufo_in_band_v[put_off] =
3972 (u64)skb_shinfo(skb)->ip6_frag_id;
3973#else
3974 sp->ufo_in_band_v[put_off] =
3975 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
3976#endif
3977 txdp->Host_Control = (unsigned long)sp->ufo_in_band_v;
3978 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
3979 sp->ufo_in_band_v,
3980 sizeof(u64), PCI_DMA_TODEVICE);
491abf25
VP		 3981 if((txdp->Buffer_Pointer == 0) ||
3982 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
3983 goto pci_map_failed;
fed5eccd 3984 txdp++;
fed5eccd 3985 }
1da177e4 3986
fed5eccd
AR		 3987 txdp->Buffer_Pointer = pci_map_single
3988 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
491abf25
VP		 3989 if((txdp->Buffer_Pointer == 0) ||
3990 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
3991 goto pci_map_failed;
3992
fed5eccd
AR		 3993 txdp->Host_Control = (unsigned long) skb;
3994 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 3995 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 3996 txdp->Control_1 |= TXD_UFO_EN;
3997
3998 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 3999 /* For fragmented SKB. */
4000 for (i = 0; i < frg_cnt; i++) {
4001 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4002 /* A '0' length fragment will be ignored */
4003 if (!frag->size)
4004 continue;
1da177e4
LT		 4005 txdp++;
4006 txdp->Buffer_Pointer = (u64) pci_map_page
4007 (sp->pdev, frag->page, frag->page_offset,
4008 frag->size, PCI_DMA_TODEVICE);
efd51b5c 4009 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4010 if (offload_type == SKB_GSO_UDP)
fed5eccd 4011 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4012 }
4013 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4014
75c30b13 4015 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4016 frg_cnt++; /* as Txd0 was used for inband header */
4017
1da177e4 4018 tx_fifo = mac_control->tx_FIFO_start[queue];
20346722 4019 val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
1da177e4
LT		 4020 writeq(val64, &tx_fifo->TxDL_Pointer);
4021
4022 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4023 TX_FIFO_LAST_LIST);
75c30b13 4024 if (offload_type)
fed5eccd 4025 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4026
1da177e4
LT		 4027 writeq(val64, &tx_fifo->List_Control);
4028
303bcb4b
K		 4029 mmiowb();
4030
1da177e4 4031 put_off++;
863c11a9
AR		 4032 if (put_off == mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1)
4033 put_off = 0;
20346722 4034 mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
1da177e4
LT		 4035
4036 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4037 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4038 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4039 DBG_PRINT(TX_DBG,
4040 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4041 put_off, get_off);
4042 netif_stop_queue(dev);
4043 }
491976b2 4044 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
1da177e4
LT		 4045 dev->trans_start = jiffies;
4046 spin_unlock_irqrestore(&sp->tx_lock, flags);
4047
491abf25
VP		 4048 return 0;
4049pci_map_failed:
4050 stats->pci_map_fail_cnt++;
4051 netif_stop_queue(dev);
4052 stats->mem_freed += skb->truesize;
4053 dev_kfree_skb(skb);
4054 spin_unlock_irqrestore(&sp->tx_lock, flags);
1da177e4
LT		 4055 return 0;
4056}
4057
25fff88e
K		 4058static void
4059s2io_alarm_handle(unsigned long data)
4060{
1ee6dd77 4061 struct s2io_nic *sp = (struct s2io_nic *)data;
25fff88e
K		 4062
4063 alarm_intr_handler(sp);
4064 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4065}
4066
1ee6dd77 4067static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
75c30b13
AR		 4068{
4069 int rxb_size, level;
4070
4071 if (!sp->lro) {
4072 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4073 level = rx_buffer_level(sp, rxb_size, rng_n);
4074
4075 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4076 int ret;
4077 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4078 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4079 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
0c61ed5f 4080 DBG_PRINT(INFO_DBG, "Out of memory in %s",
75c30b13
AR		 4081 __FUNCTION__);
4082 clear_bit(0, (&sp->tasklet_status));
4083 return -1;
4084 }
4085 clear_bit(0, (&sp->tasklet_status));
4086 } else if (level == LOW)
4087 tasklet_schedule(&sp->task);
4088
4089 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
0c61ed5f
RV		 4090 DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4091 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
75c30b13
AR		 4092 }
4093 return 0;
4094}
4095
7d12e780 4096static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4097{
1ee6dd77
RB		 4098 struct ring_info *ring = (struct ring_info *)dev_id;
4099 struct s2io_nic *sp = ring->nic;
cc6e7c44
RA		 4100
4101 atomic_inc(&sp->isr_cnt);
cc6e7c44 4102
75c30b13
AR		 4103 rx_intr_handler(ring);
4104 s2io_chk_rx_buffers(sp, ring->ring_no);
7d3d0439 4105
cc6e7c44 4106 atomic_dec(&sp->isr_cnt);
cc6e7c44
RA		 4107 return IRQ_HANDLED;
4108}
4109
7d12e780 4110static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4111{
1ee6dd77
RB		 4112 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4113 struct s2io_nic *sp = fifo->nic;
cc6e7c44
RA		 4114
4115 atomic_inc(&sp->isr_cnt);
4116 tx_intr_handler(fifo);
4117 atomic_dec(&sp->isr_cnt);
4118 return IRQ_HANDLED;
4119}
1ee6dd77 4120static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4121{
1ee6dd77 4122 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4123 u64 val64;
4124
4125 val64 = readq(&bar0->pic_int_status);
4126 if (val64 & PIC_INT_GPIO) {
4127 val64 = readq(&bar0->gpio_int_reg);
4128 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4129 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4130 /*
4131 * This is unstable state so clear both up/down
4132 * interrupt and adapter to re-evaluate the link state.
4133 */
a371a07d
K		 4134 val64 |= GPIO_INT_REG_LINK_DOWN;
4135 val64 |= GPIO_INT_REG_LINK_UP;
4136 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4137 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4138 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4139 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4140 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4141 }
c92ca04b
AR		 4142 else if (val64 & GPIO_INT_REG_LINK_UP) {
4143 val64 = readq(&bar0->adapter_status);
c92ca04b 4144 /* Enable Adapter */
19a60522
SS		 4145 val64 = readq(&bar0->adapter_control);
4146 val64 |= ADAPTER_CNTL_EN;
4147 writeq(val64, &bar0->adapter_control);
4148 val64 |= ADAPTER_LED_ON;
4149 writeq(val64, &bar0->adapter_control);
4150 if (!sp->device_enabled_once)
4151 sp->device_enabled_once = 1;
c92ca04b 4152
19a60522
SS		 4153 s2io_link(sp, LINK_UP);
4154 /*
4155 * unmask link down interrupt and mask link-up
4156 * intr
4157 */
4158 val64 = readq(&bar0->gpio_int_mask);
4159 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4160 val64 |= GPIO_INT_MASK_LINK_UP;
4161 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4162
c92ca04b
AR		 4163 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4164 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4165 s2io_link(sp, LINK_DOWN);
4166 /* Link is down so unmaks link up interrupt */
4167 val64 = readq(&bar0->gpio_int_mask);
4168 val64 &= ~GPIO_INT_MASK_LINK_UP;
4169 val64 |= GPIO_INT_MASK_LINK_DOWN;
4170 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4171
4172 /* turn off LED */
4173 val64 = readq(&bar0->adapter_control);
4174 val64 = val64 &(~ADAPTER_LED_ON);
4175 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4176 }
4177 }
c92ca04b 4178 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4179}
4180
1da177e4
LT		 4181/**
4182 * s2io_isr - ISR handler of the device .
4183 * @irq: the irq of the device.
4184 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4185 * Description: This function is the ISR handler of the device. It
4186 * identifies the reason for the interrupt and calls the relevant
4187 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4188 * recv buffers, if their numbers are below the panic value which is
4189 * presently set to 25% of the original number of rcv buffers allocated.
4190 * Return value:
20346722 4191 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4192 * IRQ_NONE: will be returned if interrupt is not from our device
4193 */
7d12e780 4194static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4195{
4196 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77
RB		 4197 struct s2io_nic *sp = dev->priv;
4198 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4199 int i;
19a60522 4200 u64 reason = 0;
1ee6dd77 4201 struct mac_info *mac_control;
1da177e4
LT		 4202 struct config_param *config;
4203
d796fdb7
LV		 4204 /* Pretend we handled any irq's from a disconnected card */
4205 if (pci_channel_offline(sp->pdev))
4206 return IRQ_NONE;
4207
7ba013ac 4208 atomic_inc(&sp->isr_cnt);
1da177e4
LT		 4209 mac_control = &sp->mac_control;
4210 config = &sp->config;
4211
20346722 4212 /*
1da177e4
LT		 4213 * Identify the cause for interrupt and call the appropriate
4214 * interrupt handler. Causes for the interrupt could be;
4215 * 1. Rx of packet.
4216 * 2. Tx complete.
4217 * 3. Link down.
20346722 4218 * 4. Error in any functional blocks of the NIC.
1da177e4
LT		 4219 */
4220 reason = readq(&bar0->general_int_status);
4221
4222 if (!reason) {
19a60522
SS		 4223 /* The interrupt was not raised by us. */
4224 atomic_dec(&sp->isr_cnt);
4225 return IRQ_NONE;
4226 }
4227 else if (unlikely(reason == S2IO_MINUS_ONE) ) {
4228 /* Disable device and get out */
7ba013ac 4229 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4230 return IRQ_NONE;
4231 }
5d3213cc 4232
db874e65
SS		 4233 if (napi) {
4234 if (reason & GEN_INTR_RXTRAFFIC) {
19a60522 4235 if ( likely ( netif_rx_schedule_prep(dev)) ) {
db874e65 4236 __netif_rx_schedule(dev);
19a60522 4237 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
db874e65 4238 }
19a60522
SS		 4239 else
4240 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
db874e65
SS		 4241 }
4242 } else {
4243 /*
4244 * Rx handler is called by default, without checking for the
4245 * cause of interrupt.
4246 * rx_traffic_int reg is an R1 register, writing all 1's
4247 * will ensure that the actual interrupt causing bit get's
4248 * cleared and hence a read can be avoided.
4249 */
19a60522
SS		 4250 if (reason & GEN_INTR_RXTRAFFIC)
4251 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4252
db874e65
SS		 4253 for (i = 0; i < config->rx_ring_num; i++) {
4254 rx_intr_handler(&mac_control->rings[i]);
1da177e4
LT		 4255 }
4256 }
1da177e4 4257
863c11a9
AR		 4258 /*
4259 * tx_traffic_int reg is an R1 register, writing all 1's
4260 * will ensure that the actual interrupt causing bit get's
4261 * cleared and hence a read can be avoided.
4262 */
19a60522
SS		 4263 if (reason & GEN_INTR_TXTRAFFIC)
4264 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
fe113638 4265
863c11a9
AR		 4266 for (i = 0; i < config->tx_fifo_num; i++)
4267 tx_intr_handler(&mac_control->fifos[i]);
20346722 4268
a371a07d
K		 4269 if (reason & GEN_INTR_TXPIC)
4270 s2io_txpic_intr_handle(sp);
20346722
K		 4271 /*
4272 * If the Rx buffer count is below the panic threshold then
4273 * reallocate the buffers from the interrupt handler itself,
1da177e4
LT		 4274 * else schedule a tasklet to reallocate the buffers.
4275 */
db874e65
SS		 4276 if (!napi) {
4277 for (i = 0; i < config->rx_ring_num; i++)
4278 s2io_chk_rx_buffers(sp, i);
4279 }
4280
4281 writeq(0, &bar0->general_int_mask);
4282 readl(&bar0->general_int_status);
4283
7ba013ac 4284 atomic_dec(&sp->isr_cnt);
1da177e4
LT		 4285 return IRQ_HANDLED;
4286}
4287
7ba013ac
K		 4288/**
4289 * s2io_updt_stats -
4290 */
1ee6dd77 4291static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4292{
1ee6dd77 4293 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4294 u64 val64;
4295 int cnt = 0;
4296
4297 if (atomic_read(&sp->card_state) == CARD_UP) {
4298 /* Apprx 30us on a 133 MHz bus */
4299 val64 = SET_UPDT_CLICKS(10) |
4300 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4301 writeq(val64, &bar0->stat_cfg);
4302 do {
4303 udelay(100);
4304 val64 = readq(&bar0->stat_cfg);
4305 if (!(val64 & BIT(0)))
4306 break;
4307 cnt++;
4308 if (cnt == 5)
4309 break; /* Updt failed */
4310 } while(1);
363dc367 4311 }
7ba013ac
K		 4312}
4313
1da177e4 4314/**
20346722 4315 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4316 * @dev : pointer to the device structure.
4317 * Description:
20346722 4318 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4319 * structure and returns a pointer to the same.
4320 * Return value:
4321 * pointer to the updated net_device_stats structure.
4322 */
4323
ac1f60db 4324static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4325{
1ee6dd77
RB		 4326 struct s2io_nic *sp = dev->priv;
4327 struct mac_info *mac_control;
1da177e4
LT		 4328 struct config_param *config;
4329
20346722 4330
1da177e4
LT		 4331 mac_control = &sp->mac_control;
4332 config = &sp->config;
4333
7ba013ac
K		 4334 /* Configure Stats for immediate updt */
4335 s2io_updt_stats(sp);
4336
4337 sp->stats.tx_packets =
4338 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722
K		 4339 sp->stats.tx_errors =
4340 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4341 sp->stats.rx_errors =
ee705dba 4342 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722
K		 4343 sp->stats.multicast =
4344 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4345 sp->stats.rx_length_errors =
ee705dba 4346 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4
LT		 4347
4348 return (&sp->stats);
4349}
4350
4351/**
4352 * s2io_set_multicast - entry point for multicast address enable/disable.
4353 * @dev : pointer to the device structure
4354 * Description:
20346722
K		 4355 * This function is a driver entry point which gets called by the kernel
4356 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4357 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4358 * determine, if multicast address must be enabled or if promiscuous mode
4359 * is to be disabled etc.
4360 * Return value:
4361 * void.
4362 */
4363
4364static void s2io_set_multicast(struct net_device *dev)
4365{
4366 int i, j, prev_cnt;
4367 struct dev_mc_list *mclist;
1ee6dd77
RB		 4368 struct s2io_nic *sp = dev->priv;
4369 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4370 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4371 0xfeffffffffffULL;
4372 u64 dis_addr = 0xffffffffffffULL, mac_addr = 0;
4373 void __iomem *add;
4374
4375 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4376 /* Enable all Multicast addresses */
4377 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4378 &bar0->rmac_addr_data0_mem);
4379 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4380 &bar0->rmac_addr_data1_mem);
4381 val64 = RMAC_ADDR_CMD_MEM_WE |
4382 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4383 RMAC_ADDR_CMD_MEM_OFFSET(MAC_MC_ALL_MC_ADDR_OFFSET);
4384 writeq(val64, &bar0->rmac_addr_cmd_mem);
4385 /* Wait till command completes */
c92ca04b 4386 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4387 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4388 S2IO_BIT_RESET);
1da177e4
LT		 4389
4390 sp->m_cast_flg = 1;
4391 sp->all_multi_pos = MAC_MC_ALL_MC_ADDR_OFFSET;
4392 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4393 /* Disable all Multicast addresses */
4394 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4395 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 4396 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4397 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4398 val64 = RMAC_ADDR_CMD_MEM_WE |
4399 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4400 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4401 writeq(val64, &bar0->rmac_addr_cmd_mem);
4402 /* Wait till command completes */
c92ca04b 4403 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4404 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4405 S2IO_BIT_RESET);
1da177e4
LT		 4406
4407 sp->m_cast_flg = 0;
4408 sp->all_multi_pos = 0;
4409 }
4410
4411 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4412 /* Put the NIC into promiscuous mode */
4413 add = &bar0->mac_cfg;
4414 val64 = readq(&bar0->mac_cfg);
4415 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4416
4417 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4418 writel((u32) val64, add);
4419 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4420 writel((u32) (val64 >> 32), (add + 4));
4421
926930b2
SS		 4422 if (vlan_tag_strip != 1) {
4423 val64 = readq(&bar0->rx_pa_cfg);
4424 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4425 writeq(val64, &bar0->rx_pa_cfg);
4426 vlan_strip_flag = 0;
4427 }
4428
1da177e4
LT		 4429 val64 = readq(&bar0->mac_cfg);
4430 sp->promisc_flg = 1;
776bd20f 4431 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 4432 dev->name);
4433 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4434 /* Remove the NIC from promiscuous mode */
4435 add = &bar0->mac_cfg;
4436 val64 = readq(&bar0->mac_cfg);
4437 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4438
4439 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4440 writel((u32) val64, add);
4441 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4442 writel((u32) (val64 >> 32), (add + 4));
4443
926930b2
SS		 4444 if (vlan_tag_strip != 0) {
4445 val64 = readq(&bar0->rx_pa_cfg);
4446 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4447 writeq(val64, &bar0->rx_pa_cfg);
4448 vlan_strip_flag = 1;
4449 }
4450
1da177e4
LT		 4451 val64 = readq(&bar0->mac_cfg);
4452 sp->promisc_flg = 0;
776bd20f 4453 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 4454 dev->name);
4455 }
4456
4457 /* Update individual M_CAST address list */
4458 if ((!sp->m_cast_flg) && dev->mc_count) {
4459 if (dev->mc_count >
4460 (MAX_ADDRS_SUPPORTED - MAC_MC_ADDR_START_OFFSET - 1)) {
4461 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4462 dev->name);
4463 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4464 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4465 return;
4466 }
4467
4468 prev_cnt = sp->mc_addr_count;
4469 sp->mc_addr_count = dev->mc_count;
4470
4471 /* Clear out the previous list of Mc in the H/W. */
4472 for (i = 0; i < prev_cnt; i++) {
4473 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4474 &bar0->rmac_addr_data0_mem);
4475 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4476 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4477 val64 = RMAC_ADDR_CMD_MEM_WE |
4478 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4479 RMAC_ADDR_CMD_MEM_OFFSET
4480 (MAC_MC_ADDR_START_OFFSET + i);
4481 writeq(val64, &bar0->rmac_addr_cmd_mem);
4482
4483 /* Wait for command completes */
c92ca04b 4484 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4485 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4486 S2IO_BIT_RESET)) {
1da177e4
LT		 4487 DBG_PRINT(ERR_DBG, "%s: Adding ",
4488 dev->name);
4489 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4490 return;
4491 }
4492 }
4493
4494 /* Create the new Rx filter list and update the same in H/W. */
4495 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4496 i++, mclist = mclist->next) {
4497 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4498 ETH_ALEN);
a7a80d5a 4499 mac_addr = 0;
1da177e4
LT		 4500 for (j = 0; j < ETH_ALEN; j++) {
4501 mac_addr |= mclist->dmi_addr[j];
4502 mac_addr <<= 8;
4503 }
4504 mac_addr >>= 8;
4505 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4506 &bar0->rmac_addr_data0_mem);
4507 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4508 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4509 val64 = RMAC_ADDR_CMD_MEM_WE |
4510 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4511 RMAC_ADDR_CMD_MEM_OFFSET
4512 (i + MAC_MC_ADDR_START_OFFSET);
4513 writeq(val64, &bar0->rmac_addr_cmd_mem);
4514
4515 /* Wait for command completes */
c92ca04b 4516 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4517 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4518 S2IO_BIT_RESET)) {
1da177e4
LT		 4519 DBG_PRINT(ERR_DBG, "%s: Adding ",
4520 dev->name);
4521 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4522 return;
4523 }
4524 }
4525 }
4526}
4527
4528/**
20346722 4529 * s2io_set_mac_addr - Programs the Xframe mac address
1da177e4
LT		 4530 * @dev : pointer to the device structure.
4531 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 4532 * Description : This procedure will program the Xframe to receive
1da177e4 4533 * frames with new Mac Address
20346722 4534 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 4535 * as defined in errno.h file on failure.
4536 */
4537
26df54bf 4538static int s2io_set_mac_addr(struct net_device *dev, u8 * addr)
1da177e4 4539{
1ee6dd77
RB		 4540 struct s2io_nic *sp = dev->priv;
4541 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4542 register u64 val64, mac_addr = 0;
4543 int i;
d8d70caf 4544 u64 old_mac_addr = 0;
1da177e4 4545
20346722 4546 /*
1da177e4
LT		 4547 * Set the new MAC address as the new unicast filter and reflect this
4548 * change on the device address registered with the OS. It will be
20346722 4549 * at offset 0.
1da177e4
LT		 4550 */
4551 for (i = 0; i < ETH_ALEN; i++) {
4552 mac_addr <<= 8;
4553 mac_addr |= addr[i];
d8d70caf
SS		 4554 old_mac_addr <<= 8;
4555 old_mac_addr |= sp->def_mac_addr[0].mac_addr[i];
4556 }
4557
4558 if(0 == mac_addr)
4559 return SUCCESS;
4560
4561 /* Update the internal structure with this new mac address */
4562 if(mac_addr != old_mac_addr) {
4563 memset(sp->def_mac_addr[0].mac_addr, 0, sizeof(ETH_ALEN));
4564 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_addr);
4565 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_addr >> 8);
4566 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_addr >> 16);
4567 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_addr >> 24);
4568 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_addr >> 32);
4569 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_addr >> 40);
1da177e4
LT		 4570 }
4571
4572 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4573 &bar0->rmac_addr_data0_mem);
4574
4575 val64 =
4576 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4577 RMAC_ADDR_CMD_MEM_OFFSET(0);
4578 writeq(val64, &bar0->rmac_addr_cmd_mem);
4579 /* Wait till command completes */
c92ca04b 4580 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 4581 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET)) {
1da177e4
LT		 4582 DBG_PRINT(ERR_DBG, "%s: set_mac_addr failed\n", dev->name);
4583 return FAILURE;
4584 }
4585
4586 return SUCCESS;
4587}
4588
4589/**
20346722 4590 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 4591 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
4592 * @info: pointer to the structure with parameters given by ethtool to set
4593 * link information.
4594 * Description:
20346722 4595 * The function sets different link parameters provided by the user onto
1da177e4
LT		 4596 * the NIC.
4597 * Return value:
4598 * 0 on success.
4599*/
4600
4601static int s2io_ethtool_sset(struct net_device *dev,
4602 struct ethtool_cmd *info)
4603{
1ee6dd77 4604 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4605 if ((info->autoneg == AUTONEG_ENABLE) ||
4606 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
4607 return -EINVAL;
4608 else {
4609 s2io_close(sp->dev);
4610 s2io_open(sp->dev);
4611 }
4612
4613 return 0;
4614}
4615
4616/**
20346722 4617 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 4618 * @sp : private member of the device structure, pointer to the
4619 * s2io_nic structure.
4620 * @info : pointer to the structure with parameters given by ethtool
4621 * to return link information.
4622 * Description:
4623 * Returns link specific information like speed, duplex etc.. to ethtool.
4624 * Return value :
4625 * return 0 on success.
4626 */
4627
4628static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
4629{
1ee6dd77 4630 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4631 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4632 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
4633 info->port = PORT_FIBRE;
4634 /* info->transceiver?? TODO */
4635
4636 if (netif_carrier_ok(sp->dev)) {
4637 info->speed = 10000;
4638 info->duplex = DUPLEX_FULL;
4639 } else {
4640 info->speed = -1;
4641 info->duplex = -1;
4642 }
4643
4644 info->autoneg = AUTONEG_DISABLE;
4645 return 0;
4646}
4647
4648/**
20346722
K		 4649 * s2io_ethtool_gdrvinfo - Returns driver specific information.
4650 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4651 * s2io_nic structure.
4652 * @info : pointer to the structure with parameters given by ethtool to
4653 * return driver information.
4654 * Description:
4655 * Returns driver specefic information like name, version etc.. to ethtool.
4656 * Return value:
4657 * void
4658 */
4659
4660static void s2io_ethtool_gdrvinfo(struct net_device *dev,
4661 struct ethtool_drvinfo *info)
4662{
1ee6dd77 4663 struct s2io_nic *sp = dev->priv;
1da177e4 4664
dbc2309d
JL		 4665 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
4666 strncpy(info->version, s2io_driver_version, sizeof(info->version));
4667 strncpy(info->fw_version, "", sizeof(info->fw_version));
4668 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 4669 info->regdump_len = XENA_REG_SPACE;
4670 info->eedump_len = XENA_EEPROM_SPACE;
4671 info->testinfo_len = S2IO_TEST_LEN;
fa1f0cb3
SS		 4672
4673 if (sp->device_type == XFRAME_I_DEVICE)
4674 info->n_stats = XFRAME_I_STAT_LEN;
4675 else
4676 info->n_stats = XFRAME_II_STAT_LEN;
1da177e4
LT		 4677}
4678
4679/**
4680 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 4681 * @sp: private member of the device structure, which is a pointer to the
1da177e4 4682 * s2io_nic structure.
20346722 4683 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 4684 * dumping the registers.
4685 * @reg_space: The input argumnet into which all the registers are dumped.
4686 * Description:
4687 * Dumps the entire register space of xFrame NIC into the user given
4688 * buffer area.
4689 * Return value :
4690 * void .
4691*/
4692
4693static void s2io_ethtool_gregs(struct net_device *dev,
4694 struct ethtool_regs *regs, void *space)
4695{
4696 int i;
4697 u64 reg;
4698 u8 *reg_space = (u8 *) space;
1ee6dd77 4699 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4700
4701 regs->len = XENA_REG_SPACE;
4702 regs->version = sp->pdev->subsystem_device;
4703
4704 for (i = 0; i < regs->len; i += 8) {
4705 reg = readq(sp->bar0 + i);
4706 memcpy((reg_space + i), &reg, 8);
4707 }
4708}
4709
4710/**
4711 * s2io_phy_id - timer function that alternates adapter LED.
20346722 4712 * @data : address of the private member of the device structure, which
1da177e4 4713 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 4714 * Description: This is actually the timer function that alternates the
4715 * adapter LED bit of the adapter control bit to set/reset every time on
4716 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 4717 * once every second.
4718*/
4719static void s2io_phy_id(unsigned long data)
4720{
1ee6dd77
RB		 4721 struct s2io_nic *sp = (struct s2io_nic *) data;
4722 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4723 u64 val64 = 0;
4724 u16 subid;
4725
4726 subid = sp->pdev->subsystem_device;
541ae68f
K		 4727 if ((sp->device_type == XFRAME_II_DEVICE) ||
4728 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 4729 val64 = readq(&bar0->gpio_control);
4730 val64 ^= GPIO_CTRL_GPIO_0;
4731 writeq(val64, &bar0->gpio_control);
4732 } else {
4733 val64 = readq(&bar0->adapter_control);
4734 val64 ^= ADAPTER_LED_ON;
4735 writeq(val64, &bar0->adapter_control);
4736 }
4737
4738 mod_timer(&sp->id_timer, jiffies + HZ / 2);
4739}
4740
4741/**
4742 * s2io_ethtool_idnic - To physically identify the nic on the system.
4743 * @sp : private member of the device structure, which is a pointer to the
4744 * s2io_nic structure.
20346722 4745 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 4746 * ethtool.
4747 * Description: Used to physically identify the NIC on the system.
20346722 4748 * The Link LED will blink for a time specified by the user for
1da177e4 4749 * identification.
20346722 4750 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 4751 * identification is possible only if it's link is up.
4752 * Return value:
4753 * int , returns 0 on success
4754 */
4755
4756static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
4757{
4758 u64 val64 = 0, last_gpio_ctrl_val;
1ee6dd77
RB		 4759 struct s2io_nic *sp = dev->priv;
4760 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4761 u16 subid;
4762
4763 subid = sp->pdev->subsystem_device;
4764 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f
K		 4765 if ((sp->device_type == XFRAME_I_DEVICE) &&
4766 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 4767 val64 = readq(&bar0->adapter_control);
4768 if (!(val64 & ADAPTER_CNTL_EN)) {
4769 printk(KERN_ERR
4770 "Adapter Link down, cannot blink LED\n");
4771 return -EFAULT;
4772 }
4773 }
4774 if (sp->id_timer.function == NULL) {
4775 init_timer(&sp->id_timer);
4776 sp->id_timer.function = s2io_phy_id;
4777 sp->id_timer.data = (unsigned long) sp;
4778 }
4779 mod_timer(&sp->id_timer, jiffies);
4780 if (data)
20346722 4781 msleep_interruptible(data * HZ);
1da177e4 4782 else
20346722 4783 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 4784 del_timer_sync(&sp->id_timer);
4785
541ae68f 4786 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 4787 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
4788 last_gpio_ctrl_val = readq(&bar0->gpio_control);
4789 }
4790
4791 return 0;
4792}
4793
0cec35eb
SH		 4794static void s2io_ethtool_gringparam(struct net_device *dev,
4795 struct ethtool_ringparam *ering)
4796{
4797 struct s2io_nic *sp = dev->priv;
4798 int i,tx_desc_count=0,rx_desc_count=0;
4799
4800 if (sp->rxd_mode == RXD_MODE_1)
4801 ering->rx_max_pending = MAX_RX_DESC_1;
4802 else if (sp->rxd_mode == RXD_MODE_3B)
4803 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 4804
4805 ering->tx_max_pending = MAX_TX_DESC;
b6627672 4806 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 4807 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
b6627672 4808
0cec35eb
SH		 4809 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
4810 ering->tx_pending = tx_desc_count;
4811 rx_desc_count = 0;
b6627672 4812 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 4813 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 4814
0cec35eb
SH		 4815 ering->rx_pending = rx_desc_count;
4816
4817 ering->rx_mini_max_pending = 0;
4818 ering->rx_mini_pending = 0;
4819 if(sp->rxd_mode == RXD_MODE_1)
4820 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
4821 else if (sp->rxd_mode == RXD_MODE_3B)
4822 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
4823 ering->rx_jumbo_pending = rx_desc_count;
4824}
4825
1da177e4
LT		 4826/**
4827 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 4828 * @sp : private member of the device structure, which is a pointer to the
4829 * s2io_nic structure.
1da177e4
LT		 4830 * @ep : pointer to the structure with pause parameters given by ethtool.
4831 * Description:
4832 * Returns the Pause frame generation and reception capability of the NIC.
4833 * Return value:
4834 * void
4835 */
4836static void s2io_ethtool_getpause_data(struct net_device *dev,
4837 struct ethtool_pauseparam *ep)
4838{
4839 u64 val64;
1ee6dd77
RB		 4840 struct s2io_nic *sp = dev->priv;
4841 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4842
4843 val64 = readq(&bar0->rmac_pause_cfg);
4844 if (val64 & RMAC_PAUSE_GEN_ENABLE)
4845 ep->tx_pause = TRUE;
4846 if (val64 & RMAC_PAUSE_RX_ENABLE)
4847 ep->rx_pause = TRUE;
4848 ep->autoneg = FALSE;
4849}
4850
4851/**
4852 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 4853 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4854 * s2io_nic structure.
4855 * @ep : pointer to the structure with pause parameters given by ethtool.
4856 * Description:
4857 * It can be used to set or reset Pause frame generation or reception
4858 * support of the NIC.
4859 * Return value:
4860 * int, returns 0 on Success
4861 */
4862
4863static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 4864 struct ethtool_pauseparam *ep)
1da177e4
LT		 4865{
4866 u64 val64;
1ee6dd77
RB		 4867 struct s2io_nic *sp = dev->priv;
4868 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4869
4870 val64 = readq(&bar0->rmac_pause_cfg);
4871 if (ep->tx_pause)
4872 val64 |= RMAC_PAUSE_GEN_ENABLE;
4873 else
4874 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
4875 if (ep->rx_pause)
4876 val64 |= RMAC_PAUSE_RX_ENABLE;
4877 else
4878 val64 &= ~RMAC_PAUSE_RX_ENABLE;
4879 writeq(val64, &bar0->rmac_pause_cfg);
4880 return 0;
4881}
4882
4883/**
4884 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 4885 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 4886 * s2io_nic structure.
4887 * @off : offset at which the data must be written
4888 * @data : Its an output parameter where the data read at the given
20346722 4889 * offset is stored.
1da177e4 4890 * Description:
20346722 4891 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 4892 * read data.
4893 * NOTE: Will allow to read only part of the EEPROM visible through the
4894 * I2C bus.
4895 * Return value:
4896 * -1 on failure and 0 on success.
4897 */
4898
4899#define S2IO_DEV_ID 5
1ee6dd77 4900static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 4901{
4902 int ret = -1;
4903 u32 exit_cnt = 0;
4904 u64 val64;
1ee6dd77 4905 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4906
ad4ebed0 4907 if (sp->device_type == XFRAME_I_DEVICE) {
4908 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4909 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
4910 I2C_CONTROL_CNTL_START;
4911 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 4912
ad4ebed0 4913 while (exit_cnt < 5) {
4914 val64 = readq(&bar0->i2c_control);
4915 if (I2C_CONTROL_CNTL_END(val64)) {
4916 *data = I2C_CONTROL_GET_DATA(val64);
4917 ret = 0;
4918 break;
4919 }
4920 msleep(50);
4921 exit_cnt++;
1da177e4 4922 }
1da177e4
LT		 4923 }
4924
ad4ebed0 4925 if (sp->device_type == XFRAME_II_DEVICE) {
4926 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 4927 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 4928 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
4929 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4930 val64 |= SPI_CONTROL_REQ;
4931 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4932 while (exit_cnt < 5) {
4933 val64 = readq(&bar0->spi_control);
4934 if (val64 & SPI_CONTROL_NACK) {
4935 ret = 1;
4936 break;
4937 } else if (val64 & SPI_CONTROL_DONE) {
4938 *data = readq(&bar0->spi_data);
4939 *data &= 0xffffff;
4940 ret = 0;
4941 break;
4942 }
4943 msleep(50);
4944 exit_cnt++;
4945 }
4946 }
1da177e4
LT		 4947 return ret;
4948}
4949
4950/**
4951 * write_eeprom - actually writes the relevant part of the data value.
4952 * @sp : private member of the device structure, which is a pointer to the
4953 * s2io_nic structure.
4954 * @off : offset at which the data must be written
4955 * @data : The data that is to be written
20346722 4956 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 4957 * the Eeprom. (max of 3)
4958 * Description:
4959 * Actually writes the relevant part of the data value into the Eeprom
4960 * through the I2C bus.
4961 * Return value:
4962 * 0 on success, -1 on failure.
4963 */
4964
1ee6dd77 4965static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 4966{
4967 int exit_cnt = 0, ret = -1;
4968 u64 val64;
1ee6dd77 4969 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 4970
ad4ebed0 4971 if (sp->device_type == XFRAME_I_DEVICE) {
4972 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
4973 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
4974 I2C_CONTROL_CNTL_START;
4975 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
4976
4977 while (exit_cnt < 5) {
4978 val64 = readq(&bar0->i2c_control);
4979 if (I2C_CONTROL_CNTL_END(val64)) {
4980 if (!(val64 & I2C_CONTROL_NACK))
4981 ret = 0;
4982 break;
4983 }
4984 msleep(50);
4985 exit_cnt++;
4986 }
4987 }
1da177e4 4988
ad4ebed0 4989 if (sp->device_type == XFRAME_II_DEVICE) {
4990 int write_cnt = (cnt == 8) ? 0 : cnt;
4991 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
4992
4993 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 4994 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 4995 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
4996 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4997 val64 |= SPI_CONTROL_REQ;
4998 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
4999 while (exit_cnt < 5) {
5000 val64 = readq(&bar0->spi_control);
5001 if (val64 & SPI_CONTROL_NACK) {
5002 ret = 1;
5003 break;
5004 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5005 ret = 0;
ad4ebed0 5006 break;
5007 }
5008 msleep(50);
5009 exit_cnt++;
1da177e4 5010 }
1da177e4 5011 }
1da177e4
LT		 5012 return ret;
5013}
1ee6dd77 5014static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5015{
b41477f3
AR		 5016 u8 *vpd_data;
5017 u8 data;
9dc737a7
AR		 5018 int i=0, cnt, fail = 0;
5019 int vpd_addr = 0x80;
5020
5021 if (nic->device_type == XFRAME_II_DEVICE) {
5022 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5023 vpd_addr = 0x80;
5024 }
5025 else {
5026 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5027 vpd_addr = 0x50;
5028 }
19a60522 5029 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5030
b41477f3 5031 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5032 if (!vpd_data) {
5033 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5034 return;
c53d4945 5035 }
491976b2 5036 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5037
9dc737a7
AR		 5038 for (i = 0; i < 256; i +=4 ) {
5039 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5040 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5041 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5042 for (cnt = 0; cnt <5; cnt++) {
5043 msleep(2);
5044 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5045 if (data == 0x80)
5046 break;
5047 }
5048 if (cnt >= 5) {
5049 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5050 fail = 1;
5051 break;
5052 }
5053 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5054 (u32 *)&vpd_data[i]);
5055 }
19a60522
SS		 5056
5057 if(!fail) {
5058 /* read serial number of adapter */
5059 for (cnt = 0; cnt < 256; cnt++) {
5060 if ((vpd_data[cnt] == 'S') &&
5061 (vpd_data[cnt+1] == 'N') &&
5062 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5063 memset(nic->serial_num, 0, VPD_STRING_LEN);
5064 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5065 vpd_data[cnt+2]);
5066 break;
5067 }
5068 }
5069 }
5070
5071 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5072 memset(nic->product_name, 0, vpd_data[1]);
5073 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5074 }
b41477f3 5075 kfree(vpd_data);
491976b2 5076 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5077}
5078
1da177e4
LT		 5079/**
5080 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5081 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5082 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5083 * containing all relevant information.
5084 * @data_buf : user defined value to be written into Eeprom.
5085 * Description: Reads the values stored in the Eeprom at given offset
5086 * for a given length. Stores these values int the input argument data
5087 * buffer 'data_buf' and returns these to the caller (ethtool.)
5088 * Return value:
5089 * int 0 on success
5090 */
5091
5092static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5093 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5094{
ad4ebed0 5095 u32 i, valid;
5096 u64 data;
1ee6dd77 5097 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5098
5099 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5100
5101 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5102 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5103
5104 for (i = 0; i < eeprom->len; i += 4) {
5105 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5106 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5107 return -EFAULT;
5108 }
5109 valid = INV(data);
5110 memcpy((data_buf + i), &valid, 4);
5111 }
5112 return 0;
5113}
5114
5115/**
5116 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5117 * @sp : private member of the device structure, which is a pointer to the
5118 * s2io_nic structure.
20346722 5119 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5120 * containing all relevant information.
5121 * @data_buf ; user defined value to be written into Eeprom.
5122 * Description:
5123 * Tries to write the user provided value in the Eeprom, at the offset
5124 * given by the user.
5125 * Return value:
5126 * 0 on success, -EFAULT on failure.
5127 */
5128
5129static int s2io_ethtool_seeprom(struct net_device *dev,
5130 struct ethtool_eeprom *eeprom,
5131 u8 * data_buf)
5132{
5133 int len = eeprom->len, cnt = 0;
ad4ebed0 5134 u64 valid = 0, data;
1ee6dd77 5135 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5136
5137 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5138 DBG_PRINT(ERR_DBG,
5139 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5140 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5141 eeprom->magic);
5142 return -EFAULT;
5143 }
5144
5145 while (len) {
5146 data = (u32) data_buf[cnt] & 0x000000FF;
5147 if (data) {
5148 valid = (u32) (data << 24);
5149 } else
5150 valid = data;
5151
5152 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5153 DBG_PRINT(ERR_DBG,
5154 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5155 DBG_PRINT(ERR_DBG,
5156 "write into the specified offset\n");
5157 return -EFAULT;
5158 }
5159 cnt++;
5160 len--;
5161 }
5162
5163 return 0;
5164}
5165
5166/**
20346722
K		 5167 * s2io_register_test - reads and writes into all clock domains.
5168 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5169 * s2io_nic structure.
5170 * @data : variable that returns the result of each of the test conducted b
5171 * by the driver.
5172 * Description:
5173 * Read and write into all clock domains. The NIC has 3 clock domains,
5174 * see that registers in all the three regions are accessible.
5175 * Return value:
5176 * 0 on success.
5177 */
5178
1ee6dd77 5179static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5180{
1ee6dd77 5181 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5182 u64 val64 = 0, exp_val;
1da177e4
LT		 5183 int fail = 0;
5184
20346722
K		 5185 val64 = readq(&bar0->pif_rd_swapper_fb);
5186 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5187 fail = 1;
5188 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5189 }
5190
5191 val64 = readq(&bar0->rmac_pause_cfg);
5192 if (val64 != 0xc000ffff00000000ULL) {
5193 fail = 1;
5194 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5195 }
5196
5197 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5198 if (sp->device_type == XFRAME_II_DEVICE)
5199 exp_val = 0x0404040404040404ULL;
5200 else
5201 exp_val = 0x0808080808080808ULL;
5202 if (val64 != exp_val) {
1da177e4
LT		 5203 fail = 1;
5204 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5205 }
5206
5207 val64 = readq(&bar0->xgxs_efifo_cfg);
5208 if (val64 != 0x000000001923141EULL) {
5209 fail = 1;
5210 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5211 }
5212
5213 val64 = 0x5A5A5A5A5A5A5A5AULL;
5214 writeq(val64, &bar0->xmsi_data);
5215 val64 = readq(&bar0->xmsi_data);
5216 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5217 fail = 1;
5218 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5219 }
5220
5221 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5222 writeq(val64, &bar0->xmsi_data);
5223 val64 = readq(&bar0->xmsi_data);
5224 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5225 fail = 1;
5226 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5227 }
5228
5229 *data = fail;
ad4ebed0 5230 return fail;
1da177e4
LT		 5231}
5232
5233/**
20346722 5234 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5235 * @sp : private member of the device structure, which is a pointer to the
5236 * s2io_nic structure.
5237 * @data:variable that returns the result of each of the test conducted by
5238 * the driver.
5239 * Description:
20346722 5240 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5241 * register.
5242 * Return value:
5243 * 0 on success.
5244 */
5245
1ee6dd77 5246static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5247{
5248 int fail = 0;
ad4ebed0 5249 u64 ret_data, org_4F0, org_7F0;
5250 u8 saved_4F0 = 0, saved_7F0 = 0;
5251 struct net_device *dev = sp->dev;
1da177e4
LT		 5252
5253 /* Test Write Error at offset 0 */
ad4ebed0 5254 /* Note that SPI interface allows write access to all areas
5255 * of EEPROM. Hence doing all negative testing only for Xframe I.
5256 */
5257 if (sp->device_type == XFRAME_I_DEVICE)
5258 if (!write_eeprom(sp, 0, 0, 3))
5259 fail = 1;
5260
5261 /* Save current values at offsets 0x4F0 and 0x7F0 */
5262 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5263 saved_4F0 = 1;
5264 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5265 saved_7F0 = 1;
1da177e4
LT		 5266
5267 /* Test Write at offset 4f0 */
ad4ebed0 5268 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5269 fail = 1;
5270 if (read_eeprom(sp, 0x4F0, &ret_data))
5271 fail = 1;
5272
ad4ebed0 5273 if (ret_data != 0x012345) {
26b7625c
AM		 5274 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5275 "Data written %llx Data read %llx\n",
5276 dev->name, (unsigned long long)0x12345,
5277 (unsigned long long)ret_data);
1da177e4 5278 fail = 1;
ad4ebed0 5279 }
1da177e4
LT		 5280
5281 /* Reset the EEPROM data go FFFF */
ad4ebed0 5282 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 5283
5284 /* Test Write Request Error at offset 0x7c */
ad4ebed0 5285 if (sp->device_type == XFRAME_I_DEVICE)
5286 if (!write_eeprom(sp, 0x07C, 0, 3))
5287 fail = 1;
1da177e4 5288
ad4ebed0 5289 /* Test Write Request at offset 0x7f0 */
5290 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 5291 fail = 1;
ad4ebed0 5292 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 5293 fail = 1;
5294
ad4ebed0 5295 if (ret_data != 0x012345) {
26b7625c
AM		 5296 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5297 "Data written %llx Data read %llx\n",
5298 dev->name, (unsigned long long)0x12345,
5299 (unsigned long long)ret_data);
1da177e4 5300 fail = 1;
ad4ebed0 5301 }
1da177e4
LT		 5302
5303 /* Reset the EEPROM data go FFFF */
ad4ebed0 5304 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 5305
ad4ebed0 5306 if (sp->device_type == XFRAME_I_DEVICE) {
5307 /* Test Write Error at offset 0x80 */
5308 if (!write_eeprom(sp, 0x080, 0, 3))
5309 fail = 1;
1da177e4 5310
ad4ebed0 5311 /* Test Write Error at offset 0xfc */
5312 if (!write_eeprom(sp, 0x0FC, 0, 3))
5313 fail = 1;
1da177e4 5314
ad4ebed0 5315 /* Test Write Error at offset 0x100 */
5316 if (!write_eeprom(sp, 0x100, 0, 3))
5317 fail = 1;
1da177e4 5318
ad4ebed0 5319 /* Test Write Error at offset 4ec */
5320 if (!write_eeprom(sp, 0x4EC, 0, 3))
5321 fail = 1;
5322 }
5323
5324 /* Restore values at offsets 0x4F0 and 0x7F0 */
5325 if (saved_4F0)
5326 write_eeprom(sp, 0x4F0, org_4F0, 3);
5327 if (saved_7F0)
5328 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 5329
5330 *data = fail;
ad4ebed0 5331 return fail;
1da177e4
LT		 5332}
5333
5334/**
5335 * s2io_bist_test - invokes the MemBist test of the card .
20346722 5336 * @sp : private member of the device structure, which is a pointer to the
1da177e4 5337 * s2io_nic structure.
20346722 5338 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 5339 * the driver.
5340 * Description:
5341 * This invokes the MemBist test of the card. We give around
5342 * 2 secs time for the Test to complete. If it's still not complete
20346722 5343 * within this peiod, we consider that the test failed.
1da177e4
LT		 5344 * Return value:
5345 * 0 on success and -1 on failure.
5346 */
5347
1ee6dd77 5348static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5349{
5350 u8 bist = 0;
5351 int cnt = 0, ret = -1;
5352
5353 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5354 bist |= PCI_BIST_START;
5355 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5356
5357 while (cnt < 20) {
5358 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5359 if (!(bist & PCI_BIST_START)) {
5360 *data = (bist & PCI_BIST_CODE_MASK);
5361 ret = 0;
5362 break;
5363 }
5364 msleep(100);
5365 cnt++;
5366 }
5367
5368 return ret;
5369}
5370
5371/**
20346722
K		 5372 * s2io-link_test - verifies the link state of the nic
5373 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 5374 * s2io_nic structure.
5375 * @data: variable that returns the result of each of the test conducted by
5376 * the driver.
5377 * Description:
20346722 5378 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 5379 * argument 'data' appropriately.
5380 * Return value:
5381 * 0 on success.
5382 */
5383
1ee6dd77 5384static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5385{
1ee6dd77 5386 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5387 u64 val64;
5388
5389 val64 = readq(&bar0->adapter_status);
c92ca04b 5390 if(!(LINK_IS_UP(val64)))
1da177e4 5391 *data = 1;
c92ca04b
AR		 5392 else
5393 *data = 0;
1da177e4 5394
b41477f3 5395 return *data;
1da177e4
LT		 5396}
5397
5398/**
20346722
K		 5399 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5400 * @sp - private member of the device structure, which is a pointer to the
1da177e4 5401 * s2io_nic structure.
20346722 5402 * @data - variable that returns the result of each of the test
1da177e4
LT		 5403 * conducted by the driver.
5404 * Description:
20346722 5405 * This is one of the offline test that tests the read and write
1da177e4
LT		 5406 * access to the RldRam chip on the NIC.
5407 * Return value:
5408 * 0 on success.
5409 */
5410
1ee6dd77 5411static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5412{
1ee6dd77 5413 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5414 u64 val64;
ad4ebed0 5415 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 5416
5417 val64 = readq(&bar0->adapter_control);
5418 val64 &= ~ADAPTER_ECC_EN;
5419 writeq(val64, &bar0->adapter_control);
5420
5421 val64 = readq(&bar0->mc_rldram_test_ctrl);
5422 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 5423 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5424
5425 val64 = readq(&bar0->mc_rldram_mrs);
5426 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5427 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5428
5429 val64 |= MC_RLDRAM_MRS_ENABLE;
5430 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5431
5432 while (iteration < 2) {
5433 val64 = 0x55555555aaaa0000ULL;
5434 if (iteration == 1) {
5435 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5436 }
5437 writeq(val64, &bar0->mc_rldram_test_d0);
5438
5439 val64 = 0xaaaa5a5555550000ULL;
5440 if (iteration == 1) {
5441 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5442 }
5443 writeq(val64, &bar0->mc_rldram_test_d1);
5444
5445 val64 = 0x55aaaaaaaa5a0000ULL;
5446 if (iteration == 1) {
5447 val64 ^= 0xFFFFFFFFFFFF0000ULL;
5448 }
5449 writeq(val64, &bar0->mc_rldram_test_d2);
5450
ad4ebed0 5451 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 5452 writeq(val64, &bar0->mc_rldram_test_add);
5453
ad4ebed0 5454 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
5455 MC_RLDRAM_TEST_GO;
5456 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5457
5458 for (cnt = 0; cnt < 5; cnt++) {
5459 val64 = readq(&bar0->mc_rldram_test_ctrl);
5460 if (val64 & MC_RLDRAM_TEST_DONE)
5461 break;
5462 msleep(200);
5463 }
5464
5465 if (cnt == 5)
5466 break;
5467
ad4ebed0 5468 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
5469 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5470
5471 for (cnt = 0; cnt < 5; cnt++) {
5472 val64 = readq(&bar0->mc_rldram_test_ctrl);
5473 if (val64 & MC_RLDRAM_TEST_DONE)
5474 break;
5475 msleep(500);
5476 }
5477
5478 if (cnt == 5)
5479 break;
5480
5481 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 5482 if (!(val64 & MC_RLDRAM_TEST_PASS))
5483 test_fail = 1;
1da177e4
LT		 5484
5485 iteration++;
5486 }
5487
ad4ebed0 5488 *data = test_fail;
1da177e4 5489
ad4ebed0 5490 /* Bring the adapter out of test mode */
5491 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
5492
5493 return test_fail;
1da177e4
LT		 5494}
5495
5496/**
5497 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
5498 * @sp : private member of the device structure, which is a pointer to the
5499 * s2io_nic structure.
5500 * @ethtest : pointer to a ethtool command specific structure that will be
5501 * returned to the user.
20346722 5502 * @data : variable that returns the result of each of the test
1da177e4
LT		 5503 * conducted by the driver.
5504 * Description:
5505 * This function conducts 6 tests ( 4 offline and 2 online) to determine
5506 * the health of the card.
5507 * Return value:
5508 * void
5509 */
5510
5511static void s2io_ethtool_test(struct net_device *dev,
5512 struct ethtool_test *ethtest,
5513 uint64_t * data)
5514{
1ee6dd77 5515 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5516 int orig_state = netif_running(sp->dev);
5517
5518 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
5519 /* Offline Tests. */
20346722 5520 if (orig_state)
1da177e4 5521 s2io_close(sp->dev);
1da177e4
LT		 5522
5523 if (s2io_register_test(sp, &data[0]))
5524 ethtest->flags |= ETH_TEST_FL_FAILED;
5525
5526 s2io_reset(sp);
1da177e4
LT		 5527
5528 if (s2io_rldram_test(sp, &data[3]))
5529 ethtest->flags |= ETH_TEST_FL_FAILED;
5530
5531 s2io_reset(sp);
1da177e4
LT		 5532
5533 if (s2io_eeprom_test(sp, &data[1]))
5534 ethtest->flags |= ETH_TEST_FL_FAILED;
5535
5536 if (s2io_bist_test(sp, &data[4]))
5537 ethtest->flags |= ETH_TEST_FL_FAILED;
5538
5539 if (orig_state)
5540 s2io_open(sp->dev);
5541
5542 data[2] = 0;
5543 } else {
5544 /* Online Tests. */
5545 if (!orig_state) {
5546 DBG_PRINT(ERR_DBG,
5547 "%s: is not up, cannot run test\n",
5548 dev->name);
5549 data[0] = -1;
5550 data[1] = -1;
5551 data[2] = -1;
5552 data[3] = -1;
5553 data[4] = -1;
5554 }
5555
5556 if (s2io_link_test(sp, &data[2]))
5557 ethtest->flags |= ETH_TEST_FL_FAILED;
5558
5559 data[0] = 0;
5560 data[1] = 0;
5561 data[3] = 0;
5562 data[4] = 0;
5563 }
5564}
5565
5566static void s2io_get_ethtool_stats(struct net_device *dev,
5567 struct ethtool_stats *estats,
5568 u64 * tmp_stats)
5569{
5570 int i = 0;
1ee6dd77
RB		 5571 struct s2io_nic *sp = dev->priv;
5572 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 5573
7ba013ac 5574 s2io_updt_stats(sp);
541ae68f
K		 5575 tmp_stats[i++] =
5576 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
5577 le32_to_cpu(stat_info->tmac_frms);
5578 tmp_stats[i++] =
5579 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
5580 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 5581 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f
K		 5582 tmp_stats[i++] =
5583 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
5584 le32_to_cpu(stat_info->tmac_mcst_frms);
5585 tmp_stats[i++] =
5586 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
5587 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 5588 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 5589 tmp_stats[i++] =
5590 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
5591 le32_to_cpu(stat_info->tmac_ttl_octets);
5592 tmp_stats[i++] =
5593 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
5594 le32_to_cpu(stat_info->tmac_ucst_frms);
5595 tmp_stats[i++] =
5596 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
5597 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f
K		 5598 tmp_stats[i++] =
5599 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
5600 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 5601 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 5602 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f
K		 5603 tmp_stats[i++] =
5604 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
5605 le32_to_cpu(stat_info->tmac_vld_ip);
5606 tmp_stats[i++] =
5607 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
5608 le32_to_cpu(stat_info->tmac_drop_ip);
5609 tmp_stats[i++] =
5610 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
5611 le32_to_cpu(stat_info->tmac_icmp);
5612 tmp_stats[i++] =
5613 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
5614 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 5615 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f
K		 5616 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
5617 le32_to_cpu(stat_info->tmac_udp);
5618 tmp_stats[i++] =
5619 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
5620 le32_to_cpu(stat_info->rmac_vld_frms);
5621 tmp_stats[i++] =
5622 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
5623 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 5624 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
5625 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f
K		 5626 tmp_stats[i++] =
5627 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
5628 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
5629 tmp_stats[i++] =
5630 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
5631 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 5632 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 5633 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 5634 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
5635 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 5636 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
5637 tmp_stats[i++] =
5638 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
5639 le32_to_cpu(stat_info->rmac_ttl_octets);
5640 tmp_stats[i++] =
5641 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
5642 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
5643 tmp_stats[i++] =
5644 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
5645 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f
K		 5646 tmp_stats[i++] =
5647 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
5648 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 5649 tmp_stats[i++] =
5650 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
5651 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
5652 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
5653 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f
K		 5654 tmp_stats[i++] =
5655 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
5656 le32_to_cpu(stat_info->rmac_usized_frms);
5657 tmp_stats[i++] =
5658 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
5659 le32_to_cpu(stat_info->rmac_osized_frms);
5660 tmp_stats[i++] =
5661 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
5662 le32_to_cpu(stat_info->rmac_frag_frms);
5663 tmp_stats[i++] =
5664 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
5665 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 5666 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
5667 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
5668 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
5669 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
5670 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
5671 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
5672 tmp_stats[i++] =
5673 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 5674 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 5675 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
5676 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 5677 tmp_stats[i++] =
5678 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 5679 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 5680 tmp_stats[i++] =
5681 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 5682 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 5683 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 5684 tmp_stats[i++] =
5685 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f
K		 5686 le32_to_cpu(stat_info->rmac_udp);
5687 tmp_stats[i++] =
5688 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
5689 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 5690 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
5691 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
5692 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
5693 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
5694 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
5695 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
5696 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
5697 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
5698 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
5699 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
5700 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
5701 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
5702 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
5703 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
5704 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
5705 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
5706 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f
K		 5707 tmp_stats[i++] =
5708 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
5709 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 5710 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
5711 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f
K		 5712 tmp_stats[i++] =
5713 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
5714 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 5715 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 5716 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
5717 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
5718 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
5719 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
5720 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
5721 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
5722 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
5723 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
5724 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
5725 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
5726 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
5727 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
5728 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
5729 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
5730 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
5731 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
5732 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
5733 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 5734
5735 /* Enhanced statistics exist only for Hercules */
5736 if(sp->device_type == XFRAME_II_DEVICE) {
5737 tmp_stats[i++] =
5738 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
5739 tmp_stats[i++] =
5740 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
5741 tmp_stats[i++] =
5742 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
5743 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
5744 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
5745 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
5746 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
5747 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
5748 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
5749 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
5750 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
5751 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
5752 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
5753 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
5754 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
5755 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
5756 }
5757
7ba013ac
K		 5758 tmp_stats[i++] = 0;
5759 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
5760 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 5761 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
5762 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
5763 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
5764 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
5765 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt;
5766 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
5767 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
5768 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
5769 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
5770 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
5771 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
5772 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
5773 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
5774 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
5775 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
5776 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
5777 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 5778 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
5779 tmp_stats[i++] = stat_info->sw_stat.sending_both;
5780 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
5781 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 5782 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 5783 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
5784 int count = 0;
6aa20a22 5785 /*
bd1034f0
AR		 5786 * Since 64-bit divide does not work on all platforms,
5787 * do repeated subtraction.
5788 */
5789 while (tmp >= stat_info->sw_stat.num_aggregations) {
5790 tmp -= stat_info->sw_stat.num_aggregations;
5791 count++;
5792 }
5793 tmp_stats[i++] = count;
fe931395 5794 }
bd1034f0
AR		 5795 else
5796 tmp_stats[i++] = 0;
c53d4945 5797 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
491abf25 5798 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
c53d4945 5799 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 5800 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
5801 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
5802 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
5803 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
5804 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
5805 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
5806
5807 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
5808 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
5809 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
5810 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
5811 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
5812
5813 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
5814 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
5815 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
5816 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
5817 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
5818 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
5819 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
5820 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
5821 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
1da177e4
LT		 5822}
5823
ac1f60db 5824static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 5825{
5826 return (XENA_REG_SPACE);
5827}
5828
5829
ac1f60db 5830static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 5831{
1ee6dd77 5832 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5833
5834 return (sp->rx_csum);
5835}
ac1f60db
AB		 5836
5837static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 5838{
1ee6dd77 5839 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5840
5841 if (data)
5842 sp->rx_csum = 1;
5843 else
5844 sp->rx_csum = 0;
5845
5846 return 0;
5847}
ac1f60db
AB		 5848
5849static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 5850{
5851 return (XENA_EEPROM_SPACE);
5852}
5853
ac1f60db 5854static int s2io_ethtool_self_test_count(struct net_device *dev)
1da177e4
LT		 5855{
5856 return (S2IO_TEST_LEN);
5857}
ac1f60db
AB		 5858
5859static void s2io_ethtool_get_strings(struct net_device *dev,
5860 u32 stringset, u8 * data)
1da177e4 5861{
fa1f0cb3
SS		 5862 int stat_size = 0;
5863 struct s2io_nic *sp = dev->priv;
5864
1da177e4
LT		 5865 switch (stringset) {
5866 case ETH_SS_TEST:
5867 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
5868 break;
5869 case ETH_SS_STATS:
fa1f0cb3
SS		 5870 stat_size = sizeof(ethtool_xena_stats_keys);
5871 memcpy(data, &ethtool_xena_stats_keys,stat_size);
5872 if(sp->device_type == XFRAME_II_DEVICE) {
5873 memcpy(data + stat_size,
5874 &ethtool_enhanced_stats_keys,
5875 sizeof(ethtool_enhanced_stats_keys));
5876 stat_size += sizeof(ethtool_enhanced_stats_keys);
5877 }
5878
5879 memcpy(data + stat_size, &ethtool_driver_stats_keys,
5880 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 5881 }
5882}
1da177e4
LT		 5883static int s2io_ethtool_get_stats_count(struct net_device *dev)
5884{
fa1f0cb3
SS		 5885 struct s2io_nic *sp = dev->priv;
5886 int stat_count = 0;
5887 switch(sp->device_type) {
5888 case XFRAME_I_DEVICE:
5889 stat_count = XFRAME_I_STAT_LEN;
5890 break;
5891
5892 case XFRAME_II_DEVICE:
5893 stat_count = XFRAME_II_STAT_LEN;
5894 break;
5895 }
5896
5897 return stat_count;
1da177e4
LT		 5898}
5899
ac1f60db 5900static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 5901{
5902 if (data)
5903 dev->features |= NETIF_F_IP_CSUM;
5904 else
5905 dev->features &= ~NETIF_F_IP_CSUM;
5906
5907 return 0;
5908}
5909
75c30b13
AR		 5910static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
5911{
5912 return (dev->features & NETIF_F_TSO) != 0;
5913}
5914static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
5915{
5916 if (data)
5917 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
5918 else
5919 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
5920
5921 return 0;
5922}
1da177e4 5923
7282d491 5924static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 5925 .get_settings = s2io_ethtool_gset,
5926 .set_settings = s2io_ethtool_sset,
5927 .get_drvinfo = s2io_ethtool_gdrvinfo,
5928 .get_regs_len = s2io_ethtool_get_regs_len,
5929 .get_regs = s2io_ethtool_gregs,
5930 .get_link = ethtool_op_get_link,
5931 .get_eeprom_len = s2io_get_eeprom_len,
5932 .get_eeprom = s2io_ethtool_geeprom,
5933 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 5934 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 5935 .get_pauseparam = s2io_ethtool_getpause_data,
5936 .set_pauseparam = s2io_ethtool_setpause_data,
5937 .get_rx_csum = s2io_ethtool_get_rx_csum,
5938 .set_rx_csum = s2io_ethtool_set_rx_csum,
5939 .get_tx_csum = ethtool_op_get_tx_csum,
5940 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
5941 .get_sg = ethtool_op_get_sg,
5942 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 5943 .get_tso = s2io_ethtool_op_get_tso,
5944 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd
AR		 5945 .get_ufo = ethtool_op_get_ufo,
5946 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 5947 .self_test_count = s2io_ethtool_self_test_count,
5948 .self_test = s2io_ethtool_test,
5949 .get_strings = s2io_ethtool_get_strings,
5950 .phys_id = s2io_ethtool_idnic,
5951 .get_stats_count = s2io_ethtool_get_stats_count,
5952 .get_ethtool_stats = s2io_get_ethtool_stats
5953};
5954
5955/**
20346722 5956 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 5957 * @dev : Device pointer.
5958 * @ifr : An IOCTL specefic structure, that can contain a pointer to
5959 * a proprietary structure used to pass information to the driver.
5960 * @cmd : This is used to distinguish between the different commands that
5961 * can be passed to the IOCTL functions.
5962 * Description:
20346722
K		 5963 * Currently there are no special functionality supported in IOCTL, hence
5964 * function always return EOPNOTSUPPORTED
1da177e4
LT		 5965 */
5966
ac1f60db 5967static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 5968{
5969 return -EOPNOTSUPP;
5970}
5971
5972/**
5973 * s2io_change_mtu - entry point to change MTU size for the device.
5974 * @dev : device pointer.
5975 * @new_mtu : the new MTU size for the device.
5976 * Description: A driver entry point to change MTU size for the device.
5977 * Before changing the MTU the device must be stopped.
5978 * Return value:
5979 * 0 on success and an appropriate (-)ve integer as defined in errno.h
5980 * file on failure.
5981 */
5982
ac1f60db 5983static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 5984{
1ee6dd77 5985 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5986
5987 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
5988 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
5989 dev->name);
5990 return -EPERM;
5991 }
5992
1da177e4 5993 dev->mtu = new_mtu;
d8892c6e 5994 if (netif_running(dev)) {
e6a8fee2 5995 s2io_card_down(sp);
d8892c6e
K		 5996 netif_stop_queue(dev);
5997 if (s2io_card_up(sp)) {
5998 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
5999 __FUNCTION__);
6000 }
6001 if (netif_queue_stopped(dev))
6002 netif_wake_queue(dev);
6003 } else { /* Device is down */
1ee6dd77 6004 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6005 u64 val64 = new_mtu;
6006
6007 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6008 }
1da177e4
LT		 6009
6010 return 0;
6011}
6012
6013/**
6014 * s2io_tasklet - Bottom half of the ISR.
6015 * @dev_adr : address of the device structure in dma_addr_t format.
6016 * Description:
6017 * This is the tasklet or the bottom half of the ISR. This is
20346722 6018 * an extension of the ISR which is scheduled by the scheduler to be run
1da177e4 6019 * when the load on the CPU is low. All low priority tasks of the ISR can
20346722 6020 * be pushed into the tasklet. For now the tasklet is used only to
1da177e4
LT		 6021 * replenish the Rx buffers in the Rx buffer descriptors.
6022 * Return value:
6023 * void.
6024 */
6025
6026static void s2io_tasklet(unsigned long dev_addr)
6027{
6028 struct net_device *dev = (struct net_device *) dev_addr;
1ee6dd77 6029 struct s2io_nic *sp = dev->priv;
1da177e4 6030 int i, ret;
1ee6dd77 6031 struct mac_info *mac_control;
1da177e4
LT		 6032 struct config_param *config;
6033
6034 mac_control = &sp->mac_control;
6035 config = &sp->config;
6036
6037 if (!TASKLET_IN_USE) {
6038 for (i = 0; i < config->rx_ring_num; i++) {
6039 ret = fill_rx_buffers(sp, i);
6040 if (ret == -ENOMEM) {
0c61ed5f 6041 DBG_PRINT(INFO_DBG, "%s: Out of ",
1da177e4 6042 dev->name);
491976b2 6043 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
1da177e4
LT		 6044 break;
6045 } else if (ret == -EFILL) {
0c61ed5f 6046 DBG_PRINT(INFO_DBG,
1da177e4
LT		 6047 "%s: Rx Ring %d is full\n",
6048 dev->name, i);
6049 break;
6050 }
6051 }
6052 clear_bit(0, (&sp->tasklet_status));
6053 }
6054}
6055
6056/**
6057 * s2io_set_link - Set the LInk status
6058 * @data: long pointer to device private structue
6059 * Description: Sets the link status for the adapter
6060 */
6061
c4028958 6062static void s2io_set_link(struct work_struct *work)
1da177e4 6063{
1ee6dd77 6064 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 6065 struct net_device *dev = nic->dev;
1ee6dd77 6066 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6067 register u64 val64;
6068 u16 subid;
6069
22747d6b
FR		 6070 rtnl_lock();
6071
6072 if (!netif_running(dev))
6073 goto out_unlock;
6074
1da177e4
LT		 6075 if (test_and_set_bit(0, &(nic->link_state))) {
6076 /* The card is being reset, no point doing anything */
22747d6b 6077 goto out_unlock;
1da177e4
LT		 6078 }
6079
6080 subid = nic->pdev->subsystem_device;
a371a07d
K		 6081 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6082 /*
6083 * Allow a small delay for the NICs self initiated
6084 * cleanup to complete.
6085 */
6086 msleep(100);
6087 }
1da177e4
LT		 6088
6089 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6090 if (LINK_IS_UP(val64)) {
6091 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6092 if (verify_xena_quiescence(nic)) {
6093 val64 = readq(&bar0->adapter_control);
6094 val64 |= ADAPTER_CNTL_EN;
1da177e4 6095 writeq(val64, &bar0->adapter_control);
19a60522
SS		 6096 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6097 nic->device_type, subid)) {
6098 val64 = readq(&bar0->gpio_control);
6099 val64 |= GPIO_CTRL_GPIO_0;
6100 writeq(val64, &bar0->gpio_control);
6101 val64 = readq(&bar0->gpio_control);
6102 } else {
6103 val64 |= ADAPTER_LED_ON;
6104 writeq(val64, &bar0->adapter_control);
a371a07d 6105 }
1da177e4 6106 nic->device_enabled_once = TRUE;
19a60522
SS		 6107 } else {
6108 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6109 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6110 netif_stop_queue(dev);
1da177e4 6111 }
19a60522
SS		 6112 }
6113 val64 = readq(&bar0->adapter_status);
6114 if (!LINK_IS_UP(val64)) {
6115 DBG_PRINT(ERR_DBG, "%s:", dev->name);
6116 DBG_PRINT(ERR_DBG, " Link down after enabling ");
6117 DBG_PRINT(ERR_DBG, "device \n");
6118 } else
1da177e4 6119 s2io_link(nic, LINK_UP);
19a60522
SS		 6120 } else {
6121 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6122 subid)) {
6123 val64 = readq(&bar0->gpio_control);
6124 val64 &= ~GPIO_CTRL_GPIO_0;
6125 writeq(val64, &bar0->gpio_control);
6126 val64 = readq(&bar0->gpio_control);
1da177e4 6127 }
19a60522 6128 s2io_link(nic, LINK_DOWN);
1da177e4
LT		 6129 }
6130 clear_bit(0, &(nic->link_state));
22747d6b
FR		 6131
6132out_unlock:
d8d70caf 6133 rtnl_unlock();
1da177e4
LT		 6134}
6135
1ee6dd77
RB		 6136static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6137 struct buffAdd *ba,
6138 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6139 u64 *temp2, int size)
5d3213cc
AR		 6140{
6141 struct net_device *dev = sp->dev;
491abf25 6142 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6143
6144 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6145 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6146 /* allocate skb */
6147 if (*skb) {
6148 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6149 /*
6150 * As Rx frame are not going to be processed,
6151 * using same mapped address for the Rxd
6152 * buffer pointer
6153 */
6d517a27 6154 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6155 } else {
6156 *skb = dev_alloc_skb(size);
6157 if (!(*skb)) {
0c61ed5f 6158 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6159 DBG_PRINT(INFO_DBG, "memory to allocate ");
6160 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6161 sp->mac_control.stats_info->sw_stat. \
6162 mem_alloc_fail_cnt++;
5d3213cc
AR		 6163 return -ENOMEM ;
6164 }
491976b2
SH		 6165 sp->mac_control.stats_info->sw_stat.mem_allocated
6166 += (*skb)->truesize;
5d3213cc
AR		 6167 /* storing the mapped addr in a temp variable
6168 * such it will be used for next rxd whose
6169 * Host Control is NULL
6170 */
6d517a27 6171 rxdp1->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6172 pci_map_single( sp->pdev, (*skb)->data,
6173 size - NET_IP_ALIGN,
6174 PCI_DMA_FROMDEVICE);
491abf25
VP		 6175 if( (rxdp1->Buffer0_ptr == 0) ||
6176 (rxdp1->Buffer0_ptr == DMA_ERROR_CODE)) {
6177 goto memalloc_failed;
6178 }
5d3213cc
AR		 6179 rxdp->Host_Control = (unsigned long) (*skb);
6180 }
6181 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6182 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6183 /* Two buffer Mode */
6184 if (*skb) {
6d517a27
VP		 6185 rxdp3->Buffer2_ptr = *temp2;
6186 rxdp3->Buffer0_ptr = *temp0;
6187 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6188 } else {
6189 *skb = dev_alloc_skb(size);
2ceaac75 6190 if (!(*skb)) {
c53d4945
SH		 6191 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6192 DBG_PRINT(INFO_DBG, "memory to allocate ");
6193 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6194 sp->mac_control.stats_info->sw_stat. \
6195 mem_alloc_fail_cnt++;
2ceaac75
DR		 6196 return -ENOMEM;
6197 }
491976b2
SH		 6198 sp->mac_control.stats_info->sw_stat.mem_allocated
6199 += (*skb)->truesize;
6d517a27 6200 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6201 pci_map_single(sp->pdev, (*skb)->data,
6202 dev->mtu + 4,
6203 PCI_DMA_FROMDEVICE);
491abf25
VP		 6204 if( (rxdp3->Buffer2_ptr == 0) ||
6205 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE)) {
6206 goto memalloc_failed;
6207 }
6d517a27 6208 rxdp3->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6209 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6210 PCI_DMA_FROMDEVICE);
491abf25
VP		 6211 if( (rxdp3->Buffer0_ptr == 0) ||
6212 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE)) {
6213 pci_unmap_single (sp->pdev,
3e847423 6214 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6215 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6216 goto memalloc_failed;
6217 }
5d3213cc
AR		 6218 rxdp->Host_Control = (unsigned long) (*skb);
6219
6220 /* Buffer-1 will be dummy buffer not used */
6d517a27 6221 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6222 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
5d3213cc 6223 PCI_DMA_FROMDEVICE);
491abf25
VP		 6224 if( (rxdp3->Buffer1_ptr == 0) ||
6225 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
6226 pci_unmap_single (sp->pdev,
3e847423
AV		 6227 (dma_addr_t)rxdp3->Buffer0_ptr,
6228 BUF0_LEN, PCI_DMA_FROMDEVICE);
6229 pci_unmap_single (sp->pdev,
6230 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6231 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6232 goto memalloc_failed;
6233 }
5d3213cc
AR		 6234 }
6235 }
6236 return 0;
491abf25
VP		 6237 memalloc_failed:
6238 stats->pci_map_fail_cnt++;
6239 stats->mem_freed += (*skb)->truesize;
6240 dev_kfree_skb(*skb);
6241 return -ENOMEM;
5d3213cc 6242}
491abf25 6243
1ee6dd77
RB		 6244static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6245 int size)
5d3213cc
AR		 6246{
6247 struct net_device *dev = sp->dev;
6248 if (sp->rxd_mode == RXD_MODE_1) {
6249 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6250 } else if (sp->rxd_mode == RXD_MODE_3B) {
6251 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6252 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6253 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
5d3213cc
AR		 6254 }
6255}
6256
1ee6dd77 6257static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6258{
6259 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6260 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6261 struct config_param *config = &sp->config;
6262 struct net_device *dev = sp->dev;
1ee6dd77 6263 struct RxD_t *rxdp = NULL;
5d3213cc 6264 struct sk_buff *skb = NULL;
1ee6dd77 6265 struct buffAdd *ba = NULL;
5d3213cc
AR		 6266 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6267
6268 /* Calculate the size based on ring mode */
6269 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6270 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6271 if (sp->rxd_mode == RXD_MODE_1)
6272 size += NET_IP_ALIGN;
6273 else if (sp->rxd_mode == RXD_MODE_3B)
6274 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6275
6276 for (i = 0; i < config->rx_ring_num; i++) {
6277 blk_cnt = config->rx_cfg[i].num_rxd /
6278 (rxd_count[sp->rxd_mode] +1);
6279
6280 for (j = 0; j < blk_cnt; j++) {
6281 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6282 rxdp = mac_control->rings[i].
6283 rx_blocks[j].rxds[k].virt_addr;
6d517a27 6284 if(sp->rxd_mode == RXD_MODE_3B)
5d3213cc 6285 ba = &mac_control->rings[i].ba[j][k];
ac1f90d6 6286 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 6287 &skb,(u64 *)&temp0_64,
6288 (u64 *)&temp1_64,
ac1f90d6
SS		 6289 (u64 *)&temp2_64,
6290 size) == ENOMEM) {
6291 return 0;
6292 }
5d3213cc
AR		 6293
6294 set_rxd_buffer_size(sp, rxdp, size);
6295 wmb();
6296 /* flip the Ownership bit to Hardware */
6297 rxdp->Control_1 |= RXD_OWN_XENA;
6298 }
6299 }
6300 }
6301 return 0;
6302
6303}
6304
1ee6dd77 6305static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 6306{
e6a8fee2 6307 int ret = 0;
c92ca04b 6308 struct net_device *dev = sp->dev;
e6a8fee2 6309 int err = 0;
1da177e4 6310
eccb8628 6311 if (sp->intr_type == MSI_X)
e6a8fee2
AR		 6312 ret = s2io_enable_msi_x(sp);
6313 if (ret) {
6314 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6315 sp->intr_type = INTA;
20346722 6316 }
1da177e4 6317
1ee6dd77 6318 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 6319 store_xmsi_data(sp);
c92ca04b 6320
e6a8fee2 6321 /* After proper initialization of H/W, register ISR */
e6a8fee2 6322 if (sp->intr_type == MSI_X) {
fb6a825b 6323 int i, msix_tx_cnt=0,msix_rx_cnt=0;
c92ca04b 6324
e6a8fee2
AR		 6325 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6326 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6327 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6328 dev->name, i);
6329 err = request_irq(sp->entries[i].vector,
6330 s2io_msix_fifo_handle, 0, sp->desc[i],
6331 sp->s2io_entries[i].arg);
fb6a825b
SS		 6332 /* If either data or addr is zero print it */
6333 if(!(sp->msix_info[i].addr &&
6334 sp->msix_info[i].data)) {
6335 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6336 "Data:0x%lx\n",sp->desc[i],
6337 (unsigned long long)
6338 sp->msix_info[i].addr,
6339 (unsigned long)
6340 ntohl(sp->msix_info[i].data));
6341 } else {
6342 msix_tx_cnt++;
6343 }
e6a8fee2
AR		 6344 } else {
6345 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6346 dev->name, i);
6347 err = request_irq(sp->entries[i].vector,
6348 s2io_msix_ring_handle, 0, sp->desc[i],
6349 sp->s2io_entries[i].arg);
fb6a825b
SS		 6350 /* If either data or addr is zero print it */
6351 if(!(sp->msix_info[i].addr &&
6352 sp->msix_info[i].data)) {
6353 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx"
6354 "Data:0x%lx\n",sp->desc[i],
6355 (unsigned long long)
6356 sp->msix_info[i].addr,
6357 (unsigned long)
6358 ntohl(sp->msix_info[i].data));
6359 } else {
6360 msix_rx_cnt++;
6361 }
c92ca04b 6362 }
e6a8fee2
AR		 6363 if (err) {
6364 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6365 "failed\n", dev->name, i);
6366 DBG_PRINT(ERR_DBG, "Returned: %d\n", err);
6367 return -1;
6368 }
6369 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6370 }
fb6a825b
SS		 6371 printk("MSI-X-TX %d entries enabled\n",msix_tx_cnt);
6372 printk("MSI-X-RX %d entries enabled\n",msix_rx_cnt);
e6a8fee2
AR		 6373 }
6374 if (sp->intr_type == INTA) {
6375 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6376 sp->name, dev);
6377 if (err) {
6378 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6379 dev->name);
6380 return -1;
6381 }
6382 }
6383 return 0;
6384}
1ee6dd77 6385static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2
AR		 6386{
6387 int cnt = 0;
6388 struct net_device *dev = sp->dev;
6389
6390 if (sp->intr_type == MSI_X) {
6391 int i;
6392 u16 msi_control;
6393
6394 for (i=1; (sp->s2io_entries[i].in_use ==
6395 MSIX_REGISTERED_SUCCESS); i++) {
6396 int vector = sp->entries[i].vector;
6397 void *arg = sp->s2io_entries[i].arg;
6398
6399 free_irq(vector, arg);
6400 }
6401 pci_read_config_word(sp->pdev, 0x42, &msi_control);
6402 msi_control &= 0xFFFE; /* Disable MSI */
6403 pci_write_config_word(sp->pdev, 0x42, msi_control);
6404
6405 pci_disable_msix(sp->pdev);
6406 } else {
6407 free_irq(sp->pdev->irq, dev);
c92ca04b
AR		 6408 }
6409 /* Waiting till all Interrupt handlers are complete */
6410 cnt = 0;
6411 do {
6412 msleep(10);
6413 if (!atomic_read(&sp->isr_cnt))
6414 break;
6415 cnt++;
6416 } while(cnt < 5);
e6a8fee2
AR		 6417}
6418
d796fdb7 6419static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
e6a8fee2
AR		 6420{
6421 int cnt = 0;
1ee6dd77 6422 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2
AR		 6423 unsigned long flags;
6424 register u64 val64 = 0;
6425
6426 del_timer_sync(&sp->alarm_timer);
6427 /* If s2io_set_link task is executing, wait till it completes. */
6428 while (test_and_set_bit(0, &(sp->link_state))) {
6429 msleep(50);
6430 }
6431 atomic_set(&sp->card_state, CARD_DOWN);
6432
6433 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 6434 if (do_io)
6435 stop_nic(sp);
e6a8fee2
AR		 6436
6437 s2io_rem_isr(sp);
1da177e4
LT		 6438
6439 /* Kill tasklet. */
6440 tasklet_kill(&sp->task);
6441
6442 /* Check if the device is Quiescent and then Reset the NIC */
d796fdb7 6443 while(do_io) {
5d3213cc
AR		 6444 /* As per the HW requirement we need to replenish the
6445 * receive buffer to avoid the ring bump. Since there is
6446 * no intention of processing the Rx frame at this pointwe are
6447 * just settting the ownership bit of rxd in Each Rx
6448 * ring to HW and set the appropriate buffer size
6449 * based on the ring mode
6450 */
6451 rxd_owner_bit_reset(sp);
6452
1da177e4 6453 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6454 if (verify_xena_quiescence(sp)) {
6455 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 6456 break;
6457 }
6458
6459 msleep(50);
6460 cnt++;
6461 if (cnt == 10) {
6462 DBG_PRINT(ERR_DBG,
6463 "s2io_close:Device not Quiescent ");
6464 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
6465 (unsigned long long) val64);
6466 break;
6467 }
d796fdb7
LV		 6468 }
6469 if (do_io)
6470 s2io_reset(sp);
1da177e4 6471
7ba013ac
K		 6472 spin_lock_irqsave(&sp->tx_lock, flags);
6473 /* Free all Tx buffers */
1da177e4 6474 free_tx_buffers(sp);
7ba013ac
K		 6475 spin_unlock_irqrestore(&sp->tx_lock, flags);
6476
6477 /* Free all Rx buffers */
6478 spin_lock_irqsave(&sp->rx_lock, flags);
1da177e4 6479 free_rx_buffers(sp);
7ba013ac 6480 spin_unlock_irqrestore(&sp->rx_lock, flags);
1da177e4 6481
1da177e4
LT		 6482 clear_bit(0, &(sp->link_state));
6483}
6484
d796fdb7
LV		 6485static void s2io_card_down(struct s2io_nic * sp)
6486{
6487 do_s2io_card_down(sp, 1);
6488}
6489
1ee6dd77 6490static int s2io_card_up(struct s2io_nic * sp)
1da177e4 6491{
cc6e7c44 6492 int i, ret = 0;
1ee6dd77 6493 struct mac_info *mac_control;
1da177e4
LT		 6494 struct config_param *config;
6495 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 6496 u16 interruptible;
1da177e4
LT		 6497
6498 /* Initialize the H/W I/O registers */
6499 if (init_nic(sp) != 0) {
6500 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
6501 dev->name);
e6a8fee2 6502 s2io_reset(sp);
1da177e4
LT		 6503 return -ENODEV;
6504 }
6505
20346722
K		 6506 /*
6507 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 6508 * Rx ring and initializing buffers into 30 Rx blocks
6509 */
6510 mac_control = &sp->mac_control;
6511 config = &sp->config;
6512
6513 for (i = 0; i < config->rx_ring_num; i++) {
6514 if ((ret = fill_rx_buffers(sp, i))) {
6515 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
6516 dev->name);
6517 s2io_reset(sp);
6518 free_rx_buffers(sp);
6519 return -ENOMEM;
6520 }
6521 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
6522 atomic_read(&sp->rx_bufs_left[i]));
6523 }
19a60522
SS		 6524 /* Maintain the state prior to the open */
6525 if (sp->promisc_flg)
6526 sp->promisc_flg = 0;
6527 if (sp->m_cast_flg) {
6528 sp->m_cast_flg = 0;
6529 sp->all_multi_pos= 0;
6530 }
1da177e4
LT		 6531
6532 /* Setting its receive mode */
6533 s2io_set_multicast(dev);
6534
7d3d0439 6535 if (sp->lro) {
b41477f3 6536 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 6537 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
6538 /* Check if we can use(if specified) user provided value */
6539 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
6540 sp->lro_max_aggr_per_sess = lro_max_pkts;
6541 }
6542
1da177e4
LT		 6543 /* Enable Rx Traffic and interrupts on the NIC */
6544 if (start_nic(sp)) {
6545 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 6546 s2io_reset(sp);
e6a8fee2
AR		 6547 free_rx_buffers(sp);
6548 return -ENODEV;
6549 }
6550
6551 /* Add interrupt service routine */
6552 if (s2io_add_isr(sp) != 0) {
6553 if (sp->intr_type == MSI_X)
6554 s2io_rem_isr(sp);
6555 s2io_reset(sp);
1da177e4
LT		 6556 free_rx_buffers(sp);
6557 return -ENODEV;
6558 }
6559
25fff88e
K		 6560 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
6561
e6a8fee2
AR		 6562 /* Enable tasklet for the device */
6563 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
6564
6565 /* Enable select interrupts */
6566 if (sp->intr_type != INTA)
6567 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
6568 else {
6569 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
6570 interruptible |= TX_PIC_INTR | RX_PIC_INTR;
6571 interruptible |= TX_MAC_INTR | RX_MAC_INTR;
6572 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
6573 }
6574
6575
1da177e4
LT		 6576 atomic_set(&sp->card_state, CARD_UP);
6577 return 0;
6578}
6579
20346722 6580/**
1da177e4
LT		 6581 * s2io_restart_nic - Resets the NIC.
6582 * @data : long pointer to the device private structure
6583 * Description:
6584 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 6585 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 6586 * the run time of the watch dog routine which is run holding a
6587 * spin lock.
6588 */
6589
c4028958 6590static void s2io_restart_nic(struct work_struct *work)
1da177e4 6591{
1ee6dd77 6592 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 6593 struct net_device *dev = sp->dev;
1da177e4 6594
22747d6b
FR		 6595 rtnl_lock();
6596
6597 if (!netif_running(dev))
6598 goto out_unlock;
6599
e6a8fee2 6600 s2io_card_down(sp);
1da177e4
LT		 6601 if (s2io_card_up(sp)) {
6602 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6603 dev->name);
6604 }
6605 netif_wake_queue(dev);
6606 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
6607 dev->name);
22747d6b
FR		 6608out_unlock:
6609 rtnl_unlock();
1da177e4
LT		 6610}
6611
20346722
K		 6612/**
6613 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 6614 * @dev : Pointer to net device structure
6615 * Description:
6616 * This function is triggered if the Tx Queue is stopped
6617 * for a pre-defined amount of time when the Interface is still up.
6618 * If the Interface is jammed in such a situation, the hardware is
6619 * reset (by s2io_close) and restarted again (by s2io_open) to
6620 * overcome any problem that might have been caused in the hardware.
6621 * Return value:
6622 * void
6623 */
6624
6625static void s2io_tx_watchdog(struct net_device *dev)
6626{
1ee6dd77 6627 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6628
6629 if (netif_carrier_ok(dev)) {
c53d4945 6630 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 6631 schedule_work(&sp->rst_timer_task);
bd1034f0 6632 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 6633 }
6634}
6635
6636/**
6637 * rx_osm_handler - To perform some OS related operations on SKB.
6638 * @sp: private member of the device structure,pointer to s2io_nic structure.
6639 * @skb : the socket buffer pointer.
6640 * @len : length of the packet
6641 * @cksum : FCS checksum of the frame.
6642 * @ring_no : the ring from which this RxD was extracted.
20346722 6643 * Description:
b41477f3 6644 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 6645 * some OS related operations on the SKB before passing it to the upper
6646 * layers. It mainly checks if the checksum is OK, if so adds it to the
6647 * SKBs cksum variable, increments the Rx packet count and passes the SKB
6648 * to the upper layer. If the checksum is wrong, it increments the Rx
6649 * packet error count, frees the SKB and returns error.
6650 * Return value:
6651 * SUCCESS on success and -1 on failure.
6652 */
1ee6dd77 6653static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 6654{
1ee6dd77 6655 struct s2io_nic *sp = ring_data->nic;
1da177e4 6656 struct net_device *dev = (struct net_device *) sp->dev;
20346722
K		 6657 struct sk_buff *skb = (struct sk_buff *)
6658 ((unsigned long) rxdp->Host_Control);
6659 int ring_no = ring_data->ring_no;
1da177e4 6660 u16 l3_csum, l4_csum;
863c11a9 6661 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
1ee6dd77 6662 struct lro *lro;
f9046eb3 6663 u8 err_mask;
da6971d8 6664
20346722 6665 skb->dev = dev;
c92ca04b 6666
863c11a9 6667 if (err) {
bd1034f0
AR		 6668 /* Check for parity error */
6669 if (err & 0x1) {
6670 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
6671 }
f9046eb3
OH		 6672 err_mask = err >> 48;
6673 switch(err_mask) {
491976b2
SH		 6674 case 1:
6675 sp->mac_control.stats_info->sw_stat.
6676 rx_parity_err_cnt++;
6677 break;
6678
6679 case 2:
6680 sp->mac_control.stats_info->sw_stat.
6681 rx_abort_cnt++;
6682 break;
6683
6684 case 3:
6685 sp->mac_control.stats_info->sw_stat.
6686 rx_parity_abort_cnt++;
6687 break;
6688
6689 case 4:
6690 sp->mac_control.stats_info->sw_stat.
6691 rx_rda_fail_cnt++;
6692 break;
6693
6694 case 5:
6695 sp->mac_control.stats_info->sw_stat.
6696 rx_unkn_prot_cnt++;
6697 break;
6698
6699 case 6:
6700 sp->mac_control.stats_info->sw_stat.
6701 rx_fcs_err_cnt++;
6702 break;
bd1034f0 6703
491976b2
SH		 6704 case 7:
6705 sp->mac_control.stats_info->sw_stat.
6706 rx_buf_size_err_cnt++;
6707 break;
6708
6709 case 8:
6710 sp->mac_control.stats_info->sw_stat.
6711 rx_rxd_corrupt_cnt++;
6712 break;
6713
6714 case 15:
6715 sp->mac_control.stats_info->sw_stat.
6716 rx_unkn_err_cnt++;
6717 break;
6718 }
863c11a9
AR		 6719 /*
6720 * Drop the packet if bad transfer code. Exception being
6721 * 0x5, which could be due to unsupported IPv6 extension header.
6722 * In this case, we let stack handle the packet.
6723 * Note that in this case, since checksum will be incorrect,
6724 * stack will validate the same.
6725 */
f9046eb3
OH		 6726 if (err_mask != 0x5) {
6727 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
6728 dev->name, err_mask);
863c11a9 6729 sp->stats.rx_crc_errors++;
491976b2
SH		 6730 sp->mac_control.stats_info->sw_stat.mem_freed
6731 += skb->truesize;
863c11a9
AR		 6732 dev_kfree_skb(skb);
6733 atomic_dec(&sp->rx_bufs_left[ring_no]);
6734 rxdp->Host_Control = 0;
6735 return 0;
6736 }
20346722 6737 }
1da177e4 6738
20346722 6739 /* Updating statistics */
573608e4 6740 sp->stats.rx_packets++;
20346722 6741 rxdp->Host_Control = 0;
da6971d8
AR		 6742 if (sp->rxd_mode == RXD_MODE_1) {
6743 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 6744
da6971d8
AR		 6745 sp->stats.rx_bytes += len;
6746 skb_put(skb, len);
6747
6d517a27 6748 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 6749 int get_block = ring_data->rx_curr_get_info.block_index;
6750 int get_off = ring_data->rx_curr_get_info.offset;
6751 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
6752 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
6753 unsigned char *buff = skb_push(skb, buf0_len);
6754
1ee6dd77 6755 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8
AR		 6756 sp->stats.rx_bytes += buf0_len + buf2_len;
6757 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 6758 skb_put(skb, buf2_len);
da6971d8 6759 }
20346722 6760
7d3d0439
RA		 6761 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
6762 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 6763 (sp->rx_csum)) {
6764 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 6765 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
6766 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 6767 /*
1da177e4
LT		 6768 * NIC verifies if the Checksum of the received
6769 * frame is Ok or not and accordingly returns
6770 * a flag in the RxD.
6771 */
6772 skb->ip_summed = CHECKSUM_UNNECESSARY;
7d3d0439
RA		 6773 if (sp->lro) {
6774 u32 tcp_len;
6775 u8 *tcp;
6776 int ret = 0;
6777
6778 ret = s2io_club_tcp_session(skb->data, &tcp,
6779 &tcp_len, &lro, rxdp, sp);
6780 switch (ret) {
6781 case 3: /* Begin anew */
6782 lro->parent = skb;
6783 goto aggregate;
6784 case 1: /* Aggregate */
6785 {
6786 lro_append_pkt(sp, lro,
6787 skb, tcp_len);
6788 goto aggregate;
6789 }
6790 case 4: /* Flush session */
6791 {
6792 lro_append_pkt(sp, lro,
6793 skb, tcp_len);
6794 queue_rx_frame(lro->parent);
6795 clear_lro_session(lro);
6796 sp->mac_control.stats_info->
6797 sw_stat.flush_max_pkts++;
6798 goto aggregate;
6799 }
6800 case 2: /* Flush both */
6801 lro->parent->data_len =
6802 lro->frags_len;
6803 sp->mac_control.stats_info->
6804 sw_stat.sending_both++;
6805 queue_rx_frame(lro->parent);
6806 clear_lro_session(lro);
6807 goto send_up;
6808 case 0: /* sessions exceeded */
c92ca04b
AR		 6809 case -1: /* non-TCP or not
6810 * L2 aggregatable
6811 */
7d3d0439
RA		 6812 case 5: /*
6813 * First pkt in session not
6814 * L3/L4 aggregatable
6815 */
6816 break;
6817 default:
6818 DBG_PRINT(ERR_DBG,
6819 "%s: Samadhana!!\n",
6820 __FUNCTION__);
6821 BUG();
6822 }
6823 }
1da177e4 6824 } else {
20346722
K		 6825 /*
6826 * Packet with erroneous checksum, let the
1da177e4
LT		 6827 * upper layers deal with it.
6828 */
6829 skb->ip_summed = CHECKSUM_NONE;
6830 }
6831 } else {
6832 skb->ip_summed = CHECKSUM_NONE;
6833 }
491976b2 6834 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439
RA		 6835 if (!sp->lro) {
6836 skb->protocol = eth_type_trans(skb, dev);
926930b2
SS		 6837 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
6838 vlan_strip_flag)) {
7d3d0439 6839 /* Queueing the vlan frame to the upper layer */
db874e65
SS		 6840 if (napi)
6841 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
6842 RXD_GET_VLAN_TAG(rxdp->Control_2));
6843 else
6844 vlan_hwaccel_rx(skb, sp->vlgrp,
6845 RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 6846 } else {
db874e65
SS		 6847 if (napi)
6848 netif_receive_skb(skb);
6849 else
6850 netif_rx(skb);
7d3d0439 6851 }
7d3d0439
RA		 6852 } else {
6853send_up:
6854 queue_rx_frame(skb);
6aa20a22 6855 }
1da177e4 6856 dev->last_rx = jiffies;
7d3d0439 6857aggregate:
1da177e4 6858 atomic_dec(&sp->rx_bufs_left[ring_no]);
1da177e4
LT		 6859 return SUCCESS;
6860}
6861
6862/**
6863 * s2io_link - stops/starts the Tx queue.
6864 * @sp : private member of the device structure, which is a pointer to the
6865 * s2io_nic structure.
6866 * @link : inidicates whether link is UP/DOWN.
6867 * Description:
6868 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 6869 * status of the NIC is is down or up. This is called by the Alarm
6870 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 6871 * Return value:
6872 * void.
6873 */
6874
1ee6dd77 6875static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 6876{
6877 struct net_device *dev = (struct net_device *) sp->dev;
6878
6879 if (link != sp->last_link_state) {
6880 if (link == LINK_DOWN) {
6881 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
6882 netif_carrier_off(dev);
491976b2
SH		 6883 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
6884 sp->mac_control.stats_info->sw_stat.link_up_time =
6885 jiffies - sp->start_time;
6886 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 6887 } else {
6888 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2
SH		 6889 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
6890 sp->mac_control.stats_info->sw_stat.link_down_time =
6891 jiffies - sp->start_time;
6892 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4
LT		 6893 netif_carrier_on(dev);
6894 }
6895 }
6896 sp->last_link_state = link;
491976b2 6897 sp->start_time = jiffies;
1da177e4
LT		 6898}
6899
20346722
K		 6900/**
6901 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
6902 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 6903 * s2io_nic structure.
6904 * Description:
6905 * This function initializes a few of the PCI and PCI-X configuration registers
6906 * with recommended values.
6907 * Return value:
6908 * void
6909 */
6910
1ee6dd77 6911static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 6912{
20346722 6913 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 6914
6915 /* Enable Data Parity Error Recovery in PCI-X command register. */
6916 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6917 &(pcix_cmd));
1da177e4 6918 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6919 (pcix_cmd | 1));
1da177e4 6920 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 6921 &(pcix_cmd));
1da177e4
LT		 6922
6923 /* Set the PErr Response bit in PCI command register. */
6924 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
6925 pci_write_config_word(sp->pdev, PCI_COMMAND,
6926 (pci_cmd | PCI_COMMAND_PARITY));
6927 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 6928}
6929
9dc737a7
AR		 6930static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
6931{
6932 if ( tx_fifo_num > 8) {
6933 DBG_PRINT(ERR_DBG, "s2io: Requested number of Tx fifos not "
6934 "supported\n");
6935 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Tx fifos\n");
6936 tx_fifo_num = 8;
6937 }
6938 if ( rx_ring_num > 8) {
6939 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
6940 "supported\n");
6941 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
6942 rx_ring_num = 8;
6943 }
db874e65
SS		 6944 if (*dev_intr_type != INTA)
6945 napi = 0;
6946
9dc737a7
AR		 6947#ifndef CONFIG_PCI_MSI
6948 if (*dev_intr_type != INTA) {
6949 DBG_PRINT(ERR_DBG, "s2io: This kernel does not support"
6950 "MSI/MSI-X. Defaulting to INTA\n");
6951 *dev_intr_type = INTA;
6952 }
6953#else
eccb8628 6954 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9dc737a7
AR		 6955 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
6956 "Defaulting to INTA\n");
6957 *dev_intr_type = INTA;
6958 }
6959#endif
6960 if ((*dev_intr_type == MSI_X) &&
6961 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
6962 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 6963 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 6964 "Defaulting to INTA\n");
6965 *dev_intr_type = INTA;
6966 }
fb6a825b 6967
6d517a27 6968 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 6969 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 6970 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
6971 rx_ring_mode = 1;
9dc737a7
AR		 6972 }
6973 return SUCCESS;
6974}
6975
9fc93a41
SS		 6976/**
6977 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
6978 * or Traffic class respectively.
6979 * @nic: device peivate variable
6980 * Description: The function configures the receive steering to
6981 * desired receive ring.
6982 * Return Value: SUCCESS on success and
6983 * '-1' on failure (endian settings incorrect).
6984 */
6985static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
6986{
6987 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6988 register u64 val64 = 0;
6989
6990 if (ds_codepoint > 63)
6991 return FAILURE;
6992
6993 val64 = RTS_DS_MEM_DATA(ring);
6994 writeq(val64, &bar0->rts_ds_mem_data);
6995
6996 val64 = RTS_DS_MEM_CTRL_WE |
6997 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
6998 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
6999
7000 writeq(val64, &bar0->rts_ds_mem_ctrl);
7001
7002 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7003 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7004 S2IO_BIT_RESET);
7005}
7006
1da177e4 7007/**
20346722 7008 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7009 * @pdev : structure containing the PCI related information of the device.
7010 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7011 * Description:
7012 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7013 * All OS related initialization including memory and device structure and
7014 * initlaization of the device private variable is done. Also the swapper
7015 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7016 * registers of the device.
7017 * Return value:
7018 * returns 0 on success and negative on failure.
7019 */
7020
7021static int __devinit
7022s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7023{
1ee6dd77 7024 struct s2io_nic *sp;
1da177e4 7025 struct net_device *dev;
1da177e4
LT		 7026 int i, j, ret;
7027 int dma_flag = FALSE;
7028 u32 mac_up, mac_down;
7029 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7030 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7031 u16 subid;
1ee6dd77 7032 struct mac_info *mac_control;
1da177e4 7033 struct config_param *config;
541ae68f 7034 int mode;
cc6e7c44 7035 u8 dev_intr_type = intr_type;
1da177e4 7036
9dc737a7
AR		 7037 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
7038 return ret;
1da177e4
LT		 7039
7040 if ((ret = pci_enable_device(pdev))) {
7041 DBG_PRINT(ERR_DBG,
7042 "s2io_init_nic: pci_enable_device failed\n");
7043 return ret;
7044 }
7045
1e7f0bd8 7046 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7047 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7048 dma_flag = TRUE;
1da177e4 7049 if (pci_set_consistent_dma_mask
1e7f0bd8 7050 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7051 DBG_PRINT(ERR_DBG,
7052 "Unable to obtain 64bit DMA for \
7053 consistent allocations\n");
7054 pci_disable_device(pdev);
7055 return -ENOMEM;
7056 }
1e7f0bd8 7057 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 7058 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7059 } else {
7060 pci_disable_device(pdev);
7061 return -ENOMEM;
7062 }
eccb8628
VP		 7063 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7064 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7065 pci_disable_device(pdev);
7066 return -ENODEV;
1da177e4
LT		 7067 }
7068
1ee6dd77 7069 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7070 if (dev == NULL) {
7071 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7072 pci_disable_device(pdev);
7073 pci_release_regions(pdev);
7074 return -ENODEV;
7075 }
7076
7077 pci_set_master(pdev);
7078 pci_set_drvdata(pdev, dev);
7079 SET_MODULE_OWNER(dev);
7080 SET_NETDEV_DEV(dev, &pdev->dev);
7081
7082 /* Private member variable initialized to s2io NIC structure */
7083 sp = dev->priv;
1ee6dd77 7084 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7085 sp->dev = dev;
7086 sp->pdev = pdev;
1da177e4 7087 sp->high_dma_flag = dma_flag;
1da177e4 7088 sp->device_enabled_once = FALSE;
da6971d8
AR		 7089 if (rx_ring_mode == 1)
7090 sp->rxd_mode = RXD_MODE_1;
7091 if (rx_ring_mode == 2)
7092 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7093
cc6e7c44 7094 sp->intr_type = dev_intr_type;
1da177e4 7095
541ae68f
K		 7096 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7097 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7098 sp->device_type = XFRAME_II_DEVICE;
7099 else
7100 sp->device_type = XFRAME_I_DEVICE;
7101
7d3d0439 7102 sp->lro = lro;
6aa20a22 7103
1da177e4
LT		 7104 /* Initialize some PCI/PCI-X fields of the NIC. */
7105 s2io_init_pci(sp);
7106
20346722 7107 /*
1da177e4 7108 * Setting the device configuration parameters.
20346722
K		 7109 * Most of these parameters can be specified by the user during
7110 * module insertion as they are module loadable parameters. If
7111 * these parameters are not not specified during load time, they
1da177e4
LT		 7112 * are initialized with default values.
7113 */
7114 mac_control = &sp->mac_control;
7115 config = &sp->config;
7116
7117 /* Tx side parameters. */
1da177e4
LT		 7118 config->tx_fifo_num = tx_fifo_num;
7119 for (i = 0; i < MAX_TX_FIFOS; i++) {
7120 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7121 config->tx_cfg[i].fifo_priority = i;
7122 }
7123
20346722
K		 7124 /* mapping the QoS priority to the configured fifos */
7125 for (i = 0; i < MAX_TX_FIFOS; i++)
7126 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7127
1da177e4
LT		 7128 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7129 for (i = 0; i < config->tx_fifo_num; i++) {
7130 config->tx_cfg[i].f_no_snoop =
7131 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7132 if (config->tx_cfg[i].fifo_len < 65) {
7133 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7134 break;
7135 }
7136 }
fed5eccd
AR		 7137 /* + 2 because one Txd for skb->data and one Txd for UFO */
7138 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7139
7140 /* Rx side parameters. */
1da177e4
LT		 7141 config->rx_ring_num = rx_ring_num;
7142 for (i = 0; i < MAX_RX_RINGS; i++) {
7143 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 7144 (rxd_count[sp->rxd_mode] + 1);
1da177e4
LT		 7145 config->rx_cfg[i].ring_priority = i;
7146 }
7147
7148 for (i = 0; i < rx_ring_num; i++) {
7149 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7150 config->rx_cfg[i].f_no_snoop =
7151 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7152 }
7153
7154 /* Setting Mac Control parameters */
7155 mac_control->rmac_pause_time = rmac_pause_time;
7156 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7157 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7158
7159
7160 /* Initialize Ring buffer parameters. */
7161 for (i = 0; i < config->rx_ring_num; i++)
7162 atomic_set(&sp->rx_bufs_left[i], 0);
7163
7ba013ac
K		 7164 /* Initialize the number of ISRs currently running */
7165 atomic_set(&sp->isr_cnt, 0);
7166
1da177e4
LT		 7167 /* initialize the shared memory used by the NIC and the host */
7168 if (init_shared_mem(sp)) {
7169 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7170 dev->name);
1da177e4
LT		 7171 ret = -ENOMEM;
7172 goto mem_alloc_failed;
7173 }
7174
7175 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7176 pci_resource_len(pdev, 0));
7177 if (!sp->bar0) {
19a60522 7178 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7179 dev->name);
7180 ret = -ENOMEM;
7181 goto bar0_remap_failed;
7182 }
7183
7184 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7185 pci_resource_len(pdev, 2));
7186 if (!sp->bar1) {
19a60522 7187 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7188 dev->name);
7189 ret = -ENOMEM;
7190 goto bar1_remap_failed;
7191 }
7192
7193 dev->irq = pdev->irq;
7194 dev->base_addr = (unsigned long) sp->bar0;
7195
7196 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7197 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7198 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 7199 (sp->bar1 + (j * 0x00020000));
7200 }
7201
7202 /* Driver entry points */
7203 dev->open = &s2io_open;
7204 dev->stop = &s2io_close;
7205 dev->hard_start_xmit = &s2io_xmit;
7206 dev->get_stats = &s2io_get_stats;
7207 dev->set_multicast_list = &s2io_set_multicast;
7208 dev->do_ioctl = &s2io_ioctl;
7209 dev->change_mtu = &s2io_change_mtu;
7210 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02
K		 7211 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7212 dev->vlan_rx_register = s2io_vlan_rx_register;
20346722 7213
1da177e4
LT		 7214 /*
7215 * will use eth_mac_addr() for dev->set_mac_address
7216 * mac address will be set every time dev->open() is called
7217 */
1da177e4 7218 dev->poll = s2io_poll;
20346722 7219 dev->weight = 32;
1da177e4 7220
612eff0e
BH		 7221#ifdef CONFIG_NET_POLL_CONTROLLER
7222 dev->poll_controller = s2io_netpoll;
7223#endif
7224
1da177e4
LT		 7225 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7226 if (sp->high_dma_flag == TRUE)
7227 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7228 dev->features |= NETIF_F_TSO;
f83ef8c0 7229 dev->features |= NETIF_F_TSO6;
db874e65 7230 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7231 dev->features |= NETIF_F_UFO;
7232 dev->features |= NETIF_F_HW_CSUM;
7233 }
1da177e4
LT		 7234
7235 dev->tx_timeout = &s2io_tx_watchdog;
7236 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7237 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7238 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7239
e960fc5c 7240 pci_save_state(sp->pdev);
1da177e4
LT		 7241
7242 /* Setting swapper control on the NIC, for proper reset operation */
7243 if (s2io_set_swapper(sp)) {
7244 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7245 dev->name);
7246 ret = -EAGAIN;
7247 goto set_swap_failed;
7248 }
7249
541ae68f
K		 7250 /* Verify if the Herc works on the slot its placed into */
7251 if (sp->device_type & XFRAME_II_DEVICE) {
7252 mode = s2io_verify_pci_mode(sp);
7253 if (mode < 0) {
7254 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7255 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7256 ret = -EBADSLT;
7257 goto set_swap_failed;
7258 }
7259 }
7260
7261 /* Not needed for Herc */
7262 if (sp->device_type & XFRAME_I_DEVICE) {
7263 /*
7264 * Fix for all "FFs" MAC address problems observed on
7265 * Alpha platforms
7266 */
7267 fix_mac_address(sp);
7268 s2io_reset(sp);
7269 }
1da177e4
LT		 7270
7271 /*
1da177e4
LT		 7272 * MAC address initialization.
7273 * For now only one mac address will be read and used.
7274 */
7275 bar0 = sp->bar0;
7276 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7277 RMAC_ADDR_CMD_MEM_OFFSET(0 + MAC_MAC_ADDR_START_OFFSET);
7278 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 7279 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 7280 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 7281 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7282 mac_down = (u32) tmp64;
7283 mac_up = (u32) (tmp64 >> 32);
7284
1da177e4
LT		 7285 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7286 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7287 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7288 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7289 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7290 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7291
1da177e4
LT		 7292 /* Set the factory defined MAC address initially */
7293 dev->addr_len = ETH_ALEN;
7294 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
7295
b41477f3
AR		 7296 /* reset Nic and bring it to known state */
7297 s2io_reset(sp);
7298
1da177e4 7299 /*
20346722 7300 * Initialize the tasklet status and link state flags
541ae68f 7301 * and the card state parameter
1da177e4
LT		 7302 */
7303 atomic_set(&(sp->card_state), 0);
7304 sp->tasklet_status = 0;
7305 sp->link_state = 0;
7306
1da177e4
LT		 7307 /* Initialize spinlocks */
7308 spin_lock_init(&sp->tx_lock);
db874e65
SS		 7309
7310 if (!napi)
7311 spin_lock_init(&sp->put_lock);
7ba013ac 7312 spin_lock_init(&sp->rx_lock);
1da177e4 7313
20346722
K		 7314 /*
7315 * SXE-002: Configure link and activity LED to init state
7316 * on driver load.
1da177e4
LT		 7317 */
7318 subid = sp->pdev->subsystem_device;
7319 if ((subid & 0xFF) >= 0x07) {
7320 val64 = readq(&bar0->gpio_control);
7321 val64 |= 0x0000800000000000ULL;
7322 writeq(val64, &bar0->gpio_control);
7323 val64 = 0x0411040400000000ULL;
7324 writeq(val64, (void __iomem *) bar0 + 0x2700);
7325 val64 = readq(&bar0->gpio_control);
7326 }
7327
7328 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7329
7330 if (register_netdev(dev)) {
7331 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7332 ret = -ENODEV;
7333 goto register_failed;
7334 }
9dc737a7 7335 s2io_vpd_read(sp);
0c61ed5f 7336 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
b41477f3 7337 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
44c10138 7338 sp->product_name, pdev->revision);
b41477f3
AR		 7339 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7340 s2io_driver_version);
9dc737a7 7341 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: "
19a60522 7342 "%02x:%02x:%02x:%02x:%02x:%02x", dev->name,
541ae68f
K		 7343 sp->def_mac_addr[0].mac_addr[0],
7344 sp->def_mac_addr[0].mac_addr[1],
7345 sp->def_mac_addr[0].mac_addr[2],
7346 sp->def_mac_addr[0].mac_addr[3],
7347 sp->def_mac_addr[0].mac_addr[4],
7348 sp->def_mac_addr[0].mac_addr[5]);
19a60522 7349 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 7350 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 7351 mode = s2io_print_pci_mode(sp);
541ae68f 7352 if (mode < 0) {
9dc737a7 7353 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 7354 ret = -EBADSLT;
9dc737a7 7355 unregister_netdev(dev);
541ae68f
K		 7356 goto set_swap_failed;
7357 }
541ae68f 7358 }
9dc737a7
AR		 7359 switch(sp->rxd_mode) {
7360 case RXD_MODE_1:
7361 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7362 dev->name);
7363 break;
7364 case RXD_MODE_3B:
7365 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7366 dev->name);
7367 break;
9dc737a7 7368 }
db874e65
SS		 7369
7370 if (napi)
7371 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
9dc737a7
AR		 7372 switch(sp->intr_type) {
7373 case INTA:
7374 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7375 break;
9dc737a7
AR		 7376 case MSI_X:
7377 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7378 break;
7379 }
7d3d0439
RA		 7380 if (sp->lro)
7381 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 7382 dev->name);
db874e65
SS		 7383 if (ufo)
7384 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7385 " enabled\n", dev->name);
7ba013ac 7386 /* Initialize device name */
9dc737a7 7387 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 7388
b6e3f982
K		 7389 /* Initialize bimodal Interrupts */
7390 sp->config.bimodal = bimodal;
7391 if (!(sp->device_type & XFRAME_II_DEVICE) && bimodal) {
7392 sp->config.bimodal = 0;
7393 DBG_PRINT(ERR_DBG,"%s:Bimodal intr not supported by Xframe I\n",
7394 dev->name);
7395 }
7396
20346722
K		 7397 /*
7398 * Make Link state as off at this point, when the Link change
7399 * interrupt comes the state will be automatically changed to
1da177e4
LT		 7400 * the right state.
7401 */
7402 netif_carrier_off(dev);
1da177e4
LT		 7403
7404 return 0;
7405
7406 register_failed:
7407 set_swap_failed:
7408 iounmap(sp->bar1);
7409 bar1_remap_failed:
7410 iounmap(sp->bar0);
7411 bar0_remap_failed:
7412 mem_alloc_failed:
7413 free_shared_mem(sp);
7414 pci_disable_device(pdev);
eccb8628 7415 pci_release_regions(pdev);
1da177e4
LT		 7416 pci_set_drvdata(pdev, NULL);
7417 free_netdev(dev);
7418
7419 return ret;
7420}
7421
7422/**
20346722 7423 * s2io_rem_nic - Free the PCI device
1da177e4 7424 * @pdev: structure containing the PCI related information of the device.
20346722 7425 * Description: This function is called by the Pci subsystem to release a
1da177e4 7426 * PCI device and free up all resource held up by the device. This could
20346722 7427 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 7428 * from memory.
7429 */
7430
7431static void __devexit s2io_rem_nic(struct pci_dev *pdev)
7432{
7433 struct net_device *dev =
7434 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 7435 struct s2io_nic *sp;
1da177e4
LT		 7436
7437 if (dev == NULL) {
7438 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
7439 return;
7440 }
7441
22747d6b
FR		 7442 flush_scheduled_work();
7443
1da177e4
LT		 7444 sp = dev->priv;
7445 unregister_netdev(dev);
7446
7447 free_shared_mem(sp);
7448 iounmap(sp->bar0);
7449 iounmap(sp->bar1);
eccb8628 7450 pci_release_regions(pdev);
1da177e4 7451 pci_set_drvdata(pdev, NULL);
1da177e4 7452 free_netdev(dev);
19a60522 7453 pci_disable_device(pdev);
1da177e4
LT		 7454}
7455
7456/**
7457 * s2io_starter - Entry point for the driver
7458 * Description: This function is the entry point for the driver. It verifies
7459 * the module loadable parameters and initializes PCI configuration space.
7460 */
7461
7462int __init s2io_starter(void)
7463{
29917620 7464 return pci_register_driver(&s2io_driver);
1da177e4
LT		 7465}
7466
7467/**
20346722 7468 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 7469 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
7470 */
7471
372cc597 7472static __exit void s2io_closer(void)
1da177e4
LT		 7473{
7474 pci_unregister_driver(&s2io_driver);
7475 DBG_PRINT(INIT_DBG, "cleanup done\n");
7476}
7477
7478module_init(s2io_starter);
7479module_exit(s2io_closer);
7d3d0439 7480
6aa20a22 7481static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
1ee6dd77 7482 struct tcphdr **tcp, struct RxD_t *rxdp)
7d3d0439
RA		 7483{
7484 int ip_off;
7485 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
7486
7487 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
7488 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
7489 __FUNCTION__);
7490 return -1;
7491 }
7492
7493 /* TODO:
7494 * By default the VLAN field in the MAC is stripped by the card, if this
7495 * feature is turned off in rx_pa_cfg register, then the ip_off field
7496 * has to be shifted by a further 2 bytes
7497 */
7498 switch (l2_type) {
7499 case 0: /* DIX type */
7500 case 4: /* DIX type with VLAN */
7501 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
7502 break;
7503 /* LLC, SNAP etc are considered non-mergeable */
7504 default:
7505 return -1;
7506 }
7507
7508 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
7509 ip_len = (u8)((*ip)->ihl);
7510 ip_len <<= 2;
7511 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
7512
7513 return 0;
7514}
7515
1ee6dd77 7516static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 7517 struct tcphdr *tcp)
7518{
7519 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7520 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
7521 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
7522 return -1;
7523 return 0;
7524}
7525
7526static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
7527{
7528 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
7529}
7530
1ee6dd77 7531static void initiate_new_session(struct lro *lro, u8 *l2h,
7d3d0439
RA		 7532 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
7533{
7534 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7535 lro->l2h = l2h;
7536 lro->iph = ip;
7537 lro->tcph = tcp;
7538 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
7539 lro->tcp_ack = ntohl(tcp->ack_seq);
7540 lro->sg_num = 1;
7541 lro->total_len = ntohs(ip->tot_len);
7542 lro->frags_len = 0;
6aa20a22 7543 /*
7d3d0439
RA		 7544 * check if we saw TCP timestamp. Other consistency checks have
7545 * already been done.
7546 */
7547 if (tcp->doff == 8) {
7548 u32 *ptr;
7549 ptr = (u32 *)(tcp+1);
7550 lro->saw_ts = 1;
7551 lro->cur_tsval = *(ptr+1);
7552 lro->cur_tsecr = *(ptr+2);
7553 }
7554 lro->in_use = 1;
7555}
7556
1ee6dd77 7557static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 7558{
7559 struct iphdr *ip = lro->iph;
7560 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 7561 __sum16 nchk;
1ee6dd77 7562 struct stat_block *statinfo = sp->mac_control.stats_info;
7d3d0439
RA		 7563 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7564
7565 /* Update L3 header */
7566 ip->tot_len = htons(lro->total_len);
7567 ip->check = 0;
7568 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
7569 ip->check = nchk;
7570
7571 /* Update L4 header */
7572 tcp->ack_seq = lro->tcp_ack;
7573 tcp->window = lro->window;
7574
7575 /* Update tsecr field if this session has timestamps enabled */
7576 if (lro->saw_ts) {
7577 u32 *ptr = (u32 *)(tcp + 1);
7578 *(ptr+2) = lro->cur_tsecr;
7579 }
7580
7581 /* Update counters required for calculation of
7582 * average no. of packets aggregated.
7583 */
7584 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
7585 statinfo->sw_stat.num_aggregations++;
7586}
7587
1ee6dd77 7588static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 7589 struct tcphdr *tcp, u32 l4_pyld)
7590{
7591 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7592 lro->total_len += l4_pyld;
7593 lro->frags_len += l4_pyld;
7594 lro->tcp_next_seq += l4_pyld;
7595 lro->sg_num++;
7596
7597 /* Update ack seq no. and window ad(from this pkt) in LRO object */
7598 lro->tcp_ack = tcp->ack_seq;
7599 lro->window = tcp->window;
6aa20a22 7600
7d3d0439
RA		 7601 if (lro->saw_ts) {
7602 u32 *ptr;
7603 /* Update tsecr and tsval from this packet */
7604 ptr = (u32 *) (tcp + 1);
6aa20a22 7605 lro->cur_tsval = *(ptr + 1);
7d3d0439
RA		 7606 lro->cur_tsecr = *(ptr + 2);
7607 }
7608}
7609
1ee6dd77 7610static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 7611 struct tcphdr *tcp, u32 tcp_pyld_len)
7612{
7d3d0439
RA		 7613 u8 *ptr;
7614
79dc1901
AM		 7615 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
7616
7d3d0439
RA		 7617 if (!tcp_pyld_len) {
7618 /* Runt frame or a pure ack */
7619 return -1;
7620 }
7621
7622 if (ip->ihl != 5) /* IP has options */
7623 return -1;
7624
75c30b13
AR		 7625 /* If we see CE codepoint in IP header, packet is not mergeable */
7626 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
7627 return -1;
7628
7629 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 7630 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 7631 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 7632 /*
7633 * Currently recognize only the ack control word and
7634 * any other control field being set would result in
7635 * flushing the LRO session
7636 */
7637 return -1;
7638 }
7639
6aa20a22 7640 /*
7d3d0439
RA		 7641 * Allow only one TCP timestamp option. Don't aggregate if
7642 * any other options are detected.
7643 */
7644 if (tcp->doff != 5 && tcp->doff != 8)
7645 return -1;
7646
7647 if (tcp->doff == 8) {
6aa20a22 7648 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 7649 while (*ptr == TCPOPT_NOP)
7650 ptr++;
7651 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
7652 return -1;
7653
7654 /* Ensure timestamp value increases monotonically */
7655 if (l_lro)
7656 if (l_lro->cur_tsval > *((u32 *)(ptr+2)))
7657 return -1;
7658
7659 /* timestamp echo reply should be non-zero */
6aa20a22 7660 if (*((u32 *)(ptr+6)) == 0)
7d3d0439
RA		 7661 return -1;
7662 }
7663
7664 return 0;
7665}
7666
7667static int
1ee6dd77
RB		 7668s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
7669 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 7670{
7671 struct iphdr *ip;
7672 struct tcphdr *tcph;
7673 int ret = 0, i;
7674
7675 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
7676 rxdp))) {
7677 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
7678 ip->saddr, ip->daddr);
7679 } else {
7680 return ret;
7681 }
7682
7683 tcph = (struct tcphdr *)*tcp;
7684 *tcp_len = get_l4_pyld_length(ip, tcph);
7685 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 7686 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 7687 if (l_lro->in_use) {
7688 if (check_for_socket_match(l_lro, ip, tcph))
7689 continue;
7690 /* Sock pair matched */
7691 *lro = l_lro;
7692
7693 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
7694 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
7695 "0x%x, actual 0x%x\n", __FUNCTION__,
7696 (*lro)->tcp_next_seq,
7697 ntohl(tcph->seq));
7698
7699 sp->mac_control.stats_info->
7700 sw_stat.outof_sequence_pkts++;
7701 ret = 2;
7702 break;
7703 }
7704
7705 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
7706 ret = 1; /* Aggregate */
7707 else
7708 ret = 2; /* Flush both */
7709 break;
7710 }
7711 }
7712
7713 if (ret == 0) {
7714 /* Before searching for available LRO objects,
7715 * check if the pkt is L3/L4 aggregatable. If not
7716 * don't create new LRO session. Just send this
7717 * packet up.
7718 */
7719 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
7720 return 5;
7721 }
7722
7723 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 7724 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 7725 if (!(l_lro->in_use)) {
7726 *lro = l_lro;
7727 ret = 3; /* Begin anew */
7728 break;
7729 }
7730 }
7731 }
7732
7733 if (ret == 0) { /* sessions exceeded */
7734 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
7735 __FUNCTION__);
7736 *lro = NULL;
7737 return ret;
7738 }
7739
7740 switch (ret) {
7741 case 3:
7742 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
7743 break;
7744 case 2:
7745 update_L3L4_header(sp, *lro);
7746 break;
7747 case 1:
7748 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
7749 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
7750 update_L3L4_header(sp, *lro);
7751 ret = 4; /* Flush the LRO */
7752 }
7753 break;
7754 default:
7755 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
7756 __FUNCTION__);
7757 break;
7758 }
7759
7760 return ret;
7761}
7762
1ee6dd77 7763static void clear_lro_session(struct lro *lro)
7d3d0439 7764{
1ee6dd77 7765 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 7766
7767 memset(lro, 0, lro_struct_size);
7768}
7769
7770static void queue_rx_frame(struct sk_buff *skb)
7771{
7772 struct net_device *dev = skb->dev;
7773
7774 skb->protocol = eth_type_trans(skb, dev);
db874e65
SS		 7775 if (napi)
7776 netif_receive_skb(skb);
7777 else
7778 netif_rx(skb);
7d3d0439
RA		 7779}
7780
1ee6dd77
RB		 7781static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
7782 struct sk_buff *skb,
7d3d0439
RA		 7783 u32 tcp_len)
7784{
75c30b13 7785 struct sk_buff *first = lro->parent;
7d3d0439
RA		 7786
7787 first->len += tcp_len;
7788 first->data_len = lro->frags_len;
7789 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 7790 if (skb_shinfo(first)->frag_list)
7791 lro->last_frag->next = skb;
7d3d0439
RA		 7792 else
7793 skb_shinfo(first)->frag_list = skb;
372cc597 7794 first->truesize += skb->truesize;
75c30b13 7795 lro->last_frag = skb;
7d3d0439
RA		 7796 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
7797 return;
7798}
d796fdb7
LV		 7799
7800/**
7801 * s2io_io_error_detected - called when PCI error is detected
7802 * @pdev: Pointer to PCI device
8453d43f 7803 * @state: The current pci connection state
d796fdb7
LV		 7804 *
7805 * This function is called after a PCI bus error affecting
7806 * this device has been detected.
7807 */
7808static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
7809 pci_channel_state_t state)
7810{
7811 struct net_device *netdev = pci_get_drvdata(pdev);
7812 struct s2io_nic *sp = netdev->priv;
7813
7814 netif_device_detach(netdev);
7815
7816 if (netif_running(netdev)) {
7817 /* Bring down the card, while avoiding PCI I/O */
7818 do_s2io_card_down(sp, 0);
d796fdb7
LV		 7819 }
7820 pci_disable_device(pdev);
7821
7822 return PCI_ERS_RESULT_NEED_RESET;
7823}
7824
7825/**
7826 * s2io_io_slot_reset - called after the pci bus has been reset.
7827 * @pdev: Pointer to PCI device
7828 *
7829 * Restart the card from scratch, as if from a cold-boot.
7830 * At this point, the card has exprienced a hard reset,
7831 * followed by fixups by BIOS, and has its config space
7832 * set up identically to what it was at cold boot.
7833 */
7834static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
7835{
7836 struct net_device *netdev = pci_get_drvdata(pdev);
7837 struct s2io_nic *sp = netdev->priv;
7838
7839 if (pci_enable_device(pdev)) {
7840 printk(KERN_ERR "s2io: "
7841 "Cannot re-enable PCI device after reset.\n");
7842 return PCI_ERS_RESULT_DISCONNECT;
7843 }
7844
7845 pci_set_master(pdev);
7846 s2io_reset(sp);
7847
7848 return PCI_ERS_RESULT_RECOVERED;
7849}
7850
7851/**
7852 * s2io_io_resume - called when traffic can start flowing again.
7853 * @pdev: Pointer to PCI device
7854 *
7855 * This callback is called when the error recovery driver tells
7856 * us that its OK to resume normal operation.
7857 */
7858static void s2io_io_resume(struct pci_dev *pdev)
7859{
7860 struct net_device *netdev = pci_get_drvdata(pdev);
7861 struct s2io_nic *sp = netdev->priv;
7862
7863 if (netif_running(netdev)) {
7864 if (s2io_card_up(sp)) {
7865 printk(KERN_ERR "s2io: "
7866 "Can't bring device back up after reset.\n");
7867 return;
7868 }
7869
7870 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
7871 s2io_card_down(sp);
7872 printk(KERN_ERR "s2io: "
7873 "Can't resetore mac addr after reset.\n");
7874 return;
7875 }
7876 }
7877
7878 netif_device_attach(netdev);
7879 netif_wake_queue(netdev);
7880}
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