]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/s2io.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
FIXED_PHY must depend on PHYLIB=y
[mirror_ubuntu-bionic-kernel.git] / drivers / net / s2io.c
CommitLineData
1da177e4 1/************************************************************************
776bd20f 2 * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
0c61ed5f 3 * Copyright(c) 2002-2007 Neterion Inc.
1da177e4
LT		 4
5 * This software may be used and distributed according to the terms of
6 * the GNU General Public License (GPL), incorporated herein by reference.
7 * Drivers based on or derived from this code fall under the GPL and must
8 * retain the authorship, copyright and license notice. This file is not
9 * a complete program and may only be used when the entire operating
10 * system is licensed under the GPL.
11 * See the file COPYING in this distribution for more information.
12 *
13 * Credits:
20346722
K		 14 * Jeff Garzik : For pointing out the improper error condition
15 * check in the s2io_xmit routine and also some
16 * issues in the Tx watch dog function. Also for
17 * patiently answering all those innumerable
1da177e4
LT		 18 * questions regaring the 2.6 porting issues.
19 * Stephen Hemminger : Providing proper 2.6 porting mechanism for some
20 * macros available only in 2.6 Kernel.
20346722 21 * Francois Romieu : For pointing out all code part that were
1da177e4 22 * deprecated and also styling related comments.
20346722 23 * Grant Grundler : For helping me get rid of some Architecture
1da177e4
LT		 24 * dependent code.
25 * Christopher Hellwig : Some more 2.6 specific issues in the driver.
20346722 26 *
1da177e4
LT		 27 * The module loadable parameters that are supported by the driver and a brief
28 * explaination of all the variables.
9dc737a7 29 *
20346722
K		 30 * rx_ring_num : This can be used to program the number of receive rings used
31 * in the driver.
9dc737a7
AR		 32 * rx_ring_sz: This defines the number of receive blocks each ring can have.
33 * This is also an array of size 8.
da6971d8 34 * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
6d517a27 35 * values are 1, 2.
1da177e4 36 * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
20346722 37 * tx_fifo_len: This too is an array of 8. Each element defines the number of
1da177e4 38 * Tx descriptors that can be associated with each corresponding FIFO.
9dc737a7 39 * intr_type: This defines the type of interrupt. The values can be 0(INTA),
8abc4d5b 40 * 2(MSI_X). Default value is '2(MSI_X)'
43b7c451 41 * lro_enable: Specifies whether to enable Large Receive Offload (LRO) or not.
9dc737a7
AR		 42 * Possible values '1' for enable '0' for disable. Default is '0'
43 * lro_max_pkts: This parameter defines maximum number of packets can be
44 * aggregated as a single large packet
926930b2
SS		 45 * napi: This parameter used to enable/disable NAPI (polling Rx)
46 * Possible values '1' for enable and '0' for disable. Default is '1'
47 * ufo: This parameter used to enable/disable UDP Fragmentation Offload(UFO)
48 * Possible values '1' for enable and '0' for disable. Default is '0'
49 * vlan_tag_strip: This can be used to enable or disable vlan stripping.
50 * Possible values '1' for enable , '0' for disable.
51 * Default is '2' - which means disable in promisc mode
52 * and enable in non-promiscuous mode.
1da177e4
LT		 53 ************************************************************************/
54
1da177e4
LT		 55#include <linux/module.h>
56#include <linux/types.h>
57#include <linux/errno.h>
58#include <linux/ioport.h>
59#include <linux/pci.h>
1e7f0bd8 60#include <linux/dma-mapping.h>
1da177e4
LT		 61#include <linux/kernel.h>
62#include <linux/netdevice.h>
63#include <linux/etherdevice.h>
64#include <linux/skbuff.h>
65#include <linux/init.h>
66#include <linux/delay.h>
67#include <linux/stddef.h>
68#include <linux/ioctl.h>
69#include <linux/timex.h>
1da177e4 70#include <linux/ethtool.h>
1da177e4 71#include <linux/workqueue.h>
be3a6b02 72#include <linux/if_vlan.h>
7d3d0439
RA		 73#include <linux/ip.h>
74#include <linux/tcp.h>
75#include <net/tcp.h>
1da177e4 76
1da177e4
LT		 77#include <asm/system.h>
78#include <asm/uaccess.h>
20346722 79#include <asm/io.h>
fe931395 80#include <asm/div64.h>
330ce0de 81#include <asm/irq.h>
1da177e4
LT		 82
83/* local include */
84#include "s2io.h"
85#include "s2io-regs.h"
86
b7c5678f 87#define DRV_VERSION "2.0.26.15-2"
6c1792f4 88
1da177e4 89/* S2io Driver name & version. */
20346722 90static char s2io_driver_name[] = "Neterion";
6c1792f4 91static char s2io_driver_version[] = DRV_VERSION;
1da177e4 92
6d517a27
VP		 93static int rxd_size[2] = {32,48};
94static int rxd_count[2] = {127,85};
da6971d8 95
1ee6dd77 96static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
5e25b9dd
K		 97{
98 int ret;
99
100 ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
101 (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
102
103 return ret;
104}
105
20346722 106/*
1da177e4
LT		 107 * Cards with following subsystem_id have a link state indication
108 * problem, 600B, 600C, 600D, 640B, 640C and 640D.
109 * macro below identifies these cards given the subsystem_id.
110 */
541ae68f
K		 111#define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid) \
112 (dev_type == XFRAME_I_DEVICE) ? \
113 ((((subid >= 0x600B) && (subid <= 0x600D)) || \
114 ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
1da177e4
LT		 115
116#define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
117 ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
118#define TASKLET_IN_USE test_and_set_bit(0, (&sp->tasklet_status))
119#define PANIC 1
120#define LOW 2
1ee6dd77 121static inline int rx_buffer_level(struct s2io_nic * sp, int rxb_size, int ring)
1da177e4 122{
1ee6dd77 123 struct mac_info *mac_control;
20346722
K		 124
125 mac_control = &sp->mac_control;
863c11a9
AR		 126 if (rxb_size <= rxd_count[sp->rxd_mode])
127 return PANIC;
128 else if ((mac_control->rings[ring].pkt_cnt - rxb_size) > 16)
129 return LOW;
130 return 0;
1da177e4
LT		 131}
132
92b84437
SS		 133static inline int is_s2io_card_up(const struct s2io_nic * sp)
134{
135 return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
136}
137
1da177e4
LT		 138/* Ethtool related variables and Macros. */
139static char s2io_gstrings[][ETH_GSTRING_LEN] = {
140 "Register test\t(offline)",
141 "Eeprom test\t(offline)",
142 "Link test\t(online)",
143 "RLDRAM test\t(offline)",
144 "BIST Test\t(offline)"
145};
146
fa1f0cb3 147static char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
1da177e4
LT		 148 {"tmac_frms"},
149 {"tmac_data_octets"},
150 {"tmac_drop_frms"},
151 {"tmac_mcst_frms"},
152 {"tmac_bcst_frms"},
153 {"tmac_pause_ctrl_frms"},
bd1034f0
AR		 154 {"tmac_ttl_octets"},
155 {"tmac_ucst_frms"},
156 {"tmac_nucst_frms"},
1da177e4 157 {"tmac_any_err_frms"},
bd1034f0 158 {"tmac_ttl_less_fb_octets"},
1da177e4
LT		 159 {"tmac_vld_ip_octets"},
160 {"tmac_vld_ip"},
161 {"tmac_drop_ip"},
162 {"tmac_icmp"},
163 {"tmac_rst_tcp"},
164 {"tmac_tcp"},
165 {"tmac_udp"},
166 {"rmac_vld_frms"},
167 {"rmac_data_octets"},
168 {"rmac_fcs_err_frms"},
169 {"rmac_drop_frms"},
170 {"rmac_vld_mcst_frms"},
171 {"rmac_vld_bcst_frms"},
172 {"rmac_in_rng_len_err_frms"},
bd1034f0 173 {"rmac_out_rng_len_err_frms"},
1da177e4
LT		 174 {"rmac_long_frms"},
175 {"rmac_pause_ctrl_frms"},
bd1034f0
AR		 176 {"rmac_unsup_ctrl_frms"},
177 {"rmac_ttl_octets"},
178 {"rmac_accepted_ucst_frms"},
179 {"rmac_accepted_nucst_frms"},
1da177e4 180 {"rmac_discarded_frms"},
bd1034f0
AR		 181 {"rmac_drop_events"},
182 {"rmac_ttl_less_fb_octets"},
183 {"rmac_ttl_frms"},
1da177e4
LT		 184 {"rmac_usized_frms"},
185 {"rmac_osized_frms"},
186 {"rmac_frag_frms"},
187 {"rmac_jabber_frms"},
bd1034f0
AR		 188 {"rmac_ttl_64_frms"},
189 {"rmac_ttl_65_127_frms"},
190 {"rmac_ttl_128_255_frms"},
191 {"rmac_ttl_256_511_frms"},
192 {"rmac_ttl_512_1023_frms"},
193 {"rmac_ttl_1024_1518_frms"},
1da177e4
LT		 194 {"rmac_ip"},
195 {"rmac_ip_octets"},
196 {"rmac_hdr_err_ip"},
197 {"rmac_drop_ip"},
198 {"rmac_icmp"},
199 {"rmac_tcp"},
200 {"rmac_udp"},
201 {"rmac_err_drp_udp"},
bd1034f0
AR		 202 {"rmac_xgmii_err_sym"},
203 {"rmac_frms_q0"},
204 {"rmac_frms_q1"},
205 {"rmac_frms_q2"},
206 {"rmac_frms_q3"},
207 {"rmac_frms_q4"},
208 {"rmac_frms_q5"},
209 {"rmac_frms_q6"},
210 {"rmac_frms_q7"},
211 {"rmac_full_q0"},
212 {"rmac_full_q1"},
213 {"rmac_full_q2"},
214 {"rmac_full_q3"},
215 {"rmac_full_q4"},
216 {"rmac_full_q5"},
217 {"rmac_full_q6"},
218 {"rmac_full_q7"},
1da177e4 219 {"rmac_pause_cnt"},
bd1034f0
AR		 220 {"rmac_xgmii_data_err_cnt"},
221 {"rmac_xgmii_ctrl_err_cnt"},
1da177e4
LT		 222 {"rmac_accepted_ip"},
223 {"rmac_err_tcp"},
bd1034f0
AR		 224 {"rd_req_cnt"},
225 {"new_rd_req_cnt"},
226 {"new_rd_req_rtry_cnt"},
227 {"rd_rtry_cnt"},
228 {"wr_rtry_rd_ack_cnt"},
229 {"wr_req_cnt"},
230 {"new_wr_req_cnt"},
231 {"new_wr_req_rtry_cnt"},
232 {"wr_rtry_cnt"},
233 {"wr_disc_cnt"},
234 {"rd_rtry_wr_ack_cnt"},
235 {"txp_wr_cnt"},
236 {"txd_rd_cnt"},
237 {"txd_wr_cnt"},
238 {"rxd_rd_cnt"},
239 {"rxd_wr_cnt"},
240 {"txf_rd_cnt"},
fa1f0cb3
SS		 241 {"rxf_wr_cnt"}
242};
243
244static char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
bd1034f0
AR		 245 {"rmac_ttl_1519_4095_frms"},
246 {"rmac_ttl_4096_8191_frms"},
247 {"rmac_ttl_8192_max_frms"},
248 {"rmac_ttl_gt_max_frms"},
249 {"rmac_osized_alt_frms"},
250 {"rmac_jabber_alt_frms"},
251 {"rmac_gt_max_alt_frms"},
252 {"rmac_vlan_frms"},
253 {"rmac_len_discard"},
254 {"rmac_fcs_discard"},
255 {"rmac_pf_discard"},
256 {"rmac_da_discard"},
257 {"rmac_red_discard"},
258 {"rmac_rts_discard"},
259 {"rmac_ingm_full_discard"},
fa1f0cb3
SS		 260 {"link_fault_cnt"}
261};
262
263static char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
7ba013ac
K		 264 {"\n DRIVER STATISTICS"},
265 {"single_bit_ecc_errs"},
266 {"double_bit_ecc_errs"},
bd1034f0
AR		 267 {"parity_err_cnt"},
268 {"serious_err_cnt"},
269 {"soft_reset_cnt"},
270 {"fifo_full_cnt"},
8116f3cf
SS		 271 {"ring_0_full_cnt"},
272 {"ring_1_full_cnt"},
273 {"ring_2_full_cnt"},
274 {"ring_3_full_cnt"},
275 {"ring_4_full_cnt"},
276 {"ring_5_full_cnt"},
277 {"ring_6_full_cnt"},
278 {"ring_7_full_cnt"},
43b7c451
SH		 279 {"alarm_transceiver_temp_high"},
280 {"alarm_transceiver_temp_low"},
281 {"alarm_laser_bias_current_high"},
282 {"alarm_laser_bias_current_low"},
283 {"alarm_laser_output_power_high"},
284 {"alarm_laser_output_power_low"},
285 {"warn_transceiver_temp_high"},
286 {"warn_transceiver_temp_low"},
287 {"warn_laser_bias_current_high"},
288 {"warn_laser_bias_current_low"},
289 {"warn_laser_output_power_high"},
290 {"warn_laser_output_power_low"},
291 {"lro_aggregated_pkts"},
292 {"lro_flush_both_count"},
293 {"lro_out_of_sequence_pkts"},
294 {"lro_flush_due_to_max_pkts"},
295 {"lro_avg_aggr_pkts"},
296 {"mem_alloc_fail_cnt"},
297 {"pci_map_fail_cnt"},
298 {"watchdog_timer_cnt"},
299 {"mem_allocated"},
300 {"mem_freed"},
301 {"link_up_cnt"},
302 {"link_down_cnt"},
303 {"link_up_time"},
304 {"link_down_time"},
305 {"tx_tcode_buf_abort_cnt"},
306 {"tx_tcode_desc_abort_cnt"},
307 {"tx_tcode_parity_err_cnt"},
308 {"tx_tcode_link_loss_cnt"},
309 {"tx_tcode_list_proc_err_cnt"},
310 {"rx_tcode_parity_err_cnt"},
311 {"rx_tcode_abort_cnt"},
312 {"rx_tcode_parity_abort_cnt"},
313 {"rx_tcode_rda_fail_cnt"},
314 {"rx_tcode_unkn_prot_cnt"},
315 {"rx_tcode_fcs_err_cnt"},
316 {"rx_tcode_buf_size_err_cnt"},
317 {"rx_tcode_rxd_corrupt_cnt"},
318 {"rx_tcode_unkn_err_cnt"},
8116f3cf
SS		 319 {"tda_err_cnt"},
320 {"pfc_err_cnt"},
321 {"pcc_err_cnt"},
322 {"tti_err_cnt"},
323 {"tpa_err_cnt"},
324 {"sm_err_cnt"},
325 {"lso_err_cnt"},
326 {"mac_tmac_err_cnt"},
327 {"mac_rmac_err_cnt"},
328 {"xgxs_txgxs_err_cnt"},
329 {"xgxs_rxgxs_err_cnt"},
330 {"rc_err_cnt"},
331 {"prc_pcix_err_cnt"},
332 {"rpa_err_cnt"},
333 {"rda_err_cnt"},
334 {"rti_err_cnt"},
335 {"mc_err_cnt"}
1da177e4
LT		 336};
337
4c3616cd
AMR		 338#define S2IO_XENA_STAT_LEN ARRAY_SIZE(ethtool_xena_stats_keys)
339#define S2IO_ENHANCED_STAT_LEN ARRAY_SIZE(ethtool_enhanced_stats_keys)
340#define S2IO_DRIVER_STAT_LEN ARRAY_SIZE(ethtool_driver_stats_keys)
fa1f0cb3
SS		 341
342#define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN )
343#define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN )
344
345#define XFRAME_I_STAT_STRINGS_LEN ( XFRAME_I_STAT_LEN * ETH_GSTRING_LEN )
346#define XFRAME_II_STAT_STRINGS_LEN ( XFRAME_II_STAT_LEN * ETH_GSTRING_LEN )
1da177e4 347
4c3616cd 348#define S2IO_TEST_LEN ARRAY_SIZE(s2io_gstrings)
1da177e4
LT		 349#define S2IO_STRINGS_LEN S2IO_TEST_LEN * ETH_GSTRING_LEN
350
25fff88e
K		 351#define S2IO_TIMER_CONF(timer, handle, arg, exp) \
352 init_timer(&timer); \
353 timer.function = handle; \
354 timer.data = (unsigned long) arg; \
355 mod_timer(&timer, (jiffies + exp)) \
356
2fd37688
SS		 357/* copy mac addr to def_mac_addr array */
358static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
359{
360 sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
361 sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
362 sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
363 sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
364 sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
365 sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
366}
be3a6b02
K		 367/* Add the vlan */
368static void s2io_vlan_rx_register(struct net_device *dev,
369 struct vlan_group *grp)
370{
2fda096d 371 int i;
1ee6dd77 372 struct s2io_nic *nic = dev->priv;
2fda096d
SR		 373 unsigned long flags[MAX_TX_FIFOS];
374 struct mac_info *mac_control = &nic->mac_control;
375 struct config_param *config = &nic->config;
376
377 for (i = 0; i < config->tx_fifo_num; i++)
378 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags[i]);
be3a6b02 379
be3a6b02 380 nic->vlgrp = grp;
2fda096d
SR		 381 for (i = config->tx_fifo_num - 1; i >= 0; i--)
382 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock,
383 flags[i]);
be3a6b02
K		 384}
385
926930b2 386/* A flag indicating whether 'RX_PA_CFG_STRIP_VLAN_TAG' bit is set or not */
7b490343 387static int vlan_strip_flag;
926930b2 388
20346722 389/*
1da177e4
LT		 390 * Constants to be programmed into the Xena's registers, to configure
391 * the XAUI.
392 */
393
1da177e4 394#define END_SIGN 0x0
f71e1309 395static const u64 herc_act_dtx_cfg[] = {
541ae68f 396 /* Set address */
e960fc5c 397 0x8000051536750000ULL, 0x80000515367500E0ULL,
541ae68f 398 /* Write data */
e960fc5c 399 0x8000051536750004ULL, 0x80000515367500E4ULL,
541ae68f
K		 400 /* Set address */
401 0x80010515003F0000ULL, 0x80010515003F00E0ULL,
402 /* Write data */
403 0x80010515003F0004ULL, 0x80010515003F00E4ULL,
404 /* Set address */
e960fc5c 405 0x801205150D440000ULL, 0x801205150D4400E0ULL,
406 /* Write data */
407 0x801205150D440004ULL, 0x801205150D4400E4ULL,
408 /* Set address */
541ae68f
K		 409 0x80020515F2100000ULL, 0x80020515F21000E0ULL,
410 /* Write data */
411 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
412 /* Done */
413 END_SIGN
414};
415
f71e1309 416static const u64 xena_dtx_cfg[] = {
c92ca04b 417 /* Set address */
1da177e4 418 0x8000051500000000ULL, 0x80000515000000E0ULL,
c92ca04b
AR		 419 /* Write data */
420 0x80000515D9350004ULL, 0x80000515D93500E4ULL,
421 /* Set address */
422 0x8001051500000000ULL, 0x80010515000000E0ULL,
423 /* Write data */
424 0x80010515001E0004ULL, 0x80010515001E00E4ULL,
425 /* Set address */
1da177e4 426 0x8002051500000000ULL, 0x80020515000000E0ULL,
c92ca04b
AR		 427 /* Write data */
428 0x80020515F2100004ULL, 0x80020515F21000E4ULL,
1da177e4
LT		 429 END_SIGN
430};
431
20346722 432/*
1da177e4
LT		 433 * Constants for Fixing the MacAddress problem seen mostly on
434 * Alpha machines.
435 */
f71e1309 436static const u64 fix_mac[] = {
1da177e4
LT		 437 0x0060000000000000ULL, 0x0060600000000000ULL,
438 0x0040600000000000ULL, 0x0000600000000000ULL,
439 0x0020600000000000ULL, 0x0060600000000000ULL,
440 0x0020600000000000ULL, 0x0060600000000000ULL,
441 0x0020600000000000ULL, 0x0060600000000000ULL,
442 0x0020600000000000ULL, 0x0060600000000000ULL,
443 0x0020600000000000ULL, 0x0060600000000000ULL,
444 0x0020600000000000ULL, 0x0060600000000000ULL,
445 0x0020600000000000ULL, 0x0060600000000000ULL,
446 0x0020600000000000ULL, 0x0060600000000000ULL,
447 0x0020600000000000ULL, 0x0060600000000000ULL,
448 0x0020600000000000ULL, 0x0060600000000000ULL,
449 0x0020600000000000ULL, 0x0000600000000000ULL,
450 0x0040600000000000ULL, 0x0060600000000000ULL,
451 END_SIGN
452};
453
b41477f3
AR		 454MODULE_LICENSE("GPL");
455MODULE_VERSION(DRV_VERSION);
456
457
1da177e4 458/* Module Loadable parameters. */
b41477f3
AR		 459S2IO_PARM_INT(tx_fifo_num, 1);
460S2IO_PARM_INT(rx_ring_num, 1);
461
462
463S2IO_PARM_INT(rx_ring_mode, 1);
464S2IO_PARM_INT(use_continuous_tx_intrs, 1);
465S2IO_PARM_INT(rmac_pause_time, 0x100);
466S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
467S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
468S2IO_PARM_INT(shared_splits, 0);
469S2IO_PARM_INT(tmac_util_period, 5);
470S2IO_PARM_INT(rmac_util_period, 5);
b41477f3 471S2IO_PARM_INT(l3l4hdr_size, 128);
303bcb4b 472/* Frequency of Rx desc syncs expressed as power of 2 */
b41477f3 473S2IO_PARM_INT(rxsync_frequency, 3);
eccb8628 474/* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
8abc4d5b 475S2IO_PARM_INT(intr_type, 2);
7d3d0439 476/* Large receive offload feature */
43b7c451
SH		 477static unsigned int lro_enable;
478module_param_named(lro, lro_enable, uint, 0);
479
7d3d0439
RA		 480/* Max pkts to be aggregated by LRO at one time. If not specified,
481 * aggregation happens until we hit max IP pkt size(64K)
482 */
b41477f3 483S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
b41477f3 484S2IO_PARM_INT(indicate_max_pkts, 0);
db874e65
SS		 485
486S2IO_PARM_INT(napi, 1);
487S2IO_PARM_INT(ufo, 0);
926930b2 488S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
b41477f3
AR		 489
490static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
491 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
492static unsigned int rx_ring_sz[MAX_RX_RINGS] =
493 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
494static unsigned int rts_frm_len[MAX_RX_RINGS] =
495 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
496
497module_param_array(tx_fifo_len, uint, NULL, 0);
498module_param_array(rx_ring_sz, uint, NULL, 0);
499module_param_array(rts_frm_len, uint, NULL, 0);
1da177e4 500
20346722 501/*
1da177e4 502 * S2IO device table.
20346722 503 * This table lists all the devices that this driver supports.
1da177e4
LT		 504 */
505static struct pci_device_id s2io_tbl[] __devinitdata = {
506 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
507 PCI_ANY_ID, PCI_ANY_ID},
508 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
509 PCI_ANY_ID, PCI_ANY_ID},
510 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
20346722
K		 511 PCI_ANY_ID, PCI_ANY_ID},
512 {PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
513 PCI_ANY_ID, PCI_ANY_ID},
1da177e4
LT		 514 {0,}
515};
516
517MODULE_DEVICE_TABLE(pci, s2io_tbl);
518
d796fdb7
LV		 519static struct pci_error_handlers s2io_err_handler = {
520 .error_detected = s2io_io_error_detected,
521 .slot_reset = s2io_io_slot_reset,
522 .resume = s2io_io_resume,
523};
524
1da177e4
LT		 525static struct pci_driver s2io_driver = {
526 .name = "S2IO",
527 .id_table = s2io_tbl,
528 .probe = s2io_init_nic,
529 .remove = __devexit_p(s2io_rem_nic),
d796fdb7 530 .err_handler = &s2io_err_handler,
1da177e4
LT		 531};
532
533/* A simplifier macro used both by init and free shared_mem Fns(). */
534#define TXD_MEM_PAGE_CNT(len, per_each) ((len+per_each - 1) / per_each)
535
536/**
537 * init_shared_mem - Allocation and Initialization of Memory
538 * @nic: Device private variable.
20346722
K		 539 * Description: The function allocates all the memory areas shared
540 * between the NIC and the driver. This includes Tx descriptors,
1da177e4
LT		 541 * Rx descriptors and the statistics block.
542 */
543
544static int init_shared_mem(struct s2io_nic *nic)
545{
546 u32 size;
547 void *tmp_v_addr, *tmp_v_addr_next;
548 dma_addr_t tmp_p_addr, tmp_p_addr_next;
1ee6dd77 549 struct RxD_block *pre_rxd_blk = NULL;
372cc597 550 int i, j, blk_cnt;
1da177e4
LT		 551 int lst_size, lst_per_page;
552 struct net_device *dev = nic->dev;
8ae418cf 553 unsigned long tmp;
1ee6dd77 554 struct buffAdd *ba;
1da177e4 555
1ee6dd77 556 struct mac_info *mac_control;
1da177e4 557 struct config_param *config;
491976b2 558 unsigned long long mem_allocated = 0;
1da177e4
LT		 559
560 mac_control = &nic->mac_control;
561 config = &nic->config;
562
563
564 /* Allocation and initialization of TXDLs in FIOFs */
565 size = 0;
566 for (i = 0; i < config->tx_fifo_num; i++) {
567 size += config->tx_cfg[i].fifo_len;
568 }
569 if (size > MAX_AVAILABLE_TXDS) {
b41477f3 570 DBG_PRINT(ERR_DBG, "s2io: Requested TxDs too high, ");
0b1f7ebe 571 DBG_PRINT(ERR_DBG, "Requested: %d, max supported: 8192\n", size);
b41477f3 572 return -EINVAL;
1da177e4
LT		 573 }
574
2fda096d
SR		 575 size = 0;
576 for (i = 0; i < config->tx_fifo_num; i++) {
577 size = config->tx_cfg[i].fifo_len;
578 /*
579 * Legal values are from 2 to 8192
580 */
581 if (size < 2) {
582 DBG_PRINT(ERR_DBG, "s2io: Invalid fifo len (%d)", size);
583 DBG_PRINT(ERR_DBG, "for fifo %d\n", i);
584 DBG_PRINT(ERR_DBG, "s2io: Legal values for fifo len"
585 "are 2 to 8192\n");
586 return -EINVAL;
587 }
588 }
589
1ee6dd77 590 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 591 lst_per_page = PAGE_SIZE / lst_size;
592
593 for (i = 0; i < config->tx_fifo_num; i++) {
594 int fifo_len = config->tx_cfg[i].fifo_len;
1ee6dd77 595 int list_holder_size = fifo_len * sizeof(struct list_info_hold);
bd684e43 596 mac_control->fifos[i].list_info = kzalloc(list_holder_size,
20346722
K		 597 GFP_KERNEL);
598 if (!mac_control->fifos[i].list_info) {
0c61ed5f 599 DBG_PRINT(INFO_DBG,
1da177e4
LT		 600 "Malloc failed for list_info\n");
601 return -ENOMEM;
602 }
491976b2 603 mem_allocated += list_holder_size;
1da177e4
LT		 604 }
605 for (i = 0; i < config->tx_fifo_num; i++) {
606 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
607 lst_per_page);
20346722
K		 608 mac_control->fifos[i].tx_curr_put_info.offset = 0;
609 mac_control->fifos[i].tx_curr_put_info.fifo_len =
1da177e4 610 config->tx_cfg[i].fifo_len - 1;
20346722
K		 611 mac_control->fifos[i].tx_curr_get_info.offset = 0;
612 mac_control->fifos[i].tx_curr_get_info.fifo_len =
1da177e4 613 config->tx_cfg[i].fifo_len - 1;
20346722
K		 614 mac_control->fifos[i].fifo_no = i;
615 mac_control->fifos[i].nic = nic;
fed5eccd 616 mac_control->fifos[i].max_txds = MAX_SKB_FRAGS + 2;
20346722 617
1da177e4
LT		 618 for (j = 0; j < page_num; j++) {
619 int k = 0;
620 dma_addr_t tmp_p;
621 void *tmp_v;
622 tmp_v = pci_alloc_consistent(nic->pdev,
623 PAGE_SIZE, &tmp_p);
624 if (!tmp_v) {
0c61ed5f 625 DBG_PRINT(INFO_DBG,
1da177e4 626 "pci_alloc_consistent ");
0c61ed5f 627 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
1da177e4
LT		 628 return -ENOMEM;
629 }
776bd20f 630 /* If we got a zero DMA address(can happen on
631 * certain platforms like PPC), reallocate.
632 * Store virtual address of page we don't want,
633 * to be freed later.
634 */
635 if (!tmp_p) {
636 mac_control->zerodma_virt_addr = tmp_v;
6aa20a22 637 DBG_PRINT(INIT_DBG,
776bd20f 638 "%s: Zero DMA address for TxDL. ", dev->name);
6aa20a22 639 DBG_PRINT(INIT_DBG,
6b4d617d 640 "Virtual address %p\n", tmp_v);
776bd20f 641 tmp_v = pci_alloc_consistent(nic->pdev,
642 PAGE_SIZE, &tmp_p);
643 if (!tmp_v) {
0c61ed5f 644 DBG_PRINT(INFO_DBG,
776bd20f 645 "pci_alloc_consistent ");
0c61ed5f 646 DBG_PRINT(INFO_DBG, "failed for TxDL\n");
776bd20f 647 return -ENOMEM;
648 }
491976b2 649 mem_allocated += PAGE_SIZE;
776bd20f 650 }
1da177e4
LT		 651 while (k < lst_per_page) {
652 int l = (j * lst_per_page) + k;
653 if (l == config->tx_cfg[i].fifo_len)
20346722
K		 654 break;
655 mac_control->fifos[i].list_info[l].list_virt_addr =
1da177e4 656 tmp_v + (k * lst_size);
20346722 657 mac_control->fifos[i].list_info[l].list_phy_addr =
1da177e4
LT		 658 tmp_p + (k * lst_size);
659 k++;
660 }
661 }
662 }
1da177e4 663
2fda096d
SR		 664 for (i = 0; i < config->tx_fifo_num; i++) {
665 size = config->tx_cfg[i].fifo_len;
666 mac_control->fifos[i].ufo_in_band_v
667 = kcalloc(size, sizeof(u64), GFP_KERNEL);
668 if (!mac_control->fifos[i].ufo_in_band_v)
669 return -ENOMEM;
670 mem_allocated += (size * sizeof(u64));
671 }
fed5eccd 672
1da177e4
LT		 673 /* Allocation and initialization of RXDs in Rings */
674 size = 0;
675 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 676 if (config->rx_cfg[i].num_rxd %
677 (rxd_count[nic->rxd_mode] + 1)) {
1da177e4
LT		 678 DBG_PRINT(ERR_DBG, "%s: RxD count of ", dev->name);
679 DBG_PRINT(ERR_DBG, "Ring%d is not a multiple of ",
680 i);
681 DBG_PRINT(ERR_DBG, "RxDs per Block");
682 return FAILURE;
683 }
684 size += config->rx_cfg[i].num_rxd;
20346722 685 mac_control->rings[i].block_count =
da6971d8
AR		 686 config->rx_cfg[i].num_rxd /
687 (rxd_count[nic->rxd_mode] + 1 );
688 mac_control->rings[i].pkt_cnt = config->rx_cfg[i].num_rxd -
689 mac_control->rings[i].block_count;
1da177e4 690 }
da6971d8 691 if (nic->rxd_mode == RXD_MODE_1)
1ee6dd77 692 size = (size * (sizeof(struct RxD1)));
da6971d8 693 else
1ee6dd77 694 size = (size * (sizeof(struct RxD3)));
1da177e4
LT		 695
696 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 697 mac_control->rings[i].rx_curr_get_info.block_index = 0;
698 mac_control->rings[i].rx_curr_get_info.offset = 0;
699 mac_control->rings[i].rx_curr_get_info.ring_len =
1da177e4 700 config->rx_cfg[i].num_rxd - 1;
20346722
K		 701 mac_control->rings[i].rx_curr_put_info.block_index = 0;
702 mac_control->rings[i].rx_curr_put_info.offset = 0;
703 mac_control->rings[i].rx_curr_put_info.ring_len =
1da177e4 704 config->rx_cfg[i].num_rxd - 1;
20346722
K		 705 mac_control->rings[i].nic = nic;
706 mac_control->rings[i].ring_no = i;
707
da6971d8
AR		 708 blk_cnt = config->rx_cfg[i].num_rxd /
709 (rxd_count[nic->rxd_mode] + 1);
1da177e4
LT		 710 /* Allocating all the Rx blocks */
711 for (j = 0; j < blk_cnt; j++) {
1ee6dd77 712 struct rx_block_info *rx_blocks;
da6971d8
AR		 713 int l;
714
715 rx_blocks = &mac_control->rings[i].rx_blocks[j];
716 size = SIZE_OF_BLOCK; //size is always page size
1da177e4
LT		 717 tmp_v_addr = pci_alloc_consistent(nic->pdev, size,
718 &tmp_p_addr);
719 if (tmp_v_addr == NULL) {
720 /*
20346722
K		 721 * In case of failure, free_shared_mem()
722 * is called, which should free any
723 * memory that was alloced till the
1da177e4
LT		 724 * failure happened.
725 */
da6971d8 726 rx_blocks->block_virt_addr = tmp_v_addr;
1da177e4
LT		 727 return -ENOMEM;
728 }
491976b2 729 mem_allocated += size;
1da177e4 730 memset(tmp_v_addr, 0, size);
da6971d8
AR		 731 rx_blocks->block_virt_addr = tmp_v_addr;
732 rx_blocks->block_dma_addr = tmp_p_addr;
1ee6dd77 733 rx_blocks->rxds = kmalloc(sizeof(struct rxd_info)*
da6971d8
AR		 734 rxd_count[nic->rxd_mode],
735 GFP_KERNEL);
372cc597
SS		 736 if (!rx_blocks->rxds)
737 return -ENOMEM;
8a4bdbaa 738 mem_allocated +=
491976b2 739 (sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
da6971d8
AR		 740 for (l=0; l<rxd_count[nic->rxd_mode];l++) {
741 rx_blocks->rxds[l].virt_addr =
742 rx_blocks->block_virt_addr +
743 (rxd_size[nic->rxd_mode] * l);
744 rx_blocks->rxds[l].dma_addr =
745 rx_blocks->block_dma_addr +
746 (rxd_size[nic->rxd_mode] * l);
747 }
1da177e4
LT		 748 }
749 /* Interlinking all Rx Blocks */
750 for (j = 0; j < blk_cnt; j++) {
20346722
K		 751 tmp_v_addr =
752 mac_control->rings[i].rx_blocks[j].block_virt_addr;
1da177e4 753 tmp_v_addr_next =
20346722 754 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4 755 blk_cnt].block_virt_addr;
20346722
K		 756 tmp_p_addr =
757 mac_control->rings[i].rx_blocks[j].block_dma_addr;
1da177e4 758 tmp_p_addr_next =
20346722 759 mac_control->rings[i].rx_blocks[(j + 1) %
1da177e4
LT		 760 blk_cnt].block_dma_addr;
761
1ee6dd77 762 pre_rxd_blk = (struct RxD_block *) tmp_v_addr;
1da177e4
LT		 763 pre_rxd_blk->reserved_2_pNext_RxD_block =
764 (unsigned long) tmp_v_addr_next;
1da177e4
LT		 765 pre_rxd_blk->pNext_RxD_Blk_physical =
766 (u64) tmp_p_addr_next;
767 }
768 }
6d517a27 769 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 770 /*
771 * Allocation of Storages for buffer addresses in 2BUFF mode
772 * and the buffers as well.
773 */
774 for (i = 0; i < config->rx_ring_num; i++) {
775 blk_cnt = config->rx_cfg[i].num_rxd /
776 (rxd_count[nic->rxd_mode]+ 1);
777 mac_control->rings[i].ba =
1ee6dd77 778 kmalloc((sizeof(struct buffAdd *) * blk_cnt),
1da177e4 779 GFP_KERNEL);
da6971d8 780 if (!mac_control->rings[i].ba)
1da177e4 781 return -ENOMEM;
491976b2 782 mem_allocated +=(sizeof(struct buffAdd *) * blk_cnt);
da6971d8
AR		 783 for (j = 0; j < blk_cnt; j++) {
784 int k = 0;
785 mac_control->rings[i].ba[j] =
1ee6dd77 786 kmalloc((sizeof(struct buffAdd) *
da6971d8
AR		 787 (rxd_count[nic->rxd_mode] + 1)),
788 GFP_KERNEL);
789 if (!mac_control->rings[i].ba[j])
1da177e4 790 return -ENOMEM;
491976b2
SH		 791 mem_allocated += (sizeof(struct buffAdd) * \
792 (rxd_count[nic->rxd_mode] + 1));
da6971d8
AR		 793 while (k != rxd_count[nic->rxd_mode]) {
794 ba = &mac_control->rings[i].ba[j][k];
795
796 ba->ba_0_org = (void *) kmalloc
797 (BUF0_LEN + ALIGN_SIZE, GFP_KERNEL);
798 if (!ba->ba_0_org)
799 return -ENOMEM;
8a4bdbaa 800 mem_allocated +=
491976b2 801 (BUF0_LEN + ALIGN_SIZE);
da6971d8
AR		 802 tmp = (unsigned long)ba->ba_0_org;
803 tmp += ALIGN_SIZE;
804 tmp &= ~((unsigned long) ALIGN_SIZE);
805 ba->ba_0 = (void *) tmp;
806
807 ba->ba_1_org = (void *) kmalloc
808 (BUF1_LEN + ALIGN_SIZE, GFP_KERNEL);
809 if (!ba->ba_1_org)
810 return -ENOMEM;
8a4bdbaa 811 mem_allocated
491976b2 812 += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 813 tmp = (unsigned long) ba->ba_1_org;
814 tmp += ALIGN_SIZE;
815 tmp &= ~((unsigned long) ALIGN_SIZE);
816 ba->ba_1 = (void *) tmp;
817 k++;
818 }
1da177e4
LT		 819 }
820 }
821 }
1da177e4
LT		 822
823 /* Allocation and initialization of Statistics block */
1ee6dd77 824 size = sizeof(struct stat_block);
1da177e4
LT		 825 mac_control->stats_mem = pci_alloc_consistent
826 (nic->pdev, size, &mac_control->stats_mem_phy);
827
828 if (!mac_control->stats_mem) {
20346722
K		 829 /*
830 * In case of failure, free_shared_mem() is called, which
831 * should free any memory that was alloced till the
1da177e4
LT		 832 * failure happened.
833 */
834 return -ENOMEM;
835 }
491976b2 836 mem_allocated += size;
1da177e4
LT		 837 mac_control->stats_mem_sz = size;
838
839 tmp_v_addr = mac_control->stats_mem;
1ee6dd77 840 mac_control->stats_info = (struct stat_block *) tmp_v_addr;
1da177e4 841 memset(tmp_v_addr, 0, size);
1da177e4
LT		 842 DBG_PRINT(INIT_DBG, "%s:Ring Mem PHY: 0x%llx\n", dev->name,
843 (unsigned long long) tmp_p_addr);
491976b2 844 mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
1da177e4
LT		 845 return SUCCESS;
846}
847
20346722
K		 848/**
849 * free_shared_mem - Free the allocated Memory
1da177e4
LT		 850 * @nic: Device private variable.
851 * Description: This function is to free all memory locations allocated by
852 * the init_shared_mem() function and return it to the kernel.
853 */
854
855static void free_shared_mem(struct s2io_nic *nic)
856{
857 int i, j, blk_cnt, size;
858 void *tmp_v_addr;
859 dma_addr_t tmp_p_addr;
1ee6dd77 860 struct mac_info *mac_control;
1da177e4
LT		 861 struct config_param *config;
862 int lst_size, lst_per_page;
8910b49f 863 struct net_device *dev;
491976b2 864 int page_num = 0;
1da177e4
LT		 865
866 if (!nic)
867 return;
868
8910b49f
MG		 869 dev = nic->dev;
870
1da177e4
LT		 871 mac_control = &nic->mac_control;
872 config = &nic->config;
873
1ee6dd77 874 lst_size = (sizeof(struct TxD) * config->max_txds);
1da177e4
LT		 875 lst_per_page = PAGE_SIZE / lst_size;
876
877 for (i = 0; i < config->tx_fifo_num; i++) {
491976b2
SH		 878 page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
879 lst_per_page);
1da177e4
LT		 880 for (j = 0; j < page_num; j++) {
881 int mem_blks = (j * lst_per_page);
776bd20f 882 if (!mac_control->fifos[i].list_info)
6aa20a22 883 return;
776bd20f 884 if (!mac_control->fifos[i].list_info[mem_blks].
885 list_virt_addr)
1da177e4
LT		 886 break;
887 pci_free_consistent(nic->pdev, PAGE_SIZE,
20346722
K		 888 mac_control->fifos[i].
889 list_info[mem_blks].
1da177e4 890 list_virt_addr,
20346722
K		 891 mac_control->fifos[i].
892 list_info[mem_blks].
1da177e4 893 list_phy_addr);
8a4bdbaa 894 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 895 += PAGE_SIZE;
1da177e4 896 }
776bd20f 897 /* If we got a zero DMA address during allocation,
898 * free the page now
899 */
900 if (mac_control->zerodma_virt_addr) {
901 pci_free_consistent(nic->pdev, PAGE_SIZE,
902 mac_control->zerodma_virt_addr,
903 (dma_addr_t)0);
6aa20a22 904 DBG_PRINT(INIT_DBG,
6b4d617d
AM		 905 "%s: Freeing TxDL with zero DMA addr. ",
906 dev->name);
907 DBG_PRINT(INIT_DBG, "Virtual address %p\n",
908 mac_control->zerodma_virt_addr);
8a4bdbaa 909 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 910 += PAGE_SIZE;
776bd20f 911 }
20346722 912 kfree(mac_control->fifos[i].list_info);
8a4bdbaa 913 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 914 (nic->config.tx_cfg[i].fifo_len *sizeof(struct list_info_hold));
1da177e4
LT		 915 }
916
1da177e4 917 size = SIZE_OF_BLOCK;
1da177e4 918 for (i = 0; i < config->rx_ring_num; i++) {
20346722 919 blk_cnt = mac_control->rings[i].block_count;
1da177e4 920 for (j = 0; j < blk_cnt; j++) {
20346722
K		 921 tmp_v_addr = mac_control->rings[i].rx_blocks[j].
922 block_virt_addr;
923 tmp_p_addr = mac_control->rings[i].rx_blocks[j].
924 block_dma_addr;
1da177e4
LT		 925 if (tmp_v_addr == NULL)
926 break;
927 pci_free_consistent(nic->pdev, size,
928 tmp_v_addr, tmp_p_addr);
491976b2 929 nic->mac_control.stats_info->sw_stat.mem_freed += size;
da6971d8 930 kfree(mac_control->rings[i].rx_blocks[j].rxds);
8a4bdbaa 931 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 932 ( sizeof(struct rxd_info)* rxd_count[nic->rxd_mode]);
1da177e4
LT		 933 }
934 }
935
6d517a27 936 if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 937 /* Freeing buffer storage addresses in 2BUFF mode. */
938 for (i = 0; i < config->rx_ring_num; i++) {
939 blk_cnt = config->rx_cfg[i].num_rxd /
940 (rxd_count[nic->rxd_mode] + 1);
941 for (j = 0; j < blk_cnt; j++) {
942 int k = 0;
943 if (!mac_control->rings[i].ba[j])
944 continue;
945 while (k != rxd_count[nic->rxd_mode]) {
1ee6dd77 946 struct buffAdd *ba =
da6971d8
AR		 947 &mac_control->rings[i].ba[j][k];
948 kfree(ba->ba_0_org);
491976b2
SH		 949 nic->mac_control.stats_info->sw_stat.\
950 mem_freed += (BUF0_LEN + ALIGN_SIZE);
da6971d8 951 kfree(ba->ba_1_org);
491976b2
SH		 952 nic->mac_control.stats_info->sw_stat.\
953 mem_freed += (BUF1_LEN + ALIGN_SIZE);
da6971d8
AR		 954 k++;
955 }
956 kfree(mac_control->rings[i].ba[j]);
9caab458
SS		 957 nic->mac_control.stats_info->sw_stat.mem_freed +=
958 (sizeof(struct buffAdd) *
959 (rxd_count[nic->rxd_mode] + 1));
1da177e4 960 }
da6971d8 961 kfree(mac_control->rings[i].ba);
8a4bdbaa 962 nic->mac_control.stats_info->sw_stat.mem_freed +=
491976b2 963 (sizeof(struct buffAdd *) * blk_cnt);
1da177e4 964 }
1da177e4 965 }
1da177e4 966
2fda096d
SR		 967 for (i = 0; i < nic->config.tx_fifo_num; i++) {
968 if (mac_control->fifos[i].ufo_in_band_v) {
969 nic->mac_control.stats_info->sw_stat.mem_freed
970 += (config->tx_cfg[i].fifo_len * sizeof(u64));
971 kfree(mac_control->fifos[i].ufo_in_band_v);
972 }
973 }
974
1da177e4 975 if (mac_control->stats_mem) {
2fda096d
SR		 976 nic->mac_control.stats_info->sw_stat.mem_freed +=
977 mac_control->stats_mem_sz;
1da177e4
LT		 978 pci_free_consistent(nic->pdev,
979 mac_control->stats_mem_sz,
980 mac_control->stats_mem,
981 mac_control->stats_mem_phy);
491976b2 982 }
1da177e4
LT		 983}
984
541ae68f
K		 985/**
986 * s2io_verify_pci_mode -
987 */
988
1ee6dd77 989static int s2io_verify_pci_mode(struct s2io_nic *nic)
541ae68f 990{
1ee6dd77 991 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 992 register u64 val64 = 0;
993 int mode;
994
995 val64 = readq(&bar0->pci_mode);
996 mode = (u8)GET_PCI_MODE(val64);
997
998 if ( val64 & PCI_MODE_UNKNOWN_MODE)
999 return -1; /* Unknown PCI mode */
1000 return mode;
1001}
1002
c92ca04b
AR		 1003#define NEC_VENID 0x1033
1004#define NEC_DEVID 0x0125
1005static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1006{
1007 struct pci_dev *tdev = NULL;
26d36b64
AC		 1008 while ((tdev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, tdev)) != NULL) {
1009 if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
c92ca04b 1010 if (tdev->bus == s2io_pdev->bus->parent)
26d36b64 1011 pci_dev_put(tdev);
c92ca04b
AR		 1012 return 1;
1013 }
1014 }
1015 return 0;
1016}
541ae68f 1017
7b32a312 1018static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
541ae68f
K		 1019/**
1020 * s2io_print_pci_mode -
1021 */
1ee6dd77 1022static int s2io_print_pci_mode(struct s2io_nic *nic)
541ae68f 1023{
1ee6dd77 1024 struct XENA_dev_config __iomem *bar0 = nic->bar0;
541ae68f
K		 1025 register u64 val64 = 0;
1026 int mode;
1027 struct config_param *config = &nic->config;
1028
1029 val64 = readq(&bar0->pci_mode);
1030 mode = (u8)GET_PCI_MODE(val64);
1031
1032 if ( val64 & PCI_MODE_UNKNOWN_MODE)
1033 return -1; /* Unknown PCI mode */
1034
c92ca04b
AR		 1035 config->bus_speed = bus_speed[mode];
1036
1037 if (s2io_on_nec_bridge(nic->pdev)) {
1038 DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1039 nic->dev->name);
1040 return mode;
1041 }
1042
541ae68f
K		 1043 if (val64 & PCI_MODE_32_BITS) {
1044 DBG_PRINT(ERR_DBG, "%s: Device is on 32 bit ", nic->dev->name);
1045 } else {
1046 DBG_PRINT(ERR_DBG, "%s: Device is on 64 bit ", nic->dev->name);
1047 }
1048
1049 switch(mode) {
1050 case PCI_MODE_PCI_33:
1051 DBG_PRINT(ERR_DBG, "33MHz PCI bus\n");
541ae68f
K		 1052 break;
1053 case PCI_MODE_PCI_66:
1054 DBG_PRINT(ERR_DBG, "66MHz PCI bus\n");
541ae68f
K		 1055 break;
1056 case PCI_MODE_PCIX_M1_66:
1057 DBG_PRINT(ERR_DBG, "66MHz PCIX(M1) bus\n");
541ae68f
K		 1058 break;
1059 case PCI_MODE_PCIX_M1_100:
1060 DBG_PRINT(ERR_DBG, "100MHz PCIX(M1) bus\n");
541ae68f
K		 1061 break;
1062 case PCI_MODE_PCIX_M1_133:
1063 DBG_PRINT(ERR_DBG, "133MHz PCIX(M1) bus\n");
541ae68f
K		 1064 break;
1065 case PCI_MODE_PCIX_M2_66:
1066 DBG_PRINT(ERR_DBG, "133MHz PCIX(M2) bus\n");
541ae68f
K		 1067 break;
1068 case PCI_MODE_PCIX_M2_100:
1069 DBG_PRINT(ERR_DBG, "200MHz PCIX(M2) bus\n");
541ae68f
K		 1070 break;
1071 case PCI_MODE_PCIX_M2_133:
1072 DBG_PRINT(ERR_DBG, "266MHz PCIX(M2) bus\n");
541ae68f
K		 1073 break;
1074 default:
1075 return -1; /* Unsupported bus speed */
1076 }
1077
1078 return mode;
1079}
1080
b7c5678f
RV		 1081/**
1082 * init_tti - Initialization transmit traffic interrupt scheme
1083 * @nic: device private variable
1084 * @link: link status (UP/DOWN) used to enable/disable continuous
1085 * transmit interrupts
1086 * Description: The function configures transmit traffic interrupts
1087 * Return Value: SUCCESS on success and
1088 * '-1' on failure
1089 */
1090
1091int init_tti(struct s2io_nic *nic, int link)
1092{
1093 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1094 register u64 val64 = 0;
1095 int i;
1096 struct config_param *config;
1097
1098 config = &nic->config;
1099
1100 for (i = 0; i < config->tx_fifo_num; i++) {
1101 /*
1102 * TTI Initialization. Default Tx timer gets us about
1103 * 250 interrupts per sec. Continuous interrupts are enabled
1104 * by default.
1105 */
1106 if (nic->device_type == XFRAME_II_DEVICE) {
1107 int count = (nic->config.bus_speed * 125)/2;
1108 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1109 } else
1110 val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1111
1112 val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1113 TTI_DATA1_MEM_TX_URNG_B(0x10) |
1114 TTI_DATA1_MEM_TX_URNG_C(0x30) |
1115 TTI_DATA1_MEM_TX_TIMER_AC_EN;
1116
1117 if (use_continuous_tx_intrs && (link == LINK_UP))
1118 val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1119 writeq(val64, &bar0->tti_data1_mem);
1120
1121 val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1122 TTI_DATA2_MEM_TX_UFC_B(0x20) |
1123 TTI_DATA2_MEM_TX_UFC_C(0x40) |
1124 TTI_DATA2_MEM_TX_UFC_D(0x80);
1125
1126 writeq(val64, &bar0->tti_data2_mem);
1127
1128 val64 = TTI_CMD_MEM_WE | TTI_CMD_MEM_STROBE_NEW_CMD |
1129 TTI_CMD_MEM_OFFSET(i);
1130 writeq(val64, &bar0->tti_command_mem);
1131
1132 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1133 TTI_CMD_MEM_STROBE_NEW_CMD, S2IO_BIT_RESET) != SUCCESS)
1134 return FAILURE;
1135 }
1136
1137 return SUCCESS;
1138}
1139
20346722
K		 1140/**
1141 * init_nic - Initialization of hardware
b7c5678f 1142 * @nic: device private variable
20346722
K		 1143 * Description: The function sequentially configures every block
1144 * of the H/W from their reset values.
1145 * Return Value: SUCCESS on success and
1da177e4
LT		 1146 * '-1' on failure (endian settings incorrect).
1147 */
1148
1149static int init_nic(struct s2io_nic *nic)
1150{
1ee6dd77 1151 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 1152 struct net_device *dev = nic->dev;
1153 register u64 val64 = 0;
1154 void __iomem *add;
1155 u32 time;
1156 int i, j;
1ee6dd77 1157 struct mac_info *mac_control;
1da177e4 1158 struct config_param *config;
c92ca04b 1159 int dtx_cnt = 0;
1da177e4 1160 unsigned long long mem_share;
20346722 1161 int mem_size;
1da177e4
LT		 1162
1163 mac_control = &nic->mac_control;
1164 config = &nic->config;
1165
5e25b9dd 1166 /* to set the swapper controle on the card */
20346722 1167 if(s2io_set_swapper(nic)) {
1da177e4 1168 DBG_PRINT(ERR_DBG,"ERROR: Setting Swapper failed\n");
9f74ffde 1169 return -EIO;
1da177e4
LT		 1170 }
1171
541ae68f
K		 1172 /*
1173 * Herc requires EOI to be removed from reset before XGXS, so..
1174 */
1175 if (nic->device_type & XFRAME_II_DEVICE) {
1176 val64 = 0xA500000000ULL;
1177 writeq(val64, &bar0->sw_reset);
1178 msleep(500);
1179 val64 = readq(&bar0->sw_reset);
1180 }
1181
1da177e4
LT		 1182 /* Remove XGXS from reset state */
1183 val64 = 0;
1184 writeq(val64, &bar0->sw_reset);
1da177e4 1185 msleep(500);
20346722 1186 val64 = readq(&bar0->sw_reset);
1da177e4 1187
7962024e
SH		 1188 /* Ensure that it's safe to access registers by checking
1189 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1190 */
1191 if (nic->device_type == XFRAME_II_DEVICE) {
1192 for (i = 0; i < 50; i++) {
1193 val64 = readq(&bar0->adapter_status);
1194 if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1195 break;
1196 msleep(10);
1197 }
1198 if (i == 50)
1199 return -ENODEV;
1200 }
1201
1da177e4
LT		 1202 /* Enable Receiving broadcasts */
1203 add = &bar0->mac_cfg;
1204 val64 = readq(&bar0->mac_cfg);
1205 val64 |= MAC_RMAC_BCAST_ENABLE;
1206 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1207 writel((u32) val64, add);
1208 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1209 writel((u32) (val64 >> 32), (add + 4));
1210
1211 /* Read registers in all blocks */
1212 val64 = readq(&bar0->mac_int_mask);
1213 val64 = readq(&bar0->mc_int_mask);
1214 val64 = readq(&bar0->xgxs_int_mask);
1215
1216 /* Set MTU */
1217 val64 = dev->mtu;
1218 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1219
541ae68f
K		 1220 if (nic->device_type & XFRAME_II_DEVICE) {
1221 while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
303bcb4b 1222 SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1da177e4 1223 &bar0->dtx_control, UF);
541ae68f
K		 1224 if (dtx_cnt & 0x1)
1225 msleep(1); /* Necessary!! */
1da177e4
LT		 1226 dtx_cnt++;
1227 }
541ae68f 1228 } else {
c92ca04b
AR		 1229 while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1230 SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1231 &bar0->dtx_control, UF);
1232 val64 = readq(&bar0->dtx_control);
1233 dtx_cnt++;
1da177e4
LT		 1234 }
1235 }
1236
1237 /* Tx DMA Initialization */
1238 val64 = 0;
1239 writeq(val64, &bar0->tx_fifo_partition_0);
1240 writeq(val64, &bar0->tx_fifo_partition_1);
1241 writeq(val64, &bar0->tx_fifo_partition_2);
1242 writeq(val64, &bar0->tx_fifo_partition_3);
1243
1244
1245 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1246 val64 |=
b7c5678f 1247 vBIT(config->tx_cfg[i].fifo_len - 1, ((j * 32) + 19),
1da177e4 1248 13) | vBIT(config->tx_cfg[i].fifo_priority,
b7c5678f 1249 ((j * 32) + 5), 3);
1da177e4
LT		 1250
1251 if (i == (config->tx_fifo_num - 1)) {
1252 if (i % 2 == 0)
1253 i++;
1254 }
1255
1256 switch (i) {
1257 case 1:
1258 writeq(val64, &bar0->tx_fifo_partition_0);
1259 val64 = 0;
b7c5678f 1260 j = 0;
1da177e4
LT		 1261 break;
1262 case 3:
1263 writeq(val64, &bar0->tx_fifo_partition_1);
1264 val64 = 0;
b7c5678f 1265 j = 0;
1da177e4
LT		 1266 break;
1267 case 5:
1268 writeq(val64, &bar0->tx_fifo_partition_2);
1269 val64 = 0;
b7c5678f 1270 j = 0;
1da177e4
LT		 1271 break;
1272 case 7:
1273 writeq(val64, &bar0->tx_fifo_partition_3);
b7c5678f
RV		 1274 val64 = 0;
1275 j = 0;
1276 break;
1277 default:
1278 j++;
1da177e4
LT		 1279 break;
1280 }
1281 }
1282
5e25b9dd
K		 1283 /*
1284 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1285 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1286 */
541ae68f 1287 if ((nic->device_type == XFRAME_I_DEVICE) &&
44c10138 1288 (nic->pdev->revision < 4))
5e25b9dd
K		 1289 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1290
1da177e4
LT		 1291 val64 = readq(&bar0->tx_fifo_partition_0);
1292 DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1293 &bar0->tx_fifo_partition_0, (unsigned long long) val64);
1294
20346722
K		 1295 /*
1296 * Initialization of Tx_PA_CONFIG register to ignore packet
1da177e4
LT		 1297 * integrity checking.
1298 */
1299 val64 = readq(&bar0->tx_pa_cfg);
1300 val64 |= TX_PA_CFG_IGNORE_FRM_ERR | TX_PA_CFG_IGNORE_SNAP_OUI |
1301 TX_PA_CFG_IGNORE_LLC_CTRL | TX_PA_CFG_IGNORE_L2_ERR;
1302 writeq(val64, &bar0->tx_pa_cfg);
1303
1304 /* Rx DMA intialization. */
1305 val64 = 0;
1306 for (i = 0; i < config->rx_ring_num; i++) {
1307 val64 |=
1308 vBIT(config->rx_cfg[i].ring_priority, (5 + (i * 8)),
1309 3);
1310 }
1311 writeq(val64, &bar0->rx_queue_priority);
1312
20346722
K		 1313 /*
1314 * Allocating equal share of memory to all the
1da177e4
LT		 1315 * configured Rings.
1316 */
1317 val64 = 0;
541ae68f
K		 1318 if (nic->device_type & XFRAME_II_DEVICE)
1319 mem_size = 32;
1320 else
1321 mem_size = 64;
1322
1da177e4
LT		 1323 for (i = 0; i < config->rx_ring_num; i++) {
1324 switch (i) {
1325 case 0:
20346722
K		 1326 mem_share = (mem_size / config->rx_ring_num +
1327 mem_size % config->rx_ring_num);
1da177e4
LT		 1328 val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1329 continue;
1330 case 1:
20346722 1331 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1332 val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1333 continue;
1334 case 2:
20346722 1335 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1336 val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1337 continue;
1338 case 3:
20346722 1339 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1340 val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1341 continue;
1342 case 4:
20346722 1343 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1344 val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1345 continue;
1346 case 5:
20346722 1347 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1348 val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1349 continue;
1350 case 6:
20346722 1351 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1352 val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1353 continue;
1354 case 7:
20346722 1355 mem_share = (mem_size / config->rx_ring_num);
1da177e4
LT		 1356 val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1357 continue;
1358 }
1359 }
1360 writeq(val64, &bar0->rx_queue_cfg);
1361
20346722 1362 /*
5e25b9dd 1363 * Filling Tx round robin registers
b7c5678f 1364 * as per the number of FIFOs for equal scheduling priority
1da177e4 1365 */
5e25b9dd
K		 1366 switch (config->tx_fifo_num) {
1367 case 1:
b7c5678f 1368 val64 = 0x0;
5e25b9dd
K		 1369 writeq(val64, &bar0->tx_w_round_robin_0);
1370 writeq(val64, &bar0->tx_w_round_robin_1);
1371 writeq(val64, &bar0->tx_w_round_robin_2);
1372 writeq(val64, &bar0->tx_w_round_robin_3);
1373 writeq(val64, &bar0->tx_w_round_robin_4);
1374 break;
1375 case 2:
b7c5678f 1376 val64 = 0x0001000100010001ULL;
5e25b9dd 1377 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1378 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1379 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1380 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1381 val64 = 0x0001000100000000ULL;
5e25b9dd
K		 1382 writeq(val64, &bar0->tx_w_round_robin_4);
1383 break;
1384 case 3:
b7c5678f 1385 val64 = 0x0001020001020001ULL;
5e25b9dd 1386 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1387 val64 = 0x0200010200010200ULL;
5e25b9dd 1388 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1389 val64 = 0x0102000102000102ULL;
5e25b9dd 1390 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1391 val64 = 0x0001020001020001ULL;
5e25b9dd 1392 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1393 val64 = 0x0200010200000000ULL;
5e25b9dd
K		 1394 writeq(val64, &bar0->tx_w_round_robin_4);
1395 break;
1396 case 4:
b7c5678f 1397 val64 = 0x0001020300010203ULL;
5e25b9dd 1398 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1399 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1400 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1401 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1402 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1403 writeq(val64, &bar0->tx_w_round_robin_4);
1404 break;
1405 case 5:
b7c5678f 1406 val64 = 0x0001020304000102ULL;
5e25b9dd 1407 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1408 val64 = 0x0304000102030400ULL;
5e25b9dd 1409 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1410 val64 = 0x0102030400010203ULL;
5e25b9dd 1411 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1412 val64 = 0x0400010203040001ULL;
5e25b9dd 1413 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1414 val64 = 0x0203040000000000ULL;
5e25b9dd
K		 1415 writeq(val64, &bar0->tx_w_round_robin_4);
1416 break;
1417 case 6:
b7c5678f 1418 val64 = 0x0001020304050001ULL;
5e25b9dd 1419 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1420 val64 = 0x0203040500010203ULL;
5e25b9dd 1421 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1422 val64 = 0x0405000102030405ULL;
5e25b9dd 1423 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1424 val64 = 0x0001020304050001ULL;
5e25b9dd 1425 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1426 val64 = 0x0203040500000000ULL;
5e25b9dd
K		 1427 writeq(val64, &bar0->tx_w_round_robin_4);
1428 break;
1429 case 7:
b7c5678f 1430 val64 = 0x0001020304050600ULL;
5e25b9dd 1431 writeq(val64, &bar0->tx_w_round_robin_0);
b7c5678f 1432 val64 = 0x0102030405060001ULL;
5e25b9dd 1433 writeq(val64, &bar0->tx_w_round_robin_1);
b7c5678f 1434 val64 = 0x0203040506000102ULL;
5e25b9dd 1435 writeq(val64, &bar0->tx_w_round_robin_2);
b7c5678f 1436 val64 = 0x0304050600010203ULL;
5e25b9dd 1437 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1438 val64 = 0x0405060000000000ULL;
5e25b9dd
K		 1439 writeq(val64, &bar0->tx_w_round_robin_4);
1440 break;
1441 case 8:
b7c5678f 1442 val64 = 0x0001020304050607ULL;
5e25b9dd 1443 writeq(val64, &bar0->tx_w_round_robin_0);
5e25b9dd 1444 writeq(val64, &bar0->tx_w_round_robin_1);
5e25b9dd 1445 writeq(val64, &bar0->tx_w_round_robin_2);
5e25b9dd 1446 writeq(val64, &bar0->tx_w_round_robin_3);
b7c5678f 1447 val64 = 0x0001020300000000ULL;
5e25b9dd
K		 1448 writeq(val64, &bar0->tx_w_round_robin_4);
1449 break;
1450 }
1451
b41477f3 1452 /* Enable all configured Tx FIFO partitions */
5d3213cc
AR		 1453 val64 = readq(&bar0->tx_fifo_partition_0);
1454 val64 |= (TX_FIFO_PARTITION_EN);
1455 writeq(val64, &bar0->tx_fifo_partition_0);
1456
5e25b9dd
K		 1457 /* Filling the Rx round robin registers as per the
1458 * number of Rings and steering based on QoS.
1459 */
1460 switch (config->rx_ring_num) {
1461 case 1:
1462 val64 = 0x8080808080808080ULL;
1463 writeq(val64, &bar0->rts_qos_steering);
1464 break;
1465 case 2:
1466 val64 = 0x0000010000010000ULL;
1467 writeq(val64, &bar0->rx_w_round_robin_0);
1468 val64 = 0x0100000100000100ULL;
1469 writeq(val64, &bar0->rx_w_round_robin_1);
1470 val64 = 0x0001000001000001ULL;
1471 writeq(val64, &bar0->rx_w_round_robin_2);
1472 val64 = 0x0000010000010000ULL;
1473 writeq(val64, &bar0->rx_w_round_robin_3);
1474 val64 = 0x0100000000000000ULL;
1475 writeq(val64, &bar0->rx_w_round_robin_4);
1476
1477 val64 = 0x8080808040404040ULL;
1478 writeq(val64, &bar0->rts_qos_steering);
1479 break;
1480 case 3:
1481 val64 = 0x0001000102000001ULL;
1482 writeq(val64, &bar0->rx_w_round_robin_0);
1483 val64 = 0x0001020000010001ULL;
1484 writeq(val64, &bar0->rx_w_round_robin_1);
1485 val64 = 0x0200000100010200ULL;
1486 writeq(val64, &bar0->rx_w_round_robin_2);
1487 val64 = 0x0001000102000001ULL;
1488 writeq(val64, &bar0->rx_w_round_robin_3);
1489 val64 = 0x0001020000000000ULL;
1490 writeq(val64, &bar0->rx_w_round_robin_4);
1491
1492 val64 = 0x8080804040402020ULL;
1493 writeq(val64, &bar0->rts_qos_steering);
1494 break;
1495 case 4:
1496 val64 = 0x0001020300010200ULL;
1497 writeq(val64, &bar0->rx_w_round_robin_0);
1498 val64 = 0x0100000102030001ULL;
1499 writeq(val64, &bar0->rx_w_round_robin_1);
1500 val64 = 0x0200010000010203ULL;
1501 writeq(val64, &bar0->rx_w_round_robin_2);
6aa20a22 1502 val64 = 0x0001020001000001ULL;
5e25b9dd
K		 1503 writeq(val64, &bar0->rx_w_round_robin_3);
1504 val64 = 0x0203000100000000ULL;
1505 writeq(val64, &bar0->rx_w_round_robin_4);
1506
1507 val64 = 0x8080404020201010ULL;
1508 writeq(val64, &bar0->rts_qos_steering);
1509 break;
1510 case 5:
1511 val64 = 0x0001000203000102ULL;
1512 writeq(val64, &bar0->rx_w_round_robin_0);
1513 val64 = 0x0001020001030004ULL;
1514 writeq(val64, &bar0->rx_w_round_robin_1);
1515 val64 = 0x0001000203000102ULL;
1516 writeq(val64, &bar0->rx_w_round_robin_2);
1517 val64 = 0x0001020001030004ULL;
1518 writeq(val64, &bar0->rx_w_round_robin_3);
1519 val64 = 0x0001000000000000ULL;
1520 writeq(val64, &bar0->rx_w_round_robin_4);
1521
1522 val64 = 0x8080404020201008ULL;
1523 writeq(val64, &bar0->rts_qos_steering);
1524 break;
1525 case 6:
1526 val64 = 0x0001020304000102ULL;
1527 writeq(val64, &bar0->rx_w_round_robin_0);
1528 val64 = 0x0304050001020001ULL;
1529 writeq(val64, &bar0->rx_w_round_robin_1);
1530 val64 = 0x0203000100000102ULL;
1531 writeq(val64, &bar0->rx_w_round_robin_2);
1532 val64 = 0x0304000102030405ULL;
1533 writeq(val64, &bar0->rx_w_round_robin_3);
1534 val64 = 0x0001000200000000ULL;
1535 writeq(val64, &bar0->rx_w_round_robin_4);
1536
1537 val64 = 0x8080404020100804ULL;
1538 writeq(val64, &bar0->rts_qos_steering);
1539 break;
1540 case 7:
1541 val64 = 0x0001020001020300ULL;
1542 writeq(val64, &bar0->rx_w_round_robin_0);
1543 val64 = 0x0102030400010203ULL;
1544 writeq(val64, &bar0->rx_w_round_robin_1);
1545 val64 = 0x0405060001020001ULL;
1546 writeq(val64, &bar0->rx_w_round_robin_2);
1547 val64 = 0x0304050000010200ULL;
1548 writeq(val64, &bar0->rx_w_round_robin_3);
1549 val64 = 0x0102030000000000ULL;
1550 writeq(val64, &bar0->rx_w_round_robin_4);
1551
1552 val64 = 0x8080402010080402ULL;
1553 writeq(val64, &bar0->rts_qos_steering);
1554 break;
1555 case 8:
1556 val64 = 0x0001020300040105ULL;
1557 writeq(val64, &bar0->rx_w_round_robin_0);
1558 val64 = 0x0200030106000204ULL;
1559 writeq(val64, &bar0->rx_w_round_robin_1);
1560 val64 = 0x0103000502010007ULL;
1561 writeq(val64, &bar0->rx_w_round_robin_2);
1562 val64 = 0x0304010002060500ULL;
1563 writeq(val64, &bar0->rx_w_round_robin_3);
1564 val64 = 0x0103020400000000ULL;
1565 writeq(val64, &bar0->rx_w_round_robin_4);
1566
1567 val64 = 0x8040201008040201ULL;
1568 writeq(val64, &bar0->rts_qos_steering);
1569 break;
1570 }
1da177e4
LT		 1571
1572 /* UDP Fix */
1573 val64 = 0;
20346722 1574 for (i = 0; i < 8; i++)
1da177e4
LT		 1575 writeq(val64, &bar0->rts_frm_len_n[i]);
1576
5e25b9dd
K		 1577 /* Set the default rts frame length for the rings configured */
1578 val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1579 for (i = 0 ; i < config->rx_ring_num ; i++)
1580 writeq(val64, &bar0->rts_frm_len_n[i]);
1581
1582 /* Set the frame length for the configured rings
1583 * desired by the user
1584 */
1585 for (i = 0; i < config->rx_ring_num; i++) {
1586 /* If rts_frm_len[i] == 0 then it is assumed that user not
1587 * specified frame length steering.
1588 * If the user provides the frame length then program
1589 * the rts_frm_len register for those values or else
1590 * leave it as it is.
1591 */
1592 if (rts_frm_len[i] != 0) {
1593 writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1594 &bar0->rts_frm_len_n[i]);
1595 }
1596 }
8a4bdbaa 1597
9fc93a41
SS		 1598 /* Disable differentiated services steering logic */
1599 for (i = 0; i < 64; i++) {
1600 if (rts_ds_steer(nic, i, 0) == FAILURE) {
1601 DBG_PRINT(ERR_DBG, "%s: failed rts ds steering",
1602 dev->name);
1603 DBG_PRINT(ERR_DBG, "set on codepoint %d\n", i);
9f74ffde 1604 return -ENODEV;
9fc93a41
SS		 1605 }
1606 }
1607
20346722 1608 /* Program statistics memory */
1da177e4 1609 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1da177e4 1610
541ae68f
K		 1611 if (nic->device_type == XFRAME_II_DEVICE) {
1612 val64 = STAT_BC(0x320);
1613 writeq(val64, &bar0->stat_byte_cnt);
1614 }
1615
20346722 1616 /*
1da177e4
LT		 1617 * Initializing the sampling rate for the device to calculate the
1618 * bandwidth utilization.
1619 */
1620 val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1621 MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1622 writeq(val64, &bar0->mac_link_util);
1623
20346722
K		 1624 /*
1625 * Initializing the Transmit and Receive Traffic Interrupt
1da177e4
LT		 1626 * Scheme.
1627 */
1da177e4 1628
b7c5678f
RV		 1629 /* Initialize TTI */
1630 if (SUCCESS != init_tti(nic, nic->last_link_state))
1631 return -ENODEV;
1da177e4 1632
8a4bdbaa
SS		 1633 /* RTI Initialization */
1634 if (nic->device_type == XFRAME_II_DEVICE) {
541ae68f 1635 /*
8a4bdbaa
SS		 1636 * Programmed to generate Apprx 500 Intrs per
1637 * second
1638 */
1639 int count = (nic->config.bus_speed * 125)/4;
1640 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1641 } else
1642 val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1643 val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1644 RTI_DATA1_MEM_RX_URNG_B(0x10) |
1645 RTI_DATA1_MEM_RX_URNG_C(0x30) | RTI_DATA1_MEM_RX_TIMER_AC_EN;
1646
1647 writeq(val64, &bar0->rti_data1_mem);
1648
1649 val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1650 RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1651 if (nic->config.intr_type == MSI_X)
1652 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) | \
1653 RTI_DATA2_MEM_RX_UFC_D(0x40));
1654 else
1655 val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) | \
1656 RTI_DATA2_MEM_RX_UFC_D(0x80));
1657 writeq(val64, &bar0->rti_data2_mem);
1da177e4 1658
8a4bdbaa
SS		 1659 for (i = 0; i < config->rx_ring_num; i++) {
1660 val64 = RTI_CMD_MEM_WE | RTI_CMD_MEM_STROBE_NEW_CMD
1661 | RTI_CMD_MEM_OFFSET(i);
1662 writeq(val64, &bar0->rti_command_mem);
1da177e4 1663
8a4bdbaa
SS		 1664 /*
1665 * Once the operation completes, the Strobe bit of the
1666 * command register will be reset. We poll for this
1667 * particular condition. We wait for a maximum of 500ms
1668 * for the operation to complete, if it's not complete
1669 * by then we return error.
1670 */
1671 time = 0;
1672 while (TRUE) {
1673 val64 = readq(&bar0->rti_command_mem);
1674 if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1675 break;
b6e3f982 1676
8a4bdbaa
SS		 1677 if (time > 10) {
1678 DBG_PRINT(ERR_DBG, "%s: RTI init Failed\n",
1679 dev->name);
9f74ffde 1680 return -ENODEV;
b6e3f982 1681 }
8a4bdbaa
SS		 1682 time++;
1683 msleep(50);
1da177e4 1684 }
1da177e4
LT		 1685 }
1686
20346722
K		 1687 /*
1688 * Initializing proper values as Pause threshold into all
1da177e4
LT		 1689 * the 8 Queues on Rx side.
1690 */
1691 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1692 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1693
1694 /* Disable RMAC PAD STRIPPING */
509a2671 1695 add = &bar0->mac_cfg;
1da177e4
LT		 1696 val64 = readq(&bar0->mac_cfg);
1697 val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1698 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1699 writel((u32) (val64), add);
1700 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1701 writel((u32) (val64 >> 32), (add + 4));
1702 val64 = readq(&bar0->mac_cfg);
1703
7d3d0439
RA		 1704 /* Enable FCS stripping by adapter */
1705 add = &bar0->mac_cfg;
1706 val64 = readq(&bar0->mac_cfg);
1707 val64 |= MAC_CFG_RMAC_STRIP_FCS;
1708 if (nic->device_type == XFRAME_II_DEVICE)
1709 writeq(val64, &bar0->mac_cfg);
1710 else {
1711 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1712 writel((u32) (val64), add);
1713 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1714 writel((u32) (val64 >> 32), (add + 4));
1715 }
1716
20346722
K		 1717 /*
1718 * Set the time value to be inserted in the pause frame
1da177e4
LT		 1719 * generated by xena.
1720 */
1721 val64 = readq(&bar0->rmac_pause_cfg);
1722 val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1723 val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1724 writeq(val64, &bar0->rmac_pause_cfg);
1725
20346722 1726 /*
1da177e4
LT		 1727 * Set the Threshold Limit for Generating the pause frame
1728 * If the amount of data in any Queue exceeds ratio of
1729 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1730 * pause frame is generated
1731 */
1732 val64 = 0;
1733 for (i = 0; i < 4; i++) {
1734 val64 |=
1735 (((u64) 0xFF00 | nic->mac_control.
1736 mc_pause_threshold_q0q3)
1737 << (i * 2 * 8));
1738 }
1739 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1740
1741 val64 = 0;
1742 for (i = 0; i < 4; i++) {
1743 val64 |=
1744 (((u64) 0xFF00 | nic->mac_control.
1745 mc_pause_threshold_q4q7)
1746 << (i * 2 * 8));
1747 }
1748 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1749
20346722
K		 1750 /*
1751 * TxDMA will stop Read request if the number of read split has
1da177e4
LT		 1752 * exceeded the limit pointed by shared_splits
1753 */
1754 val64 = readq(&bar0->pic_control);
1755 val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1756 writeq(val64, &bar0->pic_control);
1757
863c11a9
AR		 1758 if (nic->config.bus_speed == 266) {
1759 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1760 writeq(0x0, &bar0->read_retry_delay);
1761 writeq(0x0, &bar0->write_retry_delay);
1762 }
1763
541ae68f
K		 1764 /*
1765 * Programming the Herc to split every write transaction
1766 * that does not start on an ADB to reduce disconnects.
1767 */
1768 if (nic->device_type == XFRAME_II_DEVICE) {
19a60522
SS		 1769 val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1770 MISC_LINK_STABILITY_PRD(3);
863c11a9
AR		 1771 writeq(val64, &bar0->misc_control);
1772 val64 = readq(&bar0->pic_control2);
b7b5a128 1773 val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
863c11a9 1774 writeq(val64, &bar0->pic_control2);
541ae68f 1775 }
c92ca04b
AR		 1776 if (strstr(nic->product_name, "CX4")) {
1777 val64 = TMAC_AVG_IPG(0x17);
1778 writeq(val64, &bar0->tmac_avg_ipg);
a371a07d
K		 1779 }
1780
1da177e4
LT		 1781 return SUCCESS;
1782}
a371a07d
K		 1783#define LINK_UP_DOWN_INTERRUPT 1
1784#define MAC_RMAC_ERR_TIMER 2
1785
1ee6dd77 1786static int s2io_link_fault_indication(struct s2io_nic *nic)
a371a07d 1787{
eaae7f72 1788 if (nic->config.intr_type != INTA)
cc6e7c44 1789 return MAC_RMAC_ERR_TIMER;
a371a07d
K		 1790 if (nic->device_type == XFRAME_II_DEVICE)
1791 return LINK_UP_DOWN_INTERRUPT;
1792 else
1793 return MAC_RMAC_ERR_TIMER;
1794}
8116f3cf 1795
9caab458
SS		 1796/**
1797 * do_s2io_write_bits - update alarm bits in alarm register
1798 * @value: alarm bits
1799 * @flag: interrupt status
1800 * @addr: address value
1801 * Description: update alarm bits in alarm register
1802 * Return Value:
1803 * NONE.
1804 */
1805static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1806{
1807 u64 temp64;
1808
1809 temp64 = readq(addr);
1810
1811 if(flag == ENABLE_INTRS)
1812 temp64 &= ~((u64) value);
1813 else
1814 temp64 |= ((u64) value);
1815 writeq(temp64, addr);
1816}
1da177e4 1817
43b7c451 1818static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
9caab458
SS		 1819{
1820 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1821 register u64 gen_int_mask = 0;
1822
1823 if (mask & TX_DMA_INTR) {
1824
1825 gen_int_mask |= TXDMA_INT_M;
1826
1827 do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1828 TXDMA_PCC_INT | TXDMA_TTI_INT |
1829 TXDMA_LSO_INT | TXDMA_TPA_INT |
1830 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1831
1832 do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1833 PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1834 PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1835 &bar0->pfc_err_mask);
1836
1837 do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1838 TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1839 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1840
1841 do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1842 PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1843 PCC_N_SERR | PCC_6_COF_OV_ERR |
1844 PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1845 PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1846 PCC_TXB_ECC_SG_ERR, flag, &bar0->pcc_err_mask);
1847
1848 do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1849 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1850
1851 do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1852 LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1853 LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1854 flag, &bar0->lso_err_mask);
1855
1856 do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1857 flag, &bar0->tpa_err_mask);
1858
1859 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1860
1861 }
1862
1863 if (mask & TX_MAC_INTR) {
1864 gen_int_mask |= TXMAC_INT_M;
1865 do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1866 &bar0->mac_int_mask);
1867 do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1868 TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1869 TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1870 flag, &bar0->mac_tmac_err_mask);
1871 }
1872
1873 if (mask & TX_XGXS_INTR) {
1874 gen_int_mask |= TXXGXS_INT_M;
1875 do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1876 &bar0->xgxs_int_mask);
1877 do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1878 TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1879 flag, &bar0->xgxs_txgxs_err_mask);
1880 }
1881
1882 if (mask & RX_DMA_INTR) {
1883 gen_int_mask |= RXDMA_INT_M;
1884 do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1885 RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1886 flag, &bar0->rxdma_int_mask);
1887 do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1888 RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1889 RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1890 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1891 do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1892 PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1893 PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1894 &bar0->prc_pcix_err_mask);
1895 do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1896 RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1897 &bar0->rpa_err_mask);
1898 do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1899 RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1900 RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1901 RDA_FRM_ECC_SG_ERR | RDA_MISC_ERR|RDA_PCIX_ERR,
1902 flag, &bar0->rda_err_mask);
1903 do_s2io_write_bits(RTI_SM_ERR_ALARM |
1904 RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1905 flag, &bar0->rti_err_mask);
1906 }
1907
1908 if (mask & RX_MAC_INTR) {
1909 gen_int_mask |= RXMAC_INT_M;
1910 do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1911 &bar0->mac_int_mask);
1912 do_s2io_write_bits(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1913 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1914 RMAC_DOUBLE_ECC_ERR |
1915 RMAC_LINK_STATE_CHANGE_INT,
1916 flag, &bar0->mac_rmac_err_mask);
1917 }
1918
1919 if (mask & RX_XGXS_INTR)
1920 {
1921 gen_int_mask |= RXXGXS_INT_M;
1922 do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1923 &bar0->xgxs_int_mask);
1924 do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1925 &bar0->xgxs_rxgxs_err_mask);
1926 }
1927
1928 if (mask & MC_INTR) {
1929 gen_int_mask |= MC_INT_M;
1930 do_s2io_write_bits(MC_INT_MASK_MC_INT, flag, &bar0->mc_int_mask);
1931 do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1932 MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1933 &bar0->mc_err_mask);
1934 }
1935 nic->general_int_mask = gen_int_mask;
1936
1937 /* Remove this line when alarm interrupts are enabled */
1938 nic->general_int_mask = 0;
1939}
20346722
K		 1940/**
1941 * en_dis_able_nic_intrs - Enable or Disable the interrupts
1da177e4
LT		 1942 * @nic: device private variable,
1943 * @mask: A mask indicating which Intr block must be modified and,
1944 * @flag: A flag indicating whether to enable or disable the Intrs.
1945 * Description: This function will either disable or enable the interrupts
20346722
K		 1946 * depending on the flag argument. The mask argument can be used to
1947 * enable/disable any Intr block.
1da177e4
LT		 1948 * Return Value: NONE.
1949 */
1950
1951static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1952{
1ee6dd77 1953 struct XENA_dev_config __iomem *bar0 = nic->bar0;
9caab458
SS		 1954 register u64 temp64 = 0, intr_mask = 0;
1955
1956 intr_mask = nic->general_int_mask;
1da177e4
LT		 1957
1958 /* Top level interrupt classification */
1959 /* PIC Interrupts */
9caab458 1960 if (mask & TX_PIC_INTR) {
1da177e4 1961 /* Enable PIC Intrs in the general intr mask register */
9caab458 1962 intr_mask |= TXPIC_INT_M;
1da177e4 1963 if (flag == ENABLE_INTRS) {
20346722 1964 /*
a371a07d 1965 * If Hercules adapter enable GPIO otherwise
b41477f3 1966 * disable all PCIX, Flash, MDIO, IIC and GPIO
20346722
K		 1967 * interrupts for now.
1968 * TODO
1da177e4 1969 */
a371a07d
K		 1970 if (s2io_link_fault_indication(nic) ==
1971 LINK_UP_DOWN_INTERRUPT ) {
9caab458
SS		 1972 do_s2io_write_bits(PIC_INT_GPIO, flag,
1973 &bar0->pic_int_mask);
1974 do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
1975 &bar0->gpio_int_mask);
1976 } else
a371a07d 1977 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4 1978 } else if (flag == DISABLE_INTRS) {
20346722
K		 1979 /*
1980 * Disable PIC Intrs in the general
1981 * intr mask register
1da177e4
LT		 1982 */
1983 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
1da177e4
LT		 1984 }
1985 }
1986
1da177e4
LT		 1987 /* Tx traffic interrupts */
1988 if (mask & TX_TRAFFIC_INTR) {
9caab458 1989 intr_mask |= TXTRAFFIC_INT_M;
1da177e4 1990 if (flag == ENABLE_INTRS) {
20346722 1991 /*
1da177e4 1992 * Enable all the Tx side interrupts
20346722 1993 * writing 0 Enables all 64 TX interrupt levels
1da177e4
LT		 1994 */
1995 writeq(0x0, &bar0->tx_traffic_mask);
1996 } else if (flag == DISABLE_INTRS) {
20346722
K		 1997 /*
1998 * Disable Tx Traffic Intrs in the general intr mask
1da177e4
LT		 1999 * register.
2000 */
2001 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
1da177e4
LT		 2002 }
2003 }
2004
2005 /* Rx traffic interrupts */
2006 if (mask & RX_TRAFFIC_INTR) {
9caab458 2007 intr_mask |= RXTRAFFIC_INT_M;
1da177e4 2008 if (flag == ENABLE_INTRS) {
1da177e4
LT		 2009 /* writing 0 Enables all 8 RX interrupt levels */
2010 writeq(0x0, &bar0->rx_traffic_mask);
2011 } else if (flag == DISABLE_INTRS) {
20346722
K		 2012 /*
2013 * Disable Rx Traffic Intrs in the general intr mask
1da177e4
LT		 2014 * register.
2015 */
2016 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
1da177e4
LT		 2017 }
2018 }
9caab458
SS		 2019
2020 temp64 = readq(&bar0->general_int_mask);
2021 if (flag == ENABLE_INTRS)
2022 temp64 &= ~((u64) intr_mask);
2023 else
2024 temp64 = DISABLE_ALL_INTRS;
2025 writeq(temp64, &bar0->general_int_mask);
2026
2027 nic->general_int_mask = readq(&bar0->general_int_mask);
1da177e4
LT		 2028}
2029
19a60522
SS		 2030/**
2031 * verify_pcc_quiescent- Checks for PCC quiescent state
2032 * Return: 1 If PCC is quiescence
2033 * 0 If PCC is not quiescence
2034 */
1ee6dd77 2035static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
20346722 2036{
19a60522 2037 int ret = 0, herc;
1ee6dd77 2038 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522 2039 u64 val64 = readq(&bar0->adapter_status);
8a4bdbaa 2040
19a60522 2041 herc = (sp->device_type == XFRAME_II_DEVICE);
20346722
K		 2042
2043 if (flag == FALSE) {
44c10138 2044 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
19a60522 2045 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2046 ret = 1;
19a60522
SS		 2047 } else {
2048 if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2049 ret = 1;
20346722
K		 2050 }
2051 } else {
44c10138 2052 if ((!herc && (sp->pdev->revision >= 4)) || herc) {
5e25b9dd 2053 if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
19a60522 2054 ADAPTER_STATUS_RMAC_PCC_IDLE))
5e25b9dd 2055 ret = 1;
5e25b9dd
K		 2056 } else {
2057 if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
19a60522 2058 ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
5e25b9dd 2059 ret = 1;
20346722
K		 2060 }
2061 }
2062
2063 return ret;
2064}
2065/**
2066 * verify_xena_quiescence - Checks whether the H/W is ready
1da177e4 2067 * Description: Returns whether the H/W is ready to go or not. Depending
20346722 2068 * on whether adapter enable bit was written or not the comparison
1da177e4
LT		 2069 * differs and the calling function passes the input argument flag to
2070 * indicate this.
20346722 2071 * Return: 1 If xena is quiescence
1da177e4
LT		 2072 * 0 If Xena is not quiescence
2073 */
2074
1ee6dd77 2075static int verify_xena_quiescence(struct s2io_nic *sp)
1da177e4 2076{
19a60522 2077 int mode;
1ee6dd77 2078 struct XENA_dev_config __iomem *bar0 = sp->bar0;
19a60522
SS		 2079 u64 val64 = readq(&bar0->adapter_status);
2080 mode = s2io_verify_pci_mode(sp);
1da177e4 2081
19a60522
SS		 2082 if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2083 DBG_PRINT(ERR_DBG, "%s", "TDMA is not ready!");
2084 return 0;
2085 }
2086 if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2087 DBG_PRINT(ERR_DBG, "%s", "RDMA is not ready!");
2088 return 0;
2089 }
2090 if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2091 DBG_PRINT(ERR_DBG, "%s", "PFC is not ready!");
2092 return 0;
2093 }
2094 if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2095 DBG_PRINT(ERR_DBG, "%s", "TMAC BUF is not empty!");
2096 return 0;
2097 }
2098 if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2099 DBG_PRINT(ERR_DBG, "%s", "PIC is not QUIESCENT!");
2100 return 0;
2101 }
2102 if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2103 DBG_PRINT(ERR_DBG, "%s", "MC_DRAM is not ready!");
2104 return 0;
2105 }
2106 if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2107 DBG_PRINT(ERR_DBG, "%s", "MC_QUEUES is not ready!");
2108 return 0;
2109 }
2110 if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2111 DBG_PRINT(ERR_DBG, "%s", "M_PLL is not locked!");
2112 return 0;
1da177e4
LT		 2113 }
2114
19a60522
SS		 2115 /*
2116 * In PCI 33 mode, the P_PLL is not used, and therefore,
2117 * the the P_PLL_LOCK bit in the adapter_status register will
2118 * not be asserted.
2119 */
2120 if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2121 sp->device_type == XFRAME_II_DEVICE && mode !=
2122 PCI_MODE_PCI_33) {
2123 DBG_PRINT(ERR_DBG, "%s", "P_PLL is not locked!");
2124 return 0;
2125 }
2126 if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2127 ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2128 DBG_PRINT(ERR_DBG, "%s", "RC_PRC is not QUIESCENT!");
2129 return 0;
2130 }
2131 return 1;
1da177e4
LT		 2132}
2133
2134/**
2135 * fix_mac_address - Fix for Mac addr problem on Alpha platforms
2136 * @sp: Pointer to device specifc structure
20346722 2137 * Description :
1da177e4
LT		 2138 * New procedure to clear mac address reading problems on Alpha platforms
2139 *
2140 */
2141
1ee6dd77 2142static void fix_mac_address(struct s2io_nic * sp)
1da177e4 2143{
1ee6dd77 2144 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 2145 u64 val64;
2146 int i = 0;
2147
2148 while (fix_mac[i] != END_SIGN) {
2149 writeq(fix_mac[i++], &bar0->gpio_control);
20346722 2150 udelay(10);
1da177e4
LT		 2151 val64 = readq(&bar0->gpio_control);
2152 }
2153}
2154
2155/**
20346722 2156 * start_nic - Turns the device on
1da177e4 2157 * @nic : device private variable.
20346722
K		 2158 * Description:
2159 * This function actually turns the device on. Before this function is
2160 * called,all Registers are configured from their reset states
2161 * and shared memory is allocated but the NIC is still quiescent. On
1da177e4
LT		 2162 * calling this function, the device interrupts are cleared and the NIC is
2163 * literally switched on by writing into the adapter control register.
20346722 2164 * Return Value:
1da177e4
LT		 2165 * SUCCESS on success and -1 on failure.
2166 */
2167
2168static int start_nic(struct s2io_nic *nic)
2169{
1ee6dd77 2170 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 2171 struct net_device *dev = nic->dev;
2172 register u64 val64 = 0;
20346722 2173 u16 subid, i;
1ee6dd77 2174 struct mac_info *mac_control;
1da177e4
LT		 2175 struct config_param *config;
2176
2177 mac_control = &nic->mac_control;
2178 config = &nic->config;
2179
2180 /* PRC Initialization and configuration */
2181 for (i = 0; i < config->rx_ring_num; i++) {
20346722 2182 writeq((u64) mac_control->rings[i].rx_blocks[0].block_dma_addr,
1da177e4
LT		 2183 &bar0->prc_rxd0_n[i]);
2184
2185 val64 = readq(&bar0->prc_ctrl_n[i]);
da6971d8
AR		 2186 if (nic->rxd_mode == RXD_MODE_1)
2187 val64 |= PRC_CTRL_RC_ENABLED;
2188 else
2189 val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
863c11a9
AR		 2190 if (nic->device_type == XFRAME_II_DEVICE)
2191 val64 |= PRC_CTRL_GROUP_READS;
2192 val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2193 val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
1da177e4
LT		 2194 writeq(val64, &bar0->prc_ctrl_n[i]);
2195 }
2196
da6971d8
AR		 2197 if (nic->rxd_mode == RXD_MODE_3B) {
2198 /* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2199 val64 = readq(&bar0->rx_pa_cfg);
2200 val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2201 writeq(val64, &bar0->rx_pa_cfg);
2202 }
1da177e4 2203
926930b2
SS		 2204 if (vlan_tag_strip == 0) {
2205 val64 = readq(&bar0->rx_pa_cfg);
2206 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2207 writeq(val64, &bar0->rx_pa_cfg);
2208 vlan_strip_flag = 0;
2209 }
2210
20346722 2211 /*
1da177e4
LT		 2212 * Enabling MC-RLDRAM. After enabling the device, we timeout
2213 * for around 100ms, which is approximately the time required
2214 * for the device to be ready for operation.
2215 */
2216 val64 = readq(&bar0->mc_rldram_mrs);
2217 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2218 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2219 val64 = readq(&bar0->mc_rldram_mrs);
2220
20346722 2221 msleep(100); /* Delay by around 100 ms. */
1da177e4
LT		 2222
2223 /* Enabling ECC Protection. */
2224 val64 = readq(&bar0->adapter_control);
2225 val64 &= ~ADAPTER_ECC_EN;
2226 writeq(val64, &bar0->adapter_control);
2227
20346722
K		 2228 /*
2229 * Verify if the device is ready to be enabled, if so enable
1da177e4
LT		 2230 * it.
2231 */
2232 val64 = readq(&bar0->adapter_status);
19a60522 2233 if (!verify_xena_quiescence(nic)) {
1da177e4
LT		 2234 DBG_PRINT(ERR_DBG, "%s: device is not ready, ", dev->name);
2235 DBG_PRINT(ERR_DBG, "Adapter status reads: 0x%llx\n",
2236 (unsigned long long) val64);
2237 return FAILURE;
2238 }
2239
20346722 2240 /*
1da177e4 2241 * With some switches, link might be already up at this point.
20346722
K		 2242 * Because of this weird behavior, when we enable laser,
2243 * we may not get link. We need to handle this. We cannot
2244 * figure out which switch is misbehaving. So we are forced to
2245 * make a global change.
1da177e4
LT		 2246 */
2247
2248 /* Enabling Laser. */
2249 val64 = readq(&bar0->adapter_control);
2250 val64 |= ADAPTER_EOI_TX_ON;
2251 writeq(val64, &bar0->adapter_control);
2252
c92ca04b
AR		 2253 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2254 /*
2255 * Dont see link state interrupts initally on some switches,
2256 * so directly scheduling the link state task here.
2257 */
2258 schedule_work(&nic->set_link_task);
2259 }
1da177e4
LT		 2260 /* SXE-002: Initialize link and activity LED */
2261 subid = nic->pdev->subsystem_device;
541ae68f
K		 2262 if (((subid & 0xFF) >= 0x07) &&
2263 (nic->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 2264 val64 = readq(&bar0->gpio_control);
2265 val64 |= 0x0000800000000000ULL;
2266 writeq(val64, &bar0->gpio_control);
2267 val64 = 0x0411040400000000ULL;
509a2671 2268 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 2269 }
2270
1da177e4
LT		 2271 return SUCCESS;
2272}
fed5eccd
AR		 2273/**
2274 * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2275 */
1ee6dd77
RB		 2276static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data, struct \
2277 TxD *txdlp, int get_off)
fed5eccd 2278{
1ee6dd77 2279 struct s2io_nic *nic = fifo_data->nic;
fed5eccd 2280 struct sk_buff *skb;
1ee6dd77 2281 struct TxD *txds;
fed5eccd
AR		 2282 u16 j, frg_cnt;
2283
2284 txds = txdlp;
2fda096d 2285 if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
fed5eccd
AR		 2286 pci_unmap_single(nic->pdev, (dma_addr_t)
2287 txds->Buffer_Pointer, sizeof(u64),
2288 PCI_DMA_TODEVICE);
2289 txds++;
2290 }
2291
2292 skb = (struct sk_buff *) ((unsigned long)
2293 txds->Host_Control);
2294 if (!skb) {
1ee6dd77 2295 memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2296 return NULL;
2297 }
2298 pci_unmap_single(nic->pdev, (dma_addr_t)
2299 txds->Buffer_Pointer,
2300 skb->len - skb->data_len,
2301 PCI_DMA_TODEVICE);
2302 frg_cnt = skb_shinfo(skb)->nr_frags;
2303 if (frg_cnt) {
2304 txds++;
2305 for (j = 0; j < frg_cnt; j++, txds++) {
2306 skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2307 if (!txds->Buffer_Pointer)
2308 break;
6aa20a22 2309 pci_unmap_page(nic->pdev, (dma_addr_t)
fed5eccd
AR		 2310 txds->Buffer_Pointer,
2311 frag->size, PCI_DMA_TODEVICE);
2312 }
2313 }
1ee6dd77 2314 memset(txdlp,0, (sizeof(struct TxD) * fifo_data->max_txds));
fed5eccd
AR		 2315 return(skb);
2316}
1da177e4 2317
20346722
K		 2318/**
2319 * free_tx_buffers - Free all queued Tx buffers
1da177e4 2320 * @nic : device private variable.
20346722 2321 * Description:
1da177e4 2322 * Free all queued Tx buffers.
20346722 2323 * Return Value: void
1da177e4
LT		 2324*/
2325
2326static void free_tx_buffers(struct s2io_nic *nic)
2327{
2328 struct net_device *dev = nic->dev;
2329 struct sk_buff *skb;
1ee6dd77 2330 struct TxD *txdp;
1da177e4 2331 int i, j;
1ee6dd77 2332 struct mac_info *mac_control;
1da177e4 2333 struct config_param *config;
fed5eccd 2334 int cnt = 0;
1da177e4
LT		 2335
2336 mac_control = &nic->mac_control;
2337 config = &nic->config;
2338
2339 for (i = 0; i < config->tx_fifo_num; i++) {
2fda096d
SR		 2340 unsigned long flags;
2341 spin_lock_irqsave(&mac_control->fifos[i].tx_lock, flags);
1da177e4 2342 for (j = 0; j < config->tx_cfg[i].fifo_len - 1; j++) {
491976b2
SH		 2343 txdp = (struct TxD *) \
2344 mac_control->fifos[i].list_info[j].list_virt_addr;
fed5eccd
AR		 2345 skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2346 if (skb) {
8a4bdbaa 2347 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 2348 += skb->truesize;
fed5eccd
AR		 2349 dev_kfree_skb(skb);
2350 cnt++;
1da177e4 2351 }
1da177e4
LT		 2352 }
2353 DBG_PRINT(INTR_DBG,
2354 "%s:forcibly freeing %d skbs on FIFO%d\n",
2355 dev->name, cnt, i);
20346722
K		 2356 mac_control->fifos[i].tx_curr_get_info.offset = 0;
2357 mac_control->fifos[i].tx_curr_put_info.offset = 0;
2fda096d 2358 spin_unlock_irqrestore(&mac_control->fifos[i].tx_lock, flags);
1da177e4
LT		 2359 }
2360}
2361
20346722
K		 2362/**
2363 * stop_nic - To stop the nic
1da177e4 2364 * @nic ; device private variable.
20346722
K		 2365 * Description:
2366 * This function does exactly the opposite of what the start_nic()
1da177e4
LT		 2367 * function does. This function is called to stop the device.
2368 * Return Value:
2369 * void.
2370 */
2371
2372static void stop_nic(struct s2io_nic *nic)
2373{
1ee6dd77 2374 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4 2375 register u64 val64 = 0;
5d3213cc 2376 u16 interruptible;
1ee6dd77 2377 struct mac_info *mac_control;
1da177e4
LT		 2378 struct config_param *config;
2379
2380 mac_control = &nic->mac_control;
2381 config = &nic->config;
2382
2383 /* Disable all interrupts */
9caab458 2384 en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
e960fc5c 2385 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 2386 interruptible |= TX_PIC_INTR;
1da177e4
LT		 2387 en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2388
5d3213cc
AR		 2389 /* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2390 val64 = readq(&bar0->adapter_control);
2391 val64 &= ~(ADAPTER_CNTL_EN);
2392 writeq(val64, &bar0->adapter_control);
1da177e4
LT		 2393}
2394
20346722
K		 2395/**
2396 * fill_rx_buffers - Allocates the Rx side skbs
1da177e4 2397 * @nic: device private variable
20346722
K		 2398 * @ring_no: ring number
2399 * Description:
1da177e4
LT		 2400 * The function allocates Rx side skbs and puts the physical
2401 * address of these buffers into the RxD buffer pointers, so that the NIC
2402 * can DMA the received frame into these locations.
2403 * The NIC supports 3 receive modes, viz
2404 * 1. single buffer,
2405 * 2. three buffer and
2406 * 3. Five buffer modes.
20346722
K		 2407 * Each mode defines how many fragments the received frame will be split
2408 * up into by the NIC. The frame is split into L3 header, L4 Header,
1da177e4
LT		 2409 * L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2410 * is split into 3 fragments. As of now only single buffer mode is
2411 * supported.
2412 * Return Value:
2413 * SUCCESS on success or an appropriate -ve value on failure.
2414 */
2415
ac1f60db 2416static int fill_rx_buffers(struct s2io_nic *nic, int ring_no)
1da177e4
LT		 2417{
2418 struct net_device *dev = nic->dev;
2419 struct sk_buff *skb;
1ee6dd77 2420 struct RxD_t *rxdp;
1da177e4 2421 int off, off1, size, block_no, block_no1;
1da177e4 2422 u32 alloc_tab = 0;
20346722 2423 u32 alloc_cnt;
1ee6dd77 2424 struct mac_info *mac_control;
1da177e4 2425 struct config_param *config;
20346722 2426 u64 tmp;
1ee6dd77 2427 struct buffAdd *ba;
1da177e4 2428 unsigned long flags;
1ee6dd77 2429 struct RxD_t *first_rxdp = NULL;
363dc367 2430 u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
6d517a27
VP		 2431 struct RxD1 *rxdp1;
2432 struct RxD3 *rxdp3;
491abf25 2433 struct swStat *stats = &nic->mac_control.stats_info->sw_stat;
1da177e4
LT		 2434
2435 mac_control = &nic->mac_control;
2436 config = &nic->config;
20346722
K		 2437 alloc_cnt = mac_control->rings[ring_no].pkt_cnt -
2438 atomic_read(&nic->rx_bufs_left[ring_no]);
1da177e4 2439
5d3213cc 2440 block_no1 = mac_control->rings[ring_no].rx_curr_get_info.block_index;
863c11a9 2441 off1 = mac_control->rings[ring_no].rx_curr_get_info.offset;
1da177e4 2442 while (alloc_tab < alloc_cnt) {
20346722 2443 block_no = mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2444 block_index;
20346722 2445 off = mac_control->rings[ring_no].rx_curr_put_info.offset;
1da177e4 2446
da6971d8
AR		 2447 rxdp = mac_control->rings[ring_no].
2448 rx_blocks[block_no].rxds[off].virt_addr;
2449
2450 if ((block_no == block_no1) && (off == off1) &&
2451 (rxdp->Host_Control)) {
2452 DBG_PRINT(INTR_DBG, "%s: Get and Put",
2453 dev->name);
1da177e4
LT		 2454 DBG_PRINT(INTR_DBG, " info equated\n");
2455 goto end;
2456 }
da6971d8 2457 if (off && (off == rxd_count[nic->rxd_mode])) {
20346722 2458 mac_control->rings[ring_no].rx_curr_put_info.
1da177e4 2459 block_index++;
da6971d8
AR		 2460 if (mac_control->rings[ring_no].rx_curr_put_info.
2461 block_index == mac_control->rings[ring_no].
2462 block_count)
2463 mac_control->rings[ring_no].rx_curr_put_info.
2464 block_index = 0;
2465 block_no = mac_control->rings[ring_no].
2466 rx_curr_put_info.block_index;
2467 if (off == rxd_count[nic->rxd_mode])
2468 off = 0;
20346722 2469 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8
AR		 2470 offset = off;
2471 rxdp = mac_control->rings[ring_no].
2472 rx_blocks[block_no].block_virt_addr;
1da177e4
LT		 2473 DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2474 dev->name, rxdp);
2475 }
db874e65
SS		 2476 if(!napi) {
2477 spin_lock_irqsave(&nic->put_lock, flags);
2478 mac_control->rings[ring_no].put_pos =
2479 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2480 spin_unlock_irqrestore(&nic->put_lock, flags);
2481 } else {
2482 mac_control->rings[ring_no].put_pos =
2483 (block_no * (rxd_count[nic->rxd_mode] + 1)) + off;
2484 }
da6971d8 2485 if ((rxdp->Control_1 & RXD_OWN_XENA) &&
6d517a27 2486 ((nic->rxd_mode == RXD_MODE_3B) &&
b7b5a128 2487 (rxdp->Control_2 & s2BIT(0)))) {
20346722 2488 mac_control->rings[ring_no].rx_curr_put_info.
da6971d8 2489 offset = off;
1da177e4
LT		 2490 goto end;
2491 }
da6971d8
AR		 2492 /* calculate size of skb based on ring mode */
2493 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
2494 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2495 if (nic->rxd_mode == RXD_MODE_1)
2496 size += NET_IP_ALIGN;
da6971d8 2497 else
6d517a27 2498 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
1da177e4 2499
da6971d8
AR		 2500 /* allocate skb */
2501 skb = dev_alloc_skb(size);
2502 if(!skb) {
0c61ed5f
RV		 2503 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
2504 DBG_PRINT(INFO_DBG, "memory to allocate SKBs\n");
303bcb4b
K		 2505 if (first_rxdp) {
2506 wmb();
2507 first_rxdp->Control_1 |= RXD_OWN_XENA;
2508 }
c53d4945
SH		 2509 nic->mac_control.stats_info->sw_stat. \
2510 mem_alloc_fail_cnt++;
da6971d8
AR		 2511 return -ENOMEM ;
2512 }
8a4bdbaa 2513 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 2514 += skb->truesize;
da6971d8
AR		 2515 if (nic->rxd_mode == RXD_MODE_1) {
2516 /* 1 buffer mode - normal operation mode */
6d517a27 2517 rxdp1 = (struct RxD1*)rxdp;
1ee6dd77 2518 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2519 skb_reserve(skb, NET_IP_ALIGN);
6d517a27 2520 rxdp1->Buffer0_ptr = pci_map_single
863c11a9
AR		 2521 (nic->pdev, skb->data, size - NET_IP_ALIGN,
2522 PCI_DMA_FROMDEVICE);
491abf25
VP		 2523 if( (rxdp1->Buffer0_ptr == 0) ||
2524 (rxdp1->Buffer0_ptr ==
2525 DMA_ERROR_CODE))
2526 goto pci_map_failed;
2527
8a4bdbaa 2528 rxdp->Control_2 =
491976b2 2529 SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
da6971d8 2530
6d517a27 2531 } else if (nic->rxd_mode == RXD_MODE_3B) {
da6971d8 2532 /*
6d517a27
VP		 2533 * 2 buffer mode -
2534 * 2 buffer mode provides 128
da6971d8 2535 * byte aligned receive buffers.
da6971d8
AR		 2536 */
2537
6d517a27 2538 rxdp3 = (struct RxD3*)rxdp;
491976b2 2539 /* save buffer pointers to avoid frequent dma mapping */
6d517a27
VP		 2540 Buffer0_ptr = rxdp3->Buffer0_ptr;
2541 Buffer1_ptr = rxdp3->Buffer1_ptr;
1ee6dd77 2542 memset(rxdp, 0, sizeof(struct RxD3));
363dc367 2543 /* restore the buffer pointers for dma sync*/
6d517a27
VP		 2544 rxdp3->Buffer0_ptr = Buffer0_ptr;
2545 rxdp3->Buffer1_ptr = Buffer1_ptr;
363dc367 2546
da6971d8
AR		 2547 ba = &mac_control->rings[ring_no].ba[block_no][off];
2548 skb_reserve(skb, BUF0_LEN);
2549 tmp = (u64)(unsigned long) skb->data;
2550 tmp += ALIGN_SIZE;
2551 tmp &= ~ALIGN_SIZE;
2552 skb->data = (void *) (unsigned long)tmp;
27a884dc 2553 skb_reset_tail_pointer(skb);
da6971d8 2554
6d517a27
VP		 2555 if (!(rxdp3->Buffer0_ptr))
2556 rxdp3->Buffer0_ptr =
75c30b13 2557 pci_map_single(nic->pdev, ba->ba_0, BUF0_LEN,
da6971d8 2558 PCI_DMA_FROMDEVICE);
75c30b13
AR		 2559 else
2560 pci_dma_sync_single_for_device(nic->pdev,
6d517a27 2561 (dma_addr_t) rxdp3->Buffer0_ptr,
75c30b13 2562 BUF0_LEN, PCI_DMA_FROMDEVICE);
491abf25
VP		 2563 if( (rxdp3->Buffer0_ptr == 0) ||
2564 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE))
2565 goto pci_map_failed;
2566
da6971d8
AR		 2567 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2568 if (nic->rxd_mode == RXD_MODE_3B) {
2569 /* Two buffer mode */
2570
2571 /*
6aa20a22 2572 * Buffer2 will have L3/L4 header plus
da6971d8
AR		 2573 * L4 payload
2574 */
6d517a27 2575 rxdp3->Buffer2_ptr = pci_map_single
da6971d8
AR		 2576 (nic->pdev, skb->data, dev->mtu + 4,
2577 PCI_DMA_FROMDEVICE);
2578
491abf25
VP		 2579 if( (rxdp3->Buffer2_ptr == 0) ||
2580 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE))
2581 goto pci_map_failed;
2582
2583 rxdp3->Buffer1_ptr =
6aa20a22 2584 pci_map_single(nic->pdev,
75c30b13
AR		 2585 ba->ba_1, BUF1_LEN,
2586 PCI_DMA_FROMDEVICE);
491abf25
VP		 2587 if( (rxdp3->Buffer1_ptr == 0) ||
2588 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
2589 pci_unmap_single
2590 (nic->pdev,
3e847423 2591 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 2592 dev->mtu + 4,
2593 PCI_DMA_FROMDEVICE);
2594 goto pci_map_failed;
75c30b13 2595 }
da6971d8
AR		 2596 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2597 rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2598 (dev->mtu + 4);
da6971d8 2599 }
b7b5a128 2600 rxdp->Control_2 |= s2BIT(0);
1da177e4 2601 }
1da177e4 2602 rxdp->Host_Control = (unsigned long) (skb);
303bcb4b
K		 2603 if (alloc_tab & ((1 << rxsync_frequency) - 1))
2604 rxdp->Control_1 |= RXD_OWN_XENA;
1da177e4 2605 off++;
da6971d8
AR		 2606 if (off == (rxd_count[nic->rxd_mode] + 1))
2607 off = 0;
20346722 2608 mac_control->rings[ring_no].rx_curr_put_info.offset = off;
20346722 2609
da6971d8 2610 rxdp->Control_2 |= SET_RXD_MARKER;
303bcb4b
K		 2611 if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2612 if (first_rxdp) {
2613 wmb();
2614 first_rxdp->Control_1 |= RXD_OWN_XENA;
2615 }
2616 first_rxdp = rxdp;
2617 }
1da177e4
LT		 2618 atomic_inc(&nic->rx_bufs_left[ring_no]);
2619 alloc_tab++;
2620 }
2621
2622 end:
303bcb4b
K		 2623 /* Transfer ownership of first descriptor to adapter just before
2624 * exiting. Before that, use memory barrier so that ownership
2625 * and other fields are seen by adapter correctly.
2626 */
2627 if (first_rxdp) {
2628 wmb();
2629 first_rxdp->Control_1 |= RXD_OWN_XENA;
2630 }
2631
1da177e4 2632 return SUCCESS;
491abf25
VP		 2633pci_map_failed:
2634 stats->pci_map_fail_cnt++;
2635 stats->mem_freed += skb->truesize;
2636 dev_kfree_skb_irq(skb);
2637 return -ENOMEM;
1da177e4
LT		 2638}
2639
da6971d8
AR		 2640static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2641{
2642 struct net_device *dev = sp->dev;
2643 int j;
2644 struct sk_buff *skb;
1ee6dd77
RB		 2645 struct RxD_t *rxdp;
2646 struct mac_info *mac_control;
2647 struct buffAdd *ba;
6d517a27
VP		 2648 struct RxD1 *rxdp1;
2649 struct RxD3 *rxdp3;
da6971d8
AR		 2650
2651 mac_control = &sp->mac_control;
2652 for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2653 rxdp = mac_control->rings[ring_no].
2654 rx_blocks[blk].rxds[j].virt_addr;
2655 skb = (struct sk_buff *)
2656 ((unsigned long) rxdp->Host_Control);
2657 if (!skb) {
2658 continue;
2659 }
2660 if (sp->rxd_mode == RXD_MODE_1) {
6d517a27 2661 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2662 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2663 rxdp1->Buffer0_ptr,
2664 dev->mtu +
2665 HEADER_ETHERNET_II_802_3_SIZE
2666 + HEADER_802_2_SIZE +
2667 HEADER_SNAP_SIZE,
2668 PCI_DMA_FROMDEVICE);
1ee6dd77 2669 memset(rxdp, 0, sizeof(struct RxD1));
da6971d8 2670 } else if(sp->rxd_mode == RXD_MODE_3B) {
6d517a27 2671 rxdp3 = (struct RxD3*)rxdp;
da6971d8
AR		 2672 ba = &mac_control->rings[ring_no].
2673 ba[blk][j];
2674 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2675 rxdp3->Buffer0_ptr,
2676 BUF0_LEN,
da6971d8
AR		 2677 PCI_DMA_FROMDEVICE);
2678 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2679 rxdp3->Buffer1_ptr,
2680 BUF1_LEN,
da6971d8
AR		 2681 PCI_DMA_FROMDEVICE);
2682 pci_unmap_single(sp->pdev, (dma_addr_t)
6d517a27
VP		 2683 rxdp3->Buffer2_ptr,
2684 dev->mtu + 4,
da6971d8 2685 PCI_DMA_FROMDEVICE);
1ee6dd77 2686 memset(rxdp, 0, sizeof(struct RxD3));
da6971d8 2687 }
491976b2 2688 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
da6971d8
AR		 2689 dev_kfree_skb(skb);
2690 atomic_dec(&sp->rx_bufs_left[ring_no]);
2691 }
2692}
2693
1da177e4 2694/**
20346722 2695 * free_rx_buffers - Frees all Rx buffers
1da177e4 2696 * @sp: device private variable.
20346722 2697 * Description:
1da177e4
LT		 2698 * This function will free all Rx buffers allocated by host.
2699 * Return Value:
2700 * NONE.
2701 */
2702
2703static void free_rx_buffers(struct s2io_nic *sp)
2704{
2705 struct net_device *dev = sp->dev;
da6971d8 2706 int i, blk = 0, buf_cnt = 0;
1ee6dd77 2707 struct mac_info *mac_control;
1da177e4 2708 struct config_param *config;
1da177e4
LT		 2709
2710 mac_control = &sp->mac_control;
2711 config = &sp->config;
2712
2713 for (i = 0; i < config->rx_ring_num; i++) {
da6971d8
AR		 2714 for (blk = 0; blk < rx_ring_sz[i]; blk++)
2715 free_rxd_blk(sp,i,blk);
1da177e4 2716
20346722
K		 2717 mac_control->rings[i].rx_curr_put_info.block_index = 0;
2718 mac_control->rings[i].rx_curr_get_info.block_index = 0;
2719 mac_control->rings[i].rx_curr_put_info.offset = 0;
2720 mac_control->rings[i].rx_curr_get_info.offset = 0;
1da177e4
LT		 2721 atomic_set(&sp->rx_bufs_left[i], 0);
2722 DBG_PRINT(INIT_DBG, "%s:Freed 0x%x Rx Buffers on ring%d\n",
2723 dev->name, buf_cnt, i);
2724 }
2725}
2726
2727/**
2728 * s2io_poll - Rx interrupt handler for NAPI support
bea3348e 2729 * @napi : pointer to the napi structure.
20346722 2730 * @budget : The number of packets that were budgeted to be processed
1da177e4
LT		 2731 * during one pass through the 'Poll" function.
2732 * Description:
2733 * Comes into picture only if NAPI support has been incorporated. It does
2734 * the same thing that rx_intr_handler does, but not in a interrupt context
2735 * also It will process only a given number of packets.
2736 * Return value:
2737 * 0 on success and 1 if there are No Rx packets to be processed.
2738 */
2739
bea3348e 2740static int s2io_poll(struct napi_struct *napi, int budget)
1da177e4 2741{
bea3348e
SH		 2742 struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2743 struct net_device *dev = nic->dev;
20346722 2744 int pkt_cnt = 0, org_pkts_to_process;
1ee6dd77 2745 struct mac_info *mac_control;
1da177e4 2746 struct config_param *config;
1ee6dd77 2747 struct XENA_dev_config __iomem *bar0 = nic->bar0;
20346722 2748 int i;
1da177e4
LT		 2749
2750 mac_control = &nic->mac_control;
2751 config = &nic->config;
2752
bea3348e 2753 nic->pkts_to_process = budget;
20346722 2754 org_pkts_to_process = nic->pkts_to_process;
1da177e4 2755
19a60522
SS		 2756 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
2757 readl(&bar0->rx_traffic_int);
1da177e4
LT		 2758
2759 for (i = 0; i < config->rx_ring_num; i++) {
20346722
K		 2760 rx_intr_handler(&mac_control->rings[i]);
2761 pkt_cnt = org_pkts_to_process - nic->pkts_to_process;
2762 if (!nic->pkts_to_process) {
2763 /* Quota for the current iteration has been met */
2764 goto no_rx;
1da177e4 2765 }
1da177e4 2766 }
1da177e4 2767
bea3348e 2768 netif_rx_complete(dev, napi);
1da177e4
LT		 2769
2770 for (i = 0; i < config->rx_ring_num; i++) {
2771 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2772 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2773 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2774 break;
2775 }
2776 }
2777 /* Re enable the Rx interrupts. */
c92ca04b 2778 writeq(0x0, &bar0->rx_traffic_mask);
19a60522 2779 readl(&bar0->rx_traffic_mask);
bea3348e 2780 return pkt_cnt;
1da177e4 2781
20346722 2782no_rx:
1da177e4
LT		 2783 for (i = 0; i < config->rx_ring_num; i++) {
2784 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2785 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2786 DBG_PRINT(INFO_DBG, " in Rx Poll!!\n");
1da177e4
LT		 2787 break;
2788 }
2789 }
bea3348e 2790 return pkt_cnt;
1da177e4 2791}
20346722 2792
b41477f3 2793#ifdef CONFIG_NET_POLL_CONTROLLER
612eff0e 2794/**
b41477f3 2795 * s2io_netpoll - netpoll event handler entry point
612eff0e
BH		 2796 * @dev : pointer to the device structure.
2797 * Description:
b41477f3
AR		 2798 * This function will be called by upper layer to check for events on the
2799 * interface in situations where interrupts are disabled. It is used for
2800 * specific in-kernel networking tasks, such as remote consoles and kernel
2801 * debugging over the network (example netdump in RedHat).
612eff0e 2802 */
612eff0e
BH		 2803static void s2io_netpoll(struct net_device *dev)
2804{
1ee6dd77
RB		 2805 struct s2io_nic *nic = dev->priv;
2806 struct mac_info *mac_control;
612eff0e 2807 struct config_param *config;
1ee6dd77 2808 struct XENA_dev_config __iomem *bar0 = nic->bar0;
b41477f3 2809 u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
612eff0e
BH		 2810 int i;
2811
d796fdb7
LV		 2812 if (pci_channel_offline(nic->pdev))
2813 return;
2814
612eff0e
BH		 2815 disable_irq(dev->irq);
2816
612eff0e
BH		 2817 mac_control = &nic->mac_control;
2818 config = &nic->config;
2819
612eff0e 2820 writeq(val64, &bar0->rx_traffic_int);
b41477f3
AR		 2821 writeq(val64, &bar0->tx_traffic_int);
2822
6aa20a22 2823 /* we need to free up the transmitted skbufs or else netpoll will
b41477f3
AR		 2824 * run out of skbs and will fail and eventually netpoll application such
2825 * as netdump will fail.
2826 */
2827 for (i = 0; i < config->tx_fifo_num; i++)
2828 tx_intr_handler(&mac_control->fifos[i]);
612eff0e 2829
b41477f3 2830 /* check for received packet and indicate up to network */
612eff0e
BH		 2831 for (i = 0; i < config->rx_ring_num; i++)
2832 rx_intr_handler(&mac_control->rings[i]);
2833
2834 for (i = 0; i < config->rx_ring_num; i++) {
2835 if (fill_rx_buffers(nic, i) == -ENOMEM) {
0c61ed5f
RV		 2836 DBG_PRINT(INFO_DBG, "%s:Out of memory", dev->name);
2837 DBG_PRINT(INFO_DBG, " in Rx Netpoll!!\n");
612eff0e
BH		 2838 break;
2839 }
2840 }
612eff0e
BH		 2841 enable_irq(dev->irq);
2842 return;
2843}
2844#endif
2845
20346722 2846/**
1da177e4
LT		 2847 * rx_intr_handler - Rx interrupt handler
2848 * @nic: device private variable.
20346722
K		 2849 * Description:
2850 * If the interrupt is because of a received frame or if the
1da177e4 2851 * receive ring contains fresh as yet un-processed frames,this function is
20346722
K		 2852 * called. It picks out the RxD at which place the last Rx processing had
2853 * stopped and sends the skb to the OSM's Rx handler and then increments
1da177e4
LT		 2854 * the offset.
2855 * Return Value:
2856 * NONE.
2857 */
1ee6dd77 2858static void rx_intr_handler(struct ring_info *ring_data)
1da177e4 2859{
1ee6dd77 2860 struct s2io_nic *nic = ring_data->nic;
1da177e4 2861 struct net_device *dev = (struct net_device *) nic->dev;
da6971d8 2862 int get_block, put_block, put_offset;
1ee6dd77
RB		 2863 struct rx_curr_get_info get_info, put_info;
2864 struct RxD_t *rxdp;
1da177e4 2865 struct sk_buff *skb;
20346722 2866 int pkt_cnt = 0;
7d3d0439 2867 int i;
6d517a27
VP		 2868 struct RxD1* rxdp1;
2869 struct RxD3* rxdp3;
7d3d0439 2870
7ba013ac 2871 spin_lock(&nic->rx_lock);
7ba013ac 2872
20346722
K		 2873 get_info = ring_data->rx_curr_get_info;
2874 get_block = get_info.block_index;
1ee6dd77 2875 memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
20346722 2876 put_block = put_info.block_index;
da6971d8 2877 rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
db874e65
SS		 2878 if (!napi) {
2879 spin_lock(&nic->put_lock);
2880 put_offset = ring_data->put_pos;
2881 spin_unlock(&nic->put_lock);
2882 } else
2883 put_offset = ring_data->put_pos;
2884
da6971d8 2885 while (RXD_IS_UP2DT(rxdp)) {
db874e65
SS		 2886 /*
2887 * If your are next to put index then it's
2888 * FIFO full condition
2889 */
da6971d8
AR		 2890 if ((get_block == put_block) &&
2891 (get_info.offset + 1) == put_info.offset) {
75c30b13 2892 DBG_PRINT(INTR_DBG, "%s: Ring Full\n",dev->name);
da6971d8
AR		 2893 break;
2894 }
20346722
K		 2895 skb = (struct sk_buff *) ((unsigned long)rxdp->Host_Control);
2896 if (skb == NULL) {
2897 DBG_PRINT(ERR_DBG, "%s: The skb is ",
2898 dev->name);
2899 DBG_PRINT(ERR_DBG, "Null in Rx Intr\n");
7ba013ac 2900 spin_unlock(&nic->rx_lock);
20346722 2901 return;
1da177e4 2902 }
da6971d8 2903 if (nic->rxd_mode == RXD_MODE_1) {
6d517a27 2904 rxdp1 = (struct RxD1*)rxdp;
da6971d8 2905 pci_unmap_single(nic->pdev, (dma_addr_t)
6d517a27
VP		 2906 rxdp1->Buffer0_ptr,
2907 dev->mtu +
2908 HEADER_ETHERNET_II_802_3_SIZE +
2909 HEADER_802_2_SIZE +
2910 HEADER_SNAP_SIZE,
2911 PCI_DMA_FROMDEVICE);
da6971d8 2912 } else if (nic->rxd_mode == RXD_MODE_3B) {
6d517a27 2913 rxdp3 = (struct RxD3*)rxdp;
75c30b13 2914 pci_dma_sync_single_for_cpu(nic->pdev, (dma_addr_t)
6d517a27
VP		 2915 rxdp3->Buffer0_ptr,
2916 BUF0_LEN, PCI_DMA_FROMDEVICE);
da6971d8 2917 pci_unmap_single(nic->pdev, (dma_addr_t)
6d517a27
VP		 2918 rxdp3->Buffer2_ptr,
2919 dev->mtu + 4,
2920 PCI_DMA_FROMDEVICE);
da6971d8 2921 }
863c11a9 2922 prefetch(skb->data);
20346722
K		 2923 rx_osm_handler(ring_data, rxdp);
2924 get_info.offset++;
da6971d8
AR		 2925 ring_data->rx_curr_get_info.offset = get_info.offset;
2926 rxdp = ring_data->rx_blocks[get_block].
2927 rxds[get_info.offset].virt_addr;
2928 if (get_info.offset == rxd_count[nic->rxd_mode]) {
20346722 2929 get_info.offset = 0;
da6971d8 2930 ring_data->rx_curr_get_info.offset = get_info.offset;
20346722 2931 get_block++;
da6971d8
AR		 2932 if (get_block == ring_data->block_count)
2933 get_block = 0;
2934 ring_data->rx_curr_get_info.block_index = get_block;
20346722
K		 2935 rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2936 }
1da177e4 2937
20346722 2938 nic->pkts_to_process -= 1;
db874e65 2939 if ((napi) && (!nic->pkts_to_process))
20346722 2940 break;
20346722 2941 pkt_cnt++;
1da177e4
LT		 2942 if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2943 break;
2944 }
7d3d0439
RA		 2945 if (nic->lro) {
2946 /* Clear all LRO sessions before exiting */
2947 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 2948 struct lro *lro = &nic->lro0_n[i];
7d3d0439
RA		 2949 if (lro->in_use) {
2950 update_L3L4_header(nic, lro);
2951 queue_rx_frame(lro->parent);
2952 clear_lro_session(lro);
2953 }
2954 }
2955 }
2956
7ba013ac 2957 spin_unlock(&nic->rx_lock);
1da177e4 2958}
20346722
K		 2959
2960/**
1da177e4
LT		 2961 * tx_intr_handler - Transmit interrupt handler
2962 * @nic : device private variable
20346722
K		 2963 * Description:
2964 * If an interrupt was raised to indicate DMA complete of the
2965 * Tx packet, this function is called. It identifies the last TxD
2966 * whose buffer was freed and frees all skbs whose data have already
1da177e4
LT		 2967 * DMA'ed into the NICs internal memory.
2968 * Return Value:
2969 * NONE
2970 */
2971
1ee6dd77 2972static void tx_intr_handler(struct fifo_info *fifo_data)
1da177e4 2973{
1ee6dd77 2974 struct s2io_nic *nic = fifo_data->nic;
1da177e4 2975 struct net_device *dev = (struct net_device *) nic->dev;
1ee6dd77 2976 struct tx_curr_get_info get_info, put_info;
1da177e4 2977 struct sk_buff *skb;
1ee6dd77 2978 struct TxD *txdlp;
2fda096d 2979 unsigned long flags = 0;
f9046eb3 2980 u8 err_mask;
1da177e4 2981
2fda096d
SR		 2982 if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
2983 return;
2984
20346722 2985 get_info = fifo_data->tx_curr_get_info;
1ee6dd77
RB		 2986 memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
2987 txdlp = (struct TxD *) fifo_data->list_info[get_info.offset].
20346722
K		 2988 list_virt_addr;
2989 while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
2990 (get_info.offset != put_info.offset) &&
2991 (txdlp->Host_Control)) {
2992 /* Check for TxD errors */
2993 if (txdlp->Control_1 & TXD_T_CODE) {
2994 unsigned long long err;
2995 err = txdlp->Control_1 & TXD_T_CODE;
bd1034f0
AR		 2996 if (err & 0x1) {
2997 nic->mac_control.stats_info->sw_stat.
2998 parity_err_cnt++;
2999 }
491976b2
SH		 3000
3001 /* update t_code statistics */
f9046eb3
OH		 3002 err_mask = err >> 48;
3003 switch(err_mask) {
491976b2
SH		 3004 case 2:
3005 nic->mac_control.stats_info->sw_stat.
3006 tx_buf_abort_cnt++;
3007 break;
3008
3009 case 3:
3010 nic->mac_control.stats_info->sw_stat.
3011 tx_desc_abort_cnt++;
3012 break;
3013
3014 case 7:
3015 nic->mac_control.stats_info->sw_stat.
3016 tx_parity_err_cnt++;
3017 break;
3018
3019 case 10:
3020 nic->mac_control.stats_info->sw_stat.
3021 tx_link_loss_cnt++;
3022 break;
3023
3024 case 15:
3025 nic->mac_control.stats_info->sw_stat.
3026 tx_list_proc_err_cnt++;
3027 break;
3028 }
20346722 3029 }
1da177e4 3030
fed5eccd 3031 skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
20346722 3032 if (skb == NULL) {
2fda096d 3033 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
20346722
K		 3034 DBG_PRINT(ERR_DBG, "%s: Null skb ",
3035 __FUNCTION__);
3036 DBG_PRINT(ERR_DBG, "in Tx Free Intr\n");
3037 return;
3038 }
3039
20346722 3040 /* Updating the statistics block */
20346722 3041 nic->stats.tx_bytes += skb->len;
491976b2 3042 nic->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
20346722
K		 3043 dev_kfree_skb_irq(skb);
3044
3045 get_info.offset++;
863c11a9
AR		 3046 if (get_info.offset == get_info.fifo_len + 1)
3047 get_info.offset = 0;
1ee6dd77 3048 txdlp = (struct TxD *) fifo_data->list_info
20346722
K		 3049 [get_info.offset].list_virt_addr;
3050 fifo_data->tx_curr_get_info.offset =
3051 get_info.offset;
1da177e4
LT		 3052 }
3053
1da177e4
LT		 3054 if (netif_queue_stopped(dev))
3055 netif_wake_queue(dev);
2fda096d
SR		 3056
3057 spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
1da177e4
LT		 3058}
3059
bd1034f0
AR		 3060/**
3061 * s2io_mdio_write - Function to write in to MDIO registers
3062 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3063 * @addr : address value
3064 * @value : data value
3065 * @dev : pointer to net_device structure
3066 * Description:
3067 * This function is used to write values to the MDIO registers
3068 * NONE
3069 */
3070static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value, struct net_device *dev)
3071{
3072 u64 val64 = 0x0;
1ee6dd77
RB		 3073 struct s2io_nic *sp = dev->priv;
3074 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3075
3076 //address transaction
3077 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3078 | MDIO_MMD_DEV_ADDR(mmd_type)
3079 | MDIO_MMS_PRT_ADDR(0x0);
3080 writeq(val64, &bar0->mdio_control);
3081 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3082 writeq(val64, &bar0->mdio_control);
3083 udelay(100);
3084
3085 //Data transaction
3086 val64 = 0x0;
3087 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3088 | MDIO_MMD_DEV_ADDR(mmd_type)
3089 | MDIO_MMS_PRT_ADDR(0x0)
3090 | MDIO_MDIO_DATA(value)
3091 | MDIO_OP(MDIO_OP_WRITE_TRANS);
3092 writeq(val64, &bar0->mdio_control);
3093 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3094 writeq(val64, &bar0->mdio_control);
3095 udelay(100);
3096
3097 val64 = 0x0;
3098 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3099 | MDIO_MMD_DEV_ADDR(mmd_type)
3100 | MDIO_MMS_PRT_ADDR(0x0)
3101 | MDIO_OP(MDIO_OP_READ_TRANS);
3102 writeq(val64, &bar0->mdio_control);
3103 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3104 writeq(val64, &bar0->mdio_control);
3105 udelay(100);
3106
3107}
3108
3109/**
3110 * s2io_mdio_read - Function to write in to MDIO registers
3111 * @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3112 * @addr : address value
3113 * @dev : pointer to net_device structure
3114 * Description:
3115 * This function is used to read values to the MDIO registers
3116 * NONE
3117 */
3118static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3119{
3120 u64 val64 = 0x0;
3121 u64 rval64 = 0x0;
1ee6dd77
RB		 3122 struct s2io_nic *sp = dev->priv;
3123 struct XENA_dev_config __iomem *bar0 = sp->bar0;
bd1034f0
AR		 3124
3125 /* address transaction */
3126 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3127 | MDIO_MMD_DEV_ADDR(mmd_type)
3128 | MDIO_MMS_PRT_ADDR(0x0);
3129 writeq(val64, &bar0->mdio_control);
3130 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3131 writeq(val64, &bar0->mdio_control);
3132 udelay(100);
3133
3134 /* Data transaction */
3135 val64 = 0x0;
3136 val64 = val64 | MDIO_MMD_INDX_ADDR(addr)
3137 | MDIO_MMD_DEV_ADDR(mmd_type)
3138 | MDIO_MMS_PRT_ADDR(0x0)
3139 | MDIO_OP(MDIO_OP_READ_TRANS);
3140 writeq(val64, &bar0->mdio_control);
3141 val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3142 writeq(val64, &bar0->mdio_control);
3143 udelay(100);
3144
3145 /* Read the value from regs */
3146 rval64 = readq(&bar0->mdio_control);
3147 rval64 = rval64 & 0xFFFF0000;
3148 rval64 = rval64 >> 16;
3149 return rval64;
3150}
3151/**
3152 * s2io_chk_xpak_counter - Function to check the status of the xpak counters
3153 * @counter : couter value to be updated
3154 * @flag : flag to indicate the status
3155 * @type : counter type
3156 * Description:
3157 * This function is to check the status of the xpak counters value
3158 * NONE
3159 */
3160
3161static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index, u16 flag, u16 type)
3162{
3163 u64 mask = 0x3;
3164 u64 val64;
3165 int i;
3166 for(i = 0; i <index; i++)
3167 mask = mask << 0x2;
3168
3169 if(flag > 0)
3170 {
3171 *counter = *counter + 1;
3172 val64 = *regs_stat & mask;
3173 val64 = val64 >> (index * 0x2);
3174 val64 = val64 + 1;
3175 if(val64 == 3)
3176 {
3177 switch(type)
3178 {
3179 case 1:
3180 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3181 "service. Excessive temperatures may "
3182 "result in premature transceiver "
3183 "failure \n");
3184 break;
3185 case 2:
3186 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3187 "service Excessive bias currents may "
3188 "indicate imminent laser diode "
3189 "failure \n");
3190 break;
3191 case 3:
3192 DBG_PRINT(ERR_DBG, "Take Xframe NIC out of "
3193 "service Excessive laser output "
3194 "power may saturate far-end "
3195 "receiver\n");
3196 break;
3197 default:
3198 DBG_PRINT(ERR_DBG, "Incorrect XPAK Alarm "
3199 "type \n");
3200 }
3201 val64 = 0x0;
3202 }
3203 val64 = val64 << (index * 0x2);
3204 *regs_stat = (*regs_stat & (~mask)) | (val64);
3205
3206 } else {
3207 *regs_stat = *regs_stat & (~mask);
3208 }
3209}
3210
3211/**
3212 * s2io_updt_xpak_counter - Function to update the xpak counters
3213 * @dev : pointer to net_device struct
3214 * Description:
3215 * This function is to upate the status of the xpak counters value
3216 * NONE
3217 */
3218static void s2io_updt_xpak_counter(struct net_device *dev)
3219{
3220 u16 flag = 0x0;
3221 u16 type = 0x0;
3222 u16 val16 = 0x0;
3223 u64 val64 = 0x0;
3224 u64 addr = 0x0;
3225
1ee6dd77
RB		 3226 struct s2io_nic *sp = dev->priv;
3227 struct stat_block *stat_info = sp->mac_control.stats_info;
bd1034f0
AR		 3228
3229 /* Check the communication with the MDIO slave */
3230 addr = 0x0000;
3231 val64 = 0x0;
3232 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3233 if((val64 == 0xFFFF) || (val64 == 0x0000))
3234 {
3235 DBG_PRINT(ERR_DBG, "ERR: MDIO slave access failed - "
3236 "Returned %llx\n", (unsigned long long)val64);
3237 return;
3238 }
3239
3240 /* Check for the expecte value of 2040 at PMA address 0x0000 */
3241 if(val64 != 0x2040)
3242 {
3243 DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - ");
3244 DBG_PRINT(ERR_DBG, "Returned: %llx- Expected: 0x2040\n",
3245 (unsigned long long)val64);
3246 return;
3247 }
3248
3249 /* Loading the DOM register to MDIO register */
3250 addr = 0xA100;
3251 s2io_mdio_write(MDIO_MMD_PMA_DEV_ADDR, addr, val16, dev);
3252 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3253
3254 /* Reading the Alarm flags */
3255 addr = 0xA070;
3256 val64 = 0x0;
3257 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3258
3259 flag = CHECKBIT(val64, 0x7);
3260 type = 1;
3261 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_transceiver_temp_high,
3262 &stat_info->xpak_stat.xpak_regs_stat,
3263 0x0, flag, type);
3264
3265 if(CHECKBIT(val64, 0x6))
3266 stat_info->xpak_stat.alarm_transceiver_temp_low++;
3267
3268 flag = CHECKBIT(val64, 0x3);
3269 type = 2;
3270 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_bias_current_high,
3271 &stat_info->xpak_stat.xpak_regs_stat,
3272 0x2, flag, type);
3273
3274 if(CHECKBIT(val64, 0x2))
3275 stat_info->xpak_stat.alarm_laser_bias_current_low++;
3276
3277 flag = CHECKBIT(val64, 0x1);
3278 type = 3;
3279 s2io_chk_xpak_counter(&stat_info->xpak_stat.alarm_laser_output_power_high,
3280 &stat_info->xpak_stat.xpak_regs_stat,
3281 0x4, flag, type);
3282
3283 if(CHECKBIT(val64, 0x0))
3284 stat_info->xpak_stat.alarm_laser_output_power_low++;
3285
3286 /* Reading the Warning flags */
3287 addr = 0xA074;
3288 val64 = 0x0;
3289 val64 = s2io_mdio_read(MDIO_MMD_PMA_DEV_ADDR, addr, dev);
3290
3291 if(CHECKBIT(val64, 0x7))
3292 stat_info->xpak_stat.warn_transceiver_temp_high++;
3293
3294 if(CHECKBIT(val64, 0x6))
3295 stat_info->xpak_stat.warn_transceiver_temp_low++;
3296
3297 if(CHECKBIT(val64, 0x3))
3298 stat_info->xpak_stat.warn_laser_bias_current_high++;
3299
3300 if(CHECKBIT(val64, 0x2))
3301 stat_info->xpak_stat.warn_laser_bias_current_low++;
3302
3303 if(CHECKBIT(val64, 0x1))
3304 stat_info->xpak_stat.warn_laser_output_power_high++;
3305
3306 if(CHECKBIT(val64, 0x0))
3307 stat_info->xpak_stat.warn_laser_output_power_low++;
3308}
3309
20346722 3310/**
1da177e4 3311 * wait_for_cmd_complete - waits for a command to complete.
20346722 3312 * @sp : private member of the device structure, which is a pointer to the
1da177e4 3313 * s2io_nic structure.
20346722
K		 3314 * Description: Function that waits for a command to Write into RMAC
3315 * ADDR DATA registers to be completed and returns either success or
3316 * error depending on whether the command was complete or not.
1da177e4
LT		 3317 * Return value:
3318 * SUCCESS on success and FAILURE on failure.
3319 */
3320
9fc93a41
SS		 3321static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3322 int bit_state)
1da177e4 3323{
9fc93a41 3324 int ret = FAILURE, cnt = 0, delay = 1;
1da177e4
LT		 3325 u64 val64;
3326
9fc93a41
SS		 3327 if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3328 return FAILURE;
3329
3330 do {
c92ca04b 3331 val64 = readq(addr);
9fc93a41
SS		 3332 if (bit_state == S2IO_BIT_RESET) {
3333 if (!(val64 & busy_bit)) {
3334 ret = SUCCESS;
3335 break;
3336 }
3337 } else {
3338 if (!(val64 & busy_bit)) {
3339 ret = SUCCESS;
3340 break;
3341 }
1da177e4 3342 }
c92ca04b
AR		 3343
3344 if(in_interrupt())
9fc93a41 3345 mdelay(delay);
c92ca04b 3346 else
9fc93a41 3347 msleep(delay);
c92ca04b 3348
9fc93a41
SS		 3349 if (++cnt >= 10)
3350 delay = 50;
3351 } while (cnt < 20);
1da177e4
LT		 3352 return ret;
3353}
19a60522
SS		 3354/*
3355 * check_pci_device_id - Checks if the device id is supported
3356 * @id : device id
3357 * Description: Function to check if the pci device id is supported by driver.
3358 * Return value: Actual device id if supported else PCI_ANY_ID
3359 */
3360static u16 check_pci_device_id(u16 id)
3361{
3362 switch (id) {
3363 case PCI_DEVICE_ID_HERC_WIN:
3364 case PCI_DEVICE_ID_HERC_UNI:
3365 return XFRAME_II_DEVICE;
3366 case PCI_DEVICE_ID_S2IO_UNI:
3367 case PCI_DEVICE_ID_S2IO_WIN:
3368 return XFRAME_I_DEVICE;
3369 default:
3370 return PCI_ANY_ID;
3371 }
3372}
1da177e4 3373
20346722
K		 3374/**
3375 * s2io_reset - Resets the card.
1da177e4
LT		 3376 * @sp : private member of the device structure.
3377 * Description: Function to Reset the card. This function then also
20346722 3378 * restores the previously saved PCI configuration space registers as
1da177e4
LT		 3379 * the card reset also resets the configuration space.
3380 * Return value:
3381 * void.
3382 */
3383
1ee6dd77 3384static void s2io_reset(struct s2io_nic * sp)
1da177e4 3385{
1ee6dd77 3386 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 3387 u64 val64;
5e25b9dd 3388 u16 subid, pci_cmd;
19a60522
SS		 3389 int i;
3390 u16 val16;
491976b2
SH		 3391 unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3392 unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3393
19a60522
SS		 3394 DBG_PRINT(INIT_DBG,"%s - Resetting XFrame card %s\n",
3395 __FUNCTION__, sp->dev->name);
1da177e4 3396
0b1f7ebe 3397 /* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
e960fc5c 3398 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
0b1f7ebe 3399
1da177e4
LT		 3400 val64 = SW_RESET_ALL;
3401 writeq(val64, &bar0->sw_reset);
c92ca04b
AR		 3402 if (strstr(sp->product_name, "CX4")) {
3403 msleep(750);
3404 }
19a60522
SS		 3405 msleep(250);
3406 for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
1da177e4 3407
19a60522
SS		 3408 /* Restore the PCI state saved during initialization. */
3409 pci_restore_state(sp->pdev);
3410 pci_read_config_word(sp->pdev, 0x2, &val16);
3411 if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3412 break;
3413 msleep(200);
3414 }
1da177e4 3415
19a60522
SS		 3416 if (check_pci_device_id(val16) == (u16)PCI_ANY_ID) {
3417 DBG_PRINT(ERR_DBG,"%s SW_Reset failed!\n", __FUNCTION__);
3418 }
3419
3420 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3421
3422 s2io_init_pci(sp);
1da177e4 3423
20346722
K		 3424 /* Set swapper to enable I/O register access */
3425 s2io_set_swapper(sp);
3426
faa4f796
SH		 3427 /* restore mac_addr entries */
3428 do_s2io_restore_unicast_mc(sp);
3429
cc6e7c44
RA		 3430 /* Restore the MSIX table entries from local variables */
3431 restore_xmsi_data(sp);
3432
5e25b9dd 3433 /* Clear certain PCI/PCI-X fields after reset */
303bcb4b 3434 if (sp->device_type == XFRAME_II_DEVICE) {
b41477f3 3435 /* Clear "detected parity error" bit */
303bcb4b 3436 pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
5e25b9dd 3437
303bcb4b
K		 3438 /* Clearing PCIX Ecc status register */
3439 pci_write_config_dword(sp->pdev, 0x68, 0x7C);
5e25b9dd 3440
303bcb4b 3441 /* Clearing PCI_STATUS error reflected here */
b7b5a128 3442 writeq(s2BIT(62), &bar0->txpic_int_reg);
303bcb4b 3443 }
5e25b9dd 3444
20346722
K		 3445 /* Reset device statistics maintained by OS */
3446 memset(&sp->stats, 0, sizeof (struct net_device_stats));
8a4bdbaa 3447
491976b2
SH		 3448 up_cnt = sp->mac_control.stats_info->sw_stat.link_up_cnt;
3449 down_cnt = sp->mac_control.stats_info->sw_stat.link_down_cnt;
3450 up_time = sp->mac_control.stats_info->sw_stat.link_up_time;
3451 down_time = sp->mac_control.stats_info->sw_stat.link_down_time;
363dc367 3452 reset_cnt = sp->mac_control.stats_info->sw_stat.soft_reset_cnt;
491976b2
SH		 3453 mem_alloc_cnt = sp->mac_control.stats_info->sw_stat.mem_allocated;
3454 mem_free_cnt = sp->mac_control.stats_info->sw_stat.mem_freed;
3455 watchdog_cnt = sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt;
3456 /* save link up/down time/cnt, reset/memory/watchdog cnt */
363dc367 3457 memset(sp->mac_control.stats_info, 0, sizeof(struct stat_block));
491976b2
SH		 3458 /* restore link up/down time/cnt, reset/memory/watchdog cnt */
3459 sp->mac_control.stats_info->sw_stat.link_up_cnt = up_cnt;
3460 sp->mac_control.stats_info->sw_stat.link_down_cnt = down_cnt;
3461 sp->mac_control.stats_info->sw_stat.link_up_time = up_time;
3462 sp->mac_control.stats_info->sw_stat.link_down_time = down_time;
363dc367 3463 sp->mac_control.stats_info->sw_stat.soft_reset_cnt = reset_cnt;
491976b2
SH		 3464 sp->mac_control.stats_info->sw_stat.mem_allocated = mem_alloc_cnt;
3465 sp->mac_control.stats_info->sw_stat.mem_freed = mem_free_cnt;
3466 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt = watchdog_cnt;
20346722 3467
1da177e4
LT		 3468 /* SXE-002: Configure link and activity LED to turn it off */
3469 subid = sp->pdev->subsystem_device;
541ae68f
K		 3470 if (((subid & 0xFF) >= 0x07) &&
3471 (sp->device_type == XFRAME_I_DEVICE)) {
1da177e4
LT		 3472 val64 = readq(&bar0->gpio_control);
3473 val64 |= 0x0000800000000000ULL;
3474 writeq(val64, &bar0->gpio_control);
3475 val64 = 0x0411040400000000ULL;
509a2671 3476 writeq(val64, (void __iomem *)bar0 + 0x2700);
1da177e4
LT		 3477 }
3478
541ae68f
K		 3479 /*
3480 * Clear spurious ECC interrupts that would have occured on
3481 * XFRAME II cards after reset.
3482 */
3483 if (sp->device_type == XFRAME_II_DEVICE) {
3484 val64 = readq(&bar0->pcc_err_reg);
3485 writeq(val64, &bar0->pcc_err_reg);
3486 }
3487
1da177e4
LT		 3488 sp->device_enabled_once = FALSE;
3489}
3490
3491/**
20346722
K		 3492 * s2io_set_swapper - to set the swapper controle on the card
3493 * @sp : private member of the device structure,
1da177e4 3494 * pointer to the s2io_nic structure.
20346722 3495 * Description: Function to set the swapper control on the card
1da177e4
LT		 3496 * correctly depending on the 'endianness' of the system.
3497 * Return value:
3498 * SUCCESS on success and FAILURE on failure.
3499 */
3500
1ee6dd77 3501static int s2io_set_swapper(struct s2io_nic * sp)
1da177e4
LT		 3502{
3503 struct net_device *dev = sp->dev;
1ee6dd77 3504 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 3505 u64 val64, valt, valr;
3506
20346722 3507 /*
1da177e4
LT		 3508 * Set proper endian settings and verify the same by reading
3509 * the PIF Feed-back register.
3510 */
3511
3512 val64 = readq(&bar0->pif_rd_swapper_fb);
3513 if (val64 != 0x0123456789ABCDEFULL) {
3514 int i = 0;
3515 u64 value[] = { 0xC30000C3C30000C3ULL, /* FE=1, SE=1 */
3516 0x8100008181000081ULL, /* FE=1, SE=0 */
3517 0x4200004242000042ULL, /* FE=0, SE=1 */
3518 0}; /* FE=0, SE=0 */
3519
3520 while(i<4) {
3521 writeq(value[i], &bar0->swapper_ctrl);
3522 val64 = readq(&bar0->pif_rd_swapper_fb);
3523 if (val64 == 0x0123456789ABCDEFULL)
3524 break;
3525 i++;
3526 }
3527 if (i == 4) {
3528 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3529 dev->name);
3530 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3531 (unsigned long long) val64);
3532 return FAILURE;
3533 }
3534 valr = value[i];
3535 } else {
3536 valr = readq(&bar0->swapper_ctrl);
3537 }
3538
3539 valt = 0x0123456789ABCDEFULL;
3540 writeq(valt, &bar0->xmsi_address);
3541 val64 = readq(&bar0->xmsi_address);
3542
3543 if(val64 != valt) {
3544 int i = 0;
3545 u64 value[] = { 0x00C3C30000C3C300ULL, /* FE=1, SE=1 */
3546 0x0081810000818100ULL, /* FE=1, SE=0 */
3547 0x0042420000424200ULL, /* FE=0, SE=1 */
3548 0}; /* FE=0, SE=0 */
3549
3550 while(i<4) {
3551 writeq((value[i] | valr), &bar0->swapper_ctrl);
3552 writeq(valt, &bar0->xmsi_address);
3553 val64 = readq(&bar0->xmsi_address);
3554 if(val64 == valt)
3555 break;
3556 i++;
3557 }
3558 if(i == 4) {
20346722 3559 unsigned long long x = val64;
1da177e4 3560 DBG_PRINT(ERR_DBG, "Write failed, Xmsi_addr ");
20346722 3561 DBG_PRINT(ERR_DBG, "reads:0x%llx\n", x);
1da177e4
LT		 3562 return FAILURE;
3563 }
3564 }
3565 val64 = readq(&bar0->swapper_ctrl);
3566 val64 &= 0xFFFF000000000000ULL;
3567
3568#ifdef __BIG_ENDIAN
20346722
K		 3569 /*
3570 * The device by default set to a big endian format, so a
1da177e4
LT		 3571 * big endian driver need not set anything.
3572 */
3573 val64 |= (SWAPPER_CTRL_TXP_FE |
3574 SWAPPER_CTRL_TXP_SE |
3575 SWAPPER_CTRL_TXD_R_FE |
3576 SWAPPER_CTRL_TXD_W_FE |
3577 SWAPPER_CTRL_TXF_R_FE |
3578 SWAPPER_CTRL_RXD_R_FE |
3579 SWAPPER_CTRL_RXD_W_FE |
3580 SWAPPER_CTRL_RXF_W_FE |
3581 SWAPPER_CTRL_XMSI_FE |
1da177e4 3582 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3583 if (sp->config.intr_type == INTA)
cc6e7c44 3584 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3585 writeq(val64, &bar0->swapper_ctrl);
3586#else
20346722 3587 /*
1da177e4 3588 * Initially we enable all bits to make it accessible by the
20346722 3589 * driver, then we selectively enable only those bits that
1da177e4
LT		 3590 * we want to set.
3591 */
3592 val64 |= (SWAPPER_CTRL_TXP_FE |
3593 SWAPPER_CTRL_TXP_SE |
3594 SWAPPER_CTRL_TXD_R_FE |
3595 SWAPPER_CTRL_TXD_R_SE |
3596 SWAPPER_CTRL_TXD_W_FE |
3597 SWAPPER_CTRL_TXD_W_SE |
3598 SWAPPER_CTRL_TXF_R_FE |
3599 SWAPPER_CTRL_RXD_R_FE |
3600 SWAPPER_CTRL_RXD_R_SE |
3601 SWAPPER_CTRL_RXD_W_FE |
3602 SWAPPER_CTRL_RXD_W_SE |
3603 SWAPPER_CTRL_RXF_W_FE |
3604 SWAPPER_CTRL_XMSI_FE |
1da177e4 3605 SWAPPER_CTRL_STATS_FE | SWAPPER_CTRL_STATS_SE);
eaae7f72 3606 if (sp->config.intr_type == INTA)
cc6e7c44 3607 val64 |= SWAPPER_CTRL_XMSI_SE;
1da177e4
LT		 3608 writeq(val64, &bar0->swapper_ctrl);
3609#endif
3610 val64 = readq(&bar0->swapper_ctrl);
3611
20346722
K		 3612 /*
3613 * Verifying if endian settings are accurate by reading a
1da177e4
LT		 3614 * feedback register.
3615 */
3616 val64 = readq(&bar0->pif_rd_swapper_fb);
3617 if (val64 != 0x0123456789ABCDEFULL) {
3618 /* Endian settings are incorrect, calls for another dekko. */
3619 DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, ",
3620 dev->name);
3621 DBG_PRINT(ERR_DBG, "feedback read %llx\n",
3622 (unsigned long long) val64);
3623 return FAILURE;
3624 }
3625
3626 return SUCCESS;
3627}
3628
1ee6dd77 3629static int wait_for_msix_trans(struct s2io_nic *nic, int i)
cc6e7c44 3630{
1ee6dd77 3631 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3632 u64 val64;
3633 int ret = 0, cnt = 0;
3634
3635 do {
3636 val64 = readq(&bar0->xmsi_access);
b7b5a128 3637 if (!(val64 & s2BIT(15)))
cc6e7c44
RA		 3638 break;
3639 mdelay(1);
3640 cnt++;
3641 } while(cnt < 5);
3642 if (cnt == 5) {
3643 DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3644 ret = 1;
3645 }
3646
3647 return ret;
3648}
3649
1ee6dd77 3650static void restore_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3651{
1ee6dd77 3652 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3653 u64 val64;
3654 int i;
3655
75c30b13 3656 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
cc6e7c44
RA		 3657 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3658 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
b7b5a128 3659 val64 = (s2BIT(7) | s2BIT(15) | vBIT(i, 26, 6));
cc6e7c44
RA		 3660 writeq(val64, &bar0->xmsi_access);
3661 if (wait_for_msix_trans(nic, i)) {
3662 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3663 continue;
3664 }
3665 }
3666}
3667
1ee6dd77 3668static void store_xmsi_data(struct s2io_nic *nic)
cc6e7c44 3669{
1ee6dd77 3670 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3671 u64 val64, addr, data;
3672 int i;
3673
3674 /* Store and display */
75c30b13 3675 for (i=0; i < MAX_REQUESTED_MSI_X; i++) {
b7b5a128 3676 val64 = (s2BIT(15) | vBIT(i, 26, 6));
cc6e7c44
RA		 3677 writeq(val64, &bar0->xmsi_access);
3678 if (wait_for_msix_trans(nic, i)) {
3679 DBG_PRINT(ERR_DBG, "failed in %s\n", __FUNCTION__);
3680 continue;
3681 }
3682 addr = readq(&bar0->xmsi_address);
3683 data = readq(&bar0->xmsi_data);
3684 if (addr && data) {
3685 nic->msix_info[i].addr = addr;
3686 nic->msix_info[i].data = data;
3687 }
3688 }
3689}
3690
1ee6dd77 3691static int s2io_enable_msi_x(struct s2io_nic *nic)
cc6e7c44 3692{
1ee6dd77 3693 struct XENA_dev_config __iomem *bar0 = nic->bar0;
cc6e7c44
RA		 3694 u64 tx_mat, rx_mat;
3695 u16 msi_control; /* Temp variable */
3696 int ret, i, j, msix_indx = 1;
3697
bd684e43 3698 nic->entries = kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct msix_entry),
cc6e7c44 3699 GFP_KERNEL);
bd684e43 3700 if (!nic->entries) {
491976b2
SH		 3701 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n", \
3702 __FUNCTION__);
c53d4945 3703 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44
RA		 3704 return -ENOMEM;
3705 }
8a4bdbaa 3706 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 3707 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3708
3709 nic->s2io_entries =
bd684e43 3710 kcalloc(MAX_REQUESTED_MSI_X, sizeof(struct s2io_msix_entry),
cc6e7c44 3711 GFP_KERNEL);
bd684e43 3712 if (!nic->s2io_entries) {
8a4bdbaa 3713 DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
491976b2 3714 __FUNCTION__);
c53d4945 3715 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
cc6e7c44 3716 kfree(nic->entries);
8a4bdbaa 3717 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3718 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44
RA		 3719 return -ENOMEM;
3720 }
8a4bdbaa 3721 nic->mac_control.stats_info->sw_stat.mem_allocated
491976b2 3722 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3723
3724 for (i=0; i< MAX_REQUESTED_MSI_X; i++) {
3725 nic->entries[i].entry = i;
3726 nic->s2io_entries[i].entry = i;
3727 nic->s2io_entries[i].arg = NULL;
3728 nic->s2io_entries[i].in_use = 0;
3729 }
3730
3731 tx_mat = readq(&bar0->tx_mat0_n[0]);
3732 for (i=0; i<nic->config.tx_fifo_num; i++, msix_indx++) {
3733 tx_mat |= TX_MAT_SET(i, msix_indx);
3734 nic->s2io_entries[msix_indx].arg = &nic->mac_control.fifos[i];
3735 nic->s2io_entries[msix_indx].type = MSIX_FIFO_TYPE;
3736 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
3737 }
3738 writeq(tx_mat, &bar0->tx_mat0_n[0]);
3739
8a4bdbaa
SS		 3740 rx_mat = readq(&bar0->rx_mat);
3741 for (j = 0; j < nic->config.rx_ring_num; j++, msix_indx++) {
3742 rx_mat |= RX_MAT_SET(j, msix_indx);
3743 nic->s2io_entries[msix_indx].arg
3744 = &nic->mac_control.rings[j];
3745 nic->s2io_entries[msix_indx].type = MSIX_RING_TYPE;
3746 nic->s2io_entries[msix_indx].in_use = MSIX_FLG;
cc6e7c44 3747 }
8a4bdbaa 3748 writeq(rx_mat, &bar0->rx_mat);
cc6e7c44 3749
c92ca04b 3750 nic->avail_msix_vectors = 0;
cc6e7c44 3751 ret = pci_enable_msix(nic->pdev, nic->entries, MAX_REQUESTED_MSI_X);
c92ca04b
AR		 3752 /* We fail init if error or we get less vectors than min required */
3753 if (ret >= (nic->config.tx_fifo_num + nic->config.rx_ring_num + 1)) {
3754 nic->avail_msix_vectors = ret;
3755 ret = pci_enable_msix(nic->pdev, nic->entries, ret);
3756 }
cc6e7c44
RA		 3757 if (ret) {
3758 DBG_PRINT(ERR_DBG, "%s: Enabling MSIX failed\n", nic->dev->name);
3759 kfree(nic->entries);
8a4bdbaa 3760 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3761 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
cc6e7c44 3762 kfree(nic->s2io_entries);
8a4bdbaa 3763 nic->mac_control.stats_info->sw_stat.mem_freed
491976b2 3764 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
cc6e7c44
RA		 3765 nic->entries = NULL;
3766 nic->s2io_entries = NULL;
c92ca04b 3767 nic->avail_msix_vectors = 0;
cc6e7c44
RA		 3768 return -ENOMEM;
3769 }
c92ca04b
AR		 3770 if (!nic->avail_msix_vectors)
3771 nic->avail_msix_vectors = MAX_REQUESTED_MSI_X;
cc6e7c44
RA		 3772
3773 /*
3774 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3775 * in the herc NIC. (Temp change, needs to be removed later)
3776 */
3777 pci_read_config_word(nic->pdev, 0x42, &msi_control);
3778 msi_control |= 0x1; /* Enable MSI */
3779 pci_write_config_word(nic->pdev, 0x42, msi_control);
3780
3781 return 0;
3782}
3783
8abc4d5b 3784/* Handle software interrupt used during MSI(X) test */
33390a70 3785static irqreturn_t s2io_test_intr(int irq, void *dev_id)
8abc4d5b
SS		 3786{
3787 struct s2io_nic *sp = dev_id;
3788
3789 sp->msi_detected = 1;
3790 wake_up(&sp->msi_wait);
3791
3792 return IRQ_HANDLED;
3793}
3794
3795/* Test interrupt path by forcing a a software IRQ */
33390a70 3796static int s2io_test_msi(struct s2io_nic *sp)
8abc4d5b
SS		 3797{
3798 struct pci_dev *pdev = sp->pdev;
3799 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3800 int err;
3801 u64 val64, saved64;
3802
3803 err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3804 sp->name, sp);
3805 if (err) {
3806 DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3807 sp->dev->name, pci_name(pdev), pdev->irq);
3808 return err;
3809 }
3810
3811 init_waitqueue_head (&sp->msi_wait);
3812 sp->msi_detected = 0;
3813
3814 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3815 val64 |= SCHED_INT_CTRL_ONE_SHOT;
3816 val64 |= SCHED_INT_CTRL_TIMER_EN;
3817 val64 |= SCHED_INT_CTRL_INT2MSI(1);
3818 writeq(val64, &bar0->scheduled_int_ctrl);
3819
3820 wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3821
3822 if (!sp->msi_detected) {
3823 /* MSI(X) test failed, go back to INTx mode */
2450022a 3824 DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
8abc4d5b
SS		 3825 "using MSI(X) during test\n", sp->dev->name,
3826 pci_name(pdev));
3827
3828 err = -EOPNOTSUPP;
3829 }
3830
3831 free_irq(sp->entries[1].vector, sp);
3832
3833 writeq(saved64, &bar0->scheduled_int_ctrl);
3834
3835 return err;
3836}
18b2b7bd
SH		 3837
3838static void remove_msix_isr(struct s2io_nic *sp)
3839{
3840 int i;
3841 u16 msi_control;
3842
3843 for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3844 if (sp->s2io_entries[i].in_use ==
3845 MSIX_REGISTERED_SUCCESS) {
3846 int vector = sp->entries[i].vector;
3847 void *arg = sp->s2io_entries[i].arg;
3848 free_irq(vector, arg);
3849 }
3850 }
3851
3852 kfree(sp->entries);
3853 kfree(sp->s2io_entries);
3854 sp->entries = NULL;
3855 sp->s2io_entries = NULL;
3856
3857 pci_read_config_word(sp->pdev, 0x42, &msi_control);
3858 msi_control &= 0xFFFE; /* Disable MSI */
3859 pci_write_config_word(sp->pdev, 0x42, msi_control);
3860
3861 pci_disable_msix(sp->pdev);
3862}
3863
3864static void remove_inta_isr(struct s2io_nic *sp)
3865{
3866 struct net_device *dev = sp->dev;
3867
3868 free_irq(sp->pdev->irq, dev);
3869}
3870
1da177e4
LT		 3871/* ********************************************************* *
3872 * Functions defined below concern the OS part of the driver *
3873 * ********************************************************* */
3874
20346722 3875/**
1da177e4
LT		 3876 * s2io_open - open entry point of the driver
3877 * @dev : pointer to the device structure.
3878 * Description:
3879 * This function is the open entry point of the driver. It mainly calls a
3880 * function to allocate Rx buffers and inserts them into the buffer
20346722 3881 * descriptors and then enables the Rx part of the NIC.
1da177e4
LT		 3882 * Return value:
3883 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3884 * file on failure.
3885 */
3886
ac1f60db 3887static int s2io_open(struct net_device *dev)
1da177e4 3888{
1ee6dd77 3889 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 3890 int err = 0;
3891
20346722
K		 3892 /*
3893 * Make sure you have link off by default every time
1da177e4
LT		 3894 * Nic is initialized
3895 */
3896 netif_carrier_off(dev);
0b1f7ebe 3897 sp->last_link_state = 0;
1da177e4 3898
eaae7f72 3899 if (sp->config.intr_type == MSI_X) {
8abc4d5b
SS		 3900 int ret = s2io_enable_msi_x(sp);
3901
3902 if (!ret) {
8abc4d5b 3903 ret = s2io_test_msi(sp);
8abc4d5b 3904 /* rollback MSI-X, will re-enable during add_isr() */
18b2b7bd 3905 remove_msix_isr(sp);
8abc4d5b
SS		 3906 }
3907 if (ret) {
3908
3909 DBG_PRINT(ERR_DBG,
3910 "%s: MSI-X requested but failed to enable\n",
3911 dev->name);
eaae7f72 3912 sp->config.intr_type = INTA;
8abc4d5b
SS		 3913 }
3914 }
3915
c77dd43e 3916 /* NAPI doesn't work well with MSI(X) */
eaae7f72 3917 if (sp->config.intr_type != INTA) {
c77dd43e
SS		 3918 if(sp->config.napi)
3919 sp->config.napi = 0;
3920 }
3921
1da177e4 3922 /* Initialize H/W and enable interrupts */
c92ca04b
AR		 3923 err = s2io_card_up(sp);
3924 if (err) {
1da177e4
LT		 3925 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3926 dev->name);
e6a8fee2 3927 goto hw_init_failed;
1da177e4
LT		 3928 }
3929
2fd37688 3930 if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
1da177e4 3931 DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
e6a8fee2 3932 s2io_card_down(sp);
20346722 3933 err = -ENODEV;
e6a8fee2 3934 goto hw_init_failed;
1da177e4
LT		 3935 }
3936
3937 netif_start_queue(dev);
3938 return 0;
20346722 3939
20346722 3940hw_init_failed:
eaae7f72 3941 if (sp->config.intr_type == MSI_X) {
491976b2 3942 if (sp->entries) {
cc6e7c44 3943 kfree(sp->entries);
8a4bdbaa 3944 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2
SH		 3945 += (MAX_REQUESTED_MSI_X * sizeof(struct msix_entry));
3946 }
3947 if (sp->s2io_entries) {
cc6e7c44 3948 kfree(sp->s2io_entries);
8a4bdbaa 3949 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2
SH		 3950 += (MAX_REQUESTED_MSI_X * sizeof(struct s2io_msix_entry));
3951 }
cc6e7c44 3952 }
20346722 3953 return err;
1da177e4
LT		 3954}
3955
3956/**
3957 * s2io_close -close entry point of the driver
3958 * @dev : device pointer.
3959 * Description:
3960 * This is the stop entry point of the driver. It needs to undo exactly
3961 * whatever was done by the open entry point,thus it's usually referred to
3962 * as the close function.Among other things this function mainly stops the
3963 * Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3964 * Return value:
3965 * 0 on success and an appropriate (-)ve integer as defined in errno.h
3966 * file on failure.
3967 */
3968
ac1f60db 3969static int s2io_close(struct net_device *dev)
1da177e4 3970{
1ee6dd77 3971 struct s2io_nic *sp = dev->priv;
faa4f796
SH		 3972 struct config_param *config = &sp->config;
3973 u64 tmp64;
3974 int offset;
cc6e7c44 3975
9f74ffde
SH		 3976 /* Return if the device is already closed *
3977 * Can happen when s2io_card_up failed in change_mtu *
3978 */
3979 if (!is_s2io_card_up(sp))
3980 return 0;
3981
1da177e4 3982 netif_stop_queue(dev);
faa4f796
SH		 3983
3984 /* delete all populated mac entries */
3985 for (offset = 1; offset < config->max_mc_addr; offset++) {
3986 tmp64 = do_s2io_read_unicast_mc(sp, offset);
3987 if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
3988 do_s2io_delete_unicast_mc(sp, tmp64);
3989 }
3990
1da177e4 3991 /* Reset card, kill tasklet and free Tx and Rx buffers. */
e6a8fee2 3992 s2io_card_down(sp);
cc6e7c44 3993
1da177e4
LT		 3994 return 0;
3995}
3996
3997/**
3998 * s2io_xmit - Tx entry point of te driver
3999 * @skb : the socket buffer containing the Tx data.
4000 * @dev : device pointer.
4001 * Description :
4002 * This function is the Tx entry point of the driver. S2IO NIC supports
4003 * certain protocol assist features on Tx side, namely CSO, S/G, LSO.
4004 * NOTE: when device cant queue the pkt,just the trans_start variable will
4005 * not be upadted.
4006 * Return value:
4007 * 0 on success & 1 on failure.
4008 */
4009
ac1f60db 4010static int s2io_xmit(struct sk_buff *skb, struct net_device *dev)
1da177e4 4011{
1ee6dd77 4012 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 4013 u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4014 register u64 val64;
1ee6dd77
RB		 4015 struct TxD *txdp;
4016 struct TxFIFO_element __iomem *tx_fifo;
2fda096d 4017 unsigned long flags = 0;
be3a6b02
K		 4018 u16 vlan_tag = 0;
4019 int vlan_priority = 0;
2fda096d 4020 struct fifo_info *fifo = NULL;
1ee6dd77 4021 struct mac_info *mac_control;
1da177e4 4022 struct config_param *config;
75c30b13 4023 int offload_type;
491abf25 4024 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
1da177e4
LT		 4025
4026 mac_control = &sp->mac_control;
4027 config = &sp->config;
4028
20346722 4029 DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
491976b2
SH		 4030
4031 if (unlikely(skb->len <= 0)) {
4032 DBG_PRINT(TX_DBG, "%s:Buffer has no data..\n", dev->name);
4033 dev_kfree_skb_any(skb);
4034 return 0;
2fda096d 4035 }
491976b2 4036
92b84437 4037 if (!is_s2io_card_up(sp)) {
20346722 4038 DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
1da177e4 4039 dev->name);
20346722
K		 4040 dev_kfree_skb(skb);
4041 return 0;
1da177e4
LT		 4042 }
4043
4044 queue = 0;
be3a6b02
K		 4045 /* Get Fifo number to Transmit based on vlan priority */
4046 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4047 vlan_tag = vlan_tx_tag_get(skb);
4048 vlan_priority = vlan_tag >> 13;
4049 queue = config->fifo_mapping[vlan_priority];
4050 }
4051
2fda096d
SR		 4052 fifo = &mac_control->fifos[queue];
4053 spin_lock_irqsave(&fifo->tx_lock, flags);
4054 put_off = (u16) fifo->tx_curr_put_info.offset;
4055 get_off = (u16) fifo->tx_curr_get_info.offset;
4056 txdp = (struct TxD *) fifo->list_info[put_off].list_virt_addr;
20346722 4057
2fda096d 4058 queue_len = fifo->tx_curr_put_info.fifo_len + 1;
1da177e4 4059 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9
AR		 4060 if (txdp->Host_Control ||
4061 ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
776bd20f 4062 DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
1da177e4
LT		 4063 netif_stop_queue(dev);
4064 dev_kfree_skb(skb);
2fda096d 4065 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 4066 return 0;
4067 }
0b1f7ebe 4068
75c30b13 4069 offload_type = s2io_offload_type(skb);
75c30b13 4070 if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
1da177e4 4071 txdp->Control_1 |= TXD_TCP_LSO_EN;
75c30b13 4072 txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
1da177e4 4073 }
84fa7933 4074 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1da177e4
LT		 4075 txdp->Control_2 |=
4076 (TXD_TX_CKO_IPV4_EN | TXD_TX_CKO_TCP_EN |
4077 TXD_TX_CKO_UDP_EN);
4078 }
fed5eccd
AR		 4079 txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4080 txdp->Control_1 |= TXD_LIST_OWN_XENA;
2fda096d 4081 txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
d8892c6e 4082
be3a6b02
K		 4083 if (sp->vlgrp && vlan_tx_tag_present(skb)) {
4084 txdp->Control_2 |= TXD_VLAN_ENABLE;
4085 txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4086 }
4087
fed5eccd 4088 frg_len = skb->len - skb->data_len;
75c30b13 4089 if (offload_type == SKB_GSO_UDP) {
fed5eccd
AR		 4090 int ufo_size;
4091
75c30b13 4092 ufo_size = s2io_udp_mss(skb);
fed5eccd
AR		 4093 ufo_size &= ~7;
4094 txdp->Control_1 |= TXD_UFO_EN;
4095 txdp->Control_1 |= TXD_UFO_MSS(ufo_size);
4096 txdp->Control_1 |= TXD_BUFFER0_SIZE(8);
4097#ifdef __BIG_ENDIAN
2fda096d 4098 fifo->ufo_in_band_v[put_off] =
fed5eccd
AR		 4099 (u64)skb_shinfo(skb)->ip6_frag_id;
4100#else
2fda096d 4101 fifo->ufo_in_band_v[put_off] =
fed5eccd
AR		 4102 (u64)skb_shinfo(skb)->ip6_frag_id << 32;
4103#endif
2fda096d 4104 txdp->Host_Control = (unsigned long)fifo->ufo_in_band_v;
fed5eccd 4105 txdp->Buffer_Pointer = pci_map_single(sp->pdev,
2fda096d 4106 fifo->ufo_in_band_v,
fed5eccd 4107 sizeof(u64), PCI_DMA_TODEVICE);
491abf25
VP		 4108 if((txdp->Buffer_Pointer == 0) ||
4109 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4110 goto pci_map_failed;
fed5eccd 4111 txdp++;
fed5eccd 4112 }
1da177e4 4113
fed5eccd
AR		 4114 txdp->Buffer_Pointer = pci_map_single
4115 (sp->pdev, skb->data, frg_len, PCI_DMA_TODEVICE);
491abf25
VP		 4116 if((txdp->Buffer_Pointer == 0) ||
4117 (txdp->Buffer_Pointer == DMA_ERROR_CODE))
4118 goto pci_map_failed;
4119
fed5eccd
AR		 4120 txdp->Host_Control = (unsigned long) skb;
4121 txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
75c30b13 4122 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4123 txdp->Control_1 |= TXD_UFO_EN;
4124
4125 frg_cnt = skb_shinfo(skb)->nr_frags;
1da177e4
LT		 4126 /* For fragmented SKB. */
4127 for (i = 0; i < frg_cnt; i++) {
4128 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
0b1f7ebe
K		 4129 /* A '0' length fragment will be ignored */
4130 if (!frag->size)
4131 continue;
1da177e4
LT		 4132 txdp++;
4133 txdp->Buffer_Pointer = (u64) pci_map_page
4134 (sp->pdev, frag->page, frag->page_offset,
4135 frag->size, PCI_DMA_TODEVICE);
efd51b5c 4136 txdp->Control_1 = TXD_BUFFER0_SIZE(frag->size);
75c30b13 4137 if (offload_type == SKB_GSO_UDP)
fed5eccd 4138 txdp->Control_1 |= TXD_UFO_EN;
1da177e4
LT		 4139 }
4140 txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4141
75c30b13 4142 if (offload_type == SKB_GSO_UDP)
fed5eccd
AR		 4143 frg_cnt++; /* as Txd0 was used for inband header */
4144
1da177e4 4145 tx_fifo = mac_control->tx_FIFO_start[queue];
2fda096d 4146 val64 = fifo->list_info[put_off].list_phy_addr;
1da177e4
LT		 4147 writeq(val64, &tx_fifo->TxDL_Pointer);
4148
4149 val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4150 TX_FIFO_LAST_LIST);
75c30b13 4151 if (offload_type)
fed5eccd 4152 val64 |= TX_FIFO_SPECIAL_FUNC;
75c30b13 4153
1da177e4
LT		 4154 writeq(val64, &tx_fifo->List_Control);
4155
303bcb4b
K		 4156 mmiowb();
4157
1da177e4 4158 put_off++;
2fda096d 4159 if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
863c11a9 4160 put_off = 0;
2fda096d 4161 fifo->tx_curr_put_info.offset = put_off;
1da177e4
LT		 4162
4163 /* Avoid "put" pointer going beyond "get" pointer */
863c11a9 4164 if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
bd1034f0 4165 sp->mac_control.stats_info->sw_stat.fifo_full_cnt++;
1da177e4
LT		 4166 DBG_PRINT(TX_DBG,
4167 "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4168 put_off, get_off);
4169 netif_stop_queue(dev);
4170 }
491976b2 4171 mac_control->stats_info->sw_stat.mem_allocated += skb->truesize;
1da177e4 4172 dev->trans_start = jiffies;
2fda096d 4173 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4 4174
491abf25
VP		 4175 return 0;
4176pci_map_failed:
4177 stats->pci_map_fail_cnt++;
4178 netif_stop_queue(dev);
4179 stats->mem_freed += skb->truesize;
4180 dev_kfree_skb(skb);
2fda096d 4181 spin_unlock_irqrestore(&fifo->tx_lock, flags);
1da177e4
LT		 4182 return 0;
4183}
4184
25fff88e
K		 4185static void
4186s2io_alarm_handle(unsigned long data)
4187{
1ee6dd77 4188 struct s2io_nic *sp = (struct s2io_nic *)data;
8116f3cf 4189 struct net_device *dev = sp->dev;
25fff88e 4190
8116f3cf 4191 s2io_handle_errors(dev);
25fff88e
K		 4192 mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4193}
4194
1ee6dd77 4195static int s2io_chk_rx_buffers(struct s2io_nic *sp, int rng_n)
75c30b13
AR		 4196{
4197 int rxb_size, level;
4198
4199 if (!sp->lro) {
4200 rxb_size = atomic_read(&sp->rx_bufs_left[rng_n]);
4201 level = rx_buffer_level(sp, rxb_size, rng_n);
4202
4203 if ((level == PANIC) && (!TASKLET_IN_USE)) {
4204 int ret;
4205 DBG_PRINT(INTR_DBG, "%s: Rx BD hit ", __FUNCTION__);
4206 DBG_PRINT(INTR_DBG, "PANIC levels\n");
4207 if ((ret = fill_rx_buffers(sp, rng_n)) == -ENOMEM) {
0c61ed5f 4208 DBG_PRINT(INFO_DBG, "Out of memory in %s",
75c30b13
AR		 4209 __FUNCTION__);
4210 clear_bit(0, (&sp->tasklet_status));
4211 return -1;
4212 }
4213 clear_bit(0, (&sp->tasklet_status));
4214 } else if (level == LOW)
4215 tasklet_schedule(&sp->task);
4216
4217 } else if (fill_rx_buffers(sp, rng_n) == -ENOMEM) {
0c61ed5f
RV		 4218 DBG_PRINT(INFO_DBG, "%s:Out of memory", sp->dev->name);
4219 DBG_PRINT(INFO_DBG, " in Rx Intr!!\n");
75c30b13
AR		 4220 }
4221 return 0;
4222}
4223
7d12e780 4224static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
cc6e7c44 4225{
1ee6dd77
RB		 4226 struct ring_info *ring = (struct ring_info *)dev_id;
4227 struct s2io_nic *sp = ring->nic;
cc6e7c44 4228
596c5c97 4229 if (!is_s2io_card_up(sp))
92b84437 4230 return IRQ_HANDLED;
92b84437 4231
75c30b13
AR		 4232 rx_intr_handler(ring);
4233 s2io_chk_rx_buffers(sp, ring->ring_no);
7d3d0439 4234
cc6e7c44
RA		 4235 return IRQ_HANDLED;
4236}
4237
7d12e780 4238static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
cc6e7c44 4239{
1ee6dd77
RB		 4240 struct fifo_info *fifo = (struct fifo_info *)dev_id;
4241 struct s2io_nic *sp = fifo->nic;
cc6e7c44 4242
596c5c97 4243 if (!is_s2io_card_up(sp))
92b84437 4244 return IRQ_HANDLED;
92b84437 4245
cc6e7c44 4246 tx_intr_handler(fifo);
cc6e7c44
RA		 4247 return IRQ_HANDLED;
4248}
1ee6dd77 4249static void s2io_txpic_intr_handle(struct s2io_nic *sp)
a371a07d 4250{
1ee6dd77 4251 struct XENA_dev_config __iomem *bar0 = sp->bar0;
a371a07d
K		 4252 u64 val64;
4253
4254 val64 = readq(&bar0->pic_int_status);
4255 if (val64 & PIC_INT_GPIO) {
4256 val64 = readq(&bar0->gpio_int_reg);
4257 if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4258 (val64 & GPIO_INT_REG_LINK_UP)) {
c92ca04b
AR		 4259 /*
4260 * This is unstable state so clear both up/down
4261 * interrupt and adapter to re-evaluate the link state.
4262 */
a371a07d
K		 4263 val64 |= GPIO_INT_REG_LINK_DOWN;
4264 val64 |= GPIO_INT_REG_LINK_UP;
4265 writeq(val64, &bar0->gpio_int_reg);
a371a07d 4266 val64 = readq(&bar0->gpio_int_mask);
c92ca04b
AR		 4267 val64 &= ~(GPIO_INT_MASK_LINK_UP |
4268 GPIO_INT_MASK_LINK_DOWN);
a371a07d 4269 writeq(val64, &bar0->gpio_int_mask);
a371a07d 4270 }
c92ca04b
AR		 4271 else if (val64 & GPIO_INT_REG_LINK_UP) {
4272 val64 = readq(&bar0->adapter_status);
c92ca04b 4273 /* Enable Adapter */
19a60522
SS		 4274 val64 = readq(&bar0->adapter_control);
4275 val64 |= ADAPTER_CNTL_EN;
4276 writeq(val64, &bar0->adapter_control);
4277 val64 |= ADAPTER_LED_ON;
4278 writeq(val64, &bar0->adapter_control);
4279 if (!sp->device_enabled_once)
4280 sp->device_enabled_once = 1;
c92ca04b 4281
19a60522
SS		 4282 s2io_link(sp, LINK_UP);
4283 /*
4284 * unmask link down interrupt and mask link-up
4285 * intr
4286 */
4287 val64 = readq(&bar0->gpio_int_mask);
4288 val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4289 val64 |= GPIO_INT_MASK_LINK_UP;
4290 writeq(val64, &bar0->gpio_int_mask);
c92ca04b 4291
c92ca04b
AR		 4292 }else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4293 val64 = readq(&bar0->adapter_status);
19a60522
SS		 4294 s2io_link(sp, LINK_DOWN);
4295 /* Link is down so unmaks link up interrupt */
4296 val64 = readq(&bar0->gpio_int_mask);
4297 val64 &= ~GPIO_INT_MASK_LINK_UP;
4298 val64 |= GPIO_INT_MASK_LINK_DOWN;
4299 writeq(val64, &bar0->gpio_int_mask);
ac1f90d6
SS		 4300
4301 /* turn off LED */
4302 val64 = readq(&bar0->adapter_control);
4303 val64 = val64 &(~ADAPTER_LED_ON);
4304 writeq(val64, &bar0->adapter_control);
a371a07d
K		 4305 }
4306 }
c92ca04b 4307 val64 = readq(&bar0->gpio_int_mask);
a371a07d
K		 4308}
4309
8116f3cf
SS		 4310/**
4311 * do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4312 * @value: alarm bits
4313 * @addr: address value
4314 * @cnt: counter variable
4315 * Description: Check for alarm and increment the counter
4316 * Return Value:
4317 * 1 - if alarm bit set
4318 * 0 - if alarm bit is not set
4319 */
43b7c451 4320static int do_s2io_chk_alarm_bit(u64 value, void __iomem * addr,
8116f3cf
SS		 4321 unsigned long long *cnt)
4322{
4323 u64 val64;
4324 val64 = readq(addr);
4325 if ( val64 & value ) {
4326 writeq(val64, addr);
4327 (*cnt)++;
4328 return 1;
4329 }
4330 return 0;
4331
4332}
4333
4334/**
4335 * s2io_handle_errors - Xframe error indication handler
4336 * @nic: device private variable
4337 * Description: Handle alarms such as loss of link, single or
4338 * double ECC errors, critical and serious errors.
4339 * Return Value:
4340 * NONE
4341 */
4342static void s2io_handle_errors(void * dev_id)
4343{
4344 struct net_device *dev = (struct net_device *) dev_id;
4345 struct s2io_nic *sp = dev->priv;
4346 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4347 u64 temp64 = 0,val64=0;
4348 int i = 0;
4349
4350 struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4351 struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4352
92b84437 4353 if (!is_s2io_card_up(sp))
8116f3cf
SS		 4354 return;
4355
4356 if (pci_channel_offline(sp->pdev))
4357 return;
4358
4359 memset(&sw_stat->ring_full_cnt, 0,
4360 sizeof(sw_stat->ring_full_cnt));
4361
4362 /* Handling the XPAK counters update */
4363 if(stats->xpak_timer_count < 72000) {
4364 /* waiting for an hour */
4365 stats->xpak_timer_count++;
4366 } else {
4367 s2io_updt_xpak_counter(dev);
4368 /* reset the count to zero */
4369 stats->xpak_timer_count = 0;
4370 }
4371
4372 /* Handling link status change error Intr */
4373 if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4374 val64 = readq(&bar0->mac_rmac_err_reg);
4375 writeq(val64, &bar0->mac_rmac_err_reg);
4376 if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4377 schedule_work(&sp->set_link_task);
4378 }
4379
4380 /* In case of a serious error, the device will be Reset. */
4381 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4382 &sw_stat->serious_err_cnt))
4383 goto reset;
4384
4385 /* Check for data parity error */
4386 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4387 &sw_stat->parity_err_cnt))
4388 goto reset;
4389
4390 /* Check for ring full counter */
4391 if (sp->device_type == XFRAME_II_DEVICE) {
4392 val64 = readq(&bar0->ring_bump_counter1);
4393 for (i=0; i<4; i++) {
4394 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4395 temp64 >>= 64 - ((i+1)*16);
4396 sw_stat->ring_full_cnt[i] += temp64;
4397 }
4398
4399 val64 = readq(&bar0->ring_bump_counter2);
4400 for (i=0; i<4; i++) {
4401 temp64 = ( val64 & vBIT(0xFFFF,(i*16),16));
4402 temp64 >>= 64 - ((i+1)*16);
4403 sw_stat->ring_full_cnt[i+4] += temp64;
4404 }
4405 }
4406
4407 val64 = readq(&bar0->txdma_int_status);
4408 /*check for pfc_err*/
4409 if (val64 & TXDMA_PFC_INT) {
4410 if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM|
4411 PFC_MISC_0_ERR | PFC_MISC_1_ERR|
4412 PFC_PCIX_ERR, &bar0->pfc_err_reg,
4413 &sw_stat->pfc_err_cnt))
4414 goto reset;
4415 do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR, &bar0->pfc_err_reg,
4416 &sw_stat->pfc_err_cnt);
4417 }
4418
4419 /*check for tda_err*/
4420 if (val64 & TXDMA_TDA_INT) {
4421 if(do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
4422 TDA_SM1_ERR_ALARM, &bar0->tda_err_reg,
4423 &sw_stat->tda_err_cnt))
4424 goto reset;
4425 do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4426 &bar0->tda_err_reg, &sw_stat->tda_err_cnt);
4427 }
4428 /*check for pcc_err*/
4429 if (val64 & TXDMA_PCC_INT) {
4430 if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM
4431 | PCC_N_SERR | PCC_6_COF_OV_ERR
4432 | PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR
4433 | PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR
4434 | PCC_TXB_ECC_DB_ERR, &bar0->pcc_err_reg,
4435 &sw_stat->pcc_err_cnt))
4436 goto reset;
4437 do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4438 &bar0->pcc_err_reg, &sw_stat->pcc_err_cnt);
4439 }
4440
4441 /*check for tti_err*/
4442 if (val64 & TXDMA_TTI_INT) {
4443 if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM, &bar0->tti_err_reg,
4444 &sw_stat->tti_err_cnt))
4445 goto reset;
4446 do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4447 &bar0->tti_err_reg, &sw_stat->tti_err_cnt);
4448 }
4449
4450 /*check for lso_err*/
4451 if (val64 & TXDMA_LSO_INT) {
4452 if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT
4453 | LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4454 &bar0->lso_err_reg, &sw_stat->lso_err_cnt))
4455 goto reset;
4456 do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4457 &bar0->lso_err_reg, &sw_stat->lso_err_cnt);
4458 }
4459
4460 /*check for tpa_err*/
4461 if (val64 & TXDMA_TPA_INT) {
4462 if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM, &bar0->tpa_err_reg,
4463 &sw_stat->tpa_err_cnt))
4464 goto reset;
4465 do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP, &bar0->tpa_err_reg,
4466 &sw_stat->tpa_err_cnt);
4467 }
4468
4469 /*check for sm_err*/
4470 if (val64 & TXDMA_SM_INT) {
4471 if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM, &bar0->sm_err_reg,
4472 &sw_stat->sm_err_cnt))
4473 goto reset;
4474 }
4475
4476 val64 = readq(&bar0->mac_int_status);
4477 if (val64 & MAC_INT_STATUS_TMAC_INT) {
4478 if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4479 &bar0->mac_tmac_err_reg,
4480 &sw_stat->mac_tmac_err_cnt))
4481 goto reset;
4482 do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR
4483 | TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
4484 &bar0->mac_tmac_err_reg,
4485 &sw_stat->mac_tmac_err_cnt);
4486 }
4487
4488 val64 = readq(&bar0->xgxs_int_status);
4489 if (val64 & XGXS_INT_STATUS_TXGXS) {
4490 if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4491 &bar0->xgxs_txgxs_err_reg,
4492 &sw_stat->xgxs_txgxs_err_cnt))
4493 goto reset;
4494 do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4495 &bar0->xgxs_txgxs_err_reg,
4496 &sw_stat->xgxs_txgxs_err_cnt);
4497 }
4498
4499 val64 = readq(&bar0->rxdma_int_status);
4500 if (val64 & RXDMA_INT_RC_INT_M) {
4501 if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR
4502 | RC_PRCn_SM_ERR_ALARM |RC_FTC_SM_ERR_ALARM,
4503 &bar0->rc_err_reg, &sw_stat->rc_err_cnt))
4504 goto reset;
4505 do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR
4506 | RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4507 &sw_stat->rc_err_cnt);
4508 if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn
4509 | PRC_PCI_AB_F_WR_Rn, &bar0->prc_pcix_err_reg,
4510 &sw_stat->prc_pcix_err_cnt))
4511 goto reset;
4512 do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn | PRC_PCI_DP_WR_Rn
4513 | PRC_PCI_DP_F_WR_Rn, &bar0->prc_pcix_err_reg,
4514 &sw_stat->prc_pcix_err_cnt);
4515 }
4516
4517 if (val64 & RXDMA_INT_RPA_INT_M) {
4518 if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4519 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt))
4520 goto reset;
4521 do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4522 &bar0->rpa_err_reg, &sw_stat->rpa_err_cnt);
4523 }
4524
4525 if (val64 & RXDMA_INT_RDA_INT_M) {
4526 if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR
4527 | RDA_FRM_ECC_DB_N_AERR | RDA_SM1_ERR_ALARM
4528 | RDA_SM0_ERR_ALARM | RDA_RXD_ECC_DB_SERR,
4529 &bar0->rda_err_reg, &sw_stat->rda_err_cnt))
4530 goto reset;
4531 do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR | RDA_FRM_ECC_SG_ERR
4532 | RDA_MISC_ERR | RDA_PCIX_ERR,
4533 &bar0->rda_err_reg, &sw_stat->rda_err_cnt);
4534 }
4535
4536 if (val64 & RXDMA_INT_RTI_INT_M) {
4537 if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM, &bar0->rti_err_reg,
4538 &sw_stat->rti_err_cnt))
4539 goto reset;
4540 do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4541 &bar0->rti_err_reg, &sw_stat->rti_err_cnt);
4542 }
4543
4544 val64 = readq(&bar0->mac_int_status);
4545 if (val64 & MAC_INT_STATUS_RMAC_INT) {
4546 if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4547 &bar0->mac_rmac_err_reg,
4548 &sw_stat->mac_rmac_err_cnt))
4549 goto reset;
4550 do_s2io_chk_alarm_bit(RMAC_UNUSED_INT|RMAC_SINGLE_ECC_ERR|
4551 RMAC_DOUBLE_ECC_ERR, &bar0->mac_rmac_err_reg,
4552 &sw_stat->mac_rmac_err_cnt);
4553 }
4554
4555 val64 = readq(&bar0->xgxs_int_status);
4556 if (val64 & XGXS_INT_STATUS_RXGXS) {
4557 if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4558 &bar0->xgxs_rxgxs_err_reg,
4559 &sw_stat->xgxs_rxgxs_err_cnt))
4560 goto reset;
4561 }
4562
4563 val64 = readq(&bar0->mc_int_status);
4564 if(val64 & MC_INT_STATUS_MC_INT) {
4565 if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR, &bar0->mc_err_reg,
4566 &sw_stat->mc_err_cnt))
4567 goto reset;
4568
4569 /* Handling Ecc errors */
4570 if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4571 writeq(val64, &bar0->mc_err_reg);
4572 if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4573 sw_stat->double_ecc_errs++;
4574 if (sp->device_type != XFRAME_II_DEVICE) {
4575 /*
4576 * Reset XframeI only if critical error
4577 */
4578 if (val64 &
4579 (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4580 MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4581 goto reset;
4582 }
4583 } else
4584 sw_stat->single_ecc_errs++;
4585 }
4586 }
4587 return;
4588
4589reset:
4590 netif_stop_queue(dev);
4591 schedule_work(&sp->rst_timer_task);
4592 sw_stat->soft_reset_cnt++;
4593 return;
4594}
4595
1da177e4
LT		 4596/**
4597 * s2io_isr - ISR handler of the device .
4598 * @irq: the irq of the device.
4599 * @dev_id: a void pointer to the dev structure of the NIC.
20346722
K		 4600 * Description: This function is the ISR handler of the device. It
4601 * identifies the reason for the interrupt and calls the relevant
4602 * service routines. As a contongency measure, this ISR allocates the
1da177e4
LT		 4603 * recv buffers, if their numbers are below the panic value which is
4604 * presently set to 25% of the original number of rcv buffers allocated.
4605 * Return value:
20346722 4606 * IRQ_HANDLED: will be returned if IRQ was handled by this routine
1da177e4
LT		 4607 * IRQ_NONE: will be returned if interrupt is not from our device
4608 */
7d12e780 4609static irqreturn_t s2io_isr(int irq, void *dev_id)
1da177e4
LT		 4610{
4611 struct net_device *dev = (struct net_device *) dev_id;
1ee6dd77
RB		 4612 struct s2io_nic *sp = dev->priv;
4613 struct XENA_dev_config __iomem *bar0 = sp->bar0;
20346722 4614 int i;
19a60522 4615 u64 reason = 0;
1ee6dd77 4616 struct mac_info *mac_control;
1da177e4
LT		 4617 struct config_param *config;
4618
d796fdb7
LV		 4619 /* Pretend we handled any irq's from a disconnected card */
4620 if (pci_channel_offline(sp->pdev))
4621 return IRQ_NONE;
4622
596c5c97 4623 if (!is_s2io_card_up(sp))
92b84437 4624 return IRQ_NONE;
92b84437 4625
1da177e4
LT		 4626 mac_control = &sp->mac_control;
4627 config = &sp->config;
4628
20346722 4629 /*
1da177e4
LT		 4630 * Identify the cause for interrupt and call the appropriate
4631 * interrupt handler. Causes for the interrupt could be;
4632 * 1. Rx of packet.
4633 * 2. Tx complete.
4634 * 3. Link down.
1da177e4
LT		 4635 */
4636 reason = readq(&bar0->general_int_status);
4637
596c5c97
SS		 4638 if (unlikely(reason == S2IO_MINUS_ONE) ) {
4639 /* Nothing much can be done. Get out */
4640 return IRQ_HANDLED;
1da177e4 4641 }
5d3213cc 4642
596c5c97
SS		 4643 if (reason & (GEN_INTR_RXTRAFFIC |
4644 GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC))
4645 {
4646 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4647
4648 if (config->napi) {
4649 if (reason & GEN_INTR_RXTRAFFIC) {
4650 if (likely(netif_rx_schedule_prep(dev,
4651 &sp->napi))) {
4652 __netif_rx_schedule(dev, &sp->napi);
4653 writeq(S2IO_MINUS_ONE,
4654 &bar0->rx_traffic_mask);
4655 } else
4656 writeq(S2IO_MINUS_ONE,
4657 &bar0->rx_traffic_int);
db874e65 4658 }
596c5c97
SS		 4659 } else {
4660 /*
4661 * rx_traffic_int reg is an R1 register, writing all 1's
4662 * will ensure that the actual interrupt causing bit
4663 * get's cleared and hence a read can be avoided.
4664 */
4665 if (reason & GEN_INTR_RXTRAFFIC)
19a60522 4666 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
596c5c97
SS		 4667
4668 for (i = 0; i < config->rx_ring_num; i++)
4669 rx_intr_handler(&mac_control->rings[i]);
db874e65 4670 }
596c5c97 4671
db874e65 4672 /*
596c5c97 4673 * tx_traffic_int reg is an R1 register, writing all 1's
db874e65
SS		 4674 * will ensure that the actual interrupt causing bit get's
4675 * cleared and hence a read can be avoided.
4676 */
596c5c97
SS		 4677 if (reason & GEN_INTR_TXTRAFFIC)
4678 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
19a60522 4679
596c5c97
SS		 4680 for (i = 0; i < config->tx_fifo_num; i++)
4681 tx_intr_handler(&mac_control->fifos[i]);
1da177e4 4682
596c5c97
SS		 4683 if (reason & GEN_INTR_TXPIC)
4684 s2io_txpic_intr_handle(sp);
fe113638 4685
596c5c97
SS		 4686 /*
4687 * Reallocate the buffers from the interrupt handler itself.
4688 */
4689 if (!config->napi) {
4690 for (i = 0; i < config->rx_ring_num; i++)
4691 s2io_chk_rx_buffers(sp, i);
4692 }
4693 writeq(sp->general_int_mask, &bar0->general_int_mask);
4694 readl(&bar0->general_int_status);
20346722 4695
596c5c97 4696 return IRQ_HANDLED;
db874e65 4697
596c5c97
SS		 4698 }
4699 else if (!reason) {
4700 /* The interrupt was not raised by us */
4701 return IRQ_NONE;
4702 }
db874e65 4703
1da177e4
LT		 4704 return IRQ_HANDLED;
4705}
4706
7ba013ac
K		 4707/**
4708 * s2io_updt_stats -
4709 */
1ee6dd77 4710static void s2io_updt_stats(struct s2io_nic *sp)
7ba013ac 4711{
1ee6dd77 4712 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7ba013ac
K		 4713 u64 val64;
4714 int cnt = 0;
4715
92b84437 4716 if (is_s2io_card_up(sp)) {
7ba013ac
K		 4717 /* Apprx 30us on a 133 MHz bus */
4718 val64 = SET_UPDT_CLICKS(10) |
4719 STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4720 writeq(val64, &bar0->stat_cfg);
4721 do {
4722 udelay(100);
4723 val64 = readq(&bar0->stat_cfg);
b7b5a128 4724 if (!(val64 & s2BIT(0)))
7ba013ac
K		 4725 break;
4726 cnt++;
4727 if (cnt == 5)
4728 break; /* Updt failed */
4729 } while(1);
8a4bdbaa 4730 }
7ba013ac
K		 4731}
4732
1da177e4 4733/**
20346722 4734 * s2io_get_stats - Updates the device statistics structure.
1da177e4
LT		 4735 * @dev : pointer to the device structure.
4736 * Description:
20346722 4737 * This function updates the device statistics structure in the s2io_nic
1da177e4
LT		 4738 * structure and returns a pointer to the same.
4739 * Return value:
4740 * pointer to the updated net_device_stats structure.
4741 */
4742
ac1f60db 4743static struct net_device_stats *s2io_get_stats(struct net_device *dev)
1da177e4 4744{
1ee6dd77
RB		 4745 struct s2io_nic *sp = dev->priv;
4746 struct mac_info *mac_control;
1da177e4
LT		 4747 struct config_param *config;
4748
20346722 4749
1da177e4
LT		 4750 mac_control = &sp->mac_control;
4751 config = &sp->config;
4752
7ba013ac
K		 4753 /* Configure Stats for immediate updt */
4754 s2io_updt_stats(sp);
4755
4756 sp->stats.tx_packets =
4757 le32_to_cpu(mac_control->stats_info->tmac_frms);
20346722
K		 4758 sp->stats.tx_errors =
4759 le32_to_cpu(mac_control->stats_info->tmac_any_err_frms);
4760 sp->stats.rx_errors =
ee705dba 4761 le64_to_cpu(mac_control->stats_info->rmac_drop_frms);
20346722
K		 4762 sp->stats.multicast =
4763 le32_to_cpu(mac_control->stats_info->rmac_vld_mcst_frms);
1da177e4 4764 sp->stats.rx_length_errors =
ee705dba 4765 le64_to_cpu(mac_control->stats_info->rmac_long_frms);
1da177e4
LT		 4766
4767 return (&sp->stats);
4768}
4769
4770/**
4771 * s2io_set_multicast - entry point for multicast address enable/disable.
4772 * @dev : pointer to the device structure
4773 * Description:
20346722
K		 4774 * This function is a driver entry point which gets called by the kernel
4775 * whenever multicast addresses must be enabled/disabled. This also gets
1da177e4
LT		 4776 * called to set/reset promiscuous mode. Depending on the deivce flag, we
4777 * determine, if multicast address must be enabled or if promiscuous mode
4778 * is to be disabled etc.
4779 * Return value:
4780 * void.
4781 */
4782
4783static void s2io_set_multicast(struct net_device *dev)
4784{
4785 int i, j, prev_cnt;
4786 struct dev_mc_list *mclist;
1ee6dd77
RB		 4787 struct s2io_nic *sp = dev->priv;
4788 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 4789 u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4790 0xfeffffffffffULL;
faa4f796 4791 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
1da177e4 4792 void __iomem *add;
faa4f796 4793 struct config_param *config = &sp->config;
1da177e4
LT		 4794
4795 if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4796 /* Enable all Multicast addresses */
4797 writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4798 &bar0->rmac_addr_data0_mem);
4799 writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4800 &bar0->rmac_addr_data1_mem);
4801 val64 = RMAC_ADDR_CMD_MEM_WE |
4802 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 4803 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
1da177e4
LT		 4804 writeq(val64, &bar0->rmac_addr_cmd_mem);
4805 /* Wait till command completes */
c92ca04b 4806 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4807 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4808 S2IO_BIT_RESET);
1da177e4
LT		 4809
4810 sp->m_cast_flg = 1;
faa4f796 4811 sp->all_multi_pos = config->max_mc_addr - 1;
1da177e4
LT		 4812 } else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4813 /* Disable all Multicast addresses */
4814 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4815 &bar0->rmac_addr_data0_mem);
5e25b9dd
K		 4816 writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4817 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4818 val64 = RMAC_ADDR_CMD_MEM_WE |
4819 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4820 RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4821 writeq(val64, &bar0->rmac_addr_cmd_mem);
4822 /* Wait till command completes */
c92ca04b 4823 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4824 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4825 S2IO_BIT_RESET);
1da177e4
LT		 4826
4827 sp->m_cast_flg = 0;
4828 sp->all_multi_pos = 0;
4829 }
4830
4831 if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4832 /* Put the NIC into promiscuous mode */
4833 add = &bar0->mac_cfg;
4834 val64 = readq(&bar0->mac_cfg);
4835 val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4836
4837 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4838 writel((u32) val64, add);
4839 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4840 writel((u32) (val64 >> 32), (add + 4));
4841
926930b2
SS		 4842 if (vlan_tag_strip != 1) {
4843 val64 = readq(&bar0->rx_pa_cfg);
4844 val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4845 writeq(val64, &bar0->rx_pa_cfg);
4846 vlan_strip_flag = 0;
4847 }
4848
1da177e4
LT		 4849 val64 = readq(&bar0->mac_cfg);
4850 sp->promisc_flg = 1;
776bd20f 4851 DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
1da177e4
LT		 4852 dev->name);
4853 } else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4854 /* Remove the NIC from promiscuous mode */
4855 add = &bar0->mac_cfg;
4856 val64 = readq(&bar0->mac_cfg);
4857 val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4858
4859 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4860 writel((u32) val64, add);
4861 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4862 writel((u32) (val64 >> 32), (add + 4));
4863
926930b2
SS		 4864 if (vlan_tag_strip != 0) {
4865 val64 = readq(&bar0->rx_pa_cfg);
4866 val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4867 writeq(val64, &bar0->rx_pa_cfg);
4868 vlan_strip_flag = 1;
4869 }
4870
1da177e4
LT		 4871 val64 = readq(&bar0->mac_cfg);
4872 sp->promisc_flg = 0;
776bd20f 4873 DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n",
1da177e4
LT		 4874 dev->name);
4875 }
4876
4877 /* Update individual M_CAST address list */
4878 if ((!sp->m_cast_flg) && dev->mc_count) {
4879 if (dev->mc_count >
faa4f796 4880 (config->max_mc_addr - config->max_mac_addr)) {
1da177e4
LT		 4881 DBG_PRINT(ERR_DBG, "%s: No more Rx filters ",
4882 dev->name);
4883 DBG_PRINT(ERR_DBG, "can be added, please enable ");
4884 DBG_PRINT(ERR_DBG, "ALL_MULTI instead\n");
4885 return;
4886 }
4887
4888 prev_cnt = sp->mc_addr_count;
4889 sp->mc_addr_count = dev->mc_count;
4890
4891 /* Clear out the previous list of Mc in the H/W. */
4892 for (i = 0; i < prev_cnt; i++) {
4893 writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4894 &bar0->rmac_addr_data0_mem);
4895 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4896 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4897 val64 = RMAC_ADDR_CMD_MEM_WE |
4898 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4899 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 4900 (config->mc_start_offset + i);
1da177e4
LT		 4901 writeq(val64, &bar0->rmac_addr_cmd_mem);
4902
4903 /* Wait for command completes */
c92ca04b 4904 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4905 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4906 S2IO_BIT_RESET)) {
1da177e4
LT		 4907 DBG_PRINT(ERR_DBG, "%s: Adding ",
4908 dev->name);
4909 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4910 return;
4911 }
4912 }
4913
4914 /* Create the new Rx filter list and update the same in H/W. */
4915 for (i = 0, mclist = dev->mc_list; i < dev->mc_count;
4916 i++, mclist = mclist->next) {
4917 memcpy(sp->usr_addrs[i].addr, mclist->dmi_addr,
4918 ETH_ALEN);
a7a80d5a 4919 mac_addr = 0;
1da177e4
LT		 4920 for (j = 0; j < ETH_ALEN; j++) {
4921 mac_addr |= mclist->dmi_addr[j];
4922 mac_addr <<= 8;
4923 }
4924 mac_addr >>= 8;
4925 writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
4926 &bar0->rmac_addr_data0_mem);
4927 writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
20346722 4928 &bar0->rmac_addr_data1_mem);
1da177e4
LT		 4929 val64 = RMAC_ADDR_CMD_MEM_WE |
4930 RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4931 RMAC_ADDR_CMD_MEM_OFFSET
faa4f796 4932 (i + config->mc_start_offset);
1da177e4
LT		 4933 writeq(val64, &bar0->rmac_addr_cmd_mem);
4934
4935 /* Wait for command completes */
c92ca04b 4936 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41
SS		 4937 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4938 S2IO_BIT_RESET)) {
1da177e4
LT		 4939 DBG_PRINT(ERR_DBG, "%s: Adding ",
4940 dev->name);
4941 DBG_PRINT(ERR_DBG, "Multicasts failed\n");
4942 return;
4943 }
4944 }
4945 }
4946}
4947
faa4f796
SH		 4948/* read from CAM unicast & multicast addresses and store it in
4949 * def_mac_addr structure
4950 */
4951void do_s2io_store_unicast_mc(struct s2io_nic *sp)
4952{
4953 int offset;
4954 u64 mac_addr = 0x0;
4955 struct config_param *config = &sp->config;
4956
4957 /* store unicast & multicast mac addresses */
4958 for (offset = 0; offset < config->max_mc_addr; offset++) {
4959 mac_addr = do_s2io_read_unicast_mc(sp, offset);
4960 /* if read fails disable the entry */
4961 if (mac_addr == FAILURE)
4962 mac_addr = S2IO_DISABLE_MAC_ENTRY;
4963 do_s2io_copy_mac_addr(sp, offset, mac_addr);
4964 }
4965}
4966
4967/* restore unicast & multicast MAC to CAM from def_mac_addr structure */
4968static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
4969{
4970 int offset;
4971 struct config_param *config = &sp->config;
4972 /* restore unicast mac address */
4973 for (offset = 0; offset < config->max_mac_addr; offset++)
4974 do_s2io_prog_unicast(sp->dev,
4975 sp->def_mac_addr[offset].mac_addr);
4976
4977 /* restore multicast mac address */
4978 for (offset = config->mc_start_offset;
4979 offset < config->max_mc_addr; offset++)
4980 do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
4981}
4982
4983/* add a multicast MAC address to CAM */
4984static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
4985{
4986 int i;
4987 u64 mac_addr = 0;
4988 struct config_param *config = &sp->config;
4989
4990 for (i = 0; i < ETH_ALEN; i++) {
4991 mac_addr <<= 8;
4992 mac_addr |= addr[i];
4993 }
4994 if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
4995 return SUCCESS;
4996
4997 /* check if the multicast mac already preset in CAM */
4998 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
4999 u64 tmp64;
5000 tmp64 = do_s2io_read_unicast_mc(sp, i);
5001 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5002 break;
5003
5004 if (tmp64 == mac_addr)
5005 return SUCCESS;
5006 }
5007 if (i == config->max_mc_addr) {
5008 DBG_PRINT(ERR_DBG,
5009 "CAM full no space left for multicast MAC\n");
5010 return FAILURE;
5011 }
5012 /* Update the internal structure with this new mac address */
5013 do_s2io_copy_mac_addr(sp, i, mac_addr);
5014
5015 return (do_s2io_add_mac(sp, mac_addr, i));
5016}
5017
5018/* add MAC address to CAM */
5019static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
2fd37688
SS		 5020{
5021 u64 val64;
5022 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5023
5024 writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5025 &bar0->rmac_addr_data0_mem);
5026
5027 val64 =
5028 RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5029 RMAC_ADDR_CMD_MEM_OFFSET(off);
5030 writeq(val64, &bar0->rmac_addr_cmd_mem);
5031
5032 /* Wait till command completes */
5033 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5034 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5035 S2IO_BIT_RESET)) {
faa4f796 5036 DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
2fd37688
SS		 5037 return FAILURE;
5038 }
5039 return SUCCESS;
5040}
faa4f796
SH		 5041/* deletes a specified unicast/multicast mac entry from CAM */
5042static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5043{
5044 int offset;
5045 u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5046 struct config_param *config = &sp->config;
5047
5048 for (offset = 1;
5049 offset < config->max_mc_addr; offset++) {
5050 tmp64 = do_s2io_read_unicast_mc(sp, offset);
5051 if (tmp64 == addr) {
5052 /* disable the entry by writing 0xffffffffffffULL */
5053 if (do_s2io_add_mac(sp, dis_addr, offset) == FAILURE)
5054 return FAILURE;
5055 /* store the new mac list from CAM */
5056 do_s2io_store_unicast_mc(sp);
5057 return SUCCESS;
5058 }
5059 }
5060 DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5061 (unsigned long long)addr);
5062 return FAILURE;
5063}
5064
5065/* read mac entries from CAM */
5066static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5067{
5068 u64 tmp64 = 0xffffffffffff0000ULL, val64;
5069 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5070
5071 /* read mac addr */
5072 val64 =
5073 RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5074 RMAC_ADDR_CMD_MEM_OFFSET(offset);
5075 writeq(val64, &bar0->rmac_addr_cmd_mem);
5076
5077 /* Wait till command completes */
5078 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5079 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5080 S2IO_BIT_RESET)) {
5081 DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5082 return FAILURE;
5083 }
5084 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5085 return (tmp64 >> 16);
5086}
2fd37688
SS		 5087
5088/**
5089 * s2io_set_mac_addr driver entry point
5090 */
faa4f796 5091
2fd37688
SS		 5092static int s2io_set_mac_addr(struct net_device *dev, void *p)
5093{
5094 struct sockaddr *addr = p;
5095
5096 if (!is_valid_ether_addr(addr->sa_data))
5097 return -EINVAL;
5098
5099 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5100
5101 /* store the MAC address in CAM */
5102 return (do_s2io_prog_unicast(dev, dev->dev_addr));
5103}
1da177e4 5104/**
2fd37688 5105 * do_s2io_prog_unicast - Programs the Xframe mac address
1da177e4
LT		 5106 * @dev : pointer to the device structure.
5107 * @addr: a uchar pointer to the new mac address which is to be set.
20346722 5108 * Description : This procedure will program the Xframe to receive
1da177e4 5109 * frames with new Mac Address
20346722 5110 * Return value: SUCCESS on success and an appropriate (-)ve integer
1da177e4
LT		 5111 * as defined in errno.h file on failure.
5112 */
faa4f796 5113
2fd37688 5114static int do_s2io_prog_unicast(struct net_device *dev, u8 *addr)
1da177e4 5115{
1ee6dd77 5116 struct s2io_nic *sp = dev->priv;
2fd37688 5117 register u64 mac_addr = 0, perm_addr = 0;
1da177e4 5118 int i;
faa4f796
SH		 5119 u64 tmp64;
5120 struct config_param *config = &sp->config;
1da177e4 5121
20346722 5122 /*
2fd37688
SS		 5123 * Set the new MAC address as the new unicast filter and reflect this
5124 * change on the device address registered with the OS. It will be
5125 * at offset 0.
5126 */
1da177e4
LT		 5127 for (i = 0; i < ETH_ALEN; i++) {
5128 mac_addr <<= 8;
5129 mac_addr |= addr[i];
2fd37688
SS		 5130 perm_addr <<= 8;
5131 perm_addr |= sp->def_mac_addr[0].mac_addr[i];
d8d70caf
SS		 5132 }
5133
2fd37688
SS		 5134 /* check if the dev_addr is different than perm_addr */
5135 if (mac_addr == perm_addr)
d8d70caf
SS		 5136 return SUCCESS;
5137
faa4f796
SH		 5138 /* check if the mac already preset in CAM */
5139 for (i = 1; i < config->max_mac_addr; i++) {
5140 tmp64 = do_s2io_read_unicast_mc(sp, i);
5141 if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5142 break;
5143
5144 if (tmp64 == mac_addr) {
5145 DBG_PRINT(INFO_DBG,
5146 "MAC addr:0x%llx already present in CAM\n",
5147 (unsigned long long)mac_addr);
5148 return SUCCESS;
5149 }
5150 }
5151 if (i == config->max_mac_addr) {
5152 DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5153 return FAILURE;
5154 }
d8d70caf 5155 /* Update the internal structure with this new mac address */
faa4f796
SH		 5156 do_s2io_copy_mac_addr(sp, i, mac_addr);
5157 return (do_s2io_add_mac(sp, mac_addr, i));
1da177e4
LT		 5158}
5159
5160/**
20346722 5161 * s2io_ethtool_sset - Sets different link parameters.
1da177e4
LT		 5162 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
5163 * @info: pointer to the structure with parameters given by ethtool to set
5164 * link information.
5165 * Description:
20346722 5166 * The function sets different link parameters provided by the user onto
1da177e4
LT		 5167 * the NIC.
5168 * Return value:
5169 * 0 on success.
5170*/
5171
5172static int s2io_ethtool_sset(struct net_device *dev,
5173 struct ethtool_cmd *info)
5174{
1ee6dd77 5175 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5176 if ((info->autoneg == AUTONEG_ENABLE) ||
5177 (info->speed != SPEED_10000) || (info->duplex != DUPLEX_FULL))
5178 return -EINVAL;
5179 else {
5180 s2io_close(sp->dev);
5181 s2io_open(sp->dev);
5182 }
5183
5184 return 0;
5185}
5186
5187/**
20346722 5188 * s2io_ethtol_gset - Return link specific information.
1da177e4
LT		 5189 * @sp : private member of the device structure, pointer to the
5190 * s2io_nic structure.
5191 * @info : pointer to the structure with parameters given by ethtool
5192 * to return link information.
5193 * Description:
5194 * Returns link specific information like speed, duplex etc.. to ethtool.
5195 * Return value :
5196 * return 0 on success.
5197 */
5198
5199static int s2io_ethtool_gset(struct net_device *dev, struct ethtool_cmd *info)
5200{
1ee6dd77 5201 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5202 info->supported = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5203 info->advertising = (SUPPORTED_10000baseT_Full | SUPPORTED_FIBRE);
5204 info->port = PORT_FIBRE;
1a7eb72b
SS		 5205
5206 /* info->transceiver */
5207 info->transceiver = XCVR_EXTERNAL;
1da177e4
LT		 5208
5209 if (netif_carrier_ok(sp->dev)) {
5210 info->speed = 10000;
5211 info->duplex = DUPLEX_FULL;
5212 } else {
5213 info->speed = -1;
5214 info->duplex = -1;
5215 }
5216
5217 info->autoneg = AUTONEG_DISABLE;
5218 return 0;
5219}
5220
5221/**
20346722
K		 5222 * s2io_ethtool_gdrvinfo - Returns driver specific information.
5223 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5224 * s2io_nic structure.
5225 * @info : pointer to the structure with parameters given by ethtool to
5226 * return driver information.
5227 * Description:
5228 * Returns driver specefic information like name, version etc.. to ethtool.
5229 * Return value:
5230 * void
5231 */
5232
5233static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5234 struct ethtool_drvinfo *info)
5235{
1ee6dd77 5236 struct s2io_nic *sp = dev->priv;
1da177e4 5237
dbc2309d
JL		 5238 strncpy(info->driver, s2io_driver_name, sizeof(info->driver));
5239 strncpy(info->version, s2io_driver_version, sizeof(info->version));
5240 strncpy(info->fw_version, "", sizeof(info->fw_version));
5241 strncpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
1da177e4
LT		 5242 info->regdump_len = XENA_REG_SPACE;
5243 info->eedump_len = XENA_EEPROM_SPACE;
1da177e4
LT		 5244}
5245
5246/**
5247 * s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
20346722 5248 * @sp: private member of the device structure, which is a pointer to the
1da177e4 5249 * s2io_nic structure.
20346722 5250 * @regs : pointer to the structure with parameters given by ethtool for
1da177e4
LT		 5251 * dumping the registers.
5252 * @reg_space: The input argumnet into which all the registers are dumped.
5253 * Description:
5254 * Dumps the entire register space of xFrame NIC into the user given
5255 * buffer area.
5256 * Return value :
5257 * void .
5258*/
5259
5260static void s2io_ethtool_gregs(struct net_device *dev,
5261 struct ethtool_regs *regs, void *space)
5262{
5263 int i;
5264 u64 reg;
5265 u8 *reg_space = (u8 *) space;
1ee6dd77 5266 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5267
5268 regs->len = XENA_REG_SPACE;
5269 regs->version = sp->pdev->subsystem_device;
5270
5271 for (i = 0; i < regs->len; i += 8) {
5272 reg = readq(sp->bar0 + i);
5273 memcpy((reg_space + i), &reg, 8);
5274 }
5275}
5276
5277/**
5278 * s2io_phy_id - timer function that alternates adapter LED.
20346722 5279 * @data : address of the private member of the device structure, which
1da177e4 5280 * is a pointer to the s2io_nic structure, provided as an u32.
20346722
K		 5281 * Description: This is actually the timer function that alternates the
5282 * adapter LED bit of the adapter control bit to set/reset every time on
5283 * invocation. The timer is set for 1/2 a second, hence tha NIC blinks
1da177e4
LT		 5284 * once every second.
5285*/
5286static void s2io_phy_id(unsigned long data)
5287{
1ee6dd77
RB		 5288 struct s2io_nic *sp = (struct s2io_nic *) data;
5289 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5290 u64 val64 = 0;
5291 u16 subid;
5292
5293 subid = sp->pdev->subsystem_device;
541ae68f
K		 5294 if ((sp->device_type == XFRAME_II_DEVICE) ||
5295 ((subid & 0xFF) >= 0x07)) {
1da177e4
LT		 5296 val64 = readq(&bar0->gpio_control);
5297 val64 ^= GPIO_CTRL_GPIO_0;
5298 writeq(val64, &bar0->gpio_control);
5299 } else {
5300 val64 = readq(&bar0->adapter_control);
5301 val64 ^= ADAPTER_LED_ON;
5302 writeq(val64, &bar0->adapter_control);
5303 }
5304
5305 mod_timer(&sp->id_timer, jiffies + HZ / 2);
5306}
5307
5308/**
5309 * s2io_ethtool_idnic - To physically identify the nic on the system.
5310 * @sp : private member of the device structure, which is a pointer to the
5311 * s2io_nic structure.
20346722 5312 * @id : pointer to the structure with identification parameters given by
1da177e4
LT		 5313 * ethtool.
5314 * Description: Used to physically identify the NIC on the system.
20346722 5315 * The Link LED will blink for a time specified by the user for
1da177e4 5316 * identification.
20346722 5317 * NOTE: The Link has to be Up to be able to blink the LED. Hence
1da177e4
LT		 5318 * identification is possible only if it's link is up.
5319 * Return value:
5320 * int , returns 0 on success
5321 */
5322
5323static int s2io_ethtool_idnic(struct net_device *dev, u32 data)
5324{
5325 u64 val64 = 0, last_gpio_ctrl_val;
1ee6dd77
RB		 5326 struct s2io_nic *sp = dev->priv;
5327 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5328 u16 subid;
5329
5330 subid = sp->pdev->subsystem_device;
5331 last_gpio_ctrl_val = readq(&bar0->gpio_control);
541ae68f
K		 5332 if ((sp->device_type == XFRAME_I_DEVICE) &&
5333 ((subid & 0xFF) < 0x07)) {
1da177e4
LT		 5334 val64 = readq(&bar0->adapter_control);
5335 if (!(val64 & ADAPTER_CNTL_EN)) {
5336 printk(KERN_ERR
5337 "Adapter Link down, cannot blink LED\n");
5338 return -EFAULT;
5339 }
5340 }
5341 if (sp->id_timer.function == NULL) {
5342 init_timer(&sp->id_timer);
5343 sp->id_timer.function = s2io_phy_id;
5344 sp->id_timer.data = (unsigned long) sp;
5345 }
5346 mod_timer(&sp->id_timer, jiffies);
5347 if (data)
20346722 5348 msleep_interruptible(data * HZ);
1da177e4 5349 else
20346722 5350 msleep_interruptible(MAX_FLICKER_TIME);
1da177e4
LT		 5351 del_timer_sync(&sp->id_timer);
5352
541ae68f 5353 if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid)) {
1da177e4
LT		 5354 writeq(last_gpio_ctrl_val, &bar0->gpio_control);
5355 last_gpio_ctrl_val = readq(&bar0->gpio_control);
5356 }
5357
5358 return 0;
5359}
5360
0cec35eb
SH		 5361static void s2io_ethtool_gringparam(struct net_device *dev,
5362 struct ethtool_ringparam *ering)
5363{
5364 struct s2io_nic *sp = dev->priv;
5365 int i,tx_desc_count=0,rx_desc_count=0;
5366
5367 if (sp->rxd_mode == RXD_MODE_1)
5368 ering->rx_max_pending = MAX_RX_DESC_1;
5369 else if (sp->rxd_mode == RXD_MODE_3B)
5370 ering->rx_max_pending = MAX_RX_DESC_2;
0cec35eb
SH		 5371
5372 ering->tx_max_pending = MAX_TX_DESC;
8a4bdbaa 5373 for (i = 0 ; i < sp->config.tx_fifo_num ; i++)
0cec35eb 5374 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
8a4bdbaa 5375
0cec35eb
SH		 5376 DBG_PRINT(INFO_DBG,"\nmax txds : %d\n",sp->config.max_txds);
5377 ering->tx_pending = tx_desc_count;
5378 rx_desc_count = 0;
8a4bdbaa 5379 for (i = 0 ; i < sp->config.rx_ring_num ; i++)
0cec35eb 5380 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
b6627672 5381
0cec35eb
SH		 5382 ering->rx_pending = rx_desc_count;
5383
5384 ering->rx_mini_max_pending = 0;
5385 ering->rx_mini_pending = 0;
5386 if(sp->rxd_mode == RXD_MODE_1)
5387 ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5388 else if (sp->rxd_mode == RXD_MODE_3B)
5389 ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5390 ering->rx_jumbo_pending = rx_desc_count;
5391}
5392
1da177e4
LT		 5393/**
5394 * s2io_ethtool_getpause_data -Pause frame frame generation and reception.
20346722
K		 5395 * @sp : private member of the device structure, which is a pointer to the
5396 * s2io_nic structure.
1da177e4
LT		 5397 * @ep : pointer to the structure with pause parameters given by ethtool.
5398 * Description:
5399 * Returns the Pause frame generation and reception capability of the NIC.
5400 * Return value:
5401 * void
5402 */
5403static void s2io_ethtool_getpause_data(struct net_device *dev,
5404 struct ethtool_pauseparam *ep)
5405{
5406 u64 val64;
1ee6dd77
RB		 5407 struct s2io_nic *sp = dev->priv;
5408 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5409
5410 val64 = readq(&bar0->rmac_pause_cfg);
5411 if (val64 & RMAC_PAUSE_GEN_ENABLE)
5412 ep->tx_pause = TRUE;
5413 if (val64 & RMAC_PAUSE_RX_ENABLE)
5414 ep->rx_pause = TRUE;
5415 ep->autoneg = FALSE;
5416}
5417
5418/**
5419 * s2io_ethtool_setpause_data - set/reset pause frame generation.
20346722 5420 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5421 * s2io_nic structure.
5422 * @ep : pointer to the structure with pause parameters given by ethtool.
5423 * Description:
5424 * It can be used to set or reset Pause frame generation or reception
5425 * support of the NIC.
5426 * Return value:
5427 * int, returns 0 on Success
5428 */
5429
5430static int s2io_ethtool_setpause_data(struct net_device *dev,
20346722 5431 struct ethtool_pauseparam *ep)
1da177e4
LT		 5432{
5433 u64 val64;
1ee6dd77
RB		 5434 struct s2io_nic *sp = dev->priv;
5435 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5436
5437 val64 = readq(&bar0->rmac_pause_cfg);
5438 if (ep->tx_pause)
5439 val64 |= RMAC_PAUSE_GEN_ENABLE;
5440 else
5441 val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5442 if (ep->rx_pause)
5443 val64 |= RMAC_PAUSE_RX_ENABLE;
5444 else
5445 val64 &= ~RMAC_PAUSE_RX_ENABLE;
5446 writeq(val64, &bar0->rmac_pause_cfg);
5447 return 0;
5448}
5449
5450/**
5451 * read_eeprom - reads 4 bytes of data from user given offset.
20346722 5452 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5453 * s2io_nic structure.
5454 * @off : offset at which the data must be written
5455 * @data : Its an output parameter where the data read at the given
20346722 5456 * offset is stored.
1da177e4 5457 * Description:
20346722 5458 * Will read 4 bytes of data from the user given offset and return the
1da177e4
LT		 5459 * read data.
5460 * NOTE: Will allow to read only part of the EEPROM visible through the
5461 * I2C bus.
5462 * Return value:
5463 * -1 on failure and 0 on success.
5464 */
5465
5466#define S2IO_DEV_ID 5
1ee6dd77 5467static int read_eeprom(struct s2io_nic * sp, int off, u64 * data)
1da177e4
LT		 5468{
5469 int ret = -1;
5470 u32 exit_cnt = 0;
5471 u64 val64;
1ee6dd77 5472 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5473
ad4ebed0 5474 if (sp->device_type == XFRAME_I_DEVICE) {
5475 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5476 I2C_CONTROL_BYTE_CNT(0x3) | I2C_CONTROL_READ |
5477 I2C_CONTROL_CNTL_START;
5478 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
1da177e4 5479
ad4ebed0 5480 while (exit_cnt < 5) {
5481 val64 = readq(&bar0->i2c_control);
5482 if (I2C_CONTROL_CNTL_END(val64)) {
5483 *data = I2C_CONTROL_GET_DATA(val64);
5484 ret = 0;
5485 break;
5486 }
5487 msleep(50);
5488 exit_cnt++;
1da177e4 5489 }
1da177e4
LT		 5490 }
5491
ad4ebed0 5492 if (sp->device_type == XFRAME_II_DEVICE) {
5493 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5494 SPI_CONTROL_BYTECNT(0x3) |
ad4ebed0 5495 SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5496 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5497 val64 |= SPI_CONTROL_REQ;
5498 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5499 while (exit_cnt < 5) {
5500 val64 = readq(&bar0->spi_control);
5501 if (val64 & SPI_CONTROL_NACK) {
5502 ret = 1;
5503 break;
5504 } else if (val64 & SPI_CONTROL_DONE) {
5505 *data = readq(&bar0->spi_data);
5506 *data &= 0xffffff;
5507 ret = 0;
5508 break;
5509 }
5510 msleep(50);
5511 exit_cnt++;
5512 }
5513 }
1da177e4
LT		 5514 return ret;
5515}
5516
5517/**
5518 * write_eeprom - actually writes the relevant part of the data value.
5519 * @sp : private member of the device structure, which is a pointer to the
5520 * s2io_nic structure.
5521 * @off : offset at which the data must be written
5522 * @data : The data that is to be written
20346722 5523 * @cnt : Number of bytes of the data that are actually to be written into
1da177e4
LT		 5524 * the Eeprom. (max of 3)
5525 * Description:
5526 * Actually writes the relevant part of the data value into the Eeprom
5527 * through the I2C bus.
5528 * Return value:
5529 * 0 on success, -1 on failure.
5530 */
5531
1ee6dd77 5532static int write_eeprom(struct s2io_nic * sp, int off, u64 data, int cnt)
1da177e4
LT		 5533{
5534 int exit_cnt = 0, ret = -1;
5535 u64 val64;
1ee6dd77 5536 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5537
ad4ebed0 5538 if (sp->device_type == XFRAME_I_DEVICE) {
5539 val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) | I2C_CONTROL_ADDR(off) |
5540 I2C_CONTROL_BYTE_CNT(cnt) | I2C_CONTROL_SET_DATA((u32)data) |
5541 I2C_CONTROL_CNTL_START;
5542 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5543
5544 while (exit_cnt < 5) {
5545 val64 = readq(&bar0->i2c_control);
5546 if (I2C_CONTROL_CNTL_END(val64)) {
5547 if (!(val64 & I2C_CONTROL_NACK))
5548 ret = 0;
5549 break;
5550 }
5551 msleep(50);
5552 exit_cnt++;
5553 }
5554 }
1da177e4 5555
ad4ebed0 5556 if (sp->device_type == XFRAME_II_DEVICE) {
5557 int write_cnt = (cnt == 8) ? 0 : cnt;
5558 writeq(SPI_DATA_WRITE(data,(cnt<<3)), &bar0->spi_data);
5559
5560 val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
6aa20a22 5561 SPI_CONTROL_BYTECNT(write_cnt) |
ad4ebed0 5562 SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5563 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5564 val64 |= SPI_CONTROL_REQ;
5565 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5566 while (exit_cnt < 5) {
5567 val64 = readq(&bar0->spi_control);
5568 if (val64 & SPI_CONTROL_NACK) {
5569 ret = 1;
5570 break;
5571 } else if (val64 & SPI_CONTROL_DONE) {
1da177e4 5572 ret = 0;
ad4ebed0 5573 break;
5574 }
5575 msleep(50);
5576 exit_cnt++;
1da177e4 5577 }
1da177e4 5578 }
1da177e4
LT		 5579 return ret;
5580}
1ee6dd77 5581static void s2io_vpd_read(struct s2io_nic *nic)
9dc737a7 5582{
b41477f3
AR		 5583 u8 *vpd_data;
5584 u8 data;
9dc737a7
AR		 5585 int i=0, cnt, fail = 0;
5586 int vpd_addr = 0x80;
5587
5588 if (nic->device_type == XFRAME_II_DEVICE) {
5589 strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5590 vpd_addr = 0x80;
5591 }
5592 else {
5593 strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5594 vpd_addr = 0x50;
5595 }
19a60522 5596 strcpy(nic->serial_num, "NOT AVAILABLE");
9dc737a7 5597
b41477f3 5598 vpd_data = kmalloc(256, GFP_KERNEL);
c53d4945
SH		 5599 if (!vpd_data) {
5600 nic->mac_control.stats_info->sw_stat.mem_alloc_fail_cnt++;
b41477f3 5601 return;
c53d4945 5602 }
491976b2 5603 nic->mac_control.stats_info->sw_stat.mem_allocated += 256;
b41477f3 5604
9dc737a7
AR		 5605 for (i = 0; i < 256; i +=4 ) {
5606 pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5607 pci_read_config_byte(nic->pdev, (vpd_addr + 2), &data);
5608 pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5609 for (cnt = 0; cnt <5; cnt++) {
5610 msleep(2);
5611 pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5612 if (data == 0x80)
5613 break;
5614 }
5615 if (cnt >= 5) {
5616 DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5617 fail = 1;
5618 break;
5619 }
5620 pci_read_config_dword(nic->pdev, (vpd_addr + 4),
5621 (u32 *)&vpd_data[i]);
5622 }
19a60522
SS		 5623
5624 if(!fail) {
5625 /* read serial number of adapter */
5626 for (cnt = 0; cnt < 256; cnt++) {
5627 if ((vpd_data[cnt] == 'S') &&
5628 (vpd_data[cnt+1] == 'N') &&
5629 (vpd_data[cnt+2] < VPD_STRING_LEN)) {
5630 memset(nic->serial_num, 0, VPD_STRING_LEN);
5631 memcpy(nic->serial_num, &vpd_data[cnt + 3],
5632 vpd_data[cnt+2]);
5633 break;
5634 }
5635 }
5636 }
5637
5638 if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
9dc737a7
AR		 5639 memset(nic->product_name, 0, vpd_data[1]);
5640 memcpy(nic->product_name, &vpd_data[3], vpd_data[1]);
5641 }
b41477f3 5642 kfree(vpd_data);
491976b2 5643 nic->mac_control.stats_info->sw_stat.mem_freed += 256;
9dc737a7
AR		 5644}
5645
1da177e4
LT		 5646/**
5647 * s2io_ethtool_geeprom - reads the value stored in the Eeprom.
5648 * @sp : private member of the device structure, which is a pointer to the * s2io_nic structure.
20346722 5649 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5650 * containing all relevant information.
5651 * @data_buf : user defined value to be written into Eeprom.
5652 * Description: Reads the values stored in the Eeprom at given offset
5653 * for a given length. Stores these values int the input argument data
5654 * buffer 'data_buf' and returns these to the caller (ethtool.)
5655 * Return value:
5656 * int 0 on success
5657 */
5658
5659static int s2io_ethtool_geeprom(struct net_device *dev,
20346722 5660 struct ethtool_eeprom *eeprom, u8 * data_buf)
1da177e4 5661{
ad4ebed0 5662 u32 i, valid;
5663 u64 data;
1ee6dd77 5664 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5665
5666 eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5667
5668 if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5669 eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5670
5671 for (i = 0; i < eeprom->len; i += 4) {
5672 if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5673 DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5674 return -EFAULT;
5675 }
5676 valid = INV(data);
5677 memcpy((data_buf + i), &valid, 4);
5678 }
5679 return 0;
5680}
5681
5682/**
5683 * s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5684 * @sp : private member of the device structure, which is a pointer to the
5685 * s2io_nic structure.
20346722 5686 * @eeprom : pointer to the user level structure provided by ethtool,
1da177e4
LT		 5687 * containing all relevant information.
5688 * @data_buf ; user defined value to be written into Eeprom.
5689 * Description:
5690 * Tries to write the user provided value in the Eeprom, at the offset
5691 * given by the user.
5692 * Return value:
5693 * 0 on success, -EFAULT on failure.
5694 */
5695
5696static int s2io_ethtool_seeprom(struct net_device *dev,
5697 struct ethtool_eeprom *eeprom,
5698 u8 * data_buf)
5699{
5700 int len = eeprom->len, cnt = 0;
ad4ebed0 5701 u64 valid = 0, data;
1ee6dd77 5702 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 5703
5704 if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5705 DBG_PRINT(ERR_DBG,
5706 "ETHTOOL_WRITE_EEPROM Err: Magic value ");
5707 DBG_PRINT(ERR_DBG, "is wrong, Its not 0x%x\n",
5708 eeprom->magic);
5709 return -EFAULT;
5710 }
5711
5712 while (len) {
5713 data = (u32) data_buf[cnt] & 0x000000FF;
5714 if (data) {
5715 valid = (u32) (data << 24);
5716 } else
5717 valid = data;
5718
5719 if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5720 DBG_PRINT(ERR_DBG,
5721 "ETHTOOL_WRITE_EEPROM Err: Cannot ");
5722 DBG_PRINT(ERR_DBG,
5723 "write into the specified offset\n");
5724 return -EFAULT;
5725 }
5726 cnt++;
5727 len--;
5728 }
5729
5730 return 0;
5731}
5732
5733/**
20346722
K		 5734 * s2io_register_test - reads and writes into all clock domains.
5735 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 5736 * s2io_nic structure.
5737 * @data : variable that returns the result of each of the test conducted b
5738 * by the driver.
5739 * Description:
5740 * Read and write into all clock domains. The NIC has 3 clock domains,
5741 * see that registers in all the three regions are accessible.
5742 * Return value:
5743 * 0 on success.
5744 */
5745
1ee6dd77 5746static int s2io_register_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5747{
1ee6dd77 5748 struct XENA_dev_config __iomem *bar0 = sp->bar0;
ad4ebed0 5749 u64 val64 = 0, exp_val;
1da177e4
LT		 5750 int fail = 0;
5751
20346722
K		 5752 val64 = readq(&bar0->pif_rd_swapper_fb);
5753 if (val64 != 0x123456789abcdefULL) {
1da177e4
LT		 5754 fail = 1;
5755 DBG_PRINT(INFO_DBG, "Read Test level 1 fails\n");
5756 }
5757
5758 val64 = readq(&bar0->rmac_pause_cfg);
5759 if (val64 != 0xc000ffff00000000ULL) {
5760 fail = 1;
5761 DBG_PRINT(INFO_DBG, "Read Test level 2 fails\n");
5762 }
5763
5764 val64 = readq(&bar0->rx_queue_cfg);
ad4ebed0 5765 if (sp->device_type == XFRAME_II_DEVICE)
5766 exp_val = 0x0404040404040404ULL;
5767 else
5768 exp_val = 0x0808080808080808ULL;
5769 if (val64 != exp_val) {
1da177e4
LT		 5770 fail = 1;
5771 DBG_PRINT(INFO_DBG, "Read Test level 3 fails\n");
5772 }
5773
5774 val64 = readq(&bar0->xgxs_efifo_cfg);
5775 if (val64 != 0x000000001923141EULL) {
5776 fail = 1;
5777 DBG_PRINT(INFO_DBG, "Read Test level 4 fails\n");
5778 }
5779
5780 val64 = 0x5A5A5A5A5A5A5A5AULL;
5781 writeq(val64, &bar0->xmsi_data);
5782 val64 = readq(&bar0->xmsi_data);
5783 if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5784 fail = 1;
5785 DBG_PRINT(ERR_DBG, "Write Test level 1 fails\n");
5786 }
5787
5788 val64 = 0xA5A5A5A5A5A5A5A5ULL;
5789 writeq(val64, &bar0->xmsi_data);
5790 val64 = readq(&bar0->xmsi_data);
5791 if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5792 fail = 1;
5793 DBG_PRINT(ERR_DBG, "Write Test level 2 fails\n");
5794 }
5795
5796 *data = fail;
ad4ebed0 5797 return fail;
1da177e4
LT		 5798}
5799
5800/**
20346722 5801 * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
1da177e4
LT		 5802 * @sp : private member of the device structure, which is a pointer to the
5803 * s2io_nic structure.
5804 * @data:variable that returns the result of each of the test conducted by
5805 * the driver.
5806 * Description:
20346722 5807 * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
1da177e4
LT		 5808 * register.
5809 * Return value:
5810 * 0 on success.
5811 */
5812
1ee6dd77 5813static int s2io_eeprom_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5814{
5815 int fail = 0;
ad4ebed0 5816 u64 ret_data, org_4F0, org_7F0;
5817 u8 saved_4F0 = 0, saved_7F0 = 0;
5818 struct net_device *dev = sp->dev;
1da177e4
LT		 5819
5820 /* Test Write Error at offset 0 */
ad4ebed0 5821 /* Note that SPI interface allows write access to all areas
5822 * of EEPROM. Hence doing all negative testing only for Xframe I.
5823 */
5824 if (sp->device_type == XFRAME_I_DEVICE)
5825 if (!write_eeprom(sp, 0, 0, 3))
5826 fail = 1;
5827
5828 /* Save current values at offsets 0x4F0 and 0x7F0 */
5829 if (!read_eeprom(sp, 0x4F0, &org_4F0))
5830 saved_4F0 = 1;
5831 if (!read_eeprom(sp, 0x7F0, &org_7F0))
5832 saved_7F0 = 1;
1da177e4
LT		 5833
5834 /* Test Write at offset 4f0 */
ad4ebed0 5835 if (write_eeprom(sp, 0x4F0, 0x012345, 3))
1da177e4
LT		 5836 fail = 1;
5837 if (read_eeprom(sp, 0x4F0, &ret_data))
5838 fail = 1;
5839
ad4ebed0 5840 if (ret_data != 0x012345) {
26b7625c
AM		 5841 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5842 "Data written %llx Data read %llx\n",
5843 dev->name, (unsigned long long)0x12345,
5844 (unsigned long long)ret_data);
1da177e4 5845 fail = 1;
ad4ebed0 5846 }
1da177e4
LT		 5847
5848 /* Reset the EEPROM data go FFFF */
ad4ebed0 5849 write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
1da177e4
LT		 5850
5851 /* Test Write Request Error at offset 0x7c */
ad4ebed0 5852 if (sp->device_type == XFRAME_I_DEVICE)
5853 if (!write_eeprom(sp, 0x07C, 0, 3))
5854 fail = 1;
1da177e4 5855
ad4ebed0 5856 /* Test Write Request at offset 0x7f0 */
5857 if (write_eeprom(sp, 0x7F0, 0x012345, 3))
1da177e4 5858 fail = 1;
ad4ebed0 5859 if (read_eeprom(sp, 0x7F0, &ret_data))
1da177e4
LT		 5860 fail = 1;
5861
ad4ebed0 5862 if (ret_data != 0x012345) {
26b7625c
AM		 5863 DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5864 "Data written %llx Data read %llx\n",
5865 dev->name, (unsigned long long)0x12345,
5866 (unsigned long long)ret_data);
1da177e4 5867 fail = 1;
ad4ebed0 5868 }
1da177e4
LT		 5869
5870 /* Reset the EEPROM data go FFFF */
ad4ebed0 5871 write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
1da177e4 5872
ad4ebed0 5873 if (sp->device_type == XFRAME_I_DEVICE) {
5874 /* Test Write Error at offset 0x80 */
5875 if (!write_eeprom(sp, 0x080, 0, 3))
5876 fail = 1;
1da177e4 5877
ad4ebed0 5878 /* Test Write Error at offset 0xfc */
5879 if (!write_eeprom(sp, 0x0FC, 0, 3))
5880 fail = 1;
1da177e4 5881
ad4ebed0 5882 /* Test Write Error at offset 0x100 */
5883 if (!write_eeprom(sp, 0x100, 0, 3))
5884 fail = 1;
1da177e4 5885
ad4ebed0 5886 /* Test Write Error at offset 4ec */
5887 if (!write_eeprom(sp, 0x4EC, 0, 3))
5888 fail = 1;
5889 }
5890
5891 /* Restore values at offsets 0x4F0 and 0x7F0 */
5892 if (saved_4F0)
5893 write_eeprom(sp, 0x4F0, org_4F0, 3);
5894 if (saved_7F0)
5895 write_eeprom(sp, 0x7F0, org_7F0, 3);
1da177e4
LT		 5896
5897 *data = fail;
ad4ebed0 5898 return fail;
1da177e4
LT		 5899}
5900
5901/**
5902 * s2io_bist_test - invokes the MemBist test of the card .
20346722 5903 * @sp : private member of the device structure, which is a pointer to the
1da177e4 5904 * s2io_nic structure.
20346722 5905 * @data:variable that returns the result of each of the test conducted by
1da177e4
LT		 5906 * the driver.
5907 * Description:
5908 * This invokes the MemBist test of the card. We give around
5909 * 2 secs time for the Test to complete. If it's still not complete
20346722 5910 * within this peiod, we consider that the test failed.
1da177e4
LT		 5911 * Return value:
5912 * 0 on success and -1 on failure.
5913 */
5914
1ee6dd77 5915static int s2io_bist_test(struct s2io_nic * sp, uint64_t * data)
1da177e4
LT		 5916{
5917 u8 bist = 0;
5918 int cnt = 0, ret = -1;
5919
5920 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5921 bist |= PCI_BIST_START;
5922 pci_write_config_word(sp->pdev, PCI_BIST, bist);
5923
5924 while (cnt < 20) {
5925 pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
5926 if (!(bist & PCI_BIST_START)) {
5927 *data = (bist & PCI_BIST_CODE_MASK);
5928 ret = 0;
5929 break;
5930 }
5931 msleep(100);
5932 cnt++;
5933 }
5934
5935 return ret;
5936}
5937
5938/**
20346722
K		 5939 * s2io-link_test - verifies the link state of the nic
5940 * @sp ; private member of the device structure, which is a pointer to the
1da177e4
LT		 5941 * s2io_nic structure.
5942 * @data: variable that returns the result of each of the test conducted by
5943 * the driver.
5944 * Description:
20346722 5945 * The function verifies the link state of the NIC and updates the input
1da177e4
LT		 5946 * argument 'data' appropriately.
5947 * Return value:
5948 * 0 on success.
5949 */
5950
1ee6dd77 5951static int s2io_link_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5952{
1ee6dd77 5953 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4
LT		 5954 u64 val64;
5955
5956 val64 = readq(&bar0->adapter_status);
c92ca04b 5957 if(!(LINK_IS_UP(val64)))
1da177e4 5958 *data = 1;
c92ca04b
AR		 5959 else
5960 *data = 0;
1da177e4 5961
b41477f3 5962 return *data;
1da177e4
LT		 5963}
5964
5965/**
20346722
K		 5966 * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
5967 * @sp - private member of the device structure, which is a pointer to the
1da177e4 5968 * s2io_nic structure.
20346722 5969 * @data - variable that returns the result of each of the test
1da177e4
LT		 5970 * conducted by the driver.
5971 * Description:
20346722 5972 * This is one of the offline test that tests the read and write
1da177e4
LT		 5973 * access to the RldRam chip on the NIC.
5974 * Return value:
5975 * 0 on success.
5976 */
5977
1ee6dd77 5978static int s2io_rldram_test(struct s2io_nic * sp, uint64_t * data)
1da177e4 5979{
1ee6dd77 5980 struct XENA_dev_config __iomem *bar0 = sp->bar0;
1da177e4 5981 u64 val64;
ad4ebed0 5982 int cnt, iteration = 0, test_fail = 0;
1da177e4
LT		 5983
5984 val64 = readq(&bar0->adapter_control);
5985 val64 &= ~ADAPTER_ECC_EN;
5986 writeq(val64, &bar0->adapter_control);
5987
5988 val64 = readq(&bar0->mc_rldram_test_ctrl);
5989 val64 |= MC_RLDRAM_TEST_MODE;
ad4ebed0 5990 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 5991
5992 val64 = readq(&bar0->mc_rldram_mrs);
5993 val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
5994 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5995
5996 val64 |= MC_RLDRAM_MRS_ENABLE;
5997 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
5998
5999 while (iteration < 2) {
6000 val64 = 0x55555555aaaa0000ULL;
6001 if (iteration == 1) {
6002 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6003 }
6004 writeq(val64, &bar0->mc_rldram_test_d0);
6005
6006 val64 = 0xaaaa5a5555550000ULL;
6007 if (iteration == 1) {
6008 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6009 }
6010 writeq(val64, &bar0->mc_rldram_test_d1);
6011
6012 val64 = 0x55aaaaaaaa5a0000ULL;
6013 if (iteration == 1) {
6014 val64 ^= 0xFFFFFFFFFFFF0000ULL;
6015 }
6016 writeq(val64, &bar0->mc_rldram_test_d2);
6017
ad4ebed0 6018 val64 = (u64) (0x0000003ffffe0100ULL);
1da177e4
LT		 6019 writeq(val64, &bar0->mc_rldram_test_add);
6020
ad4ebed0 6021 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_WRITE |
6022 MC_RLDRAM_TEST_GO;
6023 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6024
6025 for (cnt = 0; cnt < 5; cnt++) {
6026 val64 = readq(&bar0->mc_rldram_test_ctrl);
6027 if (val64 & MC_RLDRAM_TEST_DONE)
6028 break;
6029 msleep(200);
6030 }
6031
6032 if (cnt == 5)
6033 break;
6034
ad4ebed0 6035 val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6036 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
1da177e4
LT		 6037
6038 for (cnt = 0; cnt < 5; cnt++) {
6039 val64 = readq(&bar0->mc_rldram_test_ctrl);
6040 if (val64 & MC_RLDRAM_TEST_DONE)
6041 break;
6042 msleep(500);
6043 }
6044
6045 if (cnt == 5)
6046 break;
6047
6048 val64 = readq(&bar0->mc_rldram_test_ctrl);
ad4ebed0 6049 if (!(val64 & MC_RLDRAM_TEST_PASS))
6050 test_fail = 1;
1da177e4
LT		 6051
6052 iteration++;
6053 }
6054
ad4ebed0 6055 *data = test_fail;
1da177e4 6056
ad4ebed0 6057 /* Bring the adapter out of test mode */
6058 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6059
6060 return test_fail;
1da177e4
LT		 6061}
6062
6063/**
6064 * s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6065 * @sp : private member of the device structure, which is a pointer to the
6066 * s2io_nic structure.
6067 * @ethtest : pointer to a ethtool command specific structure that will be
6068 * returned to the user.
20346722 6069 * @data : variable that returns the result of each of the test
1da177e4
LT		 6070 * conducted by the driver.
6071 * Description:
6072 * This function conducts 6 tests ( 4 offline and 2 online) to determine
6073 * the health of the card.
6074 * Return value:
6075 * void
6076 */
6077
6078static void s2io_ethtool_test(struct net_device *dev,
6079 struct ethtool_test *ethtest,
6080 uint64_t * data)
6081{
1ee6dd77 6082 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6083 int orig_state = netif_running(sp->dev);
6084
6085 if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6086 /* Offline Tests. */
20346722 6087 if (orig_state)
1da177e4 6088 s2io_close(sp->dev);
1da177e4
LT		 6089
6090 if (s2io_register_test(sp, &data[0]))
6091 ethtest->flags |= ETH_TEST_FL_FAILED;
6092
6093 s2io_reset(sp);
1da177e4
LT		 6094
6095 if (s2io_rldram_test(sp, &data[3]))
6096 ethtest->flags |= ETH_TEST_FL_FAILED;
6097
6098 s2io_reset(sp);
1da177e4
LT		 6099
6100 if (s2io_eeprom_test(sp, &data[1]))
6101 ethtest->flags |= ETH_TEST_FL_FAILED;
6102
6103 if (s2io_bist_test(sp, &data[4]))
6104 ethtest->flags |= ETH_TEST_FL_FAILED;
6105
6106 if (orig_state)
6107 s2io_open(sp->dev);
6108
6109 data[2] = 0;
6110 } else {
6111 /* Online Tests. */
6112 if (!orig_state) {
6113 DBG_PRINT(ERR_DBG,
6114 "%s: is not up, cannot run test\n",
6115 dev->name);
6116 data[0] = -1;
6117 data[1] = -1;
6118 data[2] = -1;
6119 data[3] = -1;
6120 data[4] = -1;
6121 }
6122
6123 if (s2io_link_test(sp, &data[2]))
6124 ethtest->flags |= ETH_TEST_FL_FAILED;
6125
6126 data[0] = 0;
6127 data[1] = 0;
6128 data[3] = 0;
6129 data[4] = 0;
6130 }
6131}
6132
6133static void s2io_get_ethtool_stats(struct net_device *dev,
6134 struct ethtool_stats *estats,
6135 u64 * tmp_stats)
6136{
8116f3cf 6137 int i = 0, k;
1ee6dd77
RB		 6138 struct s2io_nic *sp = dev->priv;
6139 struct stat_block *stat_info = sp->mac_control.stats_info;
1da177e4 6140
7ba013ac 6141 s2io_updt_stats(sp);
541ae68f
K		 6142 tmp_stats[i++] =
6143 (u64)le32_to_cpu(stat_info->tmac_frms_oflow) << 32 |
6144 le32_to_cpu(stat_info->tmac_frms);
6145 tmp_stats[i++] =
6146 (u64)le32_to_cpu(stat_info->tmac_data_octets_oflow) << 32 |
6147 le32_to_cpu(stat_info->tmac_data_octets);
1da177e4 6148 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_drop_frms);
541ae68f
K		 6149 tmp_stats[i++] =
6150 (u64)le32_to_cpu(stat_info->tmac_mcst_frms_oflow) << 32 |
6151 le32_to_cpu(stat_info->tmac_mcst_frms);
6152 tmp_stats[i++] =
6153 (u64)le32_to_cpu(stat_info->tmac_bcst_frms_oflow) << 32 |
6154 le32_to_cpu(stat_info->tmac_bcst_frms);
1da177e4 6155 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_pause_ctrl_frms);
bd1034f0
AR		 6156 tmp_stats[i++] =
6157 (u64)le32_to_cpu(stat_info->tmac_ttl_octets_oflow) << 32 |
6158 le32_to_cpu(stat_info->tmac_ttl_octets);
6159 tmp_stats[i++] =
6160 (u64)le32_to_cpu(stat_info->tmac_ucst_frms_oflow) << 32 |
6161 le32_to_cpu(stat_info->tmac_ucst_frms);
6162 tmp_stats[i++] =
6163 (u64)le32_to_cpu(stat_info->tmac_nucst_frms_oflow) << 32 |
6164 le32_to_cpu(stat_info->tmac_nucst_frms);
541ae68f
K		 6165 tmp_stats[i++] =
6166 (u64)le32_to_cpu(stat_info->tmac_any_err_frms_oflow) << 32 |
6167 le32_to_cpu(stat_info->tmac_any_err_frms);
bd1034f0 6168 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_ttl_less_fb_octets);
1da177e4 6169 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_vld_ip_octets);
541ae68f
K		 6170 tmp_stats[i++] =
6171 (u64)le32_to_cpu(stat_info->tmac_vld_ip_oflow) << 32 |
6172 le32_to_cpu(stat_info->tmac_vld_ip);
6173 tmp_stats[i++] =
6174 (u64)le32_to_cpu(stat_info->tmac_drop_ip_oflow) << 32 |
6175 le32_to_cpu(stat_info->tmac_drop_ip);
6176 tmp_stats[i++] =
6177 (u64)le32_to_cpu(stat_info->tmac_icmp_oflow) << 32 |
6178 le32_to_cpu(stat_info->tmac_icmp);
6179 tmp_stats[i++] =
6180 (u64)le32_to_cpu(stat_info->tmac_rst_tcp_oflow) << 32 |
6181 le32_to_cpu(stat_info->tmac_rst_tcp);
1da177e4 6182 tmp_stats[i++] = le64_to_cpu(stat_info->tmac_tcp);
541ae68f
K		 6183 tmp_stats[i++] = (u64)le32_to_cpu(stat_info->tmac_udp_oflow) << 32 |
6184 le32_to_cpu(stat_info->tmac_udp);
6185 tmp_stats[i++] =
6186 (u64)le32_to_cpu(stat_info->rmac_vld_frms_oflow) << 32 |
6187 le32_to_cpu(stat_info->rmac_vld_frms);
6188 tmp_stats[i++] =
6189 (u64)le32_to_cpu(stat_info->rmac_data_octets_oflow) << 32 |
6190 le32_to_cpu(stat_info->rmac_data_octets);
1da177e4
LT		 6191 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_fcs_err_frms);
6192 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_drop_frms);
541ae68f
K		 6193 tmp_stats[i++] =
6194 (u64)le32_to_cpu(stat_info->rmac_vld_mcst_frms_oflow) << 32 |
6195 le32_to_cpu(stat_info->rmac_vld_mcst_frms);
6196 tmp_stats[i++] =
6197 (u64)le32_to_cpu(stat_info->rmac_vld_bcst_frms_oflow) << 32 |
6198 le32_to_cpu(stat_info->rmac_vld_bcst_frms);
1da177e4 6199 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_in_rng_len_err_frms);
bd1034f0 6200 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_out_rng_len_err_frms);
1da177e4
LT		 6201 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_long_frms);
6202 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_pause_ctrl_frms);
bd1034f0
AR		 6203 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_unsup_ctrl_frms);
6204 tmp_stats[i++] =
6205 (u64)le32_to_cpu(stat_info->rmac_ttl_octets_oflow) << 32 |
6206 le32_to_cpu(stat_info->rmac_ttl_octets);
6207 tmp_stats[i++] =
6208 (u64)le32_to_cpu(stat_info->rmac_accepted_ucst_frms_oflow)
6209 << 32 | le32_to_cpu(stat_info->rmac_accepted_ucst_frms);
6210 tmp_stats[i++] =
6211 (u64)le32_to_cpu(stat_info->rmac_accepted_nucst_frms_oflow)
6212 << 32 | le32_to_cpu(stat_info->rmac_accepted_nucst_frms);
541ae68f
K		 6213 tmp_stats[i++] =
6214 (u64)le32_to_cpu(stat_info->rmac_discarded_frms_oflow) << 32 |
6215 le32_to_cpu(stat_info->rmac_discarded_frms);
bd1034f0
AR		 6216 tmp_stats[i++] =
6217 (u64)le32_to_cpu(stat_info->rmac_drop_events_oflow)
6218 << 32 | le32_to_cpu(stat_info->rmac_drop_events);
6219 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_less_fb_octets);
6220 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_frms);
541ae68f
K		 6221 tmp_stats[i++] =
6222 (u64)le32_to_cpu(stat_info->rmac_usized_frms_oflow) << 32 |
6223 le32_to_cpu(stat_info->rmac_usized_frms);
6224 tmp_stats[i++] =
6225 (u64)le32_to_cpu(stat_info->rmac_osized_frms_oflow) << 32 |
6226 le32_to_cpu(stat_info->rmac_osized_frms);
6227 tmp_stats[i++] =
6228 (u64)le32_to_cpu(stat_info->rmac_frag_frms_oflow) << 32 |
6229 le32_to_cpu(stat_info->rmac_frag_frms);
6230 tmp_stats[i++] =
6231 (u64)le32_to_cpu(stat_info->rmac_jabber_frms_oflow) << 32 |
6232 le32_to_cpu(stat_info->rmac_jabber_frms);
bd1034f0
AR		 6233 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_64_frms);
6234 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_65_127_frms);
6235 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_128_255_frms);
6236 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_256_511_frms);
6237 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_512_1023_frms);
6238 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_1024_1518_frms);
6239 tmp_stats[i++] =
6240 (u64)le32_to_cpu(stat_info->rmac_ip_oflow) << 32 |
541ae68f 6241 le32_to_cpu(stat_info->rmac_ip);
1da177e4
LT		 6242 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ip_octets);
6243 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_hdr_err_ip);
bd1034f0
AR		 6244 tmp_stats[i++] =
6245 (u64)le32_to_cpu(stat_info->rmac_drop_ip_oflow) << 32 |
541ae68f 6246 le32_to_cpu(stat_info->rmac_drop_ip);
bd1034f0
AR		 6247 tmp_stats[i++] =
6248 (u64)le32_to_cpu(stat_info->rmac_icmp_oflow) << 32 |
541ae68f 6249 le32_to_cpu(stat_info->rmac_icmp);
1da177e4 6250 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_tcp);
bd1034f0
AR		 6251 tmp_stats[i++] =
6252 (u64)le32_to_cpu(stat_info->rmac_udp_oflow) << 32 |
541ae68f
K		 6253 le32_to_cpu(stat_info->rmac_udp);
6254 tmp_stats[i++] =
6255 (u64)le32_to_cpu(stat_info->rmac_err_drp_udp_oflow) << 32 |
6256 le32_to_cpu(stat_info->rmac_err_drp_udp);
bd1034f0
AR		 6257 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_err_sym);
6258 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q0);
6259 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q1);
6260 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q2);
6261 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q3);
6262 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q4);
6263 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q5);
6264 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q6);
6265 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_frms_q7);
6266 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q0);
6267 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q1);
6268 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q2);
6269 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q3);
6270 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q4);
6271 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q5);
6272 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q6);
6273 tmp_stats[i++] = le16_to_cpu(stat_info->rmac_full_q7);
541ae68f
K		 6274 tmp_stats[i++] =
6275 (u64)le32_to_cpu(stat_info->rmac_pause_cnt_oflow) << 32 |
6276 le32_to_cpu(stat_info->rmac_pause_cnt);
bd1034f0
AR		 6277 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_data_err_cnt);
6278 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_xgmii_ctrl_err_cnt);
541ae68f
K		 6279 tmp_stats[i++] =
6280 (u64)le32_to_cpu(stat_info->rmac_accepted_ip_oflow) << 32 |
6281 le32_to_cpu(stat_info->rmac_accepted_ip);
1da177e4 6282 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_err_tcp);
bd1034f0
AR		 6283 tmp_stats[i++] = le32_to_cpu(stat_info->rd_req_cnt);
6284 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_cnt);
6285 tmp_stats[i++] = le32_to_cpu(stat_info->new_rd_req_rtry_cnt);
6286 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_cnt);
6287 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_rd_ack_cnt);
6288 tmp_stats[i++] = le32_to_cpu(stat_info->wr_req_cnt);
6289 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_cnt);
6290 tmp_stats[i++] = le32_to_cpu(stat_info->new_wr_req_rtry_cnt);
6291 tmp_stats[i++] = le32_to_cpu(stat_info->wr_rtry_cnt);
6292 tmp_stats[i++] = le32_to_cpu(stat_info->wr_disc_cnt);
6293 tmp_stats[i++] = le32_to_cpu(stat_info->rd_rtry_wr_ack_cnt);
6294 tmp_stats[i++] = le32_to_cpu(stat_info->txp_wr_cnt);
6295 tmp_stats[i++] = le32_to_cpu(stat_info->txd_rd_cnt);
6296 tmp_stats[i++] = le32_to_cpu(stat_info->txd_wr_cnt);
6297 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_rd_cnt);
6298 tmp_stats[i++] = le32_to_cpu(stat_info->rxd_wr_cnt);
6299 tmp_stats[i++] = le32_to_cpu(stat_info->txf_rd_cnt);
6300 tmp_stats[i++] = le32_to_cpu(stat_info->rxf_wr_cnt);
fa1f0cb3
SS		 6301
6302 /* Enhanced statistics exist only for Hercules */
6303 if(sp->device_type == XFRAME_II_DEVICE) {
6304 tmp_stats[i++] =
6305 le64_to_cpu(stat_info->rmac_ttl_1519_4095_frms);
6306 tmp_stats[i++] =
6307 le64_to_cpu(stat_info->rmac_ttl_4096_8191_frms);
6308 tmp_stats[i++] =
6309 le64_to_cpu(stat_info->rmac_ttl_8192_max_frms);
6310 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_ttl_gt_max_frms);
6311 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_osized_alt_frms);
6312 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_jabber_alt_frms);
6313 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_gt_max_alt_frms);
6314 tmp_stats[i++] = le64_to_cpu(stat_info->rmac_vlan_frms);
6315 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_len_discard);
6316 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_fcs_discard);
6317 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_pf_discard);
6318 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_da_discard);
6319 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_red_discard);
6320 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_rts_discard);
6321 tmp_stats[i++] = le32_to_cpu(stat_info->rmac_ingm_full_discard);
6322 tmp_stats[i++] = le32_to_cpu(stat_info->link_fault_cnt);
6323 }
6324
7ba013ac
K		 6325 tmp_stats[i++] = 0;
6326 tmp_stats[i++] = stat_info->sw_stat.single_ecc_errs;
6327 tmp_stats[i++] = stat_info->sw_stat.double_ecc_errs;
bd1034f0
AR		 6328 tmp_stats[i++] = stat_info->sw_stat.parity_err_cnt;
6329 tmp_stats[i++] = stat_info->sw_stat.serious_err_cnt;
6330 tmp_stats[i++] = stat_info->sw_stat.soft_reset_cnt;
6331 tmp_stats[i++] = stat_info->sw_stat.fifo_full_cnt;
8116f3cf
SS		 6332 for (k = 0; k < MAX_RX_RINGS; k++)
6333 tmp_stats[i++] = stat_info->sw_stat.ring_full_cnt[k];
bd1034f0
AR		 6334 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_high;
6335 tmp_stats[i++] = stat_info->xpak_stat.alarm_transceiver_temp_low;
6336 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_high;
6337 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_bias_current_low;
6338 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_high;
6339 tmp_stats[i++] = stat_info->xpak_stat.alarm_laser_output_power_low;
6340 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_high;
6341 tmp_stats[i++] = stat_info->xpak_stat.warn_transceiver_temp_low;
6342 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_high;
6343 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_bias_current_low;
6344 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_high;
6345 tmp_stats[i++] = stat_info->xpak_stat.warn_laser_output_power_low;
7d3d0439
RA		 6346 tmp_stats[i++] = stat_info->sw_stat.clubbed_frms_cnt;
6347 tmp_stats[i++] = stat_info->sw_stat.sending_both;
6348 tmp_stats[i++] = stat_info->sw_stat.outof_sequence_pkts;
6349 tmp_stats[i++] = stat_info->sw_stat.flush_max_pkts;
fe931395 6350 if (stat_info->sw_stat.num_aggregations) {
bd1034f0
AR		 6351 u64 tmp = stat_info->sw_stat.sum_avg_pkts_aggregated;
6352 int count = 0;
6aa20a22 6353 /*
bd1034f0
AR		 6354 * Since 64-bit divide does not work on all platforms,
6355 * do repeated subtraction.
6356 */
6357 while (tmp >= stat_info->sw_stat.num_aggregations) {
6358 tmp -= stat_info->sw_stat.num_aggregations;
6359 count++;
6360 }
6361 tmp_stats[i++] = count;
fe931395 6362 }
bd1034f0
AR		 6363 else
6364 tmp_stats[i++] = 0;
c53d4945 6365 tmp_stats[i++] = stat_info->sw_stat.mem_alloc_fail_cnt;
491abf25 6366 tmp_stats[i++] = stat_info->sw_stat.pci_map_fail_cnt;
c53d4945 6367 tmp_stats[i++] = stat_info->sw_stat.watchdog_timer_cnt;
491976b2
SH		 6368 tmp_stats[i++] = stat_info->sw_stat.mem_allocated;
6369 tmp_stats[i++] = stat_info->sw_stat.mem_freed;
6370 tmp_stats[i++] = stat_info->sw_stat.link_up_cnt;
6371 tmp_stats[i++] = stat_info->sw_stat.link_down_cnt;
6372 tmp_stats[i++] = stat_info->sw_stat.link_up_time;
6373 tmp_stats[i++] = stat_info->sw_stat.link_down_time;
6374
6375 tmp_stats[i++] = stat_info->sw_stat.tx_buf_abort_cnt;
6376 tmp_stats[i++] = stat_info->sw_stat.tx_desc_abort_cnt;
6377 tmp_stats[i++] = stat_info->sw_stat.tx_parity_err_cnt;
6378 tmp_stats[i++] = stat_info->sw_stat.tx_link_loss_cnt;
6379 tmp_stats[i++] = stat_info->sw_stat.tx_list_proc_err_cnt;
6380
6381 tmp_stats[i++] = stat_info->sw_stat.rx_parity_err_cnt;
6382 tmp_stats[i++] = stat_info->sw_stat.rx_abort_cnt;
6383 tmp_stats[i++] = stat_info->sw_stat.rx_parity_abort_cnt;
6384 tmp_stats[i++] = stat_info->sw_stat.rx_rda_fail_cnt;
6385 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_prot_cnt;
6386 tmp_stats[i++] = stat_info->sw_stat.rx_fcs_err_cnt;
6387 tmp_stats[i++] = stat_info->sw_stat.rx_buf_size_err_cnt;
6388 tmp_stats[i++] = stat_info->sw_stat.rx_rxd_corrupt_cnt;
6389 tmp_stats[i++] = stat_info->sw_stat.rx_unkn_err_cnt;
8116f3cf
SS		 6390 tmp_stats[i++] = stat_info->sw_stat.tda_err_cnt;
6391 tmp_stats[i++] = stat_info->sw_stat.pfc_err_cnt;
6392 tmp_stats[i++] = stat_info->sw_stat.pcc_err_cnt;
6393 tmp_stats[i++] = stat_info->sw_stat.tti_err_cnt;
6394 tmp_stats[i++] = stat_info->sw_stat.tpa_err_cnt;
6395 tmp_stats[i++] = stat_info->sw_stat.sm_err_cnt;
6396 tmp_stats[i++] = stat_info->sw_stat.lso_err_cnt;
6397 tmp_stats[i++] = stat_info->sw_stat.mac_tmac_err_cnt;
6398 tmp_stats[i++] = stat_info->sw_stat.mac_rmac_err_cnt;
6399 tmp_stats[i++] = stat_info->sw_stat.xgxs_txgxs_err_cnt;
6400 tmp_stats[i++] = stat_info->sw_stat.xgxs_rxgxs_err_cnt;
6401 tmp_stats[i++] = stat_info->sw_stat.rc_err_cnt;
6402 tmp_stats[i++] = stat_info->sw_stat.prc_pcix_err_cnt;
6403 tmp_stats[i++] = stat_info->sw_stat.rpa_err_cnt;
6404 tmp_stats[i++] = stat_info->sw_stat.rda_err_cnt;
6405 tmp_stats[i++] = stat_info->sw_stat.rti_err_cnt;
6406 tmp_stats[i++] = stat_info->sw_stat.mc_err_cnt;
1da177e4
LT		 6407}
6408
ac1f60db 6409static int s2io_ethtool_get_regs_len(struct net_device *dev)
1da177e4
LT		 6410{
6411 return (XENA_REG_SPACE);
6412}
6413
6414
ac1f60db 6415static u32 s2io_ethtool_get_rx_csum(struct net_device * dev)
1da177e4 6416{
1ee6dd77 6417 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6418
6419 return (sp->rx_csum);
6420}
ac1f60db
AB		 6421
6422static int s2io_ethtool_set_rx_csum(struct net_device *dev, u32 data)
1da177e4 6423{
1ee6dd77 6424 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 6425
6426 if (data)
6427 sp->rx_csum = 1;
6428 else
6429 sp->rx_csum = 0;
6430
6431 return 0;
6432}
ac1f60db
AB		 6433
6434static int s2io_get_eeprom_len(struct net_device *dev)
1da177e4
LT		 6435{
6436 return (XENA_EEPROM_SPACE);
6437}
6438
b9f2c044 6439static int s2io_get_sset_count(struct net_device *dev, int sset)
1da177e4 6440{
b9f2c044
JG		 6441 struct s2io_nic *sp = dev->priv;
6442
6443 switch (sset) {
6444 case ETH_SS_TEST:
6445 return S2IO_TEST_LEN;
6446 case ETH_SS_STATS:
6447 switch(sp->device_type) {
6448 case XFRAME_I_DEVICE:
6449 return XFRAME_I_STAT_LEN;
6450 case XFRAME_II_DEVICE:
6451 return XFRAME_II_STAT_LEN;
6452 default:
6453 return 0;
6454 }
6455 default:
6456 return -EOPNOTSUPP;
6457 }
1da177e4 6458}
ac1f60db
AB		 6459
6460static void s2io_ethtool_get_strings(struct net_device *dev,
6461 u32 stringset, u8 * data)
1da177e4 6462{
fa1f0cb3
SS		 6463 int stat_size = 0;
6464 struct s2io_nic *sp = dev->priv;
6465
1da177e4
LT		 6466 switch (stringset) {
6467 case ETH_SS_TEST:
6468 memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6469 break;
6470 case ETH_SS_STATS:
fa1f0cb3
SS		 6471 stat_size = sizeof(ethtool_xena_stats_keys);
6472 memcpy(data, &ethtool_xena_stats_keys,stat_size);
6473 if(sp->device_type == XFRAME_II_DEVICE) {
6474 memcpy(data + stat_size,
6475 &ethtool_enhanced_stats_keys,
6476 sizeof(ethtool_enhanced_stats_keys));
6477 stat_size += sizeof(ethtool_enhanced_stats_keys);
6478 }
6479
6480 memcpy(data + stat_size, &ethtool_driver_stats_keys,
6481 sizeof(ethtool_driver_stats_keys));
1da177e4
LT		 6482 }
6483}
1da177e4 6484
ac1f60db 6485static int s2io_ethtool_op_set_tx_csum(struct net_device *dev, u32 data)
1da177e4
LT		 6486{
6487 if (data)
6488 dev->features |= NETIF_F_IP_CSUM;
6489 else
6490 dev->features &= ~NETIF_F_IP_CSUM;
6491
6492 return 0;
6493}
6494
75c30b13
AR		 6495static u32 s2io_ethtool_op_get_tso(struct net_device *dev)
6496{
6497 return (dev->features & NETIF_F_TSO) != 0;
6498}
6499static int s2io_ethtool_op_set_tso(struct net_device *dev, u32 data)
6500{
6501 if (data)
6502 dev->features |= (NETIF_F_TSO | NETIF_F_TSO6);
6503 else
6504 dev->features &= ~(NETIF_F_TSO | NETIF_F_TSO6);
6505
6506 return 0;
6507}
1da177e4 6508
7282d491 6509static const struct ethtool_ops netdev_ethtool_ops = {
1da177e4
LT		 6510 .get_settings = s2io_ethtool_gset,
6511 .set_settings = s2io_ethtool_sset,
6512 .get_drvinfo = s2io_ethtool_gdrvinfo,
6513 .get_regs_len = s2io_ethtool_get_regs_len,
6514 .get_regs = s2io_ethtool_gregs,
6515 .get_link = ethtool_op_get_link,
6516 .get_eeprom_len = s2io_get_eeprom_len,
6517 .get_eeprom = s2io_ethtool_geeprom,
6518 .set_eeprom = s2io_ethtool_seeprom,
0cec35eb 6519 .get_ringparam = s2io_ethtool_gringparam,
1da177e4
LT		 6520 .get_pauseparam = s2io_ethtool_getpause_data,
6521 .set_pauseparam = s2io_ethtool_setpause_data,
6522 .get_rx_csum = s2io_ethtool_get_rx_csum,
6523 .set_rx_csum = s2io_ethtool_set_rx_csum,
1da177e4 6524 .set_tx_csum = s2io_ethtool_op_set_tx_csum,
1da177e4 6525 .set_sg = ethtool_op_set_sg,
75c30b13
AR		 6526 .get_tso = s2io_ethtool_op_get_tso,
6527 .set_tso = s2io_ethtool_op_set_tso,
fed5eccd 6528 .set_ufo = ethtool_op_set_ufo,
1da177e4
LT		 6529 .self_test = s2io_ethtool_test,
6530 .get_strings = s2io_ethtool_get_strings,
6531 .phys_id = s2io_ethtool_idnic,
b9f2c044
JG		 6532 .get_ethtool_stats = s2io_get_ethtool_stats,
6533 .get_sset_count = s2io_get_sset_count,
1da177e4
LT		 6534};
6535
6536/**
20346722 6537 * s2io_ioctl - Entry point for the Ioctl
1da177e4
LT		 6538 * @dev : Device pointer.
6539 * @ifr : An IOCTL specefic structure, that can contain a pointer to
6540 * a proprietary structure used to pass information to the driver.
6541 * @cmd : This is used to distinguish between the different commands that
6542 * can be passed to the IOCTL functions.
6543 * Description:
20346722
K		 6544 * Currently there are no special functionality supported in IOCTL, hence
6545 * function always return EOPNOTSUPPORTED
1da177e4
LT		 6546 */
6547
ac1f60db 6548static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1da177e4
LT		 6549{
6550 return -EOPNOTSUPP;
6551}
6552
6553/**
6554 * s2io_change_mtu - entry point to change MTU size for the device.
6555 * @dev : device pointer.
6556 * @new_mtu : the new MTU size for the device.
6557 * Description: A driver entry point to change MTU size for the device.
6558 * Before changing the MTU the device must be stopped.
6559 * Return value:
6560 * 0 on success and an appropriate (-)ve integer as defined in errno.h
6561 * file on failure.
6562 */
6563
ac1f60db 6564static int s2io_change_mtu(struct net_device *dev, int new_mtu)
1da177e4 6565{
1ee6dd77 6566 struct s2io_nic *sp = dev->priv;
9f74ffde 6567 int ret = 0;
1da177e4
LT		 6568
6569 if ((new_mtu < MIN_MTU) || (new_mtu > S2IO_JUMBO_SIZE)) {
6570 DBG_PRINT(ERR_DBG, "%s: MTU size is invalid.\n",
6571 dev->name);
6572 return -EPERM;
6573 }
6574
1da177e4 6575 dev->mtu = new_mtu;
d8892c6e 6576 if (netif_running(dev)) {
e6a8fee2 6577 s2io_card_down(sp);
d8892c6e 6578 netif_stop_queue(dev);
9f74ffde
SH		 6579 ret = s2io_card_up(sp);
6580 if (ret) {
d8892c6e
K		 6581 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6582 __FUNCTION__);
9f74ffde 6583 return ret;
d8892c6e
K		 6584 }
6585 if (netif_queue_stopped(dev))
6586 netif_wake_queue(dev);
6587 } else { /* Device is down */
1ee6dd77 6588 struct XENA_dev_config __iomem *bar0 = sp->bar0;
d8892c6e
K		 6589 u64 val64 = new_mtu;
6590
6591 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6592 }
1da177e4 6593
9f74ffde 6594 return ret;
1da177e4
LT		 6595}
6596
6597/**
6598 * s2io_tasklet - Bottom half of the ISR.
6599 * @dev_adr : address of the device structure in dma_addr_t format.
6600 * Description:
6601 * This is the tasklet or the bottom half of the ISR. This is
20346722 6602 * an extension of the ISR which is scheduled by the scheduler to be run
1da177e4 6603 * when the load on the CPU is low. All low priority tasks of the ISR can
20346722 6604 * be pushed into the tasklet. For now the tasklet is used only to
1da177e4
LT		 6605 * replenish the Rx buffers in the Rx buffer descriptors.
6606 * Return value:
6607 * void.
6608 */
6609
6610static void s2io_tasklet(unsigned long dev_addr)
6611{
6612 struct net_device *dev = (struct net_device *) dev_addr;
1ee6dd77 6613 struct s2io_nic *sp = dev->priv;
1da177e4 6614 int i, ret;
1ee6dd77 6615 struct mac_info *mac_control;
1da177e4
LT		 6616 struct config_param *config;
6617
6618 mac_control = &sp->mac_control;
6619 config = &sp->config;
6620
6621 if (!TASKLET_IN_USE) {
6622 for (i = 0; i < config->rx_ring_num; i++) {
6623 ret = fill_rx_buffers(sp, i);
6624 if (ret == -ENOMEM) {
0c61ed5f 6625 DBG_PRINT(INFO_DBG, "%s: Out of ",
1da177e4 6626 dev->name);
491976b2 6627 DBG_PRINT(INFO_DBG, "memory in tasklet\n");
1da177e4
LT		 6628 break;
6629 } else if (ret == -EFILL) {
0c61ed5f 6630 DBG_PRINT(INFO_DBG,
1da177e4
LT		 6631 "%s: Rx Ring %d is full\n",
6632 dev->name, i);
6633 break;
6634 }
6635 }
6636 clear_bit(0, (&sp->tasklet_status));
6637 }
6638}
6639
6640/**
6641 * s2io_set_link - Set the LInk status
6642 * @data: long pointer to device private structue
6643 * Description: Sets the link status for the adapter
6644 */
6645
c4028958 6646static void s2io_set_link(struct work_struct *work)
1da177e4 6647{
1ee6dd77 6648 struct s2io_nic *nic = container_of(work, struct s2io_nic, set_link_task);
1da177e4 6649 struct net_device *dev = nic->dev;
1ee6dd77 6650 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1da177e4
LT		 6651 register u64 val64;
6652 u16 subid;
6653
22747d6b
FR		 6654 rtnl_lock();
6655
6656 if (!netif_running(dev))
6657 goto out_unlock;
6658
92b84437 6659 if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
1da177e4 6660 /* The card is being reset, no point doing anything */
22747d6b 6661 goto out_unlock;
1da177e4
LT		 6662 }
6663
6664 subid = nic->pdev->subsystem_device;
a371a07d
K		 6665 if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6666 /*
6667 * Allow a small delay for the NICs self initiated
6668 * cleanup to complete.
6669 */
6670 msleep(100);
6671 }
1da177e4
LT		 6672
6673 val64 = readq(&bar0->adapter_status);
19a60522
SS		 6674 if (LINK_IS_UP(val64)) {
6675 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6676 if (verify_xena_quiescence(nic)) {
6677 val64 = readq(&bar0->adapter_control);
6678 val64 |= ADAPTER_CNTL_EN;
1da177e4 6679 writeq(val64, &bar0->adapter_control);
19a60522
SS		 6680 if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6681 nic->device_type, subid)) {
6682 val64 = readq(&bar0->gpio_control);
6683 val64 |= GPIO_CTRL_GPIO_0;
6684 writeq(val64, &bar0->gpio_control);
6685 val64 = readq(&bar0->gpio_control);
6686 } else {
6687 val64 |= ADAPTER_LED_ON;
6688 writeq(val64, &bar0->adapter_control);
a371a07d 6689 }
1da177e4 6690 nic->device_enabled_once = TRUE;
19a60522
SS		 6691 } else {
6692 DBG_PRINT(ERR_DBG, "%s: Error: ", dev->name);
6693 DBG_PRINT(ERR_DBG, "device is not Quiescent\n");
6694 netif_stop_queue(dev);
1da177e4 6695 }
19a60522 6696 }
92c48799
SS		 6697 val64 = readq(&bar0->adapter_control);
6698 val64 |= ADAPTER_LED_ON;
6699 writeq(val64, &bar0->adapter_control);
6700 s2io_link(nic, LINK_UP);
19a60522
SS		 6701 } else {
6702 if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6703 subid)) {
6704 val64 = readq(&bar0->gpio_control);
6705 val64 &= ~GPIO_CTRL_GPIO_0;
6706 writeq(val64, &bar0->gpio_control);
6707 val64 = readq(&bar0->gpio_control);
1da177e4 6708 }
92c48799
SS		 6709 /* turn off LED */
6710 val64 = readq(&bar0->adapter_control);
6711 val64 = val64 &(~ADAPTER_LED_ON);
6712 writeq(val64, &bar0->adapter_control);
19a60522 6713 s2io_link(nic, LINK_DOWN);
1da177e4 6714 }
92b84437 6715 clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
22747d6b
FR		 6716
6717out_unlock:
d8d70caf 6718 rtnl_unlock();
1da177e4
LT		 6719}
6720
1ee6dd77
RB		 6721static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6722 struct buffAdd *ba,
6723 struct sk_buff **skb, u64 *temp0, u64 *temp1,
6724 u64 *temp2, int size)
5d3213cc
AR		 6725{
6726 struct net_device *dev = sp->dev;
491abf25 6727 struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
5d3213cc
AR		 6728
6729 if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6d517a27 6730 struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
5d3213cc
AR		 6731 /* allocate skb */
6732 if (*skb) {
6733 DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6734 /*
6735 * As Rx frame are not going to be processed,
6736 * using same mapped address for the Rxd
6737 * buffer pointer
6738 */
6d517a27 6739 rxdp1->Buffer0_ptr = *temp0;
5d3213cc
AR		 6740 } else {
6741 *skb = dev_alloc_skb(size);
6742 if (!(*skb)) {
0c61ed5f 6743 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
c53d4945
SH		 6744 DBG_PRINT(INFO_DBG, "memory to allocate ");
6745 DBG_PRINT(INFO_DBG, "1 buf mode SKBs\n");
6746 sp->mac_control.stats_info->sw_stat. \
6747 mem_alloc_fail_cnt++;
5d3213cc
AR		 6748 return -ENOMEM ;
6749 }
8a4bdbaa 6750 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6751 += (*skb)->truesize;
5d3213cc
AR		 6752 /* storing the mapped addr in a temp variable
6753 * such it will be used for next rxd whose
6754 * Host Control is NULL
6755 */
6d517a27 6756 rxdp1->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6757 pci_map_single( sp->pdev, (*skb)->data,
6758 size - NET_IP_ALIGN,
6759 PCI_DMA_FROMDEVICE);
491abf25
VP		 6760 if( (rxdp1->Buffer0_ptr == 0) ||
6761 (rxdp1->Buffer0_ptr == DMA_ERROR_CODE)) {
6762 goto memalloc_failed;
6763 }
5d3213cc
AR		 6764 rxdp->Host_Control = (unsigned long) (*skb);
6765 }
6766 } else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6d517a27 6767 struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
5d3213cc
AR		 6768 /* Two buffer Mode */
6769 if (*skb) {
6d517a27
VP		 6770 rxdp3->Buffer2_ptr = *temp2;
6771 rxdp3->Buffer0_ptr = *temp0;
6772 rxdp3->Buffer1_ptr = *temp1;
5d3213cc
AR		 6773 } else {
6774 *skb = dev_alloc_skb(size);
2ceaac75 6775 if (!(*skb)) {
c53d4945
SH		 6776 DBG_PRINT(INFO_DBG, "%s: Out of ", dev->name);
6777 DBG_PRINT(INFO_DBG, "memory to allocate ");
6778 DBG_PRINT(INFO_DBG, "2 buf mode SKBs\n");
6779 sp->mac_control.stats_info->sw_stat. \
6780 mem_alloc_fail_cnt++;
2ceaac75
DR		 6781 return -ENOMEM;
6782 }
8a4bdbaa 6783 sp->mac_control.stats_info->sw_stat.mem_allocated
491976b2 6784 += (*skb)->truesize;
6d517a27 6785 rxdp3->Buffer2_ptr = *temp2 =
5d3213cc
AR		 6786 pci_map_single(sp->pdev, (*skb)->data,
6787 dev->mtu + 4,
6788 PCI_DMA_FROMDEVICE);
491abf25
VP		 6789 if( (rxdp3->Buffer2_ptr == 0) ||
6790 (rxdp3->Buffer2_ptr == DMA_ERROR_CODE)) {
6791 goto memalloc_failed;
6792 }
6d517a27 6793 rxdp3->Buffer0_ptr = *temp0 =
5d3213cc
AR		 6794 pci_map_single( sp->pdev, ba->ba_0, BUF0_LEN,
6795 PCI_DMA_FROMDEVICE);
491abf25
VP		 6796 if( (rxdp3->Buffer0_ptr == 0) ||
6797 (rxdp3->Buffer0_ptr == DMA_ERROR_CODE)) {
6798 pci_unmap_single (sp->pdev,
3e847423 6799 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6800 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6801 goto memalloc_failed;
6802 }
5d3213cc
AR		 6803 rxdp->Host_Control = (unsigned long) (*skb);
6804
6805 /* Buffer-1 will be dummy buffer not used */
6d517a27 6806 rxdp3->Buffer1_ptr = *temp1 =
5d3213cc 6807 pci_map_single(sp->pdev, ba->ba_1, BUF1_LEN,
5d3213cc 6808 PCI_DMA_FROMDEVICE);
491abf25
VP		 6809 if( (rxdp3->Buffer1_ptr == 0) ||
6810 (rxdp3->Buffer1_ptr == DMA_ERROR_CODE)) {
6811 pci_unmap_single (sp->pdev,
3e847423
AV		 6812 (dma_addr_t)rxdp3->Buffer0_ptr,
6813 BUF0_LEN, PCI_DMA_FROMDEVICE);
6814 pci_unmap_single (sp->pdev,
6815 (dma_addr_t)rxdp3->Buffer2_ptr,
491abf25
VP		 6816 dev->mtu + 4, PCI_DMA_FROMDEVICE);
6817 goto memalloc_failed;
6818 }
5d3213cc
AR		 6819 }
6820 }
6821 return 0;
491abf25
VP		 6822 memalloc_failed:
6823 stats->pci_map_fail_cnt++;
6824 stats->mem_freed += (*skb)->truesize;
6825 dev_kfree_skb(*skb);
6826 return -ENOMEM;
5d3213cc 6827}
491abf25 6828
1ee6dd77
RB		 6829static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6830 int size)
5d3213cc
AR		 6831{
6832 struct net_device *dev = sp->dev;
6833 if (sp->rxd_mode == RXD_MODE_1) {
6834 rxdp->Control_2 = SET_BUFFER0_SIZE_1( size - NET_IP_ALIGN);
6835 } else if (sp->rxd_mode == RXD_MODE_3B) {
6836 rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6837 rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6838 rxdp->Control_2 |= SET_BUFFER2_SIZE_3( dev->mtu + 4);
5d3213cc
AR		 6839 }
6840}
6841
1ee6dd77 6842static int rxd_owner_bit_reset(struct s2io_nic *sp)
5d3213cc
AR		 6843{
6844 int i, j, k, blk_cnt = 0, size;
1ee6dd77 6845 struct mac_info * mac_control = &sp->mac_control;
5d3213cc
AR		 6846 struct config_param *config = &sp->config;
6847 struct net_device *dev = sp->dev;
1ee6dd77 6848 struct RxD_t *rxdp = NULL;
5d3213cc 6849 struct sk_buff *skb = NULL;
1ee6dd77 6850 struct buffAdd *ba = NULL;
5d3213cc
AR		 6851 u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6852
6853 /* Calculate the size based on ring mode */
6854 size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6855 HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6856 if (sp->rxd_mode == RXD_MODE_1)
6857 size += NET_IP_ALIGN;
6858 else if (sp->rxd_mode == RXD_MODE_3B)
6859 size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
5d3213cc
AR		 6860
6861 for (i = 0; i < config->rx_ring_num; i++) {
6862 blk_cnt = config->rx_cfg[i].num_rxd /
6863 (rxd_count[sp->rxd_mode] +1);
6864
6865 for (j = 0; j < blk_cnt; j++) {
6866 for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6867 rxdp = mac_control->rings[i].
6868 rx_blocks[j].rxds[k].virt_addr;
6d517a27 6869 if(sp->rxd_mode == RXD_MODE_3B)
5d3213cc 6870 ba = &mac_control->rings[i].ba[j][k];
ac1f90d6 6871 if (set_rxd_buffer_pointer(sp, rxdp, ba,
5d3213cc
AR		 6872 &skb,(u64 *)&temp0_64,
6873 (u64 *)&temp1_64,
ac1f90d6
SS		 6874 (u64 *)&temp2_64,
6875 size) == ENOMEM) {
6876 return 0;
6877 }
5d3213cc
AR		 6878
6879 set_rxd_buffer_size(sp, rxdp, size);
6880 wmb();
6881 /* flip the Ownership bit to Hardware */
6882 rxdp->Control_1 |= RXD_OWN_XENA;
6883 }
6884 }
6885 }
6886 return 0;
6887
6888}
6889
1ee6dd77 6890static int s2io_add_isr(struct s2io_nic * sp)
1da177e4 6891{
e6a8fee2 6892 int ret = 0;
c92ca04b 6893 struct net_device *dev = sp->dev;
e6a8fee2 6894 int err = 0;
1da177e4 6895
eaae7f72 6896 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 6897 ret = s2io_enable_msi_x(sp);
6898 if (ret) {
6899 DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
eaae7f72 6900 sp->config.intr_type = INTA;
20346722 6901 }
1da177e4 6902
1ee6dd77 6903 /* Store the values of the MSIX table in the struct s2io_nic structure */
e6a8fee2 6904 store_xmsi_data(sp);
c92ca04b 6905
e6a8fee2 6906 /* After proper initialization of H/W, register ISR */
eaae7f72 6907 if (sp->config.intr_type == MSI_X) {
fb6a825b 6908 int i, msix_tx_cnt=0,msix_rx_cnt=0;
c92ca04b 6909
e6a8fee2
AR		 6910 for (i=1; (sp->s2io_entries[i].in_use == MSIX_FLG); i++) {
6911 if (sp->s2io_entries[i].type == MSIX_FIFO_TYPE) {
6912 sprintf(sp->desc[i], "%s:MSI-X-%d-TX",
6913 dev->name, i);
6914 err = request_irq(sp->entries[i].vector,
6915 s2io_msix_fifo_handle, 0, sp->desc[i],
6916 sp->s2io_entries[i].arg);
fb6a825b
SS		 6917 /* If either data or addr is zero print it */
6918 if(!(sp->msix_info[i].addr &&
6919 sp->msix_info[i].data)) {
2450022a 6920 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx "
fb6a825b
SS		 6921 "Data:0x%lx\n",sp->desc[i],
6922 (unsigned long long)
6923 sp->msix_info[i].addr,
6924 (unsigned long)
6925 ntohl(sp->msix_info[i].data));
6926 } else {
6927 msix_tx_cnt++;
6928 }
e6a8fee2
AR		 6929 } else {
6930 sprintf(sp->desc[i], "%s:MSI-X-%d-RX",
6931 dev->name, i);
6932 err = request_irq(sp->entries[i].vector,
6933 s2io_msix_ring_handle, 0, sp->desc[i],
6934 sp->s2io_entries[i].arg);
fb6a825b
SS		 6935 /* If either data or addr is zero print it */
6936 if(!(sp->msix_info[i].addr &&
6937 sp->msix_info[i].data)) {
2450022a 6938 DBG_PRINT(ERR_DBG, "%s @ Addr:0x%llx "
fb6a825b
SS		 6939 "Data:0x%lx\n",sp->desc[i],
6940 (unsigned long long)
6941 sp->msix_info[i].addr,
6942 (unsigned long)
6943 ntohl(sp->msix_info[i].data));
6944 } else {
6945 msix_rx_cnt++;
6946 }
c92ca04b 6947 }
e6a8fee2 6948 if (err) {
18b2b7bd 6949 remove_msix_isr(sp);
e6a8fee2
AR		 6950 DBG_PRINT(ERR_DBG,"%s:MSI-X-%d registration "
6951 "failed\n", dev->name, i);
18b2b7bd
SH		 6952 DBG_PRINT(ERR_DBG, "%s: defaulting to INTA\n",
6953 dev->name);
6954 sp->config.intr_type = INTA;
6955 break;
e6a8fee2
AR		 6956 }
6957 sp->s2io_entries[i].in_use = MSIX_REGISTERED_SUCCESS;
6958 }
18b2b7bd
SH		 6959 if (!err) {
6960 printk(KERN_INFO "MSI-X-TX %d entries enabled\n",
6961 msix_tx_cnt);
6962 printk(KERN_INFO "MSI-X-RX %d entries enabled\n",
6963 msix_rx_cnt);
6964 }
e6a8fee2 6965 }
eaae7f72 6966 if (sp->config.intr_type == INTA) {
e6a8fee2
AR		 6967 err = request_irq((int) sp->pdev->irq, s2io_isr, IRQF_SHARED,
6968 sp->name, dev);
6969 if (err) {
6970 DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6971 dev->name);
6972 return -1;
6973 }
6974 }
6975 return 0;
6976}
1ee6dd77 6977static void s2io_rem_isr(struct s2io_nic * sp)
e6a8fee2 6978{
18b2b7bd
SH		 6979 if (sp->config.intr_type == MSI_X)
6980 remove_msix_isr(sp);
6981 else
6982 remove_inta_isr(sp);
e6a8fee2
AR		 6983}
6984
d796fdb7 6985static void do_s2io_card_down(struct s2io_nic * sp, int do_io)
e6a8fee2
AR		 6986{
6987 int cnt = 0;
1ee6dd77 6988 struct XENA_dev_config __iomem *bar0 = sp->bar0;
e6a8fee2
AR		 6989 unsigned long flags;
6990 register u64 val64 = 0;
5f490c96
SH		 6991 struct config_param *config;
6992 config = &sp->config;
e6a8fee2 6993
9f74ffde
SH		 6994 if (!is_s2io_card_up(sp))
6995 return;
6996
e6a8fee2
AR		 6997 del_timer_sync(&sp->alarm_timer);
6998 /* If s2io_set_link task is executing, wait till it completes. */
92b84437 6999 while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state))) {
e6a8fee2
AR		 7000 msleep(50);
7001 }
92b84437 7002 clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
e6a8fee2 7003
5f490c96
SH		 7004 /* Disable napi */
7005 if (config->napi)
7006 napi_disable(&sp->napi);
7007
e6a8fee2 7008 /* disable Tx and Rx traffic on the NIC */
d796fdb7
LV		 7009 if (do_io)
7010 stop_nic(sp);
e6a8fee2
AR		 7011
7012 s2io_rem_isr(sp);
1da177e4
LT		 7013
7014 /* Kill tasklet. */
7015 tasklet_kill(&sp->task);
7016
7017 /* Check if the device is Quiescent and then Reset the NIC */
d796fdb7 7018 while(do_io) {
5d3213cc
AR		 7019 /* As per the HW requirement we need to replenish the
7020 * receive buffer to avoid the ring bump. Since there is
7021 * no intention of processing the Rx frame at this pointwe are
7022 * just settting the ownership bit of rxd in Each Rx
7023 * ring to HW and set the appropriate buffer size
7024 * based on the ring mode
7025 */
7026 rxd_owner_bit_reset(sp);
7027
1da177e4 7028 val64 = readq(&bar0->adapter_status);
19a60522
SS		 7029 if (verify_xena_quiescence(sp)) {
7030 if(verify_pcc_quiescent(sp, sp->device_enabled_once))
1da177e4
LT		 7031 break;
7032 }
7033
7034 msleep(50);
7035 cnt++;
7036 if (cnt == 10) {
7037 DBG_PRINT(ERR_DBG,
7038 "s2io_close:Device not Quiescent ");
7039 DBG_PRINT(ERR_DBG, "adaper status reads 0x%llx\n",
7040 (unsigned long long) val64);
7041 break;
7042 }
d796fdb7
LV		 7043 }
7044 if (do_io)
7045 s2io_reset(sp);
1da177e4 7046
7ba013ac 7047 /* Free all Tx buffers */
1da177e4 7048 free_tx_buffers(sp);
7ba013ac
K		 7049
7050 /* Free all Rx buffers */
7051 spin_lock_irqsave(&sp->rx_lock, flags);
1da177e4 7052 free_rx_buffers(sp);
7ba013ac 7053 spin_unlock_irqrestore(&sp->rx_lock, flags);
1da177e4 7054
92b84437 7055 clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
1da177e4
LT		 7056}
7057
d796fdb7
LV		 7058static void s2io_card_down(struct s2io_nic * sp)
7059{
7060 do_s2io_card_down(sp, 1);
7061}
7062
1ee6dd77 7063static int s2io_card_up(struct s2io_nic * sp)
1da177e4 7064{
cc6e7c44 7065 int i, ret = 0;
1ee6dd77 7066 struct mac_info *mac_control;
1da177e4
LT		 7067 struct config_param *config;
7068 struct net_device *dev = (struct net_device *) sp->dev;
e6a8fee2 7069 u16 interruptible;
1da177e4
LT		 7070
7071 /* Initialize the H/W I/O registers */
9f74ffde
SH		 7072 ret = init_nic(sp);
7073 if (ret != 0) {
1da177e4
LT		 7074 DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7075 dev->name);
9f74ffde
SH		 7076 if (ret != -EIO)
7077 s2io_reset(sp);
7078 return ret;
1da177e4
LT		 7079 }
7080
20346722
K		 7081 /*
7082 * Initializing the Rx buffers. For now we are considering only 1
1da177e4
LT		 7083 * Rx ring and initializing buffers into 30 Rx blocks
7084 */
7085 mac_control = &sp->mac_control;
7086 config = &sp->config;
7087
7088 for (i = 0; i < config->rx_ring_num; i++) {
7089 if ((ret = fill_rx_buffers(sp, i))) {
7090 DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7091 dev->name);
7092 s2io_reset(sp);
7093 free_rx_buffers(sp);
7094 return -ENOMEM;
7095 }
7096 DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7097 atomic_read(&sp->rx_bufs_left[i]));
7098 }
5f490c96
SH		 7099
7100 /* Initialise napi */
7101 if (config->napi)
7102 napi_enable(&sp->napi);
7103
19a60522
SS		 7104 /* Maintain the state prior to the open */
7105 if (sp->promisc_flg)
7106 sp->promisc_flg = 0;
7107 if (sp->m_cast_flg) {
7108 sp->m_cast_flg = 0;
7109 sp->all_multi_pos= 0;
7110 }
1da177e4
LT		 7111
7112 /* Setting its receive mode */
7113 s2io_set_multicast(dev);
7114
7d3d0439 7115 if (sp->lro) {
b41477f3 7116 /* Initialize max aggregatable pkts per session based on MTU */
7d3d0439
RA		 7117 sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7118 /* Check if we can use(if specified) user provided value */
7119 if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7120 sp->lro_max_aggr_per_sess = lro_max_pkts;
7121 }
7122
1da177e4
LT		 7123 /* Enable Rx Traffic and interrupts on the NIC */
7124 if (start_nic(sp)) {
7125 DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
1da177e4 7126 s2io_reset(sp);
e6a8fee2
AR		 7127 free_rx_buffers(sp);
7128 return -ENODEV;
7129 }
7130
7131 /* Add interrupt service routine */
7132 if (s2io_add_isr(sp) != 0) {
eaae7f72 7133 if (sp->config.intr_type == MSI_X)
e6a8fee2
AR		 7134 s2io_rem_isr(sp);
7135 s2io_reset(sp);
1da177e4
LT		 7136 free_rx_buffers(sp);
7137 return -ENODEV;
7138 }
7139
25fff88e
K		 7140 S2IO_TIMER_CONF(sp->alarm_timer, s2io_alarm_handle, sp, (HZ/2));
7141
e6a8fee2
AR		 7142 /* Enable tasklet for the device */
7143 tasklet_init(&sp->task, s2io_tasklet, (unsigned long) dev);
7144
7145 /* Enable select interrupts */
9caab458 7146 en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
eaae7f72 7147 if (sp->config.intr_type != INTA)
e6a8fee2
AR		 7148 en_dis_able_nic_intrs(sp, ENA_ALL_INTRS, DISABLE_INTRS);
7149 else {
7150 interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
9caab458 7151 interruptible |= TX_PIC_INTR;
e6a8fee2
AR		 7152 en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7153 }
7154
92b84437 7155 set_bit(__S2IO_STATE_CARD_UP, &sp->state);
1da177e4
LT		 7156 return 0;
7157}
7158
20346722 7159/**
1da177e4
LT		 7160 * s2io_restart_nic - Resets the NIC.
7161 * @data : long pointer to the device private structure
7162 * Description:
7163 * This function is scheduled to be run by the s2io_tx_watchdog
20346722 7164 * function after 0.5 secs to reset the NIC. The idea is to reduce
1da177e4
LT		 7165 * the run time of the watch dog routine which is run holding a
7166 * spin lock.
7167 */
7168
c4028958 7169static void s2io_restart_nic(struct work_struct *work)
1da177e4 7170{
1ee6dd77 7171 struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
c4028958 7172 struct net_device *dev = sp->dev;
1da177e4 7173
22747d6b
FR		 7174 rtnl_lock();
7175
7176 if (!netif_running(dev))
7177 goto out_unlock;
7178
e6a8fee2 7179 s2io_card_down(sp);
1da177e4
LT		 7180 if (s2io_card_up(sp)) {
7181 DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
7182 dev->name);
7183 }
7184 netif_wake_queue(dev);
7185 DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n",
7186 dev->name);
22747d6b
FR		 7187out_unlock:
7188 rtnl_unlock();
1da177e4
LT		 7189}
7190
20346722
K		 7191/**
7192 * s2io_tx_watchdog - Watchdog for transmit side.
1da177e4
LT		 7193 * @dev : Pointer to net device structure
7194 * Description:
7195 * This function is triggered if the Tx Queue is stopped
7196 * for a pre-defined amount of time when the Interface is still up.
7197 * If the Interface is jammed in such a situation, the hardware is
7198 * reset (by s2io_close) and restarted again (by s2io_open) to
7199 * overcome any problem that might have been caused in the hardware.
7200 * Return value:
7201 * void
7202 */
7203
7204static void s2io_tx_watchdog(struct net_device *dev)
7205{
1ee6dd77 7206 struct s2io_nic *sp = dev->priv;
1da177e4
LT		 7207
7208 if (netif_carrier_ok(dev)) {
c53d4945 7209 sp->mac_control.stats_info->sw_stat.watchdog_timer_cnt++;
1da177e4 7210 schedule_work(&sp->rst_timer_task);
bd1034f0 7211 sp->mac_control.stats_info->sw_stat.soft_reset_cnt++;
1da177e4
LT		 7212 }
7213}
7214
7215/**
7216 * rx_osm_handler - To perform some OS related operations on SKB.
7217 * @sp: private member of the device structure,pointer to s2io_nic structure.
7218 * @skb : the socket buffer pointer.
7219 * @len : length of the packet
7220 * @cksum : FCS checksum of the frame.
7221 * @ring_no : the ring from which this RxD was extracted.
20346722 7222 * Description:
b41477f3 7223 * This function is called by the Rx interrupt serivce routine to perform
1da177e4
LT		 7224 * some OS related operations on the SKB before passing it to the upper
7225 * layers. It mainly checks if the checksum is OK, if so adds it to the
7226 * SKBs cksum variable, increments the Rx packet count and passes the SKB
7227 * to the upper layer. If the checksum is wrong, it increments the Rx
7228 * packet error count, frees the SKB and returns error.
7229 * Return value:
7230 * SUCCESS on success and -1 on failure.
7231 */
1ee6dd77 7232static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
1da177e4 7233{
1ee6dd77 7234 struct s2io_nic *sp = ring_data->nic;
1da177e4 7235 struct net_device *dev = (struct net_device *) sp->dev;
20346722
K		 7236 struct sk_buff *skb = (struct sk_buff *)
7237 ((unsigned long) rxdp->Host_Control);
7238 int ring_no = ring_data->ring_no;
1da177e4 7239 u16 l3_csum, l4_csum;
863c11a9 7240 unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
1ee6dd77 7241 struct lro *lro;
f9046eb3 7242 u8 err_mask;
da6971d8 7243
20346722 7244 skb->dev = dev;
c92ca04b 7245
863c11a9 7246 if (err) {
bd1034f0
AR		 7247 /* Check for parity error */
7248 if (err & 0x1) {
7249 sp->mac_control.stats_info->sw_stat.parity_err_cnt++;
7250 }
f9046eb3
OH		 7251 err_mask = err >> 48;
7252 switch(err_mask) {
491976b2
SH		 7253 case 1:
7254 sp->mac_control.stats_info->sw_stat.
7255 rx_parity_err_cnt++;
7256 break;
7257
7258 case 2:
7259 sp->mac_control.stats_info->sw_stat.
7260 rx_abort_cnt++;
7261 break;
7262
7263 case 3:
7264 sp->mac_control.stats_info->sw_stat.
7265 rx_parity_abort_cnt++;
7266 break;
7267
7268 case 4:
7269 sp->mac_control.stats_info->sw_stat.
7270 rx_rda_fail_cnt++;
7271 break;
7272
7273 case 5:
7274 sp->mac_control.stats_info->sw_stat.
7275 rx_unkn_prot_cnt++;
7276 break;
7277
7278 case 6:
7279 sp->mac_control.stats_info->sw_stat.
7280 rx_fcs_err_cnt++;
7281 break;
bd1034f0 7282
491976b2
SH		 7283 case 7:
7284 sp->mac_control.stats_info->sw_stat.
7285 rx_buf_size_err_cnt++;
7286 break;
7287
7288 case 8:
7289 sp->mac_control.stats_info->sw_stat.
7290 rx_rxd_corrupt_cnt++;
7291 break;
7292
7293 case 15:
7294 sp->mac_control.stats_info->sw_stat.
7295 rx_unkn_err_cnt++;
7296 break;
7297 }
863c11a9
AR		 7298 /*
7299 * Drop the packet if bad transfer code. Exception being
7300 * 0x5, which could be due to unsupported IPv6 extension header.
7301 * In this case, we let stack handle the packet.
7302 * Note that in this case, since checksum will be incorrect,
7303 * stack will validate the same.
7304 */
f9046eb3
OH		 7305 if (err_mask != 0x5) {
7306 DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7307 dev->name, err_mask);
863c11a9 7308 sp->stats.rx_crc_errors++;
8a4bdbaa 7309 sp->mac_control.stats_info->sw_stat.mem_freed
491976b2 7310 += skb->truesize;
863c11a9
AR		 7311 dev_kfree_skb(skb);
7312 atomic_dec(&sp->rx_bufs_left[ring_no]);
7313 rxdp->Host_Control = 0;
7314 return 0;
7315 }
20346722 7316 }
1da177e4 7317
20346722 7318 /* Updating statistics */
573608e4 7319 sp->stats.rx_packets++;
20346722 7320 rxdp->Host_Control = 0;
da6971d8
AR		 7321 if (sp->rxd_mode == RXD_MODE_1) {
7322 int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
20346722 7323
da6971d8
AR		 7324 sp->stats.rx_bytes += len;
7325 skb_put(skb, len);
7326
6d517a27 7327 } else if (sp->rxd_mode == RXD_MODE_3B) {
da6971d8
AR		 7328 int get_block = ring_data->rx_curr_get_info.block_index;
7329 int get_off = ring_data->rx_curr_get_info.offset;
7330 int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7331 int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7332 unsigned char *buff = skb_push(skb, buf0_len);
7333
1ee6dd77 7334 struct buffAdd *ba = &ring_data->ba[get_block][get_off];
da6971d8
AR		 7335 sp->stats.rx_bytes += buf0_len + buf2_len;
7336 memcpy(buff, ba->ba_0, buf0_len);
6d517a27 7337 skb_put(skb, buf2_len);
da6971d8 7338 }
20346722 7339
7d3d0439
RA		 7340 if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) && ((!sp->lro) ||
7341 (sp->lro && (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG)))) &&
20346722
K		 7342 (sp->rx_csum)) {
7343 l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
1da177e4
LT		 7344 l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7345 if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
20346722 7346 /*
1da177e4
LT		 7347 * NIC verifies if the Checksum of the received
7348 * frame is Ok or not and accordingly returns
7349 * a flag in the RxD.
7350 */
7351 skb->ip_summed = CHECKSUM_UNNECESSARY;
7d3d0439
RA		 7352 if (sp->lro) {
7353 u32 tcp_len;
7354 u8 *tcp;
7355 int ret = 0;
7356
7357 ret = s2io_club_tcp_session(skb->data, &tcp,
43b7c451
SH		 7358 &tcp_len, &lro,
7359 rxdp, sp);
7d3d0439
RA		 7360 switch (ret) {
7361 case 3: /* Begin anew */
7362 lro->parent = skb;
7363 goto aggregate;
7364 case 1: /* Aggregate */
7365 {
7366 lro_append_pkt(sp, lro,
7367 skb, tcp_len);
7368 goto aggregate;
7369 }
7370 case 4: /* Flush session */
7371 {
7372 lro_append_pkt(sp, lro,
7373 skb, tcp_len);
7374 queue_rx_frame(lro->parent);
7375 clear_lro_session(lro);
7376 sp->mac_control.stats_info->
7377 sw_stat.flush_max_pkts++;
7378 goto aggregate;
7379 }
7380 case 2: /* Flush both */
7381 lro->parent->data_len =
7382 lro->frags_len;
7383 sp->mac_control.stats_info->
7384 sw_stat.sending_both++;
7385 queue_rx_frame(lro->parent);
7386 clear_lro_session(lro);
7387 goto send_up;
7388 case 0: /* sessions exceeded */
c92ca04b
AR		 7389 case -1: /* non-TCP or not
7390 * L2 aggregatable
7391 */
7d3d0439
RA		 7392 case 5: /*
7393 * First pkt in session not
7394 * L3/L4 aggregatable
7395 */
7396 break;
7397 default:
7398 DBG_PRINT(ERR_DBG,
7399 "%s: Samadhana!!\n",
7400 __FUNCTION__);
7401 BUG();
7402 }
7403 }
1da177e4 7404 } else {
20346722
K		 7405 /*
7406 * Packet with erroneous checksum, let the
1da177e4
LT		 7407 * upper layers deal with it.
7408 */
7409 skb->ip_summed = CHECKSUM_NONE;
7410 }
7411 } else {
7412 skb->ip_summed = CHECKSUM_NONE;
7413 }
491976b2 7414 sp->mac_control.stats_info->sw_stat.mem_freed += skb->truesize;
7d3d0439
RA		 7415 if (!sp->lro) {
7416 skb->protocol = eth_type_trans(skb, dev);
926930b2
SS		 7417 if ((sp->vlgrp && RXD_GET_VLAN_TAG(rxdp->Control_2) &&
7418 vlan_strip_flag)) {
7d3d0439 7419 /* Queueing the vlan frame to the upper layer */
db874e65
SS		 7420 if (napi)
7421 vlan_hwaccel_receive_skb(skb, sp->vlgrp,
7422 RXD_GET_VLAN_TAG(rxdp->Control_2));
7423 else
7424 vlan_hwaccel_rx(skb, sp->vlgrp,
7425 RXD_GET_VLAN_TAG(rxdp->Control_2));
7d3d0439 7426 } else {
db874e65
SS		 7427 if (napi)
7428 netif_receive_skb(skb);
7429 else
7430 netif_rx(skb);
7d3d0439 7431 }
7d3d0439
RA		 7432 } else {
7433send_up:
7434 queue_rx_frame(skb);
6aa20a22 7435 }
1da177e4 7436 dev->last_rx = jiffies;
7d3d0439 7437aggregate:
1da177e4 7438 atomic_dec(&sp->rx_bufs_left[ring_no]);
1da177e4
LT		 7439 return SUCCESS;
7440}
7441
7442/**
7443 * s2io_link - stops/starts the Tx queue.
7444 * @sp : private member of the device structure, which is a pointer to the
7445 * s2io_nic structure.
7446 * @link : inidicates whether link is UP/DOWN.
7447 * Description:
7448 * This function stops/starts the Tx queue depending on whether the link
20346722
K		 7449 * status of the NIC is is down or up. This is called by the Alarm
7450 * interrupt handler whenever a link change interrupt comes up.
1da177e4
LT		 7451 * Return value:
7452 * void.
7453 */
7454
1ee6dd77 7455static void s2io_link(struct s2io_nic * sp, int link)
1da177e4
LT		 7456{
7457 struct net_device *dev = (struct net_device *) sp->dev;
7458
7459 if (link != sp->last_link_state) {
b7c5678f 7460 init_tti(sp, link);
1da177e4
LT		 7461 if (link == LINK_DOWN) {
7462 DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7463 netif_carrier_off(dev);
491976b2 7464 if(sp->mac_control.stats_info->sw_stat.link_up_cnt)
8a4bdbaa 7465 sp->mac_control.stats_info->sw_stat.link_up_time =
491976b2
SH		 7466 jiffies - sp->start_time;
7467 sp->mac_control.stats_info->sw_stat.link_down_cnt++;
1da177e4
LT		 7468 } else {
7469 DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
491976b2 7470 if (sp->mac_control.stats_info->sw_stat.link_down_cnt)
8a4bdbaa 7471 sp->mac_control.stats_info->sw_stat.link_down_time =
491976b2
SH		 7472 jiffies - sp->start_time;
7473 sp->mac_control.stats_info->sw_stat.link_up_cnt++;
1da177e4
LT		 7474 netif_carrier_on(dev);
7475 }
7476 }
7477 sp->last_link_state = link;
491976b2 7478 sp->start_time = jiffies;
1da177e4
LT		 7479}
7480
20346722
K		 7481/**
7482 * s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7483 * @sp : private member of the device structure, which is a pointer to the
1da177e4
LT		 7484 * s2io_nic structure.
7485 * Description:
7486 * This function initializes a few of the PCI and PCI-X configuration registers
7487 * with recommended values.
7488 * Return value:
7489 * void
7490 */
7491
1ee6dd77 7492static void s2io_init_pci(struct s2io_nic * sp)
1da177e4 7493{
20346722 7494 u16 pci_cmd = 0, pcix_cmd = 0;
1da177e4
LT		 7495
7496 /* Enable Data Parity Error Recovery in PCI-X command register. */
7497 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7498 &(pcix_cmd));
1da177e4 7499 pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7500 (pcix_cmd | 1));
1da177e4 7501 pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
20346722 7502 &(pcix_cmd));
1da177e4
LT		 7503
7504 /* Set the PErr Response bit in PCI command register. */
7505 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7506 pci_write_config_word(sp->pdev, PCI_COMMAND,
7507 (pci_cmd | PCI_COMMAND_PARITY));
7508 pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
1da177e4
LT		 7509}
7510
9dc737a7
AR		 7511static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type)
7512{
2fda096d
SR		 7513 if ((tx_fifo_num > MAX_TX_FIFOS) ||
7514 (tx_fifo_num < FIFO_DEFAULT_NUM)) {
7515 DBG_PRINT(ERR_DBG, "s2io: Requested number of tx fifos "
7516 "(%d) not supported\n", tx_fifo_num);
7517 tx_fifo_num =
7518 ((tx_fifo_num > MAX_TX_FIFOS)? MAX_TX_FIFOS :
7519 ((tx_fifo_num < FIFO_DEFAULT_NUM) ? FIFO_DEFAULT_NUM :
7520 tx_fifo_num));
7521 DBG_PRINT(ERR_DBG, "s2io: Default to %d ", tx_fifo_num);
7522 DBG_PRINT(ERR_DBG, "tx fifos\n");
9dc737a7 7523 }
2fda096d 7524
9dc737a7
AR		 7525 if ( rx_ring_num > 8) {
7526 DBG_PRINT(ERR_DBG, "s2io: Requested number of Rx rings not "
7527 "supported\n");
7528 DBG_PRINT(ERR_DBG, "s2io: Default to 8 Rx rings\n");
7529 rx_ring_num = 8;
7530 }
db874e65
SS		 7531 if (*dev_intr_type != INTA)
7532 napi = 0;
7533
eccb8628 7534 if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
9dc737a7
AR		 7535 DBG_PRINT(ERR_DBG, "s2io: Wrong intr_type requested. "
7536 "Defaulting to INTA\n");
7537 *dev_intr_type = INTA;
7538 }
596c5c97 7539
9dc737a7
AR		 7540 if ((*dev_intr_type == MSI_X) &&
7541 ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7542 (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
6aa20a22 7543 DBG_PRINT(ERR_DBG, "s2io: Xframe I does not support MSI_X. "
9dc737a7
AR		 7544 "Defaulting to INTA\n");
7545 *dev_intr_type = INTA;
7546 }
fb6a825b 7547
6d517a27 7548 if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
9dc737a7 7549 DBG_PRINT(ERR_DBG, "s2io: Requested ring mode not supported\n");
6d517a27
VP		 7550 DBG_PRINT(ERR_DBG, "s2io: Defaulting to 1-buffer mode\n");
7551 rx_ring_mode = 1;
9dc737a7
AR		 7552 }
7553 return SUCCESS;
7554}
7555
9fc93a41
SS		 7556/**
7557 * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS
7558 * or Traffic class respectively.
b7c5678f 7559 * @nic: device private variable
9fc93a41
SS		 7560 * Description: The function configures the receive steering to
7561 * desired receive ring.
7562 * Return Value: SUCCESS on success and
7563 * '-1' on failure (endian settings incorrect).
7564 */
7565static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7566{
7567 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7568 register u64 val64 = 0;
7569
7570 if (ds_codepoint > 63)
7571 return FAILURE;
7572
7573 val64 = RTS_DS_MEM_DATA(ring);
7574 writeq(val64, &bar0->rts_ds_mem_data);
7575
7576 val64 = RTS_DS_MEM_CTRL_WE |
7577 RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7578 RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7579
7580 writeq(val64, &bar0->rts_ds_mem_ctrl);
7581
7582 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7583 RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7584 S2IO_BIT_RESET);
7585}
7586
1da177e4 7587/**
20346722 7588 * s2io_init_nic - Initialization of the adapter .
1da177e4
LT		 7589 * @pdev : structure containing the PCI related information of the device.
7590 * @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7591 * Description:
7592 * The function initializes an adapter identified by the pci_dec structure.
20346722
K		 7593 * All OS related initialization including memory and device structure and
7594 * initlaization of the device private variable is done. Also the swapper
7595 * control register is initialized to enable read and write into the I/O
1da177e4
LT		 7596 * registers of the device.
7597 * Return value:
7598 * returns 0 on success and negative on failure.
7599 */
7600
7601static int __devinit
7602s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7603{
1ee6dd77 7604 struct s2io_nic *sp;
1da177e4 7605 struct net_device *dev;
1da177e4
LT		 7606 int i, j, ret;
7607 int dma_flag = FALSE;
7608 u32 mac_up, mac_down;
7609 u64 val64 = 0, tmp64 = 0;
1ee6dd77 7610 struct XENA_dev_config __iomem *bar0 = NULL;
1da177e4 7611 u16 subid;
1ee6dd77 7612 struct mac_info *mac_control;
1da177e4 7613 struct config_param *config;
541ae68f 7614 int mode;
cc6e7c44 7615 u8 dev_intr_type = intr_type;
0795af57 7616 DECLARE_MAC_BUF(mac);
1da177e4 7617
9dc737a7
AR		 7618 if ((ret = s2io_verify_parm(pdev, &dev_intr_type)))
7619 return ret;
1da177e4
LT		 7620
7621 if ((ret = pci_enable_device(pdev))) {
7622 DBG_PRINT(ERR_DBG,
7623 "s2io_init_nic: pci_enable_device failed\n");
7624 return ret;
7625 }
7626
1e7f0bd8 7627 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7628 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 64bit DMA\n");
7629 dma_flag = TRUE;
1da177e4 7630 if (pci_set_consistent_dma_mask
1e7f0bd8 7631 (pdev, DMA_64BIT_MASK)) {
1da177e4
LT		 7632 DBG_PRINT(ERR_DBG,
7633 "Unable to obtain 64bit DMA for \
7634 consistent allocations\n");
7635 pci_disable_device(pdev);
7636 return -ENOMEM;
7637 }
1e7f0bd8 7638 } else if (!pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
1da177e4
LT		 7639 DBG_PRINT(INIT_DBG, "s2io_init_nic: Using 32bit DMA\n");
7640 } else {
7641 pci_disable_device(pdev);
7642 return -ENOMEM;
7643 }
eccb8628
VP		 7644 if ((ret = pci_request_regions(pdev, s2io_driver_name))) {
7645 DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x \n", __FUNCTION__, ret);
7646 pci_disable_device(pdev);
7647 return -ENODEV;
1da177e4
LT		 7648 }
7649
1ee6dd77 7650 dev = alloc_etherdev(sizeof(struct s2io_nic));
1da177e4
LT		 7651 if (dev == NULL) {
7652 DBG_PRINT(ERR_DBG, "Device allocation failed\n");
7653 pci_disable_device(pdev);
7654 pci_release_regions(pdev);
7655 return -ENODEV;
7656 }
7657
7658 pci_set_master(pdev);
7659 pci_set_drvdata(pdev, dev);
1da177e4
LT		 7660 SET_NETDEV_DEV(dev, &pdev->dev);
7661
7662 /* Private member variable initialized to s2io NIC structure */
7663 sp = dev->priv;
1ee6dd77 7664 memset(sp, 0, sizeof(struct s2io_nic));
1da177e4
LT		 7665 sp->dev = dev;
7666 sp->pdev = pdev;
1da177e4 7667 sp->high_dma_flag = dma_flag;
1da177e4 7668 sp->device_enabled_once = FALSE;
da6971d8
AR		 7669 if (rx_ring_mode == 1)
7670 sp->rxd_mode = RXD_MODE_1;
7671 if (rx_ring_mode == 2)
7672 sp->rxd_mode = RXD_MODE_3B;
da6971d8 7673
eaae7f72 7674 sp->config.intr_type = dev_intr_type;
1da177e4 7675
541ae68f
K		 7676 if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7677 (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7678 sp->device_type = XFRAME_II_DEVICE;
7679 else
7680 sp->device_type = XFRAME_I_DEVICE;
7681
43b7c451 7682 sp->lro = lro_enable;
6aa20a22 7683
1da177e4
LT		 7684 /* Initialize some PCI/PCI-X fields of the NIC. */
7685 s2io_init_pci(sp);
7686
20346722 7687 /*
1da177e4 7688 * Setting the device configuration parameters.
20346722
K		 7689 * Most of these parameters can be specified by the user during
7690 * module insertion as they are module loadable parameters. If
7691 * these parameters are not not specified during load time, they
1da177e4
LT		 7692 * are initialized with default values.
7693 */
7694 mac_control = &sp->mac_control;
7695 config = &sp->config;
7696
596c5c97
SS		 7697 config->napi = napi;
7698
1da177e4 7699 /* Tx side parameters. */
1da177e4
LT		 7700 config->tx_fifo_num = tx_fifo_num;
7701 for (i = 0; i < MAX_TX_FIFOS; i++) {
7702 config->tx_cfg[i].fifo_len = tx_fifo_len[i];
7703 config->tx_cfg[i].fifo_priority = i;
7704 }
7705
20346722
K		 7706 /* mapping the QoS priority to the configured fifos */
7707 for (i = 0; i < MAX_TX_FIFOS; i++)
7708 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num][i];
7709
1da177e4
LT		 7710 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7711 for (i = 0; i < config->tx_fifo_num; i++) {
7712 config->tx_cfg[i].f_no_snoop =
7713 (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7714 if (config->tx_cfg[i].fifo_len < 65) {
7715 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7716 break;
7717 }
7718 }
fed5eccd
AR		 7719 /* + 2 because one Txd for skb->data and one Txd for UFO */
7720 config->max_txds = MAX_SKB_FRAGS + 2;
1da177e4
LT		 7721
7722 /* Rx side parameters. */
1da177e4
LT		 7723 config->rx_ring_num = rx_ring_num;
7724 for (i = 0; i < MAX_RX_RINGS; i++) {
7725 config->rx_cfg[i].num_rxd = rx_ring_sz[i] *
da6971d8 7726 (rxd_count[sp->rxd_mode] + 1);
1da177e4
LT		 7727 config->rx_cfg[i].ring_priority = i;
7728 }
7729
7730 for (i = 0; i < rx_ring_num; i++) {
7731 config->rx_cfg[i].ring_org = RING_ORG_BUFF1;
7732 config->rx_cfg[i].f_no_snoop =
7733 (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7734 }
7735
7736 /* Setting Mac Control parameters */
7737 mac_control->rmac_pause_time = rmac_pause_time;
7738 mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7739 mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7740
7741
7742 /* Initialize Ring buffer parameters. */
7743 for (i = 0; i < config->rx_ring_num; i++)
7744 atomic_set(&sp->rx_bufs_left[i], 0);
7745
7746 /* initialize the shared memory used by the NIC and the host */
7747 if (init_shared_mem(sp)) {
7748 DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n",
b41477f3 7749 dev->name);
1da177e4
LT		 7750 ret = -ENOMEM;
7751 goto mem_alloc_failed;
7752 }
7753
7754 sp->bar0 = ioremap(pci_resource_start(pdev, 0),
7755 pci_resource_len(pdev, 0));
7756 if (!sp->bar0) {
19a60522 7757 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
1da177e4
LT		 7758 dev->name);
7759 ret = -ENOMEM;
7760 goto bar0_remap_failed;
7761 }
7762
7763 sp->bar1 = ioremap(pci_resource_start(pdev, 2),
7764 pci_resource_len(pdev, 2));
7765 if (!sp->bar1) {
19a60522 7766 DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
1da177e4
LT		 7767 dev->name);
7768 ret = -ENOMEM;
7769 goto bar1_remap_failed;
7770 }
7771
7772 dev->irq = pdev->irq;
7773 dev->base_addr = (unsigned long) sp->bar0;
7774
7775 /* Initializing the BAR1 address as the start of the FIFO pointer. */
7776 for (j = 0; j < MAX_TX_FIFOS; j++) {
1ee6dd77 7777 mac_control->tx_FIFO_start[j] = (struct TxFIFO_element __iomem *)
1da177e4
LT		 7778 (sp->bar1 + (j * 0x00020000));
7779 }
7780
7781 /* Driver entry points */
7782 dev->open = &s2io_open;
7783 dev->stop = &s2io_close;
7784 dev->hard_start_xmit = &s2io_xmit;
7785 dev->get_stats = &s2io_get_stats;
7786 dev->set_multicast_list = &s2io_set_multicast;
7787 dev->do_ioctl = &s2io_ioctl;
2fd37688 7788 dev->set_mac_address = &s2io_set_mac_addr;
1da177e4
LT		 7789 dev->change_mtu = &s2io_change_mtu;
7790 SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
be3a6b02
K		 7791 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
7792 dev->vlan_rx_register = s2io_vlan_rx_register;
20346722 7793
1da177e4
LT		 7794 /*
7795 * will use eth_mac_addr() for dev->set_mac_address
7796 * mac address will be set every time dev->open() is called
7797 */
bea3348e 7798 netif_napi_add(dev, &sp->napi, s2io_poll, 32);
1da177e4 7799
612eff0e
BH		 7800#ifdef CONFIG_NET_POLL_CONTROLLER
7801 dev->poll_controller = s2io_netpoll;
7802#endif
7803
1da177e4
LT		 7804 dev->features |= NETIF_F_SG | NETIF_F_IP_CSUM;
7805 if (sp->high_dma_flag == TRUE)
7806 dev->features |= NETIF_F_HIGHDMA;
1da177e4 7807 dev->features |= NETIF_F_TSO;
f83ef8c0 7808 dev->features |= NETIF_F_TSO6;
db874e65 7809 if ((sp->device_type & XFRAME_II_DEVICE) && (ufo)) {
fed5eccd
AR		 7810 dev->features |= NETIF_F_UFO;
7811 dev->features |= NETIF_F_HW_CSUM;
7812 }
1da177e4
LT		 7813
7814 dev->tx_timeout = &s2io_tx_watchdog;
7815 dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
c4028958
DH		 7816 INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7817 INIT_WORK(&sp->set_link_task, s2io_set_link);
1da177e4 7818
e960fc5c 7819 pci_save_state(sp->pdev);
1da177e4
LT		 7820
7821 /* Setting swapper control on the NIC, for proper reset operation */
7822 if (s2io_set_swapper(sp)) {
7823 DBG_PRINT(ERR_DBG, "%s:swapper settings are wrong\n",
7824 dev->name);
7825 ret = -EAGAIN;
7826 goto set_swap_failed;
7827 }
7828
541ae68f
K		 7829 /* Verify if the Herc works on the slot its placed into */
7830 if (sp->device_type & XFRAME_II_DEVICE) {
7831 mode = s2io_verify_pci_mode(sp);
7832 if (mode < 0) {
7833 DBG_PRINT(ERR_DBG, "%s: ", __FUNCTION__);
7834 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
7835 ret = -EBADSLT;
7836 goto set_swap_failed;
7837 }
7838 }
7839
7840 /* Not needed for Herc */
7841 if (sp->device_type & XFRAME_I_DEVICE) {
7842 /*
7843 * Fix for all "FFs" MAC address problems observed on
7844 * Alpha platforms
7845 */
7846 fix_mac_address(sp);
7847 s2io_reset(sp);
7848 }
1da177e4
LT		 7849
7850 /*
1da177e4
LT		 7851 * MAC address initialization.
7852 * For now only one mac address will be read and used.
7853 */
7854 bar0 = sp->bar0;
7855 val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
faa4f796 7856 RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
1da177e4 7857 writeq(val64, &bar0->rmac_addr_cmd_mem);
c92ca04b 7858 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
9fc93a41 7859 RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING, S2IO_BIT_RESET);
1da177e4
LT		 7860 tmp64 = readq(&bar0->rmac_addr_data0_mem);
7861 mac_down = (u32) tmp64;
7862 mac_up = (u32) (tmp64 >> 32);
7863
1da177e4
LT		 7864 sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7865 sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7866 sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7867 sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7868 sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7869 sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7870
1da177e4
LT		 7871 /* Set the factory defined MAC address initially */
7872 dev->addr_len = ETH_ALEN;
7873 memcpy(dev->dev_addr, sp->def_mac_addr, ETH_ALEN);
2fd37688 7874 memcpy(dev->perm_addr, dev->dev_addr, ETH_ALEN);
1da177e4 7875
faa4f796
SH		 7876 /* initialize number of multicast & unicast MAC entries variables */
7877 if (sp->device_type == XFRAME_I_DEVICE) {
7878 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
7879 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
7880 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
7881 } else if (sp->device_type == XFRAME_II_DEVICE) {
7882 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
7883 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
7884 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
7885 }
7886
7887 /* store mac addresses from CAM to s2io_nic structure */
7888 do_s2io_store_unicast_mc(sp);
7889
c77dd43e
SS		 7890 /* Store the values of the MSIX table in the s2io_nic structure */
7891 store_xmsi_data(sp);
b41477f3
AR		 7892 /* reset Nic and bring it to known state */
7893 s2io_reset(sp);
7894
1da177e4 7895 /*
20346722 7896 * Initialize the tasklet status and link state flags
541ae68f 7897 * and the card state parameter
1da177e4 7898 */
1da177e4 7899 sp->tasklet_status = 0;
92b84437 7900 sp->state = 0;
1da177e4 7901
1da177e4 7902 /* Initialize spinlocks */
2fda096d
SR		 7903 for (i = 0; i < sp->config.tx_fifo_num; i++)
7904 spin_lock_init(&mac_control->fifos[i].tx_lock);
db874e65
SS		 7905
7906 if (!napi)
7907 spin_lock_init(&sp->put_lock);
7ba013ac 7908 spin_lock_init(&sp->rx_lock);
1da177e4 7909
20346722
K		 7910 /*
7911 * SXE-002: Configure link and activity LED to init state
7912 * on driver load.
1da177e4
LT		 7913 */
7914 subid = sp->pdev->subsystem_device;
7915 if ((subid & 0xFF) >= 0x07) {
7916 val64 = readq(&bar0->gpio_control);
7917 val64 |= 0x0000800000000000ULL;
7918 writeq(val64, &bar0->gpio_control);
7919 val64 = 0x0411040400000000ULL;
7920 writeq(val64, (void __iomem *) bar0 + 0x2700);
7921 val64 = readq(&bar0->gpio_control);
7922 }
7923
7924 sp->rx_csum = 1; /* Rx chksum verify enabled by default */
7925
7926 if (register_netdev(dev)) {
7927 DBG_PRINT(ERR_DBG, "Device registration failed\n");
7928 ret = -ENODEV;
7929 goto register_failed;
7930 }
9dc737a7 7931 s2io_vpd_read(sp);
0c61ed5f 7932 DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2007 Neterion Inc.\n");
b41477f3 7933 DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n",dev->name,
44c10138 7934 sp->product_name, pdev->revision);
b41477f3
AR		 7935 DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
7936 s2io_driver_version);
0795af57
JP		 7937 DBG_PRINT(ERR_DBG, "%s: MAC ADDR: %s\n",
7938 dev->name, print_mac(mac, dev->dev_addr));
19a60522 7939 DBG_PRINT(ERR_DBG, "SERIAL NUMBER: %s\n", sp->serial_num);
9dc737a7 7940 if (sp->device_type & XFRAME_II_DEVICE) {
0b1f7ebe 7941 mode = s2io_print_pci_mode(sp);
541ae68f 7942 if (mode < 0) {
9dc737a7 7943 DBG_PRINT(ERR_DBG, " Unsupported PCI bus mode\n");
541ae68f 7944 ret = -EBADSLT;
9dc737a7 7945 unregister_netdev(dev);
541ae68f
K		 7946 goto set_swap_failed;
7947 }
541ae68f 7948 }
9dc737a7
AR		 7949 switch(sp->rxd_mode) {
7950 case RXD_MODE_1:
7951 DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
7952 dev->name);
7953 break;
7954 case RXD_MODE_3B:
7955 DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
7956 dev->name);
7957 break;
9dc737a7 7958 }
db874e65
SS		 7959
7960 if (napi)
7961 DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
eaae7f72 7962 switch(sp->config.intr_type) {
9dc737a7
AR		 7963 case INTA:
7964 DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
7965 break;
9dc737a7
AR		 7966 case MSI_X:
7967 DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
7968 break;
7969 }
7d3d0439
RA		 7970 if (sp->lro)
7971 DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
9dc737a7 7972 dev->name);
db874e65
SS		 7973 if (ufo)
7974 DBG_PRINT(ERR_DBG, "%s: UDP Fragmentation Offload(UFO)"
7975 " enabled\n", dev->name);
7ba013ac 7976 /* Initialize device name */
9dc737a7 7977 sprintf(sp->name, "%s Neterion %s", dev->name, sp->product_name);
7ba013ac 7978
20346722
K		 7979 /*
7980 * Make Link state as off at this point, when the Link change
7981 * interrupt comes the state will be automatically changed to
1da177e4
LT		 7982 * the right state.
7983 */
7984 netif_carrier_off(dev);
1da177e4
LT		 7985
7986 return 0;
7987
7988 register_failed:
7989 set_swap_failed:
7990 iounmap(sp->bar1);
7991 bar1_remap_failed:
7992 iounmap(sp->bar0);
7993 bar0_remap_failed:
7994 mem_alloc_failed:
7995 free_shared_mem(sp);
7996 pci_disable_device(pdev);
eccb8628 7997 pci_release_regions(pdev);
1da177e4
LT		 7998 pci_set_drvdata(pdev, NULL);
7999 free_netdev(dev);
8000
8001 return ret;
8002}
8003
8004/**
20346722 8005 * s2io_rem_nic - Free the PCI device
1da177e4 8006 * @pdev: structure containing the PCI related information of the device.
20346722 8007 * Description: This function is called by the Pci subsystem to release a
1da177e4 8008 * PCI device and free up all resource held up by the device. This could
20346722 8009 * be in response to a Hot plug event or when the driver is to be removed
1da177e4
LT		 8010 * from memory.
8011 */
8012
8013static void __devexit s2io_rem_nic(struct pci_dev *pdev)
8014{
8015 struct net_device *dev =
8016 (struct net_device *) pci_get_drvdata(pdev);
1ee6dd77 8017 struct s2io_nic *sp;
1da177e4
LT		 8018
8019 if (dev == NULL) {
8020 DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8021 return;
8022 }
8023
22747d6b
FR		 8024 flush_scheduled_work();
8025
1da177e4
LT		 8026 sp = dev->priv;
8027 unregister_netdev(dev);
8028
8029 free_shared_mem(sp);
8030 iounmap(sp->bar0);
8031 iounmap(sp->bar1);
eccb8628 8032 pci_release_regions(pdev);
1da177e4 8033 pci_set_drvdata(pdev, NULL);
1da177e4 8034 free_netdev(dev);
19a60522 8035 pci_disable_device(pdev);
1da177e4
LT		 8036}
8037
8038/**
8039 * s2io_starter - Entry point for the driver
8040 * Description: This function is the entry point for the driver. It verifies
8041 * the module loadable parameters and initializes PCI configuration space.
8042 */
8043
43b7c451 8044static int __init s2io_starter(void)
1da177e4 8045{
29917620 8046 return pci_register_driver(&s2io_driver);
1da177e4
LT		 8047}
8048
8049/**
20346722 8050 * s2io_closer - Cleanup routine for the driver
1da177e4
LT		 8051 * Description: This function is the cleanup routine for the driver. It unregist * ers the driver.
8052 */
8053
372cc597 8054static __exit void s2io_closer(void)
1da177e4
LT		 8055{
8056 pci_unregister_driver(&s2io_driver);
8057 DBG_PRINT(INIT_DBG, "cleanup done\n");
8058}
8059
8060module_init(s2io_starter);
8061module_exit(s2io_closer);
7d3d0439 8062
6aa20a22 8063static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
1ee6dd77 8064 struct tcphdr **tcp, struct RxD_t *rxdp)
7d3d0439
RA		 8065{
8066 int ip_off;
8067 u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8068
8069 if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8070 DBG_PRINT(INIT_DBG,"%s: Non-TCP frames not supported for LRO\n",
8071 __FUNCTION__);
8072 return -1;
8073 }
8074
8075 /* TODO:
8076 * By default the VLAN field in the MAC is stripped by the card, if this
8077 * feature is turned off in rx_pa_cfg register, then the ip_off field
8078 * has to be shifted by a further 2 bytes
8079 */
8080 switch (l2_type) {
8081 case 0: /* DIX type */
8082 case 4: /* DIX type with VLAN */
8083 ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8084 break;
8085 /* LLC, SNAP etc are considered non-mergeable */
8086 default:
8087 return -1;
8088 }
8089
8090 *ip = (struct iphdr *)((u8 *)buffer + ip_off);
8091 ip_len = (u8)((*ip)->ihl);
8092 ip_len <<= 2;
8093 *tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8094
8095 return 0;
8096}
8097
1ee6dd77 8098static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8099 struct tcphdr *tcp)
8100{
8101 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8102 if ((lro->iph->saddr != ip->saddr) || (lro->iph->daddr != ip->daddr) ||
8103 (lro->tcph->source != tcp->source) || (lro->tcph->dest != tcp->dest))
8104 return -1;
8105 return 0;
8106}
8107
8108static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8109{
8110 return(ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2));
8111}
8112
1ee6dd77 8113static void initiate_new_session(struct lro *lro, u8 *l2h,
7d3d0439
RA		 8114 struct iphdr *ip, struct tcphdr *tcp, u32 tcp_pyld_len)
8115{
8116 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8117 lro->l2h = l2h;
8118 lro->iph = ip;
8119 lro->tcph = tcp;
8120 lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
c8855953 8121 lro->tcp_ack = tcp->ack_seq;
7d3d0439
RA		 8122 lro->sg_num = 1;
8123 lro->total_len = ntohs(ip->tot_len);
8124 lro->frags_len = 0;
6aa20a22 8125 /*
7d3d0439
RA		 8126 * check if we saw TCP timestamp. Other consistency checks have
8127 * already been done.
8128 */
8129 if (tcp->doff == 8) {
c8855953
SR		 8130 __be32 *ptr;
8131 ptr = (__be32 *)(tcp+1);
7d3d0439 8132 lro->saw_ts = 1;
c8855953 8133 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8134 lro->cur_tsecr = *(ptr+2);
8135 }
8136 lro->in_use = 1;
8137}
8138
1ee6dd77 8139static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
7d3d0439
RA		 8140{
8141 struct iphdr *ip = lro->iph;
8142 struct tcphdr *tcp = lro->tcph;
bd4f3ae1 8143 __sum16 nchk;
1ee6dd77 8144 struct stat_block *statinfo = sp->mac_control.stats_info;
7d3d0439
RA		 8145 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8146
8147 /* Update L3 header */
8148 ip->tot_len = htons(lro->total_len);
8149 ip->check = 0;
8150 nchk = ip_fast_csum((u8 *)lro->iph, ip->ihl);
8151 ip->check = nchk;
8152
8153 /* Update L4 header */
8154 tcp->ack_seq = lro->tcp_ack;
8155 tcp->window = lro->window;
8156
8157 /* Update tsecr field if this session has timestamps enabled */
8158 if (lro->saw_ts) {
c8855953 8159 __be32 *ptr = (__be32 *)(tcp + 1);
7d3d0439
RA		 8160 *(ptr+2) = lro->cur_tsecr;
8161 }
8162
8163 /* Update counters required for calculation of
8164 * average no. of packets aggregated.
8165 */
8166 statinfo->sw_stat.sum_avg_pkts_aggregated += lro->sg_num;
8167 statinfo->sw_stat.num_aggregations++;
8168}
8169
1ee6dd77 8170static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
7d3d0439
RA		 8171 struct tcphdr *tcp, u32 l4_pyld)
8172{
8173 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8174 lro->total_len += l4_pyld;
8175 lro->frags_len += l4_pyld;
8176 lro->tcp_next_seq += l4_pyld;
8177 lro->sg_num++;
8178
8179 /* Update ack seq no. and window ad(from this pkt) in LRO object */
8180 lro->tcp_ack = tcp->ack_seq;
8181 lro->window = tcp->window;
6aa20a22 8182
7d3d0439 8183 if (lro->saw_ts) {
c8855953 8184 __be32 *ptr;
7d3d0439 8185 /* Update tsecr and tsval from this packet */
c8855953
SR		 8186 ptr = (__be32 *)(tcp+1);
8187 lro->cur_tsval = ntohl(*(ptr+1));
7d3d0439
RA		 8188 lro->cur_tsecr = *(ptr + 2);
8189 }
8190}
8191
1ee6dd77 8192static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
7d3d0439
RA		 8193 struct tcphdr *tcp, u32 tcp_pyld_len)
8194{
7d3d0439
RA		 8195 u8 *ptr;
8196
79dc1901
AM		 8197 DBG_PRINT(INFO_DBG,"%s: Been here...\n", __FUNCTION__);
8198
7d3d0439
RA		 8199 if (!tcp_pyld_len) {
8200 /* Runt frame or a pure ack */
8201 return -1;
8202 }
8203
8204 if (ip->ihl != 5) /* IP has options */
8205 return -1;
8206
75c30b13
AR		 8207 /* If we see CE codepoint in IP header, packet is not mergeable */
8208 if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8209 return -1;
8210
8211 /* If we see ECE or CWR flags in TCP header, packet is not mergeable */
7d3d0439 8212 if (tcp->urg || tcp->psh || tcp->rst || tcp->syn || tcp->fin ||
75c30b13 8213 tcp->ece || tcp->cwr || !tcp->ack) {
7d3d0439
RA		 8214 /*
8215 * Currently recognize only the ack control word and
8216 * any other control field being set would result in
8217 * flushing the LRO session
8218 */
8219 return -1;
8220 }
8221
6aa20a22 8222 /*
7d3d0439
RA		 8223 * Allow only one TCP timestamp option. Don't aggregate if
8224 * any other options are detected.
8225 */
8226 if (tcp->doff != 5 && tcp->doff != 8)
8227 return -1;
8228
8229 if (tcp->doff == 8) {
6aa20a22 8230 ptr = (u8 *)(tcp + 1);
7d3d0439
RA		 8231 while (*ptr == TCPOPT_NOP)
8232 ptr++;
8233 if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8234 return -1;
8235
8236 /* Ensure timestamp value increases monotonically */
8237 if (l_lro)
c8855953 8238 if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
7d3d0439
RA		 8239 return -1;
8240
8241 /* timestamp echo reply should be non-zero */
c8855953 8242 if (*((__be32 *)(ptr+6)) == 0)
7d3d0439
RA		 8243 return -1;
8244 }
8245
8246 return 0;
8247}
8248
8249static int
1ee6dd77
RB		 8250s2io_club_tcp_session(u8 *buffer, u8 **tcp, u32 *tcp_len, struct lro **lro,
8251 struct RxD_t *rxdp, struct s2io_nic *sp)
7d3d0439
RA		 8252{
8253 struct iphdr *ip;
8254 struct tcphdr *tcph;
8255 int ret = 0, i;
8256
8257 if (!(ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8258 rxdp))) {
8259 DBG_PRINT(INFO_DBG,"IP Saddr: %x Daddr: %x\n",
8260 ip->saddr, ip->daddr);
8261 } else {
8262 return ret;
8263 }
8264
8265 tcph = (struct tcphdr *)*tcp;
8266 *tcp_len = get_l4_pyld_length(ip, tcph);
8267 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 8268 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 8269 if (l_lro->in_use) {
8270 if (check_for_socket_match(l_lro, ip, tcph))
8271 continue;
8272 /* Sock pair matched */
8273 *lro = l_lro;
8274
8275 if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8276 DBG_PRINT(INFO_DBG, "%s:Out of order. expected "
8277 "0x%x, actual 0x%x\n", __FUNCTION__,
8278 (*lro)->tcp_next_seq,
8279 ntohl(tcph->seq));
8280
8281 sp->mac_control.stats_info->
8282 sw_stat.outof_sequence_pkts++;
8283 ret = 2;
8284 break;
8285 }
8286
8287 if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,*tcp_len))
8288 ret = 1; /* Aggregate */
8289 else
8290 ret = 2; /* Flush both */
8291 break;
8292 }
8293 }
8294
8295 if (ret == 0) {
8296 /* Before searching for available LRO objects,
8297 * check if the pkt is L3/L4 aggregatable. If not
8298 * don't create new LRO session. Just send this
8299 * packet up.
8300 */
8301 if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len)) {
8302 return 5;
8303 }
8304
8305 for (i=0; i<MAX_LRO_SESSIONS; i++) {
1ee6dd77 8306 struct lro *l_lro = &sp->lro0_n[i];
7d3d0439
RA		 8307 if (!(l_lro->in_use)) {
8308 *lro = l_lro;
8309 ret = 3; /* Begin anew */
8310 break;
8311 }
8312 }
8313 }
8314
8315 if (ret == 0) { /* sessions exceeded */
8316 DBG_PRINT(INFO_DBG,"%s:All LRO sessions already in use\n",
8317 __FUNCTION__);
8318 *lro = NULL;
8319 return ret;
8320 }
8321
8322 switch (ret) {
8323 case 3:
8324 initiate_new_session(*lro, buffer, ip, tcph, *tcp_len);
8325 break;
8326 case 2:
8327 update_L3L4_header(sp, *lro);
8328 break;
8329 case 1:
8330 aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8331 if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8332 update_L3L4_header(sp, *lro);
8333 ret = 4; /* Flush the LRO */
8334 }
8335 break;
8336 default:
8337 DBG_PRINT(ERR_DBG,"%s:Dont know, can't say!!\n",
8338 __FUNCTION__);
8339 break;
8340 }
8341
8342 return ret;
8343}
8344
1ee6dd77 8345static void clear_lro_session(struct lro *lro)
7d3d0439 8346{
1ee6dd77 8347 static u16 lro_struct_size = sizeof(struct lro);
7d3d0439
RA		 8348
8349 memset(lro, 0, lro_struct_size);
8350}
8351
8352static void queue_rx_frame(struct sk_buff *skb)
8353{
8354 struct net_device *dev = skb->dev;
8355
8356 skb->protocol = eth_type_trans(skb, dev);
db874e65
SS		 8357 if (napi)
8358 netif_receive_skb(skb);
8359 else
8360 netif_rx(skb);
7d3d0439
RA		 8361}
8362
1ee6dd77
RB		 8363static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8364 struct sk_buff *skb,
7d3d0439
RA		 8365 u32 tcp_len)
8366{
75c30b13 8367 struct sk_buff *first = lro->parent;
7d3d0439
RA		 8368
8369 first->len += tcp_len;
8370 first->data_len = lro->frags_len;
8371 skb_pull(skb, (skb->len - tcp_len));
75c30b13
AR		 8372 if (skb_shinfo(first)->frag_list)
8373 lro->last_frag->next = skb;
7d3d0439
RA		 8374 else
8375 skb_shinfo(first)->frag_list = skb;
372cc597 8376 first->truesize += skb->truesize;
75c30b13 8377 lro->last_frag = skb;
7d3d0439
RA		 8378 sp->mac_control.stats_info->sw_stat.clubbed_frms_cnt++;
8379 return;
8380}
d796fdb7
LV		 8381
8382/**
8383 * s2io_io_error_detected - called when PCI error is detected
8384 * @pdev: Pointer to PCI device
8453d43f 8385 * @state: The current pci connection state
d796fdb7
LV		 8386 *
8387 * This function is called after a PCI bus error affecting
8388 * this device has been detected.
8389 */
8390static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8391 pci_channel_state_t state)
8392{
8393 struct net_device *netdev = pci_get_drvdata(pdev);
8394 struct s2io_nic *sp = netdev->priv;
8395
8396 netif_device_detach(netdev);
8397
8398 if (netif_running(netdev)) {
8399 /* Bring down the card, while avoiding PCI I/O */
8400 do_s2io_card_down(sp, 0);
d796fdb7
LV		 8401 }
8402 pci_disable_device(pdev);
8403
8404 return PCI_ERS_RESULT_NEED_RESET;
8405}
8406
8407/**
8408 * s2io_io_slot_reset - called after the pci bus has been reset.
8409 * @pdev: Pointer to PCI device
8410 *
8411 * Restart the card from scratch, as if from a cold-boot.
8412 * At this point, the card has exprienced a hard reset,
8413 * followed by fixups by BIOS, and has its config space
8414 * set up identically to what it was at cold boot.
8415 */
8416static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8417{
8418 struct net_device *netdev = pci_get_drvdata(pdev);
8419 struct s2io_nic *sp = netdev->priv;
8420
8421 if (pci_enable_device(pdev)) {
8422 printk(KERN_ERR "s2io: "
8423 "Cannot re-enable PCI device after reset.\n");
8424 return PCI_ERS_RESULT_DISCONNECT;
8425 }
8426
8427 pci_set_master(pdev);
8428 s2io_reset(sp);
8429
8430 return PCI_ERS_RESULT_RECOVERED;
8431}
8432
8433/**
8434 * s2io_io_resume - called when traffic can start flowing again.
8435 * @pdev: Pointer to PCI device
8436 *
8437 * This callback is called when the error recovery driver tells
8438 * us that its OK to resume normal operation.
8439 */
8440static void s2io_io_resume(struct pci_dev *pdev)
8441{
8442 struct net_device *netdev = pci_get_drvdata(pdev);
8443 struct s2io_nic *sp = netdev->priv;
8444
8445 if (netif_running(netdev)) {
8446 if (s2io_card_up(sp)) {
8447 printk(KERN_ERR "s2io: "
8448 "Can't bring device back up after reset.\n");
8449 return;
8450 }
8451
8452 if (s2io_set_mac_addr(netdev, netdev->dev_addr) == FAILURE) {
8453 s2io_card_down(sp);
8454 printk(KERN_ERR "s2io: "
8455 "Can't resetore mac addr after reset.\n");
8456 return;
8457 }
8458 }
8459
8460 netif_device_attach(netdev);
8461 netif_wake_queue(netdev);
8462}
ubuntu-bionic-kernel mirror