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1 | /* Silan SC92031 PCI Fast Ethernet Adapter driver |
2 | * | |
3 | * Based on vendor drivers: | |
4 | * Silan Fast Ethernet Netcard Driver: | |
5 | * MODULE_AUTHOR ("gaoyonghong"); | |
6 | * MODULE_DESCRIPTION ("SILAN Fast Ethernet driver"); | |
7 | * MODULE_LICENSE("GPL"); | |
8 | * 8139D Fast Ethernet driver: | |
9 | * (C) 2002 by gaoyonghong | |
10 | * MODULE_AUTHOR ("gaoyonghong"); | |
11 | * MODULE_DESCRIPTION ("Rsltek 8139D PCI Fast Ethernet Adapter driver"); | |
12 | * MODULE_LICENSE("GPL"); | |
13 | * Both are almost identical and seem to be based on pci-skeleton.c | |
14 | * | |
15 | * Rewritten for 2.6 by Cesar Eduardo Barros | |
16 | */ | |
17 | ||
18 | /* Note about set_mac_address: I don't know how to change the hardware | |
19 | * matching, so you need to enable IFF_PROMISC when using it. | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/kernel.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/netdevice.h> | |
28 | #include <linux/etherdevice.h> | |
29 | #include <linux/ethtool.h> | |
30 | #include <linux/crc32.h> | |
31 | ||
32 | #include <asm/irq.h> | |
33 | ||
34 | #define PCI_VENDOR_ID_SILAN 0x1904 | |
35 | #define PCI_DEVICE_ID_SILAN_SC92031 0x2031 | |
36 | #define PCI_DEVICE_ID_SILAN_8139D 0x8139 | |
37 | ||
38 | #define SC92031_NAME "sc92031" | |
39 | #define SC92031_DESCRIPTION "Silan SC92031 PCI Fast Ethernet Adapter driver" | |
bf345707 CEB |
40 | |
41 | /* BAR 0 is MMIO, BAR 1 is PIO */ | |
42 | #ifndef SC92031_USE_BAR | |
43 | #define SC92031_USE_BAR 0 | |
44 | #endif | |
45 | ||
46 | /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */ | |
47 | static int multicast_filter_limit = 64; | |
48 | module_param(multicast_filter_limit, int, 0); | |
49 | MODULE_PARM_DESC(multicast_filter_limit, | |
50 | "Maximum number of filtered multicast addresses"); | |
51 | ||
52 | static int media; | |
53 | module_param(media, int, 0); | |
54 | MODULE_PARM_DESC(media, "Media type (0x00 = autodetect," | |
55 | " 0x01 = 10M half, 0x02 = 10M full," | |
56 | " 0x04 = 100M half, 0x08 = 100M full)"); | |
57 | ||
58 | /* Size of the in-memory receive ring. */ | |
59 | #define RX_BUF_LEN_IDX 3 /* 0==8K, 1==16K, 2==32K, 3==64K ,4==128K*/ | |
60 | #define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX) | |
61 | ||
62 | /* Number of Tx descriptor registers. */ | |
63 | #define NUM_TX_DESC 4 | |
64 | ||
65 | /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/ | |
66 | #define MAX_ETH_FRAME_SIZE 1536 | |
67 | ||
68 | /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */ | |
69 | #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE | |
70 | #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC) | |
71 | ||
72 | /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */ | |
73 | #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */ | |
74 | ||
75 | /* Time in jiffies before concluding the transmitter is hung. */ | |
76 | #define TX_TIMEOUT (4*HZ) | |
77 | ||
78 | #define SILAN_STATS_NUM 2 /* number of ETHTOOL_GSTATS */ | |
79 | ||
80 | /* media options */ | |
81 | #define AUTOSELECT 0x00 | |
82 | #define M10_HALF 0x01 | |
83 | #define M10_FULL 0x02 | |
84 | #define M100_HALF 0x04 | |
85 | #define M100_FULL 0x08 | |
86 | ||
87 | /* Symbolic offsets to registers. */ | |
88 | enum silan_registers { | |
89 | Config0 = 0x00, // Config0 | |
90 | Config1 = 0x04, // Config1 | |
91 | RxBufWPtr = 0x08, // Rx buffer writer poiter | |
92 | IntrStatus = 0x0C, // Interrupt status | |
93 | IntrMask = 0x10, // Interrupt mask | |
94 | RxbufAddr = 0x14, // Rx buffer start address | |
95 | RxBufRPtr = 0x18, // Rx buffer read pointer | |
96 | Txstatusall = 0x1C, // Transmit status of all descriptors | |
97 | TxStatus0 = 0x20, // Transmit status (Four 32bit registers). | |
98 | TxAddr0 = 0x30, // Tx descriptors (also four 32bit). | |
99 | RxConfig = 0x40, // Rx configuration | |
100 | MAC0 = 0x44, // Ethernet hardware address. | |
101 | MAR0 = 0x4C, // Multicast filter. | |
102 | RxStatus0 = 0x54, // Rx status | |
103 | TxConfig = 0x5C, // Tx configuration | |
104 | PhyCtrl = 0x60, // physical control | |
105 | FlowCtrlConfig = 0x64, // flow control | |
106 | Miicmd0 = 0x68, // Mii command0 register | |
107 | Miicmd1 = 0x6C, // Mii command1 register | |
108 | Miistatus = 0x70, // Mii status register | |
109 | Timercnt = 0x74, // Timer counter register | |
110 | TimerIntr = 0x78, // Timer interrupt register | |
111 | PMConfig = 0x7C, // Power Manager configuration | |
112 | CRC0 = 0x80, // Power Manager CRC ( Two 32bit regisers) | |
113 | Wakeup0 = 0x88, // power Manager wakeup( Eight 64bit regiser) | |
114 | LSBCRC0 = 0xC8, // power Manager LSBCRC(Two 32bit regiser) | |
115 | TestD0 = 0xD0, | |
116 | TestD4 = 0xD4, | |
117 | TestD8 = 0xD8, | |
118 | }; | |
119 | ||
120 | #define MII_BMCR 0 // Basic mode control register | |
121 | #define MII_BMSR 1 // Basic mode status register | |
122 | #define MII_JAB 16 | |
123 | #define MII_OutputStatus 24 | |
124 | ||
125 | #define BMCR_FULLDPLX 0x0100 // Full duplex | |
126 | #define BMCR_ANRESTART 0x0200 // Auto negotiation restart | |
127 | #define BMCR_ANENABLE 0x1000 // Enable auto negotiation | |
128 | #define BMCR_SPEED100 0x2000 // Select 100Mbps | |
129 | #define BMSR_LSTATUS 0x0004 // Link status | |
130 | #define PHY_16_JAB_ENB 0x1000 | |
131 | #define PHY_16_PORT_ENB 0x1 | |
132 | ||
133 | enum IntrStatusBits { | |
134 | LinkFail = 0x80000000, | |
135 | LinkOK = 0x40000000, | |
136 | TimeOut = 0x20000000, | |
137 | RxOverflow = 0x0040, | |
138 | RxOK = 0x0020, | |
139 | TxOK = 0x0001, | |
140 | IntrBits = LinkFail|LinkOK|TimeOut|RxOverflow|RxOK|TxOK, | |
141 | }; | |
142 | ||
143 | enum TxStatusBits { | |
144 | TxCarrierLost = 0x20000000, | |
145 | TxAborted = 0x10000000, | |
146 | TxOutOfWindow = 0x08000000, | |
147 | TxNccShift = 22, | |
148 | EarlyTxThresShift = 16, | |
149 | TxStatOK = 0x8000, | |
150 | TxUnderrun = 0x4000, | |
151 | TxOwn = 0x2000, | |
152 | }; | |
153 | ||
154 | enum RxStatusBits { | |
155 | RxStatesOK = 0x80000, | |
156 | RxBadAlign = 0x40000, | |
157 | RxHugeFrame = 0x20000, | |
158 | RxSmallFrame = 0x10000, | |
159 | RxCRCOK = 0x8000, | |
160 | RxCrlFrame = 0x4000, | |
161 | Rx_Broadcast = 0x2000, | |
162 | Rx_Multicast = 0x1000, | |
163 | RxAddrMatch = 0x0800, | |
164 | MiiErr = 0x0400, | |
165 | }; | |
166 | ||
167 | enum RxConfigBits { | |
168 | RxFullDx = 0x80000000, | |
169 | RxEnb = 0x40000000, | |
170 | RxSmall = 0x20000000, | |
171 | RxHuge = 0x10000000, | |
172 | RxErr = 0x08000000, | |
173 | RxAllphys = 0x04000000, | |
174 | RxMulticast = 0x02000000, | |
175 | RxBroadcast = 0x01000000, | |
176 | RxLoopBack = (1 << 23) | (1 << 22), | |
177 | LowThresholdShift = 12, | |
178 | HighThresholdShift = 2, | |
179 | }; | |
180 | ||
181 | enum TxConfigBits { | |
182 | TxFullDx = 0x80000000, | |
183 | TxEnb = 0x40000000, | |
184 | TxEnbPad = 0x20000000, | |
185 | TxEnbHuge = 0x10000000, | |
186 | TxEnbFCS = 0x08000000, | |
187 | TxNoBackOff = 0x04000000, | |
188 | TxEnbPrem = 0x02000000, | |
189 | TxCareLostCrs = 0x1000000, | |
190 | TxExdCollNum = 0xf00000, | |
191 | TxDataRate = 0x80000, | |
192 | }; | |
193 | ||
194 | enum PhyCtrlconfigbits { | |
195 | PhyCtrlAne = 0x80000000, | |
196 | PhyCtrlSpd100 = 0x40000000, | |
197 | PhyCtrlSpd10 = 0x20000000, | |
198 | PhyCtrlPhyBaseAddr = 0x1f000000, | |
199 | PhyCtrlDux = 0x800000, | |
200 | PhyCtrlReset = 0x400000, | |
201 | }; | |
202 | ||
203 | enum FlowCtrlConfigBits { | |
204 | FlowCtrlFullDX = 0x80000000, | |
205 | FlowCtrlEnb = 0x40000000, | |
206 | }; | |
207 | ||
208 | enum Config0Bits { | |
209 | Cfg0_Reset = 0x80000000, | |
210 | Cfg0_Anaoff = 0x40000000, | |
211 | Cfg0_LDPS = 0x20000000, | |
212 | }; | |
213 | ||
214 | enum Config1Bits { | |
215 | Cfg1_EarlyRx = 1 << 31, | |
216 | Cfg1_EarlyTx = 1 << 30, | |
217 | ||
218 | //rx buffer size | |
219 | Cfg1_Rcv8K = 0x0, | |
220 | Cfg1_Rcv16K = 0x1, | |
221 | Cfg1_Rcv32K = 0x3, | |
222 | Cfg1_Rcv64K = 0x7, | |
223 | Cfg1_Rcv128K = 0xf, | |
224 | }; | |
225 | ||
226 | enum MiiCmd0Bits { | |
227 | Mii_Divider = 0x20000000, | |
228 | Mii_WRITE = 0x400000, | |
229 | Mii_READ = 0x200000, | |
230 | Mii_SCAN = 0x100000, | |
231 | Mii_Tamod = 0x80000, | |
232 | Mii_Drvmod = 0x40000, | |
233 | Mii_mdc = 0x20000, | |
234 | Mii_mdoen = 0x10000, | |
235 | Mii_mdo = 0x8000, | |
236 | Mii_mdi = 0x4000, | |
237 | }; | |
238 | ||
239 | enum MiiStatusBits { | |
240 | Mii_StatusBusy = 0x80000000, | |
241 | }; | |
242 | ||
243 | enum PMConfigBits { | |
244 | PM_Enable = 1 << 31, | |
245 | PM_LongWF = 1 << 30, | |
246 | PM_Magic = 1 << 29, | |
247 | PM_LANWake = 1 << 28, | |
248 | PM_LWPTN = (1 << 27 | 1<< 26), | |
249 | PM_LinkUp = 1 << 25, | |
250 | PM_WakeUp = 1 << 24, | |
251 | }; | |
252 | ||
253 | /* Locking rules: | |
254 | * priv->lock protects most of the fields of priv and most of the | |
255 | * hardware registers. It does not have to protect against softirqs | |
256 | * between sc92031_disable_interrupts and sc92031_enable_interrupts; | |
257 | * it also does not need to be used in ->open and ->stop while the | |
258 | * device interrupts are off. | |
259 | * Not having to protect against softirqs is very useful due to heavy | |
260 | * use of mdelay() at _sc92031_reset. | |
261 | * Functions prefixed with _sc92031_ must be called with the lock held; | |
262 | * functions prefixed with sc92031_ must be called without the lock held. | |
263 | * Use mmiowb() before unlocking if the hardware was written to. | |
264 | */ | |
265 | ||
266 | /* Locking rules for the interrupt: | |
267 | * - the interrupt and the tasklet never run at the same time | |
268 | * - neither run between sc92031_disable_interrupts and | |
269 | * sc92031_enable_interrupt | |
270 | */ | |
271 | ||
272 | struct sc92031_priv { | |
273 | spinlock_t lock; | |
274 | /* iomap.h cookie */ | |
275 | void __iomem *port_base; | |
276 | /* pci device structure */ | |
277 | struct pci_dev *pdev; | |
278 | /* tasklet */ | |
279 | struct tasklet_struct tasklet; | |
280 | ||
281 | /* CPU address of rx ring */ | |
282 | void *rx_ring; | |
283 | /* PCI address of rx ring */ | |
284 | dma_addr_t rx_ring_dma_addr; | |
285 | /* PCI address of rx ring read pointer */ | |
286 | dma_addr_t rx_ring_tail; | |
287 | ||
288 | /* tx ring write index */ | |
289 | unsigned tx_head; | |
290 | /* tx ring read index */ | |
291 | unsigned tx_tail; | |
292 | /* CPU address of tx bounce buffer */ | |
293 | void *tx_bufs; | |
294 | /* PCI address of tx bounce buffer */ | |
295 | dma_addr_t tx_bufs_dma_addr; | |
296 | ||
297 | /* copies of some hardware registers */ | |
298 | u32 intr_status; | |
299 | atomic_t intr_mask; | |
300 | u32 rx_config; | |
301 | u32 tx_config; | |
302 | u32 pm_config; | |
303 | ||
304 | /* copy of some flags from dev->flags */ | |
305 | unsigned int mc_flags; | |
306 | ||
307 | /* for ETHTOOL_GSTATS */ | |
308 | u64 tx_timeouts; | |
309 | u64 rx_loss; | |
310 | ||
311 | /* for dev->get_stats */ | |
312 | long rx_value; | |
bf345707 CEB |
313 | }; |
314 | ||
315 | /* I don't know which registers can be safely read; however, I can guess | |
316 | * MAC0 is one of them. */ | |
317 | static inline void _sc92031_dummy_read(void __iomem *port_base) | |
318 | { | |
319 | ioread32(port_base + MAC0); | |
320 | } | |
321 | ||
322 | static u32 _sc92031_mii_wait(void __iomem *port_base) | |
323 | { | |
324 | u32 mii_status; | |
325 | ||
326 | do { | |
327 | udelay(10); | |
328 | mii_status = ioread32(port_base + Miistatus); | |
329 | } while (mii_status & Mii_StatusBusy); | |
330 | ||
331 | return mii_status; | |
332 | } | |
333 | ||
334 | static u32 _sc92031_mii_cmd(void __iomem *port_base, u32 cmd0, u32 cmd1) | |
335 | { | |
336 | iowrite32(Mii_Divider, port_base + Miicmd0); | |
337 | ||
338 | _sc92031_mii_wait(port_base); | |
339 | ||
340 | iowrite32(cmd1, port_base + Miicmd1); | |
341 | iowrite32(Mii_Divider | cmd0, port_base + Miicmd0); | |
342 | ||
343 | return _sc92031_mii_wait(port_base); | |
344 | } | |
345 | ||
346 | static void _sc92031_mii_scan(void __iomem *port_base) | |
347 | { | |
348 | _sc92031_mii_cmd(port_base, Mii_SCAN, 0x1 << 6); | |
349 | } | |
350 | ||
351 | static u16 _sc92031_mii_read(void __iomem *port_base, unsigned reg) | |
352 | { | |
353 | return _sc92031_mii_cmd(port_base, Mii_READ, reg << 6) >> 13; | |
354 | } | |
355 | ||
356 | static void _sc92031_mii_write(void __iomem *port_base, unsigned reg, u16 val) | |
357 | { | |
358 | _sc92031_mii_cmd(port_base, Mii_WRITE, (reg << 6) | ((u32)val << 11)); | |
359 | } | |
360 | ||
361 | static void sc92031_disable_interrupts(struct net_device *dev) | |
362 | { | |
363 | struct sc92031_priv *priv = netdev_priv(dev); | |
364 | void __iomem *port_base = priv->port_base; | |
365 | ||
366 | /* tell the tasklet/interrupt not to enable interrupts */ | |
367 | atomic_set(&priv->intr_mask, 0); | |
368 | wmb(); | |
369 | ||
370 | /* stop interrupts */ | |
371 | iowrite32(0, port_base + IntrMask); | |
372 | _sc92031_dummy_read(port_base); | |
373 | mmiowb(); | |
374 | ||
375 | /* wait for any concurrent interrupt/tasklet to finish */ | |
376 | synchronize_irq(dev->irq); | |
377 | tasklet_disable(&priv->tasklet); | |
378 | } | |
379 | ||
380 | static void sc92031_enable_interrupts(struct net_device *dev) | |
381 | { | |
382 | struct sc92031_priv *priv = netdev_priv(dev); | |
383 | void __iomem *port_base = priv->port_base; | |
384 | ||
385 | tasklet_enable(&priv->tasklet); | |
386 | ||
387 | atomic_set(&priv->intr_mask, IntrBits); | |
388 | wmb(); | |
389 | ||
390 | iowrite32(IntrBits, port_base + IntrMask); | |
391 | mmiowb(); | |
392 | } | |
393 | ||
394 | static void _sc92031_disable_tx_rx(struct net_device *dev) | |
395 | { | |
396 | struct sc92031_priv *priv = netdev_priv(dev); | |
397 | void __iomem *port_base = priv->port_base; | |
398 | ||
399 | priv->rx_config &= ~RxEnb; | |
400 | priv->tx_config &= ~TxEnb; | |
401 | iowrite32(priv->rx_config, port_base + RxConfig); | |
402 | iowrite32(priv->tx_config, port_base + TxConfig); | |
403 | } | |
404 | ||
405 | static void _sc92031_enable_tx_rx(struct net_device *dev) | |
406 | { | |
407 | struct sc92031_priv *priv = netdev_priv(dev); | |
408 | void __iomem *port_base = priv->port_base; | |
409 | ||
410 | priv->rx_config |= RxEnb; | |
411 | priv->tx_config |= TxEnb; | |
412 | iowrite32(priv->rx_config, port_base + RxConfig); | |
413 | iowrite32(priv->tx_config, port_base + TxConfig); | |
414 | } | |
415 | ||
416 | static void _sc92031_tx_clear(struct net_device *dev) | |
417 | { | |
418 | struct sc92031_priv *priv = netdev_priv(dev); | |
419 | ||
420 | while (priv->tx_head - priv->tx_tail > 0) { | |
421 | priv->tx_tail++; | |
9c28eaea | 422 | dev->stats.tx_dropped++; |
bf345707 CEB |
423 | } |
424 | priv->tx_head = priv->tx_tail = 0; | |
425 | } | |
426 | ||
427 | static void _sc92031_set_mar(struct net_device *dev) | |
428 | { | |
429 | struct sc92031_priv *priv = netdev_priv(dev); | |
430 | void __iomem *port_base = priv->port_base; | |
431 | u32 mar0 = 0, mar1 = 0; | |
432 | ||
433 | if ((dev->flags & IFF_PROMISC) | |
434 | || dev->mc_count > multicast_filter_limit | |
435 | || (dev->flags & IFF_ALLMULTI)) | |
436 | mar0 = mar1 = 0xffffffff; | |
437 | else if (dev->flags & IFF_MULTICAST) { | |
438 | struct dev_mc_list *mc_list; | |
439 | ||
440 | for (mc_list = dev->mc_list; mc_list; mc_list = mc_list->next) { | |
441 | u32 crc; | |
442 | unsigned bit = 0; | |
443 | ||
444 | crc = ~ether_crc(ETH_ALEN, mc_list->dmi_addr); | |
445 | crc >>= 24; | |
446 | ||
447 | if (crc & 0x01) bit |= 0x02; | |
448 | if (crc & 0x02) bit |= 0x01; | |
449 | if (crc & 0x10) bit |= 0x20; | |
450 | if (crc & 0x20) bit |= 0x10; | |
451 | if (crc & 0x40) bit |= 0x08; | |
452 | if (crc & 0x80) bit |= 0x04; | |
453 | ||
454 | if (bit > 31) | |
455 | mar0 |= 0x1 << (bit - 32); | |
456 | else | |
457 | mar1 |= 0x1 << bit; | |
458 | } | |
459 | } | |
460 | ||
461 | iowrite32(mar0, port_base + MAR0); | |
462 | iowrite32(mar1, port_base + MAR0 + 4); | |
463 | } | |
464 | ||
465 | static void _sc92031_set_rx_config(struct net_device *dev) | |
466 | { | |
467 | struct sc92031_priv *priv = netdev_priv(dev); | |
468 | void __iomem *port_base = priv->port_base; | |
469 | unsigned int old_mc_flags; | |
470 | u32 rx_config_bits = 0; | |
471 | ||
472 | old_mc_flags = priv->mc_flags; | |
473 | ||
474 | if (dev->flags & IFF_PROMISC) | |
475 | rx_config_bits |= RxSmall | RxHuge | RxErr | RxBroadcast | |
476 | | RxMulticast | RxAllphys; | |
477 | ||
478 | if (dev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) | |
479 | rx_config_bits |= RxMulticast; | |
480 | ||
481 | if (dev->flags & IFF_BROADCAST) | |
482 | rx_config_bits |= RxBroadcast; | |
483 | ||
484 | priv->rx_config &= ~(RxSmall | RxHuge | RxErr | RxBroadcast | |
485 | | RxMulticast | RxAllphys); | |
486 | priv->rx_config |= rx_config_bits; | |
487 | ||
488 | priv->mc_flags = dev->flags & (IFF_PROMISC | IFF_ALLMULTI | |
489 | | IFF_MULTICAST | IFF_BROADCAST); | |
490 | ||
491 | if (netif_carrier_ok(dev) && priv->mc_flags != old_mc_flags) | |
492 | iowrite32(priv->rx_config, port_base + RxConfig); | |
493 | } | |
494 | ||
495 | static bool _sc92031_check_media(struct net_device *dev) | |
496 | { | |
497 | struct sc92031_priv *priv = netdev_priv(dev); | |
498 | void __iomem *port_base = priv->port_base; | |
499 | u16 bmsr; | |
500 | ||
501 | bmsr = _sc92031_mii_read(port_base, MII_BMSR); | |
502 | rmb(); | |
503 | if (bmsr & BMSR_LSTATUS) { | |
504 | bool speed_100, duplex_full; | |
505 | u32 flow_ctrl_config = 0; | |
506 | u16 output_status = _sc92031_mii_read(port_base, | |
507 | MII_OutputStatus); | |
508 | _sc92031_mii_scan(port_base); | |
509 | ||
510 | speed_100 = output_status & 0x2; | |
511 | duplex_full = output_status & 0x4; | |
512 | ||
513 | /* Initial Tx/Rx configuration */ | |
514 | priv->rx_config = (0x40 << LowThresholdShift) | (0x1c0 << HighThresholdShift); | |
515 | priv->tx_config = 0x48800000; | |
516 | ||
517 | /* NOTE: vendor driver had dead code here to enable tx padding */ | |
518 | ||
519 | if (!speed_100) | |
520 | priv->tx_config |= 0x80000; | |
521 | ||
522 | // configure rx mode | |
523 | _sc92031_set_rx_config(dev); | |
524 | ||
525 | if (duplex_full) { | |
526 | priv->rx_config |= RxFullDx; | |
527 | priv->tx_config |= TxFullDx; | |
528 | flow_ctrl_config = FlowCtrlFullDX | FlowCtrlEnb; | |
529 | } else { | |
530 | priv->rx_config &= ~RxFullDx; | |
531 | priv->tx_config &= ~TxFullDx; | |
532 | } | |
533 | ||
534 | _sc92031_set_mar(dev); | |
535 | _sc92031_set_rx_config(dev); | |
536 | _sc92031_enable_tx_rx(dev); | |
537 | iowrite32(flow_ctrl_config, port_base + FlowCtrlConfig); | |
538 | ||
539 | netif_carrier_on(dev); | |
540 | ||
541 | if (printk_ratelimit()) | |
542 | printk(KERN_INFO "%s: link up, %sMbps, %s-duplex\n", | |
543 | dev->name, | |
544 | speed_100 ? "100" : "10", | |
545 | duplex_full ? "full" : "half"); | |
546 | return true; | |
547 | } else { | |
548 | _sc92031_mii_scan(port_base); | |
549 | ||
550 | netif_carrier_off(dev); | |
551 | ||
552 | _sc92031_disable_tx_rx(dev); | |
553 | ||
554 | if (printk_ratelimit()) | |
555 | printk(KERN_INFO "%s: link down\n", dev->name); | |
556 | return false; | |
557 | } | |
558 | } | |
559 | ||
560 | static void _sc92031_phy_reset(struct net_device *dev) | |
561 | { | |
562 | struct sc92031_priv *priv = netdev_priv(dev); | |
563 | void __iomem *port_base = priv->port_base; | |
564 | u32 phy_ctrl; | |
565 | ||
566 | phy_ctrl = ioread32(port_base + PhyCtrl); | |
567 | phy_ctrl &= ~(PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10); | |
568 | phy_ctrl |= PhyCtrlAne | PhyCtrlReset; | |
569 | ||
570 | switch (media) { | |
571 | default: | |
572 | case AUTOSELECT: | |
573 | phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10; | |
574 | break; | |
575 | case M10_HALF: | |
576 | phy_ctrl |= PhyCtrlSpd10; | |
577 | break; | |
578 | case M10_FULL: | |
579 | phy_ctrl |= PhyCtrlDux | PhyCtrlSpd10; | |
580 | break; | |
581 | case M100_HALF: | |
582 | phy_ctrl |= PhyCtrlSpd100; | |
583 | break; | |
584 | case M100_FULL: | |
585 | phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100; | |
586 | break; | |
587 | } | |
588 | ||
589 | iowrite32(phy_ctrl, port_base + PhyCtrl); | |
590 | mdelay(10); | |
591 | ||
592 | phy_ctrl &= ~PhyCtrlReset; | |
593 | iowrite32(phy_ctrl, port_base + PhyCtrl); | |
594 | mdelay(1); | |
595 | ||
596 | _sc92031_mii_write(port_base, MII_JAB, | |
597 | PHY_16_JAB_ENB | PHY_16_PORT_ENB); | |
598 | _sc92031_mii_scan(port_base); | |
599 | ||
600 | netif_carrier_off(dev); | |
601 | netif_stop_queue(dev); | |
602 | } | |
603 | ||
604 | static void _sc92031_reset(struct net_device *dev) | |
605 | { | |
606 | struct sc92031_priv *priv = netdev_priv(dev); | |
607 | void __iomem *port_base = priv->port_base; | |
608 | ||
609 | /* disable PM */ | |
610 | iowrite32(0, port_base + PMConfig); | |
611 | ||
612 | /* soft reset the chip */ | |
613 | iowrite32(Cfg0_Reset, port_base + Config0); | |
614 | mdelay(200); | |
615 | ||
616 | iowrite32(0, port_base + Config0); | |
617 | mdelay(10); | |
618 | ||
619 | /* disable interrupts */ | |
620 | iowrite32(0, port_base + IntrMask); | |
621 | ||
622 | /* clear multicast address */ | |
623 | iowrite32(0, port_base + MAR0); | |
624 | iowrite32(0, port_base + MAR0 + 4); | |
625 | ||
626 | /* init rx ring */ | |
627 | iowrite32(priv->rx_ring_dma_addr, port_base + RxbufAddr); | |
628 | priv->rx_ring_tail = priv->rx_ring_dma_addr; | |
629 | ||
630 | /* init tx ring */ | |
631 | _sc92031_tx_clear(dev); | |
632 | ||
633 | /* clear old register values */ | |
634 | priv->intr_status = 0; | |
635 | atomic_set(&priv->intr_mask, 0); | |
636 | priv->rx_config = 0; | |
637 | priv->tx_config = 0; | |
638 | priv->mc_flags = 0; | |
639 | ||
640 | /* configure rx buffer size */ | |
641 | /* NOTE: vendor driver had dead code here to enable early tx/rx */ | |
642 | iowrite32(Cfg1_Rcv64K, port_base + Config1); | |
643 | ||
644 | _sc92031_phy_reset(dev); | |
645 | _sc92031_check_media(dev); | |
646 | ||
647 | /* calculate rx fifo overflow */ | |
648 | priv->rx_value = 0; | |
649 | ||
650 | /* enable PM */ | |
651 | iowrite32(priv->pm_config, port_base + PMConfig); | |
652 | ||
653 | /* clear intr register */ | |
654 | ioread32(port_base + IntrStatus); | |
655 | } | |
656 | ||
657 | static void _sc92031_tx_tasklet(struct net_device *dev) | |
658 | { | |
659 | struct sc92031_priv *priv = netdev_priv(dev); | |
660 | void __iomem *port_base = priv->port_base; | |
661 | ||
662 | unsigned old_tx_tail; | |
663 | unsigned entry; | |
664 | u32 tx_status; | |
665 | ||
666 | old_tx_tail = priv->tx_tail; | |
667 | while (priv->tx_head - priv->tx_tail > 0) { | |
668 | entry = priv->tx_tail % NUM_TX_DESC; | |
669 | tx_status = ioread32(port_base + TxStatus0 + entry * 4); | |
670 | ||
671 | if (!(tx_status & (TxStatOK | TxUnderrun | TxAborted))) | |
672 | break; | |
673 | ||
674 | priv->tx_tail++; | |
675 | ||
676 | if (tx_status & TxStatOK) { | |
9c28eaea SH |
677 | dev->stats.tx_bytes += tx_status & 0x1fff; |
678 | dev->stats.tx_packets++; | |
bf345707 | 679 | /* Note: TxCarrierLost is always asserted at 100mbps. */ |
9c28eaea | 680 | dev->stats.collisions += (tx_status >> 22) & 0xf; |
bf345707 CEB |
681 | } |
682 | ||
683 | if (tx_status & (TxOutOfWindow | TxAborted)) { | |
9c28eaea | 684 | dev->stats.tx_errors++; |
bf345707 CEB |
685 | |
686 | if (tx_status & TxAborted) | |
9c28eaea | 687 | dev->stats.tx_aborted_errors++; |
bf345707 CEB |
688 | |
689 | if (tx_status & TxCarrierLost) | |
9c28eaea | 690 | dev->stats.tx_carrier_errors++; |
bf345707 CEB |
691 | |
692 | if (tx_status & TxOutOfWindow) | |
9c28eaea | 693 | dev->stats.tx_window_errors++; |
bf345707 CEB |
694 | } |
695 | ||
696 | if (tx_status & TxUnderrun) | |
9c28eaea | 697 | dev->stats.tx_fifo_errors++; |
bf345707 CEB |
698 | } |
699 | ||
700 | if (priv->tx_tail != old_tx_tail) | |
701 | if (netif_queue_stopped(dev)) | |
702 | netif_wake_queue(dev); | |
703 | } | |
704 | ||
9c28eaea SH |
705 | static void _sc92031_rx_tasklet_error(struct net_device *dev, |
706 | u32 rx_status, unsigned rx_size) | |
bf345707 CEB |
707 | { |
708 | if(rx_size > (MAX_ETH_FRAME_SIZE + 4) || rx_size < 16) { | |
9c28eaea SH |
709 | dev->stats.rx_errors++; |
710 | dev->stats.rx_length_errors++; | |
bf345707 CEB |
711 | } |
712 | ||
713 | if (!(rx_status & RxStatesOK)) { | |
9c28eaea | 714 | dev->stats.rx_errors++; |
bf345707 CEB |
715 | |
716 | if (rx_status & (RxHugeFrame | RxSmallFrame)) | |
9c28eaea | 717 | dev->stats.rx_length_errors++; |
bf345707 CEB |
718 | |
719 | if (rx_status & RxBadAlign) | |
9c28eaea | 720 | dev->stats.rx_frame_errors++; |
bf345707 CEB |
721 | |
722 | if (!(rx_status & RxCRCOK)) | |
9c28eaea SH |
723 | dev->stats.rx_crc_errors++; |
724 | } else { | |
725 | struct sc92031_priv *priv = netdev_priv(dev); | |
bf345707 | 726 | priv->rx_loss++; |
9c28eaea | 727 | } |
bf345707 CEB |
728 | } |
729 | ||
730 | static void _sc92031_rx_tasklet(struct net_device *dev) | |
731 | { | |
732 | struct sc92031_priv *priv = netdev_priv(dev); | |
733 | void __iomem *port_base = priv->port_base; | |
734 | ||
735 | dma_addr_t rx_ring_head; | |
736 | unsigned rx_len; | |
737 | unsigned rx_ring_offset; | |
738 | void *rx_ring = priv->rx_ring; | |
739 | ||
740 | rx_ring_head = ioread32(port_base + RxBufWPtr); | |
741 | rmb(); | |
742 | ||
743 | /* rx_ring_head is only 17 bits in the RxBufWPtr register. | |
744 | * we need to change it to 32 bits physical address | |
745 | */ | |
746 | rx_ring_head &= (dma_addr_t)(RX_BUF_LEN - 1); | |
747 | rx_ring_head |= priv->rx_ring_dma_addr & ~(dma_addr_t)(RX_BUF_LEN - 1); | |
748 | if (rx_ring_head < priv->rx_ring_dma_addr) | |
749 | rx_ring_head += RX_BUF_LEN; | |
750 | ||
751 | if (rx_ring_head >= priv->rx_ring_tail) | |
752 | rx_len = rx_ring_head - priv->rx_ring_tail; | |
753 | else | |
754 | rx_len = RX_BUF_LEN - (priv->rx_ring_tail - rx_ring_head); | |
755 | ||
756 | if (!rx_len) | |
757 | return; | |
758 | ||
759 | if (unlikely(rx_len > RX_BUF_LEN)) { | |
760 | if (printk_ratelimit()) | |
761 | printk(KERN_ERR "%s: rx packets length > rx buffer\n", | |
762 | dev->name); | |
763 | return; | |
764 | } | |
765 | ||
766 | rx_ring_offset = (priv->rx_ring_tail - priv->rx_ring_dma_addr) % RX_BUF_LEN; | |
767 | ||
768 | while (rx_len) { | |
769 | u32 rx_status; | |
770 | unsigned rx_size, rx_size_align, pkt_size; | |
771 | struct sk_buff *skb; | |
772 | ||
773 | rx_status = le32_to_cpup((__le32 *)(rx_ring + rx_ring_offset)); | |
774 | rmb(); | |
775 | ||
776 | rx_size = rx_status >> 20; | |
777 | rx_size_align = (rx_size + 3) & ~3; // for 4 bytes aligned | |
778 | pkt_size = rx_size - 4; // Omit the four octet CRC from the length. | |
779 | ||
780 | rx_ring_offset = (rx_ring_offset + 4) % RX_BUF_LEN; | |
781 | ||
782 | if (unlikely(rx_status == 0 | |
783 | || rx_size > (MAX_ETH_FRAME_SIZE + 4) | |
784 | || rx_size < 16 | |
785 | || !(rx_status & RxStatesOK))) { | |
9c28eaea | 786 | _sc92031_rx_tasklet_error(dev, rx_status, rx_size); |
bf345707 CEB |
787 | break; |
788 | } | |
789 | ||
790 | if (unlikely(rx_size_align + 4 > rx_len)) { | |
791 | if (printk_ratelimit()) | |
792 | printk(KERN_ERR "%s: rx_len is too small\n", dev->name); | |
793 | break; | |
794 | } | |
795 | ||
796 | rx_len -= rx_size_align + 4; | |
797 | ||
2723b019 | 798 | skb = netdev_alloc_skb(dev, pkt_size + NET_IP_ALIGN); |
bf345707 CEB |
799 | if (unlikely(!skb)) { |
800 | if (printk_ratelimit()) | |
801 | printk(KERN_ERR "%s: Couldn't allocate a skb_buff for a packet of size %u\n", | |
802 | dev->name, pkt_size); | |
803 | goto next; | |
804 | } | |
805 | ||
806 | skb_reserve(skb, NET_IP_ALIGN); | |
807 | ||
808 | if ((rx_ring_offset + pkt_size) > RX_BUF_LEN) { | |
809 | memcpy(skb_put(skb, RX_BUF_LEN - rx_ring_offset), | |
810 | rx_ring + rx_ring_offset, RX_BUF_LEN - rx_ring_offset); | |
811 | memcpy(skb_put(skb, pkt_size - (RX_BUF_LEN - rx_ring_offset)), | |
812 | rx_ring, pkt_size - (RX_BUF_LEN - rx_ring_offset)); | |
813 | } else { | |
814 | memcpy(skb_put(skb, pkt_size), rx_ring + rx_ring_offset, pkt_size); | |
815 | } | |
816 | ||
bf345707 | 817 | skb->protocol = eth_type_trans(skb, dev); |
bf345707 CEB |
818 | netif_rx(skb); |
819 | ||
9c28eaea SH |
820 | dev->stats.rx_bytes += pkt_size; |
821 | dev->stats.rx_packets++; | |
bf345707 CEB |
822 | |
823 | if (rx_status & Rx_Multicast) | |
9c28eaea | 824 | dev->stats.multicast++; |
bf345707 CEB |
825 | |
826 | next: | |
827 | rx_ring_offset = (rx_ring_offset + rx_size_align) % RX_BUF_LEN; | |
828 | } | |
829 | mb(); | |
830 | ||
831 | priv->rx_ring_tail = rx_ring_head; | |
832 | iowrite32(priv->rx_ring_tail, port_base + RxBufRPtr); | |
833 | } | |
834 | ||
835 | static void _sc92031_link_tasklet(struct net_device *dev) | |
836 | { | |
bf345707 CEB |
837 | if (_sc92031_check_media(dev)) |
838 | netif_wake_queue(dev); | |
839 | else { | |
840 | netif_stop_queue(dev); | |
9c28eaea | 841 | dev->stats.tx_carrier_errors++; |
bf345707 CEB |
842 | } |
843 | } | |
844 | ||
845 | static void sc92031_tasklet(unsigned long data) | |
846 | { | |
847 | struct net_device *dev = (struct net_device *)data; | |
848 | struct sc92031_priv *priv = netdev_priv(dev); | |
849 | void __iomem *port_base = priv->port_base; | |
850 | u32 intr_status, intr_mask; | |
851 | ||
852 | intr_status = priv->intr_status; | |
853 | ||
854 | spin_lock(&priv->lock); | |
855 | ||
856 | if (unlikely(!netif_running(dev))) | |
857 | goto out; | |
858 | ||
859 | if (intr_status & TxOK) | |
860 | _sc92031_tx_tasklet(dev); | |
861 | ||
862 | if (intr_status & RxOK) | |
863 | _sc92031_rx_tasklet(dev); | |
864 | ||
865 | if (intr_status & RxOverflow) | |
9c28eaea | 866 | dev->stats.rx_errors++; |
bf345707 CEB |
867 | |
868 | if (intr_status & TimeOut) { | |
9c28eaea SH |
869 | dev->stats.rx_errors++; |
870 | dev->stats.rx_length_errors++; | |
bf345707 CEB |
871 | } |
872 | ||
873 | if (intr_status & (LinkFail | LinkOK)) | |
874 | _sc92031_link_tasklet(dev); | |
875 | ||
876 | out: | |
877 | intr_mask = atomic_read(&priv->intr_mask); | |
878 | rmb(); | |
879 | ||
880 | iowrite32(intr_mask, port_base + IntrMask); | |
881 | mmiowb(); | |
882 | ||
883 | spin_unlock(&priv->lock); | |
884 | } | |
885 | ||
886 | static irqreturn_t sc92031_interrupt(int irq, void *dev_id) | |
887 | { | |
888 | struct net_device *dev = dev_id; | |
889 | struct sc92031_priv *priv = netdev_priv(dev); | |
890 | void __iomem *port_base = priv->port_base; | |
891 | u32 intr_status, intr_mask; | |
892 | ||
893 | /* mask interrupts before clearing IntrStatus */ | |
894 | iowrite32(0, port_base + IntrMask); | |
895 | _sc92031_dummy_read(port_base); | |
896 | ||
897 | intr_status = ioread32(port_base + IntrStatus); | |
898 | if (unlikely(intr_status == 0xffffffff)) | |
899 | return IRQ_NONE; // hardware has gone missing | |
900 | ||
901 | intr_status &= IntrBits; | |
902 | if (!intr_status) | |
903 | goto out_none; | |
904 | ||
905 | priv->intr_status = intr_status; | |
906 | tasklet_schedule(&priv->tasklet); | |
907 | ||
908 | return IRQ_HANDLED; | |
909 | ||
910 | out_none: | |
911 | intr_mask = atomic_read(&priv->intr_mask); | |
912 | rmb(); | |
913 | ||
914 | iowrite32(intr_mask, port_base + IntrMask); | |
915 | mmiowb(); | |
916 | ||
917 | return IRQ_NONE; | |
918 | } | |
919 | ||
920 | static struct net_device_stats *sc92031_get_stats(struct net_device *dev) | |
921 | { | |
922 | struct sc92031_priv *priv = netdev_priv(dev); | |
923 | void __iomem *port_base = priv->port_base; | |
924 | ||
925 | // FIXME I do not understand what is this trying to do. | |
926 | if (netif_running(dev)) { | |
927 | int temp; | |
928 | ||
929 | spin_lock_bh(&priv->lock); | |
930 | ||
931 | /* Update the error count. */ | |
932 | temp = (ioread32(port_base + RxStatus0) >> 16) & 0xffff; | |
933 | ||
934 | if (temp == 0xffff) { | |
935 | priv->rx_value += temp; | |
9c28eaea SH |
936 | dev->stats.rx_fifo_errors = priv->rx_value; |
937 | } else | |
938 | dev->stats.rx_fifo_errors = temp + priv->rx_value; | |
bf345707 CEB |
939 | |
940 | spin_unlock_bh(&priv->lock); | |
941 | } | |
942 | ||
9c28eaea | 943 | return &dev->stats; |
bf345707 CEB |
944 | } |
945 | ||
946 | static int sc92031_start_xmit(struct sk_buff *skb, struct net_device *dev) | |
947 | { | |
bf345707 CEB |
948 | struct sc92031_priv *priv = netdev_priv(dev); |
949 | void __iomem *port_base = priv->port_base; | |
bf345707 CEB |
950 | unsigned len; |
951 | unsigned entry; | |
952 | u32 tx_status; | |
953 | ||
954 | if (unlikely(skb->len > TX_BUF_SIZE)) { | |
9c28eaea | 955 | dev->stats.tx_dropped++; |
bf345707 CEB |
956 | goto out; |
957 | } | |
958 | ||
699784b7 | 959 | spin_lock(&priv->lock); |
bf345707 CEB |
960 | |
961 | if (unlikely(!netif_carrier_ok(dev))) { | |
9c28eaea | 962 | dev->stats.tx_dropped++; |
bf345707 CEB |
963 | goto out_unlock; |
964 | } | |
965 | ||
966 | BUG_ON(priv->tx_head - priv->tx_tail >= NUM_TX_DESC); | |
967 | ||
968 | entry = priv->tx_head++ % NUM_TX_DESC; | |
969 | ||
970 | skb_copy_and_csum_dev(skb, priv->tx_bufs + entry * TX_BUF_SIZE); | |
971 | ||
972 | len = skb->len; | |
6f94f709 | 973 | if (len < ETH_ZLEN) { |
5a0a92e6 GR |
974 | memset(priv->tx_bufs + entry * TX_BUF_SIZE + len, |
975 | 0, ETH_ZLEN - len); | |
976 | len = ETH_ZLEN; | |
977 | } | |
bf345707 CEB |
978 | |
979 | wmb(); | |
980 | ||
981 | if (len < 100) | |
982 | tx_status = len; | |
983 | else if (len < 300) | |
984 | tx_status = 0x30000 | len; | |
985 | else | |
986 | tx_status = 0x50000 | len; | |
987 | ||
988 | iowrite32(priv->tx_bufs_dma_addr + entry * TX_BUF_SIZE, | |
989 | port_base + TxAddr0 + entry * 4); | |
990 | iowrite32(tx_status, port_base + TxStatus0 + entry * 4); | |
991 | mmiowb(); | |
992 | ||
993 | dev->trans_start = jiffies; | |
994 | ||
995 | if (priv->tx_head - priv->tx_tail >= NUM_TX_DESC) | |
996 | netif_stop_queue(dev); | |
997 | ||
998 | out_unlock: | |
699784b7 | 999 | spin_unlock(&priv->lock); |
bf345707 CEB |
1000 | |
1001 | out: | |
1002 | dev_kfree_skb(skb); | |
1003 | ||
26a17b7b | 1004 | return NETDEV_TX_OK; |
bf345707 CEB |
1005 | } |
1006 | ||
1007 | static int sc92031_open(struct net_device *dev) | |
1008 | { | |
1009 | int err; | |
1010 | struct sc92031_priv *priv = netdev_priv(dev); | |
1011 | struct pci_dev *pdev = priv->pdev; | |
1012 | ||
1013 | priv->rx_ring = pci_alloc_consistent(pdev, RX_BUF_LEN, | |
1014 | &priv->rx_ring_dma_addr); | |
1015 | if (unlikely(!priv->rx_ring)) { | |
1016 | err = -ENOMEM; | |
1017 | goto out_alloc_rx_ring; | |
1018 | } | |
1019 | ||
1020 | priv->tx_bufs = pci_alloc_consistent(pdev, TX_BUF_TOT_LEN, | |
1021 | &priv->tx_bufs_dma_addr); | |
1022 | if (unlikely(!priv->tx_bufs)) { | |
1023 | err = -ENOMEM; | |
1024 | goto out_alloc_tx_bufs; | |
1025 | } | |
1026 | priv->tx_head = priv->tx_tail = 0; | |
1027 | ||
1028 | err = request_irq(pdev->irq, sc92031_interrupt, | |
2db6346f | 1029 | IRQF_SHARED, dev->name, dev); |
bf345707 CEB |
1030 | if (unlikely(err < 0)) |
1031 | goto out_request_irq; | |
1032 | ||
1033 | priv->pm_config = 0; | |
1034 | ||
1035 | /* Interrupts already disabled by sc92031_stop or sc92031_probe */ | |
699784b7 | 1036 | spin_lock_bh(&priv->lock); |
bf345707 CEB |
1037 | |
1038 | _sc92031_reset(dev); | |
1039 | mmiowb(); | |
1040 | ||
699784b7 | 1041 | spin_unlock_bh(&priv->lock); |
bf345707 CEB |
1042 | sc92031_enable_interrupts(dev); |
1043 | ||
1044 | if (netif_carrier_ok(dev)) | |
1045 | netif_start_queue(dev); | |
1046 | else | |
1047 | netif_tx_disable(dev); | |
1048 | ||
1049 | return 0; | |
1050 | ||
1051 | out_request_irq: | |
1052 | pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs, | |
1053 | priv->tx_bufs_dma_addr); | |
1054 | out_alloc_tx_bufs: | |
1055 | pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring, | |
1056 | priv->rx_ring_dma_addr); | |
1057 | out_alloc_rx_ring: | |
1058 | return err; | |
1059 | } | |
1060 | ||
1061 | static int sc92031_stop(struct net_device *dev) | |
1062 | { | |
1063 | struct sc92031_priv *priv = netdev_priv(dev); | |
1064 | struct pci_dev *pdev = priv->pdev; | |
1065 | ||
1066 | netif_tx_disable(dev); | |
1067 | ||
1068 | /* Disable interrupts, stop Tx and Rx. */ | |
1069 | sc92031_disable_interrupts(dev); | |
1070 | ||
699784b7 | 1071 | spin_lock_bh(&priv->lock); |
bf345707 CEB |
1072 | |
1073 | _sc92031_disable_tx_rx(dev); | |
1074 | _sc92031_tx_clear(dev); | |
1075 | mmiowb(); | |
1076 | ||
699784b7 | 1077 | spin_unlock_bh(&priv->lock); |
bf345707 CEB |
1078 | |
1079 | free_irq(pdev->irq, dev); | |
1080 | pci_free_consistent(pdev, TX_BUF_TOT_LEN, priv->tx_bufs, | |
1081 | priv->tx_bufs_dma_addr); | |
1082 | pci_free_consistent(pdev, RX_BUF_LEN, priv->rx_ring, | |
1083 | priv->rx_ring_dma_addr); | |
1084 | ||
1085 | return 0; | |
1086 | } | |
1087 | ||
1088 | static void sc92031_set_multicast_list(struct net_device *dev) | |
1089 | { | |
1090 | struct sc92031_priv *priv = netdev_priv(dev); | |
1091 | ||
1092 | spin_lock_bh(&priv->lock); | |
1093 | ||
1094 | _sc92031_set_mar(dev); | |
1095 | _sc92031_set_rx_config(dev); | |
1096 | mmiowb(); | |
1097 | ||
1098 | spin_unlock_bh(&priv->lock); | |
1099 | } | |
1100 | ||
1101 | static void sc92031_tx_timeout(struct net_device *dev) | |
1102 | { | |
1103 | struct sc92031_priv *priv = netdev_priv(dev); | |
1104 | ||
1105 | /* Disable interrupts by clearing the interrupt mask.*/ | |
1106 | sc92031_disable_interrupts(dev); | |
1107 | ||
1108 | spin_lock(&priv->lock); | |
1109 | ||
1110 | priv->tx_timeouts++; | |
1111 | ||
1112 | _sc92031_reset(dev); | |
1113 | mmiowb(); | |
1114 | ||
1115 | spin_unlock(&priv->lock); | |
1116 | ||
1117 | /* enable interrupts */ | |
1118 | sc92031_enable_interrupts(dev); | |
1119 | ||
1120 | if (netif_carrier_ok(dev)) | |
1121 | netif_wake_queue(dev); | |
1122 | } | |
1123 | ||
1124 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1125 | static void sc92031_poll_controller(struct net_device *dev) | |
1126 | { | |
1127 | disable_irq(dev->irq); | |
1128 | if (sc92031_interrupt(dev->irq, dev) != IRQ_NONE) | |
1129 | sc92031_tasklet((unsigned long)dev); | |
1130 | enable_irq(dev->irq); | |
1131 | } | |
1132 | #endif | |
1133 | ||
1134 | static int sc92031_ethtool_get_settings(struct net_device *dev, | |
1135 | struct ethtool_cmd *cmd) | |
1136 | { | |
1137 | struct sc92031_priv *priv = netdev_priv(dev); | |
1138 | void __iomem *port_base = priv->port_base; | |
1139 | u8 phy_address; | |
1140 | u32 phy_ctrl; | |
1141 | u16 output_status; | |
1142 | ||
1143 | spin_lock_bh(&priv->lock); | |
1144 | ||
1145 | phy_address = ioread32(port_base + Miicmd1) >> 27; | |
1146 | phy_ctrl = ioread32(port_base + PhyCtrl); | |
1147 | ||
1148 | output_status = _sc92031_mii_read(port_base, MII_OutputStatus); | |
1149 | _sc92031_mii_scan(port_base); | |
1150 | mmiowb(); | |
1151 | ||
1152 | spin_unlock_bh(&priv->lock); | |
1153 | ||
1154 | cmd->supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | |
1155 | | SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | |
1156 | | SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII; | |
1157 | ||
1158 | cmd->advertising = ADVERTISED_TP | ADVERTISED_MII; | |
1159 | ||
1160 | if ((phy_ctrl & (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10)) | |
1161 | == (PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10)) | |
1162 | cmd->advertising |= ADVERTISED_Autoneg; | |
1163 | ||
1164 | if ((phy_ctrl & PhyCtrlSpd10) == PhyCtrlSpd10) | |
1165 | cmd->advertising |= ADVERTISED_10baseT_Half; | |
1166 | ||
1167 | if ((phy_ctrl & (PhyCtrlSpd10 | PhyCtrlDux)) | |
1168 | == (PhyCtrlSpd10 | PhyCtrlDux)) | |
1169 | cmd->advertising |= ADVERTISED_10baseT_Full; | |
1170 | ||
1171 | if ((phy_ctrl & PhyCtrlSpd100) == PhyCtrlSpd100) | |
1172 | cmd->advertising |= ADVERTISED_100baseT_Half; | |
1173 | ||
1174 | if ((phy_ctrl & (PhyCtrlSpd100 | PhyCtrlDux)) | |
1175 | == (PhyCtrlSpd100 | PhyCtrlDux)) | |
1176 | cmd->advertising |= ADVERTISED_100baseT_Full; | |
1177 | ||
1178 | if (phy_ctrl & PhyCtrlAne) | |
1179 | cmd->advertising |= ADVERTISED_Autoneg; | |
1180 | ||
1181 | cmd->speed = (output_status & 0x2) ? SPEED_100 : SPEED_10; | |
1182 | cmd->duplex = (output_status & 0x4) ? DUPLEX_FULL : DUPLEX_HALF; | |
1183 | cmd->port = PORT_MII; | |
1184 | cmd->phy_address = phy_address; | |
1185 | cmd->transceiver = XCVR_INTERNAL; | |
1186 | cmd->autoneg = (phy_ctrl & PhyCtrlAne) ? AUTONEG_ENABLE : AUTONEG_DISABLE; | |
1187 | ||
1188 | return 0; | |
1189 | } | |
1190 | ||
1191 | static int sc92031_ethtool_set_settings(struct net_device *dev, | |
1192 | struct ethtool_cmd *cmd) | |
1193 | { | |
1194 | struct sc92031_priv *priv = netdev_priv(dev); | |
1195 | void __iomem *port_base = priv->port_base; | |
1196 | u32 phy_ctrl; | |
1197 | u32 old_phy_ctrl; | |
1198 | ||
1199 | if (!(cmd->speed == SPEED_10 || cmd->speed == SPEED_100)) | |
1200 | return -EINVAL; | |
1201 | if (!(cmd->duplex == DUPLEX_HALF || cmd->duplex == DUPLEX_FULL)) | |
1202 | return -EINVAL; | |
1203 | if (!(cmd->port == PORT_MII)) | |
1204 | return -EINVAL; | |
1205 | if (!(cmd->phy_address == 0x1f)) | |
1206 | return -EINVAL; | |
1207 | if (!(cmd->transceiver == XCVR_INTERNAL)) | |
1208 | return -EINVAL; | |
1209 | if (!(cmd->autoneg == AUTONEG_DISABLE || cmd->autoneg == AUTONEG_ENABLE)) | |
1210 | return -EINVAL; | |
1211 | ||
1212 | if (cmd->autoneg == AUTONEG_ENABLE) { | |
1213 | if (!(cmd->advertising & (ADVERTISED_Autoneg | |
1214 | | ADVERTISED_100baseT_Full | |
1215 | | ADVERTISED_100baseT_Half | |
1216 | | ADVERTISED_10baseT_Full | |
1217 | | ADVERTISED_10baseT_Half))) | |
1218 | return -EINVAL; | |
1219 | ||
1220 | phy_ctrl = PhyCtrlAne; | |
1221 | ||
1222 | // FIXME: I'm not sure what the original code was trying to do | |
1223 | if (cmd->advertising & ADVERTISED_Autoneg) | |
1224 | phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100 | PhyCtrlSpd10; | |
1225 | if (cmd->advertising & ADVERTISED_100baseT_Full) | |
1226 | phy_ctrl |= PhyCtrlDux | PhyCtrlSpd100; | |
1227 | if (cmd->advertising & ADVERTISED_100baseT_Half) | |
1228 | phy_ctrl |= PhyCtrlSpd100; | |
1229 | if (cmd->advertising & ADVERTISED_10baseT_Full) | |
1230 | phy_ctrl |= PhyCtrlSpd10 | PhyCtrlDux; | |
1231 | if (cmd->advertising & ADVERTISED_10baseT_Half) | |
1232 | phy_ctrl |= PhyCtrlSpd10; | |
1233 | } else { | |
1234 | // FIXME: Whole branch guessed | |
1235 | phy_ctrl = 0; | |
1236 | ||
1237 | if (cmd->speed == SPEED_10) | |
1238 | phy_ctrl |= PhyCtrlSpd10; | |
1239 | else /* cmd->speed == SPEED_100 */ | |
1240 | phy_ctrl |= PhyCtrlSpd100; | |
1241 | ||
1242 | if (cmd->duplex == DUPLEX_FULL) | |
1243 | phy_ctrl |= PhyCtrlDux; | |
1244 | } | |
1245 | ||
1246 | spin_lock_bh(&priv->lock); | |
1247 | ||
1248 | old_phy_ctrl = ioread32(port_base + PhyCtrl); | |
1249 | phy_ctrl |= old_phy_ctrl & ~(PhyCtrlAne | PhyCtrlDux | |
1250 | | PhyCtrlSpd100 | PhyCtrlSpd10); | |
1251 | if (phy_ctrl != old_phy_ctrl) | |
1252 | iowrite32(phy_ctrl, port_base + PhyCtrl); | |
1253 | ||
1254 | spin_unlock_bh(&priv->lock); | |
1255 | ||
1256 | return 0; | |
1257 | } | |
1258 | ||
1259 | static void sc92031_ethtool_get_drvinfo(struct net_device *dev, | |
1260 | struct ethtool_drvinfo *drvinfo) | |
1261 | { | |
1262 | struct sc92031_priv *priv = netdev_priv(dev); | |
1263 | struct pci_dev *pdev = priv->pdev; | |
1264 | ||
1265 | strcpy(drvinfo->driver, SC92031_NAME); | |
bf345707 CEB |
1266 | strcpy(drvinfo->bus_info, pci_name(pdev)); |
1267 | } | |
1268 | ||
1269 | static void sc92031_ethtool_get_wol(struct net_device *dev, | |
1270 | struct ethtool_wolinfo *wolinfo) | |
1271 | { | |
1272 | struct sc92031_priv *priv = netdev_priv(dev); | |
1273 | void __iomem *port_base = priv->port_base; | |
1274 | u32 pm_config; | |
1275 | ||
1276 | spin_lock_bh(&priv->lock); | |
1277 | pm_config = ioread32(port_base + PMConfig); | |
1278 | spin_unlock_bh(&priv->lock); | |
1279 | ||
1280 | // FIXME: Guessed | |
1281 | wolinfo->supported = WAKE_PHY | WAKE_MAGIC | |
1282 | | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; | |
1283 | wolinfo->wolopts = 0; | |
1284 | ||
1285 | if (pm_config & PM_LinkUp) | |
1286 | wolinfo->wolopts |= WAKE_PHY; | |
1287 | ||
1288 | if (pm_config & PM_Magic) | |
1289 | wolinfo->wolopts |= WAKE_MAGIC; | |
1290 | ||
1291 | if (pm_config & PM_WakeUp) | |
1292 | // FIXME: Guessed | |
1293 | wolinfo->wolopts |= WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; | |
1294 | } | |
1295 | ||
1296 | static int sc92031_ethtool_set_wol(struct net_device *dev, | |
1297 | struct ethtool_wolinfo *wolinfo) | |
1298 | { | |
1299 | struct sc92031_priv *priv = netdev_priv(dev); | |
1300 | void __iomem *port_base = priv->port_base; | |
1301 | u32 pm_config; | |
1302 | ||
1303 | spin_lock_bh(&priv->lock); | |
1304 | ||
1305 | pm_config = ioread32(port_base + PMConfig) | |
1306 | & ~(PM_LinkUp | PM_Magic | PM_WakeUp); | |
1307 | ||
1308 | if (wolinfo->wolopts & WAKE_PHY) | |
1309 | pm_config |= PM_LinkUp; | |
1310 | ||
1311 | if (wolinfo->wolopts & WAKE_MAGIC) | |
1312 | pm_config |= PM_Magic; | |
1313 | ||
1314 | // FIXME: Guessed | |
1315 | if (wolinfo->wolopts & (WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)) | |
1316 | pm_config |= PM_WakeUp; | |
1317 | ||
1318 | priv->pm_config = pm_config; | |
1319 | iowrite32(pm_config, port_base + PMConfig); | |
1320 | mmiowb(); | |
1321 | ||
1322 | spin_unlock_bh(&priv->lock); | |
1323 | ||
1324 | return 0; | |
1325 | } | |
1326 | ||
1327 | static int sc92031_ethtool_nway_reset(struct net_device *dev) | |
1328 | { | |
1329 | int err = 0; | |
1330 | struct sc92031_priv *priv = netdev_priv(dev); | |
1331 | void __iomem *port_base = priv->port_base; | |
1332 | u16 bmcr; | |
1333 | ||
1334 | spin_lock_bh(&priv->lock); | |
1335 | ||
1336 | bmcr = _sc92031_mii_read(port_base, MII_BMCR); | |
1337 | if (!(bmcr & BMCR_ANENABLE)) { | |
1338 | err = -EINVAL; | |
1339 | goto out; | |
1340 | } | |
1341 | ||
1342 | _sc92031_mii_write(port_base, MII_BMCR, bmcr | BMCR_ANRESTART); | |
1343 | ||
1344 | out: | |
1345 | _sc92031_mii_scan(port_base); | |
1346 | mmiowb(); | |
1347 | ||
1348 | spin_unlock_bh(&priv->lock); | |
1349 | ||
1350 | return err; | |
1351 | } | |
1352 | ||
1353 | static const char sc92031_ethtool_stats_strings[SILAN_STATS_NUM][ETH_GSTRING_LEN] = { | |
1354 | "tx_timeout", | |
1355 | "rx_loss", | |
1356 | }; | |
1357 | ||
1358 | static void sc92031_ethtool_get_strings(struct net_device *dev, | |
1359 | u32 stringset, u8 *data) | |
1360 | { | |
1361 | if (stringset == ETH_SS_STATS) | |
1362 | memcpy(data, sc92031_ethtool_stats_strings, | |
1363 | SILAN_STATS_NUM * ETH_GSTRING_LEN); | |
1364 | } | |
1365 | ||
b9f2c044 | 1366 | static int sc92031_ethtool_get_sset_count(struct net_device *dev, int sset) |
bf345707 | 1367 | { |
b9f2c044 JG |
1368 | switch (sset) { |
1369 | case ETH_SS_STATS: | |
1370 | return SILAN_STATS_NUM; | |
1371 | default: | |
1372 | return -EOPNOTSUPP; | |
1373 | } | |
bf345707 CEB |
1374 | } |
1375 | ||
1376 | static void sc92031_ethtool_get_ethtool_stats(struct net_device *dev, | |
1377 | struct ethtool_stats *stats, u64 *data) | |
1378 | { | |
1379 | struct sc92031_priv *priv = netdev_priv(dev); | |
1380 | ||
1381 | spin_lock_bh(&priv->lock); | |
1382 | data[0] = priv->tx_timeouts; | |
1383 | data[1] = priv->rx_loss; | |
1384 | spin_unlock_bh(&priv->lock); | |
1385 | } | |
1386 | ||
974acda0 | 1387 | static const struct ethtool_ops sc92031_ethtool_ops = { |
bf345707 CEB |
1388 | .get_settings = sc92031_ethtool_get_settings, |
1389 | .set_settings = sc92031_ethtool_set_settings, | |
1390 | .get_drvinfo = sc92031_ethtool_get_drvinfo, | |
1391 | .get_wol = sc92031_ethtool_get_wol, | |
1392 | .set_wol = sc92031_ethtool_set_wol, | |
1393 | .nway_reset = sc92031_ethtool_nway_reset, | |
1394 | .get_link = ethtool_op_get_link, | |
bf345707 | 1395 | .get_strings = sc92031_ethtool_get_strings, |
b9f2c044 | 1396 | .get_sset_count = sc92031_ethtool_get_sset_count, |
bf345707 | 1397 | .get_ethtool_stats = sc92031_ethtool_get_ethtool_stats, |
bf345707 CEB |
1398 | }; |
1399 | ||
974acda0 SH |
1400 | |
1401 | static const struct net_device_ops sc92031_netdev_ops = { | |
1402 | .ndo_get_stats = sc92031_get_stats, | |
1403 | .ndo_start_xmit = sc92031_start_xmit, | |
1404 | .ndo_open = sc92031_open, | |
1405 | .ndo_stop = sc92031_stop, | |
1406 | .ndo_set_multicast_list = sc92031_set_multicast_list, | |
1407 | .ndo_change_mtu = eth_change_mtu, | |
1408 | .ndo_validate_addr = eth_validate_addr, | |
fe96aaa1 | 1409 | .ndo_set_mac_address = eth_mac_addr, |
974acda0 SH |
1410 | .ndo_tx_timeout = sc92031_tx_timeout, |
1411 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
1412 | .ndo_poll_controller = sc92031_poll_controller, | |
1413 | #endif | |
1414 | }; | |
1415 | ||
bf345707 CEB |
1416 | static int __devinit sc92031_probe(struct pci_dev *pdev, |
1417 | const struct pci_device_id *id) | |
1418 | { | |
1419 | int err; | |
1420 | void __iomem* port_base; | |
1421 | struct net_device *dev; | |
1422 | struct sc92031_priv *priv; | |
1423 | u32 mac0, mac1; | |
eb5c8bc1 | 1424 | unsigned long base_addr; |
bf345707 CEB |
1425 | |
1426 | err = pci_enable_device(pdev); | |
1427 | if (unlikely(err < 0)) | |
1428 | goto out_enable_device; | |
1429 | ||
1430 | pci_set_master(pdev); | |
1431 | ||
1432 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1433 | if (unlikely(err < 0)) | |
1434 | goto out_set_dma_mask; | |
1435 | ||
1436 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1437 | if (unlikely(err < 0)) | |
1438 | goto out_set_dma_mask; | |
1439 | ||
1440 | err = pci_request_regions(pdev, SC92031_NAME); | |
1441 | if (unlikely(err < 0)) | |
1442 | goto out_request_regions; | |
1443 | ||
1444 | port_base = pci_iomap(pdev, SC92031_USE_BAR, 0); | |
1445 | if (unlikely(!port_base)) { | |
1446 | err = -EIO; | |
1447 | goto out_iomap; | |
1448 | } | |
1449 | ||
1450 | dev = alloc_etherdev(sizeof(struct sc92031_priv)); | |
1451 | if (unlikely(!dev)) { | |
1452 | err = -ENOMEM; | |
1453 | goto out_alloc_etherdev; | |
1454 | } | |
1455 | ||
1456 | pci_set_drvdata(pdev, dev); | |
5a81f143 | 1457 | SET_NETDEV_DEV(dev, &pdev->dev); |
bf345707 CEB |
1458 | |
1459 | #if SC92031_USE_BAR == 0 | |
1460 | dev->mem_start = pci_resource_start(pdev, SC92031_USE_BAR); | |
1461 | dev->mem_end = pci_resource_end(pdev, SC92031_USE_BAR); | |
1462 | #elif SC92031_USE_BAR == 1 | |
1463 | dev->base_addr = pci_resource_start(pdev, SC92031_USE_BAR); | |
1464 | #endif | |
1465 | dev->irq = pdev->irq; | |
1466 | ||
1467 | /* faked with skb_copy_and_csum_dev */ | |
1468 | dev->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA; | |
1469 | ||
974acda0 | 1470 | dev->netdev_ops = &sc92031_netdev_ops; |
bf345707 | 1471 | dev->watchdog_timeo = TX_TIMEOUT; |
974acda0 | 1472 | dev->ethtool_ops = &sc92031_ethtool_ops; |
bf345707 CEB |
1473 | |
1474 | priv = netdev_priv(dev); | |
1475 | spin_lock_init(&priv->lock); | |
1476 | priv->port_base = port_base; | |
1477 | priv->pdev = pdev; | |
1478 | tasklet_init(&priv->tasklet, sc92031_tasklet, (unsigned long)dev); | |
1479 | /* Fudge tasklet count so the call to sc92031_enable_interrupts at | |
1480 | * sc92031_open will work correctly */ | |
1481 | tasklet_disable_nosync(&priv->tasklet); | |
1482 | ||
1483 | /* PCI PM Wakeup */ | |
1484 | iowrite32((~PM_LongWF & ~PM_LWPTN) | PM_Enable, port_base + PMConfig); | |
1485 | ||
1486 | mac0 = ioread32(port_base + MAC0); | |
1487 | mac1 = ioread32(port_base + MAC0 + 4); | |
1488 | dev->dev_addr[0] = dev->perm_addr[0] = mac0 >> 24; | |
1489 | dev->dev_addr[1] = dev->perm_addr[1] = mac0 >> 16; | |
1490 | dev->dev_addr[2] = dev->perm_addr[2] = mac0 >> 8; | |
1491 | dev->dev_addr[3] = dev->perm_addr[3] = mac0; | |
1492 | dev->dev_addr[4] = dev->perm_addr[4] = mac1 >> 8; | |
1493 | dev->dev_addr[5] = dev->perm_addr[5] = mac1; | |
1494 | ||
1495 | err = register_netdev(dev); | |
1496 | if (err < 0) | |
1497 | goto out_register_netdev; | |
1498 | ||
eb5c8bc1 CEB |
1499 | #if SC92031_USE_BAR == 0 |
1500 | base_addr = dev->mem_start; | |
1501 | #elif SC92031_USE_BAR == 1 | |
1502 | base_addr = dev->base_addr; | |
1503 | #endif | |
1504 | printk(KERN_INFO "%s: SC92031 at 0x%lx, %pM, IRQ %d\n", dev->name, | |
1505 | base_addr, dev->dev_addr, dev->irq); | |
1506 | ||
bf345707 CEB |
1507 | return 0; |
1508 | ||
1509 | out_register_netdev: | |
1510 | free_netdev(dev); | |
1511 | out_alloc_etherdev: | |
1512 | pci_iounmap(pdev, port_base); | |
1513 | out_iomap: | |
1514 | pci_release_regions(pdev); | |
1515 | out_request_regions: | |
1516 | out_set_dma_mask: | |
1517 | pci_disable_device(pdev); | |
1518 | out_enable_device: | |
1519 | return err; | |
1520 | } | |
1521 | ||
1522 | static void __devexit sc92031_remove(struct pci_dev *pdev) | |
1523 | { | |
1524 | struct net_device *dev = pci_get_drvdata(pdev); | |
1525 | struct sc92031_priv *priv = netdev_priv(dev); | |
1526 | void __iomem* port_base = priv->port_base; | |
1527 | ||
1528 | unregister_netdev(dev); | |
1529 | free_netdev(dev); | |
1530 | pci_iounmap(pdev, port_base); | |
1531 | pci_release_regions(pdev); | |
1532 | pci_disable_device(pdev); | |
1533 | } | |
1534 | ||
1535 | static int sc92031_suspend(struct pci_dev *pdev, pm_message_t state) | |
1536 | { | |
1537 | struct net_device *dev = pci_get_drvdata(pdev); | |
1538 | struct sc92031_priv *priv = netdev_priv(dev); | |
1539 | ||
1540 | pci_save_state(pdev); | |
1541 | ||
1542 | if (!netif_running(dev)) | |
1543 | goto out; | |
1544 | ||
1545 | netif_device_detach(dev); | |
1546 | ||
1547 | /* Disable interrupts, stop Tx and Rx. */ | |
1548 | sc92031_disable_interrupts(dev); | |
1549 | ||
699784b7 | 1550 | spin_lock_bh(&priv->lock); |
bf345707 CEB |
1551 | |
1552 | _sc92031_disable_tx_rx(dev); | |
1553 | _sc92031_tx_clear(dev); | |
1554 | mmiowb(); | |
1555 | ||
699784b7 | 1556 | spin_unlock_bh(&priv->lock); |
bf345707 CEB |
1557 | |
1558 | out: | |
1559 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); | |
1560 | ||
1561 | return 0; | |
1562 | } | |
1563 | ||
1564 | static int sc92031_resume(struct pci_dev *pdev) | |
1565 | { | |
1566 | struct net_device *dev = pci_get_drvdata(pdev); | |
1567 | struct sc92031_priv *priv = netdev_priv(dev); | |
1568 | ||
1569 | pci_restore_state(pdev); | |
1570 | pci_set_power_state(pdev, PCI_D0); | |
1571 | ||
1572 | if (!netif_running(dev)) | |
1573 | goto out; | |
1574 | ||
1575 | /* Interrupts already disabled by sc92031_suspend */ | |
699784b7 | 1576 | spin_lock_bh(&priv->lock); |
bf345707 CEB |
1577 | |
1578 | _sc92031_reset(dev); | |
1579 | mmiowb(); | |
1580 | ||
699784b7 | 1581 | spin_unlock_bh(&priv->lock); |
bf345707 CEB |
1582 | sc92031_enable_interrupts(dev); |
1583 | ||
1584 | netif_device_attach(dev); | |
1585 | ||
1586 | if (netif_carrier_ok(dev)) | |
1587 | netif_wake_queue(dev); | |
1588 | else | |
1589 | netif_tx_disable(dev); | |
1590 | ||
1591 | out: | |
1592 | return 0; | |
1593 | } | |
1594 | ||
1595 | static struct pci_device_id sc92031_pci_device_id_table[] __devinitdata = { | |
1596 | { PCI_DEVICE(PCI_VENDOR_ID_SILAN, PCI_DEVICE_ID_SILAN_SC92031) }, | |
1597 | { PCI_DEVICE(PCI_VENDOR_ID_SILAN, PCI_DEVICE_ID_SILAN_8139D) }, | |
1598 | { 0, } | |
1599 | }; | |
1600 | MODULE_DEVICE_TABLE(pci, sc92031_pci_device_id_table); | |
1601 | ||
1602 | static struct pci_driver sc92031_pci_driver = { | |
1603 | .name = SC92031_NAME, | |
1604 | .id_table = sc92031_pci_device_id_table, | |
1605 | .probe = sc92031_probe, | |
1606 | .remove = __devexit_p(sc92031_remove), | |
1607 | .suspend = sc92031_suspend, | |
1608 | .resume = sc92031_resume, | |
1609 | }; | |
1610 | ||
1611 | static int __init sc92031_init(void) | |
1612 | { | |
bf345707 CEB |
1613 | return pci_register_driver(&sc92031_pci_driver); |
1614 | } | |
1615 | ||
1616 | static void __exit sc92031_exit(void) | |
1617 | { | |
1618 | pci_unregister_driver(&sc92031_pci_driver); | |
1619 | } | |
1620 | ||
1621 | module_init(sc92031_init); | |
1622 | module_exit(sc92031_exit); | |
1623 | ||
1624 | MODULE_LICENSE("GPL"); | |
1625 | MODULE_AUTHOR("Cesar Eduardo Barros <cesarb@cesarb.net>"); | |
1626 | MODULE_DESCRIPTION(SC92031_DESCRIPTION); |