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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2006-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/seq_file.h> | |
37b5a603 | 16 | #include <linux/i2c.h> |
f31a45d2 | 17 | #include <linux/mii.h> |
8ceee660 BH |
18 | #include "net_driver.h" |
19 | #include "bitfield.h" | |
20 | #include "efx.h" | |
21 | #include "mac.h" | |
8ceee660 BH |
22 | #include "spi.h" |
23 | #include "falcon.h" | |
3e6c4538 | 24 | #include "regs.h" |
12d00cad | 25 | #include "io.h" |
8ceee660 BH |
26 | #include "mdio_10g.h" |
27 | #include "phy.h" | |
8ceee660 BH |
28 | #include "workarounds.h" |
29 | ||
8986352a | 30 | /* Hardware control for SFC4000 (aka Falcon). */ |
8ceee660 | 31 | |
8ceee660 BH |
32 | /************************************************************************** |
33 | * | |
34 | * Configurable values | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
8ceee660 BH |
39 | /* This is set to 16 for a good reason. In summary, if larger than |
40 | * 16, the descriptor cache holds more than a default socket | |
41 | * buffer's worth of packets (for UDP we can only have at most one | |
42 | * socket buffer's worth outstanding). This combined with the fact | |
43 | * that we only get 1 TX event per descriptor cache means the NIC | |
44 | * goes idle. | |
45 | */ | |
46 | #define TX_DC_ENTRIES 16 | |
46e1ac0f | 47 | #define TX_DC_ENTRIES_ORDER 1 |
8ceee660 BH |
48 | |
49 | #define RX_DC_ENTRIES 64 | |
46e1ac0f | 50 | #define RX_DC_ENTRIES_ORDER 3 |
8ceee660 | 51 | |
2f7f5730 BH |
52 | static const unsigned int |
53 | /* "Large" EEPROM device: Atmel AT25640 or similar | |
54 | * 8 KB, 16-bit address, 32 B write block */ | |
55 | large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN) | |
56 | | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
57 | | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)), | |
58 | /* Default flash device: Atmel AT25F1024 | |
59 | * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */ | |
60 | default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN) | |
61 | | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
62 | | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN) | |
63 | | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) | |
64 | | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); | |
65 | ||
8ceee660 BH |
66 | /* RX FIFO XOFF watermark |
67 | * | |
68 | * When the amount of the RX FIFO increases used increases past this | |
69 | * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A) | |
70 | * This also has an effect on RX/TX arbitration | |
71 | */ | |
152b6a62 BH |
72 | int efx_nic_rx_xoff_thresh = -1; |
73 | module_param_named(rx_xoff_thresh_bytes, efx_nic_rx_xoff_thresh, int, 0644); | |
8ceee660 BH |
74 | MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold"); |
75 | ||
76 | /* RX FIFO XON watermark | |
77 | * | |
78 | * When the amount of the RX FIFO used decreases below this | |
79 | * watermark send XON. Only used if TX flow control is enabled (ethtool -A) | |
80 | * This also has an effect on RX/TX arbitration | |
81 | */ | |
152b6a62 BH |
82 | int efx_nic_rx_xon_thresh = -1; |
83 | module_param_named(rx_xon_thresh_bytes, efx_nic_rx_xon_thresh, int, 0644); | |
8ceee660 BH |
84 | MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold"); |
85 | ||
152b6a62 BH |
86 | /* If EFX_MAX_INT_ERRORS internal errors occur within |
87 | * EFX_INT_ERROR_EXPIRE seconds, we consider the NIC broken and | |
2c3c3d02 BH |
88 | * disable it. |
89 | */ | |
152b6a62 BH |
90 | #define EFX_INT_ERROR_EXPIRE 3600 |
91 | #define EFX_MAX_INT_ERRORS 5 | |
8ceee660 | 92 | |
6bc5d3a9 BH |
93 | /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times |
94 | */ | |
152b6a62 BH |
95 | #define EFX_FLUSH_INTERVAL 10 |
96 | #define EFX_FLUSH_POLL_COUNT 100 | |
8ceee660 BH |
97 | |
98 | /************************************************************************** | |
99 | * | |
100 | * Falcon constants | |
101 | * | |
102 | ************************************************************************** | |
103 | */ | |
104 | ||
8ceee660 | 105 | /* Size and alignment of special buffers (4KB) */ |
152b6a62 | 106 | #define EFX_BUF_SIZE 4096 |
8ceee660 | 107 | |
127e6e10 | 108 | /* Depth of RX flush request fifo */ |
152b6a62 | 109 | #define EFX_RX_FLUSH_COUNT 4 |
8ceee660 BH |
110 | |
111 | /************************************************************************** | |
112 | * | |
152b6a62 | 113 | * Solarstorm hardware access |
8ceee660 BH |
114 | * |
115 | **************************************************************************/ | |
116 | ||
152b6a62 BH |
117 | static inline void efx_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value, |
118 | unsigned int index) | |
12d00cad BH |
119 | { |
120 | efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base, | |
121 | value, index); | |
122 | } | |
123 | ||
8ceee660 | 124 | /* Read the current event from the event queue */ |
152b6a62 BH |
125 | static inline efx_qword_t *efx_event(struct efx_channel *channel, |
126 | unsigned int index) | |
8ceee660 BH |
127 | { |
128 | return (((efx_qword_t *) (channel->eventq.addr)) + index); | |
129 | } | |
130 | ||
131 | /* See if an event is present | |
132 | * | |
133 | * We check both the high and low dword of the event for all ones. We | |
134 | * wrote all ones when we cleared the event, and no valid event can | |
135 | * have all ones in either its high or low dwords. This approach is | |
136 | * robust against reordering. | |
137 | * | |
138 | * Note that using a single 64-bit comparison is incorrect; even | |
139 | * though the CPU read will be atomic, the DMA write may not be. | |
140 | */ | |
152b6a62 | 141 | static inline int efx_event_present(efx_qword_t *event) |
8ceee660 BH |
142 | { |
143 | return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | | |
144 | EFX_DWORD_IS_ALL_ONES(event->dword[1]))); | |
145 | } | |
146 | ||
147 | /************************************************************************** | |
148 | * | |
149 | * I2C bus - this is a bit-bashing interface using GPIO pins | |
150 | * Note that it uses the output enables to tristate the outputs | |
151 | * SDA is the data pin and SCL is the clock | |
152 | * | |
153 | ************************************************************************** | |
154 | */ | |
37b5a603 | 155 | static void falcon_setsda(void *data, int state) |
8ceee660 | 156 | { |
37b5a603 | 157 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
158 | efx_oword_t reg; |
159 | ||
12d00cad | 160 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 161 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); |
12d00cad | 162 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
8ceee660 BH |
163 | } |
164 | ||
37b5a603 | 165 | static void falcon_setscl(void *data, int state) |
8ceee660 | 166 | { |
37b5a603 | 167 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
168 | efx_oword_t reg; |
169 | ||
12d00cad | 170 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 171 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); |
12d00cad | 172 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
37b5a603 BH |
173 | } |
174 | ||
175 | static int falcon_getsda(void *data) | |
176 | { | |
177 | struct efx_nic *efx = (struct efx_nic *)data; | |
178 | efx_oword_t reg; | |
179 | ||
12d00cad | 180 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 181 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); |
8ceee660 BH |
182 | } |
183 | ||
37b5a603 | 184 | static int falcon_getscl(void *data) |
8ceee660 | 185 | { |
37b5a603 | 186 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
187 | efx_oword_t reg; |
188 | ||
12d00cad | 189 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 190 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); |
8ceee660 BH |
191 | } |
192 | ||
37b5a603 BH |
193 | static struct i2c_algo_bit_data falcon_i2c_bit_operations = { |
194 | .setsda = falcon_setsda, | |
195 | .setscl = falcon_setscl, | |
8ceee660 BH |
196 | .getsda = falcon_getsda, |
197 | .getscl = falcon_getscl, | |
62c78329 | 198 | .udelay = 5, |
9dadae68 BH |
199 | /* Wait up to 50 ms for slave to let us pull SCL high */ |
200 | .timeout = DIV_ROUND_UP(HZ, 20), | |
8ceee660 BH |
201 | }; |
202 | ||
203 | /************************************************************************** | |
204 | * | |
152b6a62 | 205 | * Special buffer handling |
8ceee660 BH |
206 | * Special buffers are used for event queues and the TX and RX |
207 | * descriptor rings. | |
208 | * | |
209 | *************************************************************************/ | |
210 | ||
211 | /* | |
152b6a62 | 212 | * Initialise a special buffer |
8ceee660 BH |
213 | * |
214 | * This will define a buffer (previously allocated via | |
152b6a62 | 215 | * efx_alloc_special_buffer()) in the buffer table, allowing |
8ceee660 BH |
216 | * it to be used for event queues, descriptor rings etc. |
217 | */ | |
bc3c90a2 | 218 | static void |
152b6a62 | 219 | efx_init_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) |
8ceee660 BH |
220 | { |
221 | efx_qword_t buf_desc; | |
222 | int index; | |
223 | dma_addr_t dma_addr; | |
224 | int i; | |
225 | ||
226 | EFX_BUG_ON_PARANOID(!buffer->addr); | |
227 | ||
228 | /* Write buffer descriptors to NIC */ | |
229 | for (i = 0; i < buffer->entries; i++) { | |
230 | index = buffer->index + i; | |
231 | dma_addr = buffer->dma_addr + (i * 4096); | |
232 | EFX_LOG(efx, "mapping special buffer %d at %llx\n", | |
233 | index, (unsigned long long)dma_addr); | |
3e6c4538 BH |
234 | EFX_POPULATE_QWORD_3(buf_desc, |
235 | FRF_AZ_BUF_ADR_REGION, 0, | |
236 | FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12, | |
237 | FRF_AZ_BUF_OWNER_ID_FBUF, 0); | |
152b6a62 | 238 | efx_write_buf_tbl(efx, &buf_desc, index); |
8ceee660 | 239 | } |
8ceee660 BH |
240 | } |
241 | ||
152b6a62 | 242 | /* Unmaps a buffer and clears the buffer table entries */ |
8ceee660 | 243 | static void |
152b6a62 | 244 | efx_fini_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) |
8ceee660 BH |
245 | { |
246 | efx_oword_t buf_tbl_upd; | |
247 | unsigned int start = buffer->index; | |
248 | unsigned int end = (buffer->index + buffer->entries - 1); | |
249 | ||
250 | if (!buffer->entries) | |
251 | return; | |
252 | ||
253 | EFX_LOG(efx, "unmapping special buffers %d-%d\n", | |
254 | buffer->index, buffer->index + buffer->entries - 1); | |
255 | ||
256 | EFX_POPULATE_OWORD_4(buf_tbl_upd, | |
3e6c4538 BH |
257 | FRF_AZ_BUF_UPD_CMD, 0, |
258 | FRF_AZ_BUF_CLR_CMD, 1, | |
259 | FRF_AZ_BUF_CLR_END_ID, end, | |
260 | FRF_AZ_BUF_CLR_START_ID, start); | |
12d00cad | 261 | efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD); |
8ceee660 BH |
262 | } |
263 | ||
264 | /* | |
152b6a62 | 265 | * Allocate a new special buffer |
8ceee660 BH |
266 | * |
267 | * This allocates memory for a new buffer, clears it and allocates a | |
152b6a62 | 268 | * new buffer ID range. It does not write into the buffer table. |
8ceee660 | 269 | * |
152b6a62 BH |
270 | * This call will allocate 4KB buffers, since 8KB buffers can't be |
271 | * used for event queues and descriptor rings. | |
8ceee660 | 272 | */ |
152b6a62 BH |
273 | static int efx_alloc_special_buffer(struct efx_nic *efx, |
274 | struct efx_special_buffer *buffer, | |
275 | unsigned int len) | |
8ceee660 | 276 | { |
152b6a62 | 277 | len = ALIGN(len, EFX_BUF_SIZE); |
8ceee660 BH |
278 | |
279 | buffer->addr = pci_alloc_consistent(efx->pci_dev, len, | |
280 | &buffer->dma_addr); | |
281 | if (!buffer->addr) | |
282 | return -ENOMEM; | |
283 | buffer->len = len; | |
152b6a62 BH |
284 | buffer->entries = len / EFX_BUF_SIZE; |
285 | BUG_ON(buffer->dma_addr & (EFX_BUF_SIZE - 1)); | |
8ceee660 BH |
286 | |
287 | /* All zeros is a potentially valid event so memset to 0xff */ | |
288 | memset(buffer->addr, 0xff, len); | |
289 | ||
290 | /* Select new buffer ID */ | |
0484e0db BH |
291 | buffer->index = efx->next_buffer_table; |
292 | efx->next_buffer_table += buffer->entries; | |
8ceee660 BH |
293 | |
294 | EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x " | |
9c8976a1 | 295 | "(virt %p phys %llx)\n", buffer->index, |
8ceee660 | 296 | buffer->index + buffer->entries - 1, |
9c8976a1 JSR |
297 | (u64)buffer->dma_addr, len, |
298 | buffer->addr, (u64)virt_to_phys(buffer->addr)); | |
8ceee660 BH |
299 | |
300 | return 0; | |
301 | } | |
302 | ||
152b6a62 BH |
303 | static void |
304 | efx_free_special_buffer(struct efx_nic *efx, struct efx_special_buffer *buffer) | |
8ceee660 BH |
305 | { |
306 | if (!buffer->addr) | |
307 | return; | |
308 | ||
309 | EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x " | |
9c8976a1 | 310 | "(virt %p phys %llx)\n", buffer->index, |
8ceee660 | 311 | buffer->index + buffer->entries - 1, |
9c8976a1 JSR |
312 | (u64)buffer->dma_addr, buffer->len, |
313 | buffer->addr, (u64)virt_to_phys(buffer->addr)); | |
8ceee660 BH |
314 | |
315 | pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr, | |
316 | buffer->dma_addr); | |
317 | buffer->addr = NULL; | |
318 | buffer->entries = 0; | |
319 | } | |
320 | ||
321 | /************************************************************************** | |
322 | * | |
152b6a62 | 323 | * Generic buffer handling |
8ceee660 BH |
324 | * These buffers are used for interrupt status and MAC stats |
325 | * | |
326 | **************************************************************************/ | |
327 | ||
152b6a62 BH |
328 | int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer, |
329 | unsigned int len) | |
8ceee660 BH |
330 | { |
331 | buffer->addr = pci_alloc_consistent(efx->pci_dev, len, | |
332 | &buffer->dma_addr); | |
333 | if (!buffer->addr) | |
334 | return -ENOMEM; | |
335 | buffer->len = len; | |
336 | memset(buffer->addr, 0, len); | |
337 | return 0; | |
338 | } | |
339 | ||
152b6a62 | 340 | void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer) |
8ceee660 BH |
341 | { |
342 | if (buffer->addr) { | |
343 | pci_free_consistent(efx->pci_dev, buffer->len, | |
344 | buffer->addr, buffer->dma_addr); | |
345 | buffer->addr = NULL; | |
346 | } | |
347 | } | |
348 | ||
349 | /************************************************************************** | |
350 | * | |
152b6a62 | 351 | * TX path |
8ceee660 BH |
352 | * |
353 | **************************************************************************/ | |
354 | ||
355 | /* Returns a pointer to the specified transmit descriptor in the TX | |
356 | * descriptor queue belonging to the specified channel. | |
357 | */ | |
152b6a62 BH |
358 | static inline efx_qword_t * |
359 | efx_tx_desc(struct efx_tx_queue *tx_queue, unsigned int index) | |
8ceee660 BH |
360 | { |
361 | return (((efx_qword_t *) (tx_queue->txd.addr)) + index); | |
362 | } | |
363 | ||
364 | /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ | |
152b6a62 | 365 | static inline void efx_notify_tx_desc(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
366 | { |
367 | unsigned write_ptr; | |
368 | efx_dword_t reg; | |
369 | ||
3ffeabdd | 370 | write_ptr = tx_queue->write_count & EFX_TXQ_MASK; |
3e6c4538 | 371 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr); |
12d00cad BH |
372 | efx_writed_page(tx_queue->efx, ®, |
373 | FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue); | |
8ceee660 BH |
374 | } |
375 | ||
376 | ||
377 | /* For each entry inserted into the software descriptor ring, create a | |
378 | * descriptor in the hardware TX descriptor ring (in host memory), and | |
379 | * write a doorbell. | |
380 | */ | |
152b6a62 | 381 | void efx_nic_push_buffers(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
382 | { |
383 | ||
384 | struct efx_tx_buffer *buffer; | |
385 | efx_qword_t *txd; | |
386 | unsigned write_ptr; | |
387 | ||
388 | BUG_ON(tx_queue->write_count == tx_queue->insert_count); | |
389 | ||
390 | do { | |
3ffeabdd | 391 | write_ptr = tx_queue->write_count & EFX_TXQ_MASK; |
8ceee660 | 392 | buffer = &tx_queue->buffer[write_ptr]; |
152b6a62 | 393 | txd = efx_tx_desc(tx_queue, write_ptr); |
8ceee660 BH |
394 | ++tx_queue->write_count; |
395 | ||
396 | /* Create TX descriptor ring entry */ | |
3e6c4538 BH |
397 | EFX_POPULATE_QWORD_4(*txd, |
398 | FSF_AZ_TX_KER_CONT, buffer->continuation, | |
399 | FSF_AZ_TX_KER_BYTE_COUNT, buffer->len, | |
400 | FSF_AZ_TX_KER_BUF_REGION, 0, | |
401 | FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr); | |
8ceee660 BH |
402 | } while (tx_queue->write_count != tx_queue->insert_count); |
403 | ||
404 | wmb(); /* Ensure descriptors are written before they are fetched */ | |
152b6a62 | 405 | efx_notify_tx_desc(tx_queue); |
8ceee660 BH |
406 | } |
407 | ||
408 | /* Allocate hardware resources for a TX queue */ | |
152b6a62 | 409 | int efx_nic_probe_tx(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
410 | { |
411 | struct efx_nic *efx = tx_queue->efx; | |
3ffeabdd BH |
412 | BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 || |
413 | EFX_TXQ_SIZE & EFX_TXQ_MASK); | |
152b6a62 BH |
414 | return efx_alloc_special_buffer(efx, &tx_queue->txd, |
415 | EFX_TXQ_SIZE * sizeof(efx_qword_t)); | |
8ceee660 BH |
416 | } |
417 | ||
152b6a62 | 418 | void efx_nic_init_tx(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
419 | { |
420 | efx_oword_t tx_desc_ptr; | |
421 | struct efx_nic *efx = tx_queue->efx; | |
8ceee660 | 422 | |
127e6e10 | 423 | tx_queue->flushed = FLUSH_NONE; |
6bc5d3a9 | 424 | |
8ceee660 | 425 | /* Pin TX descriptor ring */ |
152b6a62 | 426 | efx_init_special_buffer(efx, &tx_queue->txd); |
8ceee660 BH |
427 | |
428 | /* Push TX descriptor ring to card */ | |
429 | EFX_POPULATE_OWORD_10(tx_desc_ptr, | |
3e6c4538 BH |
430 | FRF_AZ_TX_DESCQ_EN, 1, |
431 | FRF_AZ_TX_ISCSI_DDIG_EN, 0, | |
432 | FRF_AZ_TX_ISCSI_HDIG_EN, 0, | |
433 | FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index, | |
434 | FRF_AZ_TX_DESCQ_EVQ_ID, | |
435 | tx_queue->channel->channel, | |
436 | FRF_AZ_TX_DESCQ_OWNER_ID, 0, | |
437 | FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue, | |
3ffeabdd BH |
438 | FRF_AZ_TX_DESCQ_SIZE, |
439 | __ffs(tx_queue->txd.entries), | |
3e6c4538 BH |
440 | FRF_AZ_TX_DESCQ_TYPE, 0, |
441 | FRF_BZ_TX_NON_IP_DROP_DIS, 1); | |
8ceee660 | 442 | |
daeda630 | 443 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
60ac1065 | 444 | int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM; |
3e6c4538 BH |
445 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum); |
446 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS, | |
447 | !csum); | |
8ceee660 BH |
448 | } |
449 | ||
12d00cad BH |
450 | efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, |
451 | tx_queue->queue); | |
8ceee660 | 452 | |
daeda630 | 453 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { |
8ceee660 BH |
454 | efx_oword_t reg; |
455 | ||
60ac1065 BH |
456 | /* Only 128 bits in this register */ |
457 | BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128); | |
8ceee660 | 458 | |
12d00cad | 459 | efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG); |
60ac1065 | 460 | if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM) |
8ceee660 BH |
461 | clear_bit_le(tx_queue->queue, (void *)®); |
462 | else | |
463 | set_bit_le(tx_queue->queue, (void *)®); | |
12d00cad | 464 | efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG); |
8ceee660 | 465 | } |
8ceee660 BH |
466 | } |
467 | ||
152b6a62 | 468 | static void efx_flush_tx_queue(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
469 | { |
470 | struct efx_nic *efx = tx_queue->efx; | |
8ceee660 | 471 | efx_oword_t tx_flush_descq; |
8ceee660 | 472 | |
127e6e10 BH |
473 | tx_queue->flushed = FLUSH_PENDING; |
474 | ||
8ceee660 BH |
475 | /* Post a flush command */ |
476 | EFX_POPULATE_OWORD_2(tx_flush_descq, | |
3e6c4538 BH |
477 | FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, |
478 | FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue); | |
12d00cad | 479 | efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ); |
8ceee660 BH |
480 | } |
481 | ||
152b6a62 | 482 | void efx_nic_fini_tx(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
483 | { |
484 | struct efx_nic *efx = tx_queue->efx; | |
485 | efx_oword_t tx_desc_ptr; | |
486 | ||
6bc5d3a9 | 487 | /* The queue should have been flushed */ |
127e6e10 | 488 | WARN_ON(tx_queue->flushed != FLUSH_DONE); |
8ceee660 BH |
489 | |
490 | /* Remove TX descriptor ring from card */ | |
491 | EFX_ZERO_OWORD(tx_desc_ptr); | |
12d00cad BH |
492 | efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, |
493 | tx_queue->queue); | |
8ceee660 BH |
494 | |
495 | /* Unpin TX descriptor ring */ | |
152b6a62 | 496 | efx_fini_special_buffer(efx, &tx_queue->txd); |
8ceee660 BH |
497 | } |
498 | ||
499 | /* Free buffers backing TX queue */ | |
152b6a62 | 500 | void efx_nic_remove_tx(struct efx_tx_queue *tx_queue) |
8ceee660 | 501 | { |
152b6a62 | 502 | efx_free_special_buffer(tx_queue->efx, &tx_queue->txd); |
8ceee660 BH |
503 | } |
504 | ||
505 | /************************************************************************** | |
506 | * | |
152b6a62 | 507 | * RX path |
8ceee660 BH |
508 | * |
509 | **************************************************************************/ | |
510 | ||
511 | /* Returns a pointer to the specified descriptor in the RX descriptor queue */ | |
152b6a62 BH |
512 | static inline efx_qword_t * |
513 | efx_rx_desc(struct efx_rx_queue *rx_queue, unsigned int index) | |
8ceee660 BH |
514 | { |
515 | return (((efx_qword_t *) (rx_queue->rxd.addr)) + index); | |
516 | } | |
517 | ||
518 | /* This creates an entry in the RX descriptor queue */ | |
152b6a62 BH |
519 | static inline void |
520 | efx_build_rx_desc(struct efx_rx_queue *rx_queue, unsigned index) | |
8ceee660 BH |
521 | { |
522 | struct efx_rx_buffer *rx_buf; | |
523 | efx_qword_t *rxd; | |
524 | ||
152b6a62 | 525 | rxd = efx_rx_desc(rx_queue, index); |
8ceee660 BH |
526 | rx_buf = efx_rx_buffer(rx_queue, index); |
527 | EFX_POPULATE_QWORD_3(*rxd, | |
3e6c4538 | 528 | FSF_AZ_RX_KER_BUF_SIZE, |
8ceee660 BH |
529 | rx_buf->len - |
530 | rx_queue->efx->type->rx_buffer_padding, | |
3e6c4538 BH |
531 | FSF_AZ_RX_KER_BUF_REGION, 0, |
532 | FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); | |
8ceee660 BH |
533 | } |
534 | ||
535 | /* This writes to the RX_DESC_WPTR register for the specified receive | |
536 | * descriptor ring. | |
537 | */ | |
152b6a62 | 538 | void efx_nic_notify_rx_desc(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
539 | { |
540 | efx_dword_t reg; | |
541 | unsigned write_ptr; | |
542 | ||
543 | while (rx_queue->notified_count != rx_queue->added_count) { | |
152b6a62 BH |
544 | efx_build_rx_desc(rx_queue, |
545 | rx_queue->notified_count & | |
546 | EFX_RXQ_MASK); | |
8ceee660 BH |
547 | ++rx_queue->notified_count; |
548 | } | |
549 | ||
550 | wmb(); | |
3ffeabdd | 551 | write_ptr = rx_queue->added_count & EFX_RXQ_MASK; |
3e6c4538 | 552 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr); |
12d00cad BH |
553 | efx_writed_page(rx_queue->efx, ®, |
554 | FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue); | |
8ceee660 BH |
555 | } |
556 | ||
152b6a62 | 557 | int efx_nic_probe_rx(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
558 | { |
559 | struct efx_nic *efx = rx_queue->efx; | |
3ffeabdd BH |
560 | BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 || |
561 | EFX_RXQ_SIZE & EFX_RXQ_MASK); | |
152b6a62 BH |
562 | return efx_alloc_special_buffer(efx, &rx_queue->rxd, |
563 | EFX_RXQ_SIZE * sizeof(efx_qword_t)); | |
8ceee660 BH |
564 | } |
565 | ||
152b6a62 | 566 | void efx_nic_init_rx(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
567 | { |
568 | efx_oword_t rx_desc_ptr; | |
569 | struct efx_nic *efx = rx_queue->efx; | |
daeda630 | 570 | bool is_b0 = efx_nic_rev(efx) >= EFX_REV_FALCON_B0; |
dc8cfa55 | 571 | bool iscsi_digest_en = is_b0; |
8ceee660 BH |
572 | |
573 | EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n", | |
574 | rx_queue->queue, rx_queue->rxd.index, | |
575 | rx_queue->rxd.index + rx_queue->rxd.entries - 1); | |
576 | ||
127e6e10 | 577 | rx_queue->flushed = FLUSH_NONE; |
6bc5d3a9 | 578 | |
8ceee660 | 579 | /* Pin RX descriptor ring */ |
152b6a62 | 580 | efx_init_special_buffer(efx, &rx_queue->rxd); |
8ceee660 BH |
581 | |
582 | /* Push RX descriptor ring to card */ | |
583 | EFX_POPULATE_OWORD_10(rx_desc_ptr, | |
3e6c4538 BH |
584 | FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en, |
585 | FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en, | |
586 | FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index, | |
587 | FRF_AZ_RX_DESCQ_EVQ_ID, | |
588 | rx_queue->channel->channel, | |
589 | FRF_AZ_RX_DESCQ_OWNER_ID, 0, | |
590 | FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue, | |
3ffeabdd BH |
591 | FRF_AZ_RX_DESCQ_SIZE, |
592 | __ffs(rx_queue->rxd.entries), | |
3e6c4538 | 593 | FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ , |
8ceee660 | 594 | /* For >=B0 this is scatter so disable */ |
3e6c4538 BH |
595 | FRF_AZ_RX_DESCQ_JUMBO, !is_b0, |
596 | FRF_AZ_RX_DESCQ_EN, 1); | |
12d00cad BH |
597 | efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, |
598 | rx_queue->queue); | |
8ceee660 BH |
599 | } |
600 | ||
152b6a62 | 601 | static void efx_flush_rx_queue(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
602 | { |
603 | struct efx_nic *efx = rx_queue->efx; | |
8ceee660 BH |
604 | efx_oword_t rx_flush_descq; |
605 | ||
127e6e10 BH |
606 | rx_queue->flushed = FLUSH_PENDING; |
607 | ||
8ceee660 BH |
608 | /* Post a flush command */ |
609 | EFX_POPULATE_OWORD_2(rx_flush_descq, | |
3e6c4538 BH |
610 | FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, |
611 | FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue); | |
12d00cad | 612 | efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ); |
8ceee660 BH |
613 | } |
614 | ||
152b6a62 | 615 | void efx_nic_fini_rx(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
616 | { |
617 | efx_oword_t rx_desc_ptr; | |
618 | struct efx_nic *efx = rx_queue->efx; | |
8ceee660 | 619 | |
6bc5d3a9 | 620 | /* The queue should already have been flushed */ |
127e6e10 | 621 | WARN_ON(rx_queue->flushed != FLUSH_DONE); |
8ceee660 BH |
622 | |
623 | /* Remove RX descriptor ring from card */ | |
624 | EFX_ZERO_OWORD(rx_desc_ptr); | |
12d00cad BH |
625 | efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, |
626 | rx_queue->queue); | |
8ceee660 BH |
627 | |
628 | /* Unpin RX descriptor ring */ | |
152b6a62 | 629 | efx_fini_special_buffer(efx, &rx_queue->rxd); |
8ceee660 BH |
630 | } |
631 | ||
632 | /* Free buffers backing RX queue */ | |
152b6a62 | 633 | void efx_nic_remove_rx(struct efx_rx_queue *rx_queue) |
8ceee660 | 634 | { |
152b6a62 | 635 | efx_free_special_buffer(rx_queue->efx, &rx_queue->rxd); |
8ceee660 BH |
636 | } |
637 | ||
638 | /************************************************************************** | |
639 | * | |
152b6a62 | 640 | * Event queue processing |
8ceee660 BH |
641 | * Event queues are processed by per-channel tasklets. |
642 | * | |
643 | **************************************************************************/ | |
644 | ||
645 | /* Update a channel's event queue's read pointer (RPTR) register | |
646 | * | |
647 | * This writes the EVQ_RPTR_REG register for the specified channel's | |
648 | * event queue. | |
649 | * | |
650 | * Note that EVQ_RPTR_REG contains the index of the "last read" event, | |
651 | * whereas channel->eventq_read_ptr contains the index of the "next to | |
652 | * read" event. | |
653 | */ | |
152b6a62 | 654 | void efx_nic_eventq_read_ack(struct efx_channel *channel) |
8ceee660 BH |
655 | { |
656 | efx_dword_t reg; | |
657 | struct efx_nic *efx = channel->efx; | |
658 | ||
3e6c4538 | 659 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr); |
12d00cad | 660 | efx_writed_table(efx, ®, efx->type->evq_rptr_tbl_base, |
d3074025 | 661 | channel->channel); |
8ceee660 BH |
662 | } |
663 | ||
664 | /* Use HW to insert a SW defined event */ | |
152b6a62 | 665 | void efx_generate_event(struct efx_channel *channel, efx_qword_t *event) |
8ceee660 BH |
666 | { |
667 | efx_oword_t drv_ev_reg; | |
668 | ||
3e6c4538 BH |
669 | BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 || |
670 | FRF_AZ_DRV_EV_DATA_WIDTH != 64); | |
671 | drv_ev_reg.u32[0] = event->u32[0]; | |
672 | drv_ev_reg.u32[1] = event->u32[1]; | |
673 | drv_ev_reg.u32[2] = 0; | |
674 | drv_ev_reg.u32[3] = 0; | |
675 | EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel); | |
12d00cad | 676 | efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV); |
8ceee660 BH |
677 | } |
678 | ||
679 | /* Handle a transmit completion event | |
680 | * | |
152b6a62 | 681 | * The NIC batches TX completion events; the message we receive is of |
8ceee660 BH |
682 | * the form "complete all TX events up to this index". |
683 | */ | |
152b6a62 BH |
684 | static void |
685 | efx_handle_tx_event(struct efx_channel *channel, efx_qword_t *event) | |
8ceee660 BH |
686 | { |
687 | unsigned int tx_ev_desc_ptr; | |
688 | unsigned int tx_ev_q_label; | |
689 | struct efx_tx_queue *tx_queue; | |
690 | struct efx_nic *efx = channel->efx; | |
691 | ||
3e6c4538 | 692 | if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) { |
8ceee660 | 693 | /* Transmit completion */ |
3e6c4538 BH |
694 | tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR); |
695 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); | |
8ceee660 | 696 | tx_queue = &efx->tx_queue[tx_ev_q_label]; |
6fb70fd1 BH |
697 | channel->irq_mod_score += |
698 | (tx_ev_desc_ptr - tx_queue->read_count) & | |
3ffeabdd | 699 | EFX_TXQ_MASK; |
8ceee660 | 700 | efx_xmit_done(tx_queue, tx_ev_desc_ptr); |
3e6c4538 | 701 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) { |
8ceee660 | 702 | /* Rewrite the FIFO write pointer */ |
3e6c4538 | 703 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); |
8ceee660 BH |
704 | tx_queue = &efx->tx_queue[tx_ev_q_label]; |
705 | ||
55668611 | 706 | if (efx_dev_registered(efx)) |
8ceee660 | 707 | netif_tx_lock(efx->net_dev); |
152b6a62 | 708 | efx_notify_tx_desc(tx_queue); |
55668611 | 709 | if (efx_dev_registered(efx)) |
8ceee660 | 710 | netif_tx_unlock(efx->net_dev); |
3e6c4538 | 711 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) && |
8ceee660 BH |
712 | EFX_WORKAROUND_10727(efx)) { |
713 | efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); | |
714 | } else { | |
715 | EFX_ERR(efx, "channel %d unexpected TX event " | |
716 | EFX_QWORD_FMT"\n", channel->channel, | |
717 | EFX_QWORD_VAL(*event)); | |
718 | } | |
719 | } | |
720 | ||
8ceee660 | 721 | /* Detect errors included in the rx_evt_pkt_ok bit. */ |
152b6a62 BH |
722 | static void efx_handle_rx_not_ok(struct efx_rx_queue *rx_queue, |
723 | const efx_qword_t *event, | |
724 | bool *rx_ev_pkt_ok, | |
725 | bool *discard) | |
8ceee660 BH |
726 | { |
727 | struct efx_nic *efx = rx_queue->efx; | |
dc8cfa55 BH |
728 | bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err; |
729 | bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err; | |
730 | bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc; | |
731 | bool rx_ev_other_err, rx_ev_pause_frm; | |
c1ac403b | 732 | bool rx_ev_hdr_type, rx_ev_mcast_pkt; |
dc8cfa55 | 733 | unsigned rx_ev_pkt_type; |
8ceee660 | 734 | |
3e6c4538 BH |
735 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); |
736 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); | |
737 | rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC); | |
738 | rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE); | |
8ceee660 | 739 | rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event, |
3e6c4538 | 740 | FSF_AZ_RX_EV_BUF_OWNER_ID_ERR); |
8ceee660 | 741 | rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event, |
3e6c4538 | 742 | FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR); |
8ceee660 | 743 | rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event, |
3e6c4538 BH |
744 | FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR); |
745 | rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR); | |
746 | rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC); | |
daeda630 | 747 | rx_ev_drib_nib = ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) ? |
3e6c4538 BH |
748 | 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB)); |
749 | rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR); | |
8ceee660 BH |
750 | |
751 | /* Every error apart from tobe_disc and pause_frm */ | |
752 | rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err | | |
753 | rx_ev_buf_owner_id_err | rx_ev_eth_crc_err | | |
754 | rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err); | |
755 | ||
50050877 BH |
756 | /* Count errors that are not in MAC stats. Ignore expected |
757 | * checksum errors during self-test. */ | |
8ceee660 BH |
758 | if (rx_ev_frm_trunc) |
759 | ++rx_queue->channel->n_rx_frm_trunc; | |
760 | else if (rx_ev_tobe_disc) | |
761 | ++rx_queue->channel->n_rx_tobe_disc; | |
50050877 BH |
762 | else if (!efx->loopback_selftest) { |
763 | if (rx_ev_ip_hdr_chksum_err) | |
764 | ++rx_queue->channel->n_rx_ip_hdr_chksum_err; | |
765 | else if (rx_ev_tcp_udp_chksum_err) | |
766 | ++rx_queue->channel->n_rx_tcp_udp_chksum_err; | |
767 | } | |
8ceee660 BH |
768 | |
769 | /* The frame must be discarded if any of these are true. */ | |
770 | *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib | | |
771 | rx_ev_tobe_disc | rx_ev_pause_frm); | |
772 | ||
773 | /* TOBE_DISC is expected on unicast mismatches; don't print out an | |
774 | * error message. FRM_TRUNC indicates RXDP dropped the packet due | |
775 | * to a FIFO overflow. | |
776 | */ | |
777 | #ifdef EFX_ENABLE_DEBUG | |
778 | if (rx_ev_other_err) { | |
779 | EFX_INFO_RL(efx, " RX queue %d unexpected RX event " | |
5b39fe30 | 780 | EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n", |
8ceee660 BH |
781 | rx_queue->queue, EFX_QWORD_VAL(*event), |
782 | rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "", | |
783 | rx_ev_ip_hdr_chksum_err ? | |
784 | " [IP_HDR_CHKSUM_ERR]" : "", | |
785 | rx_ev_tcp_udp_chksum_err ? | |
786 | " [TCP_UDP_CHKSUM_ERR]" : "", | |
787 | rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "", | |
788 | rx_ev_frm_trunc ? " [FRM_TRUNC]" : "", | |
789 | rx_ev_drib_nib ? " [DRIB_NIB]" : "", | |
790 | rx_ev_tobe_disc ? " [TOBE_DISC]" : "", | |
5b39fe30 | 791 | rx_ev_pause_frm ? " [PAUSE]" : ""); |
8ceee660 BH |
792 | } |
793 | #endif | |
8ceee660 BH |
794 | } |
795 | ||
796 | /* Handle receive events that are not in-order. */ | |
152b6a62 BH |
797 | static void |
798 | efx_handle_rx_bad_index(struct efx_rx_queue *rx_queue, unsigned index) | |
8ceee660 BH |
799 | { |
800 | struct efx_nic *efx = rx_queue->efx; | |
801 | unsigned expected, dropped; | |
802 | ||
3ffeabdd BH |
803 | expected = rx_queue->removed_count & EFX_RXQ_MASK; |
804 | dropped = (index - expected) & EFX_RXQ_MASK; | |
8ceee660 BH |
805 | EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n", |
806 | dropped, index, expected); | |
807 | ||
808 | efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ? | |
809 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
810 | } | |
811 | ||
812 | /* Handle a packet received event | |
813 | * | |
152b6a62 | 814 | * The NIC gives a "discard" flag if it's a unicast packet with the |
8ceee660 BH |
815 | * wrong destination address |
816 | * Also "is multicast" and "matches multicast filter" flags can be used to | |
817 | * discard non-matching multicast packets. | |
818 | */ | |
152b6a62 BH |
819 | static void |
820 | efx_handle_rx_event(struct efx_channel *channel, const efx_qword_t *event) | |
8ceee660 | 821 | { |
42cbe2d7 | 822 | unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt; |
dc8cfa55 | 823 | unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt; |
8ceee660 | 824 | unsigned expected_ptr; |
dc8cfa55 | 825 | bool rx_ev_pkt_ok, discard = false, checksummed; |
8ceee660 BH |
826 | struct efx_rx_queue *rx_queue; |
827 | struct efx_nic *efx = channel->efx; | |
828 | ||
829 | /* Basic packet information */ | |
3e6c4538 BH |
830 | rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT); |
831 | rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK); | |
832 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); | |
833 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT)); | |
834 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1); | |
835 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) != | |
836 | channel->channel); | |
8ceee660 | 837 | |
42cbe2d7 | 838 | rx_queue = &efx->rx_queue[channel->channel]; |
8ceee660 | 839 | |
3e6c4538 | 840 | rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR); |
3ffeabdd | 841 | expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK; |
42cbe2d7 | 842 | if (unlikely(rx_ev_desc_ptr != expected_ptr)) |
152b6a62 | 843 | efx_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr); |
8ceee660 BH |
844 | |
845 | if (likely(rx_ev_pkt_ok)) { | |
152b6a62 BH |
846 | /* If packet is marked as OK and packet type is TCP/IP or |
847 | * UDP/IP, then we can rely on the hardware checksum. | |
8ceee660 | 848 | */ |
3e6c4538 | 849 | checksummed = |
c1ac403b | 850 | likely(efx->rx_checksum_enabled) && |
152b6a62 BH |
851 | (rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP || |
852 | rx_ev_hdr_type == FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP); | |
8ceee660 | 853 | } else { |
152b6a62 | 854 | efx_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, &discard); |
dc8cfa55 | 855 | checksummed = false; |
8ceee660 BH |
856 | } |
857 | ||
858 | /* Detect multicast packets that didn't match the filter */ | |
3e6c4538 | 859 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); |
8ceee660 BH |
860 | if (rx_ev_mcast_pkt) { |
861 | unsigned int rx_ev_mcast_hash_match = | |
3e6c4538 | 862 | EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH); |
8ceee660 | 863 | |
c1ac403b BH |
864 | if (unlikely(!rx_ev_mcast_hash_match)) { |
865 | ++channel->n_rx_mcast_mismatch; | |
dc8cfa55 | 866 | discard = true; |
c1ac403b | 867 | } |
8ceee660 BH |
868 | } |
869 | ||
6fb70fd1 BH |
870 | channel->irq_mod_score += 2; |
871 | ||
8ceee660 BH |
872 | /* Handle received packet */ |
873 | efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt, | |
874 | checksummed, discard); | |
8ceee660 BH |
875 | } |
876 | ||
877 | /* Global events are basically PHY events */ | |
152b6a62 BH |
878 | static void |
879 | efx_handle_global_event(struct efx_channel *channel, efx_qword_t *event) | |
8ceee660 BH |
880 | { |
881 | struct efx_nic *efx = channel->efx; | |
766ca0fa | 882 | bool handled = false; |
8ceee660 | 883 | |
3e6c4538 BH |
884 | if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) || |
885 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) || | |
886 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) { | |
fdaa9aed | 887 | /* Ignored */ |
766ca0fa BH |
888 | handled = true; |
889 | } | |
8ceee660 | 890 | |
daeda630 | 891 | if ((efx_nic_rev(efx) >= EFX_REV_FALCON_B0) && |
3e6c4538 | 892 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) { |
9007b9fa | 893 | efx->xmac_poll_required = true; |
dc8cfa55 | 894 | handled = true; |
8ceee660 BH |
895 | } |
896 | ||
daeda630 | 897 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1 ? |
3e6c4538 BH |
898 | EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) : |
899 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) { | |
8ceee660 BH |
900 | EFX_ERR(efx, "channel %d seen global RX_RESET " |
901 | "event. Resetting.\n", channel->channel); | |
902 | ||
903 | atomic_inc(&efx->rx_reset); | |
904 | efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ? | |
905 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
dc8cfa55 | 906 | handled = true; |
8ceee660 BH |
907 | } |
908 | ||
909 | if (!handled) | |
910 | EFX_ERR(efx, "channel %d unknown global event " | |
911 | EFX_QWORD_FMT "\n", channel->channel, | |
912 | EFX_QWORD_VAL(*event)); | |
913 | } | |
914 | ||
152b6a62 BH |
915 | static void |
916 | efx_handle_driver_event(struct efx_channel *channel, efx_qword_t *event) | |
8ceee660 BH |
917 | { |
918 | struct efx_nic *efx = channel->efx; | |
919 | unsigned int ev_sub_code; | |
920 | unsigned int ev_sub_data; | |
921 | ||
3e6c4538 BH |
922 | ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE); |
923 | ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); | |
8ceee660 BH |
924 | |
925 | switch (ev_sub_code) { | |
3e6c4538 | 926 | case FSE_AZ_TX_DESCQ_FLS_DONE_EV: |
8ceee660 BH |
927 | EFX_TRACE(efx, "channel %d TXQ %d flushed\n", |
928 | channel->channel, ev_sub_data); | |
929 | break; | |
3e6c4538 | 930 | case FSE_AZ_RX_DESCQ_FLS_DONE_EV: |
8ceee660 BH |
931 | EFX_TRACE(efx, "channel %d RXQ %d flushed\n", |
932 | channel->channel, ev_sub_data); | |
933 | break; | |
3e6c4538 | 934 | case FSE_AZ_EVQ_INIT_DONE_EV: |
8ceee660 BH |
935 | EFX_LOG(efx, "channel %d EVQ %d initialised\n", |
936 | channel->channel, ev_sub_data); | |
937 | break; | |
3e6c4538 | 938 | case FSE_AZ_SRM_UPD_DONE_EV: |
8ceee660 BH |
939 | EFX_TRACE(efx, "channel %d SRAM update done\n", |
940 | channel->channel); | |
941 | break; | |
3e6c4538 | 942 | case FSE_AZ_WAKE_UP_EV: |
8ceee660 BH |
943 | EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n", |
944 | channel->channel, ev_sub_data); | |
945 | break; | |
3e6c4538 | 946 | case FSE_AZ_TIMER_EV: |
8ceee660 BH |
947 | EFX_TRACE(efx, "channel %d RX queue %d timer expired\n", |
948 | channel->channel, ev_sub_data); | |
949 | break; | |
3e6c4538 | 950 | case FSE_AA_RX_RECOVER_EV: |
8ceee660 BH |
951 | EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. " |
952 | "Resetting.\n", channel->channel); | |
05e3ec04 | 953 | atomic_inc(&efx->rx_reset); |
8ceee660 BH |
954 | efx_schedule_reset(efx, |
955 | EFX_WORKAROUND_6555(efx) ? | |
956 | RESET_TYPE_RX_RECOVERY : | |
957 | RESET_TYPE_DISABLE); | |
958 | break; | |
3e6c4538 | 959 | case FSE_BZ_RX_DSC_ERROR_EV: |
8ceee660 BH |
960 | EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error." |
961 | " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data); | |
962 | efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH); | |
963 | break; | |
3e6c4538 | 964 | case FSE_BZ_TX_DSC_ERROR_EV: |
8ceee660 BH |
965 | EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error." |
966 | " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data); | |
967 | efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); | |
968 | break; | |
969 | default: | |
970 | EFX_TRACE(efx, "channel %d unknown driver event code %d " | |
971 | "data %04x\n", channel->channel, ev_sub_code, | |
972 | ev_sub_data); | |
973 | break; | |
974 | } | |
975 | } | |
976 | ||
152b6a62 | 977 | int efx_nic_process_eventq(struct efx_channel *channel, int rx_quota) |
8ceee660 BH |
978 | { |
979 | unsigned int read_ptr; | |
980 | efx_qword_t event, *p_event; | |
981 | int ev_code; | |
42cbe2d7 | 982 | int rx_packets = 0; |
8ceee660 BH |
983 | |
984 | read_ptr = channel->eventq_read_ptr; | |
985 | ||
986 | do { | |
152b6a62 | 987 | p_event = efx_event(channel, read_ptr); |
8ceee660 BH |
988 | event = *p_event; |
989 | ||
152b6a62 | 990 | if (!efx_event_present(&event)) |
8ceee660 BH |
991 | /* End of events */ |
992 | break; | |
993 | ||
994 | EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n", | |
995 | channel->channel, EFX_QWORD_VAL(event)); | |
996 | ||
997 | /* Clear this event by marking it all ones */ | |
998 | EFX_SET_QWORD(*p_event); | |
999 | ||
3e6c4538 | 1000 | ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE); |
8ceee660 BH |
1001 | |
1002 | switch (ev_code) { | |
3e6c4538 | 1003 | case FSE_AZ_EV_CODE_RX_EV: |
152b6a62 | 1004 | efx_handle_rx_event(channel, &event); |
42cbe2d7 | 1005 | ++rx_packets; |
8ceee660 | 1006 | break; |
3e6c4538 | 1007 | case FSE_AZ_EV_CODE_TX_EV: |
152b6a62 | 1008 | efx_handle_tx_event(channel, &event); |
8ceee660 | 1009 | break; |
3e6c4538 BH |
1010 | case FSE_AZ_EV_CODE_DRV_GEN_EV: |
1011 | channel->eventq_magic = EFX_QWORD_FIELD( | |
1012 | event, FSF_AZ_DRV_GEN_EV_MAGIC); | |
8ceee660 BH |
1013 | EFX_LOG(channel->efx, "channel %d received generated " |
1014 | "event "EFX_QWORD_FMT"\n", channel->channel, | |
1015 | EFX_QWORD_VAL(event)); | |
1016 | break; | |
3e6c4538 | 1017 | case FSE_AZ_EV_CODE_GLOBAL_EV: |
152b6a62 | 1018 | efx_handle_global_event(channel, &event); |
8ceee660 | 1019 | break; |
3e6c4538 | 1020 | case FSE_AZ_EV_CODE_DRIVER_EV: |
152b6a62 | 1021 | efx_handle_driver_event(channel, &event); |
8ceee660 BH |
1022 | break; |
1023 | default: | |
1024 | EFX_ERR(channel->efx, "channel %d unknown event type %d" | |
1025 | " (data " EFX_QWORD_FMT ")\n", channel->channel, | |
1026 | ev_code, EFX_QWORD_VAL(event)); | |
1027 | } | |
1028 | ||
1029 | /* Increment read pointer */ | |
3ffeabdd | 1030 | read_ptr = (read_ptr + 1) & EFX_EVQ_MASK; |
8ceee660 | 1031 | |
42cbe2d7 | 1032 | } while (rx_packets < rx_quota); |
8ceee660 BH |
1033 | |
1034 | channel->eventq_read_ptr = read_ptr; | |
42cbe2d7 | 1035 | return rx_packets; |
8ceee660 BH |
1036 | } |
1037 | ||
ef2b90ee | 1038 | static void falcon_push_irq_moderation(struct efx_channel *channel) |
8ceee660 BH |
1039 | { |
1040 | efx_dword_t timer_cmd; | |
1041 | struct efx_nic *efx = channel->efx; | |
1042 | ||
1043 | /* Set timer register */ | |
1044 | if (channel->irq_moderation) { | |
8ceee660 | 1045 | EFX_POPULATE_DWORD_2(timer_cmd, |
3e6c4538 BH |
1046 | FRF_AB_TC_TIMER_MODE, |
1047 | FFE_BB_TIMER_MODE_INT_HLDOFF, | |
1048 | FRF_AB_TC_TIMER_VAL, | |
0d86ebd8 | 1049 | channel->irq_moderation - 1); |
8ceee660 BH |
1050 | } else { |
1051 | EFX_POPULATE_DWORD_2(timer_cmd, | |
3e6c4538 BH |
1052 | FRF_AB_TC_TIMER_MODE, |
1053 | FFE_BB_TIMER_MODE_DIS, | |
1054 | FRF_AB_TC_TIMER_VAL, 0); | |
8ceee660 | 1055 | } |
3e6c4538 | 1056 | BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); |
12d00cad BH |
1057 | efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, |
1058 | channel->channel); | |
8ceee660 BH |
1059 | |
1060 | } | |
1061 | ||
1062 | /* Allocate buffer table entries for event queue */ | |
152b6a62 | 1063 | int efx_nic_probe_eventq(struct efx_channel *channel) |
8ceee660 BH |
1064 | { |
1065 | struct efx_nic *efx = channel->efx; | |
3ffeabdd BH |
1066 | BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 || |
1067 | EFX_EVQ_SIZE & EFX_EVQ_MASK); | |
152b6a62 BH |
1068 | return efx_alloc_special_buffer(efx, &channel->eventq, |
1069 | EFX_EVQ_SIZE * sizeof(efx_qword_t)); | |
8ceee660 BH |
1070 | } |
1071 | ||
152b6a62 | 1072 | void efx_nic_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
1073 | { |
1074 | efx_oword_t evq_ptr; | |
1075 | struct efx_nic *efx = channel->efx; | |
8ceee660 BH |
1076 | |
1077 | EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n", | |
1078 | channel->channel, channel->eventq.index, | |
1079 | channel->eventq.index + channel->eventq.entries - 1); | |
1080 | ||
1081 | /* Pin event queue buffer */ | |
152b6a62 | 1082 | efx_init_special_buffer(efx, &channel->eventq); |
8ceee660 BH |
1083 | |
1084 | /* Fill event queue with all ones (i.e. empty events) */ | |
1085 | memset(channel->eventq.addr, 0xff, channel->eventq.len); | |
1086 | ||
1087 | /* Push event queue to card */ | |
1088 | EFX_POPULATE_OWORD_3(evq_ptr, | |
3e6c4538 | 1089 | FRF_AZ_EVQ_EN, 1, |
3ffeabdd | 1090 | FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries), |
3e6c4538 | 1091 | FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index); |
12d00cad BH |
1092 | efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base, |
1093 | channel->channel); | |
8ceee660 | 1094 | |
152b6a62 | 1095 | efx->type->push_irq_moderation(channel); |
8ceee660 BH |
1096 | } |
1097 | ||
152b6a62 | 1098 | void efx_nic_fini_eventq(struct efx_channel *channel) |
8ceee660 BH |
1099 | { |
1100 | efx_oword_t eventq_ptr; | |
1101 | struct efx_nic *efx = channel->efx; | |
1102 | ||
1103 | /* Remove event queue from card */ | |
1104 | EFX_ZERO_OWORD(eventq_ptr); | |
12d00cad BH |
1105 | efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base, |
1106 | channel->channel); | |
8ceee660 BH |
1107 | |
1108 | /* Unpin event queue */ | |
152b6a62 | 1109 | efx_fini_special_buffer(efx, &channel->eventq); |
8ceee660 BH |
1110 | } |
1111 | ||
1112 | /* Free buffers backing event queue */ | |
152b6a62 | 1113 | void efx_nic_remove_eventq(struct efx_channel *channel) |
8ceee660 | 1114 | { |
152b6a62 | 1115 | efx_free_special_buffer(channel->efx, &channel->eventq); |
8ceee660 BH |
1116 | } |
1117 | ||
1118 | ||
1119 | /* Generates a test event on the event queue. A subsequent call to | |
1120 | * process_eventq() should pick up the event and place the value of | |
1121 | * "magic" into channel->eventq_magic; | |
1122 | */ | |
152b6a62 | 1123 | void efx_nic_generate_test_event(struct efx_channel *channel, unsigned int magic) |
8ceee660 BH |
1124 | { |
1125 | efx_qword_t test_event; | |
1126 | ||
3e6c4538 BH |
1127 | EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE, |
1128 | FSE_AZ_EV_CODE_DRV_GEN_EV, | |
1129 | FSF_AZ_DRV_GEN_EV_MAGIC, magic); | |
152b6a62 | 1130 | efx_generate_event(channel, &test_event); |
8ceee660 BH |
1131 | } |
1132 | ||
6bc5d3a9 BH |
1133 | /************************************************************************** |
1134 | * | |
1135 | * Flush handling | |
1136 | * | |
1137 | **************************************************************************/ | |
1138 | ||
1139 | ||
152b6a62 | 1140 | static void efx_poll_flush_events(struct efx_nic *efx) |
6bc5d3a9 BH |
1141 | { |
1142 | struct efx_channel *channel = &efx->channel[0]; | |
1143 | struct efx_tx_queue *tx_queue; | |
1144 | struct efx_rx_queue *rx_queue; | |
4720bc6c | 1145 | unsigned int read_ptr = channel->eventq_read_ptr; |
3ffeabdd | 1146 | unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK; |
6bc5d3a9 | 1147 | |
4720bc6c | 1148 | do { |
152b6a62 | 1149 | efx_qword_t *event = efx_event(channel, read_ptr); |
6bc5d3a9 BH |
1150 | int ev_code, ev_sub_code, ev_queue; |
1151 | bool ev_failed; | |
4720bc6c | 1152 | |
152b6a62 | 1153 | if (!efx_event_present(event)) |
6bc5d3a9 BH |
1154 | break; |
1155 | ||
3e6c4538 BH |
1156 | ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE); |
1157 | ev_sub_code = EFX_QWORD_FIELD(*event, | |
1158 | FSF_AZ_DRIVER_EV_SUBCODE); | |
1159 | if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV && | |
1160 | ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) { | |
6bc5d3a9 | 1161 | ev_queue = EFX_QWORD_FIELD(*event, |
3e6c4538 | 1162 | FSF_AZ_DRIVER_EV_SUBDATA); |
6bc5d3a9 BH |
1163 | if (ev_queue < EFX_TX_QUEUE_COUNT) { |
1164 | tx_queue = efx->tx_queue + ev_queue; | |
127e6e10 | 1165 | tx_queue->flushed = FLUSH_DONE; |
6bc5d3a9 | 1166 | } |
3e6c4538 BH |
1167 | } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV && |
1168 | ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) { | |
1169 | ev_queue = EFX_QWORD_FIELD( | |
1170 | *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); | |
1171 | ev_failed = EFX_QWORD_FIELD( | |
1172 | *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); | |
6bc5d3a9 BH |
1173 | if (ev_queue < efx->n_rx_queues) { |
1174 | rx_queue = efx->rx_queue + ev_queue; | |
127e6e10 BH |
1175 | rx_queue->flushed = |
1176 | ev_failed ? FLUSH_FAILED : FLUSH_DONE; | |
6bc5d3a9 | 1177 | } |
6bc5d3a9 BH |
1178 | } |
1179 | ||
127e6e10 BH |
1180 | /* We're about to destroy the queue anyway, so |
1181 | * it's ok to throw away every non-flush event */ | |
1182 | EFX_SET_QWORD(*event); | |
1183 | ||
3ffeabdd | 1184 | read_ptr = (read_ptr + 1) & EFX_EVQ_MASK; |
4720bc6c | 1185 | } while (read_ptr != end_ptr); |
127e6e10 BH |
1186 | |
1187 | channel->eventq_read_ptr = read_ptr; | |
1188 | } | |
1189 | ||
d3245b28 BH |
1190 | static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx); |
1191 | ||
127e6e10 BH |
1192 | static void falcon_prepare_flush(struct efx_nic *efx) |
1193 | { | |
1194 | falcon_deconfigure_mac_wrapper(efx); | |
1195 | ||
1196 | /* Wait for the tx and rx fifo's to get to the next packet boundary | |
1197 | * (~1ms without back-pressure), then to drain the remainder of the | |
1198 | * fifo's at data path speeds (negligible), with a healthy margin. */ | |
1199 | msleep(10); | |
6bc5d3a9 BH |
1200 | } |
1201 | ||
1202 | /* Handle tx and rx flushes at the same time, since they run in | |
1203 | * parallel in the hardware and there's no reason for us to | |
1204 | * serialise them */ | |
152b6a62 | 1205 | int efx_nic_flush_queues(struct efx_nic *efx) |
6bc5d3a9 BH |
1206 | { |
1207 | struct efx_rx_queue *rx_queue; | |
1208 | struct efx_tx_queue *tx_queue; | |
127e6e10 | 1209 | int i, tx_pending, rx_pending; |
6bc5d3a9 | 1210 | |
ef2b90ee BH |
1211 | /* If necessary prepare the hardware for flushing */ |
1212 | efx->type->prepare_flush(efx); | |
127e6e10 BH |
1213 | |
1214 | /* Flush all tx queues in parallel */ | |
1215 | efx_for_each_tx_queue(tx_queue, efx) | |
152b6a62 | 1216 | efx_flush_tx_queue(tx_queue); |
6bc5d3a9 | 1217 | |
127e6e10 BH |
1218 | /* The hardware supports four concurrent rx flushes, each of which may |
1219 | * need to be retried if there is an outstanding descriptor fetch */ | |
152b6a62 | 1220 | for (i = 0; i < EFX_FLUSH_POLL_COUNT; ++i) { |
127e6e10 BH |
1221 | rx_pending = tx_pending = 0; |
1222 | efx_for_each_rx_queue(rx_queue, efx) { | |
1223 | if (rx_queue->flushed == FLUSH_PENDING) | |
1224 | ++rx_pending; | |
1225 | } | |
1226 | efx_for_each_rx_queue(rx_queue, efx) { | |
152b6a62 | 1227 | if (rx_pending == EFX_RX_FLUSH_COUNT) |
127e6e10 BH |
1228 | break; |
1229 | if (rx_queue->flushed == FLUSH_FAILED || | |
1230 | rx_queue->flushed == FLUSH_NONE) { | |
152b6a62 | 1231 | efx_flush_rx_queue(rx_queue); |
127e6e10 BH |
1232 | ++rx_pending; |
1233 | } | |
1234 | } | |
1235 | efx_for_each_tx_queue(tx_queue, efx) { | |
1236 | if (tx_queue->flushed != FLUSH_DONE) | |
1237 | ++tx_pending; | |
1238 | } | |
6bc5d3a9 | 1239 | |
127e6e10 | 1240 | if (rx_pending == 0 && tx_pending == 0) |
6bc5d3a9 | 1241 | return 0; |
127e6e10 | 1242 | |
152b6a62 BH |
1243 | msleep(EFX_FLUSH_INTERVAL); |
1244 | efx_poll_flush_events(efx); | |
6bc5d3a9 BH |
1245 | } |
1246 | ||
1247 | /* Mark the queues as all flushed. We're going to return failure | |
127e6e10 | 1248 | * leading to a reset, or fake up success anyway */ |
6bc5d3a9 | 1249 | efx_for_each_tx_queue(tx_queue, efx) { |
127e6e10 | 1250 | if (tx_queue->flushed != FLUSH_DONE) |
6bc5d3a9 BH |
1251 | EFX_ERR(efx, "tx queue %d flush command timed out\n", |
1252 | tx_queue->queue); | |
127e6e10 | 1253 | tx_queue->flushed = FLUSH_DONE; |
6bc5d3a9 BH |
1254 | } |
1255 | efx_for_each_rx_queue(rx_queue, efx) { | |
127e6e10 | 1256 | if (rx_queue->flushed != FLUSH_DONE) |
6bc5d3a9 BH |
1257 | EFX_ERR(efx, "rx queue %d flush command timed out\n", |
1258 | rx_queue->queue); | |
127e6e10 | 1259 | rx_queue->flushed = FLUSH_DONE; |
6bc5d3a9 BH |
1260 | } |
1261 | ||
1262 | if (EFX_WORKAROUND_7803(efx)) | |
1263 | return 0; | |
1264 | ||
1265 | return -ETIMEDOUT; | |
1266 | } | |
8ceee660 BH |
1267 | |
1268 | /************************************************************************** | |
1269 | * | |
152b6a62 | 1270 | * Hardware interrupts |
8ceee660 BH |
1271 | * The hardware interrupt handler does very little work; all the event |
1272 | * queue processing is carried out by per-channel tasklets. | |
1273 | * | |
1274 | **************************************************************************/ | |
1275 | ||
152b6a62 BH |
1276 | /* Enable/disable/generate interrupts */ |
1277 | static inline void efx_nic_interrupts(struct efx_nic *efx, | |
1278 | bool enabled, bool force) | |
8ceee660 BH |
1279 | { |
1280 | efx_oword_t int_en_reg_ker; | |
1281 | ||
1282 | EFX_POPULATE_OWORD_2(int_en_reg_ker, | |
3e6c4538 BH |
1283 | FRF_AZ_KER_INT_KER, force, |
1284 | FRF_AZ_DRV_INT_EN_KER, enabled); | |
12d00cad | 1285 | efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER); |
8ceee660 BH |
1286 | } |
1287 | ||
152b6a62 | 1288 | void efx_nic_enable_interrupts(struct efx_nic *efx) |
8ceee660 | 1289 | { |
8ceee660 BH |
1290 | struct efx_channel *channel; |
1291 | ||
1292 | EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr)); | |
1293 | wmb(); /* Ensure interrupt vector is clear before interrupts enabled */ | |
1294 | ||
8ceee660 | 1295 | /* Enable interrupts */ |
152b6a62 | 1296 | efx_nic_interrupts(efx, true, false); |
8ceee660 BH |
1297 | |
1298 | /* Force processing of all the channels to get the EVQ RPTRs up to | |
1299 | date */ | |
64ee3120 | 1300 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1301 | efx_schedule_channel(channel); |
1302 | } | |
1303 | ||
152b6a62 | 1304 | void efx_nic_disable_interrupts(struct efx_nic *efx) |
8ceee660 BH |
1305 | { |
1306 | /* Disable interrupts */ | |
152b6a62 | 1307 | efx_nic_interrupts(efx, false, false); |
8ceee660 BH |
1308 | } |
1309 | ||
152b6a62 | 1310 | /* Generate a test interrupt |
8ceee660 BH |
1311 | * Interrupt must already have been enabled, otherwise nasty things |
1312 | * may happen. | |
1313 | */ | |
152b6a62 | 1314 | void efx_nic_generate_interrupt(struct efx_nic *efx) |
8ceee660 | 1315 | { |
152b6a62 | 1316 | efx_nic_interrupts(efx, true, true); |
8ceee660 BH |
1317 | } |
1318 | ||
1319 | /* Acknowledge a legacy interrupt from Falcon | |
1320 | * | |
1321 | * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. | |
1322 | * | |
1323 | * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the | |
1324 | * BIU. Interrupt acknowledge is read sensitive so must write instead | |
1325 | * (then read to ensure the BIU collector is flushed) | |
1326 | * | |
1327 | * NB most hardware supports MSI interrupts | |
1328 | */ | |
152b6a62 | 1329 | inline void falcon_irq_ack_a1(struct efx_nic *efx) |
8ceee660 BH |
1330 | { |
1331 | efx_dword_t reg; | |
1332 | ||
3e6c4538 | 1333 | EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); |
12d00cad BH |
1334 | efx_writed(efx, ®, FR_AA_INT_ACK_KER); |
1335 | efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); | |
8ceee660 BH |
1336 | } |
1337 | ||
1338 | /* Process a fatal interrupt | |
1339 | * Disable bus mastering ASAP and schedule a reset | |
1340 | */ | |
152b6a62 | 1341 | irqreturn_t efx_nic_fatal_interrupt(struct efx_nic *efx) |
8ceee660 BH |
1342 | { |
1343 | struct falcon_nic_data *nic_data = efx->nic_data; | |
d3208b5e | 1344 | efx_oword_t *int_ker = efx->irq_status.addr; |
8ceee660 BH |
1345 | efx_oword_t fatal_intr; |
1346 | int error, mem_perr; | |
8ceee660 | 1347 | |
12d00cad | 1348 | efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER); |
3e6c4538 | 1349 | error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR); |
8ceee660 BH |
1350 | |
1351 | EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status " | |
1352 | EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), | |
1353 | EFX_OWORD_VAL(fatal_intr), | |
1354 | error ? "disabling bus mastering" : "no recognised error"); | |
1355 | if (error == 0) | |
1356 | goto out; | |
1357 | ||
1358 | /* If this is a memory parity error dump which blocks are offending */ | |
3e6c4538 | 1359 | mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER); |
8ceee660 BH |
1360 | if (mem_perr) { |
1361 | efx_oword_t reg; | |
12d00cad | 1362 | efx_reado(efx, ®, FR_AZ_MEM_STAT); |
8ceee660 BH |
1363 | EFX_ERR(efx, "SYSTEM ERROR: memory parity error " |
1364 | EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg)); | |
1365 | } | |
1366 | ||
0a62f1a6 | 1367 | /* Disable both devices */ |
ef1bba28 | 1368 | pci_clear_master(efx->pci_dev); |
152b6a62 | 1369 | if (efx_nic_is_dual_func(efx)) |
ef1bba28 | 1370 | pci_clear_master(nic_data->pci_dev2); |
152b6a62 | 1371 | efx_nic_disable_interrupts(efx); |
8ceee660 | 1372 | |
2c3c3d02 | 1373 | /* Count errors and reset or disable the NIC accordingly */ |
0484e0db BH |
1374 | if (efx->int_error_count == 0 || |
1375 | time_after(jiffies, efx->int_error_expire)) { | |
1376 | efx->int_error_count = 0; | |
1377 | efx->int_error_expire = | |
152b6a62 | 1378 | jiffies + EFX_INT_ERROR_EXPIRE * HZ; |
2c3c3d02 | 1379 | } |
152b6a62 | 1380 | if (++efx->int_error_count < EFX_MAX_INT_ERRORS) { |
8ceee660 BH |
1381 | EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n"); |
1382 | efx_schedule_reset(efx, RESET_TYPE_INT_ERROR); | |
1383 | } else { | |
1384 | EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen." | |
1385 | "NIC will be disabled\n"); | |
1386 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1387 | } | |
1388 | out: | |
1389 | return IRQ_HANDLED; | |
1390 | } | |
1391 | ||
152b6a62 | 1392 | /* Handle a legacy interrupt |
8ceee660 BH |
1393 | * Acknowledges the interrupt and schedule event queue processing. |
1394 | */ | |
152b6a62 | 1395 | static irqreturn_t efx_legacy_interrupt(int irq, void *dev_id) |
8ceee660 | 1396 | { |
d3208b5e BH |
1397 | struct efx_nic *efx = dev_id; |
1398 | efx_oword_t *int_ker = efx->irq_status.addr; | |
a9de9a74 | 1399 | irqreturn_t result = IRQ_NONE; |
8ceee660 BH |
1400 | struct efx_channel *channel; |
1401 | efx_dword_t reg; | |
1402 | u32 queues; | |
1403 | int syserr; | |
1404 | ||
1405 | /* Read the ISR which also ACKs the interrupts */ | |
12d00cad | 1406 | efx_readd(efx, ®, FR_BZ_INT_ISR0); |
8ceee660 BH |
1407 | queues = EFX_EXTRACT_DWORD(reg, 0, 31); |
1408 | ||
1409 | /* Check to see if we have a serious error condition */ | |
3e6c4538 | 1410 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
8ceee660 | 1411 | if (unlikely(syserr)) |
152b6a62 | 1412 | return efx_nic_fatal_interrupt(efx); |
8ceee660 | 1413 | |
8ceee660 | 1414 | /* Schedule processing of any interrupting queues */ |
a9de9a74 BH |
1415 | efx_for_each_channel(channel, efx) { |
1416 | if ((queues & 1) || | |
152b6a62 BH |
1417 | efx_event_present( |
1418 | efx_event(channel, channel->eventq_read_ptr))) { | |
8ceee660 | 1419 | efx_schedule_channel(channel); |
a9de9a74 BH |
1420 | result = IRQ_HANDLED; |
1421 | } | |
8ceee660 BH |
1422 | queues >>= 1; |
1423 | } | |
1424 | ||
a9de9a74 BH |
1425 | if (result == IRQ_HANDLED) { |
1426 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1427 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", | |
1428 | irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); | |
1429 | } | |
1430 | ||
1431 | return result; | |
8ceee660 BH |
1432 | } |
1433 | ||
1434 | ||
152b6a62 | 1435 | irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) |
8ceee660 | 1436 | { |
d3208b5e BH |
1437 | struct efx_nic *efx = dev_id; |
1438 | efx_oword_t *int_ker = efx->irq_status.addr; | |
8ceee660 BH |
1439 | struct efx_channel *channel; |
1440 | int syserr; | |
1441 | int queues; | |
1442 | ||
1443 | /* Check to see if this is our interrupt. If it isn't, we | |
1444 | * exit without having touched the hardware. | |
1445 | */ | |
1446 | if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) { | |
1447 | EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq, | |
1448 | raw_smp_processor_id()); | |
1449 | return IRQ_NONE; | |
1450 | } | |
1451 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1452 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
1453 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
1454 | ||
1455 | /* Check to see if we have a serious error condition */ | |
3e6c4538 | 1456 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
8ceee660 | 1457 | if (unlikely(syserr)) |
152b6a62 | 1458 | return efx_nic_fatal_interrupt(efx); |
8ceee660 BH |
1459 | |
1460 | /* Determine interrupting queues, clear interrupt status | |
1461 | * register and acknowledge the device interrupt. | |
1462 | */ | |
674979d3 BH |
1463 | BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS); |
1464 | queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q); | |
8ceee660 BH |
1465 | EFX_ZERO_OWORD(*int_ker); |
1466 | wmb(); /* Ensure the vector is cleared before interrupt ack */ | |
1467 | falcon_irq_ack_a1(efx); | |
1468 | ||
1469 | /* Schedule processing of any interrupting queues */ | |
1470 | channel = &efx->channel[0]; | |
1471 | while (queues) { | |
1472 | if (queues & 0x01) | |
1473 | efx_schedule_channel(channel); | |
1474 | channel++; | |
1475 | queues >>= 1; | |
1476 | } | |
1477 | ||
1478 | return IRQ_HANDLED; | |
1479 | } | |
1480 | ||
152b6a62 | 1481 | /* Handle an MSI interrupt |
8ceee660 BH |
1482 | * |
1483 | * Handle an MSI hardware interrupt. This routine schedules event | |
1484 | * queue processing. No interrupt acknowledgement cycle is necessary. | |
1485 | * Also, we never need to check that the interrupt is for us, since | |
1486 | * MSI interrupts cannot be shared. | |
1487 | */ | |
152b6a62 | 1488 | static irqreturn_t efx_msi_interrupt(int irq, void *dev_id) |
8ceee660 | 1489 | { |
d3208b5e | 1490 | struct efx_channel *channel = dev_id; |
8ceee660 | 1491 | struct efx_nic *efx = channel->efx; |
d3208b5e | 1492 | efx_oword_t *int_ker = efx->irq_status.addr; |
8ceee660 BH |
1493 | int syserr; |
1494 | ||
1495 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1496 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
1497 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
1498 | ||
1499 | /* Check to see if we have a serious error condition */ | |
674979d3 | 1500 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
8ceee660 | 1501 | if (unlikely(syserr)) |
152b6a62 | 1502 | return efx_nic_fatal_interrupt(efx); |
8ceee660 BH |
1503 | |
1504 | /* Schedule processing of the channel */ | |
1505 | efx_schedule_channel(channel); | |
1506 | ||
1507 | return IRQ_HANDLED; | |
1508 | } | |
1509 | ||
1510 | ||
1511 | /* Setup RSS indirection table. | |
1512 | * This maps from the hash value of the packet to RXQ | |
1513 | */ | |
152b6a62 | 1514 | static void efx_setup_rss_indir_table(struct efx_nic *efx) |
8ceee660 BH |
1515 | { |
1516 | int i = 0; | |
1517 | unsigned long offset; | |
1518 | efx_dword_t dword; | |
1519 | ||
daeda630 | 1520 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) |
8ceee660 BH |
1521 | return; |
1522 | ||
3e6c4538 BH |
1523 | for (offset = FR_BZ_RX_INDIRECTION_TBL; |
1524 | offset < FR_BZ_RX_INDIRECTION_TBL + 0x800; | |
8ceee660 | 1525 | offset += 0x10) { |
3e6c4538 | 1526 | EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE, |
8831da7b | 1527 | i % efx->n_rx_queues); |
12d00cad | 1528 | efx_writed(efx, &dword, offset); |
8ceee660 BH |
1529 | i++; |
1530 | } | |
1531 | } | |
1532 | ||
1533 | /* Hook interrupt handler(s) | |
1534 | * Try MSI and then legacy interrupts. | |
1535 | */ | |
152b6a62 | 1536 | int efx_nic_init_interrupt(struct efx_nic *efx) |
8ceee660 BH |
1537 | { |
1538 | struct efx_channel *channel; | |
1539 | int rc; | |
1540 | ||
1541 | if (!EFX_INT_MODE_USE_MSI(efx)) { | |
1542 | irq_handler_t handler; | |
daeda630 | 1543 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
152b6a62 | 1544 | handler = efx_legacy_interrupt; |
8ceee660 BH |
1545 | else |
1546 | handler = falcon_legacy_interrupt_a1; | |
1547 | ||
1548 | rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED, | |
1549 | efx->name, efx); | |
1550 | if (rc) { | |
1551 | EFX_ERR(efx, "failed to hook legacy IRQ %d\n", | |
1552 | efx->pci_dev->irq); | |
1553 | goto fail1; | |
1554 | } | |
1555 | return 0; | |
1556 | } | |
1557 | ||
1558 | /* Hook MSI or MSI-X interrupt */ | |
64ee3120 | 1559 | efx_for_each_channel(channel, efx) { |
152b6a62 | 1560 | rc = request_irq(channel->irq, efx_msi_interrupt, |
8ceee660 | 1561 | IRQF_PROBE_SHARED, /* Not shared */ |
56536e9c | 1562 | channel->name, channel); |
8ceee660 BH |
1563 | if (rc) { |
1564 | EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq); | |
1565 | goto fail2; | |
1566 | } | |
1567 | } | |
1568 | ||
1569 | return 0; | |
1570 | ||
1571 | fail2: | |
64ee3120 | 1572 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1573 | free_irq(channel->irq, channel); |
1574 | fail1: | |
1575 | return rc; | |
1576 | } | |
1577 | ||
152b6a62 | 1578 | void efx_nic_fini_interrupt(struct efx_nic *efx) |
8ceee660 BH |
1579 | { |
1580 | struct efx_channel *channel; | |
1581 | efx_oword_t reg; | |
1582 | ||
1583 | /* Disable MSI/MSI-X interrupts */ | |
64ee3120 | 1584 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1585 | if (channel->irq) |
1586 | free_irq(channel->irq, channel); | |
b3475645 | 1587 | } |
8ceee660 BH |
1588 | |
1589 | /* ACK legacy interrupt */ | |
daeda630 | 1590 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
12d00cad | 1591 | efx_reado(efx, ®, FR_BZ_INT_ISR0); |
8ceee660 BH |
1592 | else |
1593 | falcon_irq_ack_a1(efx); | |
1594 | ||
1595 | /* Disable legacy interrupt */ | |
1596 | if (efx->legacy_irq) | |
1597 | free_irq(efx->legacy_irq, efx); | |
1598 | } | |
1599 | ||
1600 | /************************************************************************** | |
1601 | * | |
1602 | * EEPROM/flash | |
1603 | * | |
1604 | ************************************************************************** | |
1605 | */ | |
1606 | ||
23d30f02 | 1607 | #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t) |
8ceee660 | 1608 | |
be4ea89c BH |
1609 | static int falcon_spi_poll(struct efx_nic *efx) |
1610 | { | |
1611 | efx_oword_t reg; | |
12d00cad | 1612 | efx_reado(efx, ®, FR_AB_EE_SPI_HCMD); |
3e6c4538 | 1613 | return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; |
be4ea89c BH |
1614 | } |
1615 | ||
8ceee660 BH |
1616 | /* Wait for SPI command completion */ |
1617 | static int falcon_spi_wait(struct efx_nic *efx) | |
1618 | { | |
be4ea89c BH |
1619 | /* Most commands will finish quickly, so we start polling at |
1620 | * very short intervals. Sometimes the command may have to | |
1621 | * wait for VPD or expansion ROM access outside of our | |
1622 | * control, so we allow up to 100 ms. */ | |
1623 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10); | |
1624 | int i; | |
1625 | ||
1626 | for (i = 0; i < 10; i++) { | |
1627 | if (!falcon_spi_poll(efx)) | |
1628 | return 0; | |
1629 | udelay(10); | |
1630 | } | |
8ceee660 | 1631 | |
4a5b504d | 1632 | for (;;) { |
be4ea89c | 1633 | if (!falcon_spi_poll(efx)) |
8ceee660 | 1634 | return 0; |
4a5b504d BH |
1635 | if (time_after_eq(jiffies, timeout)) { |
1636 | EFX_ERR(efx, "timed out waiting for SPI\n"); | |
1637 | return -ETIMEDOUT; | |
1638 | } | |
be4ea89c | 1639 | schedule_timeout_uninterruptible(1); |
4a5b504d | 1640 | } |
8ceee660 BH |
1641 | } |
1642 | ||
f4150724 BH |
1643 | int falcon_spi_cmd(const struct efx_spi_device *spi, |
1644 | unsigned int command, int address, | |
23d30f02 | 1645 | const void *in, void *out, size_t len) |
8ceee660 | 1646 | { |
4a5b504d BH |
1647 | struct efx_nic *efx = spi->efx; |
1648 | bool addressed = (address >= 0); | |
1649 | bool reading = (out != NULL); | |
8ceee660 BH |
1650 | efx_oword_t reg; |
1651 | int rc; | |
1652 | ||
4a5b504d BH |
1653 | /* Input validation */ |
1654 | if (len > FALCON_SPI_MAX_LEN) | |
1655 | return -EINVAL; | |
f4150724 | 1656 | BUG_ON(!mutex_is_locked(&efx->spi_lock)); |
8ceee660 | 1657 | |
be4ea89c BH |
1658 | /* Check that previous command is not still running */ |
1659 | rc = falcon_spi_poll(efx); | |
8ceee660 BH |
1660 | if (rc) |
1661 | return rc; | |
1662 | ||
4a5b504d BH |
1663 | /* Program address register, if we have an address */ |
1664 | if (addressed) { | |
3e6c4538 | 1665 | EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); |
12d00cad | 1666 | efx_writeo(efx, ®, FR_AB_EE_SPI_HADR); |
4a5b504d BH |
1667 | } |
1668 | ||
1669 | /* Program data register, if we have data */ | |
1670 | if (in != NULL) { | |
1671 | memcpy(®, in, len); | |
12d00cad | 1672 | efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d | 1673 | } |
8ceee660 | 1674 | |
4a5b504d | 1675 | /* Issue read/write command */ |
8ceee660 | 1676 | EFX_POPULATE_OWORD_7(reg, |
3e6c4538 BH |
1677 | FRF_AB_EE_SPI_HCMD_CMD_EN, 1, |
1678 | FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id, | |
1679 | FRF_AB_EE_SPI_HCMD_DABCNT, len, | |
1680 | FRF_AB_EE_SPI_HCMD_READ, reading, | |
1681 | FRF_AB_EE_SPI_HCMD_DUBCNT, 0, | |
1682 | FRF_AB_EE_SPI_HCMD_ADBCNT, | |
4a5b504d | 1683 | (addressed ? spi->addr_len : 0), |
3e6c4538 | 1684 | FRF_AB_EE_SPI_HCMD_ENC, command); |
12d00cad | 1685 | efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD); |
8ceee660 | 1686 | |
4a5b504d | 1687 | /* Wait for read/write to complete */ |
8ceee660 BH |
1688 | rc = falcon_spi_wait(efx); |
1689 | if (rc) | |
1690 | return rc; | |
1691 | ||
1692 | /* Read data */ | |
4a5b504d | 1693 | if (out != NULL) { |
12d00cad | 1694 | efx_reado(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d BH |
1695 | memcpy(out, ®, len); |
1696 | } | |
1697 | ||
8ceee660 BH |
1698 | return 0; |
1699 | } | |
1700 | ||
23d30f02 BH |
1701 | static size_t |
1702 | falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start) | |
4a5b504d BH |
1703 | { |
1704 | return min(FALCON_SPI_MAX_LEN, | |
1705 | (spi->block_size - (start & (spi->block_size - 1)))); | |
1706 | } | |
1707 | ||
1708 | static inline u8 | |
1709 | efx_spi_munge_command(const struct efx_spi_device *spi, | |
1710 | const u8 command, const unsigned int address) | |
1711 | { | |
1712 | return command | (((address >> 8) & spi->munge_address) << 3); | |
1713 | } | |
1714 | ||
be4ea89c BH |
1715 | /* Wait up to 10 ms for buffered write completion */ |
1716 | int falcon_spi_wait_write(const struct efx_spi_device *spi) | |
4a5b504d | 1717 | { |
be4ea89c BH |
1718 | struct efx_nic *efx = spi->efx; |
1719 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); | |
4a5b504d | 1720 | u8 status; |
be4ea89c | 1721 | int rc; |
4a5b504d | 1722 | |
be4ea89c | 1723 | for (;;) { |
4a5b504d BH |
1724 | rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL, |
1725 | &status, sizeof(status)); | |
1726 | if (rc) | |
1727 | return rc; | |
1728 | if (!(status & SPI_STATUS_NRDY)) | |
1729 | return 0; | |
be4ea89c BH |
1730 | if (time_after_eq(jiffies, timeout)) { |
1731 | EFX_ERR(efx, "SPI write timeout on device %d" | |
1732 | " last status=0x%02x\n", | |
1733 | spi->device_id, status); | |
1734 | return -ETIMEDOUT; | |
1735 | } | |
1736 | schedule_timeout_uninterruptible(1); | |
4a5b504d | 1737 | } |
4a5b504d BH |
1738 | } |
1739 | ||
1740 | int falcon_spi_read(const struct efx_spi_device *spi, loff_t start, | |
1741 | size_t len, size_t *retlen, u8 *buffer) | |
1742 | { | |
23d30f02 BH |
1743 | size_t block_len, pos = 0; |
1744 | unsigned int command; | |
4a5b504d BH |
1745 | int rc = 0; |
1746 | ||
1747 | while (pos < len) { | |
23d30f02 | 1748 | block_len = min(len - pos, FALCON_SPI_MAX_LEN); |
4a5b504d BH |
1749 | |
1750 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
1751 | rc = falcon_spi_cmd(spi, command, start + pos, NULL, | |
1752 | buffer + pos, block_len); | |
1753 | if (rc) | |
1754 | break; | |
1755 | pos += block_len; | |
1756 | ||
1757 | /* Avoid locking up the system */ | |
1758 | cond_resched(); | |
1759 | if (signal_pending(current)) { | |
1760 | rc = -EINTR; | |
1761 | break; | |
1762 | } | |
1763 | } | |
1764 | ||
1765 | if (retlen) | |
1766 | *retlen = pos; | |
1767 | return rc; | |
1768 | } | |
1769 | ||
1770 | int falcon_spi_write(const struct efx_spi_device *spi, loff_t start, | |
1771 | size_t len, size_t *retlen, const u8 *buffer) | |
1772 | { | |
1773 | u8 verify_buffer[FALCON_SPI_MAX_LEN]; | |
23d30f02 BH |
1774 | size_t block_len, pos = 0; |
1775 | unsigned int command; | |
4a5b504d BH |
1776 | int rc = 0; |
1777 | ||
1778 | while (pos < len) { | |
1779 | rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0); | |
1780 | if (rc) | |
1781 | break; | |
1782 | ||
23d30f02 | 1783 | block_len = min(len - pos, |
4a5b504d BH |
1784 | falcon_spi_write_limit(spi, start + pos)); |
1785 | command = efx_spi_munge_command(spi, SPI_WRITE, start + pos); | |
1786 | rc = falcon_spi_cmd(spi, command, start + pos, | |
1787 | buffer + pos, NULL, block_len); | |
1788 | if (rc) | |
1789 | break; | |
1790 | ||
be4ea89c | 1791 | rc = falcon_spi_wait_write(spi); |
4a5b504d BH |
1792 | if (rc) |
1793 | break; | |
1794 | ||
1795 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
1796 | rc = falcon_spi_cmd(spi, command, start + pos, | |
1797 | NULL, verify_buffer, block_len); | |
1798 | if (memcmp(verify_buffer, buffer + pos, block_len)) { | |
1799 | rc = -EIO; | |
1800 | break; | |
1801 | } | |
1802 | ||
1803 | pos += block_len; | |
1804 | ||
1805 | /* Avoid locking up the system */ | |
1806 | cond_resched(); | |
1807 | if (signal_pending(current)) { | |
1808 | rc = -EINTR; | |
1809 | break; | |
1810 | } | |
1811 | } | |
1812 | ||
1813 | if (retlen) | |
1814 | *retlen = pos; | |
1815 | return rc; | |
1816 | } | |
1817 | ||
8ceee660 BH |
1818 | /************************************************************************** |
1819 | * | |
1820 | * MAC wrapper | |
1821 | * | |
1822 | ************************************************************************** | |
1823 | */ | |
177dfcd8 | 1824 | |
ef2b90ee BH |
1825 | static void falcon_push_multicast_hash(struct efx_nic *efx) |
1826 | { | |
1827 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
1828 | ||
1829 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
1830 | ||
1831 | efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); | |
1832 | efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); | |
1833 | } | |
1834 | ||
d3245b28 | 1835 | static void falcon_reset_macs(struct efx_nic *efx) |
8ceee660 | 1836 | { |
d3245b28 BH |
1837 | struct falcon_nic_data *nic_data = efx->nic_data; |
1838 | efx_oword_t reg, mac_ctrl; | |
8ceee660 BH |
1839 | int count; |
1840 | ||
daeda630 | 1841 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { |
177dfcd8 BH |
1842 | /* It's not safe to use GLB_CTL_REG to reset the |
1843 | * macs, so instead use the internal MAC resets | |
1844 | */ | |
1845 | if (!EFX_IS10G(efx)) { | |
3e6c4538 | 1846 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1); |
12d00cad | 1847 | efx_writeo(efx, ®, FR_AB_GM_CFG1); |
177dfcd8 BH |
1848 | udelay(1000); |
1849 | ||
3e6c4538 | 1850 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0); |
12d00cad | 1851 | efx_writeo(efx, ®, FR_AB_GM_CFG1); |
177dfcd8 | 1852 | udelay(1000); |
d3245b28 | 1853 | return; |
177dfcd8 | 1854 | } else { |
3e6c4538 | 1855 | EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); |
12d00cad | 1856 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); |
177dfcd8 BH |
1857 | |
1858 | for (count = 0; count < 10000; count++) { | |
12d00cad | 1859 | efx_reado(efx, ®, FR_AB_XM_GLB_CFG); |
3e6c4538 BH |
1860 | if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == |
1861 | 0) | |
d3245b28 | 1862 | return; |
177dfcd8 BH |
1863 | udelay(10); |
1864 | } | |
8ceee660 | 1865 | |
177dfcd8 | 1866 | EFX_ERR(efx, "timed out waiting for XMAC core reset\n"); |
177dfcd8 BH |
1867 | } |
1868 | } | |
8ceee660 | 1869 | |
d3245b28 BH |
1870 | /* Mac stats will fail whist the TX fifo is draining */ |
1871 | WARN_ON(nic_data->stats_disable_count == 0); | |
8ceee660 | 1872 | |
d3245b28 BH |
1873 | efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL); |
1874 | EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1); | |
1875 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); | |
8ceee660 | 1876 | |
12d00cad | 1877 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
1878 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); |
1879 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); | |
1880 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); | |
12d00cad | 1881 | efx_writeo(efx, ®, FR_AB_GLB_CTL); |
8ceee660 BH |
1882 | |
1883 | count = 0; | |
1884 | while (1) { | |
12d00cad | 1885 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
1886 | if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && |
1887 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && | |
1888 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) { | |
8ceee660 BH |
1889 | EFX_LOG(efx, "Completed MAC reset after %d loops\n", |
1890 | count); | |
1891 | break; | |
1892 | } | |
1893 | if (count > 20) { | |
1894 | EFX_ERR(efx, "MAC reset failed\n"); | |
1895 | break; | |
1896 | } | |
1897 | count++; | |
1898 | udelay(10); | |
1899 | } | |
1900 | ||
d3245b28 BH |
1901 | /* Ensure the correct MAC is selected before statistics |
1902 | * are re-enabled by the caller */ | |
1903 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); | |
177dfcd8 BH |
1904 | } |
1905 | ||
1906 | void falcon_drain_tx_fifo(struct efx_nic *efx) | |
1907 | { | |
1908 | efx_oword_t reg; | |
1909 | ||
daeda630 | 1910 | if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) || |
177dfcd8 BH |
1911 | (efx->loopback_mode != LOOPBACK_NONE)) |
1912 | return; | |
1913 | ||
12d00cad | 1914 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
177dfcd8 | 1915 | /* There is no point in draining more than once */ |
3e6c4538 | 1916 | if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) |
177dfcd8 BH |
1917 | return; |
1918 | ||
1919 | falcon_reset_macs(efx); | |
8ceee660 BH |
1920 | } |
1921 | ||
d3245b28 | 1922 | static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) |
8ceee660 | 1923 | { |
177dfcd8 | 1924 | efx_oword_t reg; |
8ceee660 | 1925 | |
daeda630 | 1926 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) |
8ceee660 BH |
1927 | return; |
1928 | ||
1929 | /* Isolate the MAC -> RX */ | |
12d00cad | 1930 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
3e6c4538 | 1931 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); |
12d00cad | 1932 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 | 1933 | |
d3245b28 BH |
1934 | /* Isolate TX -> MAC */ |
1935 | falcon_drain_tx_fifo(efx); | |
8ceee660 BH |
1936 | } |
1937 | ||
1938 | void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) | |
1939 | { | |
eb50c0d6 | 1940 | struct efx_link_state *link_state = &efx->link_state; |
8ceee660 BH |
1941 | efx_oword_t reg; |
1942 | int link_speed; | |
8ceee660 | 1943 | |
eb50c0d6 | 1944 | switch (link_state->speed) { |
f31a45d2 BH |
1945 | case 10000: link_speed = 3; break; |
1946 | case 1000: link_speed = 2; break; | |
1947 | case 100: link_speed = 1; break; | |
1948 | default: link_speed = 0; break; | |
1949 | } | |
8ceee660 BH |
1950 | /* MAC_LINK_STATUS controls MAC backpressure but doesn't work |
1951 | * as advertised. Disable to ensure packets are not | |
1952 | * indefinitely held and TX queue can be flushed at any point | |
1953 | * while the link is down. */ | |
1954 | EFX_POPULATE_OWORD_5(reg, | |
3e6c4538 BH |
1955 | FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */, |
1956 | FRF_AB_MAC_BCAD_ACPT, 1, | |
1957 | FRF_AB_MAC_UC_PROM, efx->promiscuous, | |
1958 | FRF_AB_MAC_LINK_STATUS, 1, /* always set */ | |
1959 | FRF_AB_MAC_SPEED, link_speed); | |
8ceee660 BH |
1960 | /* On B0, MAC backpressure can be disabled and packets get |
1961 | * discarded. */ | |
daeda630 | 1962 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
3e6c4538 | 1963 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, |
eb50c0d6 | 1964 | !link_state->up); |
8ceee660 BH |
1965 | } |
1966 | ||
12d00cad | 1967 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
8ceee660 BH |
1968 | |
1969 | /* Restore the multicast hash registers. */ | |
8be4f3e6 | 1970 | falcon_push_multicast_hash(efx); |
8ceee660 | 1971 | |
12d00cad | 1972 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
4b0d29dc BH |
1973 | /* Enable XOFF signal from RX FIFO (we enabled it during NIC |
1974 | * initialisation but it may read back as 0) */ | |
1975 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); | |
8ceee660 | 1976 | /* Unisolate the MAC -> RX */ |
daeda630 | 1977 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
3e6c4538 | 1978 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); |
12d00cad | 1979 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 BH |
1980 | } |
1981 | ||
55edc6e6 | 1982 | static void falcon_stats_request(struct efx_nic *efx) |
8ceee660 | 1983 | { |
55edc6e6 | 1984 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 1985 | efx_oword_t reg; |
8ceee660 | 1986 | |
55edc6e6 BH |
1987 | WARN_ON(nic_data->stats_pending); |
1988 | WARN_ON(nic_data->stats_disable_count); | |
8ceee660 | 1989 | |
55edc6e6 BH |
1990 | if (nic_data->stats_dma_done == NULL) |
1991 | return; /* no mac selected */ | |
8ceee660 | 1992 | |
55edc6e6 BH |
1993 | *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE; |
1994 | nic_data->stats_pending = true; | |
8ceee660 BH |
1995 | wmb(); /* ensure done flag is clear */ |
1996 | ||
1997 | /* Initiate DMA transfer of stats */ | |
1998 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
1999 | FRF_AB_MAC_STAT_DMA_CMD, 1, |
2000 | FRF_AB_MAC_STAT_DMA_ADR, | |
8ceee660 | 2001 | efx->stats_buffer.dma_addr); |
12d00cad | 2002 | efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA); |
8ceee660 | 2003 | |
55edc6e6 BH |
2004 | mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2)); |
2005 | } | |
2006 | ||
2007 | static void falcon_stats_complete(struct efx_nic *efx) | |
2008 | { | |
2009 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2010 | ||
2011 | if (!nic_data->stats_pending) | |
2012 | return; | |
2013 | ||
2014 | nic_data->stats_pending = 0; | |
2015 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) { | |
2016 | rmb(); /* read the done flag before the stats */ | |
2017 | efx->mac_op->update_stats(efx); | |
2018 | } else { | |
2019 | EFX_ERR(efx, "timed out waiting for statistics\n"); | |
8ceee660 | 2020 | } |
55edc6e6 | 2021 | } |
8ceee660 | 2022 | |
55edc6e6 BH |
2023 | static void falcon_stats_timer_func(unsigned long context) |
2024 | { | |
2025 | struct efx_nic *efx = (struct efx_nic *)context; | |
2026 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2027 | ||
2028 | spin_lock(&efx->stats_lock); | |
2029 | ||
2030 | falcon_stats_complete(efx); | |
2031 | if (nic_data->stats_disable_count == 0) | |
2032 | falcon_stats_request(efx); | |
2033 | ||
2034 | spin_unlock(&efx->stats_lock); | |
8ceee660 BH |
2035 | } |
2036 | ||
d3245b28 BH |
2037 | static void falcon_switch_mac(struct efx_nic *efx); |
2038 | ||
fdaa9aed SH |
2039 | static bool falcon_loopback_link_poll(struct efx_nic *efx) |
2040 | { | |
2041 | struct efx_link_state old_state = efx->link_state; | |
2042 | ||
2043 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
2044 | WARN_ON(!LOOPBACK_INTERNAL(efx)); | |
2045 | ||
2046 | efx->link_state.fd = true; | |
2047 | efx->link_state.fc = efx->wanted_fc; | |
2048 | efx->link_state.up = true; | |
2049 | ||
2050 | if (efx->loopback_mode == LOOPBACK_GMAC) | |
2051 | efx->link_state.speed = 1000; | |
2052 | else | |
2053 | efx->link_state.speed = 10000; | |
2054 | ||
2055 | return !efx_link_state_equal(&efx->link_state, &old_state); | |
2056 | } | |
2057 | ||
d3245b28 BH |
2058 | static int falcon_reconfigure_port(struct efx_nic *efx) |
2059 | { | |
2060 | int rc; | |
2061 | ||
2062 | WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0); | |
2063 | ||
2064 | /* Poll the PHY link state *before* reconfiguring it. This means we | |
2065 | * will pick up the correct speed (in loopback) to select the correct | |
2066 | * MAC. | |
2067 | */ | |
2068 | if (LOOPBACK_INTERNAL(efx)) | |
2069 | falcon_loopback_link_poll(efx); | |
2070 | else | |
2071 | efx->phy_op->poll(efx); | |
2072 | ||
2073 | falcon_stop_nic_stats(efx); | |
2074 | falcon_deconfigure_mac_wrapper(efx); | |
2075 | ||
2076 | falcon_switch_mac(efx); | |
2077 | ||
2078 | efx->phy_op->reconfigure(efx); | |
2079 | rc = efx->mac_op->reconfigure(efx); | |
2080 | BUG_ON(rc); | |
2081 | ||
2082 | falcon_start_nic_stats(efx); | |
2083 | ||
2084 | /* Synchronise efx->link_state with the kernel */ | |
2085 | efx_link_status_changed(efx); | |
2086 | ||
2087 | return 0; | |
2088 | } | |
2089 | ||
8ceee660 BH |
2090 | /************************************************************************** |
2091 | * | |
2092 | * PHY access via GMII | |
2093 | * | |
2094 | ************************************************************************** | |
2095 | */ | |
2096 | ||
8ceee660 BH |
2097 | /* Wait for GMII access to complete */ |
2098 | static int falcon_gmii_wait(struct efx_nic *efx) | |
2099 | { | |
80cb9a0f | 2100 | efx_oword_t md_stat; |
8ceee660 BH |
2101 | int count; |
2102 | ||
177dfcd8 BH |
2103 | /* wait upto 50ms - taken max from datasheet */ |
2104 | for (count = 0; count < 5000; count++) { | |
80cb9a0f BH |
2105 | efx_reado(efx, &md_stat, FR_AB_MD_STAT); |
2106 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { | |
2107 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || | |
2108 | EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { | |
8ceee660 | 2109 | EFX_ERR(efx, "error from GMII access " |
80cb9a0f BH |
2110 | EFX_OWORD_FMT"\n", |
2111 | EFX_OWORD_VAL(md_stat)); | |
8ceee660 BH |
2112 | return -EIO; |
2113 | } | |
2114 | return 0; | |
2115 | } | |
2116 | udelay(10); | |
2117 | } | |
2118 | EFX_ERR(efx, "timed out waiting for GMII\n"); | |
2119 | return -ETIMEDOUT; | |
2120 | } | |
2121 | ||
68e7f45e BH |
2122 | /* Write an MDIO register of a PHY connected to Falcon. */ |
2123 | static int falcon_mdio_write(struct net_device *net_dev, | |
2124 | int prtad, int devad, u16 addr, u16 value) | |
8ceee660 | 2125 | { |
767e468c | 2126 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2127 | efx_oword_t reg; |
68e7f45e | 2128 | int rc; |
8ceee660 | 2129 | |
68e7f45e BH |
2130 | EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n", |
2131 | prtad, devad, addr, value); | |
8ceee660 | 2132 | |
ab867461 | 2133 | mutex_lock(&efx->mdio_lock); |
8ceee660 | 2134 | |
68e7f45e BH |
2135 | /* Check MDIO not currently being accessed */ |
2136 | rc = falcon_gmii_wait(efx); | |
2137 | if (rc) | |
8ceee660 BH |
2138 | goto out; |
2139 | ||
2140 | /* Write the address/ID register */ | |
3e6c4538 | 2141 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 2142 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 2143 | |
3e6c4538 BH |
2144 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
2145 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 2146 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
2147 | |
2148 | /* Write data */ | |
3e6c4538 | 2149 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); |
12d00cad | 2150 | efx_writeo(efx, ®, FR_AB_MD_TXD); |
8ceee660 BH |
2151 | |
2152 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2153 | FRF_AB_MD_WRC, 1, |
2154 | FRF_AB_MD_GC, 0); | |
12d00cad | 2155 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
2156 | |
2157 | /* Wait for data to be written */ | |
68e7f45e BH |
2158 | rc = falcon_gmii_wait(efx); |
2159 | if (rc) { | |
8ceee660 BH |
2160 | /* Abort the write operation */ |
2161 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2162 | FRF_AB_MD_WRC, 0, |
2163 | FRF_AB_MD_GC, 1); | |
12d00cad | 2164 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
2165 | udelay(10); |
2166 | } | |
2167 | ||
ab867461 SH |
2168 | out: |
2169 | mutex_unlock(&efx->mdio_lock); | |
68e7f45e | 2170 | return rc; |
8ceee660 BH |
2171 | } |
2172 | ||
68e7f45e BH |
2173 | /* Read an MDIO register of a PHY connected to Falcon. */ |
2174 | static int falcon_mdio_read(struct net_device *net_dev, | |
2175 | int prtad, int devad, u16 addr) | |
8ceee660 | 2176 | { |
767e468c | 2177 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2178 | efx_oword_t reg; |
68e7f45e | 2179 | int rc; |
8ceee660 | 2180 | |
ab867461 | 2181 | mutex_lock(&efx->mdio_lock); |
8ceee660 | 2182 | |
68e7f45e BH |
2183 | /* Check MDIO not currently being accessed */ |
2184 | rc = falcon_gmii_wait(efx); | |
2185 | if (rc) | |
8ceee660 BH |
2186 | goto out; |
2187 | ||
3e6c4538 | 2188 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 2189 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 2190 | |
3e6c4538 BH |
2191 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
2192 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 2193 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
2194 | |
2195 | /* Request data to be read */ | |
3e6c4538 | 2196 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); |
12d00cad | 2197 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
2198 | |
2199 | /* Wait for data to become available */ | |
68e7f45e BH |
2200 | rc = falcon_gmii_wait(efx); |
2201 | if (rc == 0) { | |
12d00cad | 2202 | efx_reado(efx, ®, FR_AB_MD_RXD); |
3e6c4538 | 2203 | rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD); |
68e7f45e BH |
2204 | EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n", |
2205 | prtad, devad, addr, rc); | |
8ceee660 BH |
2206 | } else { |
2207 | /* Abort the read operation */ | |
2208 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2209 | FRF_AB_MD_RIC, 0, |
2210 | FRF_AB_MD_GC, 1); | |
12d00cad | 2211 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 | 2212 | |
68e7f45e BH |
2213 | EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n", |
2214 | prtad, devad, addr, rc); | |
8ceee660 BH |
2215 | } |
2216 | ||
ab867461 SH |
2217 | out: |
2218 | mutex_unlock(&efx->mdio_lock); | |
68e7f45e | 2219 | return rc; |
8ceee660 BH |
2220 | } |
2221 | ||
26deba50 SH |
2222 | static void falcon_clock_mac(struct efx_nic *efx) |
2223 | { | |
2224 | unsigned strap_val; | |
2225 | efx_oword_t nic_stat; | |
2226 | ||
2227 | /* Configure the NIC generated MAC clock correctly */ | |
2228 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
2229 | strap_val = EFX_IS10G(efx) ? 5 : 3; | |
daeda630 | 2230 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
26deba50 SH |
2231 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1); |
2232 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val); | |
2233 | efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT); | |
2234 | } else { | |
2235 | /* Falcon A1 does not support 1G/10G speed switching | |
2236 | * and must not be used with a PHY that does. */ | |
2237 | BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) != | |
2238 | strap_val); | |
2239 | } | |
2240 | } | |
2241 | ||
d3245b28 | 2242 | static void falcon_switch_mac(struct efx_nic *efx) |
177dfcd8 BH |
2243 | { |
2244 | struct efx_mac_operations *old_mac_op = efx->mac_op; | |
55edc6e6 BH |
2245 | struct falcon_nic_data *nic_data = efx->nic_data; |
2246 | unsigned int stats_done_offset; | |
177dfcd8 | 2247 | |
0cc12838 | 2248 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
d3245b28 BH |
2249 | WARN_ON(nic_data->stats_disable_count == 0); |
2250 | ||
177dfcd8 BH |
2251 | efx->mac_op = (EFX_IS10G(efx) ? |
2252 | &falcon_xmac_operations : &falcon_gmac_operations); | |
177dfcd8 | 2253 | |
55edc6e6 BH |
2254 | if (EFX_IS10G(efx)) |
2255 | stats_done_offset = XgDmaDone_offset; | |
2256 | else | |
2257 | stats_done_offset = GDmaDone_offset; | |
2258 | nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset; | |
2259 | ||
0cc12838 | 2260 | if (old_mac_op == efx->mac_op) |
d3245b28 | 2261 | return; |
177dfcd8 | 2262 | |
26deba50 SH |
2263 | falcon_clock_mac(efx); |
2264 | ||
177dfcd8 | 2265 | EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G'); |
0cc12838 | 2266 | /* Not all macs support a mac-level link state */ |
9007b9fa | 2267 | efx->xmac_poll_required = false; |
d3245b28 | 2268 | falcon_reset_macs(efx); |
177dfcd8 BH |
2269 | } |
2270 | ||
8ceee660 | 2271 | /* This call is responsible for hooking in the MAC and PHY operations */ |
ef2b90ee | 2272 | static int falcon_probe_port(struct efx_nic *efx) |
8ceee660 BH |
2273 | { |
2274 | int rc; | |
2275 | ||
96c45726 BH |
2276 | switch (efx->phy_type) { |
2277 | case PHY_TYPE_SFX7101: | |
2278 | efx->phy_op = &falcon_sfx7101_phy_ops; | |
2279 | break; | |
2280 | case PHY_TYPE_SFT9001A: | |
2281 | case PHY_TYPE_SFT9001B: | |
2282 | efx->phy_op = &falcon_sft9001_phy_ops; | |
2283 | break; | |
2284 | case PHY_TYPE_QT2022C2: | |
2285 | case PHY_TYPE_QT2025C: | |
b37b62fe | 2286 | efx->phy_op = &falcon_qt202x_phy_ops; |
96c45726 BH |
2287 | break; |
2288 | default: | |
2289 | EFX_ERR(efx, "Unknown PHY type %d\n", | |
2290 | efx->phy_type); | |
2291 | return -ENODEV; | |
2292 | } | |
2293 | ||
2294 | if (efx->phy_op->macs & EFX_XMAC) | |
2295 | efx->loopback_modes |= ((1 << LOOPBACK_XGMII) | | |
2296 | (1 << LOOPBACK_XGXS) | | |
2297 | (1 << LOOPBACK_XAUI)); | |
2298 | if (efx->phy_op->macs & EFX_GMAC) | |
2299 | efx->loopback_modes |= (1 << LOOPBACK_GMAC); | |
2300 | efx->loopback_modes |= efx->phy_op->loopbacks; | |
8ceee660 | 2301 | |
68e7f45e BH |
2302 | /* Set up MDIO structure for PHY */ |
2303 | efx->mdio.mmds = efx->phy_op->mmds; | |
2304 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
2305 | efx->mdio.mdio_read = falcon_mdio_read; | |
2306 | efx->mdio.mdio_write = falcon_mdio_write; | |
8ceee660 | 2307 | |
b895d73e SH |
2308 | /* Initial assumption */ |
2309 | efx->link_state.speed = 10000; | |
2310 | efx->link_state.fd = true; | |
2311 | ||
8ceee660 | 2312 | /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ |
daeda630 | 2313 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
04cc8cac | 2314 | efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; |
8ceee660 | 2315 | else |
04cc8cac | 2316 | efx->wanted_fc = EFX_FC_RX; |
8ceee660 BH |
2317 | |
2318 | /* Allocate buffer for stats */ | |
152b6a62 BH |
2319 | rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, |
2320 | FALCON_MAC_STATS_SIZE); | |
8ceee660 BH |
2321 | if (rc) |
2322 | return rc; | |
9c8976a1 JSR |
2323 | EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n", |
2324 | (u64)efx->stats_buffer.dma_addr, | |
8ceee660 | 2325 | efx->stats_buffer.addr, |
9c8976a1 | 2326 | (u64)virt_to_phys(efx->stats_buffer.addr)); |
8ceee660 BH |
2327 | |
2328 | return 0; | |
2329 | } | |
2330 | ||
ef2b90ee | 2331 | static void falcon_remove_port(struct efx_nic *efx) |
8ceee660 | 2332 | { |
152b6a62 | 2333 | efx_nic_free_buffer(efx, &efx->stats_buffer); |
8ceee660 BH |
2334 | } |
2335 | ||
8c8661e4 BH |
2336 | /************************************************************************** |
2337 | * | |
2338 | * Falcon test code | |
2339 | * | |
2340 | **************************************************************************/ | |
2341 | ||
0aa3fbaa BH |
2342 | static int |
2343 | falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out) | |
8c8661e4 BH |
2344 | { |
2345 | struct falcon_nvconfig *nvconfig; | |
2346 | struct efx_spi_device *spi; | |
2347 | void *region; | |
2348 | int rc, magic_num, struct_ver; | |
2349 | __le16 *word, *limit; | |
2350 | u32 csum; | |
2351 | ||
2f7f5730 BH |
2352 | spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom; |
2353 | if (!spi) | |
2354 | return -EINVAL; | |
2355 | ||
0a95f563 | 2356 | region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); |
8c8661e4 BH |
2357 | if (!region) |
2358 | return -ENOMEM; | |
3e6c4538 | 2359 | nvconfig = region + FALCON_NVCONFIG_OFFSET; |
8c8661e4 | 2360 | |
f4150724 | 2361 | mutex_lock(&efx->spi_lock); |
0a95f563 | 2362 | rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region); |
f4150724 | 2363 | mutex_unlock(&efx->spi_lock); |
8c8661e4 BH |
2364 | if (rc) { |
2365 | EFX_ERR(efx, "Failed to read %s\n", | |
2366 | efx->spi_flash ? "flash" : "EEPROM"); | |
2367 | rc = -EIO; | |
2368 | goto out; | |
2369 | } | |
2370 | ||
2371 | magic_num = le16_to_cpu(nvconfig->board_magic_num); | |
2372 | struct_ver = le16_to_cpu(nvconfig->board_struct_ver); | |
2373 | ||
2374 | rc = -EINVAL; | |
3e6c4538 | 2375 | if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) { |
8c8661e4 BH |
2376 | EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num); |
2377 | goto out; | |
2378 | } | |
2379 | if (struct_ver < 2) { | |
2380 | EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver); | |
2381 | goto out; | |
2382 | } else if (struct_ver < 4) { | |
2383 | word = &nvconfig->board_magic_num; | |
2384 | limit = (__le16 *) (nvconfig + 1); | |
2385 | } else { | |
2386 | word = region; | |
0a95f563 | 2387 | limit = region + FALCON_NVCONFIG_END; |
8c8661e4 BH |
2388 | } |
2389 | for (csum = 0; word < limit; ++word) | |
2390 | csum += le16_to_cpu(*word); | |
2391 | ||
2392 | if (~csum & 0xffff) { | |
2393 | EFX_ERR(efx, "NVRAM has incorrect checksum\n"); | |
2394 | goto out; | |
2395 | } | |
2396 | ||
2397 | rc = 0; | |
2398 | if (nvconfig_out) | |
2399 | memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig)); | |
2400 | ||
2401 | out: | |
2402 | kfree(region); | |
2403 | return rc; | |
2404 | } | |
2405 | ||
0aa3fbaa BH |
2406 | static int falcon_test_nvram(struct efx_nic *efx) |
2407 | { | |
2408 | return falcon_read_nvram(efx, NULL); | |
2409 | } | |
2410 | ||
152b6a62 | 2411 | static const struct efx_nic_register_test falcon_b0_register_tests[] = { |
3e6c4538 | 2412 | { FR_AZ_ADR_REGION, |
8c8661e4 | 2413 | EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) }, |
3e6c4538 | 2414 | { FR_AZ_RX_CFG, |
8c8661e4 | 2415 | EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, |
3e6c4538 | 2416 | { FR_AZ_TX_CFG, |
8c8661e4 | 2417 | EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2418 | { FR_AZ_TX_RESERVED, |
8c8661e4 | 2419 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, |
3e6c4538 | 2420 | { FR_AB_MAC_CTRL, |
8c8661e4 | 2421 | EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2422 | { FR_AZ_SRM_TX_DC_CFG, |
8c8661e4 | 2423 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2424 | { FR_AZ_RX_DC_CFG, |
8c8661e4 | 2425 | EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2426 | { FR_AZ_RX_DC_PF_WM, |
8c8661e4 | 2427 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2428 | { FR_BZ_DP_CTRL, |
8c8661e4 | 2429 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2430 | { FR_AB_GM_CFG2, |
177dfcd8 | 2431 | EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2432 | { FR_AB_GMF_CFG0, |
177dfcd8 | 2433 | EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2434 | { FR_AB_XM_GLB_CFG, |
8c8661e4 | 2435 | EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2436 | { FR_AB_XM_TX_CFG, |
8c8661e4 | 2437 | EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2438 | { FR_AB_XM_RX_CFG, |
8c8661e4 | 2439 | EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2440 | { FR_AB_XM_RX_PARAM, |
8c8661e4 | 2441 | EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2442 | { FR_AB_XM_FC, |
8c8661e4 | 2443 | EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2444 | { FR_AB_XM_ADR_LO, |
8c8661e4 | 2445 | EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2446 | { FR_AB_XX_SD_CTL, |
8c8661e4 BH |
2447 | EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, |
2448 | }; | |
2449 | ||
2450 | static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b, | |
2451 | const efx_oword_t *mask) | |
2452 | { | |
2453 | return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) || | |
2454 | ((a->u64[1] ^ b->u64[1]) & mask->u64[1]); | |
2455 | } | |
2456 | ||
152b6a62 BH |
2457 | int efx_nic_test_registers(struct efx_nic *efx, |
2458 | const struct efx_nic_register_test *regs, | |
2459 | size_t n_regs) | |
8c8661e4 BH |
2460 | { |
2461 | unsigned address = 0, i, j; | |
2462 | efx_oword_t mask, imask, original, reg, buf; | |
2463 | ||
2464 | /* Falcon should be in loopback to isolate the XMAC from the PHY */ | |
2465 | WARN_ON(!LOOPBACK_INTERNAL(efx)); | |
2466 | ||
152b6a62 BH |
2467 | for (i = 0; i < n_regs; ++i) { |
2468 | address = regs[i].address; | |
2469 | mask = imask = regs[i].mask; | |
8c8661e4 BH |
2470 | EFX_INVERT_OWORD(imask); |
2471 | ||
12d00cad | 2472 | efx_reado(efx, &original, address); |
8c8661e4 BH |
2473 | |
2474 | /* bit sweep on and off */ | |
2475 | for (j = 0; j < 128; j++) { | |
2476 | if (!EFX_EXTRACT_OWORD32(mask, j, j)) | |
2477 | continue; | |
2478 | ||
2479 | /* Test this testable bit can be set in isolation */ | |
2480 | EFX_AND_OWORD(reg, original, mask); | |
2481 | EFX_SET_OWORD32(reg, j, j, 1); | |
2482 | ||
12d00cad BH |
2483 | efx_writeo(efx, ®, address); |
2484 | efx_reado(efx, &buf, address); | |
8c8661e4 BH |
2485 | |
2486 | if (efx_masked_compare_oword(®, &buf, &mask)) | |
2487 | goto fail; | |
2488 | ||
2489 | /* Test this testable bit can be cleared in isolation */ | |
2490 | EFX_OR_OWORD(reg, original, mask); | |
2491 | EFX_SET_OWORD32(reg, j, j, 0); | |
2492 | ||
12d00cad BH |
2493 | efx_writeo(efx, ®, address); |
2494 | efx_reado(efx, &buf, address); | |
8c8661e4 BH |
2495 | |
2496 | if (efx_masked_compare_oword(®, &buf, &mask)) | |
2497 | goto fail; | |
2498 | } | |
2499 | ||
12d00cad | 2500 | efx_writeo(efx, &original, address); |
8c8661e4 BH |
2501 | } |
2502 | ||
2503 | return 0; | |
2504 | ||
2505 | fail: | |
2506 | EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT | |
2507 | " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg), | |
2508 | EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask)); | |
2509 | return -EIO; | |
2510 | } | |
2511 | ||
152b6a62 BH |
2512 | static int falcon_b0_test_registers(struct efx_nic *efx) |
2513 | { | |
2514 | return efx_nic_test_registers(efx, falcon_b0_register_tests, | |
2515 | ARRAY_SIZE(falcon_b0_register_tests)); | |
2516 | } | |
2517 | ||
8ceee660 BH |
2518 | /************************************************************************** |
2519 | * | |
2520 | * Device reset | |
2521 | * | |
2522 | ************************************************************************** | |
2523 | */ | |
2524 | ||
2525 | /* Resets NIC to known state. This routine must be called in process | |
2526 | * context and is allowed to sleep. */ | |
ef2b90ee | 2527 | static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) |
8ceee660 BH |
2528 | { |
2529 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2530 | efx_oword_t glb_ctl_reg_ker; | |
2531 | int rc; | |
2532 | ||
c459302d | 2533 | EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method)); |
8ceee660 BH |
2534 | |
2535 | /* Initiate device reset */ | |
2536 | if (method == RESET_TYPE_WORLD) { | |
2537 | rc = pci_save_state(efx->pci_dev); | |
2538 | if (rc) { | |
2539 | EFX_ERR(efx, "failed to backup PCI state of primary " | |
2540 | "function prior to hardware reset\n"); | |
2541 | goto fail1; | |
2542 | } | |
152b6a62 | 2543 | if (efx_nic_is_dual_func(efx)) { |
8ceee660 BH |
2544 | rc = pci_save_state(nic_data->pci_dev2); |
2545 | if (rc) { | |
2546 | EFX_ERR(efx, "failed to backup PCI state of " | |
2547 | "secondary function prior to " | |
2548 | "hardware reset\n"); | |
2549 | goto fail2; | |
2550 | } | |
2551 | } | |
2552 | ||
2553 | EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, | |
3e6c4538 BH |
2554 | FRF_AB_EXT_PHY_RST_DUR, |
2555 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
2556 | FRF_AB_SWRST, 1); | |
8ceee660 | 2557 | } else { |
8ceee660 | 2558 | EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, |
3e6c4538 BH |
2559 | /* exclude PHY from "invisible" reset */ |
2560 | FRF_AB_EXT_PHY_RST_CTL, | |
2561 | method == RESET_TYPE_INVISIBLE, | |
2562 | /* exclude EEPROM/flash and PCIe */ | |
2563 | FRF_AB_PCIE_CORE_RST_CTL, 1, | |
2564 | FRF_AB_PCIE_NSTKY_RST_CTL, 1, | |
2565 | FRF_AB_PCIE_SD_RST_CTL, 1, | |
2566 | FRF_AB_EE_RST_CTL, 1, | |
2567 | FRF_AB_EXT_PHY_RST_DUR, | |
2568 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
2569 | FRF_AB_SWRST, 1); | |
2570 | } | |
12d00cad | 2571 | efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
8ceee660 BH |
2572 | |
2573 | EFX_LOG(efx, "waiting for hardware reset\n"); | |
2574 | schedule_timeout_uninterruptible(HZ / 20); | |
2575 | ||
2576 | /* Restore PCI configuration if needed */ | |
2577 | if (method == RESET_TYPE_WORLD) { | |
152b6a62 | 2578 | if (efx_nic_is_dual_func(efx)) { |
8ceee660 BH |
2579 | rc = pci_restore_state(nic_data->pci_dev2); |
2580 | if (rc) { | |
2581 | EFX_ERR(efx, "failed to restore PCI config for " | |
2582 | "the secondary function\n"); | |
2583 | goto fail3; | |
2584 | } | |
2585 | } | |
2586 | rc = pci_restore_state(efx->pci_dev); | |
2587 | if (rc) { | |
2588 | EFX_ERR(efx, "failed to restore PCI config for the " | |
2589 | "primary function\n"); | |
2590 | goto fail4; | |
2591 | } | |
2592 | EFX_LOG(efx, "successfully restored PCI config\n"); | |
2593 | } | |
2594 | ||
2595 | /* Assert that reset complete */ | |
12d00cad | 2596 | efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
3e6c4538 | 2597 | if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { |
8ceee660 BH |
2598 | rc = -ETIMEDOUT; |
2599 | EFX_ERR(efx, "timed out waiting for hardware reset\n"); | |
2600 | goto fail5; | |
2601 | } | |
2602 | EFX_LOG(efx, "hardware reset complete\n"); | |
2603 | ||
2604 | return 0; | |
2605 | ||
2606 | /* pci_save_state() and pci_restore_state() MUST be called in pairs */ | |
2607 | fail2: | |
2608 | fail3: | |
2609 | pci_restore_state(efx->pci_dev); | |
2610 | fail1: | |
2611 | fail4: | |
2612 | fail5: | |
2613 | return rc; | |
2614 | } | |
2615 | ||
ef2b90ee | 2616 | static void falcon_monitor(struct efx_nic *efx) |
fe75820b | 2617 | { |
fdaa9aed | 2618 | bool link_changed; |
fe75820b BH |
2619 | int rc; |
2620 | ||
fdaa9aed SH |
2621 | BUG_ON(!mutex_is_locked(&efx->mac_lock)); |
2622 | ||
fe75820b BH |
2623 | rc = falcon_board(efx)->type->monitor(efx); |
2624 | if (rc) { | |
2625 | EFX_ERR(efx, "Board sensor %s; shutting down PHY\n", | |
2626 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
2627 | efx->phy_mode |= PHY_MODE_LOW_POWER; | |
d3245b28 BH |
2628 | rc = __efx_reconfigure_port(efx); |
2629 | WARN_ON(rc); | |
fe75820b | 2630 | } |
fdaa9aed SH |
2631 | |
2632 | if (LOOPBACK_INTERNAL(efx)) | |
2633 | link_changed = falcon_loopback_link_poll(efx); | |
2634 | else | |
2635 | link_changed = efx->phy_op->poll(efx); | |
2636 | ||
2637 | if (link_changed) { | |
2638 | falcon_stop_nic_stats(efx); | |
2639 | falcon_deconfigure_mac_wrapper(efx); | |
2640 | ||
2641 | falcon_switch_mac(efx); | |
d3245b28 BH |
2642 | rc = efx->mac_op->reconfigure(efx); |
2643 | BUG_ON(rc); | |
fdaa9aed SH |
2644 | |
2645 | falcon_start_nic_stats(efx); | |
2646 | ||
2647 | efx_link_status_changed(efx); | |
2648 | } | |
2649 | ||
9007b9fa BH |
2650 | if (EFX_IS10G(efx)) |
2651 | falcon_poll_xmac(efx); | |
fe75820b BH |
2652 | } |
2653 | ||
8ceee660 BH |
2654 | /* Zeroes out the SRAM contents. This routine must be called in |
2655 | * process context and is allowed to sleep. | |
2656 | */ | |
2657 | static int falcon_reset_sram(struct efx_nic *efx) | |
2658 | { | |
2659 | efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; | |
2660 | int count; | |
2661 | ||
2662 | /* Set the SRAM wake/sleep GPIO appropriately. */ | |
12d00cad | 2663 | efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
3e6c4538 BH |
2664 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); |
2665 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); | |
12d00cad | 2666 | efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
8ceee660 BH |
2667 | |
2668 | /* Initiate SRAM reset */ | |
2669 | EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, | |
3e6c4538 BH |
2670 | FRF_AZ_SRM_INIT_EN, 1, |
2671 | FRF_AZ_SRM_NB_SZ, 0); | |
12d00cad | 2672 | efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
8ceee660 BH |
2673 | |
2674 | /* Wait for SRAM reset to complete */ | |
2675 | count = 0; | |
2676 | do { | |
2677 | EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count); | |
2678 | ||
2679 | /* SRAM reset is slow; expect around 16ms */ | |
2680 | schedule_timeout_uninterruptible(HZ / 50); | |
2681 | ||
2682 | /* Check for reset complete */ | |
12d00cad | 2683 | efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
3e6c4538 | 2684 | if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { |
8ceee660 BH |
2685 | EFX_LOG(efx, "SRAM reset complete\n"); |
2686 | ||
2687 | return 0; | |
2688 | } | |
2689 | } while (++count < 20); /* wait upto 0.4 sec */ | |
2690 | ||
2691 | EFX_ERR(efx, "timed out waiting for SRAM reset\n"); | |
2692 | return -ETIMEDOUT; | |
2693 | } | |
2694 | ||
4a5b504d BH |
2695 | static int falcon_spi_device_init(struct efx_nic *efx, |
2696 | struct efx_spi_device **spi_device_ret, | |
2697 | unsigned int device_id, u32 device_type) | |
2698 | { | |
2699 | struct efx_spi_device *spi_device; | |
2700 | ||
2701 | if (device_type != 0) { | |
0c53d8c8 | 2702 | spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL); |
4a5b504d BH |
2703 | if (!spi_device) |
2704 | return -ENOMEM; | |
2705 | spi_device->device_id = device_id; | |
2706 | spi_device->size = | |
2707 | 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE); | |
2708 | spi_device->addr_len = | |
2709 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN); | |
2710 | spi_device->munge_address = (spi_device->size == 1 << 9 && | |
2711 | spi_device->addr_len == 1); | |
f4150724 BH |
2712 | spi_device->erase_command = |
2713 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD); | |
2714 | spi_device->erase_size = | |
2715 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
2716 | SPI_DEV_TYPE_ERASE_SIZE); | |
4a5b504d BH |
2717 | spi_device->block_size = |
2718 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
2719 | SPI_DEV_TYPE_BLOCK_SIZE); | |
2720 | ||
2721 | spi_device->efx = efx; | |
2722 | } else { | |
2723 | spi_device = NULL; | |
2724 | } | |
2725 | ||
2726 | kfree(*spi_device_ret); | |
2727 | *spi_device_ret = spi_device; | |
2728 | return 0; | |
2729 | } | |
2730 | ||
2731 | ||
2732 | static void falcon_remove_spi_devices(struct efx_nic *efx) | |
2733 | { | |
2734 | kfree(efx->spi_eeprom); | |
2735 | efx->spi_eeprom = NULL; | |
2736 | kfree(efx->spi_flash); | |
2737 | efx->spi_flash = NULL; | |
2738 | } | |
2739 | ||
8ceee660 BH |
2740 | /* Extract non-volatile configuration */ |
2741 | static int falcon_probe_nvconfig(struct efx_nic *efx) | |
2742 | { | |
2743 | struct falcon_nvconfig *nvconfig; | |
8c8661e4 | 2744 | int board_rev; |
8ceee660 BH |
2745 | int rc; |
2746 | ||
8ceee660 | 2747 | nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); |
4a5b504d BH |
2748 | if (!nvconfig) |
2749 | return -ENOMEM; | |
8ceee660 | 2750 | |
8c8661e4 BH |
2751 | rc = falcon_read_nvram(efx, nvconfig); |
2752 | if (rc == -EINVAL) { | |
2753 | EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n"); | |
8ceee660 | 2754 | efx->phy_type = PHY_TYPE_NONE; |
68e7f45e | 2755 | efx->mdio.prtad = MDIO_PRTAD_NONE; |
8ceee660 | 2756 | board_rev = 0; |
8c8661e4 BH |
2757 | rc = 0; |
2758 | } else if (rc) { | |
2759 | goto fail1; | |
8ceee660 BH |
2760 | } else { |
2761 | struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2; | |
4a5b504d | 2762 | struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3; |
8ceee660 BH |
2763 | |
2764 | efx->phy_type = v2->port0_phy_type; | |
68e7f45e | 2765 | efx->mdio.prtad = v2->port0_phy_addr; |
8ceee660 | 2766 | board_rev = le16_to_cpu(v2->board_revision); |
4a5b504d | 2767 | |
8c8661e4 | 2768 | if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { |
3e6c4538 BH |
2769 | rc = falcon_spi_device_init( |
2770 | efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH, | |
2771 | le32_to_cpu(v3->spi_device_type | |
2772 | [FFE_AB_SPI_DEVICE_FLASH])); | |
4a5b504d BH |
2773 | if (rc) |
2774 | goto fail2; | |
3e6c4538 BH |
2775 | rc = falcon_spi_device_init( |
2776 | efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM, | |
2777 | le32_to_cpu(v3->spi_device_type | |
2778 | [FFE_AB_SPI_DEVICE_EEPROM])); | |
4a5b504d BH |
2779 | if (rc) |
2780 | goto fail2; | |
2781 | } | |
8ceee660 BH |
2782 | } |
2783 | ||
8c8661e4 BH |
2784 | /* Read the MAC addresses */ |
2785 | memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN); | |
2786 | ||
68e7f45e | 2787 | EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad); |
8ceee660 | 2788 | |
3473a5b1 | 2789 | falcon_probe_board(efx, board_rev); |
8ceee660 | 2790 | |
4a5b504d BH |
2791 | kfree(nvconfig); |
2792 | return 0; | |
2793 | ||
2794 | fail2: | |
2795 | falcon_remove_spi_devices(efx); | |
2796 | fail1: | |
8ceee660 BH |
2797 | kfree(nvconfig); |
2798 | return rc; | |
2799 | } | |
2800 | ||
152b6a62 BH |
2801 | u32 efx_nic_fpga_ver(struct efx_nic *efx) |
2802 | { | |
2803 | efx_oword_t altera_build; | |
2804 | ||
2805 | efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD); | |
2806 | return EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER); | |
2807 | } | |
2808 | ||
8ceee660 BH |
2809 | /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port |
2810 | * count, port speed). Set workaround and feature flags accordingly. | |
2811 | */ | |
2812 | static int falcon_probe_nic_variant(struct efx_nic *efx) | |
2813 | { | |
177dfcd8 | 2814 | efx_oword_t nic_stat; |
8ceee660 | 2815 | |
152b6a62 | 2816 | if (efx_nic_fpga_ver(efx) != 0) { |
8ceee660 BH |
2817 | EFX_ERR(efx, "Falcon FPGA not supported\n"); |
2818 | return -ENODEV; | |
2819 | } | |
2820 | ||
12d00cad | 2821 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); |
177dfcd8 | 2822 | |
daeda630 BH |
2823 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { |
2824 | u8 pci_rev = efx->pci_dev->revision; | |
8ceee660 | 2825 | |
daeda630 BH |
2826 | if ((pci_rev == 0xff) || (pci_rev == 0)) { |
2827 | EFX_ERR(efx, "Falcon rev A0 not supported\n"); | |
2828 | return -ENODEV; | |
2829 | } | |
b895d73e SH |
2830 | if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) { |
2831 | EFX_ERR(efx, "Falcon rev A1 1G not supported\n"); | |
2832 | return -ENODEV; | |
2833 | } | |
3e6c4538 | 2834 | if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) { |
8ceee660 BH |
2835 | EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n"); |
2836 | return -ENODEV; | |
2837 | } | |
8ceee660 BH |
2838 | } |
2839 | ||
2840 | return 0; | |
2841 | } | |
2842 | ||
4a5b504d BH |
2843 | /* Probe all SPI devices on the NIC */ |
2844 | static void falcon_probe_spi_devices(struct efx_nic *efx) | |
2845 | { | |
2846 | efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; | |
2f7f5730 | 2847 | int boot_dev; |
4a5b504d | 2848 | |
12d00cad BH |
2849 | efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL); |
2850 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
2851 | efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); | |
4a5b504d | 2852 | |
3e6c4538 BH |
2853 | if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { |
2854 | boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? | |
2855 | FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM); | |
2f7f5730 | 2856 | EFX_LOG(efx, "Booted from %s\n", |
3e6c4538 | 2857 | boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM"); |
2f7f5730 BH |
2858 | } else { |
2859 | /* Disable VPD and set clock dividers to safe | |
2860 | * values for initial programming. */ | |
2861 | boot_dev = -1; | |
2862 | EFX_LOG(efx, "Booted from internal ASIC settings;" | |
2863 | " setting SPI config\n"); | |
3e6c4538 | 2864 | EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0, |
2f7f5730 | 2865 | /* 125 MHz / 7 ~= 20 MHz */ |
3e6c4538 | 2866 | FRF_AB_EE_SF_CLOCK_DIV, 7, |
2f7f5730 | 2867 | /* 125 MHz / 63 ~= 2 MHz */ |
3e6c4538 | 2868 | FRF_AB_EE_EE_CLOCK_DIV, 63); |
12d00cad | 2869 | efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); |
4a5b504d BH |
2870 | } |
2871 | ||
3e6c4538 BH |
2872 | if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) |
2873 | falcon_spi_device_init(efx, &efx->spi_flash, | |
2874 | FFE_AB_SPI_DEVICE_FLASH, | |
2f7f5730 | 2875 | default_flash_type); |
3e6c4538 BH |
2876 | if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM) |
2877 | falcon_spi_device_init(efx, &efx->spi_eeprom, | |
2878 | FFE_AB_SPI_DEVICE_EEPROM, | |
2f7f5730 | 2879 | large_eeprom_type); |
4a5b504d BH |
2880 | } |
2881 | ||
ef2b90ee | 2882 | static int falcon_probe_nic(struct efx_nic *efx) |
8ceee660 BH |
2883 | { |
2884 | struct falcon_nic_data *nic_data; | |
e775fb93 | 2885 | struct falcon_board *board; |
8ceee660 BH |
2886 | int rc; |
2887 | ||
8ceee660 BH |
2888 | /* Allocate storage for hardware specific data */ |
2889 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); | |
88c59425 BH |
2890 | if (!nic_data) |
2891 | return -ENOMEM; | |
5daab96d | 2892 | efx->nic_data = nic_data; |
8ceee660 BH |
2893 | |
2894 | /* Determine number of ports etc. */ | |
2895 | rc = falcon_probe_nic_variant(efx); | |
2896 | if (rc) | |
2897 | goto fail1; | |
2898 | ||
2899 | /* Probe secondary function if expected */ | |
152b6a62 | 2900 | if (efx_nic_is_dual_func(efx)) { |
8ceee660 BH |
2901 | struct pci_dev *dev = pci_dev_get(efx->pci_dev); |
2902 | ||
2903 | while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID, | |
2904 | dev))) { | |
2905 | if (dev->bus == efx->pci_dev->bus && | |
2906 | dev->devfn == efx->pci_dev->devfn + 1) { | |
2907 | nic_data->pci_dev2 = dev; | |
2908 | break; | |
2909 | } | |
2910 | } | |
2911 | if (!nic_data->pci_dev2) { | |
2912 | EFX_ERR(efx, "failed to find secondary function\n"); | |
2913 | rc = -ENODEV; | |
2914 | goto fail2; | |
2915 | } | |
2916 | } | |
2917 | ||
2918 | /* Now we can reset the NIC */ | |
2919 | rc = falcon_reset_hw(efx, RESET_TYPE_ALL); | |
2920 | if (rc) { | |
2921 | EFX_ERR(efx, "failed to reset NIC\n"); | |
2922 | goto fail3; | |
2923 | } | |
2924 | ||
2925 | /* Allocate memory for INT_KER */ | |
152b6a62 | 2926 | rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); |
8ceee660 BH |
2927 | if (rc) |
2928 | goto fail4; | |
2929 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
2930 | ||
9c8976a1 JSR |
2931 | EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n", |
2932 | (u64)efx->irq_status.dma_addr, | |
2933 | efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr)); | |
8ceee660 | 2934 | |
4a5b504d BH |
2935 | falcon_probe_spi_devices(efx); |
2936 | ||
8ceee660 BH |
2937 | /* Read in the non-volatile configuration */ |
2938 | rc = falcon_probe_nvconfig(efx); | |
2939 | if (rc) | |
2940 | goto fail5; | |
2941 | ||
37b5a603 | 2942 | /* Initialise I2C adapter */ |
e775fb93 BH |
2943 | board = falcon_board(efx); |
2944 | board->i2c_adap.owner = THIS_MODULE; | |
2945 | board->i2c_data = falcon_i2c_bit_operations; | |
2946 | board->i2c_data.data = efx; | |
2947 | board->i2c_adap.algo_data = &board->i2c_data; | |
2948 | board->i2c_adap.dev.parent = &efx->pci_dev->dev; | |
2949 | strlcpy(board->i2c_adap.name, "SFC4000 GPIO", | |
2950 | sizeof(board->i2c_adap.name)); | |
2951 | rc = i2c_bit_add_bus(&board->i2c_adap); | |
37b5a603 BH |
2952 | if (rc) |
2953 | goto fail5; | |
2954 | ||
44838a44 | 2955 | rc = falcon_board(efx)->type->init(efx); |
278c0621 BH |
2956 | if (rc) { |
2957 | EFX_ERR(efx, "failed to initialise board\n"); | |
2958 | goto fail6; | |
2959 | } | |
2960 | ||
55edc6e6 BH |
2961 | nic_data->stats_disable_count = 1; |
2962 | setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func, | |
2963 | (unsigned long)efx); | |
2964 | ||
8ceee660 BH |
2965 | return 0; |
2966 | ||
278c0621 | 2967 | fail6: |
e775fb93 BH |
2968 | BUG_ON(i2c_del_adapter(&board->i2c_adap)); |
2969 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); | |
8ceee660 | 2970 | fail5: |
4a5b504d | 2971 | falcon_remove_spi_devices(efx); |
152b6a62 | 2972 | efx_nic_free_buffer(efx, &efx->irq_status); |
8ceee660 | 2973 | fail4: |
8ceee660 BH |
2974 | fail3: |
2975 | if (nic_data->pci_dev2) { | |
2976 | pci_dev_put(nic_data->pci_dev2); | |
2977 | nic_data->pci_dev2 = NULL; | |
2978 | } | |
2979 | fail2: | |
8ceee660 BH |
2980 | fail1: |
2981 | kfree(efx->nic_data); | |
2982 | return rc; | |
2983 | } | |
2984 | ||
56241ceb BH |
2985 | static void falcon_init_rx_cfg(struct efx_nic *efx) |
2986 | { | |
2987 | /* Prior to Siena the RX DMA engine will split each frame at | |
2988 | * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to | |
2989 | * be so large that that never happens. */ | |
2990 | const unsigned huge_buf_size = (3 * 4096) >> 5; | |
2991 | /* RX control FIFO thresholds (32 entries) */ | |
2992 | const unsigned ctrl_xon_thr = 20; | |
2993 | const unsigned ctrl_xoff_thr = 25; | |
2994 | /* RX data FIFO thresholds (256-byte units; size varies) */ | |
152b6a62 BH |
2995 | int data_xon_thr = efx_nic_rx_xon_thresh >> 8; |
2996 | int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8; | |
56241ceb BH |
2997 | efx_oword_t reg; |
2998 | ||
12d00cad | 2999 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
daeda630 | 3000 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { |
625b4514 BH |
3001 | /* Data FIFO size is 5.5K */ |
3002 | if (data_xon_thr < 0) | |
3003 | data_xon_thr = 512 >> 8; | |
3004 | if (data_xoff_thr < 0) | |
3005 | data_xoff_thr = 2048 >> 8; | |
3e6c4538 BH |
3006 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); |
3007 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, | |
3008 | huge_buf_size); | |
3009 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr); | |
3010 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr); | |
3011 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); | |
3012 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
56241ceb | 3013 | } else { |
625b4514 BH |
3014 | /* Data FIFO size is 80K; register fields moved */ |
3015 | if (data_xon_thr < 0) | |
3016 | data_xon_thr = 27648 >> 8; /* ~3*max MTU */ | |
3017 | if (data_xoff_thr < 0) | |
3018 | data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */ | |
3e6c4538 BH |
3019 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); |
3020 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, | |
3021 | huge_buf_size); | |
3022 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr); | |
3023 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr); | |
3024 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); | |
3025 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
3026 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); | |
56241ceb | 3027 | } |
4b0d29dc BH |
3028 | /* Always enable XOFF signal from RX FIFO. We enable |
3029 | * or disable transmission of pause frames at the MAC. */ | |
3030 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); | |
12d00cad | 3031 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
56241ceb BH |
3032 | } |
3033 | ||
152b6a62 | 3034 | void efx_nic_init_common(struct efx_nic *efx) |
8ceee660 | 3035 | { |
8ceee660 | 3036 | efx_oword_t temp; |
8ceee660 BH |
3037 | |
3038 | /* Set positions of descriptor caches in SRAM. */ | |
0228f5cd BH |
3039 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, |
3040 | efx->type->tx_dc_base / 8); | |
12d00cad | 3041 | efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG); |
0228f5cd BH |
3042 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, |
3043 | efx->type->rx_dc_base / 8); | |
12d00cad | 3044 | efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG); |
8ceee660 BH |
3045 | |
3046 | /* Set TX descriptor cache size. */ | |
46e1ac0f | 3047 | BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER)); |
3e6c4538 | 3048 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER); |
12d00cad | 3049 | efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG); |
8ceee660 BH |
3050 | |
3051 | /* Set RX descriptor cache size. Set low watermark to size-8, as | |
3052 | * this allows most efficient prefetching. | |
3053 | */ | |
46e1ac0f | 3054 | BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER)); |
3e6c4538 | 3055 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER); |
12d00cad | 3056 | efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG); |
3e6c4538 | 3057 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8); |
12d00cad | 3058 | efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM); |
8ceee660 | 3059 | |
39e60212 BH |
3060 | /* Program INT_KER address */ |
3061 | EFX_POPULATE_OWORD_2(temp, | |
3062 | FRF_AZ_NORM_INT_VEC_DIS_KER, | |
3063 | EFX_INT_MODE_USE_MSI(efx), | |
3064 | FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr); | |
3065 | efx_writeo(efx, &temp, FR_AZ_INT_ADR_KER); | |
3066 | ||
8ceee660 BH |
3067 | /* Enable all the genuinely fatal interrupts. (They are still |
3068 | * masked by the overall interrupt mask, controlled by | |
3069 | * falcon_interrupts()). | |
3070 | * | |
3071 | * Note: All other fatal interrupts are enabled | |
3072 | */ | |
3073 | EFX_POPULATE_OWORD_3(temp, | |
3e6c4538 BH |
3074 | FRF_AZ_ILL_ADR_INT_KER_EN, 1, |
3075 | FRF_AZ_RBUF_OWN_INT_KER_EN, 1, | |
3076 | FRF_AZ_TBUF_OWN_INT_KER_EN, 1); | |
8ceee660 | 3077 | EFX_INVERT_OWORD(temp); |
12d00cad | 3078 | efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER); |
8ceee660 | 3079 | |
152b6a62 BH |
3080 | efx_setup_rss_indir_table(efx); |
3081 | ||
3082 | /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be | |
3083 | * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q. | |
3084 | */ | |
3085 | efx_reado(efx, &temp, FR_AZ_TX_RESERVED); | |
3086 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe); | |
3087 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1); | |
3088 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1); | |
3089 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0); | |
3090 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1); | |
3091 | /* Enable SW_EV to inherit in char driver - assume harmless here */ | |
3092 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1); | |
3093 | /* Prefetch threshold 2 => fetch when descriptor cache half empty */ | |
3094 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2); | |
3095 | /* Squash TX of packets of 16 bytes or less */ | |
3096 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) | |
3097 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); | |
3098 | efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); | |
3099 | } | |
3100 | ||
3101 | /* This call performs hardware-specific global initialisation, such as | |
3102 | * defining the descriptor cache sizes and number of RSS channels. | |
3103 | * It does not set up any buffers, descriptor rings or event queues. | |
3104 | */ | |
3105 | static int falcon_init_nic(struct efx_nic *efx) | |
3106 | { | |
3107 | efx_oword_t temp; | |
3108 | int rc; | |
3109 | ||
3110 | /* Use on-chip SRAM */ | |
3111 | efx_reado(efx, &temp, FR_AB_NIC_STAT); | |
3112 | EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); | |
3113 | efx_writeo(efx, &temp, FR_AB_NIC_STAT); | |
3114 | ||
3115 | /* Set the source of the GMAC clock */ | |
3116 | if (efx_nic_rev(efx) == EFX_REV_FALCON_B0) { | |
3117 | efx_reado(efx, &temp, FR_AB_GPIO_CTL); | |
3118 | EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true); | |
3119 | efx_writeo(efx, &temp, FR_AB_GPIO_CTL); | |
3120 | } | |
3121 | ||
3122 | /* Select the correct MAC */ | |
3123 | falcon_clock_mac(efx); | |
3124 | ||
3125 | rc = falcon_reset_sram(efx); | |
3126 | if (rc) | |
3127 | return rc; | |
3128 | ||
3129 | /* Clear the parity enables on the TX data fifos as | |
3130 | * they produce false parity errors because of timing issues | |
3131 | */ | |
3132 | if (EFX_WORKAROUND_5129(efx)) { | |
3133 | efx_reado(efx, &temp, FR_AZ_CSR_SPARE); | |
3134 | EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); | |
3135 | efx_writeo(efx, &temp, FR_AZ_CSR_SPARE); | |
3136 | } | |
3137 | ||
8ceee660 | 3138 | if (EFX_WORKAROUND_7244(efx)) { |
12d00cad | 3139 | efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL); |
3e6c4538 BH |
3140 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); |
3141 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); | |
3142 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); | |
3143 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); | |
12d00cad | 3144 | efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL); |
8ceee660 | 3145 | } |
8ceee660 | 3146 | |
3e6c4538 | 3147 | /* XXX This is documented only for Falcon A0/A1 */ |
8ceee660 BH |
3148 | /* Setup RX. Wait for descriptor is broken and must |
3149 | * be disabled. RXDP recovery shouldn't be needed, but is. | |
3150 | */ | |
12d00cad | 3151 | efx_reado(efx, &temp, FR_AA_RX_SELF_RST); |
3e6c4538 BH |
3152 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); |
3153 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); | |
8ceee660 | 3154 | if (EFX_WORKAROUND_5583(efx)) |
3e6c4538 | 3155 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); |
12d00cad | 3156 | efx_writeo(efx, &temp, FR_AA_RX_SELF_RST); |
8ceee660 | 3157 | |
8ceee660 BH |
3158 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 |
3159 | * descriptors (which is bad). | |
3160 | */ | |
12d00cad | 3161 | efx_reado(efx, &temp, FR_AZ_TX_CFG); |
3e6c4538 | 3162 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); |
12d00cad | 3163 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); |
8ceee660 | 3164 | |
56241ceb | 3165 | falcon_init_rx_cfg(efx); |
8ceee660 BH |
3166 | |
3167 | /* Set destination of both TX and RX Flush events */ | |
daeda630 | 3168 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
3e6c4538 | 3169 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); |
12d00cad | 3170 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); |
8ceee660 BH |
3171 | } |
3172 | ||
152b6a62 BH |
3173 | efx_nic_init_common(efx); |
3174 | ||
8ceee660 BH |
3175 | return 0; |
3176 | } | |
3177 | ||
ef2b90ee | 3178 | static void falcon_remove_nic(struct efx_nic *efx) |
8ceee660 BH |
3179 | { |
3180 | struct falcon_nic_data *nic_data = efx->nic_data; | |
e775fb93 | 3181 | struct falcon_board *board = falcon_board(efx); |
37b5a603 BH |
3182 | int rc; |
3183 | ||
44838a44 | 3184 | board->type->fini(efx); |
278c0621 | 3185 | |
8c870379 | 3186 | /* Remove I2C adapter and clear it in preparation for a retry */ |
e775fb93 | 3187 | rc = i2c_del_adapter(&board->i2c_adap); |
37b5a603 | 3188 | BUG_ON(rc); |
e775fb93 | 3189 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); |
8ceee660 | 3190 | |
4a5b504d | 3191 | falcon_remove_spi_devices(efx); |
152b6a62 | 3192 | efx_nic_free_buffer(efx, &efx->irq_status); |
8ceee660 | 3193 | |
91ad757c | 3194 | falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 BH |
3195 | |
3196 | /* Release the second function after the reset */ | |
3197 | if (nic_data->pci_dev2) { | |
3198 | pci_dev_put(nic_data->pci_dev2); | |
3199 | nic_data->pci_dev2 = NULL; | |
3200 | } | |
3201 | ||
3202 | /* Tear down the private nic state */ | |
3203 | kfree(efx->nic_data); | |
3204 | efx->nic_data = NULL; | |
3205 | } | |
3206 | ||
ef2b90ee | 3207 | static void falcon_update_nic_stats(struct efx_nic *efx) |
8ceee660 | 3208 | { |
55edc6e6 | 3209 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 BH |
3210 | efx_oword_t cnt; |
3211 | ||
55edc6e6 BH |
3212 | if (nic_data->stats_disable_count) |
3213 | return; | |
3214 | ||
12d00cad | 3215 | efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP); |
3e6c4538 BH |
3216 | efx->n_rx_nodesc_drop_cnt += |
3217 | EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); | |
55edc6e6 BH |
3218 | |
3219 | if (nic_data->stats_pending && | |
3220 | *nic_data->stats_dma_done == FALCON_STATS_DONE) { | |
3221 | nic_data->stats_pending = false; | |
3222 | rmb(); /* read the done flag before the stats */ | |
3223 | efx->mac_op->update_stats(efx); | |
3224 | } | |
3225 | } | |
3226 | ||
3227 | void falcon_start_nic_stats(struct efx_nic *efx) | |
3228 | { | |
3229 | struct falcon_nic_data *nic_data = efx->nic_data; | |
3230 | ||
3231 | spin_lock_bh(&efx->stats_lock); | |
3232 | if (--nic_data->stats_disable_count == 0) | |
3233 | falcon_stats_request(efx); | |
3234 | spin_unlock_bh(&efx->stats_lock); | |
3235 | } | |
3236 | ||
3237 | void falcon_stop_nic_stats(struct efx_nic *efx) | |
3238 | { | |
3239 | struct falcon_nic_data *nic_data = efx->nic_data; | |
3240 | int i; | |
3241 | ||
3242 | might_sleep(); | |
3243 | ||
3244 | spin_lock_bh(&efx->stats_lock); | |
3245 | ++nic_data->stats_disable_count; | |
3246 | spin_unlock_bh(&efx->stats_lock); | |
3247 | ||
3248 | del_timer_sync(&nic_data->stats_timer); | |
3249 | ||
3250 | /* Wait enough time for the most recent transfer to | |
3251 | * complete. */ | |
3252 | for (i = 0; i < 4 && nic_data->stats_pending; i++) { | |
3253 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) | |
3254 | break; | |
3255 | msleep(1); | |
3256 | } | |
3257 | ||
3258 | spin_lock_bh(&efx->stats_lock); | |
3259 | falcon_stats_complete(efx); | |
3260 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
3261 | } |
3262 | ||
06629f07 BH |
3263 | static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
3264 | { | |
3265 | falcon_board(efx)->type->set_id_led(efx, mode); | |
3266 | } | |
3267 | ||
89c758fa BH |
3268 | /************************************************************************** |
3269 | * | |
3270 | * Wake on LAN | |
3271 | * | |
3272 | ************************************************************************** | |
3273 | */ | |
3274 | ||
3275 | static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) | |
3276 | { | |
3277 | wol->supported = 0; | |
3278 | wol->wolopts = 0; | |
3279 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
3280 | } | |
3281 | ||
3282 | static int falcon_set_wol(struct efx_nic *efx, u32 type) | |
3283 | { | |
3284 | if (type != 0) | |
3285 | return -EINVAL; | |
3286 | return 0; | |
3287 | } | |
3288 | ||
8ceee660 BH |
3289 | /************************************************************************** |
3290 | * | |
3291 | * Revision-dependent attributes used by efx.c | |
3292 | * | |
3293 | ************************************************************************** | |
3294 | */ | |
3295 | ||
daeda630 | 3296 | struct efx_nic_type falcon_a1_nic_type = { |
ef2b90ee BH |
3297 | .probe = falcon_probe_nic, |
3298 | .remove = falcon_remove_nic, | |
3299 | .init = falcon_init_nic, | |
3300 | .fini = efx_port_dummy_op_void, | |
3301 | .monitor = falcon_monitor, | |
3302 | .reset = falcon_reset_hw, | |
3303 | .probe_port = falcon_probe_port, | |
3304 | .remove_port = falcon_remove_port, | |
3305 | .prepare_flush = falcon_prepare_flush, | |
3306 | .update_stats = falcon_update_nic_stats, | |
3307 | .start_stats = falcon_start_nic_stats, | |
3308 | .stop_stats = falcon_stop_nic_stats, | |
06629f07 | 3309 | .set_id_led = falcon_set_id_led, |
ef2b90ee BH |
3310 | .push_irq_moderation = falcon_push_irq_moderation, |
3311 | .push_multicast_hash = falcon_push_multicast_hash, | |
d3245b28 | 3312 | .reconfigure_port = falcon_reconfigure_port, |
89c758fa BH |
3313 | .get_wol = falcon_get_wol, |
3314 | .set_wol = falcon_set_wol, | |
3315 | .resume_wol = efx_port_dummy_op_void, | |
0aa3fbaa | 3316 | .test_nvram = falcon_test_nvram, |
b895d73e SH |
3317 | .default_mac_ops = &falcon_xmac_operations, |
3318 | ||
daeda630 | 3319 | .revision = EFX_REV_FALCON_A1, |
8ceee660 | 3320 | .mem_map_size = 0x20000, |
3e6c4538 BH |
3321 | .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER, |
3322 | .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER, | |
3323 | .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER, | |
3324 | .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER, | |
3325 | .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER, | |
6d51d307 | 3326 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
8ceee660 BH |
3327 | .rx_buffer_padding = 0x24, |
3328 | .max_interrupt_mode = EFX_INT_MODE_MSI, | |
3329 | .phys_addr_channels = 4, | |
0228f5cd BH |
3330 | .tx_dc_base = 0x130000, |
3331 | .rx_dc_base = 0x100000, | |
eb9f6744 | 3332 | .reset_world_flags = ETH_RESET_IRQ, |
8ceee660 BH |
3333 | }; |
3334 | ||
daeda630 | 3335 | struct efx_nic_type falcon_b0_nic_type = { |
ef2b90ee BH |
3336 | .probe = falcon_probe_nic, |
3337 | .remove = falcon_remove_nic, | |
3338 | .init = falcon_init_nic, | |
3339 | .fini = efx_port_dummy_op_void, | |
3340 | .monitor = falcon_monitor, | |
3341 | .reset = falcon_reset_hw, | |
3342 | .probe_port = falcon_probe_port, | |
3343 | .remove_port = falcon_remove_port, | |
3344 | .prepare_flush = falcon_prepare_flush, | |
3345 | .update_stats = falcon_update_nic_stats, | |
3346 | .start_stats = falcon_start_nic_stats, | |
3347 | .stop_stats = falcon_stop_nic_stats, | |
06629f07 | 3348 | .set_id_led = falcon_set_id_led, |
ef2b90ee BH |
3349 | .push_irq_moderation = falcon_push_irq_moderation, |
3350 | .push_multicast_hash = falcon_push_multicast_hash, | |
d3245b28 | 3351 | .reconfigure_port = falcon_reconfigure_port, |
89c758fa BH |
3352 | .get_wol = falcon_get_wol, |
3353 | .set_wol = falcon_set_wol, | |
3354 | .resume_wol = efx_port_dummy_op_void, | |
9bfc4bb1 | 3355 | .test_registers = falcon_b0_test_registers, |
0aa3fbaa | 3356 | .test_nvram = falcon_test_nvram, |
b895d73e SH |
3357 | .default_mac_ops = &falcon_xmac_operations, |
3358 | ||
daeda630 | 3359 | .revision = EFX_REV_FALCON_B0, |
8ceee660 BH |
3360 | /* Map everything up to and including the RSS indirection |
3361 | * table. Don't map MSI-X table, MSI-X PBA since Linux | |
3362 | * requires that they not be mapped. */ | |
3e6c4538 BH |
3363 | .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL + |
3364 | FR_BZ_RX_INDIRECTION_TBL_STEP * | |
3365 | FR_BZ_RX_INDIRECTION_TBL_ROWS), | |
3366 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, | |
3367 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | |
3368 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | |
3369 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | |
3370 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | |
6d51d307 | 3371 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
8ceee660 BH |
3372 | .rx_buffer_padding = 0, |
3373 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
3374 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | |
3375 | * interrupt handler only supports 32 | |
3376 | * channels */ | |
0228f5cd BH |
3377 | .tx_dc_base = 0x130000, |
3378 | .rx_dc_base = 0x100000, | |
eb9f6744 | 3379 | .reset_world_flags = ETH_RESET_IRQ, |
8ceee660 BH |
3380 | }; |
3381 |