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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
906bb26c | 4 | * Copyright 2006-2009 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/seq_file.h> | |
37b5a603 | 16 | #include <linux/i2c.h> |
f31a45d2 | 17 | #include <linux/mii.h> |
5a0e3ad6 | 18 | #include <linux/slab.h> |
8ceee660 BH |
19 | #include "net_driver.h" |
20 | #include "bitfield.h" | |
21 | #include "efx.h" | |
22 | #include "mac.h" | |
8ceee660 | 23 | #include "spi.h" |
744093c9 | 24 | #include "nic.h" |
3e6c4538 | 25 | #include "regs.h" |
12d00cad | 26 | #include "io.h" |
8ceee660 | 27 | #include "phy.h" |
8ceee660 BH |
28 | #include "workarounds.h" |
29 | ||
8986352a | 30 | /* Hardware control for SFC4000 (aka Falcon). */ |
8ceee660 | 31 | |
2f7f5730 BH |
32 | static const unsigned int |
33 | /* "Large" EEPROM device: Atmel AT25640 or similar | |
34 | * 8 KB, 16-bit address, 32 B write block */ | |
35 | large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN) | |
36 | | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
37 | | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)), | |
38 | /* Default flash device: Atmel AT25F1024 | |
39 | * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */ | |
40 | default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN) | |
41 | | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
42 | | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN) | |
43 | | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) | |
44 | | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); | |
45 | ||
8ceee660 BH |
46 | /************************************************************************** |
47 | * | |
48 | * I2C bus - this is a bit-bashing interface using GPIO pins | |
49 | * Note that it uses the output enables to tristate the outputs | |
50 | * SDA is the data pin and SCL is the clock | |
51 | * | |
52 | ************************************************************************** | |
53 | */ | |
37b5a603 | 54 | static void falcon_setsda(void *data, int state) |
8ceee660 | 55 | { |
37b5a603 | 56 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
57 | efx_oword_t reg; |
58 | ||
12d00cad | 59 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 60 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); |
12d00cad | 61 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
8ceee660 BH |
62 | } |
63 | ||
37b5a603 | 64 | static void falcon_setscl(void *data, int state) |
8ceee660 | 65 | { |
37b5a603 | 66 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
67 | efx_oword_t reg; |
68 | ||
12d00cad | 69 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 70 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); |
12d00cad | 71 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
37b5a603 BH |
72 | } |
73 | ||
8e730c15 BH |
74 | static int falcon_getsda(void *data) |
75 | { | |
76 | struct efx_nic *efx = (struct efx_nic *)data; | |
77 | efx_oword_t reg; | |
8ceee660 | 78 | |
8e730c15 BH |
79 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
80 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); | |
81 | } | |
8ceee660 | 82 | |
8e730c15 BH |
83 | static int falcon_getscl(void *data) |
84 | { | |
85 | struct efx_nic *efx = (struct efx_nic *)data; | |
86 | efx_oword_t reg; | |
8ceee660 | 87 | |
8e730c15 BH |
88 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
89 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); | |
8ceee660 BH |
90 | } |
91 | ||
8e730c15 BH |
92 | static struct i2c_algo_bit_data falcon_i2c_bit_operations = { |
93 | .setsda = falcon_setsda, | |
94 | .setscl = falcon_setscl, | |
95 | .getsda = falcon_getsda, | |
96 | .getscl = falcon_getscl, | |
97 | .udelay = 5, | |
98 | /* Wait up to 50 ms for slave to let us pull SCL high */ | |
99 | .timeout = DIV_ROUND_UP(HZ, 20), | |
100 | }; | |
101 | ||
ef2b90ee | 102 | static void falcon_push_irq_moderation(struct efx_channel *channel) |
8ceee660 BH |
103 | { |
104 | efx_dword_t timer_cmd; | |
105 | struct efx_nic *efx = channel->efx; | |
106 | ||
107 | /* Set timer register */ | |
108 | if (channel->irq_moderation) { | |
8ceee660 | 109 | EFX_POPULATE_DWORD_2(timer_cmd, |
3e6c4538 BH |
110 | FRF_AB_TC_TIMER_MODE, |
111 | FFE_BB_TIMER_MODE_INT_HLDOFF, | |
112 | FRF_AB_TC_TIMER_VAL, | |
0d86ebd8 | 113 | channel->irq_moderation - 1); |
8ceee660 BH |
114 | } else { |
115 | EFX_POPULATE_DWORD_2(timer_cmd, | |
3e6c4538 BH |
116 | FRF_AB_TC_TIMER_MODE, |
117 | FFE_BB_TIMER_MODE_DIS, | |
118 | FRF_AB_TC_TIMER_VAL, 0); | |
8ceee660 | 119 | } |
3e6c4538 | 120 | BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); |
12d00cad BH |
121 | efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, |
122 | channel->channel); | |
127e6e10 BH |
123 | } |
124 | ||
d3245b28 BH |
125 | static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx); |
126 | ||
127e6e10 BH |
127 | static void falcon_prepare_flush(struct efx_nic *efx) |
128 | { | |
129 | falcon_deconfigure_mac_wrapper(efx); | |
130 | ||
131 | /* Wait for the tx and rx fifo's to get to the next packet boundary | |
132 | * (~1ms without back-pressure), then to drain the remainder of the | |
133 | * fifo's at data path speeds (negligible), with a healthy margin. */ | |
134 | msleep(10); | |
6bc5d3a9 BH |
135 | } |
136 | ||
8ceee660 BH |
137 | /* Acknowledge a legacy interrupt from Falcon |
138 | * | |
139 | * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. | |
140 | * | |
141 | * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the | |
142 | * BIU. Interrupt acknowledge is read sensitive so must write instead | |
143 | * (then read to ensure the BIU collector is flushed) | |
144 | * | |
145 | * NB most hardware supports MSI interrupts | |
146 | */ | |
152b6a62 | 147 | inline void falcon_irq_ack_a1(struct efx_nic *efx) |
8ceee660 BH |
148 | { |
149 | efx_dword_t reg; | |
150 | ||
3e6c4538 | 151 | EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); |
12d00cad BH |
152 | efx_writed(efx, ®, FR_AA_INT_ACK_KER); |
153 | efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); | |
8ceee660 BH |
154 | } |
155 | ||
8ceee660 | 156 | |
152b6a62 | 157 | irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) |
8ceee660 | 158 | { |
d3208b5e BH |
159 | struct efx_nic *efx = dev_id; |
160 | efx_oword_t *int_ker = efx->irq_status.addr; | |
8ceee660 BH |
161 | int syserr; |
162 | int queues; | |
163 | ||
164 | /* Check to see if this is our interrupt. If it isn't, we | |
165 | * exit without having touched the hardware. | |
166 | */ | |
167 | if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) { | |
62776d03 BH |
168 | netif_vdbg(efx, intr, efx->net_dev, |
169 | "IRQ %d on CPU %d not for me\n", irq, | |
170 | raw_smp_processor_id()); | |
8ceee660 BH |
171 | return IRQ_NONE; |
172 | } | |
173 | efx->last_irq_cpu = raw_smp_processor_id(); | |
62776d03 BH |
174 | netif_vdbg(efx, intr, efx->net_dev, |
175 | "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
176 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
8ceee660 | 177 | |
8ceee660 BH |
178 | /* Determine interrupting queues, clear interrupt status |
179 | * register and acknowledge the device interrupt. | |
180 | */ | |
674979d3 BH |
181 | BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS); |
182 | queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q); | |
63695459 SH |
183 | |
184 | /* Check to see if we have a serious error condition */ | |
185 | if (queues & (1U << efx->fatal_irq_level)) { | |
186 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); | |
187 | if (unlikely(syserr)) | |
188 | return efx_nic_fatal_interrupt(efx); | |
189 | } | |
190 | ||
8ceee660 BH |
191 | EFX_ZERO_OWORD(*int_ker); |
192 | wmb(); /* Ensure the vector is cleared before interrupt ack */ | |
193 | falcon_irq_ack_a1(efx); | |
194 | ||
8313aca3 BH |
195 | if (queues & 1) |
196 | efx_schedule_channel(efx_get_channel(efx, 0)); | |
197 | if (queues & 2) | |
198 | efx_schedule_channel(efx_get_channel(efx, 1)); | |
8ceee660 BH |
199 | return IRQ_HANDLED; |
200 | } | |
8ceee660 BH |
201 | /************************************************************************** |
202 | * | |
203 | * EEPROM/flash | |
204 | * | |
205 | ************************************************************************** | |
206 | */ | |
207 | ||
23d30f02 | 208 | #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t) |
8ceee660 | 209 | |
be4ea89c BH |
210 | static int falcon_spi_poll(struct efx_nic *efx) |
211 | { | |
212 | efx_oword_t reg; | |
12d00cad | 213 | efx_reado(efx, ®, FR_AB_EE_SPI_HCMD); |
3e6c4538 | 214 | return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; |
be4ea89c BH |
215 | } |
216 | ||
8ceee660 BH |
217 | /* Wait for SPI command completion */ |
218 | static int falcon_spi_wait(struct efx_nic *efx) | |
219 | { | |
be4ea89c BH |
220 | /* Most commands will finish quickly, so we start polling at |
221 | * very short intervals. Sometimes the command may have to | |
222 | * wait for VPD or expansion ROM access outside of our | |
223 | * control, so we allow up to 100 ms. */ | |
224 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10); | |
225 | int i; | |
226 | ||
227 | for (i = 0; i < 10; i++) { | |
228 | if (!falcon_spi_poll(efx)) | |
229 | return 0; | |
230 | udelay(10); | |
231 | } | |
8ceee660 | 232 | |
4a5b504d | 233 | for (;;) { |
be4ea89c | 234 | if (!falcon_spi_poll(efx)) |
8ceee660 | 235 | return 0; |
4a5b504d | 236 | if (time_after_eq(jiffies, timeout)) { |
62776d03 BH |
237 | netif_err(efx, hw, efx->net_dev, |
238 | "timed out waiting for SPI\n"); | |
4a5b504d BH |
239 | return -ETIMEDOUT; |
240 | } | |
be4ea89c | 241 | schedule_timeout_uninterruptible(1); |
4a5b504d | 242 | } |
8ceee660 BH |
243 | } |
244 | ||
76884835 | 245 | int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi, |
f4150724 | 246 | unsigned int command, int address, |
23d30f02 | 247 | const void *in, void *out, size_t len) |
8ceee660 | 248 | { |
4a5b504d BH |
249 | bool addressed = (address >= 0); |
250 | bool reading = (out != NULL); | |
8ceee660 BH |
251 | efx_oword_t reg; |
252 | int rc; | |
253 | ||
4a5b504d BH |
254 | /* Input validation */ |
255 | if (len > FALCON_SPI_MAX_LEN) | |
256 | return -EINVAL; | |
8ceee660 | 257 | |
be4ea89c BH |
258 | /* Check that previous command is not still running */ |
259 | rc = falcon_spi_poll(efx); | |
8ceee660 BH |
260 | if (rc) |
261 | return rc; | |
262 | ||
4a5b504d BH |
263 | /* Program address register, if we have an address */ |
264 | if (addressed) { | |
3e6c4538 | 265 | EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); |
12d00cad | 266 | efx_writeo(efx, ®, FR_AB_EE_SPI_HADR); |
4a5b504d BH |
267 | } |
268 | ||
269 | /* Program data register, if we have data */ | |
270 | if (in != NULL) { | |
271 | memcpy(®, in, len); | |
12d00cad | 272 | efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d | 273 | } |
8ceee660 | 274 | |
4a5b504d | 275 | /* Issue read/write command */ |
8ceee660 | 276 | EFX_POPULATE_OWORD_7(reg, |
3e6c4538 BH |
277 | FRF_AB_EE_SPI_HCMD_CMD_EN, 1, |
278 | FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id, | |
279 | FRF_AB_EE_SPI_HCMD_DABCNT, len, | |
280 | FRF_AB_EE_SPI_HCMD_READ, reading, | |
281 | FRF_AB_EE_SPI_HCMD_DUBCNT, 0, | |
282 | FRF_AB_EE_SPI_HCMD_ADBCNT, | |
4a5b504d | 283 | (addressed ? spi->addr_len : 0), |
3e6c4538 | 284 | FRF_AB_EE_SPI_HCMD_ENC, command); |
12d00cad | 285 | efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD); |
8ceee660 | 286 | |
4a5b504d | 287 | /* Wait for read/write to complete */ |
8ceee660 BH |
288 | rc = falcon_spi_wait(efx); |
289 | if (rc) | |
290 | return rc; | |
291 | ||
292 | /* Read data */ | |
4a5b504d | 293 | if (out != NULL) { |
12d00cad | 294 | efx_reado(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d BH |
295 | memcpy(out, ®, len); |
296 | } | |
297 | ||
8ceee660 BH |
298 | return 0; |
299 | } | |
300 | ||
23d30f02 BH |
301 | static size_t |
302 | falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start) | |
4a5b504d BH |
303 | { |
304 | return min(FALCON_SPI_MAX_LEN, | |
305 | (spi->block_size - (start & (spi->block_size - 1)))); | |
306 | } | |
307 | ||
308 | static inline u8 | |
309 | efx_spi_munge_command(const struct efx_spi_device *spi, | |
310 | const u8 command, const unsigned int address) | |
311 | { | |
312 | return command | (((address >> 8) & spi->munge_address) << 3); | |
313 | } | |
314 | ||
be4ea89c | 315 | /* Wait up to 10 ms for buffered write completion */ |
76884835 BH |
316 | int |
317 | falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi) | |
4a5b504d | 318 | { |
be4ea89c | 319 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); |
4a5b504d | 320 | u8 status; |
be4ea89c | 321 | int rc; |
4a5b504d | 322 | |
be4ea89c | 323 | for (;;) { |
76884835 | 324 | rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL, |
4a5b504d BH |
325 | &status, sizeof(status)); |
326 | if (rc) | |
327 | return rc; | |
328 | if (!(status & SPI_STATUS_NRDY)) | |
329 | return 0; | |
be4ea89c | 330 | if (time_after_eq(jiffies, timeout)) { |
62776d03 BH |
331 | netif_err(efx, hw, efx->net_dev, |
332 | "SPI write timeout on device %d" | |
333 | " last status=0x%02x\n", | |
334 | spi->device_id, status); | |
be4ea89c BH |
335 | return -ETIMEDOUT; |
336 | } | |
337 | schedule_timeout_uninterruptible(1); | |
4a5b504d | 338 | } |
4a5b504d BH |
339 | } |
340 | ||
76884835 BH |
341 | int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi, |
342 | loff_t start, size_t len, size_t *retlen, u8 *buffer) | |
4a5b504d | 343 | { |
23d30f02 BH |
344 | size_t block_len, pos = 0; |
345 | unsigned int command; | |
4a5b504d BH |
346 | int rc = 0; |
347 | ||
348 | while (pos < len) { | |
23d30f02 | 349 | block_len = min(len - pos, FALCON_SPI_MAX_LEN); |
4a5b504d BH |
350 | |
351 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
76884835 | 352 | rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL, |
4a5b504d BH |
353 | buffer + pos, block_len); |
354 | if (rc) | |
355 | break; | |
356 | pos += block_len; | |
357 | ||
358 | /* Avoid locking up the system */ | |
359 | cond_resched(); | |
360 | if (signal_pending(current)) { | |
361 | rc = -EINTR; | |
362 | break; | |
363 | } | |
364 | } | |
365 | ||
366 | if (retlen) | |
367 | *retlen = pos; | |
368 | return rc; | |
369 | } | |
370 | ||
76884835 BH |
371 | int |
372 | falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi, | |
373 | loff_t start, size_t len, size_t *retlen, const u8 *buffer) | |
4a5b504d BH |
374 | { |
375 | u8 verify_buffer[FALCON_SPI_MAX_LEN]; | |
23d30f02 BH |
376 | size_t block_len, pos = 0; |
377 | unsigned int command; | |
4a5b504d BH |
378 | int rc = 0; |
379 | ||
380 | while (pos < len) { | |
76884835 | 381 | rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0); |
4a5b504d BH |
382 | if (rc) |
383 | break; | |
384 | ||
23d30f02 | 385 | block_len = min(len - pos, |
4a5b504d BH |
386 | falcon_spi_write_limit(spi, start + pos)); |
387 | command = efx_spi_munge_command(spi, SPI_WRITE, start + pos); | |
76884835 | 388 | rc = falcon_spi_cmd(efx, spi, command, start + pos, |
4a5b504d BH |
389 | buffer + pos, NULL, block_len); |
390 | if (rc) | |
391 | break; | |
392 | ||
76884835 | 393 | rc = falcon_spi_wait_write(efx, spi); |
4a5b504d BH |
394 | if (rc) |
395 | break; | |
396 | ||
397 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
76884835 | 398 | rc = falcon_spi_cmd(efx, spi, command, start + pos, |
4a5b504d BH |
399 | NULL, verify_buffer, block_len); |
400 | if (memcmp(verify_buffer, buffer + pos, block_len)) { | |
401 | rc = -EIO; | |
402 | break; | |
403 | } | |
404 | ||
405 | pos += block_len; | |
406 | ||
407 | /* Avoid locking up the system */ | |
408 | cond_resched(); | |
409 | if (signal_pending(current)) { | |
410 | rc = -EINTR; | |
411 | break; | |
412 | } | |
413 | } | |
414 | ||
415 | if (retlen) | |
416 | *retlen = pos; | |
417 | return rc; | |
418 | } | |
419 | ||
8ceee660 BH |
420 | /************************************************************************** |
421 | * | |
422 | * MAC wrapper | |
423 | * | |
424 | ************************************************************************** | |
425 | */ | |
177dfcd8 | 426 | |
ef2b90ee BH |
427 | static void falcon_push_multicast_hash(struct efx_nic *efx) |
428 | { | |
429 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
430 | ||
431 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
432 | ||
433 | efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); | |
434 | efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); | |
435 | } | |
436 | ||
d3245b28 | 437 | static void falcon_reset_macs(struct efx_nic *efx) |
8ceee660 | 438 | { |
d3245b28 BH |
439 | struct falcon_nic_data *nic_data = efx->nic_data; |
440 | efx_oword_t reg, mac_ctrl; | |
8ceee660 BH |
441 | int count; |
442 | ||
daeda630 | 443 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) { |
177dfcd8 BH |
444 | /* It's not safe to use GLB_CTL_REG to reset the |
445 | * macs, so instead use the internal MAC resets | |
446 | */ | |
8fbca791 BH |
447 | EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); |
448 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); | |
449 | ||
450 | for (count = 0; count < 10000; count++) { | |
451 | efx_reado(efx, ®, FR_AB_XM_GLB_CFG); | |
452 | if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == | |
453 | 0) | |
454 | return; | |
455 | udelay(10); | |
177dfcd8 | 456 | } |
8fbca791 BH |
457 | |
458 | netif_err(efx, hw, efx->net_dev, | |
459 | "timed out waiting for XMAC core reset\n"); | |
177dfcd8 | 460 | } |
8ceee660 | 461 | |
d3245b28 BH |
462 | /* Mac stats will fail whist the TX fifo is draining */ |
463 | WARN_ON(nic_data->stats_disable_count == 0); | |
8ceee660 | 464 | |
d3245b28 BH |
465 | efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL); |
466 | EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1); | |
467 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); | |
8ceee660 | 468 | |
12d00cad | 469 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
470 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); |
471 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); | |
472 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); | |
12d00cad | 473 | efx_writeo(efx, ®, FR_AB_GLB_CTL); |
8ceee660 BH |
474 | |
475 | count = 0; | |
476 | while (1) { | |
12d00cad | 477 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
478 | if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && |
479 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && | |
480 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) { | |
62776d03 BH |
481 | netif_dbg(efx, hw, efx->net_dev, |
482 | "Completed MAC reset after %d loops\n", | |
483 | count); | |
8ceee660 BH |
484 | break; |
485 | } | |
486 | if (count > 20) { | |
62776d03 | 487 | netif_err(efx, hw, efx->net_dev, "MAC reset failed\n"); |
8ceee660 BH |
488 | break; |
489 | } | |
490 | count++; | |
491 | udelay(10); | |
492 | } | |
493 | ||
d3245b28 BH |
494 | /* Ensure the correct MAC is selected before statistics |
495 | * are re-enabled by the caller */ | |
496 | efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL); | |
b7b40eeb | 497 | |
b7b40eeb | 498 | falcon_setup_xaui(efx); |
177dfcd8 BH |
499 | } |
500 | ||
501 | void falcon_drain_tx_fifo(struct efx_nic *efx) | |
502 | { | |
503 | efx_oword_t reg; | |
504 | ||
daeda630 | 505 | if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) || |
177dfcd8 BH |
506 | (efx->loopback_mode != LOOPBACK_NONE)) |
507 | return; | |
508 | ||
12d00cad | 509 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
177dfcd8 | 510 | /* There is no point in draining more than once */ |
3e6c4538 | 511 | if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) |
177dfcd8 BH |
512 | return; |
513 | ||
514 | falcon_reset_macs(efx); | |
8ceee660 BH |
515 | } |
516 | ||
d3245b28 | 517 | static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) |
8ceee660 | 518 | { |
177dfcd8 | 519 | efx_oword_t reg; |
8ceee660 | 520 | |
daeda630 | 521 | if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) |
8ceee660 BH |
522 | return; |
523 | ||
524 | /* Isolate the MAC -> RX */ | |
12d00cad | 525 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
3e6c4538 | 526 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); |
12d00cad | 527 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 | 528 | |
d3245b28 BH |
529 | /* Isolate TX -> MAC */ |
530 | falcon_drain_tx_fifo(efx); | |
8ceee660 BH |
531 | } |
532 | ||
533 | void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) | |
534 | { | |
eb50c0d6 | 535 | struct efx_link_state *link_state = &efx->link_state; |
8ceee660 | 536 | efx_oword_t reg; |
fd371e32 SH |
537 | int link_speed, isolate; |
538 | ||
539 | isolate = (efx->reset_pending != RESET_TYPE_NONE); | |
8ceee660 | 540 | |
eb50c0d6 | 541 | switch (link_state->speed) { |
f31a45d2 BH |
542 | case 10000: link_speed = 3; break; |
543 | case 1000: link_speed = 2; break; | |
544 | case 100: link_speed = 1; break; | |
545 | default: link_speed = 0; break; | |
546 | } | |
8ceee660 BH |
547 | /* MAC_LINK_STATUS controls MAC backpressure but doesn't work |
548 | * as advertised. Disable to ensure packets are not | |
549 | * indefinitely held and TX queue can be flushed at any point | |
550 | * while the link is down. */ | |
551 | EFX_POPULATE_OWORD_5(reg, | |
3e6c4538 BH |
552 | FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */, |
553 | FRF_AB_MAC_BCAD_ACPT, 1, | |
554 | FRF_AB_MAC_UC_PROM, efx->promiscuous, | |
555 | FRF_AB_MAC_LINK_STATUS, 1, /* always set */ | |
556 | FRF_AB_MAC_SPEED, link_speed); | |
8ceee660 BH |
557 | /* On B0, MAC backpressure can be disabled and packets get |
558 | * discarded. */ | |
daeda630 | 559 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
3e6c4538 | 560 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, |
fd371e32 | 561 | !link_state->up || isolate); |
8ceee660 BH |
562 | } |
563 | ||
12d00cad | 564 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
8ceee660 BH |
565 | |
566 | /* Restore the multicast hash registers. */ | |
8be4f3e6 | 567 | falcon_push_multicast_hash(efx); |
8ceee660 | 568 | |
12d00cad | 569 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
4b0d29dc BH |
570 | /* Enable XOFF signal from RX FIFO (we enabled it during NIC |
571 | * initialisation but it may read back as 0) */ | |
572 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); | |
8ceee660 | 573 | /* Unisolate the MAC -> RX */ |
daeda630 | 574 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
fd371e32 | 575 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate); |
12d00cad | 576 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 BH |
577 | } |
578 | ||
55edc6e6 | 579 | static void falcon_stats_request(struct efx_nic *efx) |
8ceee660 | 580 | { |
55edc6e6 | 581 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 582 | efx_oword_t reg; |
8ceee660 | 583 | |
55edc6e6 BH |
584 | WARN_ON(nic_data->stats_pending); |
585 | WARN_ON(nic_data->stats_disable_count); | |
8ceee660 | 586 | |
55edc6e6 BH |
587 | if (nic_data->stats_dma_done == NULL) |
588 | return; /* no mac selected */ | |
8ceee660 | 589 | |
55edc6e6 BH |
590 | *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE; |
591 | nic_data->stats_pending = true; | |
8ceee660 BH |
592 | wmb(); /* ensure done flag is clear */ |
593 | ||
594 | /* Initiate DMA transfer of stats */ | |
595 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
596 | FRF_AB_MAC_STAT_DMA_CMD, 1, |
597 | FRF_AB_MAC_STAT_DMA_ADR, | |
8ceee660 | 598 | efx->stats_buffer.dma_addr); |
12d00cad | 599 | efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA); |
8ceee660 | 600 | |
55edc6e6 BH |
601 | mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2)); |
602 | } | |
603 | ||
604 | static void falcon_stats_complete(struct efx_nic *efx) | |
605 | { | |
606 | struct falcon_nic_data *nic_data = efx->nic_data; | |
607 | ||
608 | if (!nic_data->stats_pending) | |
609 | return; | |
610 | ||
611 | nic_data->stats_pending = 0; | |
612 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) { | |
613 | rmb(); /* read the done flag before the stats */ | |
614 | efx->mac_op->update_stats(efx); | |
615 | } else { | |
62776d03 BH |
616 | netif_err(efx, hw, efx->net_dev, |
617 | "timed out waiting for statistics\n"); | |
8ceee660 | 618 | } |
55edc6e6 | 619 | } |
8ceee660 | 620 | |
55edc6e6 BH |
621 | static void falcon_stats_timer_func(unsigned long context) |
622 | { | |
623 | struct efx_nic *efx = (struct efx_nic *)context; | |
624 | struct falcon_nic_data *nic_data = efx->nic_data; | |
625 | ||
626 | spin_lock(&efx->stats_lock); | |
627 | ||
628 | falcon_stats_complete(efx); | |
629 | if (nic_data->stats_disable_count == 0) | |
630 | falcon_stats_request(efx); | |
631 | ||
632 | spin_unlock(&efx->stats_lock); | |
8ceee660 BH |
633 | } |
634 | ||
fdaa9aed SH |
635 | static bool falcon_loopback_link_poll(struct efx_nic *efx) |
636 | { | |
637 | struct efx_link_state old_state = efx->link_state; | |
638 | ||
639 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); | |
640 | WARN_ON(!LOOPBACK_INTERNAL(efx)); | |
641 | ||
642 | efx->link_state.fd = true; | |
643 | efx->link_state.fc = efx->wanted_fc; | |
644 | efx->link_state.up = true; | |
8fbca791 | 645 | efx->link_state.speed = 10000; |
fdaa9aed SH |
646 | |
647 | return !efx_link_state_equal(&efx->link_state, &old_state); | |
648 | } | |
649 | ||
d3245b28 BH |
650 | static int falcon_reconfigure_port(struct efx_nic *efx) |
651 | { | |
652 | int rc; | |
653 | ||
654 | WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0); | |
655 | ||
656 | /* Poll the PHY link state *before* reconfiguring it. This means we | |
657 | * will pick up the correct speed (in loopback) to select the correct | |
658 | * MAC. | |
659 | */ | |
660 | if (LOOPBACK_INTERNAL(efx)) | |
661 | falcon_loopback_link_poll(efx); | |
662 | else | |
663 | efx->phy_op->poll(efx); | |
664 | ||
665 | falcon_stop_nic_stats(efx); | |
666 | falcon_deconfigure_mac_wrapper(efx); | |
667 | ||
8fbca791 | 668 | falcon_reset_macs(efx); |
d3245b28 BH |
669 | |
670 | efx->phy_op->reconfigure(efx); | |
671 | rc = efx->mac_op->reconfigure(efx); | |
672 | BUG_ON(rc); | |
673 | ||
674 | falcon_start_nic_stats(efx); | |
675 | ||
676 | /* Synchronise efx->link_state with the kernel */ | |
677 | efx_link_status_changed(efx); | |
678 | ||
679 | return 0; | |
680 | } | |
681 | ||
8ceee660 BH |
682 | /************************************************************************** |
683 | * | |
684 | * PHY access via GMII | |
685 | * | |
686 | ************************************************************************** | |
687 | */ | |
688 | ||
8ceee660 BH |
689 | /* Wait for GMII access to complete */ |
690 | static int falcon_gmii_wait(struct efx_nic *efx) | |
691 | { | |
80cb9a0f | 692 | efx_oword_t md_stat; |
8ceee660 BH |
693 | int count; |
694 | ||
177dfcd8 BH |
695 | /* wait upto 50ms - taken max from datasheet */ |
696 | for (count = 0; count < 5000; count++) { | |
80cb9a0f BH |
697 | efx_reado(efx, &md_stat, FR_AB_MD_STAT); |
698 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { | |
699 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || | |
700 | EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { | |
62776d03 BH |
701 | netif_err(efx, hw, efx->net_dev, |
702 | "error from GMII access " | |
703 | EFX_OWORD_FMT"\n", | |
704 | EFX_OWORD_VAL(md_stat)); | |
8ceee660 BH |
705 | return -EIO; |
706 | } | |
707 | return 0; | |
708 | } | |
709 | udelay(10); | |
710 | } | |
62776d03 | 711 | netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n"); |
8ceee660 BH |
712 | return -ETIMEDOUT; |
713 | } | |
714 | ||
68e7f45e BH |
715 | /* Write an MDIO register of a PHY connected to Falcon. */ |
716 | static int falcon_mdio_write(struct net_device *net_dev, | |
717 | int prtad, int devad, u16 addr, u16 value) | |
8ceee660 | 718 | { |
767e468c | 719 | struct efx_nic *efx = netdev_priv(net_dev); |
4833f02a | 720 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 721 | efx_oword_t reg; |
68e7f45e | 722 | int rc; |
8ceee660 | 723 | |
62776d03 BH |
724 | netif_vdbg(efx, hw, efx->net_dev, |
725 | "writing MDIO %d register %d.%d with 0x%04x\n", | |
68e7f45e | 726 | prtad, devad, addr, value); |
8ceee660 | 727 | |
4833f02a | 728 | mutex_lock(&nic_data->mdio_lock); |
8ceee660 | 729 | |
68e7f45e BH |
730 | /* Check MDIO not currently being accessed */ |
731 | rc = falcon_gmii_wait(efx); | |
732 | if (rc) | |
8ceee660 BH |
733 | goto out; |
734 | ||
735 | /* Write the address/ID register */ | |
3e6c4538 | 736 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 737 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 738 | |
3e6c4538 BH |
739 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
740 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 741 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
742 | |
743 | /* Write data */ | |
3e6c4538 | 744 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); |
12d00cad | 745 | efx_writeo(efx, ®, FR_AB_MD_TXD); |
8ceee660 BH |
746 | |
747 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
748 | FRF_AB_MD_WRC, 1, |
749 | FRF_AB_MD_GC, 0); | |
12d00cad | 750 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
751 | |
752 | /* Wait for data to be written */ | |
68e7f45e BH |
753 | rc = falcon_gmii_wait(efx); |
754 | if (rc) { | |
8ceee660 BH |
755 | /* Abort the write operation */ |
756 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
757 | FRF_AB_MD_WRC, 0, |
758 | FRF_AB_MD_GC, 1); | |
12d00cad | 759 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
760 | udelay(10); |
761 | } | |
762 | ||
ab867461 | 763 | out: |
4833f02a | 764 | mutex_unlock(&nic_data->mdio_lock); |
68e7f45e | 765 | return rc; |
8ceee660 BH |
766 | } |
767 | ||
68e7f45e BH |
768 | /* Read an MDIO register of a PHY connected to Falcon. */ |
769 | static int falcon_mdio_read(struct net_device *net_dev, | |
770 | int prtad, int devad, u16 addr) | |
8ceee660 | 771 | { |
767e468c | 772 | struct efx_nic *efx = netdev_priv(net_dev); |
4833f02a | 773 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 774 | efx_oword_t reg; |
68e7f45e | 775 | int rc; |
8ceee660 | 776 | |
4833f02a | 777 | mutex_lock(&nic_data->mdio_lock); |
8ceee660 | 778 | |
68e7f45e BH |
779 | /* Check MDIO not currently being accessed */ |
780 | rc = falcon_gmii_wait(efx); | |
781 | if (rc) | |
8ceee660 BH |
782 | goto out; |
783 | ||
3e6c4538 | 784 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 785 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 786 | |
3e6c4538 BH |
787 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
788 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 789 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
790 | |
791 | /* Request data to be read */ | |
3e6c4538 | 792 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); |
12d00cad | 793 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
794 | |
795 | /* Wait for data to become available */ | |
68e7f45e BH |
796 | rc = falcon_gmii_wait(efx); |
797 | if (rc == 0) { | |
12d00cad | 798 | efx_reado(efx, ®, FR_AB_MD_RXD); |
3e6c4538 | 799 | rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD); |
62776d03 BH |
800 | netif_vdbg(efx, hw, efx->net_dev, |
801 | "read from MDIO %d register %d.%d, got %04x\n", | |
802 | prtad, devad, addr, rc); | |
8ceee660 BH |
803 | } else { |
804 | /* Abort the read operation */ | |
805 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
806 | FRF_AB_MD_RIC, 0, |
807 | FRF_AB_MD_GC, 1); | |
12d00cad | 808 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 | 809 | |
62776d03 BH |
810 | netif_dbg(efx, hw, efx->net_dev, |
811 | "read from MDIO %d register %d.%d, got error %d\n", | |
812 | prtad, devad, addr, rc); | |
8ceee660 BH |
813 | } |
814 | ||
ab867461 | 815 | out: |
4833f02a | 816 | mutex_unlock(&nic_data->mdio_lock); |
68e7f45e | 817 | return rc; |
8ceee660 BH |
818 | } |
819 | ||
8ceee660 | 820 | /* This call is responsible for hooking in the MAC and PHY operations */ |
ef2b90ee | 821 | static int falcon_probe_port(struct efx_nic *efx) |
8ceee660 | 822 | { |
8fbca791 | 823 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 BH |
824 | int rc; |
825 | ||
96c45726 BH |
826 | switch (efx->phy_type) { |
827 | case PHY_TYPE_SFX7101: | |
828 | efx->phy_op = &falcon_sfx7101_phy_ops; | |
829 | break; | |
96c45726 BH |
830 | case PHY_TYPE_QT2022C2: |
831 | case PHY_TYPE_QT2025C: | |
b37b62fe | 832 | efx->phy_op = &falcon_qt202x_phy_ops; |
96c45726 | 833 | break; |
7e51b439 BH |
834 | case PHY_TYPE_TXC43128: |
835 | efx->phy_op = &falcon_txc_phy_ops; | |
836 | break; | |
96c45726 | 837 | default: |
62776d03 BH |
838 | netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n", |
839 | efx->phy_type); | |
96c45726 BH |
840 | return -ENODEV; |
841 | } | |
842 | ||
c1c4f453 | 843 | /* Fill out MDIO structure and loopback modes */ |
4833f02a | 844 | mutex_init(&nic_data->mdio_lock); |
68e7f45e BH |
845 | efx->mdio.mdio_read = falcon_mdio_read; |
846 | efx->mdio.mdio_write = falcon_mdio_write; | |
c1c4f453 BH |
847 | rc = efx->phy_op->probe(efx); |
848 | if (rc != 0) | |
849 | return rc; | |
8ceee660 | 850 | |
b895d73e SH |
851 | /* Initial assumption */ |
852 | efx->link_state.speed = 10000; | |
853 | efx->link_state.fd = true; | |
854 | ||
8ceee660 | 855 | /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ |
daeda630 | 856 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) |
04cc8cac | 857 | efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; |
8ceee660 | 858 | else |
04cc8cac | 859 | efx->wanted_fc = EFX_FC_RX; |
7a6b8f6f SH |
860 | if (efx->mdio.mmds & MDIO_DEVS_AN) |
861 | efx->wanted_fc |= EFX_FC_AUTO; | |
8ceee660 BH |
862 | |
863 | /* Allocate buffer for stats */ | |
152b6a62 BH |
864 | rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer, |
865 | FALCON_MAC_STATS_SIZE); | |
8ceee660 BH |
866 | if (rc) |
867 | return rc; | |
62776d03 BH |
868 | netif_dbg(efx, probe, efx->net_dev, |
869 | "stats buffer at %llx (virt %p phys %llx)\n", | |
870 | (u64)efx->stats_buffer.dma_addr, | |
871 | efx->stats_buffer.addr, | |
872 | (u64)virt_to_phys(efx->stats_buffer.addr)); | |
8fbca791 | 873 | nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset; |
8ceee660 BH |
874 | |
875 | return 0; | |
876 | } | |
877 | ||
ef2b90ee | 878 | static void falcon_remove_port(struct efx_nic *efx) |
8ceee660 | 879 | { |
ff3b00a0 | 880 | efx->phy_op->remove(efx); |
152b6a62 | 881 | efx_nic_free_buffer(efx, &efx->stats_buffer); |
8ceee660 BH |
882 | } |
883 | ||
8c8661e4 BH |
884 | /************************************************************************** |
885 | * | |
886 | * Falcon test code | |
887 | * | |
888 | **************************************************************************/ | |
889 | ||
0aa3fbaa BH |
890 | static int |
891 | falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out) | |
8c8661e4 | 892 | { |
4de92180 | 893 | struct falcon_nic_data *nic_data = efx->nic_data; |
8c8661e4 BH |
894 | struct falcon_nvconfig *nvconfig; |
895 | struct efx_spi_device *spi; | |
896 | void *region; | |
897 | int rc, magic_num, struct_ver; | |
898 | __le16 *word, *limit; | |
899 | u32 csum; | |
900 | ||
4de92180 BH |
901 | if (efx_spi_present(&nic_data->spi_flash)) |
902 | spi = &nic_data->spi_flash; | |
903 | else if (efx_spi_present(&nic_data->spi_eeprom)) | |
904 | spi = &nic_data->spi_eeprom; | |
905 | else | |
2f7f5730 BH |
906 | return -EINVAL; |
907 | ||
0a95f563 | 908 | region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); |
8c8661e4 BH |
909 | if (!region) |
910 | return -ENOMEM; | |
3e6c4538 | 911 | nvconfig = region + FALCON_NVCONFIG_OFFSET; |
8c8661e4 | 912 | |
4de92180 | 913 | mutex_lock(&nic_data->spi_lock); |
76884835 | 914 | rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region); |
4de92180 | 915 | mutex_unlock(&nic_data->spi_lock); |
8c8661e4 | 916 | if (rc) { |
62776d03 | 917 | netif_err(efx, hw, efx->net_dev, "Failed to read %s\n", |
4de92180 BH |
918 | efx_spi_present(&nic_data->spi_flash) ? |
919 | "flash" : "EEPROM"); | |
8c8661e4 BH |
920 | rc = -EIO; |
921 | goto out; | |
922 | } | |
923 | ||
924 | magic_num = le16_to_cpu(nvconfig->board_magic_num); | |
925 | struct_ver = le16_to_cpu(nvconfig->board_struct_ver); | |
926 | ||
927 | rc = -EINVAL; | |
3e6c4538 | 928 | if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) { |
62776d03 BH |
929 | netif_err(efx, hw, efx->net_dev, |
930 | "NVRAM bad magic 0x%x\n", magic_num); | |
8c8661e4 BH |
931 | goto out; |
932 | } | |
933 | if (struct_ver < 2) { | |
62776d03 BH |
934 | netif_err(efx, hw, efx->net_dev, |
935 | "NVRAM has ancient version 0x%x\n", struct_ver); | |
8c8661e4 BH |
936 | goto out; |
937 | } else if (struct_ver < 4) { | |
938 | word = &nvconfig->board_magic_num; | |
939 | limit = (__le16 *) (nvconfig + 1); | |
940 | } else { | |
941 | word = region; | |
0a95f563 | 942 | limit = region + FALCON_NVCONFIG_END; |
8c8661e4 BH |
943 | } |
944 | for (csum = 0; word < limit; ++word) | |
945 | csum += le16_to_cpu(*word); | |
946 | ||
947 | if (~csum & 0xffff) { | |
62776d03 BH |
948 | netif_err(efx, hw, efx->net_dev, |
949 | "NVRAM has incorrect checksum\n"); | |
8c8661e4 BH |
950 | goto out; |
951 | } | |
952 | ||
953 | rc = 0; | |
954 | if (nvconfig_out) | |
955 | memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig)); | |
956 | ||
957 | out: | |
958 | kfree(region); | |
959 | return rc; | |
960 | } | |
961 | ||
0aa3fbaa BH |
962 | static int falcon_test_nvram(struct efx_nic *efx) |
963 | { | |
964 | return falcon_read_nvram(efx, NULL); | |
965 | } | |
966 | ||
152b6a62 | 967 | static const struct efx_nic_register_test falcon_b0_register_tests[] = { |
3e6c4538 | 968 | { FR_AZ_ADR_REGION, |
4cddca54 | 969 | EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) }, |
3e6c4538 | 970 | { FR_AZ_RX_CFG, |
8c8661e4 | 971 | EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, |
3e6c4538 | 972 | { FR_AZ_TX_CFG, |
8c8661e4 | 973 | EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 974 | { FR_AZ_TX_RESERVED, |
8c8661e4 | 975 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, |
3e6c4538 | 976 | { FR_AB_MAC_CTRL, |
8c8661e4 | 977 | EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 978 | { FR_AZ_SRM_TX_DC_CFG, |
8c8661e4 | 979 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 980 | { FR_AZ_RX_DC_CFG, |
8c8661e4 | 981 | EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 982 | { FR_AZ_RX_DC_PF_WM, |
8c8661e4 | 983 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 984 | { FR_BZ_DP_CTRL, |
8c8661e4 | 985 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 986 | { FR_AB_GM_CFG2, |
177dfcd8 | 987 | EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 988 | { FR_AB_GMF_CFG0, |
177dfcd8 | 989 | EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 990 | { FR_AB_XM_GLB_CFG, |
8c8661e4 | 991 | EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 992 | { FR_AB_XM_TX_CFG, |
8c8661e4 | 993 | EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 994 | { FR_AB_XM_RX_CFG, |
8c8661e4 | 995 | EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 996 | { FR_AB_XM_RX_PARAM, |
8c8661e4 | 997 | EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 998 | { FR_AB_XM_FC, |
8c8661e4 | 999 | EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1000 | { FR_AB_XM_ADR_LO, |
8c8661e4 | 1001 | EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 1002 | { FR_AB_XX_SD_CTL, |
8c8661e4 BH |
1003 | EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, |
1004 | }; | |
1005 | ||
152b6a62 BH |
1006 | static int falcon_b0_test_registers(struct efx_nic *efx) |
1007 | { | |
1008 | return efx_nic_test_registers(efx, falcon_b0_register_tests, | |
1009 | ARRAY_SIZE(falcon_b0_register_tests)); | |
1010 | } | |
1011 | ||
8ceee660 BH |
1012 | /************************************************************************** |
1013 | * | |
1014 | * Device reset | |
1015 | * | |
1016 | ************************************************************************** | |
1017 | */ | |
1018 | ||
1019 | /* Resets NIC to known state. This routine must be called in process | |
1020 | * context and is allowed to sleep. */ | |
4de92180 | 1021 | static int __falcon_reset_hw(struct efx_nic *efx, enum reset_type method) |
8ceee660 BH |
1022 | { |
1023 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1024 | efx_oword_t glb_ctl_reg_ker; | |
1025 | int rc; | |
1026 | ||
62776d03 BH |
1027 | netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n", |
1028 | RESET_TYPE(method)); | |
8ceee660 BH |
1029 | |
1030 | /* Initiate device reset */ | |
1031 | if (method == RESET_TYPE_WORLD) { | |
1032 | rc = pci_save_state(efx->pci_dev); | |
1033 | if (rc) { | |
62776d03 BH |
1034 | netif_err(efx, drv, efx->net_dev, |
1035 | "failed to backup PCI state of primary " | |
1036 | "function prior to hardware reset\n"); | |
8ceee660 BH |
1037 | goto fail1; |
1038 | } | |
152b6a62 | 1039 | if (efx_nic_is_dual_func(efx)) { |
8ceee660 BH |
1040 | rc = pci_save_state(nic_data->pci_dev2); |
1041 | if (rc) { | |
62776d03 BH |
1042 | netif_err(efx, drv, efx->net_dev, |
1043 | "failed to backup PCI state of " | |
1044 | "secondary function prior to " | |
1045 | "hardware reset\n"); | |
8ceee660 BH |
1046 | goto fail2; |
1047 | } | |
1048 | } | |
1049 | ||
1050 | EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, | |
3e6c4538 BH |
1051 | FRF_AB_EXT_PHY_RST_DUR, |
1052 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
1053 | FRF_AB_SWRST, 1); | |
8ceee660 | 1054 | } else { |
8ceee660 | 1055 | EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, |
3e6c4538 BH |
1056 | /* exclude PHY from "invisible" reset */ |
1057 | FRF_AB_EXT_PHY_RST_CTL, | |
1058 | method == RESET_TYPE_INVISIBLE, | |
1059 | /* exclude EEPROM/flash and PCIe */ | |
1060 | FRF_AB_PCIE_CORE_RST_CTL, 1, | |
1061 | FRF_AB_PCIE_NSTKY_RST_CTL, 1, | |
1062 | FRF_AB_PCIE_SD_RST_CTL, 1, | |
1063 | FRF_AB_EE_RST_CTL, 1, | |
1064 | FRF_AB_EXT_PHY_RST_DUR, | |
1065 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
1066 | FRF_AB_SWRST, 1); | |
1067 | } | |
12d00cad | 1068 | efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
8ceee660 | 1069 | |
62776d03 | 1070 | netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n"); |
8ceee660 BH |
1071 | schedule_timeout_uninterruptible(HZ / 20); |
1072 | ||
1073 | /* Restore PCI configuration if needed */ | |
1074 | if (method == RESET_TYPE_WORLD) { | |
152b6a62 | 1075 | if (efx_nic_is_dual_func(efx)) { |
8ceee660 BH |
1076 | rc = pci_restore_state(nic_data->pci_dev2); |
1077 | if (rc) { | |
62776d03 BH |
1078 | netif_err(efx, drv, efx->net_dev, |
1079 | "failed to restore PCI config for " | |
1080 | "the secondary function\n"); | |
8ceee660 BH |
1081 | goto fail3; |
1082 | } | |
1083 | } | |
1084 | rc = pci_restore_state(efx->pci_dev); | |
1085 | if (rc) { | |
62776d03 BH |
1086 | netif_err(efx, drv, efx->net_dev, |
1087 | "failed to restore PCI config for the " | |
1088 | "primary function\n"); | |
8ceee660 BH |
1089 | goto fail4; |
1090 | } | |
62776d03 BH |
1091 | netif_dbg(efx, drv, efx->net_dev, |
1092 | "successfully restored PCI config\n"); | |
8ceee660 BH |
1093 | } |
1094 | ||
1095 | /* Assert that reset complete */ | |
12d00cad | 1096 | efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
3e6c4538 | 1097 | if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { |
8ceee660 | 1098 | rc = -ETIMEDOUT; |
62776d03 BH |
1099 | netif_err(efx, hw, efx->net_dev, |
1100 | "timed out waiting for hardware reset\n"); | |
8ceee660 BH |
1101 | goto fail5; |
1102 | } | |
62776d03 | 1103 | netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n"); |
8ceee660 BH |
1104 | |
1105 | return 0; | |
1106 | ||
1107 | /* pci_save_state() and pci_restore_state() MUST be called in pairs */ | |
1108 | fail2: | |
1109 | fail3: | |
1110 | pci_restore_state(efx->pci_dev); | |
1111 | fail1: | |
1112 | fail4: | |
1113 | fail5: | |
1114 | return rc; | |
1115 | } | |
1116 | ||
4de92180 BH |
1117 | static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) |
1118 | { | |
1119 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1120 | int rc; | |
1121 | ||
1122 | mutex_lock(&nic_data->spi_lock); | |
1123 | rc = __falcon_reset_hw(efx, method); | |
1124 | mutex_unlock(&nic_data->spi_lock); | |
1125 | ||
1126 | return rc; | |
1127 | } | |
1128 | ||
ef2b90ee | 1129 | static void falcon_monitor(struct efx_nic *efx) |
fe75820b | 1130 | { |
fdaa9aed | 1131 | bool link_changed; |
fe75820b BH |
1132 | int rc; |
1133 | ||
fdaa9aed SH |
1134 | BUG_ON(!mutex_is_locked(&efx->mac_lock)); |
1135 | ||
fe75820b BH |
1136 | rc = falcon_board(efx)->type->monitor(efx); |
1137 | if (rc) { | |
62776d03 BH |
1138 | netif_err(efx, hw, efx->net_dev, |
1139 | "Board sensor %s; shutting down PHY\n", | |
1140 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
fe75820b | 1141 | efx->phy_mode |= PHY_MODE_LOW_POWER; |
d3245b28 BH |
1142 | rc = __efx_reconfigure_port(efx); |
1143 | WARN_ON(rc); | |
fe75820b | 1144 | } |
fdaa9aed SH |
1145 | |
1146 | if (LOOPBACK_INTERNAL(efx)) | |
1147 | link_changed = falcon_loopback_link_poll(efx); | |
1148 | else | |
1149 | link_changed = efx->phy_op->poll(efx); | |
1150 | ||
1151 | if (link_changed) { | |
1152 | falcon_stop_nic_stats(efx); | |
1153 | falcon_deconfigure_mac_wrapper(efx); | |
1154 | ||
8fbca791 | 1155 | falcon_reset_macs(efx); |
d3245b28 BH |
1156 | rc = efx->mac_op->reconfigure(efx); |
1157 | BUG_ON(rc); | |
fdaa9aed SH |
1158 | |
1159 | falcon_start_nic_stats(efx); | |
1160 | ||
1161 | efx_link_status_changed(efx); | |
1162 | } | |
1163 | ||
8fbca791 | 1164 | falcon_poll_xmac(efx); |
fe75820b BH |
1165 | } |
1166 | ||
8ceee660 BH |
1167 | /* Zeroes out the SRAM contents. This routine must be called in |
1168 | * process context and is allowed to sleep. | |
1169 | */ | |
1170 | static int falcon_reset_sram(struct efx_nic *efx) | |
1171 | { | |
1172 | efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; | |
1173 | int count; | |
1174 | ||
1175 | /* Set the SRAM wake/sleep GPIO appropriately. */ | |
12d00cad | 1176 | efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
3e6c4538 BH |
1177 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); |
1178 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); | |
12d00cad | 1179 | efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
8ceee660 BH |
1180 | |
1181 | /* Initiate SRAM reset */ | |
1182 | EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, | |
3e6c4538 BH |
1183 | FRF_AZ_SRM_INIT_EN, 1, |
1184 | FRF_AZ_SRM_NB_SZ, 0); | |
12d00cad | 1185 | efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
8ceee660 BH |
1186 | |
1187 | /* Wait for SRAM reset to complete */ | |
1188 | count = 0; | |
1189 | do { | |
62776d03 BH |
1190 | netif_dbg(efx, hw, efx->net_dev, |
1191 | "waiting for SRAM reset (attempt %d)...\n", count); | |
8ceee660 BH |
1192 | |
1193 | /* SRAM reset is slow; expect around 16ms */ | |
1194 | schedule_timeout_uninterruptible(HZ / 50); | |
1195 | ||
1196 | /* Check for reset complete */ | |
12d00cad | 1197 | efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
3e6c4538 | 1198 | if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { |
62776d03 BH |
1199 | netif_dbg(efx, hw, efx->net_dev, |
1200 | "SRAM reset complete\n"); | |
8ceee660 BH |
1201 | |
1202 | return 0; | |
1203 | } | |
1204 | } while (++count < 20); /* wait upto 0.4 sec */ | |
1205 | ||
62776d03 | 1206 | netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n"); |
8ceee660 BH |
1207 | return -ETIMEDOUT; |
1208 | } | |
1209 | ||
4de92180 BH |
1210 | static void falcon_spi_device_init(struct efx_nic *efx, |
1211 | struct efx_spi_device *spi_device, | |
4a5b504d BH |
1212 | unsigned int device_id, u32 device_type) |
1213 | { | |
4a5b504d | 1214 | if (device_type != 0) { |
4a5b504d BH |
1215 | spi_device->device_id = device_id; |
1216 | spi_device->size = | |
1217 | 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE); | |
1218 | spi_device->addr_len = | |
1219 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN); | |
1220 | spi_device->munge_address = (spi_device->size == 1 << 9 && | |
1221 | spi_device->addr_len == 1); | |
f4150724 BH |
1222 | spi_device->erase_command = |
1223 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD); | |
1224 | spi_device->erase_size = | |
1225 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
1226 | SPI_DEV_TYPE_ERASE_SIZE); | |
4a5b504d BH |
1227 | spi_device->block_size = |
1228 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
1229 | SPI_DEV_TYPE_BLOCK_SIZE); | |
4a5b504d | 1230 | } else { |
4de92180 | 1231 | spi_device->size = 0; |
4a5b504d | 1232 | } |
4a5b504d BH |
1233 | } |
1234 | ||
8ceee660 BH |
1235 | /* Extract non-volatile configuration */ |
1236 | static int falcon_probe_nvconfig(struct efx_nic *efx) | |
1237 | { | |
4de92180 | 1238 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 1239 | struct falcon_nvconfig *nvconfig; |
8ceee660 BH |
1240 | int rc; |
1241 | ||
8ceee660 | 1242 | nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); |
4a5b504d BH |
1243 | if (!nvconfig) |
1244 | return -ENOMEM; | |
8ceee660 | 1245 | |
8c8661e4 | 1246 | rc = falcon_read_nvram(efx, nvconfig); |
6c88b0b6 | 1247 | if (rc) |
4de92180 | 1248 | goto out; |
6c88b0b6 BH |
1249 | |
1250 | efx->phy_type = nvconfig->board_v2.port0_phy_type; | |
1251 | efx->mdio.prtad = nvconfig->board_v2.port0_phy_addr; | |
1252 | ||
1253 | if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { | |
4de92180 BH |
1254 | falcon_spi_device_init( |
1255 | efx, &nic_data->spi_flash, FFE_AB_SPI_DEVICE_FLASH, | |
6c88b0b6 BH |
1256 | le32_to_cpu(nvconfig->board_v3 |
1257 | .spi_device_type[FFE_AB_SPI_DEVICE_FLASH])); | |
4de92180 BH |
1258 | falcon_spi_device_init( |
1259 | efx, &nic_data->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM, | |
6c88b0b6 BH |
1260 | le32_to_cpu(nvconfig->board_v3 |
1261 | .spi_device_type[FFE_AB_SPI_DEVICE_EEPROM])); | |
8ceee660 BH |
1262 | } |
1263 | ||
8c8661e4 BH |
1264 | /* Read the MAC addresses */ |
1265 | memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN); | |
1266 | ||
62776d03 BH |
1267 | netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n", |
1268 | efx->phy_type, efx->mdio.prtad); | |
8ceee660 | 1269 | |
6c88b0b6 BH |
1270 | rc = falcon_probe_board(efx, |
1271 | le16_to_cpu(nvconfig->board_v2.board_revision)); | |
4de92180 | 1272 | out: |
8ceee660 BH |
1273 | kfree(nvconfig); |
1274 | return rc; | |
1275 | } | |
1276 | ||
4a5b504d BH |
1277 | /* Probe all SPI devices on the NIC */ |
1278 | static void falcon_probe_spi_devices(struct efx_nic *efx) | |
1279 | { | |
4de92180 | 1280 | struct falcon_nic_data *nic_data = efx->nic_data; |
4a5b504d | 1281 | efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; |
2f7f5730 | 1282 | int boot_dev; |
4a5b504d | 1283 | |
12d00cad BH |
1284 | efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL); |
1285 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
1286 | efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); | |
4a5b504d | 1287 | |
3e6c4538 BH |
1288 | if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { |
1289 | boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? | |
1290 | FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM); | |
62776d03 BH |
1291 | netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n", |
1292 | boot_dev == FFE_AB_SPI_DEVICE_FLASH ? | |
1293 | "flash" : "EEPROM"); | |
2f7f5730 BH |
1294 | } else { |
1295 | /* Disable VPD and set clock dividers to safe | |
1296 | * values for initial programming. */ | |
1297 | boot_dev = -1; | |
62776d03 BH |
1298 | netif_dbg(efx, probe, efx->net_dev, |
1299 | "Booted from internal ASIC settings;" | |
1300 | " setting SPI config\n"); | |
3e6c4538 | 1301 | EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0, |
2f7f5730 | 1302 | /* 125 MHz / 7 ~= 20 MHz */ |
3e6c4538 | 1303 | FRF_AB_EE_SF_CLOCK_DIV, 7, |
2f7f5730 | 1304 | /* 125 MHz / 63 ~= 2 MHz */ |
3e6c4538 | 1305 | FRF_AB_EE_EE_CLOCK_DIV, 63); |
12d00cad | 1306 | efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); |
4a5b504d BH |
1307 | } |
1308 | ||
4de92180 BH |
1309 | mutex_init(&nic_data->spi_lock); |
1310 | ||
3e6c4538 | 1311 | if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) |
4de92180 | 1312 | falcon_spi_device_init(efx, &nic_data->spi_flash, |
3e6c4538 | 1313 | FFE_AB_SPI_DEVICE_FLASH, |
2f7f5730 | 1314 | default_flash_type); |
3e6c4538 | 1315 | if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM) |
4de92180 | 1316 | falcon_spi_device_init(efx, &nic_data->spi_eeprom, |
3e6c4538 | 1317 | FFE_AB_SPI_DEVICE_EEPROM, |
2f7f5730 | 1318 | large_eeprom_type); |
4a5b504d BH |
1319 | } |
1320 | ||
ef2b90ee | 1321 | static int falcon_probe_nic(struct efx_nic *efx) |
8ceee660 BH |
1322 | { |
1323 | struct falcon_nic_data *nic_data; | |
e775fb93 | 1324 | struct falcon_board *board; |
8ceee660 BH |
1325 | int rc; |
1326 | ||
8ceee660 BH |
1327 | /* Allocate storage for hardware specific data */ |
1328 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); | |
88c59425 BH |
1329 | if (!nic_data) |
1330 | return -ENOMEM; | |
5daab96d | 1331 | efx->nic_data = nic_data; |
8ceee660 | 1332 | |
57849460 BH |
1333 | rc = -ENODEV; |
1334 | ||
1335 | if (efx_nic_fpga_ver(efx) != 0) { | |
62776d03 BH |
1336 | netif_err(efx, probe, efx->net_dev, |
1337 | "Falcon FPGA not supported\n"); | |
8ceee660 | 1338 | goto fail1; |
57849460 BH |
1339 | } |
1340 | ||
1341 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { | |
1342 | efx_oword_t nic_stat; | |
1343 | struct pci_dev *dev; | |
1344 | u8 pci_rev = efx->pci_dev->revision; | |
8ceee660 | 1345 | |
57849460 | 1346 | if ((pci_rev == 0xff) || (pci_rev == 0)) { |
62776d03 BH |
1347 | netif_err(efx, probe, efx->net_dev, |
1348 | "Falcon rev A0 not supported\n"); | |
57849460 BH |
1349 | goto fail1; |
1350 | } | |
1351 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
1352 | if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) { | |
62776d03 BH |
1353 | netif_err(efx, probe, efx->net_dev, |
1354 | "Falcon rev A1 1G not supported\n"); | |
57849460 BH |
1355 | goto fail1; |
1356 | } | |
1357 | if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) { | |
62776d03 BH |
1358 | netif_err(efx, probe, efx->net_dev, |
1359 | "Falcon rev A1 PCI-X not supported\n"); | |
57849460 BH |
1360 | goto fail1; |
1361 | } | |
8ceee660 | 1362 | |
57849460 | 1363 | dev = pci_dev_get(efx->pci_dev); |
8ceee660 BH |
1364 | while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID, |
1365 | dev))) { | |
1366 | if (dev->bus == efx->pci_dev->bus && | |
1367 | dev->devfn == efx->pci_dev->devfn + 1) { | |
1368 | nic_data->pci_dev2 = dev; | |
1369 | break; | |
1370 | } | |
1371 | } | |
1372 | if (!nic_data->pci_dev2) { | |
62776d03 BH |
1373 | netif_err(efx, probe, efx->net_dev, |
1374 | "failed to find secondary function\n"); | |
8ceee660 BH |
1375 | rc = -ENODEV; |
1376 | goto fail2; | |
1377 | } | |
1378 | } | |
1379 | ||
1380 | /* Now we can reset the NIC */ | |
4de92180 | 1381 | rc = __falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 | 1382 | if (rc) { |
62776d03 | 1383 | netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n"); |
8ceee660 BH |
1384 | goto fail3; |
1385 | } | |
1386 | ||
1387 | /* Allocate memory for INT_KER */ | |
152b6a62 | 1388 | rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); |
8ceee660 BH |
1389 | if (rc) |
1390 | goto fail4; | |
1391 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
1392 | ||
62776d03 BH |
1393 | netif_dbg(efx, probe, efx->net_dev, |
1394 | "INT_KER at %llx (virt %p phys %llx)\n", | |
1395 | (u64)efx->irq_status.dma_addr, | |
1396 | efx->irq_status.addr, | |
1397 | (u64)virt_to_phys(efx->irq_status.addr)); | |
8ceee660 | 1398 | |
4a5b504d BH |
1399 | falcon_probe_spi_devices(efx); |
1400 | ||
8ceee660 BH |
1401 | /* Read in the non-volatile configuration */ |
1402 | rc = falcon_probe_nvconfig(efx); | |
6c88b0b6 BH |
1403 | if (rc) { |
1404 | if (rc == -EINVAL) | |
1405 | netif_err(efx, probe, efx->net_dev, "NVRAM is invalid\n"); | |
8ceee660 | 1406 | goto fail5; |
6c88b0b6 | 1407 | } |
8ceee660 | 1408 | |
37b5a603 | 1409 | /* Initialise I2C adapter */ |
e775fb93 BH |
1410 | board = falcon_board(efx); |
1411 | board->i2c_adap.owner = THIS_MODULE; | |
1412 | board->i2c_data = falcon_i2c_bit_operations; | |
1413 | board->i2c_data.data = efx; | |
1414 | board->i2c_adap.algo_data = &board->i2c_data; | |
1415 | board->i2c_adap.dev.parent = &efx->pci_dev->dev; | |
1416 | strlcpy(board->i2c_adap.name, "SFC4000 GPIO", | |
1417 | sizeof(board->i2c_adap.name)); | |
1418 | rc = i2c_bit_add_bus(&board->i2c_adap); | |
37b5a603 BH |
1419 | if (rc) |
1420 | goto fail5; | |
1421 | ||
44838a44 | 1422 | rc = falcon_board(efx)->type->init(efx); |
278c0621 | 1423 | if (rc) { |
62776d03 BH |
1424 | netif_err(efx, probe, efx->net_dev, |
1425 | "failed to initialise board\n"); | |
278c0621 BH |
1426 | goto fail6; |
1427 | } | |
1428 | ||
55edc6e6 BH |
1429 | nic_data->stats_disable_count = 1; |
1430 | setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func, | |
1431 | (unsigned long)efx); | |
1432 | ||
8ceee660 BH |
1433 | return 0; |
1434 | ||
278c0621 | 1435 | fail6: |
e775fb93 BH |
1436 | BUG_ON(i2c_del_adapter(&board->i2c_adap)); |
1437 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); | |
8ceee660 | 1438 | fail5: |
152b6a62 | 1439 | efx_nic_free_buffer(efx, &efx->irq_status); |
8ceee660 | 1440 | fail4: |
8ceee660 BH |
1441 | fail3: |
1442 | if (nic_data->pci_dev2) { | |
1443 | pci_dev_put(nic_data->pci_dev2); | |
1444 | nic_data->pci_dev2 = NULL; | |
1445 | } | |
1446 | fail2: | |
8ceee660 BH |
1447 | fail1: |
1448 | kfree(efx->nic_data); | |
1449 | return rc; | |
1450 | } | |
1451 | ||
56241ceb BH |
1452 | static void falcon_init_rx_cfg(struct efx_nic *efx) |
1453 | { | |
1454 | /* Prior to Siena the RX DMA engine will split each frame at | |
1455 | * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to | |
1456 | * be so large that that never happens. */ | |
1457 | const unsigned huge_buf_size = (3 * 4096) >> 5; | |
1458 | /* RX control FIFO thresholds (32 entries) */ | |
1459 | const unsigned ctrl_xon_thr = 20; | |
1460 | const unsigned ctrl_xoff_thr = 25; | |
1461 | /* RX data FIFO thresholds (256-byte units; size varies) */ | |
152b6a62 BH |
1462 | int data_xon_thr = efx_nic_rx_xon_thresh >> 8; |
1463 | int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8; | |
56241ceb BH |
1464 | efx_oword_t reg; |
1465 | ||
12d00cad | 1466 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
daeda630 | 1467 | if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) { |
625b4514 BH |
1468 | /* Data FIFO size is 5.5K */ |
1469 | if (data_xon_thr < 0) | |
1470 | data_xon_thr = 512 >> 8; | |
1471 | if (data_xoff_thr < 0) | |
1472 | data_xoff_thr = 2048 >> 8; | |
3e6c4538 BH |
1473 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); |
1474 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, | |
1475 | huge_buf_size); | |
1476 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr); | |
1477 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr); | |
1478 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); | |
1479 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
56241ceb | 1480 | } else { |
625b4514 BH |
1481 | /* Data FIFO size is 80K; register fields moved */ |
1482 | if (data_xon_thr < 0) | |
1483 | data_xon_thr = 27648 >> 8; /* ~3*max MTU */ | |
1484 | if (data_xoff_thr < 0) | |
1485 | data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */ | |
3e6c4538 BH |
1486 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); |
1487 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, | |
1488 | huge_buf_size); | |
1489 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr); | |
1490 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr); | |
1491 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); | |
1492 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
1493 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); | |
477e54eb BH |
1494 | |
1495 | /* Enable hash insertion. This is broken for the | |
1496 | * 'Falcon' hash so also select Toeplitz TCP/IPv4 and | |
1497 | * IPv4 hashes. */ | |
1498 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1); | |
1499 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1); | |
1500 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1); | |
56241ceb | 1501 | } |
4b0d29dc BH |
1502 | /* Always enable XOFF signal from RX FIFO. We enable |
1503 | * or disable transmission of pause frames at the MAC. */ | |
1504 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1); | |
12d00cad | 1505 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
56241ceb BH |
1506 | } |
1507 | ||
152b6a62 BH |
1508 | /* This call performs hardware-specific global initialisation, such as |
1509 | * defining the descriptor cache sizes and number of RSS channels. | |
1510 | * It does not set up any buffers, descriptor rings or event queues. | |
1511 | */ | |
1512 | static int falcon_init_nic(struct efx_nic *efx) | |
1513 | { | |
1514 | efx_oword_t temp; | |
1515 | int rc; | |
1516 | ||
1517 | /* Use on-chip SRAM */ | |
1518 | efx_reado(efx, &temp, FR_AB_NIC_STAT); | |
1519 | EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); | |
1520 | efx_writeo(efx, &temp, FR_AB_NIC_STAT); | |
1521 | ||
152b6a62 BH |
1522 | rc = falcon_reset_sram(efx); |
1523 | if (rc) | |
1524 | return rc; | |
1525 | ||
1526 | /* Clear the parity enables on the TX data fifos as | |
1527 | * they produce false parity errors because of timing issues | |
1528 | */ | |
1529 | if (EFX_WORKAROUND_5129(efx)) { | |
1530 | efx_reado(efx, &temp, FR_AZ_CSR_SPARE); | |
1531 | EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); | |
1532 | efx_writeo(efx, &temp, FR_AZ_CSR_SPARE); | |
1533 | } | |
1534 | ||
8ceee660 | 1535 | if (EFX_WORKAROUND_7244(efx)) { |
12d00cad | 1536 | efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL); |
3e6c4538 BH |
1537 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); |
1538 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); | |
1539 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); | |
1540 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); | |
12d00cad | 1541 | efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL); |
8ceee660 | 1542 | } |
8ceee660 | 1543 | |
3e6c4538 | 1544 | /* XXX This is documented only for Falcon A0/A1 */ |
8ceee660 BH |
1545 | /* Setup RX. Wait for descriptor is broken and must |
1546 | * be disabled. RXDP recovery shouldn't be needed, but is. | |
1547 | */ | |
12d00cad | 1548 | efx_reado(efx, &temp, FR_AA_RX_SELF_RST); |
3e6c4538 BH |
1549 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); |
1550 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); | |
8ceee660 | 1551 | if (EFX_WORKAROUND_5583(efx)) |
3e6c4538 | 1552 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); |
12d00cad | 1553 | efx_writeo(efx, &temp, FR_AA_RX_SELF_RST); |
8ceee660 | 1554 | |
8ceee660 BH |
1555 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 |
1556 | * descriptors (which is bad). | |
1557 | */ | |
12d00cad | 1558 | efx_reado(efx, &temp, FR_AZ_TX_CFG); |
3e6c4538 | 1559 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); |
12d00cad | 1560 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); |
8ceee660 | 1561 | |
56241ceb | 1562 | falcon_init_rx_cfg(efx); |
8ceee660 | 1563 | |
daeda630 | 1564 | if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) { |
477e54eb BH |
1565 | /* Set hash key for IPv4 */ |
1566 | memcpy(&temp, efx->rx_hash_key, sizeof(temp)); | |
1567 | efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY); | |
1568 | ||
1569 | /* Set destination of both TX and RX Flush events */ | |
3e6c4538 | 1570 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); |
12d00cad | 1571 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); |
8ceee660 BH |
1572 | } |
1573 | ||
152b6a62 BH |
1574 | efx_nic_init_common(efx); |
1575 | ||
8ceee660 BH |
1576 | return 0; |
1577 | } | |
1578 | ||
ef2b90ee | 1579 | static void falcon_remove_nic(struct efx_nic *efx) |
8ceee660 BH |
1580 | { |
1581 | struct falcon_nic_data *nic_data = efx->nic_data; | |
e775fb93 | 1582 | struct falcon_board *board = falcon_board(efx); |
37b5a603 BH |
1583 | int rc; |
1584 | ||
44838a44 | 1585 | board->type->fini(efx); |
278c0621 | 1586 | |
8c870379 | 1587 | /* Remove I2C adapter and clear it in preparation for a retry */ |
e775fb93 | 1588 | rc = i2c_del_adapter(&board->i2c_adap); |
37b5a603 | 1589 | BUG_ON(rc); |
e775fb93 | 1590 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); |
8ceee660 | 1591 | |
152b6a62 | 1592 | efx_nic_free_buffer(efx, &efx->irq_status); |
8ceee660 | 1593 | |
4de92180 | 1594 | __falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 BH |
1595 | |
1596 | /* Release the second function after the reset */ | |
1597 | if (nic_data->pci_dev2) { | |
1598 | pci_dev_put(nic_data->pci_dev2); | |
1599 | nic_data->pci_dev2 = NULL; | |
1600 | } | |
1601 | ||
1602 | /* Tear down the private nic state */ | |
1603 | kfree(efx->nic_data); | |
1604 | efx->nic_data = NULL; | |
1605 | } | |
1606 | ||
ef2b90ee | 1607 | static void falcon_update_nic_stats(struct efx_nic *efx) |
8ceee660 | 1608 | { |
55edc6e6 | 1609 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 BH |
1610 | efx_oword_t cnt; |
1611 | ||
55edc6e6 BH |
1612 | if (nic_data->stats_disable_count) |
1613 | return; | |
1614 | ||
12d00cad | 1615 | efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP); |
3e6c4538 BH |
1616 | efx->n_rx_nodesc_drop_cnt += |
1617 | EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); | |
55edc6e6 BH |
1618 | |
1619 | if (nic_data->stats_pending && | |
1620 | *nic_data->stats_dma_done == FALCON_STATS_DONE) { | |
1621 | nic_data->stats_pending = false; | |
1622 | rmb(); /* read the done flag before the stats */ | |
1623 | efx->mac_op->update_stats(efx); | |
1624 | } | |
1625 | } | |
1626 | ||
1627 | void falcon_start_nic_stats(struct efx_nic *efx) | |
1628 | { | |
1629 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1630 | ||
1631 | spin_lock_bh(&efx->stats_lock); | |
1632 | if (--nic_data->stats_disable_count == 0) | |
1633 | falcon_stats_request(efx); | |
1634 | spin_unlock_bh(&efx->stats_lock); | |
1635 | } | |
1636 | ||
1637 | void falcon_stop_nic_stats(struct efx_nic *efx) | |
1638 | { | |
1639 | struct falcon_nic_data *nic_data = efx->nic_data; | |
1640 | int i; | |
1641 | ||
1642 | might_sleep(); | |
1643 | ||
1644 | spin_lock_bh(&efx->stats_lock); | |
1645 | ++nic_data->stats_disable_count; | |
1646 | spin_unlock_bh(&efx->stats_lock); | |
1647 | ||
1648 | del_timer_sync(&nic_data->stats_timer); | |
1649 | ||
1650 | /* Wait enough time for the most recent transfer to | |
1651 | * complete. */ | |
1652 | for (i = 0; i < 4 && nic_data->stats_pending; i++) { | |
1653 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) | |
1654 | break; | |
1655 | msleep(1); | |
1656 | } | |
1657 | ||
1658 | spin_lock_bh(&efx->stats_lock); | |
1659 | falcon_stats_complete(efx); | |
1660 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
1661 | } |
1662 | ||
06629f07 BH |
1663 | static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) |
1664 | { | |
1665 | falcon_board(efx)->type->set_id_led(efx, mode); | |
1666 | } | |
1667 | ||
89c758fa BH |
1668 | /************************************************************************** |
1669 | * | |
1670 | * Wake on LAN | |
1671 | * | |
1672 | ************************************************************************** | |
1673 | */ | |
1674 | ||
1675 | static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol) | |
1676 | { | |
1677 | wol->supported = 0; | |
1678 | wol->wolopts = 0; | |
1679 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | |
1680 | } | |
1681 | ||
1682 | static int falcon_set_wol(struct efx_nic *efx, u32 type) | |
1683 | { | |
1684 | if (type != 0) | |
1685 | return -EINVAL; | |
1686 | return 0; | |
1687 | } | |
1688 | ||
8ceee660 BH |
1689 | /************************************************************************** |
1690 | * | |
754c653a | 1691 | * Revision-dependent attributes used by efx.c and nic.c |
8ceee660 BH |
1692 | * |
1693 | ************************************************************************** | |
1694 | */ | |
1695 | ||
daeda630 | 1696 | struct efx_nic_type falcon_a1_nic_type = { |
ef2b90ee BH |
1697 | .probe = falcon_probe_nic, |
1698 | .remove = falcon_remove_nic, | |
1699 | .init = falcon_init_nic, | |
1700 | .fini = efx_port_dummy_op_void, | |
1701 | .monitor = falcon_monitor, | |
1702 | .reset = falcon_reset_hw, | |
1703 | .probe_port = falcon_probe_port, | |
1704 | .remove_port = falcon_remove_port, | |
1705 | .prepare_flush = falcon_prepare_flush, | |
1706 | .update_stats = falcon_update_nic_stats, | |
1707 | .start_stats = falcon_start_nic_stats, | |
1708 | .stop_stats = falcon_stop_nic_stats, | |
06629f07 | 1709 | .set_id_led = falcon_set_id_led, |
ef2b90ee BH |
1710 | .push_irq_moderation = falcon_push_irq_moderation, |
1711 | .push_multicast_hash = falcon_push_multicast_hash, | |
d3245b28 | 1712 | .reconfigure_port = falcon_reconfigure_port, |
89c758fa BH |
1713 | .get_wol = falcon_get_wol, |
1714 | .set_wol = falcon_set_wol, | |
1715 | .resume_wol = efx_port_dummy_op_void, | |
0aa3fbaa | 1716 | .test_nvram = falcon_test_nvram, |
b895d73e SH |
1717 | .default_mac_ops = &falcon_xmac_operations, |
1718 | ||
daeda630 | 1719 | .revision = EFX_REV_FALCON_A1, |
8ceee660 | 1720 | .mem_map_size = 0x20000, |
3e6c4538 BH |
1721 | .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER, |
1722 | .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER, | |
1723 | .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER, | |
1724 | .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER, | |
1725 | .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER, | |
6d51d307 | 1726 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
8ceee660 BH |
1727 | .rx_buffer_padding = 0x24, |
1728 | .max_interrupt_mode = EFX_INT_MODE_MSI, | |
1729 | .phys_addr_channels = 4, | |
0228f5cd BH |
1730 | .tx_dc_base = 0x130000, |
1731 | .rx_dc_base = 0x100000, | |
c383b537 | 1732 | .offload_features = NETIF_F_IP_CSUM, |
eb9f6744 | 1733 | .reset_world_flags = ETH_RESET_IRQ, |
8ceee660 BH |
1734 | }; |
1735 | ||
daeda630 | 1736 | struct efx_nic_type falcon_b0_nic_type = { |
ef2b90ee BH |
1737 | .probe = falcon_probe_nic, |
1738 | .remove = falcon_remove_nic, | |
1739 | .init = falcon_init_nic, | |
1740 | .fini = efx_port_dummy_op_void, | |
1741 | .monitor = falcon_monitor, | |
1742 | .reset = falcon_reset_hw, | |
1743 | .probe_port = falcon_probe_port, | |
1744 | .remove_port = falcon_remove_port, | |
1745 | .prepare_flush = falcon_prepare_flush, | |
1746 | .update_stats = falcon_update_nic_stats, | |
1747 | .start_stats = falcon_start_nic_stats, | |
1748 | .stop_stats = falcon_stop_nic_stats, | |
06629f07 | 1749 | .set_id_led = falcon_set_id_led, |
ef2b90ee BH |
1750 | .push_irq_moderation = falcon_push_irq_moderation, |
1751 | .push_multicast_hash = falcon_push_multicast_hash, | |
d3245b28 | 1752 | .reconfigure_port = falcon_reconfigure_port, |
89c758fa BH |
1753 | .get_wol = falcon_get_wol, |
1754 | .set_wol = falcon_set_wol, | |
1755 | .resume_wol = efx_port_dummy_op_void, | |
9bfc4bb1 | 1756 | .test_registers = falcon_b0_test_registers, |
0aa3fbaa | 1757 | .test_nvram = falcon_test_nvram, |
b895d73e SH |
1758 | .default_mac_ops = &falcon_xmac_operations, |
1759 | ||
daeda630 | 1760 | .revision = EFX_REV_FALCON_B0, |
8ceee660 BH |
1761 | /* Map everything up to and including the RSS indirection |
1762 | * table. Don't map MSI-X table, MSI-X PBA since Linux | |
1763 | * requires that they not be mapped. */ | |
3e6c4538 BH |
1764 | .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL + |
1765 | FR_BZ_RX_INDIRECTION_TBL_STEP * | |
1766 | FR_BZ_RX_INDIRECTION_TBL_ROWS), | |
1767 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, | |
1768 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | |
1769 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | |
1770 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | |
1771 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | |
6d51d307 | 1772 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
39c9cf07 | 1773 | .rx_buffer_hash_size = 0x10, |
8ceee660 BH |
1774 | .rx_buffer_padding = 0, |
1775 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
1776 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | |
1777 | * interrupt handler only supports 32 | |
1778 | * channels */ | |
0228f5cd BH |
1779 | .tx_dc_base = 0x130000, |
1780 | .rx_dc_base = 0x100000, | |
b4187e42 | 1781 | .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE, |
eb9f6744 | 1782 | .reset_world_flags = ETH_RESET_IRQ, |
8ceee660 BH |
1783 | }; |
1784 |