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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
4 | * Copyright 2006-2008 Solarflare Communications Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/bitops.h> | |
12 | #include <linux/delay.h> | |
13 | #include <linux/pci.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/seq_file.h> | |
37b5a603 | 16 | #include <linux/i2c.h> |
f31a45d2 | 17 | #include <linux/mii.h> |
8ceee660 BH |
18 | #include "net_driver.h" |
19 | #include "bitfield.h" | |
20 | #include "efx.h" | |
21 | #include "mac.h" | |
8ceee660 BH |
22 | #include "spi.h" |
23 | #include "falcon.h" | |
3e6c4538 | 24 | #include "regs.h" |
12d00cad | 25 | #include "io.h" |
8ceee660 BH |
26 | #include "mdio_10g.h" |
27 | #include "phy.h" | |
8ceee660 BH |
28 | #include "workarounds.h" |
29 | ||
8986352a | 30 | /* Hardware control for SFC4000 (aka Falcon). */ |
8ceee660 | 31 | |
8ceee660 BH |
32 | /************************************************************************** |
33 | * | |
34 | * Configurable values | |
35 | * | |
36 | ************************************************************************** | |
37 | */ | |
38 | ||
8ceee660 BH |
39 | /* This is set to 16 for a good reason. In summary, if larger than |
40 | * 16, the descriptor cache holds more than a default socket | |
41 | * buffer's worth of packets (for UDP we can only have at most one | |
42 | * socket buffer's worth outstanding). This combined with the fact | |
43 | * that we only get 1 TX event per descriptor cache means the NIC | |
44 | * goes idle. | |
45 | */ | |
46 | #define TX_DC_ENTRIES 16 | |
46e1ac0f | 47 | #define TX_DC_ENTRIES_ORDER 1 |
8ceee660 BH |
48 | #define TX_DC_BASE 0x130000 |
49 | ||
50 | #define RX_DC_ENTRIES 64 | |
46e1ac0f | 51 | #define RX_DC_ENTRIES_ORDER 3 |
8ceee660 BH |
52 | #define RX_DC_BASE 0x100000 |
53 | ||
2f7f5730 BH |
54 | static const unsigned int |
55 | /* "Large" EEPROM device: Atmel AT25640 or similar | |
56 | * 8 KB, 16-bit address, 32 B write block */ | |
57 | large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN) | |
58 | | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
59 | | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)), | |
60 | /* Default flash device: Atmel AT25F1024 | |
61 | * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */ | |
62 | default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN) | |
63 | | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN) | |
64 | | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN) | |
65 | | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN) | |
66 | | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)); | |
67 | ||
8ceee660 BH |
68 | /* RX FIFO XOFF watermark |
69 | * | |
70 | * When the amount of the RX FIFO increases used increases past this | |
71 | * watermark send XOFF. Only used if RX flow control is enabled (ethtool -A) | |
72 | * This also has an effect on RX/TX arbitration | |
73 | */ | |
74 | static int rx_xoff_thresh_bytes = -1; | |
75 | module_param(rx_xoff_thresh_bytes, int, 0644); | |
76 | MODULE_PARM_DESC(rx_xoff_thresh_bytes, "RX fifo XOFF threshold"); | |
77 | ||
78 | /* RX FIFO XON watermark | |
79 | * | |
80 | * When the amount of the RX FIFO used decreases below this | |
81 | * watermark send XON. Only used if TX flow control is enabled (ethtool -A) | |
82 | * This also has an effect on RX/TX arbitration | |
83 | */ | |
84 | static int rx_xon_thresh_bytes = -1; | |
85 | module_param(rx_xon_thresh_bytes, int, 0644); | |
86 | MODULE_PARM_DESC(rx_xon_thresh_bytes, "RX fifo XON threshold"); | |
87 | ||
2c3c3d02 BH |
88 | /* If FALCON_MAX_INT_ERRORS internal errors occur within |
89 | * FALCON_INT_ERROR_EXPIRE seconds, we consider the NIC broken and | |
90 | * disable it. | |
91 | */ | |
92 | #define FALCON_INT_ERROR_EXPIRE 3600 | |
93 | #define FALCON_MAX_INT_ERRORS 5 | |
8ceee660 | 94 | |
6bc5d3a9 BH |
95 | /* We poll for events every FLUSH_INTERVAL ms, and check FLUSH_POLL_COUNT times |
96 | */ | |
97 | #define FALCON_FLUSH_INTERVAL 10 | |
98 | #define FALCON_FLUSH_POLL_COUNT 100 | |
8ceee660 BH |
99 | |
100 | /************************************************************************** | |
101 | * | |
102 | * Falcon constants | |
103 | * | |
104 | ************************************************************************** | |
105 | */ | |
106 | ||
8ceee660 BH |
107 | /* Size and alignment of special buffers (4KB) */ |
108 | #define FALCON_BUF_SIZE 4096 | |
109 | ||
127e6e10 BH |
110 | /* Depth of RX flush request fifo */ |
111 | #define FALCON_RX_FLUSH_COUNT 4 | |
112 | ||
8ceee660 | 113 | #define FALCON_IS_DUAL_FUNC(efx) \ |
55668611 | 114 | (falcon_rev(efx) < FALCON_REV_B0) |
8ceee660 BH |
115 | |
116 | /************************************************************************** | |
117 | * | |
118 | * Falcon hardware access | |
119 | * | |
120 | **************************************************************************/ | |
121 | ||
12d00cad BH |
122 | static inline void falcon_write_buf_tbl(struct efx_nic *efx, efx_qword_t *value, |
123 | unsigned int index) | |
124 | { | |
125 | efx_sram_writeq(efx, efx->membase + efx->type->buf_tbl_base, | |
126 | value, index); | |
127 | } | |
128 | ||
8ceee660 BH |
129 | /* Read the current event from the event queue */ |
130 | static inline efx_qword_t *falcon_event(struct efx_channel *channel, | |
131 | unsigned int index) | |
132 | { | |
133 | return (((efx_qword_t *) (channel->eventq.addr)) + index); | |
134 | } | |
135 | ||
136 | /* See if an event is present | |
137 | * | |
138 | * We check both the high and low dword of the event for all ones. We | |
139 | * wrote all ones when we cleared the event, and no valid event can | |
140 | * have all ones in either its high or low dwords. This approach is | |
141 | * robust against reordering. | |
142 | * | |
143 | * Note that using a single 64-bit comparison is incorrect; even | |
144 | * though the CPU read will be atomic, the DMA write may not be. | |
145 | */ | |
146 | static inline int falcon_event_present(efx_qword_t *event) | |
147 | { | |
148 | return (!(EFX_DWORD_IS_ALL_ONES(event->dword[0]) | | |
149 | EFX_DWORD_IS_ALL_ONES(event->dword[1]))); | |
150 | } | |
151 | ||
152 | /************************************************************************** | |
153 | * | |
154 | * I2C bus - this is a bit-bashing interface using GPIO pins | |
155 | * Note that it uses the output enables to tristate the outputs | |
156 | * SDA is the data pin and SCL is the clock | |
157 | * | |
158 | ************************************************************************** | |
159 | */ | |
37b5a603 | 160 | static void falcon_setsda(void *data, int state) |
8ceee660 | 161 | { |
37b5a603 | 162 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
163 | efx_oword_t reg; |
164 | ||
12d00cad | 165 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 166 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state); |
12d00cad | 167 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
8ceee660 BH |
168 | } |
169 | ||
37b5a603 | 170 | static void falcon_setscl(void *data, int state) |
8ceee660 | 171 | { |
37b5a603 | 172 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
173 | efx_oword_t reg; |
174 | ||
12d00cad | 175 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 176 | EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state); |
12d00cad | 177 | efx_writeo(efx, ®, FR_AB_GPIO_CTL); |
37b5a603 BH |
178 | } |
179 | ||
180 | static int falcon_getsda(void *data) | |
181 | { | |
182 | struct efx_nic *efx = (struct efx_nic *)data; | |
183 | efx_oword_t reg; | |
184 | ||
12d00cad | 185 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 186 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN); |
8ceee660 BH |
187 | } |
188 | ||
37b5a603 | 189 | static int falcon_getscl(void *data) |
8ceee660 | 190 | { |
37b5a603 | 191 | struct efx_nic *efx = (struct efx_nic *)data; |
8ceee660 BH |
192 | efx_oword_t reg; |
193 | ||
12d00cad | 194 | efx_reado(efx, ®, FR_AB_GPIO_CTL); |
3e6c4538 | 195 | return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN); |
8ceee660 BH |
196 | } |
197 | ||
37b5a603 BH |
198 | static struct i2c_algo_bit_data falcon_i2c_bit_operations = { |
199 | .setsda = falcon_setsda, | |
200 | .setscl = falcon_setscl, | |
8ceee660 BH |
201 | .getsda = falcon_getsda, |
202 | .getscl = falcon_getscl, | |
62c78329 | 203 | .udelay = 5, |
9dadae68 BH |
204 | /* Wait up to 50 ms for slave to let us pull SCL high */ |
205 | .timeout = DIV_ROUND_UP(HZ, 20), | |
8ceee660 BH |
206 | }; |
207 | ||
208 | /************************************************************************** | |
209 | * | |
210 | * Falcon special buffer handling | |
211 | * Special buffers are used for event queues and the TX and RX | |
212 | * descriptor rings. | |
213 | * | |
214 | *************************************************************************/ | |
215 | ||
216 | /* | |
217 | * Initialise a Falcon special buffer | |
218 | * | |
219 | * This will define a buffer (previously allocated via | |
220 | * falcon_alloc_special_buffer()) in Falcon's buffer table, allowing | |
221 | * it to be used for event queues, descriptor rings etc. | |
222 | */ | |
bc3c90a2 | 223 | static void |
8ceee660 BH |
224 | falcon_init_special_buffer(struct efx_nic *efx, |
225 | struct efx_special_buffer *buffer) | |
226 | { | |
227 | efx_qword_t buf_desc; | |
228 | int index; | |
229 | dma_addr_t dma_addr; | |
230 | int i; | |
231 | ||
232 | EFX_BUG_ON_PARANOID(!buffer->addr); | |
233 | ||
234 | /* Write buffer descriptors to NIC */ | |
235 | for (i = 0; i < buffer->entries; i++) { | |
236 | index = buffer->index + i; | |
237 | dma_addr = buffer->dma_addr + (i * 4096); | |
238 | EFX_LOG(efx, "mapping special buffer %d at %llx\n", | |
239 | index, (unsigned long long)dma_addr); | |
3e6c4538 BH |
240 | EFX_POPULATE_QWORD_3(buf_desc, |
241 | FRF_AZ_BUF_ADR_REGION, 0, | |
242 | FRF_AZ_BUF_ADR_FBUF, dma_addr >> 12, | |
243 | FRF_AZ_BUF_OWNER_ID_FBUF, 0); | |
12d00cad | 244 | falcon_write_buf_tbl(efx, &buf_desc, index); |
8ceee660 | 245 | } |
8ceee660 BH |
246 | } |
247 | ||
248 | /* Unmaps a buffer from Falcon and clears the buffer table entries */ | |
249 | static void | |
250 | falcon_fini_special_buffer(struct efx_nic *efx, | |
251 | struct efx_special_buffer *buffer) | |
252 | { | |
253 | efx_oword_t buf_tbl_upd; | |
254 | unsigned int start = buffer->index; | |
255 | unsigned int end = (buffer->index + buffer->entries - 1); | |
256 | ||
257 | if (!buffer->entries) | |
258 | return; | |
259 | ||
260 | EFX_LOG(efx, "unmapping special buffers %d-%d\n", | |
261 | buffer->index, buffer->index + buffer->entries - 1); | |
262 | ||
263 | EFX_POPULATE_OWORD_4(buf_tbl_upd, | |
3e6c4538 BH |
264 | FRF_AZ_BUF_UPD_CMD, 0, |
265 | FRF_AZ_BUF_CLR_CMD, 1, | |
266 | FRF_AZ_BUF_CLR_END_ID, end, | |
267 | FRF_AZ_BUF_CLR_START_ID, start); | |
12d00cad | 268 | efx_writeo(efx, &buf_tbl_upd, FR_AZ_BUF_TBL_UPD); |
8ceee660 BH |
269 | } |
270 | ||
271 | /* | |
272 | * Allocate a new Falcon special buffer | |
273 | * | |
274 | * This allocates memory for a new buffer, clears it and allocates a | |
275 | * new buffer ID range. It does not write into Falcon's buffer table. | |
276 | * | |
277 | * This call will allocate 4KB buffers, since Falcon can't use 8KB | |
278 | * buffers for event queues and descriptor rings. | |
279 | */ | |
280 | static int falcon_alloc_special_buffer(struct efx_nic *efx, | |
281 | struct efx_special_buffer *buffer, | |
282 | unsigned int len) | |
283 | { | |
8ceee660 BH |
284 | len = ALIGN(len, FALCON_BUF_SIZE); |
285 | ||
286 | buffer->addr = pci_alloc_consistent(efx->pci_dev, len, | |
287 | &buffer->dma_addr); | |
288 | if (!buffer->addr) | |
289 | return -ENOMEM; | |
290 | buffer->len = len; | |
291 | buffer->entries = len / FALCON_BUF_SIZE; | |
292 | BUG_ON(buffer->dma_addr & (FALCON_BUF_SIZE - 1)); | |
293 | ||
294 | /* All zeros is a potentially valid event so memset to 0xff */ | |
295 | memset(buffer->addr, 0xff, len); | |
296 | ||
297 | /* Select new buffer ID */ | |
0484e0db BH |
298 | buffer->index = efx->next_buffer_table; |
299 | efx->next_buffer_table += buffer->entries; | |
8ceee660 BH |
300 | |
301 | EFX_LOG(efx, "allocating special buffers %d-%d at %llx+%x " | |
9c8976a1 | 302 | "(virt %p phys %llx)\n", buffer->index, |
8ceee660 | 303 | buffer->index + buffer->entries - 1, |
9c8976a1 JSR |
304 | (u64)buffer->dma_addr, len, |
305 | buffer->addr, (u64)virt_to_phys(buffer->addr)); | |
8ceee660 BH |
306 | |
307 | return 0; | |
308 | } | |
309 | ||
310 | static void falcon_free_special_buffer(struct efx_nic *efx, | |
311 | struct efx_special_buffer *buffer) | |
312 | { | |
313 | if (!buffer->addr) | |
314 | return; | |
315 | ||
316 | EFX_LOG(efx, "deallocating special buffers %d-%d at %llx+%x " | |
9c8976a1 | 317 | "(virt %p phys %llx)\n", buffer->index, |
8ceee660 | 318 | buffer->index + buffer->entries - 1, |
9c8976a1 JSR |
319 | (u64)buffer->dma_addr, buffer->len, |
320 | buffer->addr, (u64)virt_to_phys(buffer->addr)); | |
8ceee660 BH |
321 | |
322 | pci_free_consistent(efx->pci_dev, buffer->len, buffer->addr, | |
323 | buffer->dma_addr); | |
324 | buffer->addr = NULL; | |
325 | buffer->entries = 0; | |
326 | } | |
327 | ||
328 | /************************************************************************** | |
329 | * | |
330 | * Falcon generic buffer handling | |
331 | * These buffers are used for interrupt status and MAC stats | |
332 | * | |
333 | **************************************************************************/ | |
334 | ||
335 | static int falcon_alloc_buffer(struct efx_nic *efx, | |
336 | struct efx_buffer *buffer, unsigned int len) | |
337 | { | |
338 | buffer->addr = pci_alloc_consistent(efx->pci_dev, len, | |
339 | &buffer->dma_addr); | |
340 | if (!buffer->addr) | |
341 | return -ENOMEM; | |
342 | buffer->len = len; | |
343 | memset(buffer->addr, 0, len); | |
344 | return 0; | |
345 | } | |
346 | ||
347 | static void falcon_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer) | |
348 | { | |
349 | if (buffer->addr) { | |
350 | pci_free_consistent(efx->pci_dev, buffer->len, | |
351 | buffer->addr, buffer->dma_addr); | |
352 | buffer->addr = NULL; | |
353 | } | |
354 | } | |
355 | ||
356 | /************************************************************************** | |
357 | * | |
358 | * Falcon TX path | |
359 | * | |
360 | **************************************************************************/ | |
361 | ||
362 | /* Returns a pointer to the specified transmit descriptor in the TX | |
363 | * descriptor queue belonging to the specified channel. | |
364 | */ | |
365 | static inline efx_qword_t *falcon_tx_desc(struct efx_tx_queue *tx_queue, | |
366 | unsigned int index) | |
367 | { | |
368 | return (((efx_qword_t *) (tx_queue->txd.addr)) + index); | |
369 | } | |
370 | ||
371 | /* This writes to the TX_DESC_WPTR; write pointer for TX descriptor ring */ | |
372 | static inline void falcon_notify_tx_desc(struct efx_tx_queue *tx_queue) | |
373 | { | |
374 | unsigned write_ptr; | |
375 | efx_dword_t reg; | |
376 | ||
3ffeabdd | 377 | write_ptr = tx_queue->write_count & EFX_TXQ_MASK; |
3e6c4538 | 378 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_TX_DESC_WPTR_DWORD, write_ptr); |
12d00cad BH |
379 | efx_writed_page(tx_queue->efx, ®, |
380 | FR_AZ_TX_DESC_UPD_DWORD_P0, tx_queue->queue); | |
8ceee660 BH |
381 | } |
382 | ||
383 | ||
384 | /* For each entry inserted into the software descriptor ring, create a | |
385 | * descriptor in the hardware TX descriptor ring (in host memory), and | |
386 | * write a doorbell. | |
387 | */ | |
388 | void falcon_push_buffers(struct efx_tx_queue *tx_queue) | |
389 | { | |
390 | ||
391 | struct efx_tx_buffer *buffer; | |
392 | efx_qword_t *txd; | |
393 | unsigned write_ptr; | |
394 | ||
395 | BUG_ON(tx_queue->write_count == tx_queue->insert_count); | |
396 | ||
397 | do { | |
3ffeabdd | 398 | write_ptr = tx_queue->write_count & EFX_TXQ_MASK; |
8ceee660 BH |
399 | buffer = &tx_queue->buffer[write_ptr]; |
400 | txd = falcon_tx_desc(tx_queue, write_ptr); | |
401 | ++tx_queue->write_count; | |
402 | ||
403 | /* Create TX descriptor ring entry */ | |
3e6c4538 BH |
404 | EFX_POPULATE_QWORD_4(*txd, |
405 | FSF_AZ_TX_KER_CONT, buffer->continuation, | |
406 | FSF_AZ_TX_KER_BYTE_COUNT, buffer->len, | |
407 | FSF_AZ_TX_KER_BUF_REGION, 0, | |
408 | FSF_AZ_TX_KER_BUF_ADDR, buffer->dma_addr); | |
8ceee660 BH |
409 | } while (tx_queue->write_count != tx_queue->insert_count); |
410 | ||
411 | wmb(); /* Ensure descriptors are written before they are fetched */ | |
412 | falcon_notify_tx_desc(tx_queue); | |
413 | } | |
414 | ||
415 | /* Allocate hardware resources for a TX queue */ | |
416 | int falcon_probe_tx(struct efx_tx_queue *tx_queue) | |
417 | { | |
418 | struct efx_nic *efx = tx_queue->efx; | |
3ffeabdd BH |
419 | BUILD_BUG_ON(EFX_TXQ_SIZE < 512 || EFX_TXQ_SIZE > 4096 || |
420 | EFX_TXQ_SIZE & EFX_TXQ_MASK); | |
8ceee660 | 421 | return falcon_alloc_special_buffer(efx, &tx_queue->txd, |
3ffeabdd | 422 | EFX_TXQ_SIZE * sizeof(efx_qword_t)); |
8ceee660 BH |
423 | } |
424 | ||
bc3c90a2 | 425 | void falcon_init_tx(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
426 | { |
427 | efx_oword_t tx_desc_ptr; | |
428 | struct efx_nic *efx = tx_queue->efx; | |
8ceee660 | 429 | |
127e6e10 | 430 | tx_queue->flushed = FLUSH_NONE; |
6bc5d3a9 | 431 | |
8ceee660 | 432 | /* Pin TX descriptor ring */ |
bc3c90a2 | 433 | falcon_init_special_buffer(efx, &tx_queue->txd); |
8ceee660 BH |
434 | |
435 | /* Push TX descriptor ring to card */ | |
436 | EFX_POPULATE_OWORD_10(tx_desc_ptr, | |
3e6c4538 BH |
437 | FRF_AZ_TX_DESCQ_EN, 1, |
438 | FRF_AZ_TX_ISCSI_DDIG_EN, 0, | |
439 | FRF_AZ_TX_ISCSI_HDIG_EN, 0, | |
440 | FRF_AZ_TX_DESCQ_BUF_BASE_ID, tx_queue->txd.index, | |
441 | FRF_AZ_TX_DESCQ_EVQ_ID, | |
442 | tx_queue->channel->channel, | |
443 | FRF_AZ_TX_DESCQ_OWNER_ID, 0, | |
444 | FRF_AZ_TX_DESCQ_LABEL, tx_queue->queue, | |
3ffeabdd BH |
445 | FRF_AZ_TX_DESCQ_SIZE, |
446 | __ffs(tx_queue->txd.entries), | |
3e6c4538 BH |
447 | FRF_AZ_TX_DESCQ_TYPE, 0, |
448 | FRF_BZ_TX_NON_IP_DROP_DIS, 1); | |
8ceee660 | 449 | |
55668611 | 450 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
60ac1065 | 451 | int csum = tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM; |
3e6c4538 BH |
452 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_IP_CHKSM_DIS, !csum); |
453 | EFX_SET_OWORD_FIELD(tx_desc_ptr, FRF_BZ_TX_TCP_CHKSM_DIS, | |
454 | !csum); | |
8ceee660 BH |
455 | } |
456 | ||
12d00cad BH |
457 | efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, |
458 | tx_queue->queue); | |
8ceee660 | 459 | |
55668611 | 460 | if (falcon_rev(efx) < FALCON_REV_B0) { |
8ceee660 BH |
461 | efx_oword_t reg; |
462 | ||
60ac1065 BH |
463 | /* Only 128 bits in this register */ |
464 | BUILD_BUG_ON(EFX_TX_QUEUE_COUNT >= 128); | |
8ceee660 | 465 | |
12d00cad | 466 | efx_reado(efx, ®, FR_AA_TX_CHKSM_CFG); |
60ac1065 | 467 | if (tx_queue->queue == EFX_TX_QUEUE_OFFLOAD_CSUM) |
8ceee660 BH |
468 | clear_bit_le(tx_queue->queue, (void *)®); |
469 | else | |
470 | set_bit_le(tx_queue->queue, (void *)®); | |
12d00cad | 471 | efx_writeo(efx, ®, FR_AA_TX_CHKSM_CFG); |
8ceee660 | 472 | } |
8ceee660 BH |
473 | } |
474 | ||
6bc5d3a9 | 475 | static void falcon_flush_tx_queue(struct efx_tx_queue *tx_queue) |
8ceee660 BH |
476 | { |
477 | struct efx_nic *efx = tx_queue->efx; | |
8ceee660 | 478 | efx_oword_t tx_flush_descq; |
8ceee660 | 479 | |
127e6e10 BH |
480 | tx_queue->flushed = FLUSH_PENDING; |
481 | ||
8ceee660 BH |
482 | /* Post a flush command */ |
483 | EFX_POPULATE_OWORD_2(tx_flush_descq, | |
3e6c4538 BH |
484 | FRF_AZ_TX_FLUSH_DESCQ_CMD, 1, |
485 | FRF_AZ_TX_FLUSH_DESCQ, tx_queue->queue); | |
12d00cad | 486 | efx_writeo(efx, &tx_flush_descq, FR_AZ_TX_FLUSH_DESCQ); |
8ceee660 BH |
487 | } |
488 | ||
489 | void falcon_fini_tx(struct efx_tx_queue *tx_queue) | |
490 | { | |
491 | struct efx_nic *efx = tx_queue->efx; | |
492 | efx_oword_t tx_desc_ptr; | |
493 | ||
6bc5d3a9 | 494 | /* The queue should have been flushed */ |
127e6e10 | 495 | WARN_ON(tx_queue->flushed != FLUSH_DONE); |
8ceee660 BH |
496 | |
497 | /* Remove TX descriptor ring from card */ | |
498 | EFX_ZERO_OWORD(tx_desc_ptr); | |
12d00cad BH |
499 | efx_writeo_table(efx, &tx_desc_ptr, efx->type->txd_ptr_tbl_base, |
500 | tx_queue->queue); | |
8ceee660 BH |
501 | |
502 | /* Unpin TX descriptor ring */ | |
503 | falcon_fini_special_buffer(efx, &tx_queue->txd); | |
504 | } | |
505 | ||
506 | /* Free buffers backing TX queue */ | |
507 | void falcon_remove_tx(struct efx_tx_queue *tx_queue) | |
508 | { | |
509 | falcon_free_special_buffer(tx_queue->efx, &tx_queue->txd); | |
510 | } | |
511 | ||
512 | /************************************************************************** | |
513 | * | |
514 | * Falcon RX path | |
515 | * | |
516 | **************************************************************************/ | |
517 | ||
518 | /* Returns a pointer to the specified descriptor in the RX descriptor queue */ | |
519 | static inline efx_qword_t *falcon_rx_desc(struct efx_rx_queue *rx_queue, | |
520 | unsigned int index) | |
521 | { | |
522 | return (((efx_qword_t *) (rx_queue->rxd.addr)) + index); | |
523 | } | |
524 | ||
525 | /* This creates an entry in the RX descriptor queue */ | |
526 | static inline void falcon_build_rx_desc(struct efx_rx_queue *rx_queue, | |
527 | unsigned index) | |
528 | { | |
529 | struct efx_rx_buffer *rx_buf; | |
530 | efx_qword_t *rxd; | |
531 | ||
532 | rxd = falcon_rx_desc(rx_queue, index); | |
533 | rx_buf = efx_rx_buffer(rx_queue, index); | |
534 | EFX_POPULATE_QWORD_3(*rxd, | |
3e6c4538 | 535 | FSF_AZ_RX_KER_BUF_SIZE, |
8ceee660 BH |
536 | rx_buf->len - |
537 | rx_queue->efx->type->rx_buffer_padding, | |
3e6c4538 BH |
538 | FSF_AZ_RX_KER_BUF_REGION, 0, |
539 | FSF_AZ_RX_KER_BUF_ADDR, rx_buf->dma_addr); | |
8ceee660 BH |
540 | } |
541 | ||
542 | /* This writes to the RX_DESC_WPTR register for the specified receive | |
543 | * descriptor ring. | |
544 | */ | |
545 | void falcon_notify_rx_desc(struct efx_rx_queue *rx_queue) | |
546 | { | |
547 | efx_dword_t reg; | |
548 | unsigned write_ptr; | |
549 | ||
550 | while (rx_queue->notified_count != rx_queue->added_count) { | |
551 | falcon_build_rx_desc(rx_queue, | |
552 | rx_queue->notified_count & | |
3ffeabdd | 553 | EFX_RXQ_MASK); |
8ceee660 BH |
554 | ++rx_queue->notified_count; |
555 | } | |
556 | ||
557 | wmb(); | |
3ffeabdd | 558 | write_ptr = rx_queue->added_count & EFX_RXQ_MASK; |
3e6c4538 | 559 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_RX_DESC_WPTR_DWORD, write_ptr); |
12d00cad BH |
560 | efx_writed_page(rx_queue->efx, ®, |
561 | FR_AZ_RX_DESC_UPD_DWORD_P0, rx_queue->queue); | |
8ceee660 BH |
562 | } |
563 | ||
564 | int falcon_probe_rx(struct efx_rx_queue *rx_queue) | |
565 | { | |
566 | struct efx_nic *efx = rx_queue->efx; | |
3ffeabdd BH |
567 | BUILD_BUG_ON(EFX_RXQ_SIZE < 512 || EFX_RXQ_SIZE > 4096 || |
568 | EFX_RXQ_SIZE & EFX_RXQ_MASK); | |
8ceee660 | 569 | return falcon_alloc_special_buffer(efx, &rx_queue->rxd, |
3ffeabdd | 570 | EFX_RXQ_SIZE * sizeof(efx_qword_t)); |
8ceee660 BH |
571 | } |
572 | ||
bc3c90a2 | 573 | void falcon_init_rx(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
574 | { |
575 | efx_oword_t rx_desc_ptr; | |
576 | struct efx_nic *efx = rx_queue->efx; | |
dc8cfa55 BH |
577 | bool is_b0 = falcon_rev(efx) >= FALCON_REV_B0; |
578 | bool iscsi_digest_en = is_b0; | |
8ceee660 BH |
579 | |
580 | EFX_LOG(efx, "RX queue %d ring in special buffers %d-%d\n", | |
581 | rx_queue->queue, rx_queue->rxd.index, | |
582 | rx_queue->rxd.index + rx_queue->rxd.entries - 1); | |
583 | ||
127e6e10 | 584 | rx_queue->flushed = FLUSH_NONE; |
6bc5d3a9 | 585 | |
8ceee660 | 586 | /* Pin RX descriptor ring */ |
bc3c90a2 | 587 | falcon_init_special_buffer(efx, &rx_queue->rxd); |
8ceee660 BH |
588 | |
589 | /* Push RX descriptor ring to card */ | |
590 | EFX_POPULATE_OWORD_10(rx_desc_ptr, | |
3e6c4538 BH |
591 | FRF_AZ_RX_ISCSI_DDIG_EN, iscsi_digest_en, |
592 | FRF_AZ_RX_ISCSI_HDIG_EN, iscsi_digest_en, | |
593 | FRF_AZ_RX_DESCQ_BUF_BASE_ID, rx_queue->rxd.index, | |
594 | FRF_AZ_RX_DESCQ_EVQ_ID, | |
595 | rx_queue->channel->channel, | |
596 | FRF_AZ_RX_DESCQ_OWNER_ID, 0, | |
597 | FRF_AZ_RX_DESCQ_LABEL, rx_queue->queue, | |
3ffeabdd BH |
598 | FRF_AZ_RX_DESCQ_SIZE, |
599 | __ffs(rx_queue->rxd.entries), | |
3e6c4538 | 600 | FRF_AZ_RX_DESCQ_TYPE, 0 /* kernel queue */ , |
8ceee660 | 601 | /* For >=B0 this is scatter so disable */ |
3e6c4538 BH |
602 | FRF_AZ_RX_DESCQ_JUMBO, !is_b0, |
603 | FRF_AZ_RX_DESCQ_EN, 1); | |
12d00cad BH |
604 | efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, |
605 | rx_queue->queue); | |
8ceee660 BH |
606 | } |
607 | ||
6bc5d3a9 | 608 | static void falcon_flush_rx_queue(struct efx_rx_queue *rx_queue) |
8ceee660 BH |
609 | { |
610 | struct efx_nic *efx = rx_queue->efx; | |
8ceee660 BH |
611 | efx_oword_t rx_flush_descq; |
612 | ||
127e6e10 BH |
613 | rx_queue->flushed = FLUSH_PENDING; |
614 | ||
8ceee660 BH |
615 | /* Post a flush command */ |
616 | EFX_POPULATE_OWORD_2(rx_flush_descq, | |
3e6c4538 BH |
617 | FRF_AZ_RX_FLUSH_DESCQ_CMD, 1, |
618 | FRF_AZ_RX_FLUSH_DESCQ, rx_queue->queue); | |
12d00cad | 619 | efx_writeo(efx, &rx_flush_descq, FR_AZ_RX_FLUSH_DESCQ); |
8ceee660 BH |
620 | } |
621 | ||
622 | void falcon_fini_rx(struct efx_rx_queue *rx_queue) | |
623 | { | |
624 | efx_oword_t rx_desc_ptr; | |
625 | struct efx_nic *efx = rx_queue->efx; | |
8ceee660 | 626 | |
6bc5d3a9 | 627 | /* The queue should already have been flushed */ |
127e6e10 | 628 | WARN_ON(rx_queue->flushed != FLUSH_DONE); |
8ceee660 BH |
629 | |
630 | /* Remove RX descriptor ring from card */ | |
631 | EFX_ZERO_OWORD(rx_desc_ptr); | |
12d00cad BH |
632 | efx_writeo_table(efx, &rx_desc_ptr, efx->type->rxd_ptr_tbl_base, |
633 | rx_queue->queue); | |
8ceee660 BH |
634 | |
635 | /* Unpin RX descriptor ring */ | |
636 | falcon_fini_special_buffer(efx, &rx_queue->rxd); | |
637 | } | |
638 | ||
639 | /* Free buffers backing RX queue */ | |
640 | void falcon_remove_rx(struct efx_rx_queue *rx_queue) | |
641 | { | |
642 | falcon_free_special_buffer(rx_queue->efx, &rx_queue->rxd); | |
643 | } | |
644 | ||
645 | /************************************************************************** | |
646 | * | |
647 | * Falcon event queue processing | |
648 | * Event queues are processed by per-channel tasklets. | |
649 | * | |
650 | **************************************************************************/ | |
651 | ||
652 | /* Update a channel's event queue's read pointer (RPTR) register | |
653 | * | |
654 | * This writes the EVQ_RPTR_REG register for the specified channel's | |
655 | * event queue. | |
656 | * | |
657 | * Note that EVQ_RPTR_REG contains the index of the "last read" event, | |
658 | * whereas channel->eventq_read_ptr contains the index of the "next to | |
659 | * read" event. | |
660 | */ | |
661 | void falcon_eventq_read_ack(struct efx_channel *channel) | |
662 | { | |
663 | efx_dword_t reg; | |
664 | struct efx_nic *efx = channel->efx; | |
665 | ||
3e6c4538 | 666 | EFX_POPULATE_DWORD_1(reg, FRF_AZ_EVQ_RPTR, channel->eventq_read_ptr); |
12d00cad | 667 | efx_writed_table(efx, ®, efx->type->evq_rptr_tbl_base, |
d3074025 | 668 | channel->channel); |
8ceee660 BH |
669 | } |
670 | ||
671 | /* Use HW to insert a SW defined event */ | |
672 | void falcon_generate_event(struct efx_channel *channel, efx_qword_t *event) | |
673 | { | |
674 | efx_oword_t drv_ev_reg; | |
675 | ||
3e6c4538 BH |
676 | BUILD_BUG_ON(FRF_AZ_DRV_EV_DATA_LBN != 0 || |
677 | FRF_AZ_DRV_EV_DATA_WIDTH != 64); | |
678 | drv_ev_reg.u32[0] = event->u32[0]; | |
679 | drv_ev_reg.u32[1] = event->u32[1]; | |
680 | drv_ev_reg.u32[2] = 0; | |
681 | drv_ev_reg.u32[3] = 0; | |
682 | EFX_SET_OWORD_FIELD(drv_ev_reg, FRF_AZ_DRV_EV_QID, channel->channel); | |
12d00cad | 683 | efx_writeo(channel->efx, &drv_ev_reg, FR_AZ_DRV_EV); |
8ceee660 BH |
684 | } |
685 | ||
686 | /* Handle a transmit completion event | |
687 | * | |
688 | * Falcon batches TX completion events; the message we receive is of | |
689 | * the form "complete all TX events up to this index". | |
690 | */ | |
4d566063 BH |
691 | static void falcon_handle_tx_event(struct efx_channel *channel, |
692 | efx_qword_t *event) | |
8ceee660 BH |
693 | { |
694 | unsigned int tx_ev_desc_ptr; | |
695 | unsigned int tx_ev_q_label; | |
696 | struct efx_tx_queue *tx_queue; | |
697 | struct efx_nic *efx = channel->efx; | |
698 | ||
3e6c4538 | 699 | if (likely(EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_COMP))) { |
8ceee660 | 700 | /* Transmit completion */ |
3e6c4538 BH |
701 | tx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_DESC_PTR); |
702 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); | |
8ceee660 | 703 | tx_queue = &efx->tx_queue[tx_ev_q_label]; |
6fb70fd1 BH |
704 | channel->irq_mod_score += |
705 | (tx_ev_desc_ptr - tx_queue->read_count) & | |
3ffeabdd | 706 | EFX_TXQ_MASK; |
8ceee660 | 707 | efx_xmit_done(tx_queue, tx_ev_desc_ptr); |
3e6c4538 | 708 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_WQ_FF_FULL)) { |
8ceee660 | 709 | /* Rewrite the FIFO write pointer */ |
3e6c4538 | 710 | tx_ev_q_label = EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_Q_LABEL); |
8ceee660 BH |
711 | tx_queue = &efx->tx_queue[tx_ev_q_label]; |
712 | ||
55668611 | 713 | if (efx_dev_registered(efx)) |
8ceee660 BH |
714 | netif_tx_lock(efx->net_dev); |
715 | falcon_notify_tx_desc(tx_queue); | |
55668611 | 716 | if (efx_dev_registered(efx)) |
8ceee660 | 717 | netif_tx_unlock(efx->net_dev); |
3e6c4538 | 718 | } else if (EFX_QWORD_FIELD(*event, FSF_AZ_TX_EV_PKT_ERR) && |
8ceee660 BH |
719 | EFX_WORKAROUND_10727(efx)) { |
720 | efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); | |
721 | } else { | |
722 | EFX_ERR(efx, "channel %d unexpected TX event " | |
723 | EFX_QWORD_FMT"\n", channel->channel, | |
724 | EFX_QWORD_VAL(*event)); | |
725 | } | |
726 | } | |
727 | ||
8ceee660 BH |
728 | /* Detect errors included in the rx_evt_pkt_ok bit. */ |
729 | static void falcon_handle_rx_not_ok(struct efx_rx_queue *rx_queue, | |
730 | const efx_qword_t *event, | |
dc8cfa55 BH |
731 | bool *rx_ev_pkt_ok, |
732 | bool *discard) | |
8ceee660 BH |
733 | { |
734 | struct efx_nic *efx = rx_queue->efx; | |
dc8cfa55 BH |
735 | bool rx_ev_buf_owner_id_err, rx_ev_ip_hdr_chksum_err; |
736 | bool rx_ev_tcp_udp_chksum_err, rx_ev_eth_crc_err; | |
737 | bool rx_ev_frm_trunc, rx_ev_drib_nib, rx_ev_tobe_disc; | |
738 | bool rx_ev_other_err, rx_ev_pause_frm; | |
739 | bool rx_ev_ip_frag_err, rx_ev_hdr_type, rx_ev_mcast_pkt; | |
740 | unsigned rx_ev_pkt_type; | |
8ceee660 | 741 | |
3e6c4538 BH |
742 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); |
743 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); | |
744 | rx_ev_tobe_disc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_TOBE_DISC); | |
745 | rx_ev_pkt_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_TYPE); | |
8ceee660 | 746 | rx_ev_buf_owner_id_err = EFX_QWORD_FIELD(*event, |
3e6c4538 BH |
747 | FSF_AZ_RX_EV_BUF_OWNER_ID_ERR); |
748 | rx_ev_ip_frag_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_IP_FRAG_ERR); | |
8ceee660 | 749 | rx_ev_ip_hdr_chksum_err = EFX_QWORD_FIELD(*event, |
3e6c4538 | 750 | FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR); |
8ceee660 | 751 | rx_ev_tcp_udp_chksum_err = EFX_QWORD_FIELD(*event, |
3e6c4538 BH |
752 | FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR); |
753 | rx_ev_eth_crc_err = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_ETH_CRC_ERR); | |
754 | rx_ev_frm_trunc = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_FRM_TRUNC); | |
55668611 | 755 | rx_ev_drib_nib = ((falcon_rev(efx) >= FALCON_REV_B0) ? |
3e6c4538 BH |
756 | 0 : EFX_QWORD_FIELD(*event, FSF_AA_RX_EV_DRIB_NIB)); |
757 | rx_ev_pause_frm = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PAUSE_FRM_ERR); | |
8ceee660 BH |
758 | |
759 | /* Every error apart from tobe_disc and pause_frm */ | |
760 | rx_ev_other_err = (rx_ev_drib_nib | rx_ev_tcp_udp_chksum_err | | |
761 | rx_ev_buf_owner_id_err | rx_ev_eth_crc_err | | |
762 | rx_ev_frm_trunc | rx_ev_ip_hdr_chksum_err); | |
763 | ||
50050877 BH |
764 | /* Count errors that are not in MAC stats. Ignore expected |
765 | * checksum errors during self-test. */ | |
8ceee660 BH |
766 | if (rx_ev_frm_trunc) |
767 | ++rx_queue->channel->n_rx_frm_trunc; | |
768 | else if (rx_ev_tobe_disc) | |
769 | ++rx_queue->channel->n_rx_tobe_disc; | |
50050877 BH |
770 | else if (!efx->loopback_selftest) { |
771 | if (rx_ev_ip_hdr_chksum_err) | |
772 | ++rx_queue->channel->n_rx_ip_hdr_chksum_err; | |
773 | else if (rx_ev_tcp_udp_chksum_err) | |
774 | ++rx_queue->channel->n_rx_tcp_udp_chksum_err; | |
775 | } | |
8ceee660 BH |
776 | if (rx_ev_ip_frag_err) |
777 | ++rx_queue->channel->n_rx_ip_frag_err; | |
778 | ||
779 | /* The frame must be discarded if any of these are true. */ | |
780 | *discard = (rx_ev_eth_crc_err | rx_ev_frm_trunc | rx_ev_drib_nib | | |
781 | rx_ev_tobe_disc | rx_ev_pause_frm); | |
782 | ||
783 | /* TOBE_DISC is expected on unicast mismatches; don't print out an | |
784 | * error message. FRM_TRUNC indicates RXDP dropped the packet due | |
785 | * to a FIFO overflow. | |
786 | */ | |
787 | #ifdef EFX_ENABLE_DEBUG | |
788 | if (rx_ev_other_err) { | |
789 | EFX_INFO_RL(efx, " RX queue %d unexpected RX event " | |
5b39fe30 | 790 | EFX_QWORD_FMT "%s%s%s%s%s%s%s%s\n", |
8ceee660 BH |
791 | rx_queue->queue, EFX_QWORD_VAL(*event), |
792 | rx_ev_buf_owner_id_err ? " [OWNER_ID_ERR]" : "", | |
793 | rx_ev_ip_hdr_chksum_err ? | |
794 | " [IP_HDR_CHKSUM_ERR]" : "", | |
795 | rx_ev_tcp_udp_chksum_err ? | |
796 | " [TCP_UDP_CHKSUM_ERR]" : "", | |
797 | rx_ev_eth_crc_err ? " [ETH_CRC_ERR]" : "", | |
798 | rx_ev_frm_trunc ? " [FRM_TRUNC]" : "", | |
799 | rx_ev_drib_nib ? " [DRIB_NIB]" : "", | |
800 | rx_ev_tobe_disc ? " [TOBE_DISC]" : "", | |
5b39fe30 | 801 | rx_ev_pause_frm ? " [PAUSE]" : ""); |
8ceee660 BH |
802 | } |
803 | #endif | |
8ceee660 BH |
804 | } |
805 | ||
806 | /* Handle receive events that are not in-order. */ | |
807 | static void falcon_handle_rx_bad_index(struct efx_rx_queue *rx_queue, | |
808 | unsigned index) | |
809 | { | |
810 | struct efx_nic *efx = rx_queue->efx; | |
811 | unsigned expected, dropped; | |
812 | ||
3ffeabdd BH |
813 | expected = rx_queue->removed_count & EFX_RXQ_MASK; |
814 | dropped = (index - expected) & EFX_RXQ_MASK; | |
8ceee660 BH |
815 | EFX_INFO(efx, "dropped %d events (index=%d expected=%d)\n", |
816 | dropped, index, expected); | |
817 | ||
818 | efx_schedule_reset(efx, EFX_WORKAROUND_5676(efx) ? | |
819 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
820 | } | |
821 | ||
822 | /* Handle a packet received event | |
823 | * | |
824 | * Falcon silicon gives a "discard" flag if it's a unicast packet with the | |
825 | * wrong destination address | |
826 | * Also "is multicast" and "matches multicast filter" flags can be used to | |
827 | * discard non-matching multicast packets. | |
828 | */ | |
42cbe2d7 BH |
829 | static void falcon_handle_rx_event(struct efx_channel *channel, |
830 | const efx_qword_t *event) | |
8ceee660 | 831 | { |
42cbe2d7 | 832 | unsigned int rx_ev_desc_ptr, rx_ev_byte_cnt; |
dc8cfa55 | 833 | unsigned int rx_ev_hdr_type, rx_ev_mcast_pkt; |
8ceee660 | 834 | unsigned expected_ptr; |
dc8cfa55 | 835 | bool rx_ev_pkt_ok, discard = false, checksummed; |
8ceee660 BH |
836 | struct efx_rx_queue *rx_queue; |
837 | struct efx_nic *efx = channel->efx; | |
838 | ||
839 | /* Basic packet information */ | |
3e6c4538 BH |
840 | rx_ev_byte_cnt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_BYTE_CNT); |
841 | rx_ev_pkt_ok = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_PKT_OK); | |
842 | rx_ev_hdr_type = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_HDR_TYPE); | |
843 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_JUMBO_CONT)); | |
844 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_SOP) != 1); | |
845 | WARN_ON(EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_Q_LABEL) != | |
846 | channel->channel); | |
8ceee660 | 847 | |
42cbe2d7 | 848 | rx_queue = &efx->rx_queue[channel->channel]; |
8ceee660 | 849 | |
3e6c4538 | 850 | rx_ev_desc_ptr = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_DESC_PTR); |
3ffeabdd | 851 | expected_ptr = rx_queue->removed_count & EFX_RXQ_MASK; |
42cbe2d7 | 852 | if (unlikely(rx_ev_desc_ptr != expected_ptr)) |
8ceee660 | 853 | falcon_handle_rx_bad_index(rx_queue, rx_ev_desc_ptr); |
8ceee660 BH |
854 | |
855 | if (likely(rx_ev_pkt_ok)) { | |
856 | /* If packet is marked as OK and packet type is TCP/IPv4 or | |
857 | * UDP/IPv4, then we can rely on the hardware checksum. | |
858 | */ | |
3e6c4538 | 859 | checksummed = |
9c1bbbaf BH |
860 | efx->rx_checksum_enabled && |
861 | (rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP || | |
862 | rx_ev_hdr_type == FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP); | |
8ceee660 BH |
863 | } else { |
864 | falcon_handle_rx_not_ok(rx_queue, event, &rx_ev_pkt_ok, | |
5b39fe30 | 865 | &discard); |
dc8cfa55 | 866 | checksummed = false; |
8ceee660 BH |
867 | } |
868 | ||
869 | /* Detect multicast packets that didn't match the filter */ | |
3e6c4538 | 870 | rx_ev_mcast_pkt = EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_PKT); |
8ceee660 BH |
871 | if (rx_ev_mcast_pkt) { |
872 | unsigned int rx_ev_mcast_hash_match = | |
3e6c4538 | 873 | EFX_QWORD_FIELD(*event, FSF_AZ_RX_EV_MCAST_HASH_MATCH); |
8ceee660 BH |
874 | |
875 | if (unlikely(!rx_ev_mcast_hash_match)) | |
dc8cfa55 | 876 | discard = true; |
8ceee660 BH |
877 | } |
878 | ||
6fb70fd1 BH |
879 | channel->irq_mod_score += 2; |
880 | ||
8ceee660 BH |
881 | /* Handle received packet */ |
882 | efx_rx_packet(rx_queue, rx_ev_desc_ptr, rx_ev_byte_cnt, | |
883 | checksummed, discard); | |
8ceee660 BH |
884 | } |
885 | ||
886 | /* Global events are basically PHY events */ | |
887 | static void falcon_handle_global_event(struct efx_channel *channel, | |
888 | efx_qword_t *event) | |
889 | { | |
890 | struct efx_nic *efx = channel->efx; | |
766ca0fa | 891 | bool handled = false; |
8ceee660 | 892 | |
3e6c4538 BH |
893 | if (EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_G_PHY0_INTR) || |
894 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XG_PHY0_INTR) || | |
895 | EFX_QWORD_FIELD(*event, FSF_AB_GLB_EV_XFP_PHY0_INTR)) { | |
766ca0fa BH |
896 | efx->phy_op->clear_interrupt(efx); |
897 | queue_work(efx->workqueue, &efx->phy_work); | |
898 | handled = true; | |
899 | } | |
8ceee660 | 900 | |
55668611 | 901 | if ((falcon_rev(efx) >= FALCON_REV_B0) && |
3e6c4538 | 902 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_XG_MGT_INTR)) { |
9007b9fa | 903 | efx->xmac_poll_required = true; |
dc8cfa55 | 904 | handled = true; |
8ceee660 BH |
905 | } |
906 | ||
56241ceb | 907 | if (falcon_rev(efx) <= FALCON_REV_A1 ? |
3e6c4538 BH |
908 | EFX_QWORD_FIELD(*event, FSF_AA_GLB_EV_RX_RECOVERY) : |
909 | EFX_QWORD_FIELD(*event, FSF_BB_GLB_EV_RX_RECOVERY)) { | |
8ceee660 BH |
910 | EFX_ERR(efx, "channel %d seen global RX_RESET " |
911 | "event. Resetting.\n", channel->channel); | |
912 | ||
913 | atomic_inc(&efx->rx_reset); | |
914 | efx_schedule_reset(efx, EFX_WORKAROUND_6555(efx) ? | |
915 | RESET_TYPE_RX_RECOVERY : RESET_TYPE_DISABLE); | |
dc8cfa55 | 916 | handled = true; |
8ceee660 BH |
917 | } |
918 | ||
919 | if (!handled) | |
920 | EFX_ERR(efx, "channel %d unknown global event " | |
921 | EFX_QWORD_FMT "\n", channel->channel, | |
922 | EFX_QWORD_VAL(*event)); | |
923 | } | |
924 | ||
925 | static void falcon_handle_driver_event(struct efx_channel *channel, | |
926 | efx_qword_t *event) | |
927 | { | |
928 | struct efx_nic *efx = channel->efx; | |
929 | unsigned int ev_sub_code; | |
930 | unsigned int ev_sub_data; | |
931 | ||
3e6c4538 BH |
932 | ev_sub_code = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBCODE); |
933 | ev_sub_data = EFX_QWORD_FIELD(*event, FSF_AZ_DRIVER_EV_SUBDATA); | |
8ceee660 BH |
934 | |
935 | switch (ev_sub_code) { | |
3e6c4538 | 936 | case FSE_AZ_TX_DESCQ_FLS_DONE_EV: |
8ceee660 BH |
937 | EFX_TRACE(efx, "channel %d TXQ %d flushed\n", |
938 | channel->channel, ev_sub_data); | |
939 | break; | |
3e6c4538 | 940 | case FSE_AZ_RX_DESCQ_FLS_DONE_EV: |
8ceee660 BH |
941 | EFX_TRACE(efx, "channel %d RXQ %d flushed\n", |
942 | channel->channel, ev_sub_data); | |
943 | break; | |
3e6c4538 | 944 | case FSE_AZ_EVQ_INIT_DONE_EV: |
8ceee660 BH |
945 | EFX_LOG(efx, "channel %d EVQ %d initialised\n", |
946 | channel->channel, ev_sub_data); | |
947 | break; | |
3e6c4538 | 948 | case FSE_AZ_SRM_UPD_DONE_EV: |
8ceee660 BH |
949 | EFX_TRACE(efx, "channel %d SRAM update done\n", |
950 | channel->channel); | |
951 | break; | |
3e6c4538 | 952 | case FSE_AZ_WAKE_UP_EV: |
8ceee660 BH |
953 | EFX_TRACE(efx, "channel %d RXQ %d wakeup event\n", |
954 | channel->channel, ev_sub_data); | |
955 | break; | |
3e6c4538 | 956 | case FSE_AZ_TIMER_EV: |
8ceee660 BH |
957 | EFX_TRACE(efx, "channel %d RX queue %d timer expired\n", |
958 | channel->channel, ev_sub_data); | |
959 | break; | |
3e6c4538 | 960 | case FSE_AA_RX_RECOVER_EV: |
8ceee660 BH |
961 | EFX_ERR(efx, "channel %d seen DRIVER RX_RESET event. " |
962 | "Resetting.\n", channel->channel); | |
05e3ec04 | 963 | atomic_inc(&efx->rx_reset); |
8ceee660 BH |
964 | efx_schedule_reset(efx, |
965 | EFX_WORKAROUND_6555(efx) ? | |
966 | RESET_TYPE_RX_RECOVERY : | |
967 | RESET_TYPE_DISABLE); | |
968 | break; | |
3e6c4538 | 969 | case FSE_BZ_RX_DSC_ERROR_EV: |
8ceee660 BH |
970 | EFX_ERR(efx, "RX DMA Q %d reports descriptor fetch error." |
971 | " RX Q %d is disabled.\n", ev_sub_data, ev_sub_data); | |
972 | efx_schedule_reset(efx, RESET_TYPE_RX_DESC_FETCH); | |
973 | break; | |
3e6c4538 | 974 | case FSE_BZ_TX_DSC_ERROR_EV: |
8ceee660 BH |
975 | EFX_ERR(efx, "TX DMA Q %d reports descriptor fetch error." |
976 | " TX Q %d is disabled.\n", ev_sub_data, ev_sub_data); | |
977 | efx_schedule_reset(efx, RESET_TYPE_TX_DESC_FETCH); | |
978 | break; | |
979 | default: | |
980 | EFX_TRACE(efx, "channel %d unknown driver event code %d " | |
981 | "data %04x\n", channel->channel, ev_sub_code, | |
982 | ev_sub_data); | |
983 | break; | |
984 | } | |
985 | } | |
986 | ||
42cbe2d7 | 987 | int falcon_process_eventq(struct efx_channel *channel, int rx_quota) |
8ceee660 BH |
988 | { |
989 | unsigned int read_ptr; | |
990 | efx_qword_t event, *p_event; | |
991 | int ev_code; | |
42cbe2d7 | 992 | int rx_packets = 0; |
8ceee660 BH |
993 | |
994 | read_ptr = channel->eventq_read_ptr; | |
995 | ||
996 | do { | |
997 | p_event = falcon_event(channel, read_ptr); | |
998 | event = *p_event; | |
999 | ||
1000 | if (!falcon_event_present(&event)) | |
1001 | /* End of events */ | |
1002 | break; | |
1003 | ||
1004 | EFX_TRACE(channel->efx, "channel %d event is "EFX_QWORD_FMT"\n", | |
1005 | channel->channel, EFX_QWORD_VAL(event)); | |
1006 | ||
1007 | /* Clear this event by marking it all ones */ | |
1008 | EFX_SET_QWORD(*p_event); | |
1009 | ||
3e6c4538 | 1010 | ev_code = EFX_QWORD_FIELD(event, FSF_AZ_EV_CODE); |
8ceee660 BH |
1011 | |
1012 | switch (ev_code) { | |
3e6c4538 | 1013 | case FSE_AZ_EV_CODE_RX_EV: |
42cbe2d7 BH |
1014 | falcon_handle_rx_event(channel, &event); |
1015 | ++rx_packets; | |
8ceee660 | 1016 | break; |
3e6c4538 | 1017 | case FSE_AZ_EV_CODE_TX_EV: |
8ceee660 BH |
1018 | falcon_handle_tx_event(channel, &event); |
1019 | break; | |
3e6c4538 BH |
1020 | case FSE_AZ_EV_CODE_DRV_GEN_EV: |
1021 | channel->eventq_magic = EFX_QWORD_FIELD( | |
1022 | event, FSF_AZ_DRV_GEN_EV_MAGIC); | |
8ceee660 BH |
1023 | EFX_LOG(channel->efx, "channel %d received generated " |
1024 | "event "EFX_QWORD_FMT"\n", channel->channel, | |
1025 | EFX_QWORD_VAL(event)); | |
1026 | break; | |
3e6c4538 | 1027 | case FSE_AZ_EV_CODE_GLOBAL_EV: |
8ceee660 BH |
1028 | falcon_handle_global_event(channel, &event); |
1029 | break; | |
3e6c4538 | 1030 | case FSE_AZ_EV_CODE_DRIVER_EV: |
8ceee660 BH |
1031 | falcon_handle_driver_event(channel, &event); |
1032 | break; | |
1033 | default: | |
1034 | EFX_ERR(channel->efx, "channel %d unknown event type %d" | |
1035 | " (data " EFX_QWORD_FMT ")\n", channel->channel, | |
1036 | ev_code, EFX_QWORD_VAL(event)); | |
1037 | } | |
1038 | ||
1039 | /* Increment read pointer */ | |
3ffeabdd | 1040 | read_ptr = (read_ptr + 1) & EFX_EVQ_MASK; |
8ceee660 | 1041 | |
42cbe2d7 | 1042 | } while (rx_packets < rx_quota); |
8ceee660 BH |
1043 | |
1044 | channel->eventq_read_ptr = read_ptr; | |
42cbe2d7 | 1045 | return rx_packets; |
8ceee660 BH |
1046 | } |
1047 | ||
1048 | void falcon_set_int_moderation(struct efx_channel *channel) | |
1049 | { | |
1050 | efx_dword_t timer_cmd; | |
1051 | struct efx_nic *efx = channel->efx; | |
1052 | ||
1053 | /* Set timer register */ | |
1054 | if (channel->irq_moderation) { | |
8ceee660 | 1055 | EFX_POPULATE_DWORD_2(timer_cmd, |
3e6c4538 BH |
1056 | FRF_AB_TC_TIMER_MODE, |
1057 | FFE_BB_TIMER_MODE_INT_HLDOFF, | |
1058 | FRF_AB_TC_TIMER_VAL, | |
0d86ebd8 | 1059 | channel->irq_moderation - 1); |
8ceee660 BH |
1060 | } else { |
1061 | EFX_POPULATE_DWORD_2(timer_cmd, | |
3e6c4538 BH |
1062 | FRF_AB_TC_TIMER_MODE, |
1063 | FFE_BB_TIMER_MODE_DIS, | |
1064 | FRF_AB_TC_TIMER_VAL, 0); | |
8ceee660 | 1065 | } |
3e6c4538 | 1066 | BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0); |
12d00cad BH |
1067 | efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0, |
1068 | channel->channel); | |
8ceee660 BH |
1069 | |
1070 | } | |
1071 | ||
1072 | /* Allocate buffer table entries for event queue */ | |
1073 | int falcon_probe_eventq(struct efx_channel *channel) | |
1074 | { | |
1075 | struct efx_nic *efx = channel->efx; | |
3ffeabdd BH |
1076 | BUILD_BUG_ON(EFX_EVQ_SIZE < 512 || EFX_EVQ_SIZE > 32768 || |
1077 | EFX_EVQ_SIZE & EFX_EVQ_MASK); | |
1078 | return falcon_alloc_special_buffer(efx, &channel->eventq, | |
1079 | EFX_EVQ_SIZE * sizeof(efx_qword_t)); | |
8ceee660 BH |
1080 | } |
1081 | ||
bc3c90a2 | 1082 | void falcon_init_eventq(struct efx_channel *channel) |
8ceee660 BH |
1083 | { |
1084 | efx_oword_t evq_ptr; | |
1085 | struct efx_nic *efx = channel->efx; | |
8ceee660 BH |
1086 | |
1087 | EFX_LOG(efx, "channel %d event queue in special buffers %d-%d\n", | |
1088 | channel->channel, channel->eventq.index, | |
1089 | channel->eventq.index + channel->eventq.entries - 1); | |
1090 | ||
1091 | /* Pin event queue buffer */ | |
bc3c90a2 | 1092 | falcon_init_special_buffer(efx, &channel->eventq); |
8ceee660 BH |
1093 | |
1094 | /* Fill event queue with all ones (i.e. empty events) */ | |
1095 | memset(channel->eventq.addr, 0xff, channel->eventq.len); | |
1096 | ||
1097 | /* Push event queue to card */ | |
1098 | EFX_POPULATE_OWORD_3(evq_ptr, | |
3e6c4538 | 1099 | FRF_AZ_EVQ_EN, 1, |
3ffeabdd | 1100 | FRF_AZ_EVQ_SIZE, __ffs(channel->eventq.entries), |
3e6c4538 | 1101 | FRF_AZ_EVQ_BUF_BASE_ID, channel->eventq.index); |
12d00cad BH |
1102 | efx_writeo_table(efx, &evq_ptr, efx->type->evq_ptr_tbl_base, |
1103 | channel->channel); | |
8ceee660 BH |
1104 | |
1105 | falcon_set_int_moderation(channel); | |
8ceee660 BH |
1106 | } |
1107 | ||
1108 | void falcon_fini_eventq(struct efx_channel *channel) | |
1109 | { | |
1110 | efx_oword_t eventq_ptr; | |
1111 | struct efx_nic *efx = channel->efx; | |
1112 | ||
1113 | /* Remove event queue from card */ | |
1114 | EFX_ZERO_OWORD(eventq_ptr); | |
12d00cad BH |
1115 | efx_writeo_table(efx, &eventq_ptr, efx->type->evq_ptr_tbl_base, |
1116 | channel->channel); | |
8ceee660 BH |
1117 | |
1118 | /* Unpin event queue */ | |
1119 | falcon_fini_special_buffer(efx, &channel->eventq); | |
1120 | } | |
1121 | ||
1122 | /* Free buffers backing event queue */ | |
1123 | void falcon_remove_eventq(struct efx_channel *channel) | |
1124 | { | |
1125 | falcon_free_special_buffer(channel->efx, &channel->eventq); | |
1126 | } | |
1127 | ||
1128 | ||
1129 | /* Generates a test event on the event queue. A subsequent call to | |
1130 | * process_eventq() should pick up the event and place the value of | |
1131 | * "magic" into channel->eventq_magic; | |
1132 | */ | |
1133 | void falcon_generate_test_event(struct efx_channel *channel, unsigned int magic) | |
1134 | { | |
1135 | efx_qword_t test_event; | |
1136 | ||
3e6c4538 BH |
1137 | EFX_POPULATE_QWORD_2(test_event, FSF_AZ_EV_CODE, |
1138 | FSE_AZ_EV_CODE_DRV_GEN_EV, | |
1139 | FSF_AZ_DRV_GEN_EV_MAGIC, magic); | |
8ceee660 BH |
1140 | falcon_generate_event(channel, &test_event); |
1141 | } | |
1142 | ||
177dfcd8 BH |
1143 | void falcon_sim_phy_event(struct efx_nic *efx) |
1144 | { | |
1145 | efx_qword_t phy_event; | |
1146 | ||
3e6c4538 BH |
1147 | EFX_POPULATE_QWORD_1(phy_event, FSF_AZ_EV_CODE, |
1148 | FSE_AZ_EV_CODE_GLOBAL_EV); | |
177dfcd8 | 1149 | if (EFX_IS10G(efx)) |
3e6c4538 | 1150 | EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_XG_PHY0_INTR, 1); |
177dfcd8 | 1151 | else |
3e6c4538 | 1152 | EFX_SET_QWORD_FIELD(phy_event, FSF_AB_GLB_EV_G_PHY0_INTR, 1); |
177dfcd8 BH |
1153 | |
1154 | falcon_generate_event(&efx->channel[0], &phy_event); | |
1155 | } | |
1156 | ||
6bc5d3a9 BH |
1157 | /************************************************************************** |
1158 | * | |
1159 | * Flush handling | |
1160 | * | |
1161 | **************************************************************************/ | |
1162 | ||
1163 | ||
1164 | static void falcon_poll_flush_events(struct efx_nic *efx) | |
1165 | { | |
1166 | struct efx_channel *channel = &efx->channel[0]; | |
1167 | struct efx_tx_queue *tx_queue; | |
1168 | struct efx_rx_queue *rx_queue; | |
4720bc6c | 1169 | unsigned int read_ptr = channel->eventq_read_ptr; |
3ffeabdd | 1170 | unsigned int end_ptr = (read_ptr - 1) & EFX_EVQ_MASK; |
6bc5d3a9 | 1171 | |
4720bc6c | 1172 | do { |
6bc5d3a9 BH |
1173 | efx_qword_t *event = falcon_event(channel, read_ptr); |
1174 | int ev_code, ev_sub_code, ev_queue; | |
1175 | bool ev_failed; | |
4720bc6c | 1176 | |
6bc5d3a9 BH |
1177 | if (!falcon_event_present(event)) |
1178 | break; | |
1179 | ||
3e6c4538 BH |
1180 | ev_code = EFX_QWORD_FIELD(*event, FSF_AZ_EV_CODE); |
1181 | ev_sub_code = EFX_QWORD_FIELD(*event, | |
1182 | FSF_AZ_DRIVER_EV_SUBCODE); | |
1183 | if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV && | |
1184 | ev_sub_code == FSE_AZ_TX_DESCQ_FLS_DONE_EV) { | |
6bc5d3a9 | 1185 | ev_queue = EFX_QWORD_FIELD(*event, |
3e6c4538 | 1186 | FSF_AZ_DRIVER_EV_SUBDATA); |
6bc5d3a9 BH |
1187 | if (ev_queue < EFX_TX_QUEUE_COUNT) { |
1188 | tx_queue = efx->tx_queue + ev_queue; | |
127e6e10 | 1189 | tx_queue->flushed = FLUSH_DONE; |
6bc5d3a9 | 1190 | } |
3e6c4538 BH |
1191 | } else if (ev_code == FSE_AZ_EV_CODE_DRIVER_EV && |
1192 | ev_sub_code == FSE_AZ_RX_DESCQ_FLS_DONE_EV) { | |
1193 | ev_queue = EFX_QWORD_FIELD( | |
1194 | *event, FSF_AZ_DRIVER_EV_RX_DESCQ_ID); | |
1195 | ev_failed = EFX_QWORD_FIELD( | |
1196 | *event, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL); | |
6bc5d3a9 BH |
1197 | if (ev_queue < efx->n_rx_queues) { |
1198 | rx_queue = efx->rx_queue + ev_queue; | |
127e6e10 BH |
1199 | rx_queue->flushed = |
1200 | ev_failed ? FLUSH_FAILED : FLUSH_DONE; | |
6bc5d3a9 | 1201 | } |
6bc5d3a9 BH |
1202 | } |
1203 | ||
127e6e10 BH |
1204 | /* We're about to destroy the queue anyway, so |
1205 | * it's ok to throw away every non-flush event */ | |
1206 | EFX_SET_QWORD(*event); | |
1207 | ||
3ffeabdd | 1208 | read_ptr = (read_ptr + 1) & EFX_EVQ_MASK; |
4720bc6c | 1209 | } while (read_ptr != end_ptr); |
127e6e10 BH |
1210 | |
1211 | channel->eventq_read_ptr = read_ptr; | |
1212 | } | |
1213 | ||
1214 | static void falcon_prepare_flush(struct efx_nic *efx) | |
1215 | { | |
1216 | falcon_deconfigure_mac_wrapper(efx); | |
1217 | ||
1218 | /* Wait for the tx and rx fifo's to get to the next packet boundary | |
1219 | * (~1ms without back-pressure), then to drain the remainder of the | |
1220 | * fifo's at data path speeds (negligible), with a healthy margin. */ | |
1221 | msleep(10); | |
6bc5d3a9 BH |
1222 | } |
1223 | ||
1224 | /* Handle tx and rx flushes at the same time, since they run in | |
1225 | * parallel in the hardware and there's no reason for us to | |
1226 | * serialise them */ | |
1227 | int falcon_flush_queues(struct efx_nic *efx) | |
1228 | { | |
1229 | struct efx_rx_queue *rx_queue; | |
1230 | struct efx_tx_queue *tx_queue; | |
127e6e10 | 1231 | int i, tx_pending, rx_pending; |
6bc5d3a9 | 1232 | |
127e6e10 BH |
1233 | falcon_prepare_flush(efx); |
1234 | ||
1235 | /* Flush all tx queues in parallel */ | |
1236 | efx_for_each_tx_queue(tx_queue, efx) | |
6bc5d3a9 | 1237 | falcon_flush_tx_queue(tx_queue); |
6bc5d3a9 | 1238 | |
127e6e10 BH |
1239 | /* The hardware supports four concurrent rx flushes, each of which may |
1240 | * need to be retried if there is an outstanding descriptor fetch */ | |
6bc5d3a9 | 1241 | for (i = 0; i < FALCON_FLUSH_POLL_COUNT; ++i) { |
127e6e10 BH |
1242 | rx_pending = tx_pending = 0; |
1243 | efx_for_each_rx_queue(rx_queue, efx) { | |
1244 | if (rx_queue->flushed == FLUSH_PENDING) | |
1245 | ++rx_pending; | |
1246 | } | |
1247 | efx_for_each_rx_queue(rx_queue, efx) { | |
1248 | if (rx_pending == FALCON_RX_FLUSH_COUNT) | |
1249 | break; | |
1250 | if (rx_queue->flushed == FLUSH_FAILED || | |
1251 | rx_queue->flushed == FLUSH_NONE) { | |
1252 | falcon_flush_rx_queue(rx_queue); | |
1253 | ++rx_pending; | |
1254 | } | |
1255 | } | |
1256 | efx_for_each_tx_queue(tx_queue, efx) { | |
1257 | if (tx_queue->flushed != FLUSH_DONE) | |
1258 | ++tx_pending; | |
1259 | } | |
6bc5d3a9 | 1260 | |
127e6e10 | 1261 | if (rx_pending == 0 && tx_pending == 0) |
6bc5d3a9 | 1262 | return 0; |
127e6e10 BH |
1263 | |
1264 | msleep(FALCON_FLUSH_INTERVAL); | |
1265 | falcon_poll_flush_events(efx); | |
6bc5d3a9 BH |
1266 | } |
1267 | ||
1268 | /* Mark the queues as all flushed. We're going to return failure | |
127e6e10 | 1269 | * leading to a reset, or fake up success anyway */ |
6bc5d3a9 | 1270 | efx_for_each_tx_queue(tx_queue, efx) { |
127e6e10 | 1271 | if (tx_queue->flushed != FLUSH_DONE) |
6bc5d3a9 BH |
1272 | EFX_ERR(efx, "tx queue %d flush command timed out\n", |
1273 | tx_queue->queue); | |
127e6e10 | 1274 | tx_queue->flushed = FLUSH_DONE; |
6bc5d3a9 BH |
1275 | } |
1276 | efx_for_each_rx_queue(rx_queue, efx) { | |
127e6e10 | 1277 | if (rx_queue->flushed != FLUSH_DONE) |
6bc5d3a9 BH |
1278 | EFX_ERR(efx, "rx queue %d flush command timed out\n", |
1279 | rx_queue->queue); | |
127e6e10 | 1280 | rx_queue->flushed = FLUSH_DONE; |
6bc5d3a9 BH |
1281 | } |
1282 | ||
1283 | if (EFX_WORKAROUND_7803(efx)) | |
1284 | return 0; | |
1285 | ||
1286 | return -ETIMEDOUT; | |
1287 | } | |
8ceee660 BH |
1288 | |
1289 | /************************************************************************** | |
1290 | * | |
1291 | * Falcon hardware interrupts | |
1292 | * The hardware interrupt handler does very little work; all the event | |
1293 | * queue processing is carried out by per-channel tasklets. | |
1294 | * | |
1295 | **************************************************************************/ | |
1296 | ||
1297 | /* Enable/disable/generate Falcon interrupts */ | |
1298 | static inline void falcon_interrupts(struct efx_nic *efx, int enabled, | |
1299 | int force) | |
1300 | { | |
1301 | efx_oword_t int_en_reg_ker; | |
1302 | ||
1303 | EFX_POPULATE_OWORD_2(int_en_reg_ker, | |
3e6c4538 BH |
1304 | FRF_AZ_KER_INT_KER, force, |
1305 | FRF_AZ_DRV_INT_EN_KER, enabled); | |
12d00cad | 1306 | efx_writeo(efx, &int_en_reg_ker, FR_AZ_INT_EN_KER); |
8ceee660 BH |
1307 | } |
1308 | ||
1309 | void falcon_enable_interrupts(struct efx_nic *efx) | |
1310 | { | |
1311 | efx_oword_t int_adr_reg_ker; | |
1312 | struct efx_channel *channel; | |
1313 | ||
1314 | EFX_ZERO_OWORD(*((efx_oword_t *) efx->irq_status.addr)); | |
1315 | wmb(); /* Ensure interrupt vector is clear before interrupts enabled */ | |
1316 | ||
1317 | /* Program address */ | |
1318 | EFX_POPULATE_OWORD_2(int_adr_reg_ker, | |
3e6c4538 BH |
1319 | FRF_AZ_NORM_INT_VEC_DIS_KER, |
1320 | EFX_INT_MODE_USE_MSI(efx), | |
1321 | FRF_AZ_INT_ADR_KER, efx->irq_status.dma_addr); | |
12d00cad | 1322 | efx_writeo(efx, &int_adr_reg_ker, FR_AZ_INT_ADR_KER); |
8ceee660 BH |
1323 | |
1324 | /* Enable interrupts */ | |
1325 | falcon_interrupts(efx, 1, 0); | |
1326 | ||
1327 | /* Force processing of all the channels to get the EVQ RPTRs up to | |
1328 | date */ | |
64ee3120 | 1329 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1330 | efx_schedule_channel(channel); |
1331 | } | |
1332 | ||
1333 | void falcon_disable_interrupts(struct efx_nic *efx) | |
1334 | { | |
1335 | /* Disable interrupts */ | |
1336 | falcon_interrupts(efx, 0, 0); | |
1337 | } | |
1338 | ||
1339 | /* Generate a Falcon test interrupt | |
1340 | * Interrupt must already have been enabled, otherwise nasty things | |
1341 | * may happen. | |
1342 | */ | |
1343 | void falcon_generate_interrupt(struct efx_nic *efx) | |
1344 | { | |
1345 | falcon_interrupts(efx, 1, 1); | |
1346 | } | |
1347 | ||
1348 | /* Acknowledge a legacy interrupt from Falcon | |
1349 | * | |
1350 | * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG. | |
1351 | * | |
1352 | * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the | |
1353 | * BIU. Interrupt acknowledge is read sensitive so must write instead | |
1354 | * (then read to ensure the BIU collector is flushed) | |
1355 | * | |
1356 | * NB most hardware supports MSI interrupts | |
1357 | */ | |
1358 | static inline void falcon_irq_ack_a1(struct efx_nic *efx) | |
1359 | { | |
1360 | efx_dword_t reg; | |
1361 | ||
3e6c4538 | 1362 | EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e); |
12d00cad BH |
1363 | efx_writed(efx, ®, FR_AA_INT_ACK_KER); |
1364 | efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS); | |
8ceee660 BH |
1365 | } |
1366 | ||
1367 | /* Process a fatal interrupt | |
1368 | * Disable bus mastering ASAP and schedule a reset | |
1369 | */ | |
1370 | static irqreturn_t falcon_fatal_interrupt(struct efx_nic *efx) | |
1371 | { | |
1372 | struct falcon_nic_data *nic_data = efx->nic_data; | |
d3208b5e | 1373 | efx_oword_t *int_ker = efx->irq_status.addr; |
8ceee660 BH |
1374 | efx_oword_t fatal_intr; |
1375 | int error, mem_perr; | |
8ceee660 | 1376 | |
12d00cad | 1377 | efx_reado(efx, &fatal_intr, FR_AZ_FATAL_INTR_KER); |
3e6c4538 | 1378 | error = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_FATAL_INTR); |
8ceee660 BH |
1379 | |
1380 | EFX_ERR(efx, "SYSTEM ERROR " EFX_OWORD_FMT " status " | |
1381 | EFX_OWORD_FMT ": %s\n", EFX_OWORD_VAL(*int_ker), | |
1382 | EFX_OWORD_VAL(fatal_intr), | |
1383 | error ? "disabling bus mastering" : "no recognised error"); | |
1384 | if (error == 0) | |
1385 | goto out; | |
1386 | ||
1387 | /* If this is a memory parity error dump which blocks are offending */ | |
3e6c4538 | 1388 | mem_perr = EFX_OWORD_FIELD(fatal_intr, FRF_AZ_MEM_PERR_INT_KER); |
8ceee660 BH |
1389 | if (mem_perr) { |
1390 | efx_oword_t reg; | |
12d00cad | 1391 | efx_reado(efx, ®, FR_AZ_MEM_STAT); |
8ceee660 BH |
1392 | EFX_ERR(efx, "SYSTEM ERROR: memory parity error " |
1393 | EFX_OWORD_FMT "\n", EFX_OWORD_VAL(reg)); | |
1394 | } | |
1395 | ||
0a62f1a6 | 1396 | /* Disable both devices */ |
ef1bba28 | 1397 | pci_clear_master(efx->pci_dev); |
8ceee660 | 1398 | if (FALCON_IS_DUAL_FUNC(efx)) |
ef1bba28 | 1399 | pci_clear_master(nic_data->pci_dev2); |
0a62f1a6 | 1400 | falcon_disable_interrupts(efx); |
8ceee660 | 1401 | |
2c3c3d02 | 1402 | /* Count errors and reset or disable the NIC accordingly */ |
0484e0db BH |
1403 | if (efx->int_error_count == 0 || |
1404 | time_after(jiffies, efx->int_error_expire)) { | |
1405 | efx->int_error_count = 0; | |
1406 | efx->int_error_expire = | |
2c3c3d02 BH |
1407 | jiffies + FALCON_INT_ERROR_EXPIRE * HZ; |
1408 | } | |
0484e0db | 1409 | if (++efx->int_error_count < FALCON_MAX_INT_ERRORS) { |
8ceee660 BH |
1410 | EFX_ERR(efx, "SYSTEM ERROR - reset scheduled\n"); |
1411 | efx_schedule_reset(efx, RESET_TYPE_INT_ERROR); | |
1412 | } else { | |
1413 | EFX_ERR(efx, "SYSTEM ERROR - max number of errors seen." | |
1414 | "NIC will be disabled\n"); | |
1415 | efx_schedule_reset(efx, RESET_TYPE_DISABLE); | |
1416 | } | |
1417 | out: | |
1418 | return IRQ_HANDLED; | |
1419 | } | |
1420 | ||
1421 | /* Handle a legacy interrupt from Falcon | |
1422 | * Acknowledges the interrupt and schedule event queue processing. | |
1423 | */ | |
1424 | static irqreturn_t falcon_legacy_interrupt_b0(int irq, void *dev_id) | |
1425 | { | |
d3208b5e BH |
1426 | struct efx_nic *efx = dev_id; |
1427 | efx_oword_t *int_ker = efx->irq_status.addr; | |
a9de9a74 | 1428 | irqreturn_t result = IRQ_NONE; |
8ceee660 BH |
1429 | struct efx_channel *channel; |
1430 | efx_dword_t reg; | |
1431 | u32 queues; | |
1432 | int syserr; | |
1433 | ||
1434 | /* Read the ISR which also ACKs the interrupts */ | |
12d00cad | 1435 | efx_readd(efx, ®, FR_BZ_INT_ISR0); |
8ceee660 BH |
1436 | queues = EFX_EXTRACT_DWORD(reg, 0, 31); |
1437 | ||
1438 | /* Check to see if we have a serious error condition */ | |
3e6c4538 | 1439 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
8ceee660 BH |
1440 | if (unlikely(syserr)) |
1441 | return falcon_fatal_interrupt(efx); | |
1442 | ||
8ceee660 | 1443 | /* Schedule processing of any interrupting queues */ |
a9de9a74 BH |
1444 | efx_for_each_channel(channel, efx) { |
1445 | if ((queues & 1) || | |
1446 | falcon_event_present( | |
1447 | falcon_event(channel, channel->eventq_read_ptr))) { | |
8ceee660 | 1448 | efx_schedule_channel(channel); |
a9de9a74 BH |
1449 | result = IRQ_HANDLED; |
1450 | } | |
8ceee660 BH |
1451 | queues >>= 1; |
1452 | } | |
1453 | ||
a9de9a74 BH |
1454 | if (result == IRQ_HANDLED) { |
1455 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1456 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_DWORD_FMT "\n", | |
1457 | irq, raw_smp_processor_id(), EFX_DWORD_VAL(reg)); | |
1458 | } | |
1459 | ||
1460 | return result; | |
8ceee660 BH |
1461 | } |
1462 | ||
1463 | ||
1464 | static irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id) | |
1465 | { | |
d3208b5e BH |
1466 | struct efx_nic *efx = dev_id; |
1467 | efx_oword_t *int_ker = efx->irq_status.addr; | |
8ceee660 BH |
1468 | struct efx_channel *channel; |
1469 | int syserr; | |
1470 | int queues; | |
1471 | ||
1472 | /* Check to see if this is our interrupt. If it isn't, we | |
1473 | * exit without having touched the hardware. | |
1474 | */ | |
1475 | if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) { | |
1476 | EFX_TRACE(efx, "IRQ %d on CPU %d not for me\n", irq, | |
1477 | raw_smp_processor_id()); | |
1478 | return IRQ_NONE; | |
1479 | } | |
1480 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1481 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
1482 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
1483 | ||
1484 | /* Check to see if we have a serious error condition */ | |
3e6c4538 | 1485 | syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT); |
8ceee660 BH |
1486 | if (unlikely(syserr)) |
1487 | return falcon_fatal_interrupt(efx); | |
1488 | ||
1489 | /* Determine interrupting queues, clear interrupt status | |
1490 | * register and acknowledge the device interrupt. | |
1491 | */ | |
1492 | BUILD_BUG_ON(INT_EVQS_WIDTH > EFX_MAX_CHANNELS); | |
1493 | queues = EFX_OWORD_FIELD(*int_ker, INT_EVQS); | |
1494 | EFX_ZERO_OWORD(*int_ker); | |
1495 | wmb(); /* Ensure the vector is cleared before interrupt ack */ | |
1496 | falcon_irq_ack_a1(efx); | |
1497 | ||
1498 | /* Schedule processing of any interrupting queues */ | |
1499 | channel = &efx->channel[0]; | |
1500 | while (queues) { | |
1501 | if (queues & 0x01) | |
1502 | efx_schedule_channel(channel); | |
1503 | channel++; | |
1504 | queues >>= 1; | |
1505 | } | |
1506 | ||
1507 | return IRQ_HANDLED; | |
1508 | } | |
1509 | ||
1510 | /* Handle an MSI interrupt from Falcon | |
1511 | * | |
1512 | * Handle an MSI hardware interrupt. This routine schedules event | |
1513 | * queue processing. No interrupt acknowledgement cycle is necessary. | |
1514 | * Also, we never need to check that the interrupt is for us, since | |
1515 | * MSI interrupts cannot be shared. | |
1516 | */ | |
1517 | static irqreturn_t falcon_msi_interrupt(int irq, void *dev_id) | |
1518 | { | |
d3208b5e | 1519 | struct efx_channel *channel = dev_id; |
8ceee660 | 1520 | struct efx_nic *efx = channel->efx; |
d3208b5e | 1521 | efx_oword_t *int_ker = efx->irq_status.addr; |
8ceee660 BH |
1522 | int syserr; |
1523 | ||
1524 | efx->last_irq_cpu = raw_smp_processor_id(); | |
1525 | EFX_TRACE(efx, "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n", | |
1526 | irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker)); | |
1527 | ||
1528 | /* Check to see if we have a serious error condition */ | |
1529 | syserr = EFX_OWORD_FIELD(*int_ker, FATAL_INT); | |
1530 | if (unlikely(syserr)) | |
1531 | return falcon_fatal_interrupt(efx); | |
1532 | ||
1533 | /* Schedule processing of the channel */ | |
1534 | efx_schedule_channel(channel); | |
1535 | ||
1536 | return IRQ_HANDLED; | |
1537 | } | |
1538 | ||
1539 | ||
1540 | /* Setup RSS indirection table. | |
1541 | * This maps from the hash value of the packet to RXQ | |
1542 | */ | |
1543 | static void falcon_setup_rss_indir_table(struct efx_nic *efx) | |
1544 | { | |
1545 | int i = 0; | |
1546 | unsigned long offset; | |
1547 | efx_dword_t dword; | |
1548 | ||
55668611 | 1549 | if (falcon_rev(efx) < FALCON_REV_B0) |
8ceee660 BH |
1550 | return; |
1551 | ||
3e6c4538 BH |
1552 | for (offset = FR_BZ_RX_INDIRECTION_TBL; |
1553 | offset < FR_BZ_RX_INDIRECTION_TBL + 0x800; | |
8ceee660 | 1554 | offset += 0x10) { |
3e6c4538 | 1555 | EFX_POPULATE_DWORD_1(dword, FRF_BZ_IT_QUEUE, |
8831da7b | 1556 | i % efx->n_rx_queues); |
12d00cad | 1557 | efx_writed(efx, &dword, offset); |
8ceee660 BH |
1558 | i++; |
1559 | } | |
1560 | } | |
1561 | ||
1562 | /* Hook interrupt handler(s) | |
1563 | * Try MSI and then legacy interrupts. | |
1564 | */ | |
1565 | int falcon_init_interrupt(struct efx_nic *efx) | |
1566 | { | |
1567 | struct efx_channel *channel; | |
1568 | int rc; | |
1569 | ||
1570 | if (!EFX_INT_MODE_USE_MSI(efx)) { | |
1571 | irq_handler_t handler; | |
55668611 | 1572 | if (falcon_rev(efx) >= FALCON_REV_B0) |
8ceee660 BH |
1573 | handler = falcon_legacy_interrupt_b0; |
1574 | else | |
1575 | handler = falcon_legacy_interrupt_a1; | |
1576 | ||
1577 | rc = request_irq(efx->legacy_irq, handler, IRQF_SHARED, | |
1578 | efx->name, efx); | |
1579 | if (rc) { | |
1580 | EFX_ERR(efx, "failed to hook legacy IRQ %d\n", | |
1581 | efx->pci_dev->irq); | |
1582 | goto fail1; | |
1583 | } | |
1584 | return 0; | |
1585 | } | |
1586 | ||
1587 | /* Hook MSI or MSI-X interrupt */ | |
64ee3120 | 1588 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1589 | rc = request_irq(channel->irq, falcon_msi_interrupt, |
1590 | IRQF_PROBE_SHARED, /* Not shared */ | |
56536e9c | 1591 | channel->name, channel); |
8ceee660 BH |
1592 | if (rc) { |
1593 | EFX_ERR(efx, "failed to hook IRQ %d\n", channel->irq); | |
1594 | goto fail2; | |
1595 | } | |
1596 | } | |
1597 | ||
1598 | return 0; | |
1599 | ||
1600 | fail2: | |
64ee3120 | 1601 | efx_for_each_channel(channel, efx) |
8ceee660 BH |
1602 | free_irq(channel->irq, channel); |
1603 | fail1: | |
1604 | return rc; | |
1605 | } | |
1606 | ||
1607 | void falcon_fini_interrupt(struct efx_nic *efx) | |
1608 | { | |
1609 | struct efx_channel *channel; | |
1610 | efx_oword_t reg; | |
1611 | ||
1612 | /* Disable MSI/MSI-X interrupts */ | |
64ee3120 | 1613 | efx_for_each_channel(channel, efx) { |
8ceee660 BH |
1614 | if (channel->irq) |
1615 | free_irq(channel->irq, channel); | |
b3475645 | 1616 | } |
8ceee660 BH |
1617 | |
1618 | /* ACK legacy interrupt */ | |
55668611 | 1619 | if (falcon_rev(efx) >= FALCON_REV_B0) |
12d00cad | 1620 | efx_reado(efx, ®, FR_BZ_INT_ISR0); |
8ceee660 BH |
1621 | else |
1622 | falcon_irq_ack_a1(efx); | |
1623 | ||
1624 | /* Disable legacy interrupt */ | |
1625 | if (efx->legacy_irq) | |
1626 | free_irq(efx->legacy_irq, efx); | |
1627 | } | |
1628 | ||
1629 | /************************************************************************** | |
1630 | * | |
1631 | * EEPROM/flash | |
1632 | * | |
1633 | ************************************************************************** | |
1634 | */ | |
1635 | ||
23d30f02 | 1636 | #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t) |
8ceee660 | 1637 | |
be4ea89c BH |
1638 | static int falcon_spi_poll(struct efx_nic *efx) |
1639 | { | |
1640 | efx_oword_t reg; | |
12d00cad | 1641 | efx_reado(efx, ®, FR_AB_EE_SPI_HCMD); |
3e6c4538 | 1642 | return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0; |
be4ea89c BH |
1643 | } |
1644 | ||
8ceee660 BH |
1645 | /* Wait for SPI command completion */ |
1646 | static int falcon_spi_wait(struct efx_nic *efx) | |
1647 | { | |
be4ea89c BH |
1648 | /* Most commands will finish quickly, so we start polling at |
1649 | * very short intervals. Sometimes the command may have to | |
1650 | * wait for VPD or expansion ROM access outside of our | |
1651 | * control, so we allow up to 100 ms. */ | |
1652 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10); | |
1653 | int i; | |
1654 | ||
1655 | for (i = 0; i < 10; i++) { | |
1656 | if (!falcon_spi_poll(efx)) | |
1657 | return 0; | |
1658 | udelay(10); | |
1659 | } | |
8ceee660 | 1660 | |
4a5b504d | 1661 | for (;;) { |
be4ea89c | 1662 | if (!falcon_spi_poll(efx)) |
8ceee660 | 1663 | return 0; |
4a5b504d BH |
1664 | if (time_after_eq(jiffies, timeout)) { |
1665 | EFX_ERR(efx, "timed out waiting for SPI\n"); | |
1666 | return -ETIMEDOUT; | |
1667 | } | |
be4ea89c | 1668 | schedule_timeout_uninterruptible(1); |
4a5b504d | 1669 | } |
8ceee660 BH |
1670 | } |
1671 | ||
f4150724 BH |
1672 | int falcon_spi_cmd(const struct efx_spi_device *spi, |
1673 | unsigned int command, int address, | |
23d30f02 | 1674 | const void *in, void *out, size_t len) |
8ceee660 | 1675 | { |
4a5b504d BH |
1676 | struct efx_nic *efx = spi->efx; |
1677 | bool addressed = (address >= 0); | |
1678 | bool reading = (out != NULL); | |
8ceee660 BH |
1679 | efx_oword_t reg; |
1680 | int rc; | |
1681 | ||
4a5b504d BH |
1682 | /* Input validation */ |
1683 | if (len > FALCON_SPI_MAX_LEN) | |
1684 | return -EINVAL; | |
f4150724 | 1685 | BUG_ON(!mutex_is_locked(&efx->spi_lock)); |
8ceee660 | 1686 | |
be4ea89c BH |
1687 | /* Check that previous command is not still running */ |
1688 | rc = falcon_spi_poll(efx); | |
8ceee660 BH |
1689 | if (rc) |
1690 | return rc; | |
1691 | ||
4a5b504d BH |
1692 | /* Program address register, if we have an address */ |
1693 | if (addressed) { | |
3e6c4538 | 1694 | EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address); |
12d00cad | 1695 | efx_writeo(efx, ®, FR_AB_EE_SPI_HADR); |
4a5b504d BH |
1696 | } |
1697 | ||
1698 | /* Program data register, if we have data */ | |
1699 | if (in != NULL) { | |
1700 | memcpy(®, in, len); | |
12d00cad | 1701 | efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d | 1702 | } |
8ceee660 | 1703 | |
4a5b504d | 1704 | /* Issue read/write command */ |
8ceee660 | 1705 | EFX_POPULATE_OWORD_7(reg, |
3e6c4538 BH |
1706 | FRF_AB_EE_SPI_HCMD_CMD_EN, 1, |
1707 | FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id, | |
1708 | FRF_AB_EE_SPI_HCMD_DABCNT, len, | |
1709 | FRF_AB_EE_SPI_HCMD_READ, reading, | |
1710 | FRF_AB_EE_SPI_HCMD_DUBCNT, 0, | |
1711 | FRF_AB_EE_SPI_HCMD_ADBCNT, | |
4a5b504d | 1712 | (addressed ? spi->addr_len : 0), |
3e6c4538 | 1713 | FRF_AB_EE_SPI_HCMD_ENC, command); |
12d00cad | 1714 | efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD); |
8ceee660 | 1715 | |
4a5b504d | 1716 | /* Wait for read/write to complete */ |
8ceee660 BH |
1717 | rc = falcon_spi_wait(efx); |
1718 | if (rc) | |
1719 | return rc; | |
1720 | ||
1721 | /* Read data */ | |
4a5b504d | 1722 | if (out != NULL) { |
12d00cad | 1723 | efx_reado(efx, ®, FR_AB_EE_SPI_HDATA); |
4a5b504d BH |
1724 | memcpy(out, ®, len); |
1725 | } | |
1726 | ||
8ceee660 BH |
1727 | return 0; |
1728 | } | |
1729 | ||
23d30f02 BH |
1730 | static size_t |
1731 | falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start) | |
4a5b504d BH |
1732 | { |
1733 | return min(FALCON_SPI_MAX_LEN, | |
1734 | (spi->block_size - (start & (spi->block_size - 1)))); | |
1735 | } | |
1736 | ||
1737 | static inline u8 | |
1738 | efx_spi_munge_command(const struct efx_spi_device *spi, | |
1739 | const u8 command, const unsigned int address) | |
1740 | { | |
1741 | return command | (((address >> 8) & spi->munge_address) << 3); | |
1742 | } | |
1743 | ||
be4ea89c BH |
1744 | /* Wait up to 10 ms for buffered write completion */ |
1745 | int falcon_spi_wait_write(const struct efx_spi_device *spi) | |
4a5b504d | 1746 | { |
be4ea89c BH |
1747 | struct efx_nic *efx = spi->efx; |
1748 | unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100); | |
4a5b504d | 1749 | u8 status; |
be4ea89c | 1750 | int rc; |
4a5b504d | 1751 | |
be4ea89c | 1752 | for (;;) { |
4a5b504d BH |
1753 | rc = falcon_spi_cmd(spi, SPI_RDSR, -1, NULL, |
1754 | &status, sizeof(status)); | |
1755 | if (rc) | |
1756 | return rc; | |
1757 | if (!(status & SPI_STATUS_NRDY)) | |
1758 | return 0; | |
be4ea89c BH |
1759 | if (time_after_eq(jiffies, timeout)) { |
1760 | EFX_ERR(efx, "SPI write timeout on device %d" | |
1761 | " last status=0x%02x\n", | |
1762 | spi->device_id, status); | |
1763 | return -ETIMEDOUT; | |
1764 | } | |
1765 | schedule_timeout_uninterruptible(1); | |
4a5b504d | 1766 | } |
4a5b504d BH |
1767 | } |
1768 | ||
1769 | int falcon_spi_read(const struct efx_spi_device *spi, loff_t start, | |
1770 | size_t len, size_t *retlen, u8 *buffer) | |
1771 | { | |
23d30f02 BH |
1772 | size_t block_len, pos = 0; |
1773 | unsigned int command; | |
4a5b504d BH |
1774 | int rc = 0; |
1775 | ||
1776 | while (pos < len) { | |
23d30f02 | 1777 | block_len = min(len - pos, FALCON_SPI_MAX_LEN); |
4a5b504d BH |
1778 | |
1779 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
1780 | rc = falcon_spi_cmd(spi, command, start + pos, NULL, | |
1781 | buffer + pos, block_len); | |
1782 | if (rc) | |
1783 | break; | |
1784 | pos += block_len; | |
1785 | ||
1786 | /* Avoid locking up the system */ | |
1787 | cond_resched(); | |
1788 | if (signal_pending(current)) { | |
1789 | rc = -EINTR; | |
1790 | break; | |
1791 | } | |
1792 | } | |
1793 | ||
1794 | if (retlen) | |
1795 | *retlen = pos; | |
1796 | return rc; | |
1797 | } | |
1798 | ||
1799 | int falcon_spi_write(const struct efx_spi_device *spi, loff_t start, | |
1800 | size_t len, size_t *retlen, const u8 *buffer) | |
1801 | { | |
1802 | u8 verify_buffer[FALCON_SPI_MAX_LEN]; | |
23d30f02 BH |
1803 | size_t block_len, pos = 0; |
1804 | unsigned int command; | |
4a5b504d BH |
1805 | int rc = 0; |
1806 | ||
1807 | while (pos < len) { | |
1808 | rc = falcon_spi_cmd(spi, SPI_WREN, -1, NULL, NULL, 0); | |
1809 | if (rc) | |
1810 | break; | |
1811 | ||
23d30f02 | 1812 | block_len = min(len - pos, |
4a5b504d BH |
1813 | falcon_spi_write_limit(spi, start + pos)); |
1814 | command = efx_spi_munge_command(spi, SPI_WRITE, start + pos); | |
1815 | rc = falcon_spi_cmd(spi, command, start + pos, | |
1816 | buffer + pos, NULL, block_len); | |
1817 | if (rc) | |
1818 | break; | |
1819 | ||
be4ea89c | 1820 | rc = falcon_spi_wait_write(spi); |
4a5b504d BH |
1821 | if (rc) |
1822 | break; | |
1823 | ||
1824 | command = efx_spi_munge_command(spi, SPI_READ, start + pos); | |
1825 | rc = falcon_spi_cmd(spi, command, start + pos, | |
1826 | NULL, verify_buffer, block_len); | |
1827 | if (memcmp(verify_buffer, buffer + pos, block_len)) { | |
1828 | rc = -EIO; | |
1829 | break; | |
1830 | } | |
1831 | ||
1832 | pos += block_len; | |
1833 | ||
1834 | /* Avoid locking up the system */ | |
1835 | cond_resched(); | |
1836 | if (signal_pending(current)) { | |
1837 | rc = -EINTR; | |
1838 | break; | |
1839 | } | |
1840 | } | |
1841 | ||
1842 | if (retlen) | |
1843 | *retlen = pos; | |
1844 | return rc; | |
1845 | } | |
1846 | ||
8ceee660 BH |
1847 | /************************************************************************** |
1848 | * | |
1849 | * MAC wrapper | |
1850 | * | |
1851 | ************************************************************************** | |
1852 | */ | |
177dfcd8 BH |
1853 | |
1854 | static int falcon_reset_macs(struct efx_nic *efx) | |
8ceee660 | 1855 | { |
177dfcd8 | 1856 | efx_oword_t reg; |
8ceee660 BH |
1857 | int count; |
1858 | ||
177dfcd8 BH |
1859 | if (falcon_rev(efx) < FALCON_REV_B0) { |
1860 | /* It's not safe to use GLB_CTL_REG to reset the | |
1861 | * macs, so instead use the internal MAC resets | |
1862 | */ | |
1863 | if (!EFX_IS10G(efx)) { | |
3e6c4538 | 1864 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 1); |
12d00cad | 1865 | efx_writeo(efx, ®, FR_AB_GM_CFG1); |
177dfcd8 BH |
1866 | udelay(1000); |
1867 | ||
3e6c4538 | 1868 | EFX_POPULATE_OWORD_1(reg, FRF_AB_GM_SW_RST, 0); |
12d00cad | 1869 | efx_writeo(efx, ®, FR_AB_GM_CFG1); |
177dfcd8 BH |
1870 | udelay(1000); |
1871 | return 0; | |
1872 | } else { | |
3e6c4538 | 1873 | EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1); |
12d00cad | 1874 | efx_writeo(efx, ®, FR_AB_XM_GLB_CFG); |
177dfcd8 BH |
1875 | |
1876 | for (count = 0; count < 10000; count++) { | |
12d00cad | 1877 | efx_reado(efx, ®, FR_AB_XM_GLB_CFG); |
3e6c4538 BH |
1878 | if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) == |
1879 | 0) | |
177dfcd8 BH |
1880 | return 0; |
1881 | udelay(10); | |
1882 | } | |
8ceee660 | 1883 | |
177dfcd8 BH |
1884 | EFX_ERR(efx, "timed out waiting for XMAC core reset\n"); |
1885 | return -ETIMEDOUT; | |
1886 | } | |
1887 | } | |
8ceee660 BH |
1888 | |
1889 | /* MAC stats will fail whilst the TX fifo is draining. Serialise | |
1890 | * the drain sequence with the statistics fetch */ | |
55edc6e6 | 1891 | falcon_stop_nic_stats(efx); |
8ceee660 | 1892 | |
12d00cad | 1893 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
3e6c4538 | 1894 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, 1); |
12d00cad | 1895 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
8ceee660 | 1896 | |
12d00cad | 1897 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
1898 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1); |
1899 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1); | |
1900 | EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1); | |
12d00cad | 1901 | efx_writeo(efx, ®, FR_AB_GLB_CTL); |
8ceee660 BH |
1902 | |
1903 | count = 0; | |
1904 | while (1) { | |
12d00cad | 1905 | efx_reado(efx, ®, FR_AB_GLB_CTL); |
3e6c4538 BH |
1906 | if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) && |
1907 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) && | |
1908 | !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) { | |
8ceee660 BH |
1909 | EFX_LOG(efx, "Completed MAC reset after %d loops\n", |
1910 | count); | |
1911 | break; | |
1912 | } | |
1913 | if (count > 20) { | |
1914 | EFX_ERR(efx, "MAC reset failed\n"); | |
1915 | break; | |
1916 | } | |
1917 | count++; | |
1918 | udelay(10); | |
1919 | } | |
1920 | ||
8ceee660 BH |
1921 | /* If we've reset the EM block and the link is up, then |
1922 | * we'll have to kick the XAUI link so the PHY can recover */ | |
eb50c0d6 | 1923 | if (efx->link_state.up && EFX_IS10G(efx) && EFX_WORKAROUND_5147(efx)) |
8ceee660 | 1924 | falcon_reset_xaui(efx); |
177dfcd8 | 1925 | |
55edc6e6 BH |
1926 | falcon_start_nic_stats(efx); |
1927 | ||
177dfcd8 BH |
1928 | return 0; |
1929 | } | |
1930 | ||
1931 | void falcon_drain_tx_fifo(struct efx_nic *efx) | |
1932 | { | |
1933 | efx_oword_t reg; | |
1934 | ||
1935 | if ((falcon_rev(efx) < FALCON_REV_B0) || | |
1936 | (efx->loopback_mode != LOOPBACK_NONE)) | |
1937 | return; | |
1938 | ||
12d00cad | 1939 | efx_reado(efx, ®, FR_AB_MAC_CTRL); |
177dfcd8 | 1940 | /* There is no point in draining more than once */ |
3e6c4538 | 1941 | if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN)) |
177dfcd8 BH |
1942 | return; |
1943 | ||
1944 | falcon_reset_macs(efx); | |
8ceee660 BH |
1945 | } |
1946 | ||
1947 | void falcon_deconfigure_mac_wrapper(struct efx_nic *efx) | |
1948 | { | |
177dfcd8 | 1949 | efx_oword_t reg; |
8ceee660 | 1950 | |
55668611 | 1951 | if (falcon_rev(efx) < FALCON_REV_B0) |
8ceee660 BH |
1952 | return; |
1953 | ||
1954 | /* Isolate the MAC -> RX */ | |
12d00cad | 1955 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
3e6c4538 | 1956 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0); |
12d00cad | 1957 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 | 1958 | |
eb50c0d6 | 1959 | if (!efx->link_state.up) |
8ceee660 BH |
1960 | falcon_drain_tx_fifo(efx); |
1961 | } | |
1962 | ||
1963 | void falcon_reconfigure_mac_wrapper(struct efx_nic *efx) | |
1964 | { | |
eb50c0d6 | 1965 | struct efx_link_state *link_state = &efx->link_state; |
8ceee660 BH |
1966 | efx_oword_t reg; |
1967 | int link_speed; | |
dc8cfa55 | 1968 | bool tx_fc; |
8ceee660 | 1969 | |
eb50c0d6 | 1970 | switch (link_state->speed) { |
f31a45d2 BH |
1971 | case 10000: link_speed = 3; break; |
1972 | case 1000: link_speed = 2; break; | |
1973 | case 100: link_speed = 1; break; | |
1974 | default: link_speed = 0; break; | |
1975 | } | |
8ceee660 BH |
1976 | /* MAC_LINK_STATUS controls MAC backpressure but doesn't work |
1977 | * as advertised. Disable to ensure packets are not | |
1978 | * indefinitely held and TX queue can be flushed at any point | |
1979 | * while the link is down. */ | |
1980 | EFX_POPULATE_OWORD_5(reg, | |
3e6c4538 BH |
1981 | FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */, |
1982 | FRF_AB_MAC_BCAD_ACPT, 1, | |
1983 | FRF_AB_MAC_UC_PROM, efx->promiscuous, | |
1984 | FRF_AB_MAC_LINK_STATUS, 1, /* always set */ | |
1985 | FRF_AB_MAC_SPEED, link_speed); | |
8ceee660 BH |
1986 | /* On B0, MAC backpressure can be disabled and packets get |
1987 | * discarded. */ | |
55668611 | 1988 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
3e6c4538 | 1989 | EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN, |
eb50c0d6 | 1990 | !link_state->up); |
8ceee660 BH |
1991 | } |
1992 | ||
12d00cad | 1993 | efx_writeo(efx, ®, FR_AB_MAC_CTRL); |
8ceee660 BH |
1994 | |
1995 | /* Restore the multicast hash registers. */ | |
8be4f3e6 | 1996 | falcon_push_multicast_hash(efx); |
8ceee660 BH |
1997 | |
1998 | /* Transmission of pause frames when RX crosses the threshold is | |
1999 | * covered by RX_XOFF_MAC_EN and XM_TX_CFG_REG:XM_FCNTL. | |
2000 | * Action on receipt of pause frames is controller by XM_DIS_FCNTL */ | |
eb50c0d6 | 2001 | tx_fc = !!(efx->link_state.fc & EFX_FC_TX); |
12d00cad | 2002 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
3e6c4538 | 2003 | EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, tx_fc); |
8ceee660 BH |
2004 | |
2005 | /* Unisolate the MAC -> RX */ | |
55668611 | 2006 | if (falcon_rev(efx) >= FALCON_REV_B0) |
3e6c4538 | 2007 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); |
12d00cad | 2008 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
8ceee660 BH |
2009 | } |
2010 | ||
55edc6e6 | 2011 | static void falcon_stats_request(struct efx_nic *efx) |
8ceee660 | 2012 | { |
55edc6e6 | 2013 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 | 2014 | efx_oword_t reg; |
8ceee660 | 2015 | |
55edc6e6 BH |
2016 | WARN_ON(nic_data->stats_pending); |
2017 | WARN_ON(nic_data->stats_disable_count); | |
8ceee660 | 2018 | |
55edc6e6 BH |
2019 | if (nic_data->stats_dma_done == NULL) |
2020 | return; /* no mac selected */ | |
8ceee660 | 2021 | |
55edc6e6 BH |
2022 | *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE; |
2023 | nic_data->stats_pending = true; | |
8ceee660 BH |
2024 | wmb(); /* ensure done flag is clear */ |
2025 | ||
2026 | /* Initiate DMA transfer of stats */ | |
2027 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2028 | FRF_AB_MAC_STAT_DMA_CMD, 1, |
2029 | FRF_AB_MAC_STAT_DMA_ADR, | |
8ceee660 | 2030 | efx->stats_buffer.dma_addr); |
12d00cad | 2031 | efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA); |
8ceee660 | 2032 | |
55edc6e6 BH |
2033 | mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2)); |
2034 | } | |
2035 | ||
2036 | static void falcon_stats_complete(struct efx_nic *efx) | |
2037 | { | |
2038 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2039 | ||
2040 | if (!nic_data->stats_pending) | |
2041 | return; | |
2042 | ||
2043 | nic_data->stats_pending = 0; | |
2044 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) { | |
2045 | rmb(); /* read the done flag before the stats */ | |
2046 | efx->mac_op->update_stats(efx); | |
2047 | } else { | |
2048 | EFX_ERR(efx, "timed out waiting for statistics\n"); | |
8ceee660 | 2049 | } |
55edc6e6 | 2050 | } |
8ceee660 | 2051 | |
55edc6e6 BH |
2052 | static void falcon_stats_timer_func(unsigned long context) |
2053 | { | |
2054 | struct efx_nic *efx = (struct efx_nic *)context; | |
2055 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2056 | ||
2057 | spin_lock(&efx->stats_lock); | |
2058 | ||
2059 | falcon_stats_complete(efx); | |
2060 | if (nic_data->stats_disable_count == 0) | |
2061 | falcon_stats_request(efx); | |
2062 | ||
2063 | spin_unlock(&efx->stats_lock); | |
8ceee660 BH |
2064 | } |
2065 | ||
2066 | /************************************************************************** | |
2067 | * | |
2068 | * PHY access via GMII | |
2069 | * | |
2070 | ************************************************************************** | |
2071 | */ | |
2072 | ||
8ceee660 BH |
2073 | /* Wait for GMII access to complete */ |
2074 | static int falcon_gmii_wait(struct efx_nic *efx) | |
2075 | { | |
80cb9a0f | 2076 | efx_oword_t md_stat; |
8ceee660 BH |
2077 | int count; |
2078 | ||
177dfcd8 BH |
2079 | /* wait upto 50ms - taken max from datasheet */ |
2080 | for (count = 0; count < 5000; count++) { | |
80cb9a0f BH |
2081 | efx_reado(efx, &md_stat, FR_AB_MD_STAT); |
2082 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) { | |
2083 | if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 || | |
2084 | EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) { | |
8ceee660 | 2085 | EFX_ERR(efx, "error from GMII access " |
80cb9a0f BH |
2086 | EFX_OWORD_FMT"\n", |
2087 | EFX_OWORD_VAL(md_stat)); | |
8ceee660 BH |
2088 | return -EIO; |
2089 | } | |
2090 | return 0; | |
2091 | } | |
2092 | udelay(10); | |
2093 | } | |
2094 | EFX_ERR(efx, "timed out waiting for GMII\n"); | |
2095 | return -ETIMEDOUT; | |
2096 | } | |
2097 | ||
68e7f45e BH |
2098 | /* Write an MDIO register of a PHY connected to Falcon. */ |
2099 | static int falcon_mdio_write(struct net_device *net_dev, | |
2100 | int prtad, int devad, u16 addr, u16 value) | |
8ceee660 | 2101 | { |
767e468c | 2102 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2103 | efx_oword_t reg; |
68e7f45e | 2104 | int rc; |
8ceee660 | 2105 | |
68e7f45e BH |
2106 | EFX_REGDUMP(efx, "writing MDIO %d register %d.%d with 0x%04x\n", |
2107 | prtad, devad, addr, value); | |
8ceee660 BH |
2108 | |
2109 | spin_lock_bh(&efx->phy_lock); | |
2110 | ||
68e7f45e BH |
2111 | /* Check MDIO not currently being accessed */ |
2112 | rc = falcon_gmii_wait(efx); | |
2113 | if (rc) | |
8ceee660 BH |
2114 | goto out; |
2115 | ||
2116 | /* Write the address/ID register */ | |
3e6c4538 | 2117 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 2118 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 2119 | |
3e6c4538 BH |
2120 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
2121 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 2122 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
2123 | |
2124 | /* Write data */ | |
3e6c4538 | 2125 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value); |
12d00cad | 2126 | efx_writeo(efx, ®, FR_AB_MD_TXD); |
8ceee660 BH |
2127 | |
2128 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2129 | FRF_AB_MD_WRC, 1, |
2130 | FRF_AB_MD_GC, 0); | |
12d00cad | 2131 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
2132 | |
2133 | /* Wait for data to be written */ | |
68e7f45e BH |
2134 | rc = falcon_gmii_wait(efx); |
2135 | if (rc) { | |
8ceee660 BH |
2136 | /* Abort the write operation */ |
2137 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2138 | FRF_AB_MD_WRC, 0, |
2139 | FRF_AB_MD_GC, 1); | |
12d00cad | 2140 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
2141 | udelay(10); |
2142 | } | |
2143 | ||
2144 | out: | |
2145 | spin_unlock_bh(&efx->phy_lock); | |
68e7f45e | 2146 | return rc; |
8ceee660 BH |
2147 | } |
2148 | ||
68e7f45e BH |
2149 | /* Read an MDIO register of a PHY connected to Falcon. */ |
2150 | static int falcon_mdio_read(struct net_device *net_dev, | |
2151 | int prtad, int devad, u16 addr) | |
8ceee660 | 2152 | { |
767e468c | 2153 | struct efx_nic *efx = netdev_priv(net_dev); |
8ceee660 | 2154 | efx_oword_t reg; |
68e7f45e | 2155 | int rc; |
8ceee660 BH |
2156 | |
2157 | spin_lock_bh(&efx->phy_lock); | |
2158 | ||
68e7f45e BH |
2159 | /* Check MDIO not currently being accessed */ |
2160 | rc = falcon_gmii_wait(efx); | |
2161 | if (rc) | |
8ceee660 BH |
2162 | goto out; |
2163 | ||
3e6c4538 | 2164 | EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr); |
12d00cad | 2165 | efx_writeo(efx, ®, FR_AB_MD_PHY_ADR); |
8ceee660 | 2166 | |
3e6c4538 BH |
2167 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad, |
2168 | FRF_AB_MD_DEV_ADR, devad); | |
12d00cad | 2169 | efx_writeo(efx, ®, FR_AB_MD_ID); |
8ceee660 BH |
2170 | |
2171 | /* Request data to be read */ | |
3e6c4538 | 2172 | EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0); |
12d00cad | 2173 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 BH |
2174 | |
2175 | /* Wait for data to become available */ | |
68e7f45e BH |
2176 | rc = falcon_gmii_wait(efx); |
2177 | if (rc == 0) { | |
12d00cad | 2178 | efx_reado(efx, ®, FR_AB_MD_RXD); |
3e6c4538 | 2179 | rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD); |
68e7f45e BH |
2180 | EFX_REGDUMP(efx, "read from MDIO %d register %d.%d, got %04x\n", |
2181 | prtad, devad, addr, rc); | |
8ceee660 BH |
2182 | } else { |
2183 | /* Abort the read operation */ | |
2184 | EFX_POPULATE_OWORD_2(reg, | |
3e6c4538 BH |
2185 | FRF_AB_MD_RIC, 0, |
2186 | FRF_AB_MD_GC, 1); | |
12d00cad | 2187 | efx_writeo(efx, ®, FR_AB_MD_CS); |
8ceee660 | 2188 | |
68e7f45e BH |
2189 | EFX_LOG(efx, "read from MDIO %d register %d.%d, got error %d\n", |
2190 | prtad, devad, addr, rc); | |
8ceee660 BH |
2191 | } |
2192 | ||
2193 | out: | |
2194 | spin_unlock_bh(&efx->phy_lock); | |
68e7f45e | 2195 | return rc; |
8ceee660 BH |
2196 | } |
2197 | ||
26deba50 SH |
2198 | static void falcon_clock_mac(struct efx_nic *efx) |
2199 | { | |
2200 | unsigned strap_val; | |
2201 | efx_oword_t nic_stat; | |
2202 | ||
2203 | /* Configure the NIC generated MAC clock correctly */ | |
2204 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
2205 | strap_val = EFX_IS10G(efx) ? 5 : 3; | |
2206 | if (falcon_rev(efx) >= FALCON_REV_B0) { | |
2207 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP_EN, 1); | |
2208 | EFX_SET_OWORD_FIELD(nic_stat, FRF_BB_EE_STRAP, strap_val); | |
2209 | efx_writeo(efx, &nic_stat, FR_AB_NIC_STAT); | |
2210 | } else { | |
2211 | /* Falcon A1 does not support 1G/10G speed switching | |
2212 | * and must not be used with a PHY that does. */ | |
2213 | BUG_ON(EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_PINS) != | |
2214 | strap_val); | |
2215 | } | |
2216 | } | |
2217 | ||
177dfcd8 BH |
2218 | int falcon_switch_mac(struct efx_nic *efx) |
2219 | { | |
2220 | struct efx_mac_operations *old_mac_op = efx->mac_op; | |
55edc6e6 BH |
2221 | struct falcon_nic_data *nic_data = efx->nic_data; |
2222 | unsigned int stats_done_offset; | |
1974cc20 BH |
2223 | int rc = 0; |
2224 | ||
2225 | /* Don't try to fetch MAC stats while we're switching MACs */ | |
55edc6e6 | 2226 | falcon_stop_nic_stats(efx); |
177dfcd8 BH |
2227 | |
2228 | /* Internal loopbacks override the phy speed setting */ | |
2229 | if (efx->loopback_mode == LOOPBACK_GMAC) { | |
eb50c0d6 BH |
2230 | efx->link_state.speed = 1000; |
2231 | efx->link_state.fd = true; | |
177dfcd8 | 2232 | } else if (LOOPBACK_INTERNAL(efx)) { |
eb50c0d6 BH |
2233 | efx->link_state.speed = 10000; |
2234 | efx->link_state.fd = true; | |
177dfcd8 BH |
2235 | } |
2236 | ||
0cc12838 | 2237 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
177dfcd8 BH |
2238 | efx->mac_op = (EFX_IS10G(efx) ? |
2239 | &falcon_xmac_operations : &falcon_gmac_operations); | |
177dfcd8 | 2240 | |
55edc6e6 BH |
2241 | if (EFX_IS10G(efx)) |
2242 | stats_done_offset = XgDmaDone_offset; | |
2243 | else | |
2244 | stats_done_offset = GDmaDone_offset; | |
2245 | nic_data->stats_dma_done = efx->stats_buffer.addr + stats_done_offset; | |
2246 | ||
0cc12838 | 2247 | if (old_mac_op == efx->mac_op) |
1974cc20 | 2248 | goto out; |
177dfcd8 | 2249 | |
26deba50 SH |
2250 | falcon_clock_mac(efx); |
2251 | ||
177dfcd8 | 2252 | EFX_LOG(efx, "selected %cMAC\n", EFX_IS10G(efx) ? 'X' : 'G'); |
0cc12838 | 2253 | /* Not all macs support a mac-level link state */ |
9007b9fa | 2254 | efx->xmac_poll_required = false; |
0cc12838 | 2255 | |
1974cc20 BH |
2256 | rc = falcon_reset_macs(efx); |
2257 | out: | |
55edc6e6 | 2258 | falcon_start_nic_stats(efx); |
1974cc20 | 2259 | return rc; |
177dfcd8 BH |
2260 | } |
2261 | ||
8ceee660 BH |
2262 | /* This call is responsible for hooking in the MAC and PHY operations */ |
2263 | int falcon_probe_port(struct efx_nic *efx) | |
2264 | { | |
2265 | int rc; | |
2266 | ||
96c45726 BH |
2267 | switch (efx->phy_type) { |
2268 | case PHY_TYPE_SFX7101: | |
2269 | efx->phy_op = &falcon_sfx7101_phy_ops; | |
2270 | break; | |
2271 | case PHY_TYPE_SFT9001A: | |
2272 | case PHY_TYPE_SFT9001B: | |
2273 | efx->phy_op = &falcon_sft9001_phy_ops; | |
2274 | break; | |
2275 | case PHY_TYPE_QT2022C2: | |
2276 | case PHY_TYPE_QT2025C: | |
b37b62fe | 2277 | efx->phy_op = &falcon_qt202x_phy_ops; |
96c45726 BH |
2278 | break; |
2279 | default: | |
2280 | EFX_ERR(efx, "Unknown PHY type %d\n", | |
2281 | efx->phy_type); | |
2282 | return -ENODEV; | |
2283 | } | |
2284 | ||
2285 | if (efx->phy_op->macs & EFX_XMAC) | |
2286 | efx->loopback_modes |= ((1 << LOOPBACK_XGMII) | | |
2287 | (1 << LOOPBACK_XGXS) | | |
2288 | (1 << LOOPBACK_XAUI)); | |
2289 | if (efx->phy_op->macs & EFX_GMAC) | |
2290 | efx->loopback_modes |= (1 << LOOPBACK_GMAC); | |
2291 | efx->loopback_modes |= efx->phy_op->loopbacks; | |
8ceee660 | 2292 | |
68e7f45e BH |
2293 | /* Set up MDIO structure for PHY */ |
2294 | efx->mdio.mmds = efx->phy_op->mmds; | |
2295 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
2296 | efx->mdio.mdio_read = falcon_mdio_read; | |
2297 | efx->mdio.mdio_write = falcon_mdio_write; | |
8ceee660 BH |
2298 | |
2299 | /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */ | |
55668611 | 2300 | if (falcon_rev(efx) >= FALCON_REV_B0) |
04cc8cac | 2301 | efx->wanted_fc = EFX_FC_RX | EFX_FC_TX; |
8ceee660 | 2302 | else |
04cc8cac | 2303 | efx->wanted_fc = EFX_FC_RX; |
8ceee660 BH |
2304 | |
2305 | /* Allocate buffer for stats */ | |
2306 | rc = falcon_alloc_buffer(efx, &efx->stats_buffer, | |
2307 | FALCON_MAC_STATS_SIZE); | |
2308 | if (rc) | |
2309 | return rc; | |
9c8976a1 JSR |
2310 | EFX_LOG(efx, "stats buffer at %llx (virt %p phys %llx)\n", |
2311 | (u64)efx->stats_buffer.dma_addr, | |
8ceee660 | 2312 | efx->stats_buffer.addr, |
9c8976a1 | 2313 | (u64)virt_to_phys(efx->stats_buffer.addr)); |
8ceee660 BH |
2314 | |
2315 | return 0; | |
2316 | } | |
2317 | ||
2318 | void falcon_remove_port(struct efx_nic *efx) | |
2319 | { | |
2320 | falcon_free_buffer(efx, &efx->stats_buffer); | |
2321 | } | |
2322 | ||
2323 | /************************************************************************** | |
2324 | * | |
2325 | * Multicast filtering | |
2326 | * | |
2327 | ************************************************************************** | |
2328 | */ | |
2329 | ||
8be4f3e6 | 2330 | void falcon_push_multicast_hash(struct efx_nic *efx) |
8ceee660 BH |
2331 | { |
2332 | union efx_multicast_hash *mc_hash = &efx->multicast_hash; | |
2333 | ||
8be4f3e6 | 2334 | WARN_ON(!mutex_is_locked(&efx->mac_lock)); |
8ceee660 | 2335 | |
12d00cad BH |
2336 | efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0); |
2337 | efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1); | |
8ceee660 BH |
2338 | } |
2339 | ||
8c8661e4 BH |
2340 | |
2341 | /************************************************************************** | |
2342 | * | |
2343 | * Falcon test code | |
2344 | * | |
2345 | **************************************************************************/ | |
2346 | ||
2347 | int falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out) | |
2348 | { | |
2349 | struct falcon_nvconfig *nvconfig; | |
2350 | struct efx_spi_device *spi; | |
2351 | void *region; | |
2352 | int rc, magic_num, struct_ver; | |
2353 | __le16 *word, *limit; | |
2354 | u32 csum; | |
2355 | ||
2f7f5730 BH |
2356 | spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom; |
2357 | if (!spi) | |
2358 | return -EINVAL; | |
2359 | ||
0a95f563 | 2360 | region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL); |
8c8661e4 BH |
2361 | if (!region) |
2362 | return -ENOMEM; | |
3e6c4538 | 2363 | nvconfig = region + FALCON_NVCONFIG_OFFSET; |
8c8661e4 | 2364 | |
f4150724 | 2365 | mutex_lock(&efx->spi_lock); |
0a95f563 | 2366 | rc = falcon_spi_read(spi, 0, FALCON_NVCONFIG_END, NULL, region); |
f4150724 | 2367 | mutex_unlock(&efx->spi_lock); |
8c8661e4 BH |
2368 | if (rc) { |
2369 | EFX_ERR(efx, "Failed to read %s\n", | |
2370 | efx->spi_flash ? "flash" : "EEPROM"); | |
2371 | rc = -EIO; | |
2372 | goto out; | |
2373 | } | |
2374 | ||
2375 | magic_num = le16_to_cpu(nvconfig->board_magic_num); | |
2376 | struct_ver = le16_to_cpu(nvconfig->board_struct_ver); | |
2377 | ||
2378 | rc = -EINVAL; | |
3e6c4538 | 2379 | if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) { |
8c8661e4 BH |
2380 | EFX_ERR(efx, "NVRAM bad magic 0x%x\n", magic_num); |
2381 | goto out; | |
2382 | } | |
2383 | if (struct_ver < 2) { | |
2384 | EFX_ERR(efx, "NVRAM has ancient version 0x%x\n", struct_ver); | |
2385 | goto out; | |
2386 | } else if (struct_ver < 4) { | |
2387 | word = &nvconfig->board_magic_num; | |
2388 | limit = (__le16 *) (nvconfig + 1); | |
2389 | } else { | |
2390 | word = region; | |
0a95f563 | 2391 | limit = region + FALCON_NVCONFIG_END; |
8c8661e4 BH |
2392 | } |
2393 | for (csum = 0; word < limit; ++word) | |
2394 | csum += le16_to_cpu(*word); | |
2395 | ||
2396 | if (~csum & 0xffff) { | |
2397 | EFX_ERR(efx, "NVRAM has incorrect checksum\n"); | |
2398 | goto out; | |
2399 | } | |
2400 | ||
2401 | rc = 0; | |
2402 | if (nvconfig_out) | |
2403 | memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig)); | |
2404 | ||
2405 | out: | |
2406 | kfree(region); | |
2407 | return rc; | |
2408 | } | |
2409 | ||
2410 | /* Registers tested in the falcon register test */ | |
2411 | static struct { | |
2412 | unsigned address; | |
2413 | efx_oword_t mask; | |
2414 | } efx_test_registers[] = { | |
3e6c4538 | 2415 | { FR_AZ_ADR_REGION, |
8c8661e4 | 2416 | EFX_OWORD32(0x0001FFFF, 0x0001FFFF, 0x0001FFFF, 0x0001FFFF) }, |
3e6c4538 | 2417 | { FR_AZ_RX_CFG, |
8c8661e4 | 2418 | EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) }, |
3e6c4538 | 2419 | { FR_AZ_TX_CFG, |
8c8661e4 | 2420 | EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2421 | { FR_AZ_TX_RESERVED, |
8c8661e4 | 2422 | EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) }, |
3e6c4538 | 2423 | { FR_AB_MAC_CTRL, |
8c8661e4 | 2424 | EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2425 | { FR_AZ_SRM_TX_DC_CFG, |
8c8661e4 | 2426 | EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2427 | { FR_AZ_RX_DC_CFG, |
8c8661e4 | 2428 | EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2429 | { FR_AZ_RX_DC_PF_WM, |
8c8661e4 | 2430 | EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2431 | { FR_BZ_DP_CTRL, |
8c8661e4 | 2432 | EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2433 | { FR_AB_GM_CFG2, |
177dfcd8 | 2434 | EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2435 | { FR_AB_GMF_CFG0, |
177dfcd8 | 2436 | EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2437 | { FR_AB_XM_GLB_CFG, |
8c8661e4 | 2438 | EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2439 | { FR_AB_XM_TX_CFG, |
8c8661e4 | 2440 | EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2441 | { FR_AB_XM_RX_CFG, |
8c8661e4 | 2442 | EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2443 | { FR_AB_XM_RX_PARAM, |
8c8661e4 | 2444 | EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2445 | { FR_AB_XM_FC, |
8c8661e4 | 2446 | EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2447 | { FR_AB_XM_ADR_LO, |
8c8661e4 | 2448 | EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) }, |
3e6c4538 | 2449 | { FR_AB_XX_SD_CTL, |
8c8661e4 BH |
2450 | EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) }, |
2451 | }; | |
2452 | ||
2453 | static bool efx_masked_compare_oword(const efx_oword_t *a, const efx_oword_t *b, | |
2454 | const efx_oword_t *mask) | |
2455 | { | |
2456 | return ((a->u64[0] ^ b->u64[0]) & mask->u64[0]) || | |
2457 | ((a->u64[1] ^ b->u64[1]) & mask->u64[1]); | |
2458 | } | |
2459 | ||
2460 | int falcon_test_registers(struct efx_nic *efx) | |
2461 | { | |
2462 | unsigned address = 0, i, j; | |
2463 | efx_oword_t mask, imask, original, reg, buf; | |
2464 | ||
2465 | /* Falcon should be in loopback to isolate the XMAC from the PHY */ | |
2466 | WARN_ON(!LOOPBACK_INTERNAL(efx)); | |
2467 | ||
2468 | for (i = 0; i < ARRAY_SIZE(efx_test_registers); ++i) { | |
2469 | address = efx_test_registers[i].address; | |
2470 | mask = imask = efx_test_registers[i].mask; | |
2471 | EFX_INVERT_OWORD(imask); | |
2472 | ||
12d00cad | 2473 | efx_reado(efx, &original, address); |
8c8661e4 BH |
2474 | |
2475 | /* bit sweep on and off */ | |
2476 | for (j = 0; j < 128; j++) { | |
2477 | if (!EFX_EXTRACT_OWORD32(mask, j, j)) | |
2478 | continue; | |
2479 | ||
2480 | /* Test this testable bit can be set in isolation */ | |
2481 | EFX_AND_OWORD(reg, original, mask); | |
2482 | EFX_SET_OWORD32(reg, j, j, 1); | |
2483 | ||
12d00cad BH |
2484 | efx_writeo(efx, ®, address); |
2485 | efx_reado(efx, &buf, address); | |
8c8661e4 BH |
2486 | |
2487 | if (efx_masked_compare_oword(®, &buf, &mask)) | |
2488 | goto fail; | |
2489 | ||
2490 | /* Test this testable bit can be cleared in isolation */ | |
2491 | EFX_OR_OWORD(reg, original, mask); | |
2492 | EFX_SET_OWORD32(reg, j, j, 0); | |
2493 | ||
12d00cad BH |
2494 | efx_writeo(efx, ®, address); |
2495 | efx_reado(efx, &buf, address); | |
8c8661e4 BH |
2496 | |
2497 | if (efx_masked_compare_oword(®, &buf, &mask)) | |
2498 | goto fail; | |
2499 | } | |
2500 | ||
12d00cad | 2501 | efx_writeo(efx, &original, address); |
8c8661e4 BH |
2502 | } |
2503 | ||
2504 | return 0; | |
2505 | ||
2506 | fail: | |
2507 | EFX_ERR(efx, "wrote "EFX_OWORD_FMT" read "EFX_OWORD_FMT | |
2508 | " at address 0x%x mask "EFX_OWORD_FMT"\n", EFX_OWORD_VAL(reg), | |
2509 | EFX_OWORD_VAL(buf), address, EFX_OWORD_VAL(mask)); | |
2510 | return -EIO; | |
2511 | } | |
2512 | ||
8ceee660 BH |
2513 | /************************************************************************** |
2514 | * | |
2515 | * Device reset | |
2516 | * | |
2517 | ************************************************************************** | |
2518 | */ | |
2519 | ||
2520 | /* Resets NIC to known state. This routine must be called in process | |
2521 | * context and is allowed to sleep. */ | |
2522 | int falcon_reset_hw(struct efx_nic *efx, enum reset_type method) | |
2523 | { | |
2524 | struct falcon_nic_data *nic_data = efx->nic_data; | |
2525 | efx_oword_t glb_ctl_reg_ker; | |
2526 | int rc; | |
2527 | ||
c459302d | 2528 | EFX_LOG(efx, "performing %s hardware reset\n", RESET_TYPE(method)); |
8ceee660 BH |
2529 | |
2530 | /* Initiate device reset */ | |
2531 | if (method == RESET_TYPE_WORLD) { | |
2532 | rc = pci_save_state(efx->pci_dev); | |
2533 | if (rc) { | |
2534 | EFX_ERR(efx, "failed to backup PCI state of primary " | |
2535 | "function prior to hardware reset\n"); | |
2536 | goto fail1; | |
2537 | } | |
2538 | if (FALCON_IS_DUAL_FUNC(efx)) { | |
2539 | rc = pci_save_state(nic_data->pci_dev2); | |
2540 | if (rc) { | |
2541 | EFX_ERR(efx, "failed to backup PCI state of " | |
2542 | "secondary function prior to " | |
2543 | "hardware reset\n"); | |
2544 | goto fail2; | |
2545 | } | |
2546 | } | |
2547 | ||
2548 | EFX_POPULATE_OWORD_2(glb_ctl_reg_ker, | |
3e6c4538 BH |
2549 | FRF_AB_EXT_PHY_RST_DUR, |
2550 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
2551 | FRF_AB_SWRST, 1); | |
8ceee660 | 2552 | } else { |
8ceee660 | 2553 | EFX_POPULATE_OWORD_7(glb_ctl_reg_ker, |
3e6c4538 BH |
2554 | /* exclude PHY from "invisible" reset */ |
2555 | FRF_AB_EXT_PHY_RST_CTL, | |
2556 | method == RESET_TYPE_INVISIBLE, | |
2557 | /* exclude EEPROM/flash and PCIe */ | |
2558 | FRF_AB_PCIE_CORE_RST_CTL, 1, | |
2559 | FRF_AB_PCIE_NSTKY_RST_CTL, 1, | |
2560 | FRF_AB_PCIE_SD_RST_CTL, 1, | |
2561 | FRF_AB_EE_RST_CTL, 1, | |
2562 | FRF_AB_EXT_PHY_RST_DUR, | |
2563 | FFE_AB_EXT_PHY_RST_DUR_10240US, | |
2564 | FRF_AB_SWRST, 1); | |
2565 | } | |
12d00cad | 2566 | efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
8ceee660 BH |
2567 | |
2568 | EFX_LOG(efx, "waiting for hardware reset\n"); | |
2569 | schedule_timeout_uninterruptible(HZ / 20); | |
2570 | ||
2571 | /* Restore PCI configuration if needed */ | |
2572 | if (method == RESET_TYPE_WORLD) { | |
2573 | if (FALCON_IS_DUAL_FUNC(efx)) { | |
2574 | rc = pci_restore_state(nic_data->pci_dev2); | |
2575 | if (rc) { | |
2576 | EFX_ERR(efx, "failed to restore PCI config for " | |
2577 | "the secondary function\n"); | |
2578 | goto fail3; | |
2579 | } | |
2580 | } | |
2581 | rc = pci_restore_state(efx->pci_dev); | |
2582 | if (rc) { | |
2583 | EFX_ERR(efx, "failed to restore PCI config for the " | |
2584 | "primary function\n"); | |
2585 | goto fail4; | |
2586 | } | |
2587 | EFX_LOG(efx, "successfully restored PCI config\n"); | |
2588 | } | |
2589 | ||
2590 | /* Assert that reset complete */ | |
12d00cad | 2591 | efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL); |
3e6c4538 | 2592 | if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) { |
8ceee660 BH |
2593 | rc = -ETIMEDOUT; |
2594 | EFX_ERR(efx, "timed out waiting for hardware reset\n"); | |
2595 | goto fail5; | |
2596 | } | |
2597 | EFX_LOG(efx, "hardware reset complete\n"); | |
2598 | ||
2599 | return 0; | |
2600 | ||
2601 | /* pci_save_state() and pci_restore_state() MUST be called in pairs */ | |
2602 | fail2: | |
2603 | fail3: | |
2604 | pci_restore_state(efx->pci_dev); | |
2605 | fail1: | |
2606 | fail4: | |
2607 | fail5: | |
2608 | return rc; | |
2609 | } | |
2610 | ||
fe75820b BH |
2611 | void falcon_monitor(struct efx_nic *efx) |
2612 | { | |
2613 | int rc; | |
2614 | ||
2615 | rc = falcon_board(efx)->type->monitor(efx); | |
2616 | if (rc) { | |
2617 | EFX_ERR(efx, "Board sensor %s; shutting down PHY\n", | |
2618 | (rc == -ERANGE) ? "reported fault" : "failed"); | |
2619 | efx->phy_mode |= PHY_MODE_LOW_POWER; | |
2620 | falcon_sim_phy_event(efx); | |
2621 | } | |
2622 | efx->phy_op->poll(efx); | |
9007b9fa BH |
2623 | if (EFX_IS10G(efx)) |
2624 | falcon_poll_xmac(efx); | |
fe75820b BH |
2625 | } |
2626 | ||
8ceee660 BH |
2627 | /* Zeroes out the SRAM contents. This routine must be called in |
2628 | * process context and is allowed to sleep. | |
2629 | */ | |
2630 | static int falcon_reset_sram(struct efx_nic *efx) | |
2631 | { | |
2632 | efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker; | |
2633 | int count; | |
2634 | ||
2635 | /* Set the SRAM wake/sleep GPIO appropriately. */ | |
12d00cad | 2636 | efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
3e6c4538 BH |
2637 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1); |
2638 | EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1); | |
12d00cad | 2639 | efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL); |
8ceee660 BH |
2640 | |
2641 | /* Initiate SRAM reset */ | |
2642 | EFX_POPULATE_OWORD_2(srm_cfg_reg_ker, | |
3e6c4538 BH |
2643 | FRF_AZ_SRM_INIT_EN, 1, |
2644 | FRF_AZ_SRM_NB_SZ, 0); | |
12d00cad | 2645 | efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
8ceee660 BH |
2646 | |
2647 | /* Wait for SRAM reset to complete */ | |
2648 | count = 0; | |
2649 | do { | |
2650 | EFX_LOG(efx, "waiting for SRAM reset (attempt %d)...\n", count); | |
2651 | ||
2652 | /* SRAM reset is slow; expect around 16ms */ | |
2653 | schedule_timeout_uninterruptible(HZ / 50); | |
2654 | ||
2655 | /* Check for reset complete */ | |
12d00cad | 2656 | efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG); |
3e6c4538 | 2657 | if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) { |
8ceee660 BH |
2658 | EFX_LOG(efx, "SRAM reset complete\n"); |
2659 | ||
2660 | return 0; | |
2661 | } | |
2662 | } while (++count < 20); /* wait upto 0.4 sec */ | |
2663 | ||
2664 | EFX_ERR(efx, "timed out waiting for SRAM reset\n"); | |
2665 | return -ETIMEDOUT; | |
2666 | } | |
2667 | ||
4a5b504d BH |
2668 | static int falcon_spi_device_init(struct efx_nic *efx, |
2669 | struct efx_spi_device **spi_device_ret, | |
2670 | unsigned int device_id, u32 device_type) | |
2671 | { | |
2672 | struct efx_spi_device *spi_device; | |
2673 | ||
2674 | if (device_type != 0) { | |
0c53d8c8 | 2675 | spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL); |
4a5b504d BH |
2676 | if (!spi_device) |
2677 | return -ENOMEM; | |
2678 | spi_device->device_id = device_id; | |
2679 | spi_device->size = | |
2680 | 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE); | |
2681 | spi_device->addr_len = | |
2682 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN); | |
2683 | spi_device->munge_address = (spi_device->size == 1 << 9 && | |
2684 | spi_device->addr_len == 1); | |
f4150724 BH |
2685 | spi_device->erase_command = |
2686 | SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD); | |
2687 | spi_device->erase_size = | |
2688 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
2689 | SPI_DEV_TYPE_ERASE_SIZE); | |
4a5b504d BH |
2690 | spi_device->block_size = |
2691 | 1 << SPI_DEV_TYPE_FIELD(device_type, | |
2692 | SPI_DEV_TYPE_BLOCK_SIZE); | |
2693 | ||
2694 | spi_device->efx = efx; | |
2695 | } else { | |
2696 | spi_device = NULL; | |
2697 | } | |
2698 | ||
2699 | kfree(*spi_device_ret); | |
2700 | *spi_device_ret = spi_device; | |
2701 | return 0; | |
2702 | } | |
2703 | ||
2704 | ||
2705 | static void falcon_remove_spi_devices(struct efx_nic *efx) | |
2706 | { | |
2707 | kfree(efx->spi_eeprom); | |
2708 | efx->spi_eeprom = NULL; | |
2709 | kfree(efx->spi_flash); | |
2710 | efx->spi_flash = NULL; | |
2711 | } | |
2712 | ||
8ceee660 BH |
2713 | /* Extract non-volatile configuration */ |
2714 | static int falcon_probe_nvconfig(struct efx_nic *efx) | |
2715 | { | |
2716 | struct falcon_nvconfig *nvconfig; | |
8c8661e4 | 2717 | int board_rev; |
8ceee660 BH |
2718 | int rc; |
2719 | ||
8ceee660 | 2720 | nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL); |
4a5b504d BH |
2721 | if (!nvconfig) |
2722 | return -ENOMEM; | |
8ceee660 | 2723 | |
8c8661e4 BH |
2724 | rc = falcon_read_nvram(efx, nvconfig); |
2725 | if (rc == -EINVAL) { | |
2726 | EFX_ERR(efx, "NVRAM is invalid therefore using defaults\n"); | |
8ceee660 | 2727 | efx->phy_type = PHY_TYPE_NONE; |
68e7f45e | 2728 | efx->mdio.prtad = MDIO_PRTAD_NONE; |
8ceee660 | 2729 | board_rev = 0; |
8c8661e4 BH |
2730 | rc = 0; |
2731 | } else if (rc) { | |
2732 | goto fail1; | |
8ceee660 BH |
2733 | } else { |
2734 | struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2; | |
4a5b504d | 2735 | struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3; |
8ceee660 BH |
2736 | |
2737 | efx->phy_type = v2->port0_phy_type; | |
68e7f45e | 2738 | efx->mdio.prtad = v2->port0_phy_addr; |
8ceee660 | 2739 | board_rev = le16_to_cpu(v2->board_revision); |
4a5b504d | 2740 | |
8c8661e4 | 2741 | if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) { |
3e6c4538 BH |
2742 | rc = falcon_spi_device_init( |
2743 | efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH, | |
2744 | le32_to_cpu(v3->spi_device_type | |
2745 | [FFE_AB_SPI_DEVICE_FLASH])); | |
4a5b504d BH |
2746 | if (rc) |
2747 | goto fail2; | |
3e6c4538 BH |
2748 | rc = falcon_spi_device_init( |
2749 | efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM, | |
2750 | le32_to_cpu(v3->spi_device_type | |
2751 | [FFE_AB_SPI_DEVICE_EEPROM])); | |
4a5b504d BH |
2752 | if (rc) |
2753 | goto fail2; | |
2754 | } | |
8ceee660 BH |
2755 | } |
2756 | ||
8c8661e4 BH |
2757 | /* Read the MAC addresses */ |
2758 | memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN); | |
2759 | ||
68e7f45e | 2760 | EFX_LOG(efx, "PHY is %d phy_id %d\n", efx->phy_type, efx->mdio.prtad); |
8ceee660 | 2761 | |
3473a5b1 | 2762 | falcon_probe_board(efx, board_rev); |
8ceee660 | 2763 | |
4a5b504d BH |
2764 | kfree(nvconfig); |
2765 | return 0; | |
2766 | ||
2767 | fail2: | |
2768 | falcon_remove_spi_devices(efx); | |
2769 | fail1: | |
8ceee660 BH |
2770 | kfree(nvconfig); |
2771 | return rc; | |
2772 | } | |
2773 | ||
2774 | /* Probe the NIC variant (revision, ASIC vs FPGA, function count, port | |
2775 | * count, port speed). Set workaround and feature flags accordingly. | |
2776 | */ | |
2777 | static int falcon_probe_nic_variant(struct efx_nic *efx) | |
2778 | { | |
2779 | efx_oword_t altera_build; | |
177dfcd8 | 2780 | efx_oword_t nic_stat; |
8ceee660 | 2781 | |
12d00cad | 2782 | efx_reado(efx, &altera_build, FR_AZ_ALTERA_BUILD); |
3e6c4538 | 2783 | if (EFX_OWORD_FIELD(altera_build, FRF_AZ_ALTERA_BUILD_VER)) { |
8ceee660 BH |
2784 | EFX_ERR(efx, "Falcon FPGA not supported\n"); |
2785 | return -ENODEV; | |
2786 | } | |
2787 | ||
12d00cad | 2788 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); |
177dfcd8 | 2789 | |
55668611 | 2790 | switch (falcon_rev(efx)) { |
8ceee660 BH |
2791 | case FALCON_REV_A0: |
2792 | case 0xff: | |
2793 | EFX_ERR(efx, "Falcon rev A0 not supported\n"); | |
2794 | return -ENODEV; | |
2795 | ||
177dfcd8 | 2796 | case FALCON_REV_A1: |
3e6c4538 | 2797 | if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) { |
8ceee660 BH |
2798 | EFX_ERR(efx, "Falcon rev A1 PCI-X not supported\n"); |
2799 | return -ENODEV; | |
2800 | } | |
8ceee660 | 2801 | break; |
8ceee660 BH |
2802 | |
2803 | case FALCON_REV_B0: | |
2804 | break; | |
2805 | ||
2806 | default: | |
55668611 | 2807 | EFX_ERR(efx, "Unknown Falcon rev %d\n", falcon_rev(efx)); |
8ceee660 BH |
2808 | return -ENODEV; |
2809 | } | |
2810 | ||
177dfcd8 | 2811 | /* Initial assumed speed */ |
eb50c0d6 | 2812 | efx->link_state.speed = EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) ? 10000 : 1000; |
177dfcd8 | 2813 | |
8ceee660 BH |
2814 | return 0; |
2815 | } | |
2816 | ||
4a5b504d BH |
2817 | /* Probe all SPI devices on the NIC */ |
2818 | static void falcon_probe_spi_devices(struct efx_nic *efx) | |
2819 | { | |
2820 | efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg; | |
2f7f5730 | 2821 | int boot_dev; |
4a5b504d | 2822 | |
12d00cad BH |
2823 | efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL); |
2824 | efx_reado(efx, &nic_stat, FR_AB_NIC_STAT); | |
2825 | efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); | |
4a5b504d | 2826 | |
3e6c4538 BH |
2827 | if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) { |
2828 | boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ? | |
2829 | FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM); | |
2f7f5730 | 2830 | EFX_LOG(efx, "Booted from %s\n", |
3e6c4538 | 2831 | boot_dev == FFE_AB_SPI_DEVICE_FLASH ? "flash" : "EEPROM"); |
2f7f5730 BH |
2832 | } else { |
2833 | /* Disable VPD and set clock dividers to safe | |
2834 | * values for initial programming. */ | |
2835 | boot_dev = -1; | |
2836 | EFX_LOG(efx, "Booted from internal ASIC settings;" | |
2837 | " setting SPI config\n"); | |
3e6c4538 | 2838 | EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0, |
2f7f5730 | 2839 | /* 125 MHz / 7 ~= 20 MHz */ |
3e6c4538 | 2840 | FRF_AB_EE_SF_CLOCK_DIV, 7, |
2f7f5730 | 2841 | /* 125 MHz / 63 ~= 2 MHz */ |
3e6c4538 | 2842 | FRF_AB_EE_EE_CLOCK_DIV, 63); |
12d00cad | 2843 | efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0); |
4a5b504d BH |
2844 | } |
2845 | ||
3e6c4538 BH |
2846 | if (boot_dev == FFE_AB_SPI_DEVICE_FLASH) |
2847 | falcon_spi_device_init(efx, &efx->spi_flash, | |
2848 | FFE_AB_SPI_DEVICE_FLASH, | |
2f7f5730 | 2849 | default_flash_type); |
3e6c4538 BH |
2850 | if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM) |
2851 | falcon_spi_device_init(efx, &efx->spi_eeprom, | |
2852 | FFE_AB_SPI_DEVICE_EEPROM, | |
2f7f5730 | 2853 | large_eeprom_type); |
4a5b504d BH |
2854 | } |
2855 | ||
8ceee660 BH |
2856 | int falcon_probe_nic(struct efx_nic *efx) |
2857 | { | |
2858 | struct falcon_nic_data *nic_data; | |
e775fb93 | 2859 | struct falcon_board *board; |
8ceee660 BH |
2860 | int rc; |
2861 | ||
8ceee660 BH |
2862 | /* Allocate storage for hardware specific data */ |
2863 | nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL); | |
88c59425 BH |
2864 | if (!nic_data) |
2865 | return -ENOMEM; | |
5daab96d | 2866 | efx->nic_data = nic_data; |
8ceee660 BH |
2867 | |
2868 | /* Determine number of ports etc. */ | |
2869 | rc = falcon_probe_nic_variant(efx); | |
2870 | if (rc) | |
2871 | goto fail1; | |
2872 | ||
2873 | /* Probe secondary function if expected */ | |
2874 | if (FALCON_IS_DUAL_FUNC(efx)) { | |
2875 | struct pci_dev *dev = pci_dev_get(efx->pci_dev); | |
2876 | ||
2877 | while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID, | |
2878 | dev))) { | |
2879 | if (dev->bus == efx->pci_dev->bus && | |
2880 | dev->devfn == efx->pci_dev->devfn + 1) { | |
2881 | nic_data->pci_dev2 = dev; | |
2882 | break; | |
2883 | } | |
2884 | } | |
2885 | if (!nic_data->pci_dev2) { | |
2886 | EFX_ERR(efx, "failed to find secondary function\n"); | |
2887 | rc = -ENODEV; | |
2888 | goto fail2; | |
2889 | } | |
2890 | } | |
2891 | ||
2892 | /* Now we can reset the NIC */ | |
2893 | rc = falcon_reset_hw(efx, RESET_TYPE_ALL); | |
2894 | if (rc) { | |
2895 | EFX_ERR(efx, "failed to reset NIC\n"); | |
2896 | goto fail3; | |
2897 | } | |
2898 | ||
2899 | /* Allocate memory for INT_KER */ | |
2900 | rc = falcon_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t)); | |
2901 | if (rc) | |
2902 | goto fail4; | |
2903 | BUG_ON(efx->irq_status.dma_addr & 0x0f); | |
2904 | ||
9c8976a1 JSR |
2905 | EFX_LOG(efx, "INT_KER at %llx (virt %p phys %llx)\n", |
2906 | (u64)efx->irq_status.dma_addr, | |
2907 | efx->irq_status.addr, (u64)virt_to_phys(efx->irq_status.addr)); | |
8ceee660 | 2908 | |
4a5b504d BH |
2909 | falcon_probe_spi_devices(efx); |
2910 | ||
8ceee660 BH |
2911 | /* Read in the non-volatile configuration */ |
2912 | rc = falcon_probe_nvconfig(efx); | |
2913 | if (rc) | |
2914 | goto fail5; | |
2915 | ||
37b5a603 | 2916 | /* Initialise I2C adapter */ |
e775fb93 BH |
2917 | board = falcon_board(efx); |
2918 | board->i2c_adap.owner = THIS_MODULE; | |
2919 | board->i2c_data = falcon_i2c_bit_operations; | |
2920 | board->i2c_data.data = efx; | |
2921 | board->i2c_adap.algo_data = &board->i2c_data; | |
2922 | board->i2c_adap.dev.parent = &efx->pci_dev->dev; | |
2923 | strlcpy(board->i2c_adap.name, "SFC4000 GPIO", | |
2924 | sizeof(board->i2c_adap.name)); | |
2925 | rc = i2c_bit_add_bus(&board->i2c_adap); | |
37b5a603 BH |
2926 | if (rc) |
2927 | goto fail5; | |
2928 | ||
44838a44 | 2929 | rc = falcon_board(efx)->type->init(efx); |
278c0621 BH |
2930 | if (rc) { |
2931 | EFX_ERR(efx, "failed to initialise board\n"); | |
2932 | goto fail6; | |
2933 | } | |
2934 | ||
55edc6e6 BH |
2935 | nic_data->stats_disable_count = 1; |
2936 | setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func, | |
2937 | (unsigned long)efx); | |
2938 | ||
8ceee660 BH |
2939 | return 0; |
2940 | ||
278c0621 | 2941 | fail6: |
e775fb93 BH |
2942 | BUG_ON(i2c_del_adapter(&board->i2c_adap)); |
2943 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); | |
8ceee660 | 2944 | fail5: |
4a5b504d | 2945 | falcon_remove_spi_devices(efx); |
8ceee660 BH |
2946 | falcon_free_buffer(efx, &efx->irq_status); |
2947 | fail4: | |
8ceee660 BH |
2948 | fail3: |
2949 | if (nic_data->pci_dev2) { | |
2950 | pci_dev_put(nic_data->pci_dev2); | |
2951 | nic_data->pci_dev2 = NULL; | |
2952 | } | |
2953 | fail2: | |
8ceee660 BH |
2954 | fail1: |
2955 | kfree(efx->nic_data); | |
2956 | return rc; | |
2957 | } | |
2958 | ||
56241ceb BH |
2959 | static void falcon_init_rx_cfg(struct efx_nic *efx) |
2960 | { | |
2961 | /* Prior to Siena the RX DMA engine will split each frame at | |
2962 | * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to | |
2963 | * be so large that that never happens. */ | |
2964 | const unsigned huge_buf_size = (3 * 4096) >> 5; | |
2965 | /* RX control FIFO thresholds (32 entries) */ | |
2966 | const unsigned ctrl_xon_thr = 20; | |
2967 | const unsigned ctrl_xoff_thr = 25; | |
2968 | /* RX data FIFO thresholds (256-byte units; size varies) */ | |
625b4514 BH |
2969 | int data_xon_thr = rx_xon_thresh_bytes >> 8; |
2970 | int data_xoff_thr = rx_xoff_thresh_bytes >> 8; | |
56241ceb BH |
2971 | efx_oword_t reg; |
2972 | ||
12d00cad | 2973 | efx_reado(efx, ®, FR_AZ_RX_CFG); |
56241ceb | 2974 | if (falcon_rev(efx) <= FALCON_REV_A1) { |
625b4514 BH |
2975 | /* Data FIFO size is 5.5K */ |
2976 | if (data_xon_thr < 0) | |
2977 | data_xon_thr = 512 >> 8; | |
2978 | if (data_xoff_thr < 0) | |
2979 | data_xoff_thr = 2048 >> 8; | |
3e6c4538 BH |
2980 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0); |
2981 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE, | |
2982 | huge_buf_size); | |
2983 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr); | |
2984 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr); | |
2985 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr); | |
2986 | EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
56241ceb | 2987 | } else { |
625b4514 BH |
2988 | /* Data FIFO size is 80K; register fields moved */ |
2989 | if (data_xon_thr < 0) | |
2990 | data_xon_thr = 27648 >> 8; /* ~3*max MTU */ | |
2991 | if (data_xoff_thr < 0) | |
2992 | data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */ | |
3e6c4538 BH |
2993 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0); |
2994 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE, | |
2995 | huge_buf_size); | |
2996 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr); | |
2997 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr); | |
2998 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr); | |
2999 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr); | |
3000 | EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1); | |
56241ceb | 3001 | } |
12d00cad | 3002 | efx_writeo(efx, ®, FR_AZ_RX_CFG); |
56241ceb BH |
3003 | } |
3004 | ||
8ceee660 BH |
3005 | /* This call performs hardware-specific global initialisation, such as |
3006 | * defining the descriptor cache sizes and number of RSS channels. | |
3007 | * It does not set up any buffers, descriptor rings or event queues. | |
3008 | */ | |
3009 | int falcon_init_nic(struct efx_nic *efx) | |
3010 | { | |
8ceee660 | 3011 | efx_oword_t temp; |
8ceee660 BH |
3012 | int rc; |
3013 | ||
8ceee660 | 3014 | /* Use on-chip SRAM */ |
12d00cad | 3015 | efx_reado(efx, &temp, FR_AB_NIC_STAT); |
3e6c4538 | 3016 | EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1); |
12d00cad | 3017 | efx_writeo(efx, &temp, FR_AB_NIC_STAT); |
8ceee660 | 3018 | |
6f158d5f BH |
3019 | /* Set the source of the GMAC clock */ |
3020 | if (falcon_rev(efx) == FALCON_REV_B0) { | |
12d00cad | 3021 | efx_reado(efx, &temp, FR_AB_GPIO_CTL); |
3e6c4538 | 3022 | EFX_SET_OWORD_FIELD(temp, FRF_AB_USE_NIC_CLK, true); |
12d00cad | 3023 | efx_writeo(efx, &temp, FR_AB_GPIO_CTL); |
6f158d5f BH |
3024 | } |
3025 | ||
26deba50 SH |
3026 | /* Select the correct MAC */ |
3027 | falcon_clock_mac(efx); | |
3028 | ||
8ceee660 BH |
3029 | rc = falcon_reset_sram(efx); |
3030 | if (rc) | |
3031 | return rc; | |
3032 | ||
3033 | /* Set positions of descriptor caches in SRAM. */ | |
3e6c4538 | 3034 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8); |
12d00cad | 3035 | efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG); |
3e6c4538 | 3036 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8); |
12d00cad | 3037 | efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG); |
8ceee660 BH |
3038 | |
3039 | /* Set TX descriptor cache size. */ | |
46e1ac0f | 3040 | BUILD_BUG_ON(TX_DC_ENTRIES != (8 << TX_DC_ENTRIES_ORDER)); |
3e6c4538 | 3041 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_TX_DC_SIZE, TX_DC_ENTRIES_ORDER); |
12d00cad | 3042 | efx_writeo(efx, &temp, FR_AZ_TX_DC_CFG); |
8ceee660 BH |
3043 | |
3044 | /* Set RX descriptor cache size. Set low watermark to size-8, as | |
3045 | * this allows most efficient prefetching. | |
3046 | */ | |
46e1ac0f | 3047 | BUILD_BUG_ON(RX_DC_ENTRIES != (8 << RX_DC_ENTRIES_ORDER)); |
3e6c4538 | 3048 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_SIZE, RX_DC_ENTRIES_ORDER); |
12d00cad | 3049 | efx_writeo(efx, &temp, FR_AZ_RX_DC_CFG); |
3e6c4538 | 3050 | EFX_POPULATE_OWORD_1(temp, FRF_AZ_RX_DC_PF_LWM, RX_DC_ENTRIES - 8); |
12d00cad | 3051 | efx_writeo(efx, &temp, FR_AZ_RX_DC_PF_WM); |
8ceee660 BH |
3052 | |
3053 | /* Clear the parity enables on the TX data fifos as | |
3054 | * they produce false parity errors because of timing issues | |
3055 | */ | |
3056 | if (EFX_WORKAROUND_5129(efx)) { | |
12d00cad | 3057 | efx_reado(efx, &temp, FR_AZ_CSR_SPARE); |
3e6c4538 | 3058 | EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0); |
12d00cad | 3059 | efx_writeo(efx, &temp, FR_AZ_CSR_SPARE); |
8ceee660 BH |
3060 | } |
3061 | ||
3062 | /* Enable all the genuinely fatal interrupts. (They are still | |
3063 | * masked by the overall interrupt mask, controlled by | |
3064 | * falcon_interrupts()). | |
3065 | * | |
3066 | * Note: All other fatal interrupts are enabled | |
3067 | */ | |
3068 | EFX_POPULATE_OWORD_3(temp, | |
3e6c4538 BH |
3069 | FRF_AZ_ILL_ADR_INT_KER_EN, 1, |
3070 | FRF_AZ_RBUF_OWN_INT_KER_EN, 1, | |
3071 | FRF_AZ_TBUF_OWN_INT_KER_EN, 1); | |
8ceee660 | 3072 | EFX_INVERT_OWORD(temp); |
12d00cad | 3073 | efx_writeo(efx, &temp, FR_AZ_FATAL_INTR_KER); |
8ceee660 | 3074 | |
8ceee660 | 3075 | if (EFX_WORKAROUND_7244(efx)) { |
12d00cad | 3076 | efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL); |
3e6c4538 BH |
3077 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8); |
3078 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8); | |
3079 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8); | |
3080 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8); | |
12d00cad | 3081 | efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL); |
8ceee660 | 3082 | } |
8ceee660 BH |
3083 | |
3084 | falcon_setup_rss_indir_table(efx); | |
3085 | ||
3e6c4538 | 3086 | /* XXX This is documented only for Falcon A0/A1 */ |
8ceee660 BH |
3087 | /* Setup RX. Wait for descriptor is broken and must |
3088 | * be disabled. RXDP recovery shouldn't be needed, but is. | |
3089 | */ | |
12d00cad | 3090 | efx_reado(efx, &temp, FR_AA_RX_SELF_RST); |
3e6c4538 BH |
3091 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1); |
3092 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1); | |
8ceee660 | 3093 | if (EFX_WORKAROUND_5583(efx)) |
3e6c4538 | 3094 | EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1); |
12d00cad | 3095 | efx_writeo(efx, &temp, FR_AA_RX_SELF_RST); |
8ceee660 BH |
3096 | |
3097 | /* Disable the ugly timer-based TX DMA backoff and allow TX DMA to be | |
3098 | * controlled by the RX FIFO fill level. Set arbitration to one pkt/Q. | |
3099 | */ | |
12d00cad | 3100 | efx_reado(efx, &temp, FR_AZ_TX_RESERVED); |
3e6c4538 BH |
3101 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER, 0xfe); |
3102 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_RX_SPACER_EN, 1); | |
3103 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_ONE_PKT_PER_Q, 1); | |
3104 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PUSH_EN, 0); | |
3105 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_DIS_NON_IP_EV, 1); | |
8ceee660 | 3106 | /* Enable SW_EV to inherit in char driver - assume harmless here */ |
3e6c4538 | 3107 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_SOFT_EVT_EN, 1); |
8ceee660 | 3108 | /* Prefetch threshold 2 => fetch when descriptor cache half empty */ |
3e6c4538 | 3109 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_PREF_THRESHOLD, 2); |
8ceee660 | 3110 | /* Squash TX of packets of 16 bytes or less */ |
55668611 | 3111 | if (falcon_rev(efx) >= FALCON_REV_B0 && EFX_WORKAROUND_9141(efx)) |
3e6c4538 | 3112 | EFX_SET_OWORD_FIELD(temp, FRF_BZ_TX_FLUSH_MIN_LEN_EN, 1); |
12d00cad | 3113 | efx_writeo(efx, &temp, FR_AZ_TX_RESERVED); |
8ceee660 BH |
3114 | |
3115 | /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16 | |
3116 | * descriptors (which is bad). | |
3117 | */ | |
12d00cad | 3118 | efx_reado(efx, &temp, FR_AZ_TX_CFG); |
3e6c4538 | 3119 | EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0); |
12d00cad | 3120 | efx_writeo(efx, &temp, FR_AZ_TX_CFG); |
8ceee660 | 3121 | |
56241ceb | 3122 | falcon_init_rx_cfg(efx); |
8ceee660 BH |
3123 | |
3124 | /* Set destination of both TX and RX Flush events */ | |
55668611 | 3125 | if (falcon_rev(efx) >= FALCON_REV_B0) { |
3e6c4538 | 3126 | EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0); |
12d00cad | 3127 | efx_writeo(efx, &temp, FR_BZ_DP_CTRL); |
8ceee660 BH |
3128 | } |
3129 | ||
3130 | return 0; | |
3131 | } | |
3132 | ||
3133 | void falcon_remove_nic(struct efx_nic *efx) | |
3134 | { | |
3135 | struct falcon_nic_data *nic_data = efx->nic_data; | |
e775fb93 | 3136 | struct falcon_board *board = falcon_board(efx); |
37b5a603 BH |
3137 | int rc; |
3138 | ||
44838a44 | 3139 | board->type->fini(efx); |
278c0621 | 3140 | |
8c870379 | 3141 | /* Remove I2C adapter and clear it in preparation for a retry */ |
e775fb93 | 3142 | rc = i2c_del_adapter(&board->i2c_adap); |
37b5a603 | 3143 | BUG_ON(rc); |
e775fb93 | 3144 | memset(&board->i2c_adap, 0, sizeof(board->i2c_adap)); |
8ceee660 | 3145 | |
4a5b504d | 3146 | falcon_remove_spi_devices(efx); |
8ceee660 BH |
3147 | falcon_free_buffer(efx, &efx->irq_status); |
3148 | ||
91ad757c | 3149 | falcon_reset_hw(efx, RESET_TYPE_ALL); |
8ceee660 BH |
3150 | |
3151 | /* Release the second function after the reset */ | |
3152 | if (nic_data->pci_dev2) { | |
3153 | pci_dev_put(nic_data->pci_dev2); | |
3154 | nic_data->pci_dev2 = NULL; | |
3155 | } | |
3156 | ||
3157 | /* Tear down the private nic state */ | |
3158 | kfree(efx->nic_data); | |
3159 | efx->nic_data = NULL; | |
3160 | } | |
3161 | ||
3162 | void falcon_update_nic_stats(struct efx_nic *efx) | |
3163 | { | |
55edc6e6 | 3164 | struct falcon_nic_data *nic_data = efx->nic_data; |
8ceee660 BH |
3165 | efx_oword_t cnt; |
3166 | ||
55edc6e6 BH |
3167 | if (nic_data->stats_disable_count) |
3168 | return; | |
3169 | ||
12d00cad | 3170 | efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP); |
3e6c4538 BH |
3171 | efx->n_rx_nodesc_drop_cnt += |
3172 | EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT); | |
55edc6e6 BH |
3173 | |
3174 | if (nic_data->stats_pending && | |
3175 | *nic_data->stats_dma_done == FALCON_STATS_DONE) { | |
3176 | nic_data->stats_pending = false; | |
3177 | rmb(); /* read the done flag before the stats */ | |
3178 | efx->mac_op->update_stats(efx); | |
3179 | } | |
3180 | } | |
3181 | ||
3182 | void falcon_start_nic_stats(struct efx_nic *efx) | |
3183 | { | |
3184 | struct falcon_nic_data *nic_data = efx->nic_data; | |
3185 | ||
3186 | spin_lock_bh(&efx->stats_lock); | |
3187 | if (--nic_data->stats_disable_count == 0) | |
3188 | falcon_stats_request(efx); | |
3189 | spin_unlock_bh(&efx->stats_lock); | |
3190 | } | |
3191 | ||
3192 | void falcon_stop_nic_stats(struct efx_nic *efx) | |
3193 | { | |
3194 | struct falcon_nic_data *nic_data = efx->nic_data; | |
3195 | int i; | |
3196 | ||
3197 | might_sleep(); | |
3198 | ||
3199 | spin_lock_bh(&efx->stats_lock); | |
3200 | ++nic_data->stats_disable_count; | |
3201 | spin_unlock_bh(&efx->stats_lock); | |
3202 | ||
3203 | del_timer_sync(&nic_data->stats_timer); | |
3204 | ||
3205 | /* Wait enough time for the most recent transfer to | |
3206 | * complete. */ | |
3207 | for (i = 0; i < 4 && nic_data->stats_pending; i++) { | |
3208 | if (*nic_data->stats_dma_done == FALCON_STATS_DONE) | |
3209 | break; | |
3210 | msleep(1); | |
3211 | } | |
3212 | ||
3213 | spin_lock_bh(&efx->stats_lock); | |
3214 | falcon_stats_complete(efx); | |
3215 | spin_unlock_bh(&efx->stats_lock); | |
8ceee660 BH |
3216 | } |
3217 | ||
3218 | /************************************************************************** | |
3219 | * | |
3220 | * Revision-dependent attributes used by efx.c | |
3221 | * | |
3222 | ************************************************************************** | |
3223 | */ | |
3224 | ||
3225 | struct efx_nic_type falcon_a_nic_type = { | |
8ceee660 | 3226 | .mem_map_size = 0x20000, |
3e6c4538 BH |
3227 | .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER, |
3228 | .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER, | |
3229 | .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER, | |
3230 | .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER, | |
3231 | .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER, | |
6d51d307 | 3232 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
8ceee660 BH |
3233 | .rx_buffer_padding = 0x24, |
3234 | .max_interrupt_mode = EFX_INT_MODE_MSI, | |
3235 | .phys_addr_channels = 4, | |
3236 | }; | |
3237 | ||
3238 | struct efx_nic_type falcon_b_nic_type = { | |
8ceee660 BH |
3239 | /* Map everything up to and including the RSS indirection |
3240 | * table. Don't map MSI-X table, MSI-X PBA since Linux | |
3241 | * requires that they not be mapped. */ | |
3e6c4538 BH |
3242 | .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL + |
3243 | FR_BZ_RX_INDIRECTION_TBL_STEP * | |
3244 | FR_BZ_RX_INDIRECTION_TBL_ROWS), | |
3245 | .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL, | |
3246 | .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL, | |
3247 | .buf_tbl_base = FR_BZ_BUF_FULL_TBL, | |
3248 | .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL, | |
3249 | .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR, | |
6d51d307 | 3250 | .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH), |
8ceee660 BH |
3251 | .rx_buffer_padding = 0, |
3252 | .max_interrupt_mode = EFX_INT_MODE_MSIX, | |
3253 | .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy | |
3254 | * interrupt handler only supports 32 | |
3255 | * channels */ | |
3256 | }; | |
3257 |