[mirror_ubuntu-bionic-kernel.git] / drivers / net / sfc / falcon_io.h

/****************************************************************************
 * Driver for Solarflare Solarstorm network controllers and boards
 * Copyright 2005-2006 Fen Systems Ltd.
 * Copyright 2006-2008 Solarflare Communications Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation, incorporated herein by reference.
 */

#ifndef EFX_FALCON_IO_H
#define EFX_FALCON_IO_H

#include <linux/io.h>
#include <linux/spinlock.h>
#include "net_driver.h"

/**************************************************************************
 *
 * Falcon hardware access
 *
 **************************************************************************
 *
 * Notes on locking strategy:
 *
 * Most Falcon registers require 16-byte (or 8-byte, for SRAM
 * registers) atomic writes which necessitates locking.
 * Under normal operation few writes to the Falcon BAR are made and these
 * registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and TX_DESC_UPD_REG) are special
 * cased to allow 4-byte (hence lockless) accesses.
 *
 * It *is* safe to write to these 4-byte registers in the middle of an
 * access to an 8-byte or 16-byte register.  We therefore use a
 * spinlock to protect accesses to the larger registers, but no locks
 * for the 4-byte registers.
 *
 * A write barrier is needed to ensure that DW3 is written after DW0/1/2
 * due to the way the 16byte registers are "collected" in the Falcon BIU
 *
 * We also lock when carrying out reads, to ensure consistency of the
 * data (made possible since the BIU reads all 128 bits into a cache).
 * Reads are very rare, so this isn't a significant performance
 * impact.  (Most data transferred from NIC to host is DMAed directly
 * into host memory).
 *
 * I/O BAR access uses locks for both reads and writes (but is only provided
 * for testing purposes).
 */

/* Special buffer descriptors (Falcon SRAM) */
#define BUF_TBL_KER_A1 0x18000
#define BUF_TBL_KER_B0 0x800000


#if BITS_PER_LONG == 64
#define FALCON_USE_QWORD_IO 1
#endif

#ifdef FALCON_USE_QWORD_IO
static inline void _falcon_writeq(struct efx_nic *efx, __le64 value,
				  unsigned int reg)
{
	__raw_writeq((__force u64)value, efx->membase + reg);
}
static inline __le64 _falcon_readq(struct efx_nic *efx, unsigned int reg)
{
	return (__force __le64)__raw_readq(efx->membase + reg);
}
#endif

static inline void _falcon_writel(struct efx_nic *efx, __le32 value,
				  unsigned int reg)
{
	__raw_writel((__force u32)value, efx->membase + reg);
}
static inline __le32 _falcon_readl(struct efx_nic *efx, unsigned int reg)
{
	return (__force __le32)__raw_readl(efx->membase + reg);
}

/* Writes to a normal 16-byte Falcon register, locking as appropriate. */
static inline void falcon_write(struct efx_nic *efx, efx_oword_t *value,
				unsigned int reg)
{
	unsigned long flags;

	EFX_REGDUMP(efx, "writing register %x with " EFX_OWORD_FMT "\n", reg,
		    EFX_OWORD_VAL(*value));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef FALCON_USE_QWORD_IO
	_falcon_writeq(efx, value->u64[0], reg + 0);
	wmb();
	_falcon_writeq(efx, value->u64[1], reg + 8);
#else
	_falcon_writel(efx, value->u32[0], reg + 0);
	_falcon_writel(efx, value->u32[1], reg + 4);
	_falcon_writel(efx, value->u32[2], reg + 8);
	wmb();
	_falcon_writel(efx, value->u32[3], reg + 12);
#endif
	mmiowb();
	spin_unlock_irqrestore(&efx->biu_lock, flags);
}

/* Writes to an 8-byte Falcon SRAM register, locking as appropriate. */
static inline void falcon_write_sram(struct efx_nic *efx, efx_qword_t *value,
				     unsigned int index)
{
	unsigned int reg = efx->type->buf_tbl_base + (index * sizeof(*value));
	unsigned long flags;

	EFX_REGDUMP(efx, "writing SRAM register %x with " EFX_QWORD_FMT "\n",
		    reg, EFX_QWORD_VAL(*value));

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef FALCON_USE_QWORD_IO
	_falcon_writeq(efx, value->u64[0], reg + 0);
#else
	_falcon_writel(efx, value->u32[0], reg + 0);
	wmb();
	_falcon_writel(efx, value->u32[1], reg + 4);
#endif
	mmiowb();
	spin_unlock_irqrestore(&efx->biu_lock, flags);
}

/* Write dword to Falcon register that allows partial writes
 *
 * Some Falcon registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and
 * TX_DESC_UPD_REG) can be written to as a single dword.  This allows
 * for lockless writes.
 */
static inline void falcon_writel(struct efx_nic *efx, efx_dword_t *value,
				 unsigned int reg)
{
	EFX_REGDUMP(efx, "writing partial register %x with "EFX_DWORD_FMT"\n",
		    reg, EFX_DWORD_VAL(*value));

	/* No lock required */
	_falcon_writel(efx, value->u32[0], reg);
}

/* Read from a Falcon register
 *
 * This reads an entire 16-byte Falcon register in one go, locking as
 * appropriate.  It is essential to read the first dword first, as this
 * prompts Falcon to load the current value into the shadow register.
 */
static inline void falcon_read(struct efx_nic *efx, efx_oword_t *value,
			       unsigned int reg)
{
	unsigned long flags;

	spin_lock_irqsave(&efx->biu_lock, flags);
	value->u32[0] = _falcon_readl(efx, reg + 0);
	rmb();
	value->u32[1] = _falcon_readl(efx, reg + 4);
	value->u32[2] = _falcon_readl(efx, reg + 8);
	value->u32[3] = _falcon_readl(efx, reg + 12);
	spin_unlock_irqrestore(&efx->biu_lock, flags);

	EFX_REGDUMP(efx, "read from register %x, got " EFX_OWORD_FMT "\n", reg,
		    EFX_OWORD_VAL(*value));
}

/* This reads an 8-byte Falcon SRAM entry in one go. */
static inline void falcon_read_sram(struct efx_nic *efx, efx_qword_t *value,
				    unsigned int index)
{
	unsigned int reg = efx->type->buf_tbl_base + (index * sizeof(*value));
	unsigned long flags;

	spin_lock_irqsave(&efx->biu_lock, flags);
#ifdef FALCON_USE_QWORD_IO
	value->u64[0] = _falcon_readq(efx, reg + 0);
#else
	value->u32[0] = _falcon_readl(efx, reg + 0);
	rmb();
	value->u32[1] = _falcon_readl(efx, reg + 4);
#endif
	spin_unlock_irqrestore(&efx->biu_lock, flags);

	EFX_REGDUMP(efx, "read from SRAM register %x, got "EFX_QWORD_FMT"\n",
		    reg, EFX_QWORD_VAL(*value));
}

/* Read dword from Falcon register that allows partial writes (sic) */
static inline void falcon_readl(struct efx_nic *efx, efx_dword_t *value,
				unsigned int reg)
{
	value->u32[0] = _falcon_readl(efx, reg);
	EFX_REGDUMP(efx, "read from register %x, got "EFX_DWORD_FMT"\n",
		    reg, EFX_DWORD_VAL(*value));
}

/* Write to a register forming part of a table */
static inline void falcon_write_table(struct efx_nic *efx, efx_oword_t *value,
				      unsigned int reg, unsigned int index)
{
	falcon_write(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Read to a register forming part of a table */
static inline void falcon_read_table(struct efx_nic *efx, efx_oword_t *value,
				     unsigned int reg, unsigned int index)
{
	falcon_read(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Write to a dword register forming part of a table */
static inline void falcon_writel_table(struct efx_nic *efx, efx_dword_t *value,
				       unsigned int reg, unsigned int index)
{
	falcon_writel(efx, value, reg + index * sizeof(efx_oword_t));
}

/* Page-mapped register block size */
#define FALCON_PAGE_BLOCK_SIZE 0x2000

/* Calculate offset to page-mapped register block */
#define FALCON_PAGED_REG(page, reg) \
	((page) * FALCON_PAGE_BLOCK_SIZE + (reg))

/* As for falcon_write(), but for a page-mapped register. */
static inline void falcon_write_page(struct efx_nic *efx, efx_oword_t *value,
				     unsigned int reg, unsigned int page)
{
	falcon_write(efx, value, FALCON_PAGED_REG(page, reg));
}

/* As for falcon_writel(), but for a page-mapped register. */
static inline void falcon_writel_page(struct efx_nic *efx, efx_dword_t *value,
				      unsigned int reg, unsigned int page)
{
	falcon_writel(efx, value, FALCON_PAGED_REG(page, reg));
}

/* Write dword to Falcon page-mapped register with an extra lock.
 *
 * As for falcon_writel_page(), but for a register that suffers from
 * SFC bug 3181. Take out a lock so the BIU collector cannot be
 * confused. */
static inline void falcon_writel_page_locked(struct efx_nic *efx,
					     efx_dword_t *value,
					     unsigned int reg,
					     unsigned int page)
{
	unsigned long flags;

	spin_lock_irqsave(&efx->biu_lock, flags);
	falcon_writel(efx, value, FALCON_PAGED_REG(page, reg));
	spin_unlock_irqrestore(&efx->biu_lock, flags);
}

#endif /* EFX_FALCON_IO_H */
Commit	Line	Data
8ceee660 BH	1	/****************************************************************************
	2	* Driver for Solarflare Solarstorm network controllers and boards
	3	* Copyright 2005-2006 Fen Systems Ltd.
	4	* Copyright 2006-2008 Solarflare Communications Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License version 2 as published
	8	* by the Free Software Foundation, incorporated herein by reference.
	9	*/
	10
	11	#ifndef EFX_FALCON_IO_H
	12	#define EFX_FALCON_IO_H
	13
	14	#include <linux/io.h>
	15	#include <linux/spinlock.h>
	16	#include "net_driver.h"
	17
	18	/**************************************************************************
	19	*
	20	* Falcon hardware access
	21	*
	22	**************************************************************************
	23	*
	24	* Notes on locking strategy:
	25	*
	26	* Most Falcon registers require 16-byte (or 8-byte, for SRAM
	27	* registers) atomic writes which necessitates locking.
	28	* Under normal operation few writes to the Falcon BAR are made and these
	29	* registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and TX_DESC_UPD_REG) are special
	30	* cased to allow 4-byte (hence lockless) accesses.
	31	*
	32	* It is safe to write to these 4-byte registers in the middle of an
	33	* access to an 8-byte or 16-byte register. We therefore use a
	34	* spinlock to protect accesses to the larger registers, but no locks
	35	* for the 4-byte registers.
	36	*
	37	* A write barrier is needed to ensure that DW3 is written after DW0/1/2
	38	* due to the way the 16byte registers are "collected" in the Falcon BIU
	39	*
	40	* We also lock when carrying out reads, to ensure consistency of the
	41	* data (made possible since the BIU reads all 128 bits into a cache).
	42	* Reads are very rare, so this isn't a significant performance
	43	* impact. (Most data transferred from NIC to host is DMAed directly
	44	* into host memory).
	45	*
	46	* I/O BAR access uses locks for both reads and writes (but is only provided
	47	* for testing purposes).
	48	*/
	49
	50	/* Special buffer descriptors (Falcon SRAM) */
	51	#define BUF_TBL_KER_A1 0x18000
	52	#define BUF_TBL_KER_B0 0x800000
	53
	54
	55	#if BITS_PER_LONG == 64
	56	#define FALCON_USE_QWORD_IO 1
	57	#endif
	58
55668611 BH	59	#ifdef FALCON_USE_QWORD_IO
	60	static inline void _falcon_writeq(struct efx_nic *efx, __le64 value,
	61	unsigned int reg)
	62	{
	63	__raw_writeq((__force u64)value, efx->membase + reg);
	64	}
	65	static inline __le64 _falcon_readq(struct efx_nic *efx, unsigned int reg)
	66	{
	67	return (__force __le64)__raw_readq(efx->membase + reg);
	68	}
	69	#endif
	70
	71	static inline void _falcon_writel(struct efx_nic *efx, __le32 value,
	72	unsigned int reg)
	73	{
	74	__raw_writel((__force u32)value, efx->membase + reg);
	75	}
	76	static inline __le32 _falcon_readl(struct efx_nic *efx, unsigned int reg)
	77	{
	78	return (__force __le32)__raw_readl(efx->membase + reg);
	79	}
8ceee660 BH	80
	81	/* Writes to a normal 16-byte Falcon register, locking as appropriate. */
	82	static inline void falcon_write(struct efx_nic efx, efx_oword_t value,
	83	unsigned int reg)
	84	{
	85	unsigned long flags;
	86
	87	EFX_REGDUMP(efx, "writing register %x with " EFX_OWORD_FMT "\n", reg,
	88	EFX_OWORD_VAL(*value));
	89
	90	spin_lock_irqsave(&efx->biu_lock, flags);
	91	#ifdef FALCON_USE_QWORD_IO
	92	_falcon_writeq(efx, value->u64[0], reg + 0);
	93	wmb();
	94	_falcon_writeq(efx, value->u64[1], reg + 8);
	95	#else
	96	_falcon_writel(efx, value->u32[0], reg + 0);
	97	_falcon_writel(efx, value->u32[1], reg + 4);
	98	_falcon_writel(efx, value->u32[2], reg + 8);
	99	wmb();
	100	_falcon_writel(efx, value->u32[3], reg + 12);
	101	#endif
	102	mmiowb();
	103	spin_unlock_irqrestore(&efx->biu_lock, flags);
	104	}
	105
	106	/* Writes to an 8-byte Falcon SRAM register, locking as appropriate. */
	107	static inline void falcon_write_sram(struct efx_nic efx, efx_qword_t value,
	108	unsigned int index)
	109	{
	110	unsigned int reg = efx->type->buf_tbl_base + (index * sizeof(*value));
	111	unsigned long flags;
	112
	113	EFX_REGDUMP(efx, "writing SRAM register %x with " EFX_QWORD_FMT "\n",
	114	reg, EFX_QWORD_VAL(*value));
	115
	116	spin_lock_irqsave(&efx->biu_lock, flags);
	117	#ifdef FALCON_USE_QWORD_IO
	118	_falcon_writeq(efx, value->u64[0], reg + 0);
	119	#else
	120	_falcon_writel(efx, value->u32[0], reg + 0);
	121	wmb();
	122	_falcon_writel(efx, value->u32[1], reg + 4);
	123	#endif
	124	mmiowb();
	125	spin_unlock_irqrestore(&efx->biu_lock, flags);
	126	}
	127
	128	/* Write dword to Falcon register that allows partial writes
	129	*
	130	* Some Falcon registers (EVQ_RPTR_REG, RX_DESC_UPD_REG and
	131	* TX_DESC_UPD_REG) can be written to as a single dword. This allows
	132	* for lockless writes.
	133	*/
	134	static inline void falcon_writel(struct efx_nic efx, efx_dword_t value,
	135	unsigned int reg)
	136	{
	137	EFX_REGDUMP(efx, "writing partial register %x with "EFX_DWORD_FMT"\n",
	138	reg, EFX_DWORD_VAL(*value));
	139
	140	/* No lock required */
	141	_falcon_writel(efx, value->u32[0], reg);
	142	}
	143
144	/* Read from a Falcon register
145	*
146	* This reads an entire 16-byte Falcon register in one go, locking as
147	* appropriate. It is essential to read the first dword first, as this
148	* prompts Falcon to load the current value into the shadow register.
149	*/
150	static inline void falcon_read(struct efx_nic efx, efx_oword_t value,
151	unsigned int reg)
152	{
153	unsigned long flags;
154
155	spin_lock_irqsave(&efx->biu_lock, flags);
156	value->u32[0] = _falcon_readl(efx, reg + 0);
157	rmb();
158	value->u32[1] = _falcon_readl(efx, reg + 4);
159	value->u32[2] = _falcon_readl(efx, reg + 8);
160	value->u32[3] = _falcon_readl(efx, reg + 12);
161	spin_unlock_irqrestore(&efx->biu_lock, flags);
162
163	EFX_REGDUMP(efx, "read from register %x, got " EFX_OWORD_FMT "\n", reg,
164	EFX_OWORD_VAL(*value));
165	}
166
167	/* This reads an 8-byte Falcon SRAM entry in one go. */
168	static inline void falcon_read_sram(struct efx_nic efx, efx_qword_t value,
169	unsigned int index)
170	{
171	unsigned int reg = efx->type->buf_tbl_base + (index * sizeof(*value));
172	unsigned long flags;
173
174	spin_lock_irqsave(&efx->biu_lock, flags);
175	#ifdef FALCON_USE_QWORD_IO
176	value->u64[0] = _falcon_readq(efx, reg + 0);
177	#else
178	value->u32[0] = _falcon_readl(efx, reg + 0);
179	rmb();
180	value->u32[1] = _falcon_readl(efx, reg + 4);
181	#endif
182	spin_unlock_irqrestore(&efx->biu_lock, flags);
183
184	EFX_REGDUMP(efx, "read from SRAM register %x, got "EFX_QWORD_FMT"\n",
185	reg, EFX_QWORD_VAL(*value));
186	}
187
188	/* Read dword from Falcon register that allows partial writes (sic) */
189	static inline void falcon_readl(struct efx_nic efx, efx_dword_t value,
190	unsigned int reg)
191	{
192	value->u32[0] = _falcon_readl(efx, reg);
193	EFX_REGDUMP(efx, "read from register %x, got "EFX_DWORD_FMT"\n",
194	reg, EFX_DWORD_VAL(*value));
195	}
196
197	/* Write to a register forming part of a table */
198	static inline void falcon_write_table(struct efx_nic efx, efx_oword_t value,
199	unsigned int reg, unsigned int index)
200	{
201	falcon_write(efx, value, reg + index * sizeof(efx_oword_t));
202	}
203
204	/* Read to a register forming part of a table */
205	static inline void falcon_read_table(struct efx_nic efx, efx_oword_t value,
206	unsigned int reg, unsigned int index)
207	{
208	falcon_read(efx, value, reg + index * sizeof(efx_oword_t));
209	}
210
211	/* Write to a dword register forming part of a table */
212	static inline void falcon_writel_table(struct efx_nic efx, efx_dword_t value,
213	unsigned int reg, unsigned int index)
214	{
215	falcon_writel(efx, value, reg + index * sizeof(efx_oword_t));
216	}
217
218	/* Page-mapped register block size */
219	#define FALCON_PAGE_BLOCK_SIZE 0x2000
220
221	/* Calculate offset to page-mapped register block */
222	#define FALCON_PAGED_REG(page, reg) \
223	((page) * FALCON_PAGE_BLOCK_SIZE + (reg))
224
225	/* As for falcon_write(), but for a page-mapped register. */
226	static inline void falcon_write_page(struct efx_nic efx, efx_oword_t value,
227	unsigned int reg, unsigned int page)
228	{
229	falcon_write(efx, value, FALCON_PAGED_REG(page, reg));
230	}
231
232	/* As for falcon_writel(), but for a page-mapped register. */
233	static inline void falcon_writel_page(struct efx_nic efx, efx_dword_t value,
234	unsigned int reg, unsigned int page)
235	{
236	falcon_writel(efx, value, FALCON_PAGED_REG(page, reg));
237	}
238
239	/* Write dword to Falcon page-mapped register with an extra lock.
240	*
241	* As for falcon_writel_page(), but for a register that suffers from
242	* SFC bug 3181. Take out a lock so the BIU collector cannot be
243	* confused. */
244	static inline void falcon_writel_page_locked(struct efx_nic *efx,
245	efx_dword_t *value,
246	unsigned int reg,
247	unsigned int page)
248	{
249	unsigned long flags;
250
251	spin_lock_irqsave(&efx->biu_lock, flags);
252	falcon_writel(efx, value, FALCON_PAGED_REG(page, reg));
253	spin_unlock_irqrestore(&efx->biu_lock, flags);
254	}
255
256	#endif /* EFX_FALCON_IO_H */