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8ceee660 | 1 | /**************************************************************************** |
177dfcd8 | 2 | * Driver for Solarflare Solarstorm network controllers and boards |
906bb26c | 3 | * Copyright 2007-2009 Solarflare Communications Inc. |
8ceee660 BH |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License version 2 as published | |
7 | * by the Free Software Foundation, incorporated herein by reference. | |
8 | */ | |
9 | ||
10 | #include <linux/delay.h> | |
da3bc071 | 11 | #include <linux/rtnetlink.h> |
8ceee660 | 12 | #include <linux/seq_file.h> |
5a0e3ad6 | 13 | #include <linux/slab.h> |
8ceee660 | 14 | #include "efx.h" |
8ceee660 | 15 | #include "mdio_10g.h" |
744093c9 | 16 | #include "nic.h" |
8ceee660 | 17 | #include "phy.h" |
3e6c4538 | 18 | #include "regs.h" |
e6fa2eb7 BH |
19 | #include "workarounds.h" |
20 | #include "selftest.h" | |
8ceee660 | 21 | |
e6fa2eb7 BH |
22 | /* We expect these MMDs to be in the package. SFT9001 also has a |
23 | * clause 22 extension MMD, but since it doesn't have all the generic | |
24 | * MMD registers it is pointless to include it here. | |
25 | */ | |
68e7f45e BH |
26 | #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \ |
27 | MDIO_DEVS_PCS | \ | |
28 | MDIO_DEVS_PHYXS | \ | |
29 | MDIO_DEVS_AN) | |
8ceee660 | 30 | |
e6fa2eb7 BH |
31 | #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \ |
32 | (1 << LOOPBACK_PCS) | \ | |
33 | (1 << LOOPBACK_PMAPMD) | \ | |
e58f69f4 | 34 | (1 << LOOPBACK_PHYXS_WS)) |
e6fa2eb7 BH |
35 | |
36 | #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \ | |
37 | (1 << LOOPBACK_PHYXS) | \ | |
38 | (1 << LOOPBACK_PCS) | \ | |
39 | (1 << LOOPBACK_PMAPMD) | \ | |
e58f69f4 | 40 | (1 << LOOPBACK_PHYXS_WS)) |
3273c2e8 | 41 | |
8ceee660 BH |
42 | /* We complain if we fail to see the link partner as 10G capable this many |
43 | * times in a row (must be > 1 as sampling the autoneg. registers is racy) | |
44 | */ | |
45 | #define MAX_BAD_LP_TRIES (5) | |
46 | ||
47 | /* Extended control register */ | |
e6fa2eb7 BH |
48 | #define PMA_PMD_XCONTROL_REG 49152 |
49 | #define PMA_PMD_EXT_GMII_EN_LBN 1 | |
50 | #define PMA_PMD_EXT_GMII_EN_WIDTH 1 | |
51 | #define PMA_PMD_EXT_CLK_OUT_LBN 2 | |
52 | #define PMA_PMD_EXT_CLK_OUT_WIDTH 1 | |
53 | #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */ | |
54 | #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1 | |
55 | #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */ | |
56 | #define PMA_PMD_EXT_CLK312_WIDTH 1 | |
57 | #define PMA_PMD_EXT_LPOWER_LBN 12 | |
58 | #define PMA_PMD_EXT_LPOWER_WIDTH 1 | |
869b5b38 SH |
59 | #define PMA_PMD_EXT_ROBUST_LBN 14 |
60 | #define PMA_PMD_EXT_ROBUST_WIDTH 1 | |
e6fa2eb7 BH |
61 | #define PMA_PMD_EXT_SSR_LBN 15 |
62 | #define PMA_PMD_EXT_SSR_WIDTH 1 | |
8ceee660 BH |
63 | |
64 | /* extended status register */ | |
e6fa2eb7 | 65 | #define PMA_PMD_XSTATUS_REG 49153 |
e762cd70 | 66 | #define PMA_PMD_XSTAT_MDIX_LBN 14 |
8ceee660 BH |
67 | #define PMA_PMD_XSTAT_FLP_LBN (12) |
68 | ||
69 | /* LED control register */ | |
e6fa2eb7 | 70 | #define PMA_PMD_LED_CTRL_REG 49159 |
8ceee660 BH |
71 | #define PMA_PMA_LED_ACTIVITY_LBN (3) |
72 | ||
73 | /* LED function override register */ | |
e6fa2eb7 | 74 | #define PMA_PMD_LED_OVERR_REG 49161 |
8ceee660 BH |
75 | /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/ |
76 | #define PMA_PMD_LED_LINK_LBN (0) | |
77 | #define PMA_PMD_LED_SPEED_LBN (2) | |
78 | #define PMA_PMD_LED_TX_LBN (4) | |
79 | #define PMA_PMD_LED_RX_LBN (6) | |
80 | /* Override settings */ | |
81 | #define PMA_PMD_LED_AUTO (0) /* H/W control */ | |
82 | #define PMA_PMD_LED_ON (1) | |
83 | #define PMA_PMD_LED_OFF (2) | |
84 | #define PMA_PMD_LED_FLASH (3) | |
04cc8cac | 85 | #define PMA_PMD_LED_MASK 3 |
8ceee660 | 86 | /* All LEDs under hardware control */ |
dcf477b2 | 87 | #define SFT9001_PMA_PMD_LED_DEFAULT 0 |
8ceee660 | 88 | /* Green and Amber under hardware control, Red off */ |
dcf477b2 | 89 | #define SFX7101_PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) |
8ceee660 | 90 | |
e6fa2eb7 BH |
91 | #define PMA_PMD_SPEED_ENABLE_REG 49192 |
92 | #define PMA_PMD_100TX_ADV_LBN 1 | |
93 | #define PMA_PMD_100TX_ADV_WIDTH 1 | |
94 | #define PMA_PMD_1000T_ADV_LBN 2 | |
95 | #define PMA_PMD_1000T_ADV_WIDTH 1 | |
96 | #define PMA_PMD_10000T_ADV_LBN 3 | |
97 | #define PMA_PMD_10000T_ADV_WIDTH 1 | |
98 | #define PMA_PMD_SPEED_LBN 4 | |
99 | #define PMA_PMD_SPEED_WIDTH 4 | |
100 | ||
307505e9 BH |
101 | /* Cable diagnostics - SFT9001 only */ |
102 | #define PMA_PMD_CDIAG_CTRL_REG 49213 | |
103 | #define CDIAG_CTRL_IMMED_LBN 15 | |
104 | #define CDIAG_CTRL_BRK_LINK_LBN 12 | |
105 | #define CDIAG_CTRL_IN_PROG_LBN 11 | |
106 | #define CDIAG_CTRL_LEN_UNIT_LBN 10 | |
107 | #define CDIAG_CTRL_LEN_METRES 1 | |
108 | #define PMA_PMD_CDIAG_RES_REG 49174 | |
109 | #define CDIAG_RES_A_LBN 12 | |
110 | #define CDIAG_RES_B_LBN 8 | |
111 | #define CDIAG_RES_C_LBN 4 | |
112 | #define CDIAG_RES_D_LBN 0 | |
113 | #define CDIAG_RES_WIDTH 4 | |
114 | #define CDIAG_RES_OPEN 2 | |
115 | #define CDIAG_RES_OK 1 | |
116 | #define CDIAG_RES_INVALID 0 | |
117 | /* Set of 4 registers for pairs A-D */ | |
118 | #define PMA_PMD_CDIAG_LEN_REG 49175 | |
119 | ||
e6fa2eb7 BH |
120 | /* Serdes control registers - SFT9001 only */ |
121 | #define PMA_PMD_CSERDES_CTRL_REG 64258 | |
122 | /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */ | |
123 | #define PMA_PMD_CSERDES_DEFAULT 0x000f | |
124 | ||
125 | /* Misc register defines - SFX7101 only */ | |
126 | #define PCS_CLOCK_CTRL_REG 55297 | |
8ceee660 BH |
127 | #define PLL312_RST_N_LBN 2 |
128 | ||
e6fa2eb7 | 129 | #define PCS_SOFT_RST2_REG 55302 |
8ceee660 BH |
130 | #define SERDES_RST_N_LBN 13 |
131 | #define XGXS_RST_N_LBN 12 | |
132 | ||
e6fa2eb7 | 133 | #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */ |
8ceee660 BH |
134 | #define CLK312_EN_LBN 3 |
135 | ||
3273c2e8 | 136 | /* PHYXS registers */ |
e6fa2eb7 BH |
137 | #define PHYXS_XCONTROL_REG 49152 |
138 | #define PHYXS_RESET_LBN 15 | |
139 | #define PHYXS_RESET_WIDTH 1 | |
140 | ||
3273c2e8 BH |
141 | #define PHYXS_TEST1 (49162) |
142 | #define LOOPBACK_NEAR_LBN (8) | |
143 | #define LOOPBACK_NEAR_WIDTH (1) | |
144 | ||
8ceee660 | 145 | /* Boot status register */ |
190dbcfd BH |
146 | #define PCS_BOOT_STATUS_REG 53248 |
147 | #define PCS_BOOT_FATAL_ERROR_LBN 0 | |
148 | #define PCS_BOOT_PROGRESS_LBN 1 | |
149 | #define PCS_BOOT_PROGRESS_WIDTH 2 | |
150 | #define PCS_BOOT_PROGRESS_INIT 0 | |
151 | #define PCS_BOOT_PROGRESS_WAIT_MDIO 1 | |
152 | #define PCS_BOOT_PROGRESS_CHECKSUM 2 | |
153 | #define PCS_BOOT_PROGRESS_JUMP 3 | |
154 | #define PCS_BOOT_DOWNLOAD_WAIT_LBN 3 | |
155 | #define PCS_BOOT_CODE_STARTED_LBN 4 | |
8ceee660 | 156 | |
e6fa2eb7 BH |
157 | /* 100M/1G PHY registers */ |
158 | #define GPHY_XCONTROL_REG 49152 | |
159 | #define GPHY_ISOLATE_LBN 10 | |
160 | #define GPHY_ISOLATE_WIDTH 1 | |
161 | #define GPHY_DUPLEX_LBN 8 | |
162 | #define GPHY_DUPLEX_WIDTH 1 | |
163 | #define GPHY_LOOPBACK_NEAR_LBN 14 | |
164 | #define GPHY_LOOPBACK_NEAR_WIDTH 1 | |
165 | ||
166 | #define C22EXT_STATUS_REG 49153 | |
167 | #define C22EXT_STATUS_LINK_LBN 2 | |
168 | #define C22EXT_STATUS_LINK_WIDTH 1 | |
169 | ||
af4ad9bc BH |
170 | #define C22EXT_MSTSLV_CTRL 49161 |
171 | #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8 | |
172 | #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9 | |
173 | ||
174 | #define C22EXT_MSTSLV_STATUS 49162 | |
175 | #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10 | |
176 | #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11 | |
e6fa2eb7 | 177 | |
8ceee660 BH |
178 | /* Time to wait between powering down the LNPGA and turning off the power |
179 | * rails */ | |
180 | #define LNPGA_PDOWN_WAIT (HZ / 5) | |
181 | ||
8ceee660 | 182 | struct tenxpress_phy_data { |
3273c2e8 | 183 | enum efx_loopback_mode loopback_mode; |
f8b87c17 | 184 | enum efx_phy_mode phy_mode; |
8ceee660 BH |
185 | int bad_lp_tries; |
186 | }; | |
187 | ||
e6fa2eb7 BH |
188 | static ssize_t show_phy_short_reach(struct device *dev, |
189 | struct device_attribute *attr, char *buf) | |
190 | { | |
191 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
192 | int reg; | |
193 | ||
68e7f45e BH |
194 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR); |
195 | return sprintf(buf, "%d\n", !!(reg & MDIO_PMA_10GBT_TXPWR_SHORT)); | |
e6fa2eb7 BH |
196 | } |
197 | ||
198 | static ssize_t set_phy_short_reach(struct device *dev, | |
199 | struct device_attribute *attr, | |
200 | const char *buf, size_t count) | |
201 | { | |
202 | struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev)); | |
d3245b28 | 203 | int rc; |
e6fa2eb7 BH |
204 | |
205 | rtnl_lock(); | |
ff3b00a0 SH |
206 | if (efx->state != STATE_RUNNING) { |
207 | rc = -EBUSY; | |
208 | } else { | |
209 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR, | |
210 | MDIO_PMA_10GBT_TXPWR_SHORT, | |
211 | count != 0 && *buf != '0'); | |
212 | rc = efx_reconfigure_port(efx); | |
213 | } | |
e6fa2eb7 BH |
214 | rtnl_unlock(); |
215 | ||
d3245b28 | 216 | return rc < 0 ? rc : (ssize_t)count; |
e6fa2eb7 BH |
217 | } |
218 | ||
219 | static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach, | |
220 | set_phy_short_reach); | |
221 | ||
190dbcfd | 222 | int sft9001_wait_boot(struct efx_nic *efx) |
8ceee660 | 223 | { |
190dbcfd | 224 | unsigned long timeout = jiffies + HZ + 1; |
8ceee660 BH |
225 | int boot_stat; |
226 | ||
190dbcfd | 227 | for (;;) { |
68e7f45e BH |
228 | boot_stat = efx_mdio_read(efx, MDIO_MMD_PCS, |
229 | PCS_BOOT_STATUS_REG); | |
190dbcfd BH |
230 | if (boot_stat >= 0) { |
231 | EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat); | |
232 | switch (boot_stat & | |
233 | ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
234 | (3 << PCS_BOOT_PROGRESS_LBN) | | |
235 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
236 | (1 << PCS_BOOT_CODE_STARTED_LBN))) { | |
237 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
238 | (PCS_BOOT_PROGRESS_CHECKSUM << | |
239 | PCS_BOOT_PROGRESS_LBN)): | |
240 | case ((1 << PCS_BOOT_FATAL_ERROR_LBN) | | |
241 | (PCS_BOOT_PROGRESS_INIT << | |
242 | PCS_BOOT_PROGRESS_LBN) | | |
243 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
244 | return -EINVAL; | |
245 | case ((PCS_BOOT_PROGRESS_WAIT_MDIO << | |
246 | PCS_BOOT_PROGRESS_LBN) | | |
247 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)): | |
248 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
249 | 0 : -EIO; | |
250 | case ((PCS_BOOT_PROGRESS_JUMP << | |
251 | PCS_BOOT_PROGRESS_LBN) | | |
252 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
253 | case ((PCS_BOOT_PROGRESS_JUMP << | |
254 | PCS_BOOT_PROGRESS_LBN) | | |
255 | (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) | | |
256 | (1 << PCS_BOOT_CODE_STARTED_LBN)): | |
257 | return (efx->phy_mode & PHY_MODE_SPECIAL) ? | |
258 | -EIO : 0; | |
259 | default: | |
260 | if (boot_stat & (1 << PCS_BOOT_FATAL_ERROR_LBN)) | |
261 | return -EIO; | |
262 | break; | |
263 | } | |
264 | } | |
265 | ||
266 | if (time_after_eq(jiffies, timeout)) | |
267 | return -ETIMEDOUT; | |
268 | ||
269 | msleep(50); | |
8ceee660 | 270 | } |
8ceee660 BH |
271 | } |
272 | ||
8ceee660 BH |
273 | static int tenxpress_init(struct efx_nic *efx) |
274 | { | |
e6fa2eb7 | 275 | int reg; |
8ceee660 | 276 | |
e6fa2eb7 BH |
277 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
278 | /* Enable 312.5 MHz clock */ | |
68e7f45e BH |
279 | efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG, |
280 | 1 << CLK312_EN_LBN); | |
e6fa2eb7 BH |
281 | } else { |
282 | /* Enable 312.5 MHz clock and GMII */ | |
68e7f45e | 283 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
e6fa2eb7 BH |
284 | reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) | |
285 | (1 << PMA_PMD_EXT_CLK_OUT_LBN) | | |
869b5b38 SH |
286 | (1 << PMA_PMD_EXT_CLK312_LBN) | |
287 | (1 << PMA_PMD_EXT_ROBUST_LBN)); | |
288 | ||
68e7f45e BH |
289 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
290 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, | |
291 | GPHY_XCONTROL_REG, 1 << GPHY_ISOLATE_LBN, | |
292 | false); | |
e6fa2eb7 | 293 | } |
8ceee660 | 294 | |
8ceee660 | 295 | /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */ |
e6fa2eb7 | 296 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
68e7f45e BH |
297 | efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG, |
298 | 1 << PMA_PMA_LED_ACTIVITY_LBN, true); | |
299 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, | |
dcf477b2 | 300 | SFX7101_PMA_PMD_LED_DEFAULT); |
e6fa2eb7 | 301 | } |
8ceee660 | 302 | |
190dbcfd | 303 | return 0; |
8ceee660 BH |
304 | } |
305 | ||
ff3b00a0 | 306 | static int tenxpress_phy_probe(struct efx_nic *efx) |
c1c4f453 | 307 | { |
ff3b00a0 SH |
308 | struct tenxpress_phy_data *phy_data; |
309 | int rc; | |
310 | ||
311 | /* Allocate phy private storage */ | |
312 | phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL); | |
313 | if (!phy_data) | |
314 | return -ENOMEM; | |
315 | efx->phy_data = phy_data; | |
316 | phy_data->phy_mode = efx->phy_mode; | |
317 | ||
318 | /* Create any special files */ | |
319 | if (efx->phy_type == PHY_TYPE_SFT9001B) { | |
320 | rc = device_create_file(&efx->pci_dev->dev, | |
321 | &dev_attr_phy_short_reach); | |
322 | if (rc) | |
323 | goto fail; | |
324 | } | |
325 | ||
326 | if (efx->phy_type == PHY_TYPE_SFX7101) { | |
327 | efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS; | |
328 | efx->mdio.mode_support = MDIO_SUPPORTS_C45; | |
329 | ||
330 | efx->loopback_modes = SFX7101_LOOPBACKS | FALCON_XMAC_LOOPBACKS; | |
331 | ||
332 | efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg | | |
333 | ADVERTISED_10000baseT_Full); | |
334 | } else { | |
335 | efx->mdio.mmds = TENXPRESS_REQUIRED_DEVS; | |
336 | efx->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22; | |
337 | ||
338 | efx->loopback_modes = (SFT9001_LOOPBACKS | | |
339 | FALCON_XMAC_LOOPBACKS | | |
340 | FALCON_GMAC_LOOPBACKS); | |
341 | ||
342 | efx->link_advertising = (ADVERTISED_TP | ADVERTISED_Autoneg | | |
343 | ADVERTISED_10000baseT_Full | | |
344 | ADVERTISED_1000baseT_Full | | |
345 | ADVERTISED_100baseT_Full); | |
346 | } | |
c1c4f453 | 347 | |
c1c4f453 | 348 | return 0; |
ff3b00a0 SH |
349 | |
350 | fail: | |
351 | kfree(efx->phy_data); | |
352 | efx->phy_data = NULL; | |
353 | return rc; | |
c1c4f453 BH |
354 | } |
355 | ||
8ceee660 BH |
356 | static int tenxpress_phy_init(struct efx_nic *efx) |
357 | { | |
ff3b00a0 | 358 | int rc; |
8ceee660 | 359 | |
44838a44 | 360 | falcon_board(efx)->type->init_phy(efx); |
981fc1b4 | 361 | |
e6fa2eb7 BH |
362 | if (!(efx->phy_mode & PHY_MODE_SPECIAL)) { |
363 | if (efx->phy_type == PHY_TYPE_SFT9001A) { | |
364 | int reg; | |
68e7f45e BH |
365 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
366 | PMA_PMD_XCONTROL_REG); | |
e6fa2eb7 | 367 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
68e7f45e BH |
368 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
369 | PMA_PMD_XCONTROL_REG, reg); | |
e6fa2eb7 BH |
370 | mdelay(200); |
371 | } | |
8ceee660 | 372 | |
68e7f45e | 373 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
e6fa2eb7 | 374 | if (rc < 0) |
ff3b00a0 | 375 | return rc; |
e6fa2eb7 | 376 | |
68e7f45e | 377 | rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0); |
e6fa2eb7 | 378 | if (rc < 0) |
ff3b00a0 | 379 | return rc; |
e6fa2eb7 | 380 | } |
8ceee660 BH |
381 | |
382 | rc = tenxpress_init(efx); | |
383 | if (rc < 0) | |
ff3b00a0 | 384 | return rc; |
8ceee660 | 385 | |
ff3b00a0 | 386 | /* Reinitialise flow control settings */ |
d3245b28 BH |
387 | efx_link_set_wanted_fc(efx, efx->wanted_fc); |
388 | efx_mdio_an_reconfigure(efx); | |
c634263d | 389 | |
8ceee660 BH |
390 | schedule_timeout_uninterruptible(HZ / 5); /* 200ms */ |
391 | ||
e6fa2eb7 | 392 | /* Let XGXS and SerDes out of reset */ |
8ceee660 BH |
393 | falcon_reset_xaui(efx); |
394 | ||
395 | return 0; | |
8ceee660 BH |
396 | } |
397 | ||
e6fa2eb7 BH |
398 | /* Perform a "special software reset" on the PHY. The caller is |
399 | * responsible for saving and restoring the PHY hardware registers | |
400 | * properly, and masking/unmasking LASI */ | |
3273c2e8 BH |
401 | static int tenxpress_special_reset(struct efx_nic *efx) |
402 | { | |
403 | int rc, reg; | |
404 | ||
c8fcc49c BH |
405 | /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so |
406 | * a special software reset can glitch the XGMAC sufficiently for stats | |
1974cc20 | 407 | * requests to fail. */ |
55edc6e6 | 408 | falcon_stop_nic_stats(efx); |
3273c2e8 BH |
409 | |
410 | /* Initiate reset */ | |
68e7f45e | 411 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG); |
3273c2e8 | 412 | reg |= (1 << PMA_PMD_EXT_SSR_LBN); |
68e7f45e | 413 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); |
3273c2e8 | 414 | |
c8fcc49c | 415 | mdelay(200); |
3273c2e8 BH |
416 | |
417 | /* Wait for the blocks to come out of reset */ | |
68e7f45e | 418 | rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS); |
3273c2e8 | 419 | if (rc < 0) |
1974cc20 | 420 | goto out; |
3273c2e8 BH |
421 | |
422 | /* Try and reconfigure the device */ | |
423 | rc = tenxpress_init(efx); | |
424 | if (rc < 0) | |
1974cc20 | 425 | goto out; |
3273c2e8 | 426 | |
e6fa2eb7 BH |
427 | /* Wait for the XGXS state machine to churn */ |
428 | mdelay(10); | |
1974cc20 | 429 | out: |
55edc6e6 | 430 | falcon_start_nic_stats(efx); |
c8fcc49c | 431 | return rc; |
3273c2e8 BH |
432 | } |
433 | ||
e6fa2eb7 | 434 | static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok) |
8ceee660 BH |
435 | { |
436 | struct tenxpress_phy_data *pd = efx->phy_data; | |
04cc8cac | 437 | bool bad_lp; |
8ceee660 BH |
438 | int reg; |
439 | ||
04cc8cac BH |
440 | if (link_ok) { |
441 | bad_lp = false; | |
442 | } else { | |
443 | /* Check that AN has started but not completed. */ | |
68e7f45e BH |
444 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1); |
445 | if (!(reg & MDIO_AN_STAT1_LPABLE)) | |
04cc8cac | 446 | return; /* LP status is unknown */ |
68e7f45e | 447 | bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE); |
04cc8cac BH |
448 | if (bad_lp) |
449 | pd->bad_lp_tries++; | |
450 | } | |
451 | ||
8ceee660 | 452 | /* Nothing to do if all is well and was previously so. */ |
04cc8cac | 453 | if (!pd->bad_lp_tries) |
8ceee660 BH |
454 | return; |
455 | ||
04cc8cac BH |
456 | /* Use the RX (red) LED as an error indicator once we've seen AN |
457 | * failure several times in a row, and also log a message. */ | |
458 | if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) { | |
68e7f45e BH |
459 | reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
460 | PMA_PMD_LED_OVERR_REG); | |
04cc8cac BH |
461 | reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN); |
462 | if (!bad_lp) { | |
463 | reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN; | |
464 | } else { | |
465 | reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN; | |
466 | EFX_ERR(efx, "appears to be plugged into a port" | |
467 | " that is not 10GBASE-T capable. The PHY" | |
468 | " supports 10GBASE-T ONLY, so no link can" | |
469 | " be established\n"); | |
470 | } | |
68e7f45e BH |
471 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, |
472 | PMA_PMD_LED_OVERR_REG, reg); | |
04cc8cac | 473 | pd->bad_lp_tries = bad_lp; |
8ceee660 | 474 | } |
8ceee660 BH |
475 | } |
476 | ||
e6fa2eb7 | 477 | static bool sfx7101_link_ok(struct efx_nic *efx) |
8ceee660 | 478 | { |
68e7f45e BH |
479 | return efx_mdio_links_ok(efx, |
480 | MDIO_DEVS_PMAPMD | | |
481 | MDIO_DEVS_PCS | | |
482 | MDIO_DEVS_PHYXS); | |
e6fa2eb7 BH |
483 | } |
484 | ||
485 | static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
486 | { | |
e6fa2eb7 BH |
487 | u32 reg; |
488 | ||
caa8d8bb | 489 | if (efx_phy_mode_disabled(efx->phy_mode)) |
e6fa2eb7 | 490 | return false; |
caa8d8bb BH |
491 | else if (efx->loopback_mode == LOOPBACK_GPHY) |
492 | return true; | |
e6fa2eb7 | 493 | else if (efx->loopback_mode) |
68e7f45e BH |
494 | return efx_mdio_links_ok(efx, |
495 | MDIO_DEVS_PMAPMD | | |
496 | MDIO_DEVS_PHYXS); | |
e6fa2eb7 BH |
497 | |
498 | /* We must use the same definition of link state as LASI, | |
499 | * otherwise we can miss a link state transition | |
500 | */ | |
501 | if (ecmd->speed == 10000) { | |
68e7f45e BH |
502 | reg = efx_mdio_read(efx, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1); |
503 | return reg & MDIO_PCS_10GBRT_STAT1_BLKLK; | |
e6fa2eb7 | 504 | } else { |
68e7f45e | 505 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_STATUS_REG); |
e6fa2eb7 BH |
506 | return reg & (1 << C22EXT_STATUS_LINK_LBN); |
507 | } | |
8ceee660 BH |
508 | } |
509 | ||
e6fa2eb7 | 510 | static void tenxpress_ext_loopback(struct efx_nic *efx) |
3273c2e8 | 511 | { |
68e7f45e BH |
512 | efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1, |
513 | 1 << LOOPBACK_NEAR_LBN, | |
514 | efx->loopback_mode == LOOPBACK_PHYXS); | |
e6fa2eb7 | 515 | if (efx->phy_type != PHY_TYPE_SFX7101) |
68e7f45e BH |
516 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, GPHY_XCONTROL_REG, |
517 | 1 << GPHY_LOOPBACK_NEAR_LBN, | |
518 | efx->loopback_mode == LOOPBACK_GPHY); | |
e6fa2eb7 BH |
519 | } |
520 | ||
521 | static void tenxpress_low_power(struct efx_nic *efx) | |
522 | { | |
e6fa2eb7 | 523 | if (efx->phy_type == PHY_TYPE_SFX7101) |
68e7f45e | 524 | efx_mdio_set_mmds_lpower( |
e6fa2eb7 BH |
525 | efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER), |
526 | TENXPRESS_REQUIRED_DEVS); | |
3273c2e8 | 527 | else |
68e7f45e BH |
528 | efx_mdio_set_flag( |
529 | efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, | |
530 | 1 << PMA_PMD_EXT_LPOWER_LBN, | |
e6fa2eb7 | 531 | !!(efx->phy_mode & PHY_MODE_LOW_POWER)); |
3273c2e8 BH |
532 | } |
533 | ||
d3245b28 | 534 | static int tenxpress_phy_reconfigure(struct efx_nic *efx) |
8ceee660 | 535 | { |
3273c2e8 | 536 | struct tenxpress_phy_data *phy_data = efx->phy_data; |
8b9dc8dd | 537 | bool phy_mode_change, loop_reset; |
3273c2e8 | 538 | |
e6fa2eb7 | 539 | if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) { |
f8b87c17 | 540 | phy_data->phy_mode = efx->phy_mode; |
d3245b28 | 541 | return 0; |
f8b87c17 | 542 | } |
8ceee660 | 543 | |
e6fa2eb7 BH |
544 | phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL && |
545 | phy_data->phy_mode != PHY_MODE_NORMAL); | |
c1c4f453 | 546 | loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, LOOPBACKS_EXTERNAL(efx)) || |
e6fa2eb7 BH |
547 | LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY)); |
548 | ||
8b9dc8dd | 549 | if (loop_reset || phy_mode_change) { |
d3245b28 | 550 | tenxpress_special_reset(efx); |
e6fa2eb7 | 551 | |
d3245b28 BH |
552 | /* Reset XAUI if we were in 10G, and are staying |
553 | * in 10G. If we're moving into and out of 10G | |
554 | * then xaui will be reset anyway */ | |
555 | if (EFX_IS10G(efx)) | |
556 | falcon_reset_xaui(efx); | |
3273c2e8 BH |
557 | } |
558 | ||
d3245b28 | 559 | tenxpress_low_power(efx); |
68e7f45e BH |
560 | efx_mdio_transmit_disable(efx); |
561 | efx_mdio_phy_reconfigure(efx); | |
e6fa2eb7 | 562 | tenxpress_ext_loopback(efx); |
d3245b28 | 563 | efx_mdio_an_reconfigure(efx); |
3273c2e8 | 564 | |
3273c2e8 | 565 | phy_data->loopback_mode = efx->loopback_mode; |
f8b87c17 | 566 | phy_data->phy_mode = efx->phy_mode; |
d3245b28 BH |
567 | |
568 | return 0; | |
8ceee660 BH |
569 | } |
570 | ||
fdaa9aed SH |
571 | static void |
572 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd); | |
573 | ||
574 | /* Poll for link state changes */ | |
575 | static bool tenxpress_phy_poll(struct efx_nic *efx) | |
8ceee660 | 576 | { |
fdaa9aed | 577 | struct efx_link_state old_state = efx->link_state; |
8ceee660 | 578 | |
e6fa2eb7 | 579 | if (efx->phy_type == PHY_TYPE_SFX7101) { |
fdaa9aed SH |
580 | efx->link_state.up = sfx7101_link_ok(efx); |
581 | efx->link_state.speed = 10000; | |
582 | efx->link_state.fd = true; | |
583 | efx->link_state.fc = efx_mdio_get_pause(efx); | |
584 | ||
585 | sfx7101_check_bad_lp(efx, efx->link_state.up); | |
766ca0fa | 586 | } else { |
fdaa9aed | 587 | struct ethtool_cmd ecmd; |
8ceee660 | 588 | |
fdaa9aed SH |
589 | /* Check the LASI alarm first */ |
590 | if (efx->loopback_mode == LOOPBACK_NONE && | |
591 | !(efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_LASI_STAT) & | |
592 | MDIO_PMA_LASI_LSALARM)) | |
593 | return false; | |
8ceee660 | 594 | |
fdaa9aed SH |
595 | tenxpress_get_settings(efx, &ecmd); |
596 | ||
597 | efx->link_state.up = sft9001_link_ok(efx, &ecmd); | |
598 | efx->link_state.speed = ecmd.speed; | |
599 | efx->link_state.fd = (ecmd.duplex == DUPLEX_FULL); | |
600 | efx->link_state.fc = efx_mdio_get_pause(efx); | |
601 | } | |
602 | ||
603 | return !efx_link_state_equal(&efx->link_state, &old_state); | |
8ceee660 BH |
604 | } |
605 | ||
ff3b00a0 | 606 | static void sfx7101_phy_fini(struct efx_nic *efx) |
8ceee660 BH |
607 | { |
608 | int reg; | |
609 | ||
ff3b00a0 SH |
610 | /* Power down the LNPGA */ |
611 | reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN); | |
612 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg); | |
613 | ||
614 | /* Waiting here ensures that the board fini, which can turn | |
615 | * off the power to the PHY, won't get run until the LNPGA | |
616 | * powerdown has been given long enough to complete. */ | |
617 | schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */ | |
618 | } | |
619 | ||
620 | static void tenxpress_phy_remove(struct efx_nic *efx) | |
621 | { | |
2a7e637d | 622 | if (efx->phy_type == PHY_TYPE_SFT9001B) |
e6fa2eb7 BH |
623 | device_remove_file(&efx->pci_dev->dev, |
624 | &dev_attr_phy_short_reach); | |
2a7e637d | 625 | |
8ceee660 BH |
626 | kfree(efx->phy_data); |
627 | efx->phy_data = NULL; | |
628 | } | |
629 | ||
630 | ||
398468ed BH |
631 | /* Override the RX, TX and link LEDs */ |
632 | void tenxpress_set_id_led(struct efx_nic *efx, enum efx_led_mode mode) | |
8ceee660 BH |
633 | { |
634 | int reg; | |
635 | ||
398468ed BH |
636 | switch (mode) { |
637 | case EFX_LED_OFF: | |
638 | reg = (PMA_PMD_LED_OFF << PMA_PMD_LED_TX_LBN) | | |
639 | (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN) | | |
640 | (PMA_PMD_LED_OFF << PMA_PMD_LED_LINK_LBN); | |
641 | break; | |
642 | case EFX_LED_ON: | |
643 | reg = (PMA_PMD_LED_ON << PMA_PMD_LED_TX_LBN) | | |
644 | (PMA_PMD_LED_ON << PMA_PMD_LED_RX_LBN) | | |
645 | (PMA_PMD_LED_ON << PMA_PMD_LED_LINK_LBN); | |
646 | break; | |
647 | default: | |
dcf477b2 BH |
648 | if (efx->phy_type == PHY_TYPE_SFX7101) |
649 | reg = SFX7101_PMA_PMD_LED_DEFAULT; | |
650 | else | |
651 | reg = SFT9001_PMA_PMD_LED_DEFAULT; | |
398468ed BH |
652 | break; |
653 | } | |
8ceee660 | 654 | |
68e7f45e | 655 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg); |
8ceee660 BH |
656 | } |
657 | ||
307505e9 | 658 | static const char *const sfx7101_test_names[] = { |
1796721a BH |
659 | "bist" |
660 | }; | |
661 | ||
c1c4f453 BH |
662 | static const char *sfx7101_test_name(struct efx_nic *efx, unsigned int index) |
663 | { | |
664 | if (index < ARRAY_SIZE(sfx7101_test_names)) | |
665 | return sfx7101_test_names[index]; | |
666 | return NULL; | |
667 | } | |
668 | ||
1796721a | 669 | static int |
307505e9 | 670 | sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags) |
8c8661e4 | 671 | { |
1796721a BH |
672 | int rc; |
673 | ||
674 | if (!(flags & ETH_TEST_FL_OFFLINE)) | |
675 | return 0; | |
676 | ||
8c8661e4 | 677 | /* BIST is automatically run after a special software reset */ |
1796721a BH |
678 | rc = tenxpress_special_reset(efx); |
679 | results[0] = rc ? -1 : 1; | |
d3245b28 BH |
680 | |
681 | efx_mdio_an_reconfigure(efx); | |
682 | ||
1796721a | 683 | return rc; |
8c8661e4 BH |
684 | } |
685 | ||
307505e9 BH |
686 | static const char *const sft9001_test_names[] = { |
687 | "bist", | |
688 | "cable.pairA.status", | |
689 | "cable.pairB.status", | |
690 | "cable.pairC.status", | |
691 | "cable.pairD.status", | |
692 | "cable.pairA.length", | |
693 | "cable.pairB.length", | |
694 | "cable.pairC.length", | |
695 | "cable.pairD.length", | |
696 | }; | |
697 | ||
c1c4f453 BH |
698 | static const char *sft9001_test_name(struct efx_nic *efx, unsigned int index) |
699 | { | |
700 | if (index < ARRAY_SIZE(sft9001_test_names)) | |
701 | return sft9001_test_names[index]; | |
702 | return NULL; | |
703 | } | |
704 | ||
307505e9 BH |
705 | static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags) |
706 | { | |
22ef02c2 | 707 | int rc = 0, rc2, i, ctrl_reg, res_reg; |
307505e9 | 708 | |
307505e9 BH |
709 | /* Initialise cable diagnostic results to unknown failure */ |
710 | for (i = 1; i < 9; ++i) | |
711 | results[i] = -1; | |
712 | ||
713 | /* Run cable diagnostics; wait up to 5 seconds for them to complete. | |
714 | * A cable fault is not a self-test failure, but a timeout is. */ | |
22ef02c2 BH |
715 | ctrl_reg = ((1 << CDIAG_CTRL_IMMED_LBN) | |
716 | (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN)); | |
717 | if (flags & ETH_TEST_FL_OFFLINE) { | |
718 | /* Break the link in order to run full diagnostics. We | |
719 | * must reset the PHY to resume normal service. */ | |
720 | ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN); | |
721 | } | |
68e7f45e BH |
722 | efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG, |
723 | ctrl_reg); | |
307505e9 | 724 | i = 0; |
68e7f45e | 725 | while (efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG) & |
307505e9 BH |
726 | (1 << CDIAG_CTRL_IN_PROG_LBN)) { |
727 | if (++i == 50) { | |
728 | rc = -ETIMEDOUT; | |
22ef02c2 | 729 | goto out; |
307505e9 BH |
730 | } |
731 | msleep(100); | |
732 | } | |
68e7f45e | 733 | res_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_RES_REG); |
307505e9 BH |
734 | for (i = 0; i < 4; i++) { |
735 | int pair_res = | |
736 | (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH)) | |
737 | & ((1 << CDIAG_RES_WIDTH) - 1); | |
68e7f45e BH |
738 | int len_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, |
739 | PMA_PMD_CDIAG_LEN_REG + i); | |
307505e9 BH |
740 | if (pair_res == CDIAG_RES_OK) |
741 | results[1 + i] = 1; | |
742 | else if (pair_res == CDIAG_RES_INVALID) | |
743 | results[1 + i] = -1; | |
744 | else | |
745 | results[1 + i] = -pair_res; | |
746 | if (pair_res != CDIAG_RES_INVALID && | |
747 | pair_res != CDIAG_RES_OPEN && | |
748 | len_reg != 0xffff) | |
749 | results[5 + i] = len_reg; | |
750 | } | |
751 | ||
22ef02c2 BH |
752 | out: |
753 | if (flags & ETH_TEST_FL_OFFLINE) { | |
754 | /* Reset, running the BIST and then resuming normal service. */ | |
755 | rc2 = tenxpress_special_reset(efx); | |
756 | results[0] = rc2 ? -1 : 1; | |
757 | if (!rc) | |
758 | rc = rc2; | |
759 | ||
d3245b28 | 760 | efx_mdio_an_reconfigure(efx); |
22ef02c2 | 761 | } |
307505e9 BH |
762 | |
763 | return rc; | |
764 | } | |
765 | ||
af4ad9bc BH |
766 | static void |
767 | tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) | |
04cc8cac | 768 | { |
af4ad9bc | 769 | u32 adv = 0, lpa = 0; |
04cc8cac BH |
770 | int reg; |
771 | ||
e6fa2eb7 | 772 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
68e7f45e | 773 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL); |
af4ad9bc BH |
774 | if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN)) |
775 | adv |= ADVERTISED_1000baseT_Full; | |
68e7f45e | 776 | reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_STATUS); |
af4ad9bc | 777 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN)) |
e6fa2eb7 | 778 | lpa |= ADVERTISED_1000baseT_Half; |
af4ad9bc | 779 | if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN)) |
e6fa2eb7 BH |
780 | lpa |= ADVERTISED_1000baseT_Full; |
781 | } | |
68e7f45e BH |
782 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL); |
783 | if (reg & MDIO_AN_10GBT_CTRL_ADV10G) | |
af4ad9bc | 784 | adv |= ADVERTISED_10000baseT_Full; |
68e7f45e BH |
785 | reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); |
786 | if (reg & MDIO_AN_10GBT_STAT_LP10G) | |
04cc8cac | 787 | lpa |= ADVERTISED_10000baseT_Full; |
04cc8cac | 788 | |
68e7f45e | 789 | mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa); |
e6fa2eb7 | 790 | |
e762cd70 | 791 | if (efx->phy_type != PHY_TYPE_SFX7101) { |
af4ad9bc BH |
792 | ecmd->supported |= (SUPPORTED_100baseT_Full | |
793 | SUPPORTED_1000baseT_Full); | |
e762cd70 BH |
794 | if (ecmd->speed != SPEED_10000) { |
795 | ecmd->eth_tp_mdix = | |
796 | (efx_mdio_read(efx, MDIO_MMD_PMAPMD, | |
797 | PMA_PMD_XSTATUS_REG) & | |
798 | (1 << PMA_PMD_XSTAT_MDIX_LBN)) | |
799 | ? ETH_TP_MDI_X : ETH_TP_MDI; | |
800 | } | |
801 | } | |
8b9dc8dd SH |
802 | |
803 | /* In loopback, the PHY automatically brings up the correct interface, | |
804 | * but doesn't advertise the correct speed. So override it */ | |
805 | if (efx->loopback_mode == LOOPBACK_GPHY) | |
806 | ecmd->speed = SPEED_1000; | |
c1c4f453 | 807 | else if (LOOPBACK_EXTERNAL(efx)) |
8b9dc8dd | 808 | ecmd->speed = SPEED_10000; |
04cc8cac BH |
809 | } |
810 | ||
af4ad9bc | 811 | static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd) |
e6fa2eb7 | 812 | { |
af4ad9bc BH |
813 | if (!ecmd->autoneg) |
814 | return -EINVAL; | |
e6fa2eb7 | 815 | |
68e7f45e | 816 | return efx_mdio_set_settings(efx, ecmd); |
e6fa2eb7 BH |
817 | } |
818 | ||
af4ad9bc | 819 | static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 820 | { |
68e7f45e BH |
821 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, |
822 | MDIO_AN_10GBT_CTRL_ADV10G, | |
823 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
824 | } |
825 | ||
af4ad9bc | 826 | static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising) |
e6fa2eb7 | 827 | { |
68e7f45e BH |
828 | efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL, |
829 | 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN, | |
830 | advertising & ADVERTISED_1000baseT_Full); | |
831 | efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, | |
832 | MDIO_AN_10GBT_CTRL_ADV10G, | |
833 | advertising & ADVERTISED_10000baseT_Full); | |
e6fa2eb7 BH |
834 | } |
835 | ||
836 | struct efx_phy_operations falcon_sfx7101_phy_ops = { | |
ff3b00a0 | 837 | .probe = tenxpress_phy_probe, |
8ceee660 BH |
838 | .init = tenxpress_phy_init, |
839 | .reconfigure = tenxpress_phy_reconfigure, | |
766ca0fa | 840 | .poll = tenxpress_phy_poll, |
ff3b00a0 SH |
841 | .fini = sfx7101_phy_fini, |
842 | .remove = tenxpress_phy_remove, | |
af4ad9bc BH |
843 | .get_settings = tenxpress_get_settings, |
844 | .set_settings = tenxpress_set_settings, | |
845 | .set_npage_adv = sfx7101_set_npage_adv, | |
4f16c073 | 846 | .test_alive = efx_mdio_test_alive, |
c1c4f453 | 847 | .test_name = sfx7101_test_name, |
307505e9 | 848 | .run_tests = sfx7101_run_tests, |
e6fa2eb7 BH |
849 | }; |
850 | ||
851 | struct efx_phy_operations falcon_sft9001_phy_ops = { | |
ff3b00a0 | 852 | .probe = tenxpress_phy_probe, |
e6fa2eb7 BH |
853 | .init = tenxpress_phy_init, |
854 | .reconfigure = tenxpress_phy_reconfigure, | |
855 | .poll = tenxpress_phy_poll, | |
ff3b00a0 SH |
856 | .fini = efx_port_dummy_op_void, |
857 | .remove = tenxpress_phy_remove, | |
af4ad9bc BH |
858 | .get_settings = tenxpress_get_settings, |
859 | .set_settings = tenxpress_set_settings, | |
860 | .set_npage_adv = sft9001_set_npage_adv, | |
4f16c073 | 861 | .test_alive = efx_mdio_test_alive, |
c1c4f453 | 862 | .test_name = sft9001_test_name, |
307505e9 | 863 | .run_tests = sft9001_run_tests, |
8ceee660 | 864 | }; |