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8ceee660 BH |
1 | /**************************************************************************** |
2 | * Driver for Solarflare Solarstorm network controllers and boards | |
3 | * Copyright 2005-2006 Fen Systems Ltd. | |
906bb26c | 4 | * Copyright 2005-2009 Solarflare Communications Inc. |
8ceee660 BH |
5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | |
7 | * under the terms of the GNU General Public License version 2 as published | |
8 | * by the Free Software Foundation, incorporated herein by reference. | |
9 | */ | |
10 | ||
11 | #include <linux/pci.h> | |
12 | #include <linux/tcp.h> | |
13 | #include <linux/ip.h> | |
14 | #include <linux/in.h> | |
738a8f4b | 15 | #include <linux/ipv6.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
738a8f4b | 17 | #include <net/ipv6.h> |
8ceee660 BH |
18 | #include <linux/if_ether.h> |
19 | #include <linux/highmem.h> | |
20 | #include "net_driver.h" | |
8ceee660 | 21 | #include "efx.h" |
744093c9 | 22 | #include "nic.h" |
8ceee660 BH |
23 | #include "workarounds.h" |
24 | ||
25 | /* | |
26 | * TX descriptor ring full threshold | |
27 | * | |
28 | * The tx_queue descriptor ring fill-level must fall below this value | |
29 | * before we restart the netif queue | |
30 | */ | |
ecc910f5 | 31 | #define EFX_TXQ_THRESHOLD(_efx) ((_efx)->txq_entries / 2u) |
8ceee660 | 32 | |
4d566063 BH |
33 | static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue, |
34 | struct efx_tx_buffer *buffer) | |
8ceee660 BH |
35 | { |
36 | if (buffer->unmap_len) { | |
37 | struct pci_dev *pci_dev = tx_queue->efx->pci_dev; | |
cc12dac2 BH |
38 | dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len - |
39 | buffer->unmap_len); | |
8ceee660 | 40 | if (buffer->unmap_single) |
cc12dac2 BH |
41 | pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len, |
42 | PCI_DMA_TODEVICE); | |
8ceee660 | 43 | else |
cc12dac2 BH |
44 | pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len, |
45 | PCI_DMA_TODEVICE); | |
8ceee660 | 46 | buffer->unmap_len = 0; |
dc8cfa55 | 47 | buffer->unmap_single = false; |
8ceee660 BH |
48 | } |
49 | ||
50 | if (buffer->skb) { | |
51 | dev_kfree_skb_any((struct sk_buff *) buffer->skb); | |
52 | buffer->skb = NULL; | |
62776d03 BH |
53 | netif_vdbg(tx_queue->efx, tx_done, tx_queue->efx->net_dev, |
54 | "TX queue %d transmission id %x complete\n", | |
55 | tx_queue->queue, tx_queue->read_count); | |
8ceee660 BH |
56 | } |
57 | } | |
58 | ||
b9b39b62 BH |
59 | /** |
60 | * struct efx_tso_header - a DMA mapped buffer for packet headers | |
61 | * @next: Linked list of free ones. | |
62 | * The list is protected by the TX queue lock. | |
63 | * @dma_unmap_len: Length to unmap for an oversize buffer, or 0. | |
64 | * @dma_addr: The DMA address of the header below. | |
65 | * | |
66 | * This controls the memory used for a TSO header. Use TSOH_DATA() | |
67 | * to find the packet header data. Use TSOH_SIZE() to calculate the | |
68 | * total size required for a given packet header length. TSO headers | |
69 | * in the free list are exactly %TSOH_STD_SIZE bytes in size. | |
70 | */ | |
71 | struct efx_tso_header { | |
72 | union { | |
73 | struct efx_tso_header *next; | |
74 | size_t unmap_len; | |
75 | }; | |
76 | dma_addr_t dma_addr; | |
77 | }; | |
78 | ||
79 | static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, | |
740847da | 80 | struct sk_buff *skb); |
b9b39b62 BH |
81 | static void efx_fini_tso(struct efx_tx_queue *tx_queue); |
82 | static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, | |
83 | struct efx_tso_header *tsoh); | |
84 | ||
4d566063 BH |
85 | static void efx_tsoh_free(struct efx_tx_queue *tx_queue, |
86 | struct efx_tx_buffer *buffer) | |
b9b39b62 BH |
87 | { |
88 | if (buffer->tsoh) { | |
89 | if (likely(!buffer->tsoh->unmap_len)) { | |
90 | buffer->tsoh->next = tx_queue->tso_headers_free; | |
91 | tx_queue->tso_headers_free = buffer->tsoh; | |
92 | } else { | |
93 | efx_tsoh_heap_free(tx_queue, buffer->tsoh); | |
94 | } | |
95 | buffer->tsoh = NULL; | |
96 | } | |
97 | } | |
98 | ||
8ceee660 | 99 | |
63f19884 BH |
100 | static inline unsigned |
101 | efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr) | |
102 | { | |
103 | /* Depending on the NIC revision, we can use descriptor | |
104 | * lengths up to 8K or 8K-1. However, since PCI Express | |
105 | * devices must split read requests at 4K boundaries, there is | |
106 | * little benefit from using descriptors that cross those | |
107 | * boundaries and we keep things simple by not doing so. | |
108 | */ | |
109 | unsigned len = (~dma_addr & 0xfff) + 1; | |
110 | ||
111 | /* Work around hardware bug for unaligned buffers. */ | |
112 | if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf)) | |
113 | len = min_t(unsigned, len, 512 - (dma_addr & 0xf)); | |
114 | ||
115 | return len; | |
116 | } | |
117 | ||
8ceee660 BH |
118 | /* |
119 | * Add a socket buffer to a TX queue | |
120 | * | |
121 | * This maps all fragments of a socket buffer for DMA and adds them to | |
122 | * the TX queue. The queue's insert pointer will be incremented by | |
123 | * the number of fragments in the socket buffer. | |
124 | * | |
125 | * If any DMA mapping fails, any mapped fragments will be unmapped, | |
126 | * the queue's insert pointer will be restored to its original value. | |
127 | * | |
497f5ba3 BH |
128 | * This function is split out from efx_hard_start_xmit to allow the |
129 | * loopback test to direct packets via specific TX queues. | |
130 | * | |
8ceee660 BH |
131 | * Returns NETDEV_TX_OK or NETDEV_TX_BUSY |
132 | * You must hold netif_tx_lock() to call this function. | |
133 | */ | |
497f5ba3 | 134 | netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb) |
8ceee660 BH |
135 | { |
136 | struct efx_nic *efx = tx_queue->efx; | |
137 | struct pci_dev *pci_dev = efx->pci_dev; | |
138 | struct efx_tx_buffer *buffer; | |
139 | skb_frag_t *fragment; | |
140 | struct page *page; | |
141 | int page_offset; | |
63f19884 | 142 | unsigned int len, unmap_len = 0, fill_level, insert_ptr; |
8ceee660 BH |
143 | dma_addr_t dma_addr, unmap_addr = 0; |
144 | unsigned int dma_len; | |
dc8cfa55 | 145 | bool unmap_single; |
8ceee660 | 146 | int q_space, i = 0; |
61357325 | 147 | netdev_tx_t rc = NETDEV_TX_OK; |
8ceee660 BH |
148 | |
149 | EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count); | |
150 | ||
9bc183d7 | 151 | if (skb_shinfo(skb)->gso_size) |
b9b39b62 BH |
152 | return efx_enqueue_skb_tso(tx_queue, skb); |
153 | ||
8ceee660 BH |
154 | /* Get size of the initial fragment */ |
155 | len = skb_headlen(skb); | |
156 | ||
bb145a9e BH |
157 | /* Pad if necessary */ |
158 | if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) { | |
159 | EFX_BUG_ON_PARANOID(skb->data_len); | |
160 | len = 32 + 1; | |
161 | if (skb_pad(skb, len - skb->len)) | |
162 | return NETDEV_TX_OK; | |
163 | } | |
164 | ||
8ceee660 | 165 | fill_level = tx_queue->insert_count - tx_queue->old_read_count; |
ecc910f5 | 166 | q_space = efx->txq_entries - 1 - fill_level; |
8ceee660 BH |
167 | |
168 | /* Map for DMA. Use pci_map_single rather than pci_map_page | |
169 | * since this is more efficient on machines with sparse | |
170 | * memory. | |
171 | */ | |
dc8cfa55 | 172 | unmap_single = true; |
8ceee660 BH |
173 | dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE); |
174 | ||
175 | /* Process all fragments */ | |
176 | while (1) { | |
8d8bb39b | 177 | if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr))) |
8ceee660 BH |
178 | goto pci_err; |
179 | ||
180 | /* Store fields for marking in the per-fragment final | |
181 | * descriptor */ | |
182 | unmap_len = len; | |
183 | unmap_addr = dma_addr; | |
184 | ||
185 | /* Add to TX queue, splitting across DMA boundaries */ | |
186 | do { | |
187 | if (unlikely(q_space-- <= 0)) { | |
188 | /* It might be that completions have | |
189 | * happened since the xmit path last | |
190 | * checked. Update the xmit path's | |
191 | * copy of read_count. | |
192 | */ | |
c04bfc6b | 193 | netif_tx_stop_queue(tx_queue->core_txq); |
8ceee660 | 194 | /* This memory barrier protects the |
c04bfc6b | 195 | * change of queue state from the access |
8ceee660 BH |
196 | * of read_count. */ |
197 | smp_mb(); | |
198 | tx_queue->old_read_count = | |
51c56f40 | 199 | ACCESS_ONCE(tx_queue->read_count); |
8ceee660 BH |
200 | fill_level = (tx_queue->insert_count |
201 | - tx_queue->old_read_count); | |
ecc910f5 | 202 | q_space = efx->txq_entries - 1 - fill_level; |
c04bfc6b BH |
203 | if (unlikely(q_space-- <= 0)) { |
204 | rc = NETDEV_TX_BUSY; | |
205 | goto unwind; | |
206 | } | |
8ceee660 | 207 | smp_mb(); |
c04bfc6b | 208 | netif_tx_start_queue(tx_queue->core_txq); |
8ceee660 BH |
209 | } |
210 | ||
ecc910f5 | 211 | insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask; |
8ceee660 | 212 | buffer = &tx_queue->buffer[insert_ptr]; |
b9b39b62 BH |
213 | efx_tsoh_free(tx_queue, buffer); |
214 | EFX_BUG_ON_PARANOID(buffer->tsoh); | |
8ceee660 BH |
215 | EFX_BUG_ON_PARANOID(buffer->skb); |
216 | EFX_BUG_ON_PARANOID(buffer->len); | |
dc8cfa55 | 217 | EFX_BUG_ON_PARANOID(!buffer->continuation); |
8ceee660 BH |
218 | EFX_BUG_ON_PARANOID(buffer->unmap_len); |
219 | ||
63f19884 BH |
220 | dma_len = efx_max_tx_len(efx, dma_addr); |
221 | if (likely(dma_len >= len)) | |
8ceee660 BH |
222 | dma_len = len; |
223 | ||
8ceee660 BH |
224 | /* Fill out per descriptor fields */ |
225 | buffer->len = dma_len; | |
226 | buffer->dma_addr = dma_addr; | |
227 | len -= dma_len; | |
228 | dma_addr += dma_len; | |
229 | ++tx_queue->insert_count; | |
230 | } while (len); | |
231 | ||
232 | /* Transfer ownership of the unmapping to the final buffer */ | |
8ceee660 BH |
233 | buffer->unmap_single = unmap_single; |
234 | buffer->unmap_len = unmap_len; | |
235 | unmap_len = 0; | |
236 | ||
237 | /* Get address and size of next fragment */ | |
238 | if (i >= skb_shinfo(skb)->nr_frags) | |
239 | break; | |
240 | fragment = &skb_shinfo(skb)->frags[i]; | |
241 | len = fragment->size; | |
242 | page = fragment->page; | |
243 | page_offset = fragment->page_offset; | |
244 | i++; | |
245 | /* Map for DMA */ | |
dc8cfa55 | 246 | unmap_single = false; |
8ceee660 BH |
247 | dma_addr = pci_map_page(pci_dev, page, page_offset, len, |
248 | PCI_DMA_TODEVICE); | |
249 | } | |
250 | ||
251 | /* Transfer ownership of the skb to the final buffer */ | |
252 | buffer->skb = skb; | |
dc8cfa55 | 253 | buffer->continuation = false; |
8ceee660 BH |
254 | |
255 | /* Pass off to hardware */ | |
152b6a62 | 256 | efx_nic_push_buffers(tx_queue); |
8ceee660 BH |
257 | |
258 | return NETDEV_TX_OK; | |
259 | ||
260 | pci_err: | |
62776d03 BH |
261 | netif_err(efx, tx_err, efx->net_dev, |
262 | " TX queue %d could not map skb with %d bytes %d " | |
263 | "fragments for DMA\n", tx_queue->queue, skb->len, | |
264 | skb_shinfo(skb)->nr_frags + 1); | |
8ceee660 BH |
265 | |
266 | /* Mark the packet as transmitted, and free the SKB ourselves */ | |
9bc183d7 | 267 | dev_kfree_skb_any(skb); |
8ceee660 BH |
268 | |
269 | unwind: | |
270 | /* Work backwards until we hit the original insert pointer value */ | |
271 | while (tx_queue->insert_count != tx_queue->write_count) { | |
272 | --tx_queue->insert_count; | |
ecc910f5 | 273 | insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask; |
8ceee660 BH |
274 | buffer = &tx_queue->buffer[insert_ptr]; |
275 | efx_dequeue_buffer(tx_queue, buffer); | |
276 | buffer->len = 0; | |
277 | } | |
278 | ||
279 | /* Free the fragment we were mid-way through pushing */ | |
ecbd95c1 BH |
280 | if (unmap_len) { |
281 | if (unmap_single) | |
282 | pci_unmap_single(pci_dev, unmap_addr, unmap_len, | |
283 | PCI_DMA_TODEVICE); | |
284 | else | |
285 | pci_unmap_page(pci_dev, unmap_addr, unmap_len, | |
286 | PCI_DMA_TODEVICE); | |
287 | } | |
8ceee660 BH |
288 | |
289 | return rc; | |
290 | } | |
291 | ||
292 | /* Remove packets from the TX queue | |
293 | * | |
294 | * This removes packets from the TX queue, up to and including the | |
295 | * specified index. | |
296 | */ | |
4d566063 BH |
297 | static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue, |
298 | unsigned int index) | |
8ceee660 BH |
299 | { |
300 | struct efx_nic *efx = tx_queue->efx; | |
301 | unsigned int stop_index, read_ptr; | |
8ceee660 | 302 | |
ecc910f5 SH |
303 | stop_index = (index + 1) & tx_queue->ptr_mask; |
304 | read_ptr = tx_queue->read_count & tx_queue->ptr_mask; | |
8ceee660 BH |
305 | |
306 | while (read_ptr != stop_index) { | |
307 | struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr]; | |
308 | if (unlikely(buffer->len == 0)) { | |
62776d03 BH |
309 | netif_err(efx, tx_err, efx->net_dev, |
310 | "TX queue %d spurious TX completion id %x\n", | |
311 | tx_queue->queue, read_ptr); | |
8ceee660 BH |
312 | efx_schedule_reset(efx, RESET_TYPE_TX_SKIP); |
313 | return; | |
314 | } | |
315 | ||
316 | efx_dequeue_buffer(tx_queue, buffer); | |
dc8cfa55 | 317 | buffer->continuation = true; |
8ceee660 BH |
318 | buffer->len = 0; |
319 | ||
320 | ++tx_queue->read_count; | |
ecc910f5 | 321 | read_ptr = tx_queue->read_count & tx_queue->ptr_mask; |
8ceee660 BH |
322 | } |
323 | } | |
324 | ||
8ceee660 BH |
325 | /* Initiate a packet transmission. We use one channel per CPU |
326 | * (sharing when we have more CPUs than channels). On Falcon, the TX | |
327 | * completion events will be directed back to the CPU that transmitted | |
328 | * the packet, which should be cache-efficient. | |
329 | * | |
330 | * Context: non-blocking. | |
331 | * Note that returning anything other than NETDEV_TX_OK will cause the | |
332 | * OS to free the skb. | |
333 | */ | |
61357325 SH |
334 | netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb, |
335 | struct net_device *net_dev) | |
8ceee660 | 336 | { |
767e468c | 337 | struct efx_nic *efx = netdev_priv(net_dev); |
60ac1065 BH |
338 | struct efx_tx_queue *tx_queue; |
339 | ||
a7ef5933 BH |
340 | if (unlikely(efx->port_inhibited)) |
341 | return NETDEV_TX_BUSY; | |
342 | ||
f7d12cdc BH |
343 | tx_queue = efx_get_tx_queue(efx, skb_get_queue_mapping(skb), |
344 | skb->ip_summed == CHECKSUM_PARTIAL ? | |
345 | EFX_TXQ_TYPE_OFFLOAD : 0); | |
60ac1065 | 346 | |
497f5ba3 | 347 | return efx_enqueue_skb(tx_queue, skb); |
8ceee660 BH |
348 | } |
349 | ||
60031fcc BH |
350 | void efx_init_tx_queue_core_txq(struct efx_tx_queue *tx_queue) |
351 | { | |
352 | /* Must be inverse of queue lookup in efx_hard_start_xmit() */ | |
353 | tx_queue->core_txq = netdev_get_tx_queue( | |
354 | tx_queue->efx->net_dev, tx_queue->queue / EFX_TXQ_TYPES); | |
355 | } | |
356 | ||
8ceee660 BH |
357 | void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index) |
358 | { | |
359 | unsigned fill_level; | |
360 | struct efx_nic *efx = tx_queue->efx; | |
361 | ||
ecc910f5 | 362 | EFX_BUG_ON_PARANOID(index > tx_queue->ptr_mask); |
8ceee660 BH |
363 | |
364 | efx_dequeue_buffers(tx_queue, index); | |
365 | ||
366 | /* See if we need to restart the netif queue. This barrier | |
c04bfc6b BH |
367 | * separates the update of read_count from the test of the |
368 | * queue state. */ | |
8ceee660 | 369 | smp_mb(); |
c04bfc6b BH |
370 | if (unlikely(netif_tx_queue_stopped(tx_queue->core_txq)) && |
371 | likely(efx->port_enabled)) { | |
8ceee660 | 372 | fill_level = tx_queue->insert_count - tx_queue->read_count; |
ecc910f5 | 373 | if (fill_level < EFX_TXQ_THRESHOLD(efx)) { |
55668611 | 374 | EFX_BUG_ON_PARANOID(!efx_dev_registered(efx)); |
c04bfc6b | 375 | netif_tx_wake_queue(tx_queue->core_txq); |
8ceee660 BH |
376 | } |
377 | } | |
cd38557d BH |
378 | |
379 | /* Check whether the hardware queue is now empty */ | |
380 | if ((int)(tx_queue->read_count - tx_queue->old_write_count) >= 0) { | |
381 | tx_queue->old_write_count = ACCESS_ONCE(tx_queue->write_count); | |
382 | if (tx_queue->read_count == tx_queue->old_write_count) { | |
383 | smp_mb(); | |
384 | tx_queue->empty_read_count = | |
385 | tx_queue->read_count | EFX_EMPTY_COUNT_VALID; | |
386 | } | |
387 | } | |
8ceee660 BH |
388 | } |
389 | ||
390 | int efx_probe_tx_queue(struct efx_tx_queue *tx_queue) | |
391 | { | |
392 | struct efx_nic *efx = tx_queue->efx; | |
ecc910f5 | 393 | unsigned int entries; |
8ceee660 BH |
394 | int i, rc; |
395 | ||
ecc910f5 SH |
396 | /* Create the smallest power-of-two aligned ring */ |
397 | entries = max(roundup_pow_of_two(efx->txq_entries), EFX_MIN_DMAQ_SIZE); | |
398 | EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE); | |
399 | tx_queue->ptr_mask = entries - 1; | |
400 | ||
401 | netif_dbg(efx, probe, efx->net_dev, | |
402 | "creating TX queue %d size %#x mask %#x\n", | |
403 | tx_queue->queue, efx->txq_entries, tx_queue->ptr_mask); | |
8ceee660 BH |
404 | |
405 | /* Allocate software ring */ | |
ecc910f5 SH |
406 | tx_queue->buffer = kzalloc(entries * sizeof(*tx_queue->buffer), |
407 | GFP_KERNEL); | |
60ac1065 BH |
408 | if (!tx_queue->buffer) |
409 | return -ENOMEM; | |
ecc910f5 | 410 | for (i = 0; i <= tx_queue->ptr_mask; ++i) |
dc8cfa55 | 411 | tx_queue->buffer[i].continuation = true; |
8ceee660 BH |
412 | |
413 | /* Allocate hardware ring */ | |
152b6a62 | 414 | rc = efx_nic_probe_tx(tx_queue); |
8ceee660 | 415 | if (rc) |
60ac1065 | 416 | goto fail; |
8ceee660 BH |
417 | |
418 | return 0; | |
419 | ||
60ac1065 | 420 | fail: |
8ceee660 BH |
421 | kfree(tx_queue->buffer); |
422 | tx_queue->buffer = NULL; | |
8ceee660 BH |
423 | return rc; |
424 | } | |
425 | ||
bc3c90a2 | 426 | void efx_init_tx_queue(struct efx_tx_queue *tx_queue) |
8ceee660 | 427 | { |
62776d03 BH |
428 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
429 | "initialising TX queue %d\n", tx_queue->queue); | |
8ceee660 BH |
430 | |
431 | tx_queue->insert_count = 0; | |
432 | tx_queue->write_count = 0; | |
cd38557d | 433 | tx_queue->old_write_count = 0; |
8ceee660 BH |
434 | tx_queue->read_count = 0; |
435 | tx_queue->old_read_count = 0; | |
cd38557d | 436 | tx_queue->empty_read_count = 0 | EFX_EMPTY_COUNT_VALID; |
8ceee660 BH |
437 | |
438 | /* Set up TX descriptor ring */ | |
152b6a62 | 439 | efx_nic_init_tx(tx_queue); |
8ceee660 BH |
440 | } |
441 | ||
442 | void efx_release_tx_buffers(struct efx_tx_queue *tx_queue) | |
443 | { | |
444 | struct efx_tx_buffer *buffer; | |
445 | ||
446 | if (!tx_queue->buffer) | |
447 | return; | |
448 | ||
449 | /* Free any buffers left in the ring */ | |
450 | while (tx_queue->read_count != tx_queue->write_count) { | |
ecc910f5 | 451 | buffer = &tx_queue->buffer[tx_queue->read_count & tx_queue->ptr_mask]; |
8ceee660 | 452 | efx_dequeue_buffer(tx_queue, buffer); |
dc8cfa55 | 453 | buffer->continuation = true; |
8ceee660 BH |
454 | buffer->len = 0; |
455 | ||
456 | ++tx_queue->read_count; | |
457 | } | |
458 | } | |
459 | ||
460 | void efx_fini_tx_queue(struct efx_tx_queue *tx_queue) | |
461 | { | |
62776d03 BH |
462 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
463 | "shutting down TX queue %d\n", tx_queue->queue); | |
8ceee660 BH |
464 | |
465 | /* Flush TX queue, remove descriptor ring */ | |
152b6a62 | 466 | efx_nic_fini_tx(tx_queue); |
8ceee660 BH |
467 | |
468 | efx_release_tx_buffers(tx_queue); | |
469 | ||
b9b39b62 BH |
470 | /* Free up TSO header cache */ |
471 | efx_fini_tso(tx_queue); | |
8ceee660 BH |
472 | } |
473 | ||
474 | void efx_remove_tx_queue(struct efx_tx_queue *tx_queue) | |
475 | { | |
62776d03 BH |
476 | netif_dbg(tx_queue->efx, drv, tx_queue->efx->net_dev, |
477 | "destroying TX queue %d\n", tx_queue->queue); | |
152b6a62 | 478 | efx_nic_remove_tx(tx_queue); |
8ceee660 BH |
479 | |
480 | kfree(tx_queue->buffer); | |
481 | tx_queue->buffer = NULL; | |
8ceee660 BH |
482 | } |
483 | ||
484 | ||
b9b39b62 BH |
485 | /* Efx TCP segmentation acceleration. |
486 | * | |
487 | * Why? Because by doing it here in the driver we can go significantly | |
488 | * faster than the GSO. | |
489 | * | |
490 | * Requires TX checksum offload support. | |
491 | */ | |
492 | ||
493 | /* Number of bytes inserted at the start of a TSO header buffer, | |
494 | * similar to NET_IP_ALIGN. | |
495 | */ | |
13e9ab11 | 496 | #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
b9b39b62 BH |
497 | #define TSOH_OFFSET 0 |
498 | #else | |
499 | #define TSOH_OFFSET NET_IP_ALIGN | |
500 | #endif | |
501 | ||
502 | #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET) | |
503 | ||
504 | /* Total size of struct efx_tso_header, buffer and padding */ | |
505 | #define TSOH_SIZE(hdr_len) \ | |
506 | (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len) | |
507 | ||
508 | /* Size of blocks on free list. Larger blocks must be allocated from | |
509 | * the heap. | |
510 | */ | |
511 | #define TSOH_STD_SIZE 128 | |
512 | ||
513 | #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2)) | |
514 | #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data) | |
515 | #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data) | |
516 | #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data) | |
738a8f4b | 517 | #define SKB_IPV6_OFF(skb) PTR_DIFF(ipv6_hdr(skb), (skb)->data) |
b9b39b62 BH |
518 | |
519 | /** | |
520 | * struct tso_state - TSO state for an SKB | |
23d9e60b | 521 | * @out_len: Remaining length in current segment |
b9b39b62 | 522 | * @seqnum: Current sequence number |
23d9e60b | 523 | * @ipv4_id: Current IPv4 ID, host endian |
b9b39b62 | 524 | * @packet_space: Remaining space in current packet |
23d9e60b BH |
525 | * @dma_addr: DMA address of current position |
526 | * @in_len: Remaining length in current SKB fragment | |
527 | * @unmap_len: Length of SKB fragment | |
528 | * @unmap_addr: DMA address of SKB fragment | |
529 | * @unmap_single: DMA single vs page mapping flag | |
738a8f4b | 530 | * @protocol: Network protocol (after any VLAN header) |
23d9e60b BH |
531 | * @header_len: Number of bytes of header |
532 | * @full_packet_size: Number of bytes to put in each outgoing segment | |
b9b39b62 BH |
533 | * |
534 | * The state used during segmentation. It is put into this data structure | |
535 | * just to make it easy to pass into inline functions. | |
536 | */ | |
537 | struct tso_state { | |
23d9e60b BH |
538 | /* Output position */ |
539 | unsigned out_len; | |
b9b39b62 | 540 | unsigned seqnum; |
23d9e60b | 541 | unsigned ipv4_id; |
b9b39b62 BH |
542 | unsigned packet_space; |
543 | ||
23d9e60b BH |
544 | /* Input position */ |
545 | dma_addr_t dma_addr; | |
546 | unsigned in_len; | |
547 | unsigned unmap_len; | |
548 | dma_addr_t unmap_addr; | |
549 | bool unmap_single; | |
550 | ||
738a8f4b | 551 | __be16 protocol; |
23d9e60b BH |
552 | unsigned header_len; |
553 | int full_packet_size; | |
b9b39b62 BH |
554 | }; |
555 | ||
556 | ||
557 | /* | |
558 | * Verify that our various assumptions about sk_buffs and the conditions | |
738a8f4b | 559 | * under which TSO will be attempted hold true. Return the protocol number. |
b9b39b62 | 560 | */ |
738a8f4b | 561 | static __be16 efx_tso_check_protocol(struct sk_buff *skb) |
b9b39b62 | 562 | { |
740847da BH |
563 | __be16 protocol = skb->protocol; |
564 | ||
b9b39b62 | 565 | EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto != |
740847da BH |
566 | protocol); |
567 | if (protocol == htons(ETH_P_8021Q)) { | |
568 | /* Find the encapsulated protocol; reset network header | |
569 | * and transport header based on that. */ | |
570 | struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data; | |
571 | protocol = veh->h_vlan_encapsulated_proto; | |
572 | skb_set_network_header(skb, sizeof(*veh)); | |
573 | if (protocol == htons(ETH_P_IP)) | |
574 | skb_set_transport_header(skb, sizeof(*veh) + | |
575 | 4 * ip_hdr(skb)->ihl); | |
738a8f4b BH |
576 | else if (protocol == htons(ETH_P_IPV6)) |
577 | skb_set_transport_header(skb, sizeof(*veh) + | |
578 | sizeof(struct ipv6hdr)); | |
740847da BH |
579 | } |
580 | ||
738a8f4b BH |
581 | if (protocol == htons(ETH_P_IP)) { |
582 | EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP); | |
583 | } else { | |
584 | EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IPV6)); | |
585 | EFX_BUG_ON_PARANOID(ipv6_hdr(skb)->nexthdr != NEXTHDR_TCP); | |
586 | } | |
b9b39b62 BH |
587 | EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data) |
588 | + (tcp_hdr(skb)->doff << 2u)) > | |
589 | skb_headlen(skb)); | |
738a8f4b BH |
590 | |
591 | return protocol; | |
b9b39b62 BH |
592 | } |
593 | ||
594 | ||
595 | /* | |
596 | * Allocate a page worth of efx_tso_header structures, and string them | |
597 | * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM. | |
598 | */ | |
599 | static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue) | |
600 | { | |
601 | ||
602 | struct pci_dev *pci_dev = tx_queue->efx->pci_dev; | |
603 | struct efx_tso_header *tsoh; | |
604 | dma_addr_t dma_addr; | |
605 | u8 *base_kva, *kva; | |
606 | ||
607 | base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr); | |
608 | if (base_kva == NULL) { | |
62776d03 BH |
609 | netif_err(tx_queue->efx, tx_err, tx_queue->efx->net_dev, |
610 | "Unable to allocate page for TSO headers\n"); | |
b9b39b62 BH |
611 | return -ENOMEM; |
612 | } | |
613 | ||
614 | /* pci_alloc_consistent() allocates pages. */ | |
615 | EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u)); | |
616 | ||
617 | for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) { | |
618 | tsoh = (struct efx_tso_header *)kva; | |
619 | tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva); | |
620 | tsoh->next = tx_queue->tso_headers_free; | |
621 | tx_queue->tso_headers_free = tsoh; | |
622 | } | |
623 | ||
624 | return 0; | |
625 | } | |
626 | ||
627 | ||
628 | /* Free up a TSO header, and all others in the same page. */ | |
629 | static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue, | |
630 | struct efx_tso_header *tsoh, | |
631 | struct pci_dev *pci_dev) | |
632 | { | |
633 | struct efx_tso_header **p; | |
634 | unsigned long base_kva; | |
635 | dma_addr_t base_dma; | |
636 | ||
637 | base_kva = (unsigned long)tsoh & PAGE_MASK; | |
638 | base_dma = tsoh->dma_addr & PAGE_MASK; | |
639 | ||
640 | p = &tx_queue->tso_headers_free; | |
b3475645 | 641 | while (*p != NULL) { |
b9b39b62 BH |
642 | if (((unsigned long)*p & PAGE_MASK) == base_kva) |
643 | *p = (*p)->next; | |
644 | else | |
645 | p = &(*p)->next; | |
b3475645 | 646 | } |
b9b39b62 BH |
647 | |
648 | pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma); | |
649 | } | |
650 | ||
651 | static struct efx_tso_header * | |
652 | efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len) | |
653 | { | |
654 | struct efx_tso_header *tsoh; | |
655 | ||
656 | tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA); | |
657 | if (unlikely(!tsoh)) | |
658 | return NULL; | |
659 | ||
660 | tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev, | |
661 | TSOH_BUFFER(tsoh), header_len, | |
662 | PCI_DMA_TODEVICE); | |
8d8bb39b FT |
663 | if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev, |
664 | tsoh->dma_addr))) { | |
b9b39b62 BH |
665 | kfree(tsoh); |
666 | return NULL; | |
667 | } | |
668 | ||
669 | tsoh->unmap_len = header_len; | |
670 | return tsoh; | |
671 | } | |
672 | ||
673 | static void | |
674 | efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh) | |
675 | { | |
676 | pci_unmap_single(tx_queue->efx->pci_dev, | |
677 | tsoh->dma_addr, tsoh->unmap_len, | |
678 | PCI_DMA_TODEVICE); | |
679 | kfree(tsoh); | |
680 | } | |
681 | ||
682 | /** | |
683 | * efx_tx_queue_insert - push descriptors onto the TX queue | |
684 | * @tx_queue: Efx TX queue | |
685 | * @dma_addr: DMA address of fragment | |
686 | * @len: Length of fragment | |
ecbd95c1 | 687 | * @final_buffer: The final buffer inserted into the queue |
b9b39b62 BH |
688 | * |
689 | * Push descriptors onto the TX queue. Return 0 on success or 1 if | |
690 | * @tx_queue full. | |
691 | */ | |
692 | static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue, | |
693 | dma_addr_t dma_addr, unsigned len, | |
ecbd95c1 | 694 | struct efx_tx_buffer **final_buffer) |
b9b39b62 BH |
695 | { |
696 | struct efx_tx_buffer *buffer; | |
697 | struct efx_nic *efx = tx_queue->efx; | |
63f19884 | 698 | unsigned dma_len, fill_level, insert_ptr; |
b9b39b62 BH |
699 | int q_space; |
700 | ||
701 | EFX_BUG_ON_PARANOID(len <= 0); | |
702 | ||
703 | fill_level = tx_queue->insert_count - tx_queue->old_read_count; | |
704 | /* -1 as there is no way to represent all descriptors used */ | |
ecc910f5 | 705 | q_space = efx->txq_entries - 1 - fill_level; |
b9b39b62 BH |
706 | |
707 | while (1) { | |
708 | if (unlikely(q_space-- <= 0)) { | |
709 | /* It might be that completions have happened | |
710 | * since the xmit path last checked. Update | |
711 | * the xmit path's copy of read_count. | |
712 | */ | |
c04bfc6b | 713 | netif_tx_stop_queue(tx_queue->core_txq); |
b9b39b62 | 714 | /* This memory barrier protects the change of |
c04bfc6b | 715 | * queue state from the access of read_count. */ |
b9b39b62 BH |
716 | smp_mb(); |
717 | tx_queue->old_read_count = | |
51c56f40 | 718 | ACCESS_ONCE(tx_queue->read_count); |
b9b39b62 BH |
719 | fill_level = (tx_queue->insert_count |
720 | - tx_queue->old_read_count); | |
ecc910f5 | 721 | q_space = efx->txq_entries - 1 - fill_level; |
ecbd95c1 BH |
722 | if (unlikely(q_space-- <= 0)) { |
723 | *final_buffer = NULL; | |
b9b39b62 | 724 | return 1; |
ecbd95c1 | 725 | } |
b9b39b62 | 726 | smp_mb(); |
c04bfc6b | 727 | netif_tx_start_queue(tx_queue->core_txq); |
b9b39b62 BH |
728 | } |
729 | ||
ecc910f5 | 730 | insert_ptr = tx_queue->insert_count & tx_queue->ptr_mask; |
b9b39b62 BH |
731 | buffer = &tx_queue->buffer[insert_ptr]; |
732 | ++tx_queue->insert_count; | |
733 | ||
734 | EFX_BUG_ON_PARANOID(tx_queue->insert_count - | |
ecc910f5 SH |
735 | tx_queue->read_count >= |
736 | efx->txq_entries); | |
b9b39b62 BH |
737 | |
738 | efx_tsoh_free(tx_queue, buffer); | |
739 | EFX_BUG_ON_PARANOID(buffer->len); | |
740 | EFX_BUG_ON_PARANOID(buffer->unmap_len); | |
741 | EFX_BUG_ON_PARANOID(buffer->skb); | |
dc8cfa55 | 742 | EFX_BUG_ON_PARANOID(!buffer->continuation); |
b9b39b62 BH |
743 | EFX_BUG_ON_PARANOID(buffer->tsoh); |
744 | ||
745 | buffer->dma_addr = dma_addr; | |
746 | ||
63f19884 | 747 | dma_len = efx_max_tx_len(efx, dma_addr); |
b9b39b62 BH |
748 | |
749 | /* If there is enough space to send then do so */ | |
750 | if (dma_len >= len) | |
751 | break; | |
752 | ||
753 | buffer->len = dma_len; /* Don't set the other members */ | |
754 | dma_addr += dma_len; | |
755 | len -= dma_len; | |
756 | } | |
757 | ||
758 | EFX_BUG_ON_PARANOID(!len); | |
759 | buffer->len = len; | |
ecbd95c1 | 760 | *final_buffer = buffer; |
b9b39b62 BH |
761 | return 0; |
762 | } | |
763 | ||
764 | ||
765 | /* | |
766 | * Put a TSO header into the TX queue. | |
767 | * | |
768 | * This is special-cased because we know that it is small enough to fit in | |
769 | * a single fragment, and we know it doesn't cross a page boundary. It | |
770 | * also allows us to not worry about end-of-packet etc. | |
771 | */ | |
4d566063 BH |
772 | static void efx_tso_put_header(struct efx_tx_queue *tx_queue, |
773 | struct efx_tso_header *tsoh, unsigned len) | |
b9b39b62 BH |
774 | { |
775 | struct efx_tx_buffer *buffer; | |
776 | ||
ecc910f5 | 777 | buffer = &tx_queue->buffer[tx_queue->insert_count & tx_queue->ptr_mask]; |
b9b39b62 BH |
778 | efx_tsoh_free(tx_queue, buffer); |
779 | EFX_BUG_ON_PARANOID(buffer->len); | |
780 | EFX_BUG_ON_PARANOID(buffer->unmap_len); | |
781 | EFX_BUG_ON_PARANOID(buffer->skb); | |
dc8cfa55 | 782 | EFX_BUG_ON_PARANOID(!buffer->continuation); |
b9b39b62 BH |
783 | EFX_BUG_ON_PARANOID(buffer->tsoh); |
784 | buffer->len = len; | |
785 | buffer->dma_addr = tsoh->dma_addr; | |
786 | buffer->tsoh = tsoh; | |
787 | ||
788 | ++tx_queue->insert_count; | |
789 | } | |
790 | ||
791 | ||
792 | /* Remove descriptors put into a tx_queue. */ | |
793 | static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue) | |
794 | { | |
795 | struct efx_tx_buffer *buffer; | |
cc12dac2 | 796 | dma_addr_t unmap_addr; |
b9b39b62 BH |
797 | |
798 | /* Work backwards until we hit the original insert pointer value */ | |
799 | while (tx_queue->insert_count != tx_queue->write_count) { | |
800 | --tx_queue->insert_count; | |
801 | buffer = &tx_queue->buffer[tx_queue->insert_count & | |
ecc910f5 | 802 | tx_queue->ptr_mask]; |
b9b39b62 BH |
803 | efx_tsoh_free(tx_queue, buffer); |
804 | EFX_BUG_ON_PARANOID(buffer->skb); | |
b9b39b62 | 805 | if (buffer->unmap_len) { |
cc12dac2 BH |
806 | unmap_addr = (buffer->dma_addr + buffer->len - |
807 | buffer->unmap_len); | |
ecbd95c1 BH |
808 | if (buffer->unmap_single) |
809 | pci_unmap_single(tx_queue->efx->pci_dev, | |
cc12dac2 | 810 | unmap_addr, buffer->unmap_len, |
ecbd95c1 BH |
811 | PCI_DMA_TODEVICE); |
812 | else | |
813 | pci_unmap_page(tx_queue->efx->pci_dev, | |
cc12dac2 | 814 | unmap_addr, buffer->unmap_len, |
ecbd95c1 | 815 | PCI_DMA_TODEVICE); |
b9b39b62 BH |
816 | buffer->unmap_len = 0; |
817 | } | |
a7ebd27a NT |
818 | buffer->len = 0; |
819 | buffer->continuation = true; | |
b9b39b62 BH |
820 | } |
821 | } | |
822 | ||
823 | ||
824 | /* Parse the SKB header and initialise state. */ | |
4d566063 | 825 | static void tso_start(struct tso_state *st, const struct sk_buff *skb) |
b9b39b62 BH |
826 | { |
827 | /* All ethernet/IP/TCP headers combined size is TCP header size | |
828 | * plus offset of TCP header relative to start of packet. | |
829 | */ | |
23d9e60b BH |
830 | st->header_len = ((tcp_hdr(skb)->doff << 2u) |
831 | + PTR_DIFF(tcp_hdr(skb), skb->data)); | |
832 | st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size; | |
b9b39b62 | 833 | |
738a8f4b BH |
834 | if (st->protocol == htons(ETH_P_IP)) |
835 | st->ipv4_id = ntohs(ip_hdr(skb)->id); | |
836 | else | |
837 | st->ipv4_id = 0; | |
b9b39b62 BH |
838 | st->seqnum = ntohl(tcp_hdr(skb)->seq); |
839 | ||
840 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg); | |
841 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn); | |
842 | EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst); | |
843 | ||
23d9e60b BH |
844 | st->packet_space = st->full_packet_size; |
845 | st->out_len = skb->len - st->header_len; | |
846 | st->unmap_len = 0; | |
847 | st->unmap_single = false; | |
b9b39b62 BH |
848 | } |
849 | ||
4d566063 BH |
850 | static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx, |
851 | skb_frag_t *frag) | |
b9b39b62 | 852 | { |
23d9e60b BH |
853 | st->unmap_addr = pci_map_page(efx->pci_dev, frag->page, |
854 | frag->page_offset, frag->size, | |
855 | PCI_DMA_TODEVICE); | |
856 | if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) { | |
857 | st->unmap_single = false; | |
858 | st->unmap_len = frag->size; | |
859 | st->in_len = frag->size; | |
860 | st->dma_addr = st->unmap_addr; | |
ecbd95c1 BH |
861 | return 0; |
862 | } | |
863 | return -ENOMEM; | |
864 | } | |
865 | ||
4d566063 BH |
866 | static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx, |
867 | const struct sk_buff *skb) | |
ecbd95c1 | 868 | { |
23d9e60b | 869 | int hl = st->header_len; |
ecbd95c1 | 870 | int len = skb_headlen(skb) - hl; |
b9b39b62 | 871 | |
23d9e60b BH |
872 | st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl, |
873 | len, PCI_DMA_TODEVICE); | |
874 | if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) { | |
875 | st->unmap_single = true; | |
876 | st->unmap_len = len; | |
877 | st->in_len = len; | |
878 | st->dma_addr = st->unmap_addr; | |
b9b39b62 BH |
879 | return 0; |
880 | } | |
881 | return -ENOMEM; | |
882 | } | |
883 | ||
884 | ||
885 | /** | |
886 | * tso_fill_packet_with_fragment - form descriptors for the current fragment | |
887 | * @tx_queue: Efx TX queue | |
888 | * @skb: Socket buffer | |
889 | * @st: TSO state | |
890 | * | |
891 | * Form descriptors for the current fragment, until we reach the end | |
892 | * of fragment or end-of-packet. Return 0 on success, 1 if not enough | |
893 | * space in @tx_queue. | |
894 | */ | |
4d566063 BH |
895 | static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue, |
896 | const struct sk_buff *skb, | |
897 | struct tso_state *st) | |
b9b39b62 | 898 | { |
ecbd95c1 | 899 | struct efx_tx_buffer *buffer; |
b9b39b62 BH |
900 | int n, end_of_packet, rc; |
901 | ||
23d9e60b | 902 | if (st->in_len == 0) |
b9b39b62 BH |
903 | return 0; |
904 | if (st->packet_space == 0) | |
905 | return 0; | |
906 | ||
23d9e60b | 907 | EFX_BUG_ON_PARANOID(st->in_len <= 0); |
b9b39b62 BH |
908 | EFX_BUG_ON_PARANOID(st->packet_space <= 0); |
909 | ||
23d9e60b | 910 | n = min(st->in_len, st->packet_space); |
b9b39b62 BH |
911 | |
912 | st->packet_space -= n; | |
23d9e60b BH |
913 | st->out_len -= n; |
914 | st->in_len -= n; | |
b9b39b62 | 915 | |
23d9e60b | 916 | rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer); |
ecbd95c1 | 917 | if (likely(rc == 0)) { |
23d9e60b | 918 | if (st->out_len == 0) |
ecbd95c1 BH |
919 | /* Transfer ownership of the skb */ |
920 | buffer->skb = skb; | |
b9b39b62 | 921 | |
23d9e60b | 922 | end_of_packet = st->out_len == 0 || st->packet_space == 0; |
ecbd95c1 | 923 | buffer->continuation = !end_of_packet; |
b9b39b62 | 924 | |
23d9e60b | 925 | if (st->in_len == 0) { |
ecbd95c1 | 926 | /* Transfer ownership of the pci mapping */ |
23d9e60b BH |
927 | buffer->unmap_len = st->unmap_len; |
928 | buffer->unmap_single = st->unmap_single; | |
929 | st->unmap_len = 0; | |
ecbd95c1 BH |
930 | } |
931 | } | |
932 | ||
23d9e60b | 933 | st->dma_addr += n; |
b9b39b62 BH |
934 | return rc; |
935 | } | |
936 | ||
937 | ||
938 | /** | |
939 | * tso_start_new_packet - generate a new header and prepare for the new packet | |
940 | * @tx_queue: Efx TX queue | |
941 | * @skb: Socket buffer | |
942 | * @st: TSO state | |
943 | * | |
944 | * Generate a new header and prepare for the new packet. Return 0 on | |
945 | * success, or -1 if failed to alloc header. | |
946 | */ | |
4d566063 BH |
947 | static int tso_start_new_packet(struct efx_tx_queue *tx_queue, |
948 | const struct sk_buff *skb, | |
949 | struct tso_state *st) | |
b9b39b62 BH |
950 | { |
951 | struct efx_tso_header *tsoh; | |
b9b39b62 BH |
952 | struct tcphdr *tsoh_th; |
953 | unsigned ip_length; | |
954 | u8 *header; | |
955 | ||
956 | /* Allocate a DMA-mapped header buffer. */ | |
23d9e60b | 957 | if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) { |
b3475645 | 958 | if (tx_queue->tso_headers_free == NULL) { |
b9b39b62 BH |
959 | if (efx_tsoh_block_alloc(tx_queue)) |
960 | return -1; | |
b3475645 | 961 | } |
b9b39b62 BH |
962 | EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free); |
963 | tsoh = tx_queue->tso_headers_free; | |
964 | tx_queue->tso_headers_free = tsoh->next; | |
965 | tsoh->unmap_len = 0; | |
966 | } else { | |
967 | tx_queue->tso_long_headers++; | |
23d9e60b | 968 | tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len); |
b9b39b62 BH |
969 | if (unlikely(!tsoh)) |
970 | return -1; | |
971 | } | |
972 | ||
973 | header = TSOH_BUFFER(tsoh); | |
974 | tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb)); | |
b9b39b62 BH |
975 | |
976 | /* Copy and update the headers. */ | |
23d9e60b | 977 | memcpy(header, skb->data, st->header_len); |
b9b39b62 BH |
978 | |
979 | tsoh_th->seq = htonl(st->seqnum); | |
980 | st->seqnum += skb_shinfo(skb)->gso_size; | |
23d9e60b | 981 | if (st->out_len > skb_shinfo(skb)->gso_size) { |
b9b39b62 | 982 | /* This packet will not finish the TSO burst. */ |
23d9e60b | 983 | ip_length = st->full_packet_size - ETH_HDR_LEN(skb); |
b9b39b62 BH |
984 | tsoh_th->fin = 0; |
985 | tsoh_th->psh = 0; | |
986 | } else { | |
987 | /* This packet will be the last in the TSO burst. */ | |
23d9e60b | 988 | ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len; |
b9b39b62 BH |
989 | tsoh_th->fin = tcp_hdr(skb)->fin; |
990 | tsoh_th->psh = tcp_hdr(skb)->psh; | |
991 | } | |
b9b39b62 | 992 | |
738a8f4b BH |
993 | if (st->protocol == htons(ETH_P_IP)) { |
994 | struct iphdr *tsoh_iph = | |
995 | (struct iphdr *)(header + SKB_IPV4_OFF(skb)); | |
996 | ||
997 | tsoh_iph->tot_len = htons(ip_length); | |
998 | ||
999 | /* Linux leaves suitable gaps in the IP ID space for us to fill. */ | |
1000 | tsoh_iph->id = htons(st->ipv4_id); | |
1001 | st->ipv4_id++; | |
1002 | } else { | |
1003 | struct ipv6hdr *tsoh_iph = | |
1004 | (struct ipv6hdr *)(header + SKB_IPV6_OFF(skb)); | |
1005 | ||
1006 | tsoh_iph->payload_len = htons(ip_length - sizeof(*tsoh_iph)); | |
1007 | } | |
b9b39b62 BH |
1008 | |
1009 | st->packet_space = skb_shinfo(skb)->gso_size; | |
1010 | ++tx_queue->tso_packets; | |
1011 | ||
1012 | /* Form a descriptor for this header. */ | |
23d9e60b | 1013 | efx_tso_put_header(tx_queue, tsoh, st->header_len); |
b9b39b62 BH |
1014 | |
1015 | return 0; | |
1016 | } | |
1017 | ||
1018 | ||
1019 | /** | |
1020 | * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer | |
1021 | * @tx_queue: Efx TX queue | |
1022 | * @skb: Socket buffer | |
1023 | * | |
1024 | * Context: You must hold netif_tx_lock() to call this function. | |
1025 | * | |
1026 | * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if | |
1027 | * @skb was not enqueued. In all cases @skb is consumed. Return | |
1028 | * %NETDEV_TX_OK or %NETDEV_TX_BUSY. | |
1029 | */ | |
1030 | static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue, | |
740847da | 1031 | struct sk_buff *skb) |
b9b39b62 | 1032 | { |
ecbd95c1 | 1033 | struct efx_nic *efx = tx_queue->efx; |
b9b39b62 BH |
1034 | int frag_i, rc, rc2 = NETDEV_TX_OK; |
1035 | struct tso_state state; | |
b9b39b62 | 1036 | |
738a8f4b BH |
1037 | /* Find the packet protocol and sanity-check it */ |
1038 | state.protocol = efx_tso_check_protocol(skb); | |
b9b39b62 BH |
1039 | |
1040 | EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count); | |
1041 | ||
1042 | tso_start(&state, skb); | |
1043 | ||
1044 | /* Assume that skb header area contains exactly the headers, and | |
1045 | * all payload is in the frag list. | |
1046 | */ | |
23d9e60b | 1047 | if (skb_headlen(skb) == state.header_len) { |
b9b39b62 BH |
1048 | /* Grab the first payload fragment. */ |
1049 | EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1); | |
1050 | frag_i = 0; | |
ecbd95c1 BH |
1051 | rc = tso_get_fragment(&state, efx, |
1052 | skb_shinfo(skb)->frags + frag_i); | |
b9b39b62 BH |
1053 | if (rc) |
1054 | goto mem_err; | |
1055 | } else { | |
ecbd95c1 | 1056 | rc = tso_get_head_fragment(&state, efx, skb); |
b9b39b62 BH |
1057 | if (rc) |
1058 | goto mem_err; | |
1059 | frag_i = -1; | |
1060 | } | |
1061 | ||
1062 | if (tso_start_new_packet(tx_queue, skb, &state) < 0) | |
1063 | goto mem_err; | |
1064 | ||
1065 | while (1) { | |
1066 | rc = tso_fill_packet_with_fragment(tx_queue, skb, &state); | |
c04bfc6b BH |
1067 | if (unlikely(rc)) { |
1068 | rc2 = NETDEV_TX_BUSY; | |
1069 | goto unwind; | |
1070 | } | |
b9b39b62 BH |
1071 | |
1072 | /* Move onto the next fragment? */ | |
23d9e60b | 1073 | if (state.in_len == 0) { |
b9b39b62 BH |
1074 | if (++frag_i >= skb_shinfo(skb)->nr_frags) |
1075 | /* End of payload reached. */ | |
1076 | break; | |
ecbd95c1 BH |
1077 | rc = tso_get_fragment(&state, efx, |
1078 | skb_shinfo(skb)->frags + frag_i); | |
b9b39b62 BH |
1079 | if (rc) |
1080 | goto mem_err; | |
1081 | } | |
1082 | ||
1083 | /* Start at new packet? */ | |
1084 | if (state.packet_space == 0 && | |
1085 | tso_start_new_packet(tx_queue, skb, &state) < 0) | |
1086 | goto mem_err; | |
1087 | } | |
1088 | ||
1089 | /* Pass off to hardware */ | |
152b6a62 | 1090 | efx_nic_push_buffers(tx_queue); |
b9b39b62 BH |
1091 | |
1092 | tx_queue->tso_bursts++; | |
1093 | return NETDEV_TX_OK; | |
1094 | ||
1095 | mem_err: | |
62776d03 BH |
1096 | netif_err(efx, tx_err, efx->net_dev, |
1097 | "Out of memory for TSO headers, or PCI mapping error\n"); | |
9bc183d7 | 1098 | dev_kfree_skb_any(skb); |
b9b39b62 BH |
1099 | |
1100 | unwind: | |
5988b63a | 1101 | /* Free the DMA mapping we were in the process of writing out */ |
23d9e60b BH |
1102 | if (state.unmap_len) { |
1103 | if (state.unmap_single) | |
1104 | pci_unmap_single(efx->pci_dev, state.unmap_addr, | |
1105 | state.unmap_len, PCI_DMA_TODEVICE); | |
ecbd95c1 | 1106 | else |
23d9e60b BH |
1107 | pci_unmap_page(efx->pci_dev, state.unmap_addr, |
1108 | state.unmap_len, PCI_DMA_TODEVICE); | |
ecbd95c1 | 1109 | } |
5988b63a | 1110 | |
b9b39b62 BH |
1111 | efx_enqueue_unwind(tx_queue); |
1112 | return rc2; | |
1113 | } | |
1114 | ||
1115 | ||
1116 | /* | |
1117 | * Free up all TSO datastructures associated with tx_queue. This | |
1118 | * routine should be called only once the tx_queue is both empty and | |
1119 | * will no longer be used. | |
1120 | */ | |
1121 | static void efx_fini_tso(struct efx_tx_queue *tx_queue) | |
1122 | { | |
1123 | unsigned i; | |
1124 | ||
b3475645 | 1125 | if (tx_queue->buffer) { |
ecc910f5 | 1126 | for (i = 0; i <= tx_queue->ptr_mask; ++i) |
b9b39b62 | 1127 | efx_tsoh_free(tx_queue, &tx_queue->buffer[i]); |
b3475645 | 1128 | } |
b9b39b62 BH |
1129 | |
1130 | while (tx_queue->tso_headers_free != NULL) | |
1131 | efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free, | |
1132 | tx_queue->efx->pci_dev); | |
1133 | } |