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86a74ff2
NI		 1/*
2 * SuperH Ethernet device driver
3 *
b0ca2a21 4 * Copyright (C) 2006-2008 Nobuhiro Iwamatsu
380af9e3 5 * Copyright (C) 2008-2009 Renesas Solutions Corp.
86a74ff2
NI		 6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * The full GNU General Public License is included in this distribution in
20 * the file called "COPYING".
21 */
22
86a74ff2
NI		 23#include <linux/init.h>
24#include <linux/dma-mapping.h>
25#include <linux/etherdevice.h>
26#include <linux/delay.h>
27#include <linux/platform_device.h>
28#include <linux/mdio-bitbang.h>
29#include <linux/netdevice.h>
30#include <linux/phy.h>
31#include <linux/cache.h>
32#include <linux/io.h>
bcd5149d 33#include <linux/pm_runtime.h>
5a0e3ad6 34#include <linux/slab.h>
dc19e4e5 35#include <linux/ethtool.h>
f568a926 36#include <asm/cacheflush.h>
86a74ff2
NI		 37
38#include "sh_eth.h"
39
dc19e4e5
NI		 40#define SH_ETH_DEF_MSG_ENABLE \
41 (NETIF_MSG_LINK | \
42 NETIF_MSG_TIMER | \
43 NETIF_MSG_RX_ERR| \
44 NETIF_MSG_TX_ERR)
45
380af9e3 46/* There is CPU dependent code */
65ac8851
YS		 47#if defined(CONFIG_CPU_SUBTYPE_SH7724)
48#define SH_ETH_RESET_DEFAULT 1
49static void sh_eth_set_duplex(struct net_device *ndev)
50{
51 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 52
53 if (mdp->duplex) /* Full */
4a55530f 54 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
65ac8851 55 else /* Half */
4a55530f 56 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
65ac8851
YS		 57}
58
59static void sh_eth_set_rate(struct net_device *ndev)
60{
61 struct sh_eth_private *mdp = netdev_priv(ndev);
65ac8851
YS		 62
63 switch (mdp->speed) {
64 case 10: /* 10BASE */
4a55530f 65 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_RTM, ECMR);
65ac8851
YS		 66 break;
67 case 100:/* 100BASE */
4a55530f 68 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_RTM, ECMR);
65ac8851
YS		 69 break;
70 default:
71 break;
72 }
73}
74
75/* SH7724 */
76static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
77 .set_duplex = sh_eth_set_duplex,
78 .set_rate = sh_eth_set_rate,
79
80 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
81 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
82 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x01ff009f,
83
84 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
85 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
86 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
87 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
88
89 .apr = 1,
90 .mpr = 1,
91 .tpauser = 1,
92 .hw_swap = 1,
503914cf
MD		 93 .rpadir = 1,
94 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
65ac8851 95};
f29a3d04 96#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
8fcd4961
YS		 97#define SH_ETH_HAS_BOTH_MODULES 1
98#define SH_ETH_HAS_TSU 1
f29a3d04
YS		 99static void sh_eth_set_duplex(struct net_device *ndev)
100{
101 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 102
103 if (mdp->duplex) /* Full */
4a55530f 104 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
f29a3d04 105 else /* Half */
4a55530f 106 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
f29a3d04
YS		 107}
108
109static void sh_eth_set_rate(struct net_device *ndev)
110{
111 struct sh_eth_private *mdp = netdev_priv(ndev);
f29a3d04
YS		 112
113 switch (mdp->speed) {
114 case 10: /* 10BASE */
4a55530f 115 sh_eth_write(ndev, 0, RTRATE);
f29a3d04
YS		 116 break;
117 case 100:/* 100BASE */
4a55530f 118 sh_eth_write(ndev, 1, RTRATE);
f29a3d04
YS		 119 break;
120 default:
121 break;
122 }
123}
124
125/* SH7757 */
126static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
127 .set_duplex = sh_eth_set_duplex,
128 .set_rate = sh_eth_set_rate,
129
130 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
131 .rmcr_value = 0x00000001,
132
133 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
134 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE |
135 EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI,
136 .tx_error_check = EESR_TWB | EESR_TABT | EESR_TDE | EESR_TFE,
137
138 .apr = 1,
139 .mpr = 1,
140 .tpauser = 1,
141 .hw_swap = 1,
142 .no_ade = 1,
143};
65ac8851 144
8fcd4961
YS		 145#define SH_GIGA_ETH_BASE 0xfee00000
146#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
147#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
148static void sh_eth_chip_reset_giga(struct net_device *ndev)
149{
150 int i;
151 unsigned long mahr[2], malr[2];
152
153 /* save MAHR and MALR */
154 for (i = 0; i < 2; i++) {
155 malr[i] = readl(GIGA_MALR(i));
156 mahr[i] = readl(GIGA_MAHR(i));
157 }
158
159 /* reset device */
160 writel(ARSTR_ARSTR, SH_GIGA_ETH_BASE + 0x1800);
161 mdelay(1);
162
163 /* restore MAHR and MALR */
164 for (i = 0; i < 2; i++) {
165 writel(malr[i], GIGA_MALR(i));
166 writel(mahr[i], GIGA_MAHR(i));
167 }
168}
169
170static int sh_eth_is_gether(struct sh_eth_private *mdp);
171static void sh_eth_reset(struct net_device *ndev)
172{
173 struct sh_eth_private *mdp = netdev_priv(ndev);
174 int cnt = 100;
175
176 if (sh_eth_is_gether(mdp)) {
177 sh_eth_write(ndev, 0x03, EDSR);
178 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER,
179 EDMR);
180 while (cnt > 0) {
181 if (!(sh_eth_read(ndev, EDMR) & 0x3))
182 break;
183 mdelay(1);
184 cnt--;
185 }
186 if (cnt < 0)
187 printk(KERN_ERR "Device reset fail\n");
188
189 /* Table Init */
190 sh_eth_write(ndev, 0x0, TDLAR);
191 sh_eth_write(ndev, 0x0, TDFAR);
192 sh_eth_write(ndev, 0x0, TDFXR);
193 sh_eth_write(ndev, 0x0, TDFFR);
194 sh_eth_write(ndev, 0x0, RDLAR);
195 sh_eth_write(ndev, 0x0, RDFAR);
196 sh_eth_write(ndev, 0x0, RDFXR);
197 sh_eth_write(ndev, 0x0, RDFFR);
198 } else {
199 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER,
200 EDMR);
201 mdelay(3);
202 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER,
203 EDMR);
204 }
205}
206
207static void sh_eth_set_duplex_giga(struct net_device *ndev)
208{
209 struct sh_eth_private *mdp = netdev_priv(ndev);
210
211 if (mdp->duplex) /* Full */
212 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
213 else /* Half */
214 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
215}
216
217static void sh_eth_set_rate_giga(struct net_device *ndev)
218{
219 struct sh_eth_private *mdp = netdev_priv(ndev);
220
221 switch (mdp->speed) {
222 case 10: /* 10BASE */
223 sh_eth_write(ndev, 0x00000000, GECMR);
224 break;
225 case 100:/* 100BASE */
226 sh_eth_write(ndev, 0x00000010, GECMR);
227 break;
228 case 1000: /* 1000BASE */
229 sh_eth_write(ndev, 0x00000020, GECMR);
230 break;
231 default:
232 break;
233 }
234}
235
236/* SH7757(GETHERC) */
237static struct sh_eth_cpu_data sh_eth_my_cpu_data_giga = {
238 .chip_reset = sh_eth_chip_reset_giga,
239 .set_duplex = sh_eth_set_duplex_giga,
240 .set_rate = sh_eth_set_rate_giga,
241
242 .ecsr_value = ECSR_ICD | ECSR_MPD,
243 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
244 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
245
246 .tx_check = EESR_TC1 | EESR_FTC,
247 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
248 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
249 EESR_ECI,
250 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
251 EESR_TFE,
252 .fdr_value = 0x0000072f,
253 .rmcr_value = 0x00000001,
254
255 .apr = 1,
256 .mpr = 1,
257 .tpauser = 1,
258 .bculr = 1,
259 .hw_swap = 1,
260 .rpadir = 1,
261 .rpadir_value = 2 << 16,
262 .no_trimd = 1,
263 .no_ade = 1,
264};
265
266static struct sh_eth_cpu_data *sh_eth_get_cpu_data(struct sh_eth_private *mdp)
267{
268 if (sh_eth_is_gether(mdp))
269 return &sh_eth_my_cpu_data_giga;
270 else
271 return &sh_eth_my_cpu_data;
272}
273
65ac8851 274#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
380af9e3
YS		 275#define SH_ETH_HAS_TSU 1
276static void sh_eth_chip_reset(struct net_device *ndev)
277{
4986b996
YS		 278 struct sh_eth_private *mdp = netdev_priv(ndev);
279
380af9e3 280 /* reset device */
4986b996 281 sh_eth_tsu_write(mdp, ARSTR_ARSTR, ARSTR);
380af9e3
YS		 282 mdelay(1);
283}
284
285static void sh_eth_reset(struct net_device *ndev)
286{
380af9e3
YS		 287 int cnt = 100;
288
4a55530f 289 sh_eth_write(ndev, EDSR_ENALL, EDSR);
c5ed5368 290 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_GETHER, EDMR);
380af9e3 291 while (cnt > 0) {
4a55530f 292 if (!(sh_eth_read(ndev, EDMR) & 0x3))
380af9e3
YS		 293 break;
294 mdelay(1);
295 cnt--;
296 }
890c8c18 297 if (cnt == 0)
380af9e3
YS		 298 printk(KERN_ERR "Device reset fail\n");
299
300 /* Table Init */
4a55530f
YS		 301 sh_eth_write(ndev, 0x0, TDLAR);
302 sh_eth_write(ndev, 0x0, TDFAR);
303 sh_eth_write(ndev, 0x0, TDFXR);
304 sh_eth_write(ndev, 0x0, TDFFR);
305 sh_eth_write(ndev, 0x0, RDLAR);
306 sh_eth_write(ndev, 0x0, RDFAR);
307 sh_eth_write(ndev, 0x0, RDFXR);
308 sh_eth_write(ndev, 0x0, RDFFR);
380af9e3
YS		 309}
310
311static void sh_eth_set_duplex(struct net_device *ndev)
312{
313 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 314
315 if (mdp->duplex) /* Full */
4a55530f 316 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) | ECMR_DM, ECMR);
380af9e3 317 else /* Half */
4a55530f 318 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) & ~ECMR_DM, ECMR);
380af9e3
YS		 319}
320
321static void sh_eth_set_rate(struct net_device *ndev)
322{
323 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3
YS		 324
325 switch (mdp->speed) {
326 case 10: /* 10BASE */
4a55530f 327 sh_eth_write(ndev, GECMR_10, GECMR);
380af9e3
YS		 328 break;
329 case 100:/* 100BASE */
4a55530f 330 sh_eth_write(ndev, GECMR_100, GECMR);
380af9e3
YS		 331 break;
332 case 1000: /* 1000BASE */
4a55530f 333 sh_eth_write(ndev, GECMR_1000, GECMR);
380af9e3
YS		 334 break;
335 default:
336 break;
337 }
338}
339
340/* sh7763 */
341static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
342 .chip_reset = sh_eth_chip_reset,
343 .set_duplex = sh_eth_set_duplex,
344 .set_rate = sh_eth_set_rate,
345
346 .ecsr_value = ECSR_ICD | ECSR_MPD,
347 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
348 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
349
350 .tx_check = EESR_TC1 | EESR_FTC,
351 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT | \
352 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE | \
353 EESR_ECI,
354 .tx_error_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_TDE | \
355 EESR_TFE,
356
357 .apr = 1,
358 .mpr = 1,
359 .tpauser = 1,
360 .bculr = 1,
361 .hw_swap = 1,
380af9e3
YS		 362 .no_trimd = 1,
363 .no_ade = 1,
4986b996 364 .tsu = 1,
380af9e3
YS		 365};
366
367#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
368#define SH_ETH_RESET_DEFAULT 1
369static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
370 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
371
372 .apr = 1,
373 .mpr = 1,
374 .tpauser = 1,
375 .hw_swap = 1,
376};
377#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
378#define SH_ETH_RESET_DEFAULT 1
379#define SH_ETH_HAS_TSU 1
380static struct sh_eth_cpu_data sh_eth_my_cpu_data = {
381 .eesipr_value = DMAC_M_RFRMER | DMAC_M_ECI | 0x003fffff,
4986b996 382 .tsu = 1,
380af9e3
YS		 383};
384#endif
385
386static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
387{
388 if (!cd->ecsr_value)
389 cd->ecsr_value = DEFAULT_ECSR_INIT;
390
391 if (!cd->ecsipr_value)
392 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
393
394 if (!cd->fcftr_value)
395 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF | \
396 DEFAULT_FIFO_F_D_RFD;
397
398 if (!cd->fdr_value)
399 cd->fdr_value = DEFAULT_FDR_INIT;
400
401 if (!cd->rmcr_value)
402 cd->rmcr_value = DEFAULT_RMCR_VALUE;
403
404 if (!cd->tx_check)
405 cd->tx_check = DEFAULT_TX_CHECK;
406
407 if (!cd->eesr_err_check)
408 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
409
410 if (!cd->tx_error_check)
411 cd->tx_error_check = DEFAULT_TX_ERROR_CHECK;
412}
413
414#if defined(SH_ETH_RESET_DEFAULT)
415/* Chip Reset */
416static void sh_eth_reset(struct net_device *ndev)
417{
c5ed5368 418 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) | EDMR_SRST_ETHER, EDMR);
380af9e3 419 mdelay(3);
c5ed5368 420 sh_eth_write(ndev, sh_eth_read(ndev, EDMR) & ~EDMR_SRST_ETHER, EDMR);
380af9e3
YS		 421}
422#endif
423
424#if defined(CONFIG_CPU_SH4)
425static void sh_eth_set_receive_align(struct sk_buff *skb)
426{
427 int reserve;
428
429 reserve = SH4_SKB_RX_ALIGN - ((u32)skb->data & (SH4_SKB_RX_ALIGN - 1));
430 if (reserve)
431 skb_reserve(skb, reserve);
432}
433#else
434static void sh_eth_set_receive_align(struct sk_buff *skb)
435{
436 skb_reserve(skb, SH2_SH3_SKB_RX_ALIGN);
437}
438#endif
439
440
71557a37
YS		 441/* CPU <-> EDMAC endian convert */
442static inline __u32 cpu_to_edmac(struct sh_eth_private *mdp, u32 x)
443{
444 switch (mdp->edmac_endian) {
445 case EDMAC_LITTLE_ENDIAN:
446 return cpu_to_le32(x);
447 case EDMAC_BIG_ENDIAN:
448 return cpu_to_be32(x);
449 }
450 return x;
451}
452
453static inline __u32 edmac_to_cpu(struct sh_eth_private *mdp, u32 x)
454{
455 switch (mdp->edmac_endian) {
456 case EDMAC_LITTLE_ENDIAN:
457 return le32_to_cpu(x);
458 case EDMAC_BIG_ENDIAN:
459 return be32_to_cpu(x);
460 }
461 return x;
462}
463
86a74ff2
NI		 464/*
465 * Program the hardware MAC address from dev->dev_addr.
466 */
467static void update_mac_address(struct net_device *ndev)
468{
4a55530f
YS		 469 sh_eth_write(ndev,
470 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
471 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
472 sh_eth_write(ndev,
473 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
86a74ff2
NI		 474}
475
476/*
477 * Get MAC address from SuperH MAC address register
478 *
479 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
480 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
481 * When you want use this device, you must set MAC address in bootloader.
482 *
483 */
748031f9 484static void read_mac_address(struct net_device *ndev, unsigned char *mac)
86a74ff2 485{
748031f9
MD		 486 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
487 memcpy(ndev->dev_addr, mac, 6);
488 } else {
4a55530f
YS		 489 ndev->dev_addr[0] = (sh_eth_read(ndev, MAHR) >> 24);
490 ndev->dev_addr[1] = (sh_eth_read(ndev, MAHR) >> 16) & 0xFF;
491 ndev->dev_addr[2] = (sh_eth_read(ndev, MAHR) >> 8) & 0xFF;
492 ndev->dev_addr[3] = (sh_eth_read(ndev, MAHR) & 0xFF);
493 ndev->dev_addr[4] = (sh_eth_read(ndev, MALR) >> 8) & 0xFF;
494 ndev->dev_addr[5] = (sh_eth_read(ndev, MALR) & 0xFF);
748031f9 495 }
86a74ff2
NI		 496}
497
c5ed5368
YS		 498static int sh_eth_is_gether(struct sh_eth_private *mdp)
499{
500 if (mdp->reg_offset == sh_eth_offset_gigabit)
501 return 1;
502 else
503 return 0;
504}
505
506static unsigned long sh_eth_get_edtrr_trns(struct sh_eth_private *mdp)
507{
508 if (sh_eth_is_gether(mdp))
509 return EDTRR_TRNS_GETHER;
510 else
511 return EDTRR_TRNS_ETHER;
512}
513
86a74ff2 514struct bb_info {
b3017e6a 515 void (*set_gate)(unsigned long addr);
86a74ff2
NI		 516 struct mdiobb_ctrl ctrl;
517 u32 addr;
518 u32 mmd_msk;/* MMD */
519 u32 mdo_msk;
520 u32 mdi_msk;
521 u32 mdc_msk;
522};
523
524/* PHY bit set */
525static void bb_set(u32 addr, u32 msk)
526{
900fcf09 527 writel(readl(addr) | msk, addr);
86a74ff2
NI		 528}
529
530/* PHY bit clear */
531static void bb_clr(u32 addr, u32 msk)
532{
900fcf09 533 writel((readl(addr) & ~msk), addr);
86a74ff2
NI		 534}
535
536/* PHY bit read */
537static int bb_read(u32 addr, u32 msk)
538{
900fcf09 539 return (readl(addr) & msk) != 0;
86a74ff2
NI		 540}
541
542/* Data I/O pin control */
543static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
544{
545 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 546
547 if (bitbang->set_gate)
548 bitbang->set_gate(bitbang->addr);
549
86a74ff2
NI		 550 if (bit)
551 bb_set(bitbang->addr, bitbang->mmd_msk);
552 else
553 bb_clr(bitbang->addr, bitbang->mmd_msk);
554}
555
556/* Set bit data*/
557static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
558{
559 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
560
b3017e6a
YS		 561 if (bitbang->set_gate)
562 bitbang->set_gate(bitbang->addr);
563
86a74ff2
NI		 564 if (bit)
565 bb_set(bitbang->addr, bitbang->mdo_msk);
566 else
567 bb_clr(bitbang->addr, bitbang->mdo_msk);
568}
569
570/* Get bit data*/
571static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
572{
573 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
b3017e6a
YS		 574
575 if (bitbang->set_gate)
576 bitbang->set_gate(bitbang->addr);
577
86a74ff2
NI		 578 return bb_read(bitbang->addr, bitbang->mdi_msk);
579}
580
581/* MDC pin control */
582static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
583{
584 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
585
b3017e6a
YS		 586 if (bitbang->set_gate)
587 bitbang->set_gate(bitbang->addr);
588
86a74ff2
NI		 589 if (bit)
590 bb_set(bitbang->addr, bitbang->mdc_msk);
591 else
592 bb_clr(bitbang->addr, bitbang->mdc_msk);
593}
594
595/* mdio bus control struct */
596static struct mdiobb_ops bb_ops = {
597 .owner = THIS_MODULE,
598 .set_mdc = sh_mdc_ctrl,
599 .set_mdio_dir = sh_mmd_ctrl,
600 .set_mdio_data = sh_set_mdio,
601 .get_mdio_data = sh_get_mdio,
602};
603
86a74ff2
NI		 604/* free skb and descriptor buffer */
605static void sh_eth_ring_free(struct net_device *ndev)
606{
607 struct sh_eth_private *mdp = netdev_priv(ndev);
608 int i;
609
610 /* Free Rx skb ringbuffer */
611 if (mdp->rx_skbuff) {
612 for (i = 0; i < RX_RING_SIZE; i++) {
613 if (mdp->rx_skbuff[i])
614 dev_kfree_skb(mdp->rx_skbuff[i]);
615 }
616 }
617 kfree(mdp->rx_skbuff);
618
619 /* Free Tx skb ringbuffer */
620 if (mdp->tx_skbuff) {
621 for (i = 0; i < TX_RING_SIZE; i++) {
622 if (mdp->tx_skbuff[i])
623 dev_kfree_skb(mdp->tx_skbuff[i]);
624 }
625 }
626 kfree(mdp->tx_skbuff);
627}
628
629/* format skb and descriptor buffer */
630static void sh_eth_ring_format(struct net_device *ndev)
631{
632 struct sh_eth_private *mdp = netdev_priv(ndev);
633 int i;
634 struct sk_buff *skb;
635 struct sh_eth_rxdesc *rxdesc = NULL;
636 struct sh_eth_txdesc *txdesc = NULL;
637 int rx_ringsize = sizeof(*rxdesc) * RX_RING_SIZE;
638 int tx_ringsize = sizeof(*txdesc) * TX_RING_SIZE;
639
640 mdp->cur_rx = mdp->cur_tx = 0;
641 mdp->dirty_rx = mdp->dirty_tx = 0;
642
643 memset(mdp->rx_ring, 0, rx_ringsize);
644
645 /* build Rx ring buffer */
646 for (i = 0; i < RX_RING_SIZE; i++) {
647 /* skb */
648 mdp->rx_skbuff[i] = NULL;
649 skb = dev_alloc_skb(mdp->rx_buf_sz);
650 mdp->rx_skbuff[i] = skb;
651 if (skb == NULL)
652 break;
e88aae7b
YS		 653 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
654 DMA_FROM_DEVICE);
b0ca2a21 655 skb->dev = ndev; /* Mark as being used by this device. */
380af9e3
YS		 656 sh_eth_set_receive_align(skb);
657
86a74ff2
NI		 658 /* RX descriptor */
659 rxdesc = &mdp->rx_ring[i];
0029d64a 660 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
71557a37 661 rxdesc->status = cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 662
663 /* The size of the buffer is 16 byte boundary. */
0029d64a 664 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21
NI		 665 /* Rx descriptor address set */
666 if (i == 0) {
4a55530f 667 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
c5ed5368
YS		 668 if (sh_eth_is_gether(mdp))
669 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
b0ca2a21 670 }
86a74ff2
NI		 671 }
672
673 mdp->dirty_rx = (u32) (i - RX_RING_SIZE);
674
675 /* Mark the last entry as wrapping the ring. */
71557a37 676 rxdesc->status |= cpu_to_edmac(mdp, RD_RDEL);
86a74ff2
NI		 677
678 memset(mdp->tx_ring, 0, tx_ringsize);
679
680 /* build Tx ring buffer */
681 for (i = 0; i < TX_RING_SIZE; i++) {
682 mdp->tx_skbuff[i] = NULL;
683 txdesc = &mdp->tx_ring[i];
71557a37 684 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 685 txdesc->buffer_length = 0;
b0ca2a21 686 if (i == 0) {
71557a37 687 /* Tx descriptor address set */
4a55530f 688 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
c5ed5368
YS		 689 if (sh_eth_is_gether(mdp))
690 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
b0ca2a21 691 }
86a74ff2
NI		 692 }
693
71557a37 694 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 695}
696
697/* Get skb and descriptor buffer */
698static int sh_eth_ring_init(struct net_device *ndev)
699{
700 struct sh_eth_private *mdp = netdev_priv(ndev);
701 int rx_ringsize, tx_ringsize, ret = 0;
702
703 /*
704 * +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
705 * card needs room to do 8 byte alignment, +2 so we can reserve
706 * the first 2 bytes, and +16 gets room for the status word from the
707 * card.
708 */
709 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
710 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
503914cf
MD		 711 if (mdp->cd->rpadir)
712 mdp->rx_buf_sz += NET_IP_ALIGN;
86a74ff2
NI		 713
714 /* Allocate RX and TX skb rings */
715 mdp->rx_skbuff = kmalloc(sizeof(*mdp->rx_skbuff) * RX_RING_SIZE,
716 GFP_KERNEL);
717 if (!mdp->rx_skbuff) {
380af9e3 718 dev_err(&ndev->dev, "Cannot allocate Rx skb\n");
86a74ff2
NI		 719 ret = -ENOMEM;
720 return ret;
721 }
722
723 mdp->tx_skbuff = kmalloc(sizeof(*mdp->tx_skbuff) * TX_RING_SIZE,
724 GFP_KERNEL);
725 if (!mdp->tx_skbuff) {
380af9e3 726 dev_err(&ndev->dev, "Cannot allocate Tx skb\n");
86a74ff2
NI		 727 ret = -ENOMEM;
728 goto skb_ring_free;
729 }
730
731 /* Allocate all Rx descriptors. */
732 rx_ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
733 mdp->rx_ring = dma_alloc_coherent(NULL, rx_ringsize, &mdp->rx_desc_dma,
734 GFP_KERNEL);
735
736 if (!mdp->rx_ring) {
380af9e3
YS		 737 dev_err(&ndev->dev, "Cannot allocate Rx Ring (size %d bytes)\n",
738 rx_ringsize);
86a74ff2
NI		 739 ret = -ENOMEM;
740 goto desc_ring_free;
741 }
742
743 mdp->dirty_rx = 0;
744
745 /* Allocate all Tx descriptors. */
746 tx_ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
747 mdp->tx_ring = dma_alloc_coherent(NULL, tx_ringsize, &mdp->tx_desc_dma,
748 GFP_KERNEL);
749 if (!mdp->tx_ring) {
380af9e3
YS		 750 dev_err(&ndev->dev, "Cannot allocate Tx Ring (size %d bytes)\n",
751 tx_ringsize);
86a74ff2
NI		 752 ret = -ENOMEM;
753 goto desc_ring_free;
754 }
755 return ret;
756
757desc_ring_free:
758 /* free DMA buffer */
759 dma_free_coherent(NULL, rx_ringsize, mdp->rx_ring, mdp->rx_desc_dma);
760
761skb_ring_free:
762 /* Free Rx and Tx skb ring buffer */
763 sh_eth_ring_free(ndev);
764
765 return ret;
766}
767
768static int sh_eth_dev_init(struct net_device *ndev)
769{
770 int ret = 0;
771 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 772 u_int32_t rx_int_var, tx_int_var;
773 u32 val;
774
775 /* Soft Reset */
776 sh_eth_reset(ndev);
777
b0ca2a21
NI		 778 /* Descriptor format */
779 sh_eth_ring_format(ndev);
380af9e3 780 if (mdp->cd->rpadir)
4a55530f 781 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
86a74ff2
NI		 782
783 /* all sh_eth int mask */
4a55530f 784 sh_eth_write(ndev, 0, EESIPR);
86a74ff2 785
380af9e3
YS		 786#if defined(__LITTLE_ENDIAN__)
787 if (mdp->cd->hw_swap)
4a55530f 788 sh_eth_write(ndev, EDMR_EL, EDMR);
380af9e3 789 else
b0ca2a21 790#endif
4a55530f 791 sh_eth_write(ndev, 0, EDMR);
86a74ff2 792
b0ca2a21 793 /* FIFO size set */
4a55530f
YS		 794 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
795 sh_eth_write(ndev, 0, TFTR);
86a74ff2 796
b0ca2a21 797 /* Frame recv control */
4a55530f 798 sh_eth_write(ndev, mdp->cd->rmcr_value, RMCR);
86a74ff2
NI		 799
800 rx_int_var = mdp->rx_int_var = DESC_I_RINT8 | DESC_I_RINT5;
801 tx_int_var = mdp->tx_int_var = DESC_I_TINT2;
4a55530f 802 sh_eth_write(ndev, rx_int_var | tx_int_var, TRSCER);
86a74ff2 803
380af9e3 804 if (mdp->cd->bculr)
4a55530f 805 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
b0ca2a21 806
4a55530f 807 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
86a74ff2 808
380af9e3 809 if (!mdp->cd->no_trimd)
4a55530f 810 sh_eth_write(ndev, 0, TRIMD);
86a74ff2 811
b0ca2a21 812 /* Recv frame limit set register */
4a55530f 813 sh_eth_write(ndev, RFLR_VALUE, RFLR);
86a74ff2 814
4a55530f
YS		 815 sh_eth_write(ndev, sh_eth_read(ndev, EESR), EESR);
816 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
86a74ff2
NI		 817
818 /* PAUSE Prohibition */
4a55530f 819 val = (sh_eth_read(ndev, ECMR) & ECMR_DM) |
86a74ff2
NI		 820 ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) | ECMR_TE | ECMR_RE;
821
4a55530f 822 sh_eth_write(ndev, val, ECMR);
b0ca2a21 823
380af9e3
YS		 824 if (mdp->cd->set_rate)
825 mdp->cd->set_rate(ndev);
826
b0ca2a21 827 /* E-MAC Status Register clear */
4a55530f 828 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
b0ca2a21
NI		 829
830 /* E-MAC Interrupt Enable register */
4a55530f 831 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
86a74ff2
NI		 832
833 /* Set MAC address */
834 update_mac_address(ndev);
835
836 /* mask reset */
380af9e3 837 if (mdp->cd->apr)
4a55530f 838 sh_eth_write(ndev, APR_AP, APR);
380af9e3 839 if (mdp->cd->mpr)
4a55530f 840 sh_eth_write(ndev, MPR_MP, MPR);
380af9e3 841 if (mdp->cd->tpauser)
4a55530f 842 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
b0ca2a21 843
86a74ff2 844 /* Setting the Rx mode will start the Rx process. */
4a55530f 845 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 846
847 netif_start_queue(ndev);
848
849 return ret;
850}
851
852/* free Tx skb function */
853static int sh_eth_txfree(struct net_device *ndev)
854{
855 struct sh_eth_private *mdp = netdev_priv(ndev);
856 struct sh_eth_txdesc *txdesc;
857 int freeNum = 0;
858 int entry = 0;
859
860 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
861 entry = mdp->dirty_tx % TX_RING_SIZE;
862 txdesc = &mdp->tx_ring[entry];
71557a37 863 if (txdesc->status & cpu_to_edmac(mdp, TD_TACT))
86a74ff2
NI		 864 break;
865 /* Free the original skb. */
866 if (mdp->tx_skbuff[entry]) {
867 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
868 mdp->tx_skbuff[entry] = NULL;
869 freeNum++;
870 }
71557a37 871 txdesc->status = cpu_to_edmac(mdp, TD_TFP);
86a74ff2 872 if (entry >= TX_RING_SIZE - 1)
71557a37 873 txdesc->status |= cpu_to_edmac(mdp, TD_TDLE);
86a74ff2
NI		 874
875 mdp->stats.tx_packets++;
876 mdp->stats.tx_bytes += txdesc->buffer_length;
877 }
878 return freeNum;
879}
880
881/* Packet receive function */
882static int sh_eth_rx(struct net_device *ndev)
883{
884 struct sh_eth_private *mdp = netdev_priv(ndev);
885 struct sh_eth_rxdesc *rxdesc;
886
887 int entry = mdp->cur_rx % RX_RING_SIZE;
888 int boguscnt = (mdp->dirty_rx + RX_RING_SIZE) - mdp->cur_rx;
889 struct sk_buff *skb;
890 u16 pkt_len = 0;
380af9e3 891 u32 desc_status;
86a74ff2
NI		 892
893 rxdesc = &mdp->rx_ring[entry];
71557a37
YS		 894 while (!(rxdesc->status & cpu_to_edmac(mdp, RD_RACT))) {
895 desc_status = edmac_to_cpu(mdp, rxdesc->status);
86a74ff2
NI		 896 pkt_len = rxdesc->frame_length;
897
898 if (--boguscnt < 0)
899 break;
900
901 if (!(desc_status & RDFEND))
902 mdp->stats.rx_length_errors++;
903
904 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
905 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
906 mdp->stats.rx_errors++;
907 if (desc_status & RD_RFS1)
908 mdp->stats.rx_crc_errors++;
909 if (desc_status & RD_RFS2)
910 mdp->stats.rx_frame_errors++;
911 if (desc_status & RD_RFS3)
912 mdp->stats.rx_length_errors++;
913 if (desc_status & RD_RFS4)
914 mdp->stats.rx_length_errors++;
915 if (desc_status & RD_RFS6)
916 mdp->stats.rx_missed_errors++;
917 if (desc_status & RD_RFS10)
918 mdp->stats.rx_over_errors++;
919 } else {
380af9e3
YS		 920 if (!mdp->cd->hw_swap)
921 sh_eth_soft_swap(
922 phys_to_virt(ALIGN(rxdesc->addr, 4)),
923 pkt_len + 2);
86a74ff2
NI		 924 skb = mdp->rx_skbuff[entry];
925 mdp->rx_skbuff[entry] = NULL;
503914cf
MD		 926 if (mdp->cd->rpadir)
927 skb_reserve(skb, NET_IP_ALIGN);
86a74ff2
NI		 928 skb_put(skb, pkt_len);
929 skb->protocol = eth_type_trans(skb, ndev);
930 netif_rx(skb);
86a74ff2
NI		 931 mdp->stats.rx_packets++;
932 mdp->stats.rx_bytes += pkt_len;
933 }
71557a37 934 rxdesc->status |= cpu_to_edmac(mdp, RD_RACT);
86a74ff2 935 entry = (++mdp->cur_rx) % RX_RING_SIZE;
862df497 936 rxdesc = &mdp->rx_ring[entry];
86a74ff2
NI		 937 }
938
939 /* Refill the Rx ring buffers. */
940 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
941 entry = mdp->dirty_rx % RX_RING_SIZE;
942 rxdesc = &mdp->rx_ring[entry];
b0ca2a21 943 /* The size of the buffer is 16 byte boundary. */
0029d64a 944 rxdesc->buffer_length = ALIGN(mdp->rx_buf_sz, 16);
b0ca2a21 945
86a74ff2
NI		 946 if (mdp->rx_skbuff[entry] == NULL) {
947 skb = dev_alloc_skb(mdp->rx_buf_sz);
948 mdp->rx_skbuff[entry] = skb;
949 if (skb == NULL)
950 break; /* Better luck next round. */
e88aae7b
YS		 951 dma_map_single(&ndev->dev, skb->tail, mdp->rx_buf_sz,
952 DMA_FROM_DEVICE);
86a74ff2 953 skb->dev = ndev;
380af9e3
YS		 954 sh_eth_set_receive_align(skb);
955
bc8acf2c 956 skb_checksum_none_assert(skb);
0029d64a 957 rxdesc->addr = virt_to_phys(PTR_ALIGN(skb->data, 4));
86a74ff2 958 }
86a74ff2
NI		 959 if (entry >= RX_RING_SIZE - 1)
960 rxdesc->status |=
71557a37 961 cpu_to_edmac(mdp, RD_RACT | RD_RFP | RD_RDEL);
86a74ff2
NI		 962 else
963 rxdesc->status |=
71557a37 964 cpu_to_edmac(mdp, RD_RACT | RD_RFP);
86a74ff2
NI		 965 }
966
967 /* Restart Rx engine if stopped. */
968 /* If we don't need to check status, don't. -KDU */
4a55530f
YS		 969 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R))
970 sh_eth_write(ndev, EDRRR_R, EDRRR);
86a74ff2
NI		 971
972 return 0;
973}
974
4a55530f 975static void sh_eth_rcv_snd_disable(struct net_device *ndev)
dc19e4e5
NI		 976{
977 /* disable tx and rx */
4a55530f
YS		 978 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) &
979 ~(ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 980}
981
4a55530f 982static void sh_eth_rcv_snd_enable(struct net_device *ndev)
dc19e4e5
NI		 983{
984 /* enable tx and rx */
4a55530f
YS		 985 sh_eth_write(ndev, sh_eth_read(ndev, ECMR) |
986 (ECMR_RE | ECMR_TE), ECMR);
dc19e4e5
NI		 987}
988
86a74ff2
NI		 989/* error control function */
990static void sh_eth_error(struct net_device *ndev, int intr_status)
991{
992 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 993 u32 felic_stat;
380af9e3
YS		 994 u32 link_stat;
995 u32 mask;
86a74ff2
NI		 996
997 if (intr_status & EESR_ECI) {
4a55530f
YS		 998 felic_stat = sh_eth_read(ndev, ECSR);
999 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
86a74ff2
NI		 1000 if (felic_stat & ECSR_ICD)
1001 mdp->stats.tx_carrier_errors++;
1002 if (felic_stat & ECSR_LCHNG) {
1003 /* Link Changed */
4923576b 1004 if (mdp->cd->no_psr || mdp->no_ether_link) {
380af9e3
YS		 1005 if (mdp->link == PHY_DOWN)
1006 link_stat = 0;
1007 else
1008 link_stat = PHY_ST_LINK;
1009 } else {
4a55530f 1010 link_stat = (sh_eth_read(ndev, PSR));
4923576b
YS		 1011 if (mdp->ether_link_active_low)
1012 link_stat = ~link_stat;
380af9e3 1013 }
dc19e4e5 1014 if (!(link_stat & PHY_ST_LINK))
4a55530f 1015 sh_eth_rcv_snd_disable(ndev);
dc19e4e5 1016 else {
86a74ff2 1017 /* Link Up */
4a55530f
YS		 1018 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) &
1019 ~DMAC_M_ECI, EESIPR);
86a74ff2 1020 /*clear int */
4a55530f
YS		 1021 sh_eth_write(ndev, sh_eth_read(ndev, ECSR),
1022 ECSR);
1023 sh_eth_write(ndev, sh_eth_read(ndev, EESIPR) |
1024 DMAC_M_ECI, EESIPR);
86a74ff2 1025 /* enable tx and rx */
4a55530f 1026 sh_eth_rcv_snd_enable(ndev);
86a74ff2
NI		 1027 }
1028 }
1029 }
1030
1031 if (intr_status & EESR_TWB) {
1032 /* Write buck end. unused write back interrupt */
1033 if (intr_status & EESR_TABT) /* Transmit Abort int */
1034 mdp->stats.tx_aborted_errors++;
dc19e4e5
NI		 1035 if (netif_msg_tx_err(mdp))
1036 dev_err(&ndev->dev, "Transmit Abort\n");
86a74ff2
NI		 1037 }
1038
1039 if (intr_status & EESR_RABT) {
1040 /* Receive Abort int */
1041 if (intr_status & EESR_RFRMER) {
1042 /* Receive Frame Overflow int */
1043 mdp->stats.rx_frame_errors++;
dc19e4e5
NI		 1044 if (netif_msg_rx_err(mdp))
1045 dev_err(&ndev->dev, "Receive Abort\n");
86a74ff2
NI		 1046 }
1047 }
380af9e3 1048
dc19e4e5
NI		 1049 if (intr_status & EESR_TDE) {
1050 /* Transmit Descriptor Empty int */
1051 mdp->stats.tx_fifo_errors++;
1052 if (netif_msg_tx_err(mdp))
1053 dev_err(&ndev->dev, "Transmit Descriptor Empty\n");
1054 }
1055
1056 if (intr_status & EESR_TFE) {
1057 /* FIFO under flow */
1058 mdp->stats.tx_fifo_errors++;
1059 if (netif_msg_tx_err(mdp))
1060 dev_err(&ndev->dev, "Transmit FIFO Under flow\n");
86a74ff2
NI		 1061 }
1062
1063 if (intr_status & EESR_RDE) {
1064 /* Receive Descriptor Empty int */
1065 mdp->stats.rx_over_errors++;
1066
4a55530f
YS		 1067 if (sh_eth_read(ndev, EDRRR) ^ EDRRR_R)
1068 sh_eth_write(ndev, EDRRR_R, EDRRR);
dc19e4e5
NI		 1069 if (netif_msg_rx_err(mdp))
1070 dev_err(&ndev->dev, "Receive Descriptor Empty\n");
86a74ff2 1071 }
dc19e4e5 1072
86a74ff2
NI		 1073 if (intr_status & EESR_RFE) {
1074 /* Receive FIFO Overflow int */
1075 mdp->stats.rx_fifo_errors++;
dc19e4e5
NI		 1076 if (netif_msg_rx_err(mdp))
1077 dev_err(&ndev->dev, "Receive FIFO Overflow\n");
1078 }
1079
1080 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1081 /* Address Error */
1082 mdp->stats.tx_fifo_errors++;
1083 if (netif_msg_tx_err(mdp))
1084 dev_err(&ndev->dev, "Address Error\n");
86a74ff2 1085 }
380af9e3
YS		 1086
1087 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1088 if (mdp->cd->no_ade)
1089 mask &= ~EESR_ADE;
1090 if (intr_status & mask) {
86a74ff2 1091 /* Tx error */
4a55530f 1092 u32 edtrr = sh_eth_read(ndev, EDTRR);
86a74ff2 1093 /* dmesg */
380af9e3
YS		 1094 dev_err(&ndev->dev, "TX error. status=%8.8x cur_tx=%8.8x ",
1095 intr_status, mdp->cur_tx);
1096 dev_err(&ndev->dev, "dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
86a74ff2
NI		 1097 mdp->dirty_tx, (u32) ndev->state, edtrr);
1098 /* dirty buffer free */
1099 sh_eth_txfree(ndev);
1100
1101 /* SH7712 BUG */
c5ed5368 1102 if (edtrr ^ sh_eth_get_edtrr_trns(mdp)) {
86a74ff2 1103 /* tx dma start */
c5ed5368 1104 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
86a74ff2
NI		 1105 }
1106 /* wakeup */
1107 netif_wake_queue(ndev);
1108 }
1109}
1110
1111static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1112{
1113 struct net_device *ndev = netdev;
1114 struct sh_eth_private *mdp = netdev_priv(ndev);
380af9e3 1115 struct sh_eth_cpu_data *cd = mdp->cd;
0e0fde3c 1116 irqreturn_t ret = IRQ_NONE;
4a55530f 1117 u32 intr_status = 0;
86a74ff2 1118
86a74ff2
NI		 1119 spin_lock(&mdp->lock);
1120
b0ca2a21 1121 /* Get interrpt stat */
4a55530f 1122 intr_status = sh_eth_read(ndev, EESR);
86a74ff2 1123 /* Clear interrupt */
0e0fde3c
NI		 1124 if (intr_status & (EESR_FRC | EESR_RMAF | EESR_RRF |
1125 EESR_RTLF | EESR_RTSF | EESR_PRE | EESR_CERF |
380af9e3 1126 cd->tx_check | cd->eesr_err_check)) {
4a55530f 1127 sh_eth_write(ndev, intr_status, EESR);
0e0fde3c
NI		 1128 ret = IRQ_HANDLED;
1129 } else
1130 goto other_irq;
86a74ff2 1131
b0ca2a21
NI		 1132 if (intr_status & (EESR_FRC | /* Frame recv*/
1133 EESR_RMAF | /* Multi cast address recv*/
1134 EESR_RRF | /* Bit frame recv */
1135 EESR_RTLF | /* Long frame recv*/
1136 EESR_RTSF | /* short frame recv */
1137 EESR_PRE | /* PHY-LSI recv error */
1138 EESR_CERF)){ /* recv frame CRC error */
86a74ff2 1139 sh_eth_rx(ndev);
b0ca2a21 1140 }
86a74ff2 1141
b0ca2a21 1142 /* Tx Check */
380af9e3 1143 if (intr_status & cd->tx_check) {
86a74ff2
NI		 1144 sh_eth_txfree(ndev);
1145 netif_wake_queue(ndev);
1146 }
1147
380af9e3 1148 if (intr_status & cd->eesr_err_check)
86a74ff2
NI		 1149 sh_eth_error(ndev, intr_status);
1150
0e0fde3c 1151other_irq:
86a74ff2
NI		 1152 spin_unlock(&mdp->lock);
1153
0e0fde3c 1154 return ret;
86a74ff2
NI		 1155}
1156
1157static void sh_eth_timer(unsigned long data)
1158{
1159 struct net_device *ndev = (struct net_device *)data;
1160 struct sh_eth_private *mdp = netdev_priv(ndev);
1161
1162 mod_timer(&mdp->timer, jiffies + (10 * HZ));
1163}
1164
1165/* PHY state control function */
1166static void sh_eth_adjust_link(struct net_device *ndev)
1167{
1168 struct sh_eth_private *mdp = netdev_priv(ndev);
1169 struct phy_device *phydev = mdp->phydev;
86a74ff2
NI		 1170 int new_state = 0;
1171
1172 if (phydev->link != PHY_DOWN) {
1173 if (phydev->duplex != mdp->duplex) {
1174 new_state = 1;
1175 mdp->duplex = phydev->duplex;
380af9e3
YS		 1176 if (mdp->cd->set_duplex)
1177 mdp->cd->set_duplex(ndev);
86a74ff2
NI		 1178 }
1179
1180 if (phydev->speed != mdp->speed) {
1181 new_state = 1;
1182 mdp->speed = phydev->speed;
380af9e3
YS		 1183 if (mdp->cd->set_rate)
1184 mdp->cd->set_rate(ndev);
86a74ff2
NI		 1185 }
1186 if (mdp->link == PHY_DOWN) {
4a55530f
YS		 1187 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_TXF)
1188 | ECMR_DM, ECMR);
86a74ff2
NI		 1189 new_state = 1;
1190 mdp->link = phydev->link;
86a74ff2
NI		 1191 }
1192 } else if (mdp->link) {
1193 new_state = 1;
1194 mdp->link = PHY_DOWN;
1195 mdp->speed = 0;
1196 mdp->duplex = -1;
86a74ff2
NI		 1197 }
1198
dc19e4e5 1199 if (new_state && netif_msg_link(mdp))
86a74ff2
NI		 1200 phy_print_status(phydev);
1201}
1202
1203/* PHY init function */
1204static int sh_eth_phy_init(struct net_device *ndev)
1205{
1206 struct sh_eth_private *mdp = netdev_priv(ndev);
0a372eb9 1207 char phy_id[MII_BUS_ID_SIZE + 3];
86a74ff2
NI		 1208 struct phy_device *phydev = NULL;
1209
fb28ad35 1210 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
86a74ff2
NI		 1211 mdp->mii_bus->id , mdp->phy_id);
1212
1213 mdp->link = PHY_DOWN;
1214 mdp->speed = 0;
1215 mdp->duplex = -1;
1216
1217 /* Try connect to PHY */
c061b18d 1218 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
e47c9052 1219 0, mdp->phy_interface);
86a74ff2
NI		 1220 if (IS_ERR(phydev)) {
1221 dev_err(&ndev->dev, "phy_connect failed\n");
1222 return PTR_ERR(phydev);
1223 }
380af9e3 1224
86a74ff2 1225 dev_info(&ndev->dev, "attached phy %i to driver %s\n",
380af9e3 1226 phydev->addr, phydev->drv->name);
86a74ff2
NI		 1227
1228 mdp->phydev = phydev;
1229
1230 return 0;
1231}
1232
1233/* PHY control start function */
1234static int sh_eth_phy_start(struct net_device *ndev)
1235{
1236 struct sh_eth_private *mdp = netdev_priv(ndev);
1237 int ret;
1238
1239 ret = sh_eth_phy_init(ndev);
1240 if (ret)
1241 return ret;
1242
1243 /* reset phy - this also wakes it from PDOWN */
1244 phy_write(mdp->phydev, MII_BMCR, BMCR_RESET);
1245 phy_start(mdp->phydev);
1246
1247 return 0;
1248}
1249
dc19e4e5
NI		 1250static int sh_eth_get_settings(struct net_device *ndev,
1251 struct ethtool_cmd *ecmd)
1252{
1253 struct sh_eth_private *mdp = netdev_priv(ndev);
1254 unsigned long flags;
1255 int ret;
1256
1257 spin_lock_irqsave(&mdp->lock, flags);
1258 ret = phy_ethtool_gset(mdp->phydev, ecmd);
1259 spin_unlock_irqrestore(&mdp->lock, flags);
1260
1261 return ret;
1262}
1263
1264static int sh_eth_set_settings(struct net_device *ndev,
1265 struct ethtool_cmd *ecmd)
1266{
1267 struct sh_eth_private *mdp = netdev_priv(ndev);
1268 unsigned long flags;
1269 int ret;
dc19e4e5
NI		 1270
1271 spin_lock_irqsave(&mdp->lock, flags);
1272
1273 /* disable tx and rx */
4a55530f 1274 sh_eth_rcv_snd_disable(ndev);
dc19e4e5
NI		 1275
1276 ret = phy_ethtool_sset(mdp->phydev, ecmd);
1277 if (ret)
1278 goto error_exit;
1279
1280 if (ecmd->duplex == DUPLEX_FULL)
1281 mdp->duplex = 1;
1282 else
1283 mdp->duplex = 0;
1284
1285 if (mdp->cd->set_duplex)
1286 mdp->cd->set_duplex(ndev);
1287
1288error_exit:
1289 mdelay(1);
1290
1291 /* enable tx and rx */
4a55530f 1292 sh_eth_rcv_snd_enable(ndev);
dc19e4e5
NI		 1293
1294 spin_unlock_irqrestore(&mdp->lock, flags);
1295
1296 return ret;
1297}
1298
1299static int sh_eth_nway_reset(struct net_device *ndev)
1300{
1301 struct sh_eth_private *mdp = netdev_priv(ndev);
1302 unsigned long flags;
1303 int ret;
1304
1305 spin_lock_irqsave(&mdp->lock, flags);
1306 ret = phy_start_aneg(mdp->phydev);
1307 spin_unlock_irqrestore(&mdp->lock, flags);
1308
1309 return ret;
1310}
1311
1312static u32 sh_eth_get_msglevel(struct net_device *ndev)
1313{
1314 struct sh_eth_private *mdp = netdev_priv(ndev);
1315 return mdp->msg_enable;
1316}
1317
1318static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
1319{
1320 struct sh_eth_private *mdp = netdev_priv(ndev);
1321 mdp->msg_enable = value;
1322}
1323
1324static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
1325 "rx_current", "tx_current",
1326 "rx_dirty", "tx_dirty",
1327};
1328#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
1329
1330static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
1331{
1332 switch (sset) {
1333 case ETH_SS_STATS:
1334 return SH_ETH_STATS_LEN;
1335 default:
1336 return -EOPNOTSUPP;
1337 }
1338}
1339
1340static void sh_eth_get_ethtool_stats(struct net_device *ndev,
1341 struct ethtool_stats *stats, u64 *data)
1342{
1343 struct sh_eth_private *mdp = netdev_priv(ndev);
1344 int i = 0;
1345
1346 /* device-specific stats */
1347 data[i++] = mdp->cur_rx;
1348 data[i++] = mdp->cur_tx;
1349 data[i++] = mdp->dirty_rx;
1350 data[i++] = mdp->dirty_tx;
1351}
1352
1353static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1354{
1355 switch (stringset) {
1356 case ETH_SS_STATS:
1357 memcpy(data, *sh_eth_gstrings_stats,
1358 sizeof(sh_eth_gstrings_stats));
1359 break;
1360 }
1361}
1362
1363static struct ethtool_ops sh_eth_ethtool_ops = {
1364 .get_settings = sh_eth_get_settings,
1365 .set_settings = sh_eth_set_settings,
1366 .nway_reset = sh_eth_nway_reset,
1367 .get_msglevel = sh_eth_get_msglevel,
1368 .set_msglevel = sh_eth_set_msglevel,
1369 .get_link = ethtool_op_get_link,
1370 .get_strings = sh_eth_get_strings,
1371 .get_ethtool_stats = sh_eth_get_ethtool_stats,
1372 .get_sset_count = sh_eth_get_sset_count,
1373};
1374
86a74ff2
NI		 1375/* network device open function */
1376static int sh_eth_open(struct net_device *ndev)
1377{
1378 int ret = 0;
1379 struct sh_eth_private *mdp = netdev_priv(ndev);
1380
bcd5149d
MD		 1381 pm_runtime_get_sync(&mdp->pdev->dev);
1382
a0607fd3 1383 ret = request_irq(ndev->irq, sh_eth_interrupt,
f29a3d04 1384#if defined(CONFIG_CPU_SUBTYPE_SH7763) || \
dc19e4e5
NI		 1385 defined(CONFIG_CPU_SUBTYPE_SH7764) || \
1386 defined(CONFIG_CPU_SUBTYPE_SH7757)
0e0fde3c
NI		 1387 IRQF_SHARED,
1388#else
1389 0,
1390#endif
1391 ndev->name, ndev);
86a74ff2 1392 if (ret) {
380af9e3 1393 dev_err(&ndev->dev, "Can not assign IRQ number\n");
86a74ff2
NI		 1394 return ret;
1395 }
1396
1397 /* Descriptor set */
1398 ret = sh_eth_ring_init(ndev);
1399 if (ret)
1400 goto out_free_irq;
1401
1402 /* device init */
1403 ret = sh_eth_dev_init(ndev);
1404 if (ret)
1405 goto out_free_irq;
1406
1407 /* PHY control start*/
1408 ret = sh_eth_phy_start(ndev);
1409 if (ret)
1410 goto out_free_irq;
1411
1412 /* Set the timer to check for link beat. */
1413 init_timer(&mdp->timer);
1414 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
b0ca2a21 1415 setup_timer(&mdp->timer, sh_eth_timer, (unsigned long)ndev);
86a74ff2
NI		 1416
1417 return ret;
1418
1419out_free_irq:
1420 free_irq(ndev->irq, ndev);
bcd5149d 1421 pm_runtime_put_sync(&mdp->pdev->dev);
86a74ff2
NI		 1422 return ret;
1423}
1424
1425/* Timeout function */
1426static void sh_eth_tx_timeout(struct net_device *ndev)
1427{
1428 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1429 struct sh_eth_rxdesc *rxdesc;
1430 int i;
1431
1432 netif_stop_queue(ndev);
1433
dc19e4e5
NI		 1434 if (netif_msg_timer(mdp))
1435 dev_err(&ndev->dev, "%s: transmit timed out, status %8.8x,"
4a55530f 1436 " resetting...\n", ndev->name, (int)sh_eth_read(ndev, EESR));
86a74ff2
NI		 1437
1438 /* tx_errors count up */
1439 mdp->stats.tx_errors++;
1440
1441 /* timer off */
1442 del_timer_sync(&mdp->timer);
1443
1444 /* Free all the skbuffs in the Rx queue. */
1445 for (i = 0; i < RX_RING_SIZE; i++) {
1446 rxdesc = &mdp->rx_ring[i];
1447 rxdesc->status = 0;
1448 rxdesc->addr = 0xBADF00D0;
1449 if (mdp->rx_skbuff[i])
1450 dev_kfree_skb(mdp->rx_skbuff[i]);
1451 mdp->rx_skbuff[i] = NULL;
1452 }
1453 for (i = 0; i < TX_RING_SIZE; i++) {
1454 if (mdp->tx_skbuff[i])
1455 dev_kfree_skb(mdp->tx_skbuff[i]);
1456 mdp->tx_skbuff[i] = NULL;
1457 }
1458
1459 /* device init */
1460 sh_eth_dev_init(ndev);
1461
1462 /* timer on */
1463 mdp->timer.expires = (jiffies + (24 * HZ)) / 10;/* 2.4 sec. */
1464 add_timer(&mdp->timer);
1465}
1466
1467/* Packet transmit function */
1468static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1469{
1470 struct sh_eth_private *mdp = netdev_priv(ndev);
1471 struct sh_eth_txdesc *txdesc;
1472 u32 entry;
fb5e2f9b 1473 unsigned long flags;
86a74ff2
NI		 1474
1475 spin_lock_irqsave(&mdp->lock, flags);
1476 if ((mdp->cur_tx - mdp->dirty_tx) >= (TX_RING_SIZE - 4)) {
1477 if (!sh_eth_txfree(ndev)) {
dc19e4e5
NI		 1478 if (netif_msg_tx_queued(mdp))
1479 dev_warn(&ndev->dev, "TxFD exhausted.\n");
86a74ff2
NI		 1480 netif_stop_queue(ndev);
1481 spin_unlock_irqrestore(&mdp->lock, flags);
5b548140 1482 return NETDEV_TX_BUSY;
86a74ff2
NI		 1483 }
1484 }
1485 spin_unlock_irqrestore(&mdp->lock, flags);
1486
1487 entry = mdp->cur_tx % TX_RING_SIZE;
1488 mdp->tx_skbuff[entry] = skb;
1489 txdesc = &mdp->tx_ring[entry];
0029d64a 1490 txdesc->addr = virt_to_phys(skb->data);
86a74ff2 1491 /* soft swap. */
380af9e3
YS		 1492 if (!mdp->cd->hw_swap)
1493 sh_eth_soft_swap(phys_to_virt(ALIGN(txdesc->addr, 4)),
1494 skb->len + 2);
86a74ff2
NI		 1495 /* write back */
1496 __flush_purge_region(skb->data, skb->len);
1497 if (skb->len < ETHERSMALL)
1498 txdesc->buffer_length = ETHERSMALL;
1499 else
1500 txdesc->buffer_length = skb->len;
1501
1502 if (entry >= TX_RING_SIZE - 1)
71557a37 1503 txdesc->status |= cpu_to_edmac(mdp, TD_TACT | TD_TDLE);
86a74ff2 1504 else
71557a37 1505 txdesc->status |= cpu_to_edmac(mdp, TD_TACT);
86a74ff2
NI		 1506
1507 mdp->cur_tx++;
1508
c5ed5368
YS		 1509 if (!(sh_eth_read(ndev, EDTRR) & sh_eth_get_edtrr_trns(mdp)))
1510 sh_eth_write(ndev, sh_eth_get_edtrr_trns(mdp), EDTRR);
b0ca2a21 1511
6ed10654 1512 return NETDEV_TX_OK;
86a74ff2
NI		 1513}
1514
1515/* device close function */
1516static int sh_eth_close(struct net_device *ndev)
1517{
1518 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2
NI		 1519 int ringsize;
1520
1521 netif_stop_queue(ndev);
1522
1523 /* Disable interrupts by clearing the interrupt mask. */
4a55530f 1524 sh_eth_write(ndev, 0x0000, EESIPR);
86a74ff2
NI		 1525
1526 /* Stop the chip's Tx and Rx processes. */
4a55530f
YS		 1527 sh_eth_write(ndev, 0, EDTRR);
1528 sh_eth_write(ndev, 0, EDRRR);
86a74ff2
NI		 1529
1530 /* PHY Disconnect */
1531 if (mdp->phydev) {
1532 phy_stop(mdp->phydev);
1533 phy_disconnect(mdp->phydev);
1534 }
1535
1536 free_irq(ndev->irq, ndev);
1537
1538 del_timer_sync(&mdp->timer);
1539
1540 /* Free all the skbuffs in the Rx queue. */
1541 sh_eth_ring_free(ndev);
1542
1543 /* free DMA buffer */
1544 ringsize = sizeof(struct sh_eth_rxdesc) * RX_RING_SIZE;
1545 dma_free_coherent(NULL, ringsize, mdp->rx_ring, mdp->rx_desc_dma);
1546
1547 /* free DMA buffer */
1548 ringsize = sizeof(struct sh_eth_txdesc) * TX_RING_SIZE;
1549 dma_free_coherent(NULL, ringsize, mdp->tx_ring, mdp->tx_desc_dma);
1550
bcd5149d
MD		 1551 pm_runtime_put_sync(&mdp->pdev->dev);
1552
86a74ff2
NI		 1553 return 0;
1554}
1555
1556static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
1557{
1558 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1559
bcd5149d
MD		 1560 pm_runtime_get_sync(&mdp->pdev->dev);
1561
4a55530f
YS		 1562 mdp->stats.tx_dropped += sh_eth_read(ndev, TROCR);
1563 sh_eth_write(ndev, 0, TROCR); /* (write clear) */
1564 mdp->stats.collisions += sh_eth_read(ndev, CDCR);
1565 sh_eth_write(ndev, 0, CDCR); /* (write clear) */
1566 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, LCCR);
1567 sh_eth_write(ndev, 0, LCCR); /* (write clear) */
c5ed5368
YS		 1568 if (sh_eth_is_gether(mdp)) {
1569 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CERCR);
1570 sh_eth_write(ndev, 0, CERCR); /* (write clear) */
1571 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CEECR);
1572 sh_eth_write(ndev, 0, CEECR); /* (write clear) */
1573 } else {
1574 mdp->stats.tx_carrier_errors += sh_eth_read(ndev, CNDCR);
1575 sh_eth_write(ndev, 0, CNDCR); /* (write clear) */
1576 }
bcd5149d
MD		 1577 pm_runtime_put_sync(&mdp->pdev->dev);
1578
86a74ff2
NI		 1579 return &mdp->stats;
1580}
1581
1582/* ioctl to device funciotn*/
1583static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq,
1584 int cmd)
1585{
1586 struct sh_eth_private *mdp = netdev_priv(ndev);
1587 struct phy_device *phydev = mdp->phydev;
1588
1589 if (!netif_running(ndev))
1590 return -EINVAL;
1591
1592 if (!phydev)
1593 return -ENODEV;
1594
28b04113 1595 return phy_mii_ioctl(phydev, rq, cmd);
86a74ff2
NI		 1596}
1597
380af9e3 1598#if defined(SH_ETH_HAS_TSU)
86a74ff2
NI		 1599/* Multicast reception directions set */
1600static void sh_eth_set_multicast_list(struct net_device *ndev)
1601{
86a74ff2
NI		 1602 if (ndev->flags & IFF_PROMISC) {
1603 /* Set promiscuous. */
4a55530f
YS		 1604 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_MCT) |
1605 ECMR_PRM, ECMR);
86a74ff2
NI		 1606 } else {
1607 /* Normal, unicast/broadcast-only mode. */
4a55530f
YS		 1608 sh_eth_write(ndev, (sh_eth_read(ndev, ECMR) & ~ECMR_PRM) |
1609 ECMR_MCT, ECMR);
86a74ff2
NI		 1610 }
1611}
4986b996 1612#endif /* SH_ETH_HAS_TSU */
86a74ff2
NI		 1613
1614/* SuperH's TSU register init function */
4a55530f 1615static void sh_eth_tsu_init(struct sh_eth_private *mdp)
86a74ff2 1616{
4a55530f
YS		 1617 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
1618 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
1619 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
1620 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
1621 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
1622 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
1623 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
1624 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
1625 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
1626 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
c5ed5368
YS		 1627 if (sh_eth_is_gether(mdp)) {
1628 sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */
1629 sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
1630 } else {
1631 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
1632 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
1633 }
4a55530f
YS		 1634 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
1635 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
1636 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
1637 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
1638 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
1639 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
1640 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
86a74ff2
NI		 1641}
1642
1643/* MDIO bus release function */
1644static int sh_mdio_release(struct net_device *ndev)
1645{
1646 struct mii_bus *bus = dev_get_drvdata(&ndev->dev);
1647
1648 /* unregister mdio bus */
1649 mdiobus_unregister(bus);
1650
1651 /* remove mdio bus info from net_device */
1652 dev_set_drvdata(&ndev->dev, NULL);
1653
0f0b405c
DK		 1654 /* free interrupts memory */
1655 kfree(bus->irq);
1656
86a74ff2
NI		 1657 /* free bitbang info */
1658 free_mdio_bitbang(bus);
1659
1660 return 0;
1661}
1662
1663/* MDIO bus init function */
b3017e6a
YS		 1664static int sh_mdio_init(struct net_device *ndev, int id,
1665 struct sh_eth_plat_data *pd)
86a74ff2
NI		 1666{
1667 int ret, i;
1668 struct bb_info *bitbang;
1669 struct sh_eth_private *mdp = netdev_priv(ndev);
1670
1671 /* create bit control struct for PHY */
1672 bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
1673 if (!bitbang) {
1674 ret = -ENOMEM;
1675 goto out;
1676 }
1677
1678 /* bitbang init */
4a55530f 1679 bitbang->addr = ndev->base_addr + mdp->reg_offset[PIR];
b3017e6a 1680 bitbang->set_gate = pd->set_mdio_gate;
86a74ff2
NI		 1681 bitbang->mdi_msk = 0x08;
1682 bitbang->mdo_msk = 0x04;
1683 bitbang->mmd_msk = 0x02;/* MMD */
1684 bitbang->mdc_msk = 0x01;
1685 bitbang->ctrl.ops = &bb_ops;
1686
c2e07b3a 1687 /* MII controller setting */
86a74ff2
NI		 1688 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
1689 if (!mdp->mii_bus) {
1690 ret = -ENOMEM;
1691 goto out_free_bitbang;
1692 }
1693
1694 /* Hook up MII support for ethtool */
1695 mdp->mii_bus->name = "sh_mii";
18ee49dd 1696 mdp->mii_bus->parent = &ndev->dev;
fb5e2f9b 1697 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%x", id);
86a74ff2
NI		 1698
1699 /* PHY IRQ */
1700 mdp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
1701 if (!mdp->mii_bus->irq) {
1702 ret = -ENOMEM;
1703 goto out_free_bus;
1704 }
1705
1706 for (i = 0; i < PHY_MAX_ADDR; i++)
1707 mdp->mii_bus->irq[i] = PHY_POLL;
1708
1709 /* regist mdio bus */
1710 ret = mdiobus_register(mdp->mii_bus);
1711 if (ret)
1712 goto out_free_irq;
1713
1714 dev_set_drvdata(&ndev->dev, mdp->mii_bus);
1715
1716 return 0;
1717
1718out_free_irq:
1719 kfree(mdp->mii_bus->irq);
1720
1721out_free_bus:
298cf9be 1722 free_mdio_bitbang(mdp->mii_bus);
86a74ff2
NI		 1723
1724out_free_bitbang:
1725 kfree(bitbang);
1726
1727out:
1728 return ret;
1729}
1730
4a55530f
YS		 1731static const u16 *sh_eth_get_register_offset(int register_type)
1732{
1733 const u16 *reg_offset = NULL;
1734
1735 switch (register_type) {
1736 case SH_ETH_REG_GIGABIT:
1737 reg_offset = sh_eth_offset_gigabit;
1738 break;
1739 case SH_ETH_REG_FAST_SH4:
1740 reg_offset = sh_eth_offset_fast_sh4;
1741 break;
1742 case SH_ETH_REG_FAST_SH3_SH2:
1743 reg_offset = sh_eth_offset_fast_sh3_sh2;
1744 break;
1745 default:
1746 printk(KERN_ERR "Unknown register type (%d)\n", register_type);
1747 break;
1748 }
1749
1750 return reg_offset;
1751}
1752
ebf84eaa
AB		 1753static const struct net_device_ops sh_eth_netdev_ops = {
1754 .ndo_open = sh_eth_open,
1755 .ndo_stop = sh_eth_close,
1756 .ndo_start_xmit = sh_eth_start_xmit,
1757 .ndo_get_stats = sh_eth_get_stats,
380af9e3 1758#if defined(SH_ETH_HAS_TSU)
ebf84eaa 1759 .ndo_set_multicast_list = sh_eth_set_multicast_list,
380af9e3 1760#endif
ebf84eaa
AB		 1761 .ndo_tx_timeout = sh_eth_tx_timeout,
1762 .ndo_do_ioctl = sh_eth_do_ioctl,
1763 .ndo_validate_addr = eth_validate_addr,
1764 .ndo_set_mac_address = eth_mac_addr,
1765 .ndo_change_mtu = eth_change_mtu,
1766};
1767
86a74ff2
NI		 1768static int sh_eth_drv_probe(struct platform_device *pdev)
1769{
9c38657c 1770 int ret, devno = 0;
86a74ff2
NI		 1771 struct resource *res;
1772 struct net_device *ndev = NULL;
1773 struct sh_eth_private *mdp;
71557a37 1774 struct sh_eth_plat_data *pd;
86a74ff2
NI		 1775
1776 /* get base addr */
1777 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1778 if (unlikely(res == NULL)) {
1779 dev_err(&pdev->dev, "invalid resource\n");
1780 ret = -EINVAL;
1781 goto out;
1782 }
1783
1784 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
1785 if (!ndev) {
380af9e3 1786 dev_err(&pdev->dev, "Could not allocate device.\n");
86a74ff2
NI		 1787 ret = -ENOMEM;
1788 goto out;
1789 }
1790
1791 /* The sh Ether-specific entries in the device structure. */
1792 ndev->base_addr = res->start;
1793 devno = pdev->id;
1794 if (devno < 0)
1795 devno = 0;
1796
1797 ndev->dma = -1;
cc3c080d 1798 ret = platform_get_irq(pdev, 0);
1799 if (ret < 0) {
86a74ff2
NI		 1800 ret = -ENODEV;
1801 goto out_release;
1802 }
cc3c080d 1803 ndev->irq = ret;
86a74ff2
NI		 1804
1805 SET_NETDEV_DEV(ndev, &pdev->dev);
1806
1807 /* Fill in the fields of the device structure with ethernet values. */
1808 ether_setup(ndev);
1809
1810 mdp = netdev_priv(ndev);
1811 spin_lock_init(&mdp->lock);
bcd5149d
MD		 1812 mdp->pdev = pdev;
1813 pm_runtime_enable(&pdev->dev);
1814 pm_runtime_resume(&pdev->dev);
86a74ff2 1815
71557a37 1816 pd = (struct sh_eth_plat_data *)(pdev->dev.platform_data);
86a74ff2 1817 /* get PHY ID */
71557a37 1818 mdp->phy_id = pd->phy;
e47c9052 1819 mdp->phy_interface = pd->phy_interface;
71557a37
YS		 1820 /* EDMAC endian */
1821 mdp->edmac_endian = pd->edmac_endian;
4923576b
YS		 1822 mdp->no_ether_link = pd->no_ether_link;
1823 mdp->ether_link_active_low = pd->ether_link_active_low;
4a55530f 1824 mdp->reg_offset = sh_eth_get_register_offset(pd->register_type);
86a74ff2 1825
380af9e3 1826 /* set cpu data */
8fcd4961
YS		 1827#if defined(SH_ETH_HAS_BOTH_MODULES)
1828 mdp->cd = sh_eth_get_cpu_data(mdp);
1829#else
380af9e3 1830 mdp->cd = &sh_eth_my_cpu_data;
8fcd4961 1831#endif
380af9e3
YS		 1832 sh_eth_set_default_cpu_data(mdp->cd);
1833
86a74ff2 1834 /* set function */
ebf84eaa 1835 ndev->netdev_ops = &sh_eth_netdev_ops;
dc19e4e5 1836 SET_ETHTOOL_OPS(ndev, &sh_eth_ethtool_ops);
86a74ff2
NI		 1837 ndev->watchdog_timeo = TX_TIMEOUT;
1838
dc19e4e5
NI		 1839 /* debug message level */
1840 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
86a74ff2
NI		 1841 mdp->post_rx = POST_RX >> (devno << 1);
1842 mdp->post_fw = POST_FW >> (devno << 1);
1843
1844 /* read and set MAC address */
748031f9 1845 read_mac_address(ndev, pd->mac_addr);
86a74ff2
NI		 1846
1847 /* First device only init */
1848 if (!devno) {
4986b996
YS		 1849 if (mdp->cd->tsu) {
1850 struct resource *rtsu;
1851 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1852 if (!rtsu) {
1853 dev_err(&pdev->dev, "Not found TSU resource\n");
1854 goto out_release;
1855 }
1856 mdp->tsu_addr = ioremap(rtsu->start,
1857 resource_size(rtsu));
1858 }
380af9e3
YS		 1859 if (mdp->cd->chip_reset)
1860 mdp->cd->chip_reset(ndev);
86a74ff2 1861
4986b996
YS		 1862 if (mdp->cd->tsu) {
1863 /* TSU init (Init only)*/
1864 sh_eth_tsu_init(mdp);
1865 }
86a74ff2
NI		 1866 }
1867
1868 /* network device register */
1869 ret = register_netdev(ndev);
1870 if (ret)
1871 goto out_release;
1872
1873 /* mdio bus init */
b3017e6a 1874 ret = sh_mdio_init(ndev, pdev->id, pd);
86a74ff2
NI		 1875 if (ret)
1876 goto out_unregister;
1877
25985edc 1878 /* print device information */
6cd9b49d
HS		 1879 pr_info("Base address at 0x%x, %pM, IRQ %d.\n",
1880 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
86a74ff2
NI		 1881
1882 platform_set_drvdata(pdev, ndev);
1883
1884 return ret;
1885
1886out_unregister:
1887 unregister_netdev(ndev);
1888
1889out_release:
1890 /* net_dev free */
4986b996
YS		 1891 if (mdp->tsu_addr)
1892 iounmap(mdp->tsu_addr);
86a74ff2
NI		 1893 if (ndev)
1894 free_netdev(ndev);
1895
1896out:
1897 return ret;
1898}
1899
1900static int sh_eth_drv_remove(struct platform_device *pdev)
1901{
1902 struct net_device *ndev = platform_get_drvdata(pdev);
4986b996 1903 struct sh_eth_private *mdp = netdev_priv(ndev);
86a74ff2 1904
4986b996 1905 iounmap(mdp->tsu_addr);
86a74ff2
NI		 1906 sh_mdio_release(ndev);
1907 unregister_netdev(ndev);
bcd5149d 1908 pm_runtime_disable(&pdev->dev);
86a74ff2
NI		 1909 free_netdev(ndev);
1910 platform_set_drvdata(pdev, NULL);
1911
1912 return 0;
1913}
1914
bcd5149d
MD		 1915static int sh_eth_runtime_nop(struct device *dev)
1916{
1917 /*
1918 * Runtime PM callback shared between ->runtime_suspend()
1919 * and ->runtime_resume(). Simply returns success.
1920 *
1921 * This driver re-initializes all registers after
1922 * pm_runtime_get_sync() anyway so there is no need
1923 * to save and restore registers here.
1924 */
1925 return 0;
1926}
1927
1928static struct dev_pm_ops sh_eth_dev_pm_ops = {
1929 .runtime_suspend = sh_eth_runtime_nop,
1930 .runtime_resume = sh_eth_runtime_nop,
1931};
1932
86a74ff2
NI		 1933static struct platform_driver sh_eth_driver = {
1934 .probe = sh_eth_drv_probe,
1935 .remove = sh_eth_drv_remove,
1936 .driver = {
1937 .name = CARDNAME,
bcd5149d 1938 .pm = &sh_eth_dev_pm_ops,
86a74ff2
NI		 1939 },
1940};
1941
1942static int __init sh_eth_init(void)
1943{
1944 return platform_driver_register(&sh_eth_driver);
1945}
1946
1947static void __exit sh_eth_cleanup(void)
1948{
1949 platform_driver_unregister(&sh_eth_driver);
1950}
1951
1952module_init(sh_eth_init);
1953module_exit(sh_eth_cleanup);
1954
1955MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
1956MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
1957MODULE_LICENSE("GPL v2");
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