]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/net/sis900.c
Fix common misspellings
[mirror_ubuntu-bionic-kernel.git] / drivers / net / sis900.c
CommitLineData
1da177e4 1/* sis900.c: A SiS 900/7016 PCI Fast Ethernet driver for Linux.
6aa20a22 2 Copyright 1999 Silicon Integrated System Corporation
d269a69f 3 Revision: 1.08.10 Apr. 2 2006
6aa20a22 4
1da177e4 5 Modified from the driver which is originally written by Donald Becker.
6aa20a22 6
1da177e4
LT
7 This software may be used and distributed according to the terms
8 of the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on this skeleton fall under the GPL and must retain
10 the authorship (implicit copyright) notice.
6aa20a22 11
1da177e4
LT
12 References:
13 SiS 7016 Fast Ethernet PCI Bus 10/100 Mbps LAN Controller with OnNow Support,
14 preliminary Rev. 1.0 Jan. 14, 1998
15 SiS 900 Fast Ethernet PCI Bus 10/100 Mbps LAN Single Chip with OnNow Support,
16 preliminary Rev. 1.0 Nov. 10, 1998
17 SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
18 preliminary Rev. 1.0 Jan. 18, 1998
19
d269a69f 20 Rev 1.08.10 Apr. 2 2006 Daniele Venzano add vlan (jumbo packets) support
ea37ccea 21 Rev 1.08.09 Sep. 19 2005 Daniele Venzano add Wake on LAN support
1da177e4 22 Rev 1.08.08 Jan. 22 2005 Daniele Venzano use netif_msg for debugging messages
d269a69f 23 Rev 1.08.07 Nov. 2 2003 Daniele Venzano <venza@brownhat.org> add suspend/resume support
1da177e4
LT
24 Rev 1.08.06 Sep. 24 2002 Mufasa Yang bug fix for Tx timeout & add SiS963 support
25 Rev 1.08.05 Jun. 6 2002 Mufasa Yang bug fix for read_eeprom & Tx descriptor over-boundary
26 Rev 1.08.04 Apr. 25 2002 Mufasa Yang <mufasa@sis.com.tw> added SiS962 support
27 Rev 1.08.03 Feb. 1 2002 Matt Domsch <Matt_Domsch@dell.com> update to use library crc32 function
28 Rev 1.08.02 Nov. 30 2001 Hui-Fen Hsu workaround for EDB & bug fix for dhcp problem
29 Rev 1.08.01 Aug. 25 2001 Hui-Fen Hsu update for 630ET & workaround for ICS1893 PHY
30 Rev 1.08.00 Jun. 11 2001 Hui-Fen Hsu workaround for RTL8201 PHY and some bug fix
31 Rev 1.07.11 Apr. 2 2001 Hui-Fen Hsu updates PCI drivers to use the new pci_set_dma_mask for kernel 2.4.3
6aa20a22 32 Rev 1.07.10 Mar. 1 2001 Hui-Fen Hsu <hfhsu@sis.com.tw> some bug fix & 635M/B support
1da177e4
LT
33 Rev 1.07.09 Feb. 9 2001 Dave Jones <davej@suse.de> PCI enable cleanup
34 Rev 1.07.08 Jan. 8 2001 Lei-Chun Chang added RTL8201 PHY support
35 Rev 1.07.07 Nov. 29 2000 Lei-Chun Chang added kernel-doc extractable documentation and 630 workaround fix
36 Rev 1.07.06 Nov. 7 2000 Jeff Garzik <jgarzik@pobox.com> some bug fix and cleaning
37 Rev 1.07.05 Nov. 6 2000 metapirat<metapirat@gmx.de> contribute media type select by ifconfig
38 Rev 1.07.04 Sep. 6 2000 Lei-Chun Chang added ICS1893 PHY support
b595076a 39 Rev 1.07.03 Aug. 24 2000 Lei-Chun Chang (lcchang@sis.com.tw) modified 630E equalizer workaround rule
1da177e4
LT
40 Rev 1.07.01 Aug. 08 2000 Ollie Lho minor update for SiS 630E and SiS 630E A1
41 Rev 1.07 Mar. 07 2000 Ollie Lho bug fix in Rx buffer ring
42 Rev 1.06.04 Feb. 11 2000 Jeff Garzik <jgarzik@pobox.com> softnet and init for kernel 2.4
43 Rev 1.06.03 Dec. 23 1999 Ollie Lho Third release
44 Rev 1.06.02 Nov. 23 1999 Ollie Lho bug in mac probing fixed
45 Rev 1.06.01 Nov. 16 1999 Ollie Lho CRC calculation provide by Joseph Zbiciak (im14u2c@primenet.com)
46 Rev 1.06 Nov. 4 1999 Ollie Lho (ollie@sis.com.tw) Second release
47 Rev 1.05.05 Oct. 29 1999 Ollie Lho (ollie@sis.com.tw) Single buffer Tx/Rx
48 Chin-Shan Li (lcs@sis.com.tw) Added AMD Am79c901 HomePNA PHY support
49 Rev 1.05 Aug. 7 1999 Jim Huang (cmhuang@sis.com.tw) Initial release
50*/
51
52#include <linux/module.h>
53#include <linux/moduleparam.h>
54#include <linux/kernel.h>
d43c36dc 55#include <linux/sched.h>
1da177e4
LT
56#include <linux/string.h>
57#include <linux/timer.h>
58#include <linux/errno.h>
59#include <linux/ioport.h>
60#include <linux/slab.h>
61#include <linux/interrupt.h>
62#include <linux/pci.h>
63#include <linux/netdevice.h>
64#include <linux/init.h>
65#include <linux/mii.h>
66#include <linux/etherdevice.h>
67#include <linux/skbuff.h>
68#include <linux/delay.h>
69#include <linux/ethtool.h>
70#include <linux/crc32.h>
71#include <linux/bitops.h>
12b279f9 72#include <linux/dma-mapping.h>
1da177e4
LT
73
74#include <asm/processor.h> /* Processor type for cache alignment. */
75#include <asm/io.h>
76#include <asm/irq.h>
77#include <asm/uaccess.h> /* User space memory access functions */
78
79#include "sis900.h"
80
81#define SIS900_MODULE_NAME "sis900"
d269a69f 82#define SIS900_DRV_VERSION "v1.08.10 Apr. 2 2006"
1da177e4 83
9a3c3de7
SH
84static const char version[] __devinitconst =
85 KERN_INFO "sis900.c: " SIS900_DRV_VERSION "\n";
1da177e4
LT
86
87static int max_interrupt_work = 40;
88static int multicast_filter_limit = 128;
89
90static int sis900_debug = -1; /* Use SIS900_DEF_MSG as value */
91
92#define SIS900_DEF_MSG \
93 (NETIF_MSG_DRV | \
94 NETIF_MSG_LINK | \
95 NETIF_MSG_RX_ERR | \
96 NETIF_MSG_TX_ERR)
97
98/* Time in jiffies before concluding the transmitter is hung. */
99#define TX_TIMEOUT (4*HZ)
1da177e4
LT
100
101enum {
102 SIS_900 = 0,
103 SIS_7016
104};
f71e1309 105static const char * card_names[] = {
1da177e4
LT
106 "SiS 900 PCI Fast Ethernet",
107 "SiS 7016 PCI Fast Ethernet"
108};
a3aa1884 109static DEFINE_PCI_DEVICE_TABLE(sis900_pci_tbl) = {
1da177e4
LT
110 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_900,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_900},
112 {PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_7016,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, SIS_7016},
114 {0,}
115};
116MODULE_DEVICE_TABLE (pci, sis900_pci_tbl);
117
118static void sis900_read_mode(struct net_device *net_dev, int *speed, int *duplex);
119
f71e1309 120static const struct mii_chip_info {
1da177e4
LT
121 const char * name;
122 u16 phy_id0;
123 u16 phy_id1;
124 u8 phy_types;
125#define HOME 0x0001
126#define LAN 0x0002
127#define MIX 0x0003
128#define UNKNOWN 0x0
129} mii_chip_table[] = {
130 { "SiS 900 Internal MII PHY", 0x001d, 0x8000, LAN },
131 { "SiS 7014 Physical Layer Solution", 0x0016, 0xf830, LAN },
d8e95e52 132 { "SiS 900 on Foxconn 661 7MI", 0x0143, 0xBC70, LAN },
1da177e4 133 { "Altimata AC101LF PHY", 0x0022, 0x5520, LAN },
494aced2 134 { "ADM 7001 LAN PHY", 0x002e, 0xcc60, LAN },
1da177e4
LT
135 { "AMD 79C901 10BASE-T PHY", 0x0000, 0x6B70, LAN },
136 { "AMD 79C901 HomePNA PHY", 0x0000, 0x6B90, HOME},
137 { "ICS LAN PHY", 0x0015, 0xF440, LAN },
80a8003f 138 { "ICS LAN PHY", 0x0143, 0xBC70, LAN },
1da177e4
LT
139 { "NS 83851 PHY", 0x2000, 0x5C20, MIX },
140 { "NS 83847 PHY", 0x2000, 0x5C30, MIX },
141 { "Realtek RTL8201 PHY", 0x0000, 0x8200, LAN },
142 { "VIA 6103 PHY", 0x0101, 0x8f20, LAN },
143 {NULL,},
144};
145
146struct mii_phy {
147 struct mii_phy * next;
148 int phy_addr;
149 u16 phy_id0;
150 u16 phy_id1;
151 u16 status;
152 u8 phy_types;
153};
154
155typedef struct _BufferDesc {
156 u32 link;
157 u32 cmdsts;
158 u32 bufptr;
159} BufferDesc;
160
161struct sis900_private {
1da177e4
LT
162 struct pci_dev * pci_dev;
163
164 spinlock_t lock;
165
166 struct mii_phy * mii;
167 struct mii_phy * first_mii; /* record the first mii structure */
168 unsigned int cur_phy;
da369b01 169 struct mii_if_info mii_info;
1da177e4
LT
170
171 struct timer_list timer; /* Link status detection timer. */
172 u8 autong_complete; /* 1: auto-negotiate complete */
173
174 u32 msg_enable;
175
176 unsigned int cur_rx, dirty_rx; /* producer/comsumer pointers for Tx/Rx ring */
177 unsigned int cur_tx, dirty_tx;
178
179 /* The saved address of a sent/receive-in-place packet buffer */
180 struct sk_buff *tx_skbuff[NUM_TX_DESC];
181 struct sk_buff *rx_skbuff[NUM_RX_DESC];
182 BufferDesc *tx_ring;
183 BufferDesc *rx_ring;
184
185 dma_addr_t tx_ring_dma;
186 dma_addr_t rx_ring_dma;
187
188 unsigned int tx_full; /* The Tx queue is full. */
189 u8 host_bridge_rev;
190 u8 chipset_rev;
191};
192
193MODULE_AUTHOR("Jim Huang <cmhuang@sis.com.tw>, Ollie Lho <ollie@sis.com.tw>");
194MODULE_DESCRIPTION("SiS 900 PCI Fast Ethernet driver");
195MODULE_LICENSE("GPL");
196
197module_param(multicast_filter_limit, int, 0444);
198module_param(max_interrupt_work, int, 0444);
199module_param(sis900_debug, int, 0444);
200MODULE_PARM_DESC(multicast_filter_limit, "SiS 900/7016 maximum number of filtered multicast addresses");
201MODULE_PARM_DESC(max_interrupt_work, "SiS 900/7016 maximum events handled per interrupt");
202MODULE_PARM_DESC(sis900_debug, "SiS 900/7016 bitmapped debugging message level");
203
204#ifdef CONFIG_NET_POLL_CONTROLLER
205static void sis900_poll(struct net_device *dev);
206#endif
207static int sis900_open(struct net_device *net_dev);
208static int sis900_mii_probe (struct net_device * net_dev);
209static void sis900_init_rxfilter (struct net_device * net_dev);
210static u16 read_eeprom(long ioaddr, int location);
da369b01 211static int mdio_read(struct net_device *net_dev, int phy_id, int location);
1da177e4
LT
212static void mdio_write(struct net_device *net_dev, int phy_id, int location, int val);
213static void sis900_timer(unsigned long data);
214static void sis900_check_mode (struct net_device *net_dev, struct mii_phy *mii_phy);
215static void sis900_tx_timeout(struct net_device *net_dev);
216static void sis900_init_tx_ring(struct net_device *net_dev);
217static void sis900_init_rx_ring(struct net_device *net_dev);
61357325
SH
218static netdev_tx_t sis900_start_xmit(struct sk_buff *skb,
219 struct net_device *net_dev);
1da177e4
LT
220static int sis900_rx(struct net_device *net_dev);
221static void sis900_finish_xmit (struct net_device *net_dev);
7d12e780 222static irqreturn_t sis900_interrupt(int irq, void *dev_instance);
1da177e4
LT
223static int sis900_close(struct net_device *net_dev);
224static int mii_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd);
1da177e4
LT
225static u16 sis900_mcast_bitnr(u8 *addr, u8 revision);
226static void set_rx_mode(struct net_device *net_dev);
227static void sis900_reset(struct net_device *net_dev);
228static void sis630_set_eq(struct net_device *net_dev, u8 revision);
229static int sis900_set_config(struct net_device *dev, struct ifmap *map);
230static u16 sis900_default_phy(struct net_device * net_dev);
231static void sis900_set_capability( struct net_device *net_dev ,struct mii_phy *phy);
232static u16 sis900_reset_phy(struct net_device *net_dev, int phy_addr);
233static void sis900_auto_negotiate(struct net_device *net_dev, int phy_addr);
234static void sis900_set_mode (long ioaddr, int speed, int duplex);
7282d491 235static const struct ethtool_ops sis900_ethtool_ops;
1da177e4
LT
236
237/**
238 * sis900_get_mac_addr - Get MAC address for stand alone SiS900 model
239 * @pci_dev: the sis900 pci device
6aa20a22 240 * @net_dev: the net device to get address for
1da177e4
LT
241 *
242 * Older SiS900 and friends, use EEPROM to store MAC address.
243 * MAC address is read from read_eeprom() into @net_dev->dev_addr.
244 */
245
246static int __devinit sis900_get_mac_addr(struct pci_dev * pci_dev, struct net_device *net_dev)
247{
248 long ioaddr = pci_resource_start(pci_dev, 0);
249 u16 signature;
250 int i;
251
252 /* check to see if we have sane EEPROM */
6aa20a22 253 signature = (u16) read_eeprom(ioaddr, EEPROMSignature);
1da177e4 254 if (signature == 0xffff || signature == 0x0000) {
6aa20a22 255 printk (KERN_WARNING "%s: Error EERPOM read %x\n",
1da177e4
LT
256 pci_name(pci_dev), signature);
257 return 0;
258 }
259
260 /* get MAC address from EEPROM */
261 for (i = 0; i < 3; i++)
262 ((u16 *)(net_dev->dev_addr))[i] = read_eeprom(ioaddr, i+EEPROMMACAddr);
263
264 return 1;
265}
266
267/**
268 * sis630e_get_mac_addr - Get MAC address for SiS630E model
269 * @pci_dev: the sis900 pci device
6aa20a22 270 * @net_dev: the net device to get address for
1da177e4
LT
271 *
272 * SiS630E model, use APC CMOS RAM to store MAC address.
273 * APC CMOS RAM is accessed through ISA bridge.
274 * MAC address is read into @net_dev->dev_addr.
275 */
276
277static int __devinit sis630e_get_mac_addr(struct pci_dev * pci_dev,
278 struct net_device *net_dev)
279{
280 struct pci_dev *isa_bridge = NULL;
281 u8 reg;
282 int i;
283
284 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0008, isa_bridge);
285 if (!isa_bridge)
286 isa_bridge = pci_get_device(PCI_VENDOR_ID_SI, 0x0018, isa_bridge);
287 if (!isa_bridge) {
288 printk(KERN_WARNING "%s: Can not find ISA bridge\n",
289 pci_name(pci_dev));
290 return 0;
291 }
292 pci_read_config_byte(isa_bridge, 0x48, &reg);
293 pci_write_config_byte(isa_bridge, 0x48, reg | 0x40);
294
295 for (i = 0; i < 6; i++) {
296 outb(0x09 + i, 0x70);
6aa20a22 297 ((u8 *)(net_dev->dev_addr))[i] = inb(0x71);
1da177e4
LT
298 }
299 pci_write_config_byte(isa_bridge, 0x48, reg & ~0x40);
300 pci_dev_put(isa_bridge);
301
302 return 1;
303}
304
305
306/**
307 * sis635_get_mac_addr - Get MAC address for SIS635 model
308 * @pci_dev: the sis900 pci device
6aa20a22 309 * @net_dev: the net device to get address for
1da177e4
LT
310 *
311 * SiS635 model, set MAC Reload Bit to load Mac address from APC
6aa20a22 312 * to rfdr. rfdr is accessed through rfcr. MAC address is read into
1da177e4
LT
313 * @net_dev->dev_addr.
314 */
315
316static int __devinit sis635_get_mac_addr(struct pci_dev * pci_dev,
317 struct net_device *net_dev)
318{
319 long ioaddr = net_dev->base_addr;
320 u32 rfcrSave;
321 u32 i;
322
323 rfcrSave = inl(rfcr + ioaddr);
324
325 outl(rfcrSave | RELOAD, ioaddr + cr);
326 outl(0, ioaddr + cr);
327
328 /* disable packet filtering before setting filter */
329 outl(rfcrSave & ~RFEN, rfcr + ioaddr);
330
331 /* load MAC addr to filter data register */
332 for (i = 0 ; i < 3 ; i++) {
333 outl((i << RFADDR_shift), ioaddr + rfcr);
334 *( ((u16 *)net_dev->dev_addr) + i) = inw(ioaddr + rfdr);
335 }
336
337 /* enable packet filtering */
338 outl(rfcrSave | RFEN, rfcr + ioaddr);
339
340 return 1;
341}
342
343/**
344 * sis96x_get_mac_addr - Get MAC address for SiS962 or SiS963 model
345 * @pci_dev: the sis900 pci device
6aa20a22 346 * @net_dev: the net device to get address for
1da177e4 347 *
6aa20a22 348 * SiS962 or SiS963 model, use EEPROM to store MAC address. And EEPROM
1da177e4 349 * is shared by
6aa20a22
JG
350 * LAN and 1394. When access EEPROM, send EEREQ signal to hardware first
351 * and wait for EEGNT. If EEGNT is ON, EEPROM is permitted to be access
1da177e4 352 * by LAN, otherwise is not. After MAC address is read from EEPROM, send
6aa20a22
JG
353 * EEDONE signal to refuse EEPROM access by LAN.
354 * The EEPROM map of SiS962 or SiS963 is different to SiS900.
355 * The signature field in SiS962 or SiS963 spec is meaningless.
1da177e4
LT
356 * MAC address is read into @net_dev->dev_addr.
357 */
358
359static int __devinit sis96x_get_mac_addr(struct pci_dev * pci_dev,
360 struct net_device *net_dev)
361{
362 long ioaddr = net_dev->base_addr;
363 long ee_addr = ioaddr + mear;
364 u32 waittime = 0;
365 int i;
6aa20a22 366
1da177e4
LT
367 outl(EEREQ, ee_addr);
368 while(waittime < 2000) {
369 if(inl(ee_addr) & EEGNT) {
370
371 /* get MAC address from EEPROM */
372 for (i = 0; i < 3; i++)
373 ((u16 *)(net_dev->dev_addr))[i] = read_eeprom(ioaddr, i+EEPROMMACAddr);
374
375 outl(EEDONE, ee_addr);
376 return 1;
377 } else {
6aa20a22 378 udelay(1);
1da177e4
LT
379 waittime ++;
380 }
381 }
382 outl(EEDONE, ee_addr);
383 return 0;
384}
385
09ab9e7c
SH
386static const struct net_device_ops sis900_netdev_ops = {
387 .ndo_open = sis900_open,
388 .ndo_stop = sis900_close,
389 .ndo_start_xmit = sis900_start_xmit,
390 .ndo_set_config = sis900_set_config,
391 .ndo_set_multicast_list = set_rx_mode,
392 .ndo_change_mtu = eth_change_mtu,
393 .ndo_validate_addr = eth_validate_addr,
fe96aaa1 394 .ndo_set_mac_address = eth_mac_addr,
09ab9e7c
SH
395 .ndo_do_ioctl = mii_ioctl,
396 .ndo_tx_timeout = sis900_tx_timeout,
397#ifdef CONFIG_NET_POLL_CONTROLLER
398 .ndo_poll_controller = sis900_poll,
399#endif
400};
401
1da177e4
LT
402/**
403 * sis900_probe - Probe for sis900 device
404 * @pci_dev: the sis900 pci device
405 * @pci_id: the pci device ID
406 *
407 * Check and probe sis900 net device for @pci_dev.
6aa20a22 408 * Get mac address according to the chip revision,
1da177e4
LT
409 * and assign SiS900-specific entries in the device structure.
410 * ie: sis900_open(), sis900_start_xmit(), sis900_close(), etc.
411 */
412
413static int __devinit sis900_probe(struct pci_dev *pci_dev,
414 const struct pci_device_id *pci_id)
415{
416 struct sis900_private *sis_priv;
417 struct net_device *net_dev;
418 struct pci_dev *dev;
419 dma_addr_t ring_dma;
420 void *ring_space;
421 long ioaddr;
422 int i, ret;
f71e1309 423 const char *card_name = card_names[pci_id->driver_data];
1da177e4
LT
424 const char *dev_name = pci_name(pci_dev);
425
426/* when built into the kernel, we only print version if device is found */
427#ifndef MODULE
428 static int printed_version;
429 if (!printed_version++)
430 printk(version);
431#endif
432
433 /* setup various bits in PCI command register */
434 ret = pci_enable_device(pci_dev);
435 if(ret) return ret;
6aa20a22 436
284901a9 437 i = pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32));
1da177e4 438 if(i){
2450022a 439 printk(KERN_ERR "sis900.c: architecture does not support "
1da177e4
LT
440 "32bit PCI busmaster DMA\n");
441 return i;
442 }
6aa20a22 443
1da177e4 444 pci_set_master(pci_dev);
6aa20a22 445
1da177e4
LT
446 net_dev = alloc_etherdev(sizeof(struct sis900_private));
447 if (!net_dev)
448 return -ENOMEM;
1da177e4
LT
449 SET_NETDEV_DEV(net_dev, &pci_dev->dev);
450
451 /* We do a request_region() to register /proc/ioports info. */
6aa20a22 452 ioaddr = pci_resource_start(pci_dev, 0);
1da177e4
LT
453 ret = pci_request_regions(pci_dev, "sis900");
454 if (ret)
455 goto err_out;
456
8f15ea42 457 sis_priv = netdev_priv(net_dev);
1da177e4
LT
458 net_dev->base_addr = ioaddr;
459 net_dev->irq = pci_dev->irq;
460 sis_priv->pci_dev = pci_dev;
461 spin_lock_init(&sis_priv->lock);
462
463 pci_set_drvdata(pci_dev, net_dev);
464
465 ring_space = pci_alloc_consistent(pci_dev, TX_TOTAL_SIZE, &ring_dma);
466 if (!ring_space) {
467 ret = -ENOMEM;
468 goto err_out_cleardev;
469 }
470 sis_priv->tx_ring = (BufferDesc *)ring_space;
471 sis_priv->tx_ring_dma = ring_dma;
472
473 ring_space = pci_alloc_consistent(pci_dev, RX_TOTAL_SIZE, &ring_dma);
474 if (!ring_space) {
475 ret = -ENOMEM;
476 goto err_unmap_tx;
477 }
478 sis_priv->rx_ring = (BufferDesc *)ring_space;
479 sis_priv->rx_ring_dma = ring_dma;
6aa20a22 480
1da177e4 481 /* The SiS900-specific entries in the device structure. */
09ab9e7c 482 net_dev->netdev_ops = &sis900_netdev_ops;
1da177e4
LT
483 net_dev->watchdog_timeo = TX_TIMEOUT;
484 net_dev->ethtool_ops = &sis900_ethtool_ops;
485
1da177e4
LT
486 if (sis900_debug > 0)
487 sis_priv->msg_enable = sis900_debug;
488 else
489 sis_priv->msg_enable = SIS900_DEF_MSG;
da369b01
DV
490
491 sis_priv->mii_info.dev = net_dev;
492 sis_priv->mii_info.mdio_read = mdio_read;
493 sis_priv->mii_info.mdio_write = mdio_write;
494 sis_priv->mii_info.phy_id_mask = 0x1f;
495 sis_priv->mii_info.reg_num_mask = 0x1f;
496
1da177e4 497 /* Get Mac address according to the chip revision */
eaaa3a7c 498 sis_priv->chipset_rev = pci_dev->revision;
1da177e4
LT
499 if(netif_msg_probe(sis_priv))
500 printk(KERN_DEBUG "%s: detected revision %2.2x, "
501 "trying to get MAC address...\n",
502 dev_name, sis_priv->chipset_rev);
6aa20a22 503
1da177e4
LT
504 ret = 0;
505 if (sis_priv->chipset_rev == SIS630E_900_REV)
506 ret = sis630e_get_mac_addr(pci_dev, net_dev);
507 else if ((sis_priv->chipset_rev > 0x81) && (sis_priv->chipset_rev <= 0x90) )
508 ret = sis635_get_mac_addr(pci_dev, net_dev);
509 else if (sis_priv->chipset_rev == SIS96x_900_REV)
510 ret = sis96x_get_mac_addr(pci_dev, net_dev);
511 else
512 ret = sis900_get_mac_addr(pci_dev, net_dev);
513
d1d5e6b1
DV
514 if (!ret || !is_valid_ether_addr(net_dev->dev_addr)) {
515 random_ether_addr(net_dev->dev_addr);
516 printk(KERN_WARNING "%s: Unreadable or invalid MAC address,"
517 "using random generated one\n", dev_name);
1da177e4 518 }
6aa20a22 519
1da177e4
LT
520 /* 630ET : set the mii access mode as software-mode */
521 if (sis_priv->chipset_rev == SIS630ET_900_REV)
522 outl(ACCESSMODE | inl(ioaddr + cr), ioaddr + cr);
523
524 /* probe for mii transceiver */
525 if (sis900_mii_probe(net_dev) == 0) {
526 printk(KERN_WARNING "%s: Error probing MII device.\n",
527 dev_name);
528 ret = -ENODEV;
529 goto err_unmap_rx;
530 }
531
532 /* save our host bridge revision */
533 dev = pci_get_device(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_630, NULL);
534 if (dev) {
eaaa3a7c 535 sis_priv->host_bridge_rev = dev->revision;
1da177e4
LT
536 pci_dev_put(dev);
537 }
538
539 ret = register_netdev(net_dev);
540 if (ret)
541 goto err_unmap_rx;
542
543 /* print some information about our NIC */
e174961c 544 printk(KERN_INFO "%s: %s at %#lx, IRQ %d, %pM\n",
0795af57 545 net_dev->name, card_name, ioaddr, net_dev->irq,
e174961c 546 net_dev->dev_addr);
1da177e4 547
ea37ccea 548 /* Detect Wake on Lan support */
7bef4b39 549 ret = (inl(net_dev->base_addr + CFGPMC) & PMESP) >> 27;
ea37ccea
DV
550 if (netif_msg_probe(sis_priv) && (ret & PME_D3C) == 0)
551 printk(KERN_INFO "%s: Wake on LAN only available from suspend to RAM.", net_dev->name);
552
1da177e4
LT
553 return 0;
554
555 err_unmap_rx:
556 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
557 sis_priv->rx_ring_dma);
558 err_unmap_tx:
559 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
560 sis_priv->tx_ring_dma);
561 err_out_cleardev:
562 pci_set_drvdata(pci_dev, NULL);
563 pci_release_regions(pci_dev);
564 err_out:
565 free_netdev(net_dev);
566 return ret;
567}
568
569/**
570 * sis900_mii_probe - Probe MII PHY for sis900
571 * @net_dev: the net device to probe for
6aa20a22 572 *
1da177e4
LT
573 * Search for total of 32 possible mii phy addresses.
574 * Identify and set current phy if found one,
575 * return error if it failed to found.
576 */
577
4e50a8e3 578static int __devinit sis900_mii_probe(struct net_device * net_dev)
1da177e4 579{
8f15ea42 580 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
581 const char *dev_name = pci_name(sis_priv->pci_dev);
582 u16 poll_bit = MII_STAT_LINK, status = 0;
583 unsigned long timeout = jiffies + 5 * HZ;
584 int phy_addr;
585
586 sis_priv->mii = NULL;
587
588 /* search for total of 32 possible mii phy addresses */
6aa20a22 589 for (phy_addr = 0; phy_addr < 32; phy_addr++) {
1da177e4
LT
590 struct mii_phy * mii_phy = NULL;
591 u16 mii_status;
592 int i;
593
594 mii_phy = NULL;
595 for(i = 0; i < 2; i++)
596 mii_status = mdio_read(net_dev, phy_addr, MII_STATUS);
597
598 if (mii_status == 0xffff || mii_status == 0x0000) {
599 if (netif_msg_probe(sis_priv))
600 printk(KERN_DEBUG "%s: MII at address %d"
601 " not accessible\n",
602 dev_name, phy_addr);
603 continue;
604 }
6aa20a22 605
1da177e4
LT
606 if ((mii_phy = kmalloc(sizeof(struct mii_phy), GFP_KERNEL)) == NULL) {
607 printk(KERN_WARNING "Cannot allocate mem for struct mii_phy\n");
608 mii_phy = sis_priv->first_mii;
609 while (mii_phy) {
610 struct mii_phy *phy;
611 phy = mii_phy;
612 mii_phy = mii_phy->next;
613 kfree(phy);
614 }
615 return 0;
616 }
6aa20a22 617
1da177e4 618 mii_phy->phy_id0 = mdio_read(net_dev, phy_addr, MII_PHY_ID0);
6aa20a22 619 mii_phy->phy_id1 = mdio_read(net_dev, phy_addr, MII_PHY_ID1);
1da177e4
LT
620 mii_phy->phy_addr = phy_addr;
621 mii_phy->status = mii_status;
622 mii_phy->next = sis_priv->mii;
623 sis_priv->mii = mii_phy;
624 sis_priv->first_mii = mii_phy;
625
626 for (i = 0; mii_chip_table[i].phy_id1; i++)
627 if ((mii_phy->phy_id0 == mii_chip_table[i].phy_id0 ) &&
628 ((mii_phy->phy_id1 & 0xFFF0) == mii_chip_table[i].phy_id1)){
629 mii_phy->phy_types = mii_chip_table[i].phy_types;
630 if (mii_chip_table[i].phy_types == MIX)
631 mii_phy->phy_types =
632 (mii_status & (MII_STAT_CAN_TX_FDX | MII_STAT_CAN_TX)) ? LAN : HOME;
633 printk(KERN_INFO "%s: %s transceiver found "
634 "at address %d.\n",
635 dev_name,
636 mii_chip_table[i].name,
637 phy_addr);
638 break;
639 }
6aa20a22 640
1da177e4
LT
641 if( !mii_chip_table[i].phy_id1 ) {
642 printk(KERN_INFO "%s: Unknown PHY transceiver found at address %d.\n",
643 dev_name, phy_addr);
644 mii_phy->phy_types = UNKNOWN;
645 }
646 }
6aa20a22 647
1da177e4
LT
648 if (sis_priv->mii == NULL) {
649 printk(KERN_INFO "%s: No MII transceivers found!\n", dev_name);
650 return 0;
651 }
652
653 /* select default PHY for mac */
654 sis_priv->mii = NULL;
655 sis900_default_phy( net_dev );
656
657 /* Reset phy if default phy is internal sis900 */
658 if ((sis_priv->mii->phy_id0 == 0x001D) &&
659 ((sis_priv->mii->phy_id1&0xFFF0) == 0x8000))
660 status = sis900_reset_phy(net_dev, sis_priv->cur_phy);
6aa20a22 661
1da177e4
LT
662 /* workaround for ICS1893 PHY */
663 if ((sis_priv->mii->phy_id0 == 0x0015) &&
664 ((sis_priv->mii->phy_id1&0xFFF0) == 0xF440))
665 mdio_write(net_dev, sis_priv->cur_phy, 0x0018, 0xD200);
666
667 if(status & MII_STAT_LINK){
668 while (poll_bit) {
669 yield();
670
671 poll_bit ^= (mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS) & poll_bit);
672 if (time_after_eq(jiffies, timeout)) {
673 printk(KERN_WARNING "%s: reset phy and link down now\n",
674 dev_name);
675 return -ETIME;
676 }
677 }
678 }
679
680 if (sis_priv->chipset_rev == SIS630E_900_REV) {
681 /* SiS 630E has some bugs on default value of PHY registers */
682 mdio_write(net_dev, sis_priv->cur_phy, MII_ANADV, 0x05e1);
683 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG1, 0x22);
684 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG2, 0xff00);
685 mdio_write(net_dev, sis_priv->cur_phy, MII_MASK, 0xffc0);
6aa20a22 686 //mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, 0x1000);
1da177e4
LT
687 }
688
689 if (sis_priv->mii->status & MII_STAT_LINK)
690 netif_carrier_on(net_dev);
691 else
692 netif_carrier_off(net_dev);
693
694 return 1;
695}
696
697/**
698 * sis900_default_phy - Select default PHY for sis900 mac.
699 * @net_dev: the net device to probe for
700 *
701 * Select first detected PHY with link as default.
702 * If no one is link on, select PHY whose types is HOME as default.
703 * If HOME doesn't exist, select LAN.
704 */
705
706static u16 sis900_default_phy(struct net_device * net_dev)
707{
8f15ea42 708 struct sis900_private *sis_priv = netdev_priv(net_dev);
6aa20a22 709 struct mii_phy *phy = NULL, *phy_home = NULL,
1da177e4
LT
710 *default_phy = NULL, *phy_lan = NULL;
711 u16 status;
712
713 for (phy=sis_priv->first_mii; phy; phy=phy->next) {
714 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
715 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
716
717 /* Link ON & Not select default PHY & not ghost PHY */
718 if ((status & MII_STAT_LINK) && !default_phy &&
719 (phy->phy_types != UNKNOWN))
720 default_phy = phy;
721 else {
722 status = mdio_read(net_dev, phy->phy_addr, MII_CONTROL);
723 mdio_write(net_dev, phy->phy_addr, MII_CONTROL,
724 status | MII_CNTL_AUTO | MII_CNTL_ISOLATE);
725 if (phy->phy_types == HOME)
726 phy_home = phy;
727 else if(phy->phy_types == LAN)
728 phy_lan = phy;
729 }
730 }
731
732 if (!default_phy && phy_home)
733 default_phy = phy_home;
734 else if (!default_phy && phy_lan)
735 default_phy = phy_lan;
736 else if (!default_phy)
737 default_phy = sis_priv->first_mii;
738
739 if (sis_priv->mii != default_phy) {
740 sis_priv->mii = default_phy;
741 sis_priv->cur_phy = default_phy->phy_addr;
742 printk(KERN_INFO "%s: Using transceiver found at address %d as default\n",
743 pci_name(sis_priv->pci_dev), sis_priv->cur_phy);
744 }
6aa20a22 745
da369b01
DV
746 sis_priv->mii_info.phy_id = sis_priv->cur_phy;
747
1da177e4
LT
748 status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL);
749 status &= (~MII_CNTL_ISOLATE);
750
6aa20a22 751 mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, status);
1da177e4
LT
752 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
753 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
754
6aa20a22 755 return status;
1da177e4
LT
756}
757
758
759/**
760 * sis900_set_capability - set the media capability of network adapter.
761 * @net_dev : the net device to probe for
762 * @phy : default PHY
763 *
764 * Set the media capability of network adapter according to
765 * mii status register. It's necessary before auto-negotiate.
766 */
6aa20a22 767
1da177e4
LT
768static void sis900_set_capability(struct net_device *net_dev, struct mii_phy *phy)
769{
770 u16 cap;
771 u16 status;
6aa20a22 772
1da177e4
LT
773 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
774 status = mdio_read(net_dev, phy->phy_addr, MII_STATUS);
6aa20a22 775
1da177e4
LT
776 cap = MII_NWAY_CSMA_CD |
777 ((phy->status & MII_STAT_CAN_TX_FDX)? MII_NWAY_TX_FDX:0) |
778 ((phy->status & MII_STAT_CAN_TX) ? MII_NWAY_TX:0) |
779 ((phy->status & MII_STAT_CAN_T_FDX) ? MII_NWAY_T_FDX:0)|
780 ((phy->status & MII_STAT_CAN_T) ? MII_NWAY_T:0);
781
782 mdio_write(net_dev, phy->phy_addr, MII_ANADV, cap);
783}
784
785
786/* Delay between EEPROM clock transitions. */
787#define eeprom_delay() inl(ee_addr)
788
789/**
790 * read_eeprom - Read Serial EEPROM
791 * @ioaddr: base i/o address
792 * @location: the EEPROM location to read
793 *
794 * Read Serial EEPROM through EEPROM Access Register.
795 * Note that location is in word (16 bits) unit
796 */
797
798static u16 __devinit read_eeprom(long ioaddr, int location)
799{
800 int i;
801 u16 retval = 0;
802 long ee_addr = ioaddr + mear;
803 u32 read_cmd = location | EEread;
804
805 outl(0, ee_addr);
806 eeprom_delay();
807 outl(EECS, ee_addr);
808 eeprom_delay();
809
810 /* Shift the read command (9) bits out. */
811 for (i = 8; i >= 0; i--) {
812 u32 dataval = (read_cmd & (1 << i)) ? EEDI | EECS : EECS;
813 outl(dataval, ee_addr);
814 eeprom_delay();
815 outl(dataval | EECLK, ee_addr);
816 eeprom_delay();
817 }
818 outl(EECS, ee_addr);
819 eeprom_delay();
820
821 /* read the 16-bits data in */
822 for (i = 16; i > 0; i--) {
823 outl(EECS, ee_addr);
824 eeprom_delay();
825 outl(EECS | EECLK, ee_addr);
826 eeprom_delay();
827 retval = (retval << 1) | ((inl(ee_addr) & EEDO) ? 1 : 0);
828 eeprom_delay();
829 }
830
831 /* Terminate the EEPROM access. */
832 outl(0, ee_addr);
833 eeprom_delay();
834
807540ba 835 return retval;
1da177e4
LT
836}
837
838/* Read and write the MII management registers using software-generated
839 serial MDIO protocol. Note that the command bits and data bits are
840 send out separately */
841#define mdio_delay() inl(mdio_addr)
842
843static void mdio_idle(long mdio_addr)
844{
845 outl(MDIO | MDDIR, mdio_addr);
846 mdio_delay();
847 outl(MDIO | MDDIR | MDC, mdio_addr);
848}
849
850/* Syncronize the MII management interface by shifting 32 one bits out. */
851static void mdio_reset(long mdio_addr)
852{
853 int i;
854
855 for (i = 31; i >= 0; i--) {
856 outl(MDDIR | MDIO, mdio_addr);
857 mdio_delay();
858 outl(MDDIR | MDIO | MDC, mdio_addr);
859 mdio_delay();
860 }
1da177e4
LT
861}
862
863/**
864 * mdio_read - read MII PHY register
865 * @net_dev: the net device to read
866 * @phy_id: the phy address to read
867 * @location: the phy regiester id to read
868 *
869 * Read MII registers through MDIO and MDC
870 * using MDIO management frame structure and protocol(defined by ISO/IEC).
871 * Please see SiS7014 or ICS spec
872 */
873
da369b01 874static int mdio_read(struct net_device *net_dev, int phy_id, int location)
1da177e4
LT
875{
876 long mdio_addr = net_dev->base_addr + mear;
877 int mii_cmd = MIIread|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
878 u16 retval = 0;
879 int i;
880
881 mdio_reset(mdio_addr);
882 mdio_idle(mdio_addr);
883
884 for (i = 15; i >= 0; i--) {
885 int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR;
886 outl(dataval, mdio_addr);
887 mdio_delay();
888 outl(dataval | MDC, mdio_addr);
889 mdio_delay();
890 }
891
892 /* Read the 16 data bits. */
893 for (i = 16; i > 0; i--) {
894 outl(0, mdio_addr);
895 mdio_delay();
896 retval = (retval << 1) | ((inl(mdio_addr) & MDIO) ? 1 : 0);
897 outl(MDC, mdio_addr);
898 mdio_delay();
899 }
900 outl(0x00, mdio_addr);
901
902 return retval;
903}
904
905/**
906 * mdio_write - write MII PHY register
907 * @net_dev: the net device to write
908 * @phy_id: the phy address to write
909 * @location: the phy regiester id to write
910 * @value: the register value to write with
911 *
912 * Write MII registers with @value through MDIO and MDC
913 * using MDIO management frame structure and protocol(defined by ISO/IEC)
914 * please see SiS7014 or ICS spec
915 */
916
917static void mdio_write(struct net_device *net_dev, int phy_id, int location,
918 int value)
919{
920 long mdio_addr = net_dev->base_addr + mear;
921 int mii_cmd = MIIwrite|(phy_id<<MIIpmdShift)|(location<<MIIregShift);
922 int i;
923
924 mdio_reset(mdio_addr);
925 mdio_idle(mdio_addr);
926
927 /* Shift the command bits out. */
928 for (i = 15; i >= 0; i--) {
929 int dataval = (mii_cmd & (1 << i)) ? MDDIR | MDIO : MDDIR;
930 outb(dataval, mdio_addr);
931 mdio_delay();
932 outb(dataval | MDC, mdio_addr);
933 mdio_delay();
934 }
935 mdio_delay();
936
937 /* Shift the value bits out. */
938 for (i = 15; i >= 0; i--) {
939 int dataval = (value & (1 << i)) ? MDDIR | MDIO : MDDIR;
940 outl(dataval, mdio_addr);
941 mdio_delay();
942 outl(dataval | MDC, mdio_addr);
943 mdio_delay();
944 }
945 mdio_delay();
946
947 /* Clear out extra bits. */
948 for (i = 2; i > 0; i--) {
949 outb(0, mdio_addr);
950 mdio_delay();
951 outb(MDC, mdio_addr);
952 mdio_delay();
953 }
954 outl(0x00, mdio_addr);
1da177e4
LT
955}
956
957
958/**
959 * sis900_reset_phy - reset sis900 mii phy.
960 * @net_dev: the net device to write
961 * @phy_addr: default phy address
962 *
963 * Some specific phy can't work properly without reset.
964 * This function will be called during initialization and
965 * link status change from ON to DOWN.
966 */
967
968static u16 sis900_reset_phy(struct net_device *net_dev, int phy_addr)
969{
f3be9742 970 int i;
1da177e4
LT
971 u16 status;
972
f3be9742 973 for (i = 0; i < 2; i++)
1da177e4
LT
974 status = mdio_read(net_dev, phy_addr, MII_STATUS);
975
976 mdio_write( net_dev, phy_addr, MII_CONTROL, MII_CNTL_RESET );
6aa20a22 977
1da177e4
LT
978 return status;
979}
980
981#ifdef CONFIG_NET_POLL_CONTROLLER
982/*
983 * Polling 'interrupt' - used by things like netconsole to send skbs
984 * without having to re-enable interrupts. It's not called while
985 * the interrupt routine is executing.
986*/
987static void sis900_poll(struct net_device *dev)
988{
989 disable_irq(dev->irq);
7d12e780 990 sis900_interrupt(dev->irq, dev);
1da177e4
LT
991 enable_irq(dev->irq);
992}
993#endif
994
995/**
996 * sis900_open - open sis900 device
997 * @net_dev: the net device to open
998 *
999 * Do some initialization and start net interface.
1000 * enable interrupts and set sis900 timer.
1001 */
1002
1003static int
1004sis900_open(struct net_device *net_dev)
1005{
8f15ea42 1006 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1007 long ioaddr = net_dev->base_addr;
1008 int ret;
1009
1010 /* Soft reset the chip. */
1011 sis900_reset(net_dev);
1012
1013 /* Equalizer workaround Rule */
1014 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1015
a0607fd3 1016 ret = request_irq(net_dev->irq, sis900_interrupt, IRQF_SHARED,
1da177e4
LT
1017 net_dev->name, net_dev);
1018 if (ret)
1019 return ret;
1020
1021 sis900_init_rxfilter(net_dev);
1022
1023 sis900_init_tx_ring(net_dev);
1024 sis900_init_rx_ring(net_dev);
1025
1026 set_rx_mode(net_dev);
1027
1028 netif_start_queue(net_dev);
1029
1030 /* Workaround for EDB */
1031 sis900_set_mode(ioaddr, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
1032
1033 /* Enable all known interrupts by setting the interrupt mask. */
1034 outl((RxSOVR|RxORN|RxERR|RxOK|TxURN|TxERR|TxIDLE), ioaddr + imr);
1035 outl(RxENA | inl(ioaddr + cr), ioaddr + cr);
1036 outl(IE, ioaddr + ier);
1037
1038 sis900_check_mode(net_dev, sis_priv->mii);
1039
1040 /* Set the timer to switch to check for link beat and perhaps switch
1041 to an alternate media type. */
1042 init_timer(&sis_priv->timer);
1043 sis_priv->timer.expires = jiffies + HZ;
1044 sis_priv->timer.data = (unsigned long)net_dev;
c061b18d 1045 sis_priv->timer.function = sis900_timer;
1da177e4
LT
1046 add_timer(&sis_priv->timer);
1047
1048 return 0;
1049}
1050
1051/**
1052 * sis900_init_rxfilter - Initialize the Rx filter
1053 * @net_dev: the net device to initialize for
1054 *
1055 * Set receive filter address to our MAC address
1056 * and enable packet filtering.
1057 */
1058
1059static void
1060sis900_init_rxfilter (struct net_device * net_dev)
1061{
8f15ea42 1062 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1063 long ioaddr = net_dev->base_addr;
1064 u32 rfcrSave;
1065 u32 i;
1066
1067 rfcrSave = inl(rfcr + ioaddr);
1068
1069 /* disable packet filtering before setting filter */
1070 outl(rfcrSave & ~RFEN, rfcr + ioaddr);
1071
1072 /* load MAC addr to filter data register */
1073 for (i = 0 ; i < 3 ; i++) {
1074 u32 w;
1075
1076 w = (u32) *((u16 *)(net_dev->dev_addr)+i);
1077 outl((i << RFADDR_shift), ioaddr + rfcr);
1078 outl(w, ioaddr + rfdr);
1079
1080 if (netif_msg_hw(sis_priv)) {
1081 printk(KERN_DEBUG "%s: Receive Filter Addrss[%d]=%x\n",
1082 net_dev->name, i, inl(ioaddr + rfdr));
1083 }
1084 }
1085
1086 /* enable packet filtering */
1087 outl(rfcrSave | RFEN, rfcr + ioaddr);
1088}
1089
1090/**
1091 * sis900_init_tx_ring - Initialize the Tx descriptor ring
1092 * @net_dev: the net device to initialize for
1093 *
6aa20a22 1094 * Initialize the Tx descriptor ring,
1da177e4
LT
1095 */
1096
1097static void
1098sis900_init_tx_ring(struct net_device *net_dev)
1099{
8f15ea42 1100 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1101 long ioaddr = net_dev->base_addr;
1102 int i;
1103
1104 sis_priv->tx_full = 0;
1105 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1106
1107 for (i = 0; i < NUM_TX_DESC; i++) {
1108 sis_priv->tx_skbuff[i] = NULL;
1109
1110 sis_priv->tx_ring[i].link = sis_priv->tx_ring_dma +
1111 ((i+1)%NUM_TX_DESC)*sizeof(BufferDesc);
1112 sis_priv->tx_ring[i].cmdsts = 0;
1113 sis_priv->tx_ring[i].bufptr = 0;
1114 }
1115
1116 /* load Transmit Descriptor Register */
1117 outl(sis_priv->tx_ring_dma, ioaddr + txdp);
1118 if (netif_msg_hw(sis_priv))
1119 printk(KERN_DEBUG "%s: TX descriptor register loaded with: %8.8x\n",
1120 net_dev->name, inl(ioaddr + txdp));
1121}
1122
1123/**
1124 * sis900_init_rx_ring - Initialize the Rx descriptor ring
1125 * @net_dev: the net device to initialize for
1126 *
6aa20a22 1127 * Initialize the Rx descriptor ring,
1da177e4
LT
1128 * and pre-allocate recevie buffers (socket buffer)
1129 */
1130
6aa20a22 1131static void
1da177e4
LT
1132sis900_init_rx_ring(struct net_device *net_dev)
1133{
8f15ea42 1134 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1135 long ioaddr = net_dev->base_addr;
1136 int i;
1137
1138 sis_priv->cur_rx = 0;
1139 sis_priv->dirty_rx = 0;
1140
1141 /* init RX descriptor */
1142 for (i = 0; i < NUM_RX_DESC; i++) {
1143 sis_priv->rx_skbuff[i] = NULL;
1144
1145 sis_priv->rx_ring[i].link = sis_priv->rx_ring_dma +
1146 ((i+1)%NUM_RX_DESC)*sizeof(BufferDesc);
1147 sis_priv->rx_ring[i].cmdsts = 0;
1148 sis_priv->rx_ring[i].bufptr = 0;
1149 }
1150
1151 /* allocate sock buffers */
1152 for (i = 0; i < NUM_RX_DESC; i++) {
1153 struct sk_buff *skb;
1154
1155 if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
1156 /* not enough memory for skbuff, this makes a "hole"
1157 on the buffer ring, it is not clear how the
1158 hardware will react to this kind of degenerated
1159 buffer */
1160 break;
1161 }
1da177e4
LT
1162 sis_priv->rx_skbuff[i] = skb;
1163 sis_priv->rx_ring[i].cmdsts = RX_BUF_SIZE;
1164 sis_priv->rx_ring[i].bufptr = pci_map_single(sis_priv->pci_dev,
689be439 1165 skb->data, RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1da177e4
LT
1166 }
1167 sis_priv->dirty_rx = (unsigned int) (i - NUM_RX_DESC);
1168
1169 /* load Receive Descriptor Register */
1170 outl(sis_priv->rx_ring_dma, ioaddr + rxdp);
1171 if (netif_msg_hw(sis_priv))
1172 printk(KERN_DEBUG "%s: RX descriptor register loaded with: %8.8x\n",
1173 net_dev->name, inl(ioaddr + rxdp));
1174}
1175
1176/**
1177 * sis630_set_eq - set phy equalizer value for 630 LAN
1178 * @net_dev: the net device to set equalizer value
1179 * @revision: 630 LAN revision number
1180 *
1181 * 630E equalizer workaround rule(Cyrus Huang 08/15)
1182 * PHY register 14h(Test)
25985edc 1183 * Bit 14: 0 -- Automatically detect (default)
1da177e4
LT
1184 * 1 -- Manually set Equalizer filter
1185 * Bit 13: 0 -- (Default)
1186 * 1 -- Speed up convergence of equalizer setting
1187 * Bit 9 : 0 -- (Default)
1188 * 1 -- Disable Baseline Wander
1189 * Bit 3~7 -- Equalizer filter setting
1190 * Link ON: Set Bit 9, 13 to 1, Bit 14 to 0
1191 * Then calculate equalizer value
1192 * Then set equalizer value, and set Bit 14 to 1, Bit 9 to 0
1193 * Link Off:Set Bit 13 to 1, Bit 14 to 0
1194 * Calculate Equalizer value:
25985edc 1195 * When Link is ON and Bit 14 is 0, SIS900PHY will auto-detect proper equalizer value.
1da177e4
LT
1196 * When the equalizer is stable, this value is not a fixed value. It will be within
1197 * a small range(eg. 7~9). Then we get a minimum and a maximum value(eg. min=7, max=9)
1198 * 0 <= max <= 4 --> set equalizer to max
1199 * 5 <= max <= 14 --> set equalizer to max+1 or set equalizer to max+2 if max == min
1200 * max >= 15 --> set equalizer to max+5 or set equalizer to max+6 if max == min
1201 */
1202
1203static void sis630_set_eq(struct net_device *net_dev, u8 revision)
1204{
8f15ea42 1205 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1206 u16 reg14h, eq_value=0, max_value=0, min_value=0;
1207 int i, maxcount=10;
1208
1209 if ( !(revision == SIS630E_900_REV || revision == SIS630EA1_900_REV ||
1210 revision == SIS630A_900_REV || revision == SIS630ET_900_REV) )
1211 return;
1212
1213 if (netif_carrier_ok(net_dev)) {
1214 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1215 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1216 (0x2200 | reg14h) & 0xBFFF);
1217 for (i=0; i < maxcount; i++) {
1218 eq_value = (0x00F8 & mdio_read(net_dev,
1219 sis_priv->cur_phy, MII_RESV)) >> 3;
1220 if (i == 0)
1221 max_value=min_value=eq_value;
1222 max_value = (eq_value > max_value) ?
1223 eq_value : max_value;
1224 min_value = (eq_value < min_value) ?
1225 eq_value : min_value;
1226 }
1227 /* 630E rule to determine the equalizer value */
1228 if (revision == SIS630E_900_REV || revision == SIS630EA1_900_REV ||
1229 revision == SIS630ET_900_REV) {
1230 if (max_value < 5)
1231 eq_value = max_value;
1232 else if (max_value >= 5 && max_value < 15)
1233 eq_value = (max_value == min_value) ?
1234 max_value+2 : max_value+1;
1235 else if (max_value >= 15)
1236 eq_value=(max_value == min_value) ?
1237 max_value+6 : max_value+5;
1238 }
1239 /* 630B0&B1 rule to determine the equalizer value */
6aa20a22
JG
1240 if (revision == SIS630A_900_REV &&
1241 (sis_priv->host_bridge_rev == SIS630B0 ||
1da177e4
LT
1242 sis_priv->host_bridge_rev == SIS630B1)) {
1243 if (max_value == 0)
1244 eq_value = 3;
1245 else
1246 eq_value = (max_value + min_value + 1)/2;
1247 }
1248 /* write equalizer value and setting */
1249 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1250 reg14h = (reg14h & 0xFF07) | ((eq_value << 3) & 0x00F8);
1251 reg14h = (reg14h | 0x6000) & 0xFDFF;
1252 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV, reg14h);
1253 } else {
1254 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
6aa20a22
JG
1255 if (revision == SIS630A_900_REV &&
1256 (sis_priv->host_bridge_rev == SIS630B0 ||
1257 sis_priv->host_bridge_rev == SIS630B1))
1da177e4
LT
1258 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1259 (reg14h | 0x2200) & 0xBFFF);
1260 else
1261 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1262 (reg14h | 0x2000) & 0xBFFF);
1263 }
1da177e4
LT
1264}
1265
1266/**
1267 * sis900_timer - sis900 timer routine
1268 * @data: pointer to sis900 net device
1269 *
6aa20a22 1270 * On each timer ticks we check two things,
1da177e4
LT
1271 * link status (ON/OFF) and link mode (10/100/Full/Half)
1272 */
1273
1274static void sis900_timer(unsigned long data)
1275{
1276 struct net_device *net_dev = (struct net_device *)data;
8f15ea42 1277 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4 1278 struct mii_phy *mii_phy = sis_priv->mii;
f71e1309 1279 static const int next_tick = 5*HZ;
1da177e4
LT
1280 u16 status;
1281
1282 if (!sis_priv->autong_complete){
ef0cd87e 1283 int uninitialized_var(speed), duplex = 0;
1da177e4
LT
1284
1285 sis900_read_mode(net_dev, &speed, &duplex);
1286 if (duplex){
1287 sis900_set_mode(net_dev->base_addr, speed, duplex);
1288 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1289 netif_start_queue(net_dev);
1290 }
1291
1292 sis_priv->timer.expires = jiffies + HZ;
1293 add_timer(&sis_priv->timer);
1294 return;
1295 }
1296
1297 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1298 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1299
1300 /* Link OFF -> ON */
1301 if (!netif_carrier_ok(net_dev)) {
1302 LookForLink:
1303 /* Search for new PHY */
1304 status = sis900_default_phy(net_dev);
1305 mii_phy = sis_priv->mii;
1306
1307 if (status & MII_STAT_LINK){
1308 sis900_check_mode(net_dev, mii_phy);
1309 netif_carrier_on(net_dev);
1310 }
1311 } else {
1312 /* Link ON -> OFF */
1313 if (!(status & MII_STAT_LINK)){
1314 netif_carrier_off(net_dev);
1315 if(netif_msg_link(sis_priv))
1316 printk(KERN_INFO "%s: Media Link Off\n", net_dev->name);
1317
1318 /* Change mode issue */
6aa20a22 1319 if ((mii_phy->phy_id0 == 0x001D) &&
1da177e4
LT
1320 ((mii_phy->phy_id1 & 0xFFF0) == 0x8000))
1321 sis900_reset_phy(net_dev, sis_priv->cur_phy);
6aa20a22 1322
1da177e4 1323 sis630_set_eq(net_dev, sis_priv->chipset_rev);
6aa20a22 1324
1da177e4
LT
1325 goto LookForLink;
1326 }
1327 }
1328
1329 sis_priv->timer.expires = jiffies + next_tick;
1330 add_timer(&sis_priv->timer);
1331}
1332
1333/**
1334 * sis900_check_mode - check the media mode for sis900
1335 * @net_dev: the net device to be checked
1336 * @mii_phy: the mii phy
1337 *
1338 * Older driver gets the media mode from mii status output
1339 * register. Now we set our media capability and auto-negotiate
1340 * to get the upper bound of speed and duplex between two ends.
1341 * If the types of mii phy is HOME, it doesn't need to auto-negotiate
1342 * and autong_complete should be set to 1.
1343 */
1344
1345static void sis900_check_mode(struct net_device *net_dev, struct mii_phy *mii_phy)
1346{
8f15ea42 1347 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1348 long ioaddr = net_dev->base_addr;
1349 int speed, duplex;
1350
1351 if (mii_phy->phy_types == LAN) {
1352 outl(~EXD & inl(ioaddr + cfg), ioaddr + cfg);
1353 sis900_set_capability(net_dev , mii_phy);
1354 sis900_auto_negotiate(net_dev, sis_priv->cur_phy);
1355 } else {
1356 outl(EXD | inl(ioaddr + cfg), ioaddr + cfg);
1357 speed = HW_SPEED_HOME;
1358 duplex = FDX_CAPABLE_HALF_SELECTED;
1359 sis900_set_mode(ioaddr, speed, duplex);
1360 sis_priv->autong_complete = 1;
1361 }
1362}
1363
1364/**
1365 * sis900_set_mode - Set the media mode of mac register.
1366 * @ioaddr: the address of the device
1367 * @speed : the transmit speed to be determined
1368 * @duplex: the duplex mode to be determined
1369 *
1370 * Set the media mode of mac register txcfg/rxcfg according to
1371 * speed and duplex of phy. Bit EDB_MASTER_EN indicates the EDB
1372 * bus is used instead of PCI bus. When this bit is set 1, the
1373 * Max DMA Burst Size for TX/RX DMA should be no larger than 16
1374 * double words.
1375 */
1376
1377static void sis900_set_mode (long ioaddr, int speed, int duplex)
1378{
1379 u32 tx_flags = 0, rx_flags = 0;
1380
1381 if (inl(ioaddr + cfg) & EDB_MASTER_EN) {
1382 tx_flags = TxATP | (DMA_BURST_64 << TxMXDMA_shift) |
1383 (TX_FILL_THRESH << TxFILLT_shift);
1384 rx_flags = DMA_BURST_64 << RxMXDMA_shift;
1385 } else {
1386 tx_flags = TxATP | (DMA_BURST_512 << TxMXDMA_shift) |
1387 (TX_FILL_THRESH << TxFILLT_shift);
1388 rx_flags = DMA_BURST_512 << RxMXDMA_shift;
1389 }
1390
1391 if (speed == HW_SPEED_HOME || speed == HW_SPEED_10_MBPS) {
1392 rx_flags |= (RxDRNT_10 << RxDRNT_shift);
1393 tx_flags |= (TxDRNT_10 << TxDRNT_shift);
1394 } else {
1395 rx_flags |= (RxDRNT_100 << RxDRNT_shift);
1396 tx_flags |= (TxDRNT_100 << TxDRNT_shift);
1397 }
1398
1399 if (duplex == FDX_CAPABLE_FULL_SELECTED) {
1400 tx_flags |= (TxCSI | TxHBI);
1401 rx_flags |= RxATX;
1402 }
1403
d269a69f
DV
1404#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
1405 /* Can accept Jumbo packet */
1406 rx_flags |= RxAJAB;
1407#endif
1408
1da177e4
LT
1409 outl (tx_flags, ioaddr + txcfg);
1410 outl (rx_flags, ioaddr + rxcfg);
1411}
1412
1413/**
1414 * sis900_auto_negotiate - Set the Auto-Negotiation Enable/Reset bit.
1415 * @net_dev: the net device to read mode for
1416 * @phy_addr: mii phy address
1417 *
1418 * If the adapter is link-on, set the auto-negotiate enable/reset bit.
1419 * autong_complete should be set to 0 when starting auto-negotiation.
1420 * autong_complete should be set to 1 if we didn't start auto-negotiation.
1421 * sis900_timer will wait for link on again if autong_complete = 0.
1422 */
1423
1424static void sis900_auto_negotiate(struct net_device *net_dev, int phy_addr)
1425{
8f15ea42 1426 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1427 int i = 0;
1428 u32 status;
6aa20a22 1429
f3be9742 1430 for (i = 0; i < 2; i++)
1da177e4
LT
1431 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1432
1433 if (!(status & MII_STAT_LINK)){
1434 if(netif_msg_link(sis_priv))
1435 printk(KERN_INFO "%s: Media Link Off\n", net_dev->name);
1436 sis_priv->autong_complete = 1;
1437 netif_carrier_off(net_dev);
1438 return;
1439 }
1440
1441 /* (Re)start AutoNegotiate */
1442 mdio_write(net_dev, phy_addr, MII_CONTROL,
1443 MII_CNTL_AUTO | MII_CNTL_RST_AUTO);
1444 sis_priv->autong_complete = 0;
1445}
1446
1447
1448/**
1449 * sis900_read_mode - read media mode for sis900 internal phy
1450 * @net_dev: the net device to read mode for
1451 * @speed : the transmit speed to be determined
1452 * @duplex : the duplex mode to be determined
1453 *
1454 * The capability of remote end will be put in mii register autorec
1455 * after auto-negotiation. Use AND operation to get the upper bound
1456 * of speed and duplex between two ends.
1457 */
1458
1459static void sis900_read_mode(struct net_device *net_dev, int *speed, int *duplex)
1460{
8f15ea42 1461 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1462 struct mii_phy *phy = sis_priv->mii;
1463 int phy_addr = sis_priv->cur_phy;
1464 u32 status;
1465 u16 autoadv, autorec;
f3be9742 1466 int i;
1da177e4 1467
f3be9742 1468 for (i = 0; i < 2; i++)
1da177e4
LT
1469 status = mdio_read(net_dev, phy_addr, MII_STATUS);
1470
1471 if (!(status & MII_STAT_LINK))
1472 return;
1473
1474 /* AutoNegotiate completed */
1475 autoadv = mdio_read(net_dev, phy_addr, MII_ANADV);
1476 autorec = mdio_read(net_dev, phy_addr, MII_ANLPAR);
1477 status = autoadv & autorec;
6aa20a22 1478
1da177e4
LT
1479 *speed = HW_SPEED_10_MBPS;
1480 *duplex = FDX_CAPABLE_HALF_SELECTED;
1481
1482 if (status & (MII_NWAY_TX | MII_NWAY_TX_FDX))
1483 *speed = HW_SPEED_100_MBPS;
1484 if (status & ( MII_NWAY_TX_FDX | MII_NWAY_T_FDX))
1485 *duplex = FDX_CAPABLE_FULL_SELECTED;
6aa20a22 1486
1da177e4
LT
1487 sis_priv->autong_complete = 1;
1488
1489 /* Workaround for Realtek RTL8201 PHY issue */
1490 if ((phy->phy_id0 == 0x0000) && ((phy->phy_id1 & 0xFFF0) == 0x8200)) {
1491 if (mdio_read(net_dev, phy_addr, MII_CONTROL) & MII_CNTL_FDX)
1492 *duplex = FDX_CAPABLE_FULL_SELECTED;
1493 if (mdio_read(net_dev, phy_addr, 0x0019) & 0x01)
1494 *speed = HW_SPEED_100_MBPS;
1495 }
1496
1497 if(netif_msg_link(sis_priv))
2381a55c 1498 printk(KERN_INFO "%s: Media Link On %s %s-duplex\n",
1da177e4
LT
1499 net_dev->name,
1500 *speed == HW_SPEED_100_MBPS ?
1501 "100mbps" : "10mbps",
1502 *duplex == FDX_CAPABLE_FULL_SELECTED ?
1503 "full" : "half");
1504}
1505
1506/**
1507 * sis900_tx_timeout - sis900 transmit timeout routine
1508 * @net_dev: the net device to transmit
1509 *
1510 * print transmit timeout status
1511 * disable interrupts and do some tasks
1512 */
1513
1514static void sis900_tx_timeout(struct net_device *net_dev)
1515{
8f15ea42 1516 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1517 long ioaddr = net_dev->base_addr;
1518 unsigned long flags;
1519 int i;
1520
1521 if(netif_msg_tx_err(sis_priv))
2381a55c 1522 printk(KERN_INFO "%s: Transmit timeout, status %8.8x %8.8x\n",
1da177e4
LT
1523 net_dev->name, inl(ioaddr + cr), inl(ioaddr + isr));
1524
1525 /* Disable interrupts by clearing the interrupt mask. */
1526 outl(0x0000, ioaddr + imr);
1527
1528 /* use spinlock to prevent interrupt handler accessing buffer ring */
1529 spin_lock_irqsave(&sis_priv->lock, flags);
1530
1531 /* discard unsent packets */
1532 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1533 for (i = 0; i < NUM_TX_DESC; i++) {
1534 struct sk_buff *skb = sis_priv->tx_skbuff[i];
1535
1536 if (skb) {
6aa20a22 1537 pci_unmap_single(sis_priv->pci_dev,
1da177e4
LT
1538 sis_priv->tx_ring[i].bufptr, skb->len,
1539 PCI_DMA_TODEVICE);
1540 dev_kfree_skb_irq(skb);
1541 sis_priv->tx_skbuff[i] = NULL;
1542 sis_priv->tx_ring[i].cmdsts = 0;
1543 sis_priv->tx_ring[i].bufptr = 0;
09f75cd7 1544 net_dev->stats.tx_dropped++;
1da177e4
LT
1545 }
1546 }
1547 sis_priv->tx_full = 0;
1548 netif_wake_queue(net_dev);
1549
1550 spin_unlock_irqrestore(&sis_priv->lock, flags);
1551
1ae5dc34 1552 net_dev->trans_start = jiffies; /* prevent tx timeout */
1da177e4
LT
1553
1554 /* load Transmit Descriptor Register */
1555 outl(sis_priv->tx_ring_dma, ioaddr + txdp);
1556
1557 /* Enable all known interrupts by setting the interrupt mask. */
1558 outl((RxSOVR|RxORN|RxERR|RxOK|TxURN|TxERR|TxIDLE), ioaddr + imr);
1da177e4
LT
1559}
1560
1561/**
1562 * sis900_start_xmit - sis900 start transmit routine
1563 * @skb: socket buffer pointer to put the data being transmitted
1564 * @net_dev: the net device to transmit with
1565 *
6aa20a22 1566 * Set the transmit buffer descriptor,
1da177e4
LT
1567 * and write TxENA to enable transmit state machine.
1568 * tell upper layer if the buffer is full
1569 */
1570
61357325 1571static netdev_tx_t
1da177e4
LT
1572sis900_start_xmit(struct sk_buff *skb, struct net_device *net_dev)
1573{
8f15ea42 1574 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1575 long ioaddr = net_dev->base_addr;
1576 unsigned int entry;
1577 unsigned long flags;
1578 unsigned int index_cur_tx, index_dirty_tx;
1579 unsigned int count_dirty_tx;
1580
1581 /* Don't transmit data before the complete of auto-negotiation */
1582 if(!sis_priv->autong_complete){
1583 netif_stop_queue(net_dev);
5b548140 1584 return NETDEV_TX_BUSY;
1da177e4
LT
1585 }
1586
1587 spin_lock_irqsave(&sis_priv->lock, flags);
1588
1589 /* Calculate the next Tx descriptor entry. */
1590 entry = sis_priv->cur_tx % NUM_TX_DESC;
1591 sis_priv->tx_skbuff[entry] = skb;
1592
1593 /* set the transmit buffer descriptor and enable Transmit State Machine */
1594 sis_priv->tx_ring[entry].bufptr = pci_map_single(sis_priv->pci_dev,
1595 skb->data, skb->len, PCI_DMA_TODEVICE);
1596 sis_priv->tx_ring[entry].cmdsts = (OWN | skb->len);
1597 outl(TxENA | inl(ioaddr + cr), ioaddr + cr);
1598
1599 sis_priv->cur_tx ++;
1600 index_cur_tx = sis_priv->cur_tx;
1601 index_dirty_tx = sis_priv->dirty_tx;
1602
1603 for (count_dirty_tx = 0; index_cur_tx != index_dirty_tx; index_dirty_tx++)
1604 count_dirty_tx ++;
1605
1606 if (index_cur_tx == index_dirty_tx) {
1607 /* dirty_tx is met in the cycle of cur_tx, buffer full */
1608 sis_priv->tx_full = 1;
1609 netif_stop_queue(net_dev);
6aa20a22 1610 } else if (count_dirty_tx < NUM_TX_DESC) {
1da177e4
LT
1611 /* Typical path, tell upper layer that more transmission is possible */
1612 netif_start_queue(net_dev);
1613 } else {
1614 /* buffer full, tell upper layer no more transmission */
1615 sis_priv->tx_full = 1;
1616 netif_stop_queue(net_dev);
1617 }
1618
1619 spin_unlock_irqrestore(&sis_priv->lock, flags);
1620
1da177e4
LT
1621 if (netif_msg_tx_queued(sis_priv))
1622 printk(KERN_DEBUG "%s: Queued Tx packet at %p size %d "
1623 "to slot %d.\n",
1624 net_dev->name, skb->data, (int)skb->len, entry);
1625
6ed10654 1626 return NETDEV_TX_OK;
1da177e4
LT
1627}
1628
1629/**
1630 * sis900_interrupt - sis900 interrupt handler
1631 * @irq: the irq number
1632 * @dev_instance: the client data object
1da177e4 1633 *
6aa20a22 1634 * The interrupt handler does all of the Rx thread work,
1da177e4
LT
1635 * and cleans up after the Tx thread
1636 */
1637
7d12e780 1638static irqreturn_t sis900_interrupt(int irq, void *dev_instance)
1da177e4
LT
1639{
1640 struct net_device *net_dev = dev_instance;
8f15ea42 1641 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1642 int boguscnt = max_interrupt_work;
1643 long ioaddr = net_dev->base_addr;
1644 u32 status;
1645 unsigned int handled = 0;
1646
1647 spin_lock (&sis_priv->lock);
1648
1649 do {
1650 status = inl(ioaddr + isr);
1651
1652 if ((status & (HIBERR|TxURN|TxERR|TxIDLE|RxORN|RxERR|RxOK)) == 0)
1653 /* nothing intresting happened */
1654 break;
1655 handled = 1;
1656
1657 /* why dow't we break after Tx/Rx case ?? keyword: full-duplex */
1658 if (status & (RxORN | RxERR | RxOK))
1659 /* Rx interrupt */
1660 sis900_rx(net_dev);
1661
1662 if (status & (TxURN | TxERR | TxIDLE))
1663 /* Tx interrupt */
1664 sis900_finish_xmit(net_dev);
1665
1666 /* something strange happened !!! */
1667 if (status & HIBERR) {
1668 if(netif_msg_intr(sis_priv))
2450022a 1669 printk(KERN_INFO "%s: Abnormal interrupt, "
1da177e4
LT
1670 "status %#8.8x.\n", net_dev->name, status);
1671 break;
1672 }
1673 if (--boguscnt < 0) {
1674 if(netif_msg_intr(sis_priv))
1675 printk(KERN_INFO "%s: Too much work at interrupt, "
1676 "interrupt status = %#8.8x.\n",
1677 net_dev->name, status);
1678 break;
1679 }
1680 } while (1);
1681
1682 if(netif_msg_intr(sis_priv))
1683 printk(KERN_DEBUG "%s: exiting interrupt, "
1684 "interrupt status = 0x%#8.8x.\n",
1685 net_dev->name, inl(ioaddr + isr));
6aa20a22 1686
1da177e4
LT
1687 spin_unlock (&sis_priv->lock);
1688 return IRQ_RETVAL(handled);
1689}
1690
1691/**
1692 * sis900_rx - sis900 receive routine
1693 * @net_dev: the net device which receives data
1694 *
6aa20a22 1695 * Process receive interrupt events,
1da177e4 1696 * put buffer to higher layer and refill buffer pool
0b28002f 1697 * Note: This function is called by interrupt handler,
1da177e4
LT
1698 * don't do "too much" work here
1699 */
1700
1701static int sis900_rx(struct net_device *net_dev)
1702{
8f15ea42 1703 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1704 long ioaddr = net_dev->base_addr;
1705 unsigned int entry = sis_priv->cur_rx % NUM_RX_DESC;
1706 u32 rx_status = sis_priv->rx_ring[entry].cmdsts;
7380a78a 1707 int rx_work_limit;
1da177e4
LT
1708
1709 if (netif_msg_rx_status(sis_priv))
1710 printk(KERN_DEBUG "sis900_rx, cur_rx:%4.4d, dirty_rx:%4.4d "
1711 "status:0x%8.8x\n",
1712 sis_priv->cur_rx, sis_priv->dirty_rx, rx_status);
7380a78a 1713 rx_work_limit = sis_priv->dirty_rx + NUM_RX_DESC - sis_priv->cur_rx;
1da177e4
LT
1714
1715 while (rx_status & OWN) {
1716 unsigned int rx_size;
d269a69f 1717 unsigned int data_size;
1da177e4 1718
7380a78a
VA
1719 if (--rx_work_limit < 0)
1720 break;
1721
d269a69f
DV
1722 data_size = rx_status & DSIZE;
1723 rx_size = data_size - CRC_SIZE;
1724
1725#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
25985edc 1726 /* ``TOOLONG'' flag means jumbo packet received. */
d269a69f
DV
1727 if ((rx_status & TOOLONG) && data_size <= MAX_FRAME_SIZE)
1728 rx_status &= (~ ((unsigned int)TOOLONG));
1729#endif
1da177e4
LT
1730
1731 if (rx_status & (ABORT|OVERRUN|TOOLONG|RUNT|RXISERR|CRCERR|FAERR)) {
1732 /* corrupted packet received */
1733 if (netif_msg_rx_err(sis_priv))
1734 printk(KERN_DEBUG "%s: Corrupted packet "
d269a69f
DV
1735 "received, buffer status = 0x%8.8x/%d.\n",
1736 net_dev->name, rx_status, data_size);
09f75cd7 1737 net_dev->stats.rx_errors++;
1da177e4 1738 if (rx_status & OVERRUN)
09f75cd7 1739 net_dev->stats.rx_over_errors++;
1da177e4 1740 if (rx_status & (TOOLONG|RUNT))
09f75cd7 1741 net_dev->stats.rx_length_errors++;
1da177e4 1742 if (rx_status & (RXISERR | FAERR))
09f75cd7 1743 net_dev->stats.rx_frame_errors++;
6aa20a22 1744 if (rx_status & CRCERR)
09f75cd7 1745 net_dev->stats.rx_crc_errors++;
1da177e4
LT
1746 /* reset buffer descriptor state */
1747 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1748 } else {
1749 struct sk_buff * skb;
dc5a1449 1750 struct sk_buff * rx_skb;
1da177e4 1751
b748d9e3
NH
1752 pci_unmap_single(sis_priv->pci_dev,
1753 sis_priv->rx_ring[entry].bufptr, RX_BUF_SIZE,
1754 PCI_DMA_FROMDEVICE);
1755
af901ca1 1756 /* refill the Rx buffer, what if there is not enough
b748d9e3
NH
1757 * memory for new socket buffer ?? */
1758 if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
1759 /*
1760 * Not enough memory to refill the buffer
1761 * so we need to recycle the old one so
1762 * as to avoid creating a memory hole
1763 * in the rx ring
1764 */
1765 skb = sis_priv->rx_skbuff[entry];
09f75cd7 1766 net_dev->stats.rx_dropped++;
b748d9e3 1767 goto refill_rx_ring;
7d2e3cb7 1768 }
b748d9e3 1769
1da177e4 1770 /* This situation should never happen, but due to
af901ca1 1771 some unknown bugs, it is possible that
1da177e4
LT
1772 we are working on NULL sk_buff :-( */
1773 if (sis_priv->rx_skbuff[entry] == NULL) {
1774 if (netif_msg_rx_err(sis_priv))
6aa20a22 1775 printk(KERN_WARNING "%s: NULL pointer "
7380a78a
VA
1776 "encountered in Rx ring\n"
1777 "cur_rx:%4.4d, dirty_rx:%4.4d\n",
1778 net_dev->name, sis_priv->cur_rx,
1779 sis_priv->dirty_rx);
bf1f9ae0 1780 dev_kfree_skb(skb);
1da177e4
LT
1781 break;
1782 }
1783
1da177e4 1784 /* give the socket buffer to upper layers */
dc5a1449
NH
1785 rx_skb = sis_priv->rx_skbuff[entry];
1786 skb_put(rx_skb, rx_size);
1787 rx_skb->protocol = eth_type_trans(rx_skb, net_dev);
1788 netif_rx(rx_skb);
1da177e4
LT
1789
1790 /* some network statistics */
1791 if ((rx_status & BCAST) == MCAST)
09f75cd7 1792 net_dev->stats.multicast++;
09f75cd7
JG
1793 net_dev->stats.rx_bytes += rx_size;
1794 net_dev->stats.rx_packets++;
b748d9e3
NH
1795 sis_priv->dirty_rx++;
1796refill_rx_ring:
1da177e4
LT
1797 sis_priv->rx_skbuff[entry] = skb;
1798 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
6aa20a22
JG
1799 sis_priv->rx_ring[entry].bufptr =
1800 pci_map_single(sis_priv->pci_dev, skb->data,
1da177e4 1801 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1da177e4
LT
1802 }
1803 sis_priv->cur_rx++;
1804 entry = sis_priv->cur_rx % NUM_RX_DESC;
1805 rx_status = sis_priv->rx_ring[entry].cmdsts;
1806 } // while
1807
1808 /* refill the Rx buffer, what if the rate of refilling is slower
1809 * than consuming ?? */
7380a78a 1810 for (; sis_priv->cur_rx != sis_priv->dirty_rx; sis_priv->dirty_rx++) {
1da177e4
LT
1811 struct sk_buff *skb;
1812
1813 entry = sis_priv->dirty_rx % NUM_RX_DESC;
1814
1815 if (sis_priv->rx_skbuff[entry] == NULL) {
1816 if ((skb = dev_alloc_skb(RX_BUF_SIZE)) == NULL) {
1817 /* not enough memory for skbuff, this makes a
1818 * "hole" on the buffer ring, it is not clear
1819 * how the hardware will react to this kind
1820 * of degenerated buffer */
1821 if (netif_msg_rx_err(sis_priv))
2450022a 1822 printk(KERN_INFO "%s: Memory squeeze, "
1da177e4
LT
1823 "deferring packet.\n",
1824 net_dev->name);
09f75cd7 1825 net_dev->stats.rx_dropped++;
1da177e4
LT
1826 break;
1827 }
1da177e4
LT
1828 sis_priv->rx_skbuff[entry] = skb;
1829 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1830 sis_priv->rx_ring[entry].bufptr =
689be439 1831 pci_map_single(sis_priv->pci_dev, skb->data,
1da177e4
LT
1832 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1833 }
1834 }
1835 /* re-enable the potentially idle receive state matchine */
1836 outl(RxENA | inl(ioaddr + cr), ioaddr + cr );
1837
1838 return 0;
1839}
1840
1841/**
1842 * sis900_finish_xmit - finish up transmission of packets
1843 * @net_dev: the net device to be transmitted on
1844 *
6aa20a22 1845 * Check for error condition and free socket buffer etc
1da177e4 1846 * schedule for more transmission as needed
0b28002f 1847 * Note: This function is called by interrupt handler,
1da177e4
LT
1848 * don't do "too much" work here
1849 */
1850
1851static void sis900_finish_xmit (struct net_device *net_dev)
1852{
8f15ea42 1853 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1854
1855 for (; sis_priv->dirty_tx != sis_priv->cur_tx; sis_priv->dirty_tx++) {
1856 struct sk_buff *skb;
1857 unsigned int entry;
1858 u32 tx_status;
1859
1860 entry = sis_priv->dirty_tx % NUM_TX_DESC;
1861 tx_status = sis_priv->tx_ring[entry].cmdsts;
1862
1863 if (tx_status & OWN) {
1864 /* The packet is not transmitted yet (owned by hardware) !
1865 * Note: the interrupt is generated only when Tx Machine
1866 * is idle, so this is an almost impossible case */
1867 break;
1868 }
1869
1870 if (tx_status & (ABORT | UNDERRUN | OWCOLL)) {
1871 /* packet unsuccessfully transmitted */
1872 if (netif_msg_tx_err(sis_priv))
1873 printk(KERN_DEBUG "%s: Transmit "
1874 "error, Tx status %8.8x.\n",
1875 net_dev->name, tx_status);
09f75cd7 1876 net_dev->stats.tx_errors++;
1da177e4 1877 if (tx_status & UNDERRUN)
09f75cd7 1878 net_dev->stats.tx_fifo_errors++;
1da177e4 1879 if (tx_status & ABORT)
09f75cd7 1880 net_dev->stats.tx_aborted_errors++;
1da177e4 1881 if (tx_status & NOCARRIER)
09f75cd7 1882 net_dev->stats.tx_carrier_errors++;
1da177e4 1883 if (tx_status & OWCOLL)
09f75cd7 1884 net_dev->stats.tx_window_errors++;
1da177e4
LT
1885 } else {
1886 /* packet successfully transmitted */
09f75cd7
JG
1887 net_dev->stats.collisions += (tx_status & COLCNT) >> 16;
1888 net_dev->stats.tx_bytes += tx_status & DSIZE;
1889 net_dev->stats.tx_packets++;
1da177e4
LT
1890 }
1891 /* Free the original skb. */
1892 skb = sis_priv->tx_skbuff[entry];
6aa20a22 1893 pci_unmap_single(sis_priv->pci_dev,
1da177e4
LT
1894 sis_priv->tx_ring[entry].bufptr, skb->len,
1895 PCI_DMA_TODEVICE);
1896 dev_kfree_skb_irq(skb);
1897 sis_priv->tx_skbuff[entry] = NULL;
1898 sis_priv->tx_ring[entry].bufptr = 0;
1899 sis_priv->tx_ring[entry].cmdsts = 0;
1900 }
1901
1902 if (sis_priv->tx_full && netif_queue_stopped(net_dev) &&
1903 sis_priv->cur_tx - sis_priv->dirty_tx < NUM_TX_DESC - 4) {
1904 /* The ring is no longer full, clear tx_full and schedule
1905 * more transmission by netif_wake_queue(net_dev) */
1906 sis_priv->tx_full = 0;
1907 netif_wake_queue (net_dev);
1908 }
1909}
1910
1911/**
6aa20a22 1912 * sis900_close - close sis900 device
1da177e4
LT
1913 * @net_dev: the net device to be closed
1914 *
6aa20a22 1915 * Disable interrupts, stop the Tx and Rx Status Machine
1da177e4
LT
1916 * free Tx and RX socket buffer
1917 */
1918
1919static int sis900_close(struct net_device *net_dev)
1920{
1921 long ioaddr = net_dev->base_addr;
8f15ea42 1922 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1923 struct sk_buff *skb;
1924 int i;
1925
1926 netif_stop_queue(net_dev);
1927
1928 /* Disable interrupts by clearing the interrupt mask. */
1929 outl(0x0000, ioaddr + imr);
1930 outl(0x0000, ioaddr + ier);
1931
1932 /* Stop the chip's Tx and Rx Status Machine */
1933 outl(RxDIS | TxDIS | inl(ioaddr + cr), ioaddr + cr);
1934
1935 del_timer(&sis_priv->timer);
1936
1937 free_irq(net_dev->irq, net_dev);
1938
1939 /* Free Tx and RX skbuff */
1940 for (i = 0; i < NUM_RX_DESC; i++) {
1941 skb = sis_priv->rx_skbuff[i];
1942 if (skb) {
6aa20a22 1943 pci_unmap_single(sis_priv->pci_dev,
1da177e4
LT
1944 sis_priv->rx_ring[i].bufptr,
1945 RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1946 dev_kfree_skb(skb);
1947 sis_priv->rx_skbuff[i] = NULL;
1948 }
1949 }
1950 for (i = 0; i < NUM_TX_DESC; i++) {
1951 skb = sis_priv->tx_skbuff[i];
1952 if (skb) {
6aa20a22 1953 pci_unmap_single(sis_priv->pci_dev,
1da177e4
LT
1954 sis_priv->tx_ring[i].bufptr, skb->len,
1955 PCI_DMA_TODEVICE);
1956 dev_kfree_skb(skb);
1957 sis_priv->tx_skbuff[i] = NULL;
1958 }
1959 }
1960
1961 /* Green! Put the chip in low-power mode. */
1962
1963 return 0;
1964}
1965
1966/**
1967 * sis900_get_drvinfo - Return information about driver
1968 * @net_dev: the net device to probe
1969 * @info: container for info returned
1970 *
1971 * Process ethtool command such as "ehtool -i" to show information
1972 */
6aa20a22 1973
1da177e4
LT
1974static void sis900_get_drvinfo(struct net_device *net_dev,
1975 struct ethtool_drvinfo *info)
1976{
8f15ea42 1977 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1978
1979 strcpy (info->driver, SIS900_MODULE_NAME);
1980 strcpy (info->version, SIS900_DRV_VERSION);
1981 strcpy (info->bus_info, pci_name(sis_priv->pci_dev));
1982}
1983
1984static u32 sis900_get_msglevel(struct net_device *net_dev)
1985{
8f15ea42 1986 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1987 return sis_priv->msg_enable;
1988}
6aa20a22 1989
1da177e4
LT
1990static void sis900_set_msglevel(struct net_device *net_dev, u32 value)
1991{
8f15ea42 1992 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
1993 sis_priv->msg_enable = value;
1994}
1995
da369b01
DV
1996static u32 sis900_get_link(struct net_device *net_dev)
1997{
8f15ea42 1998 struct sis900_private *sis_priv = netdev_priv(net_dev);
da369b01
DV
1999 return mii_link_ok(&sis_priv->mii_info);
2000}
2001
2002static int sis900_get_settings(struct net_device *net_dev,
2003 struct ethtool_cmd *cmd)
2004{
8f15ea42 2005 struct sis900_private *sis_priv = netdev_priv(net_dev);
da369b01
DV
2006 spin_lock_irq(&sis_priv->lock);
2007 mii_ethtool_gset(&sis_priv->mii_info, cmd);
2008 spin_unlock_irq(&sis_priv->lock);
2009 return 0;
2010}
2011
2012static int sis900_set_settings(struct net_device *net_dev,
2013 struct ethtool_cmd *cmd)
2014{
8f15ea42 2015 struct sis900_private *sis_priv = netdev_priv(net_dev);
da369b01
DV
2016 int rt;
2017 spin_lock_irq(&sis_priv->lock);
2018 rt = mii_ethtool_sset(&sis_priv->mii_info, cmd);
2019 spin_unlock_irq(&sis_priv->lock);
2020 return rt;
2021}
2022
2023static int sis900_nway_reset(struct net_device *net_dev)
2024{
8f15ea42 2025 struct sis900_private *sis_priv = netdev_priv(net_dev);
da369b01
DV
2026 return mii_nway_restart(&sis_priv->mii_info);
2027}
2028
ea37ccea
DV
2029/**
2030 * sis900_set_wol - Set up Wake on Lan registers
2031 * @net_dev: the net device to probe
2032 * @wol: container for info passed to the driver
2033 *
2034 * Process ethtool command "wol" to setup wake on lan features.
2035 * SiS900 supports sending WoL events if a correct packet is received,
2036 * but there is no simple way to filter them to only a subset (broadcast,
2037 * multicast, unicast or arp).
2038 */
6aa20a22 2039
ea37ccea
DV
2040static int sis900_set_wol(struct net_device *net_dev, struct ethtool_wolinfo *wol)
2041{
8f15ea42 2042 struct sis900_private *sis_priv = netdev_priv(net_dev);
ea37ccea
DV
2043 long pmctrl_addr = net_dev->base_addr + pmctrl;
2044 u32 cfgpmcsr = 0, pmctrl_bits = 0;
2045
2046 if (wol->wolopts == 0) {
2047 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
7bef4b39 2048 cfgpmcsr &= ~PME_EN;
ea37ccea
DV
2049 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2050 outl(pmctrl_bits, pmctrl_addr);
2051 if (netif_msg_wol(sis_priv))
2052 printk(KERN_DEBUG "%s: Wake on LAN disabled\n", net_dev->name);
2053 return 0;
2054 }
2055
2056 if (wol->wolopts & (WAKE_MAGICSECURE | WAKE_UCAST | WAKE_MCAST
2057 | WAKE_BCAST | WAKE_ARP))
2058 return -EINVAL;
2059
2060 if (wol->wolopts & WAKE_MAGIC)
2061 pmctrl_bits |= MAGICPKT;
2062 if (wol->wolopts & WAKE_PHY)
2063 pmctrl_bits |= LINKON;
6aa20a22 2064
ea37ccea
DV
2065 outl(pmctrl_bits, pmctrl_addr);
2066
2067 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
2068 cfgpmcsr |= PME_EN;
2069 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2070 if (netif_msg_wol(sis_priv))
2071 printk(KERN_DEBUG "%s: Wake on LAN enabled\n", net_dev->name);
2072
2073 return 0;
2074}
2075
2076static void sis900_get_wol(struct net_device *net_dev, struct ethtool_wolinfo *wol)
2077{
2078 long pmctrl_addr = net_dev->base_addr + pmctrl;
2079 u32 pmctrl_bits;
2080
2081 pmctrl_bits = inl(pmctrl_addr);
2082 if (pmctrl_bits & MAGICPKT)
2083 wol->wolopts |= WAKE_MAGIC;
2084 if (pmctrl_bits & LINKON)
2085 wol->wolopts |= WAKE_PHY;
2086
2087 wol->supported = (WAKE_PHY | WAKE_MAGIC);
2088}
2089
7282d491 2090static const struct ethtool_ops sis900_ethtool_ops = {
1da177e4
LT
2091 .get_drvinfo = sis900_get_drvinfo,
2092 .get_msglevel = sis900_get_msglevel,
2093 .set_msglevel = sis900_set_msglevel,
da369b01
DV
2094 .get_link = sis900_get_link,
2095 .get_settings = sis900_get_settings,
2096 .set_settings = sis900_set_settings,
2097 .nway_reset = sis900_nway_reset,
ea37ccea
DV
2098 .get_wol = sis900_get_wol,
2099 .set_wol = sis900_set_wol
1da177e4
LT
2100};
2101
2102/**
6aa20a22 2103 * mii_ioctl - process MII i/o control command
1da177e4
LT
2104 * @net_dev: the net device to command for
2105 * @rq: parameter for command
2106 * @cmd: the i/o command
2107 *
2108 * Process MII command like read/write MII register
2109 */
2110
2111static int mii_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
2112{
8f15ea42 2113 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
2114 struct mii_ioctl_data *data = if_mii(rq);
2115
2116 switch(cmd) {
2117 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2118 data->phy_id = sis_priv->mii->phy_addr;
2119 /* Fall Through */
2120
2121 case SIOCGMIIREG: /* Read MII PHY register. */
2122 data->val_out = mdio_read(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f);
2123 return 0;
2124
2125 case SIOCSMIIREG: /* Write MII PHY register. */
1da177e4
LT
2126 mdio_write(net_dev, data->phy_id & 0x1f, data->reg_num & 0x1f, data->val_in);
2127 return 0;
2128 default:
2129 return -EOPNOTSUPP;
2130 }
2131}
2132
1da177e4 2133/**
6aa20a22 2134 * sis900_set_config - Set media type by net_device.set_config
1da177e4
LT
2135 * @dev: the net device for media type change
2136 * @map: ifmap passed by ifconfig
2137 *
2138 * Set media type to 10baseT, 100baseT or 0(for auto) by ifconfig
2139 * we support only port changes. All other runtime configuration
2140 * changes will be ignored
2141 */
2142
2143static int sis900_set_config(struct net_device *dev, struct ifmap *map)
6aa20a22 2144{
8f15ea42 2145 struct sis900_private *sis_priv = netdev_priv(dev);
1da177e4 2146 struct mii_phy *mii_phy = sis_priv->mii;
6aa20a22 2147
1da177e4
LT
2148 u16 status;
2149
2150 if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
2151 /* we switch on the ifmap->port field. I couldn't find anything
2152 * like a definition or standard for the values of that field.
2153 * I think the meaning of those values is device specific. But
2154 * since I would like to change the media type via the ifconfig
6aa20a22 2155 * command I use the definition from linux/netdevice.h
1da177e4
LT
2156 * (which seems to be different from the ifport(pcmcia) definition) */
2157 switch(map->port){
6aa20a22 2158 case IF_PORT_UNKNOWN: /* use auto here */
1da177e4
LT
2159 dev->if_port = map->port;
2160 /* we are going to change the media type, so the Link
2161 * will be temporary down and we need to reflect that
2162 * here. When the Link comes up again, it will be
2163 * sensed by the sis_timer procedure, which also does
2164 * all the rest for us */
2165 netif_carrier_off(dev);
6aa20a22 2166
1da177e4
LT
2167 /* read current state */
2168 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
6aa20a22 2169
1da177e4
LT
2170 /* enable auto negotiation and reset the negotioation
2171 * (I don't really know what the auto negatiotiation
2172 * reset really means, but it sounds for me right to
2173 * do one here) */
2174 mdio_write(dev, mii_phy->phy_addr,
2175 MII_CONTROL, status | MII_CNTL_AUTO | MII_CNTL_RST_AUTO);
2176
2177 break;
6aa20a22
JG
2178
2179 case IF_PORT_10BASET: /* 10BaseT */
1da177e4 2180 dev->if_port = map->port;
6aa20a22 2181
1da177e4
LT
2182 /* we are going to change the media type, so the Link
2183 * will be temporary down and we need to reflect that
2184 * here. When the Link comes up again, it will be
2185 * sensed by the sis_timer procedure, which also does
2186 * all the rest for us */
2187 netif_carrier_off(dev);
6aa20a22 2188
1da177e4
LT
2189 /* set Speed to 10Mbps */
2190 /* read current state */
2191 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
6aa20a22 2192
1da177e4
LT
2193 /* disable auto negotiation and force 10MBit mode*/
2194 mdio_write(dev, mii_phy->phy_addr,
2195 MII_CONTROL, status & ~(MII_CNTL_SPEED |
2196 MII_CNTL_AUTO));
2197 break;
6aa20a22 2198
1da177e4 2199 case IF_PORT_100BASET: /* 100BaseT */
6aa20a22 2200 case IF_PORT_100BASETX: /* 100BaseTx */
1da177e4 2201 dev->if_port = map->port;
6aa20a22 2202
1da177e4
LT
2203 /* we are going to change the media type, so the Link
2204 * will be temporary down and we need to reflect that
2205 * here. When the Link comes up again, it will be
2206 * sensed by the sis_timer procedure, which also does
2207 * all the rest for us */
2208 netif_carrier_off(dev);
6aa20a22 2209
1da177e4
LT
2210 /* set Speed to 100Mbps */
2211 /* disable auto negotiation and enable 100MBit Mode */
2212 status = mdio_read(dev, mii_phy->phy_addr, MII_CONTROL);
2213 mdio_write(dev, mii_phy->phy_addr,
2214 MII_CONTROL, (status & ~MII_CNTL_SPEED) |
2215 MII_CNTL_SPEED);
6aa20a22 2216
1da177e4 2217 break;
6aa20a22 2218
1da177e4
LT
2219 case IF_PORT_10BASE2: /* 10Base2 */
2220 case IF_PORT_AUI: /* AUI */
2221 case IF_PORT_100BASEFX: /* 100BaseFx */
2222 /* These Modes are not supported (are they?)*/
2223 return -EOPNOTSUPP;
2224 break;
6aa20a22 2225
1da177e4
LT
2226 default:
2227 return -EINVAL;
2228 }
2229 }
2230 return 0;
2231}
2232
2233/**
6aa20a22 2234 * sis900_mcast_bitnr - compute hashtable index
1da177e4
LT
2235 * @addr: multicast address
2236 * @revision: revision id of chip
2237 *
2238 * SiS 900 uses the most sigificant 7 bits to index a 128 bits multicast
2239 * hash table, which makes this function a little bit different from other drivers
2240 * SiS 900 B0 & 635 M/B uses the most significat 8 bits to index 256 bits
6aa20a22 2241 * multicast hash table.
1da177e4
LT
2242 */
2243
2244static inline u16 sis900_mcast_bitnr(u8 *addr, u8 revision)
2245{
2246
2247 u32 crc = ether_crc(6, addr);
2248
2249 /* leave 8 or 7 most siginifant bits */
2250 if ((revision >= SIS635A_900_REV) || (revision == SIS900B_900_REV))
807540ba 2251 return (int)(crc >> 24);
1da177e4 2252 else
807540ba 2253 return (int)(crc >> 25);
1da177e4
LT
2254}
2255
2256/**
6aa20a22 2257 * set_rx_mode - Set SiS900 receive mode
1da177e4
LT
2258 * @net_dev: the net device to be set
2259 *
2260 * Set SiS900 receive mode for promiscuous, multicast, or broadcast mode.
2261 * And set the appropriate multicast filter.
2262 * Multicast hash table changes from 128 to 256 bits for 635M/B & 900B0.
2263 */
2264
2265static void set_rx_mode(struct net_device *net_dev)
2266{
2267 long ioaddr = net_dev->base_addr;
8f15ea42 2268 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
2269 u16 mc_filter[16] = {0}; /* 256/128 bits multicast hash table */
2270 int i, table_entries;
2271 u32 rx_mode;
2272
7f927fcc 2273 /* 635 Hash Table entries = 256(2^16) */
1da177e4
LT
2274 if((sis_priv->chipset_rev >= SIS635A_900_REV) ||
2275 (sis_priv->chipset_rev == SIS900B_900_REV))
2276 table_entries = 16;
2277 else
2278 table_entries = 8;
2279
2280 if (net_dev->flags & IFF_PROMISC) {
2281 /* Accept any kinds of packets */
2282 rx_mode = RFPromiscuous;
2283 for (i = 0; i < table_entries; i++)
2284 mc_filter[i] = 0xffff;
4cd24eaf 2285 } else if ((netdev_mc_count(net_dev) > multicast_filter_limit) ||
1da177e4
LT
2286 (net_dev->flags & IFF_ALLMULTI)) {
2287 /* too many multicast addresses or accept all multicast packet */
2288 rx_mode = RFAAB | RFAAM;
2289 for (i = 0; i < table_entries; i++)
2290 mc_filter[i] = 0xffff;
2291 } else {
2292 /* Accept Broadcast packet, destination address matchs our
2293 * MAC address, use Receive Filter to reject unwanted MCAST
2294 * packets */
22bedad3 2295 struct netdev_hw_addr *ha;
1da177e4 2296 rx_mode = RFAAB;
5508590c 2297
22bedad3
JP
2298 netdev_for_each_mc_addr(ha, net_dev) {
2299 unsigned int bit_nr;
2300
2301 bit_nr = sis900_mcast_bitnr(ha->addr,
2302 sis_priv->chipset_rev);
1da177e4
LT
2303 mc_filter[bit_nr >> 4] |= (1 << (bit_nr & 0xf));
2304 }
2305 }
2306
2307 /* update Multicast Hash Table in Receive Filter */
2308 for (i = 0; i < table_entries; i++) {
2309 /* why plus 0x04 ??, That makes the correct value for hash table. */
2310 outl((u32)(0x00000004+i) << RFADDR_shift, ioaddr + rfcr);
2311 outl(mc_filter[i], ioaddr + rfdr);
2312 }
2313
2314 outl(RFEN | rx_mode, ioaddr + rfcr);
2315
2316 /* sis900 is capable of looping back packets at MAC level for
2317 * debugging purpose */
2318 if (net_dev->flags & IFF_LOOPBACK) {
2319 u32 cr_saved;
2320 /* We must disable Tx/Rx before setting loopback mode */
2321 cr_saved = inl(ioaddr + cr);
2322 outl(cr_saved | TxDIS | RxDIS, ioaddr + cr);
2323 /* enable loopback */
2324 outl(inl(ioaddr + txcfg) | TxMLB, ioaddr + txcfg);
2325 outl(inl(ioaddr + rxcfg) | RxATX, ioaddr + rxcfg);
2326 /* restore cr */
2327 outl(cr_saved, ioaddr + cr);
2328 }
1da177e4
LT
2329}
2330
2331/**
6aa20a22 2332 * sis900_reset - Reset sis900 MAC
1da177e4
LT
2333 * @net_dev: the net device to reset
2334 *
2335 * reset sis900 MAC and wait until finished
2336 * reset through command register
2337 * change backoff algorithm for 900B0 & 635 M/B
2338 */
2339
2340static void sis900_reset(struct net_device *net_dev)
2341{
8f15ea42 2342 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
2343 long ioaddr = net_dev->base_addr;
2344 int i = 0;
2345 u32 status = TxRCMP | RxRCMP;
2346
2347 outl(0, ioaddr + ier);
2348 outl(0, ioaddr + imr);
2349 outl(0, ioaddr + rfcr);
2350
2351 outl(RxRESET | TxRESET | RESET | inl(ioaddr + cr), ioaddr + cr);
6aa20a22 2352
1da177e4
LT
2353 /* Check that the chip has finished the reset. */
2354 while (status && (i++ < 1000)) {
2355 status ^= (inl(isr + ioaddr) & status);
2356 }
2357
2358 if( (sis_priv->chipset_rev >= SIS635A_900_REV) ||
2359 (sis_priv->chipset_rev == SIS900B_900_REV) )
2360 outl(PESEL | RND_CNT, ioaddr + cfg);
2361 else
2362 outl(PESEL, ioaddr + cfg);
2363}
2364
2365/**
6aa20a22 2366 * sis900_remove - Remove sis900 device
1da177e4
LT
2367 * @pci_dev: the pci device to be removed
2368 *
2369 * remove and release SiS900 net device
2370 */
2371
2372static void __devexit sis900_remove(struct pci_dev *pci_dev)
2373{
2374 struct net_device *net_dev = pci_get_drvdata(pci_dev);
8f15ea42 2375 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
2376 struct mii_phy *phy = NULL;
2377
2378 while (sis_priv->first_mii) {
2379 phy = sis_priv->first_mii;
2380 sis_priv->first_mii = phy->next;
2381 kfree(phy);
2382 }
2383
2384 pci_free_consistent(pci_dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
2385 sis_priv->rx_ring_dma);
2386 pci_free_consistent(pci_dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
2387 sis_priv->tx_ring_dma);
2388 unregister_netdev(net_dev);
2389 free_netdev(net_dev);
2390 pci_release_regions(pci_dev);
2391 pci_set_drvdata(pci_dev, NULL);
2392}
2393
2394#ifdef CONFIG_PM
2395
2396static int sis900_suspend(struct pci_dev *pci_dev, pm_message_t state)
2397{
2398 struct net_device *net_dev = pci_get_drvdata(pci_dev);
2399 long ioaddr = net_dev->base_addr;
2400
2401 if(!netif_running(net_dev))
2402 return 0;
2403
2404 netif_stop_queue(net_dev);
2405 netif_device_detach(net_dev);
2406
2407 /* Stop the chip's Tx and Rx Status Machine */
2408 outl(RxDIS | TxDIS | inl(ioaddr + cr), ioaddr + cr);
2409
2410 pci_set_power_state(pci_dev, PCI_D3hot);
2411 pci_save_state(pci_dev);
2412
2413 return 0;
2414}
2415
2416static int sis900_resume(struct pci_dev *pci_dev)
2417{
2418 struct net_device *net_dev = pci_get_drvdata(pci_dev);
8f15ea42 2419 struct sis900_private *sis_priv = netdev_priv(net_dev);
1da177e4
LT
2420 long ioaddr = net_dev->base_addr;
2421
2422 if(!netif_running(net_dev))
2423 return 0;
2424 pci_restore_state(pci_dev);
2425 pci_set_power_state(pci_dev, PCI_D0);
2426
2427 sis900_init_rxfilter(net_dev);
2428
2429 sis900_init_tx_ring(net_dev);
2430 sis900_init_rx_ring(net_dev);
2431
2432 set_rx_mode(net_dev);
2433
2434 netif_device_attach(net_dev);
2435 netif_start_queue(net_dev);
2436
2437 /* Workaround for EDB */
2438 sis900_set_mode(ioaddr, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
2439
2440 /* Enable all known interrupts by setting the interrupt mask. */
2441 outl((RxSOVR|RxORN|RxERR|RxOK|TxURN|TxERR|TxIDLE), ioaddr + imr);
2442 outl(RxENA | inl(ioaddr + cr), ioaddr + cr);
2443 outl(IE, ioaddr + ier);
2444
2445 sis900_check_mode(net_dev, sis_priv->mii);
2446
2447 return 0;
2448}
2449#endif /* CONFIG_PM */
2450
2451static struct pci_driver sis900_pci_driver = {
2452 .name = SIS900_MODULE_NAME,
2453 .id_table = sis900_pci_tbl,
2454 .probe = sis900_probe,
2455 .remove = __devexit_p(sis900_remove),
2456#ifdef CONFIG_PM
2457 .suspend = sis900_suspend,
2458 .resume = sis900_resume,
2459#endif /* CONFIG_PM */
2460};
2461
2462static int __init sis900_init_module(void)
2463{
2464/* when a module, this is printed whether or not devices are found in probe */
2465#ifdef MODULE
2466 printk(version);
2467#endif
2468
29917620 2469 return pci_register_driver(&sis900_pci_driver);
1da177e4
LT
2470}
2471
2472static void __exit sis900_cleanup_module(void)
2473{
2474 pci_unregister_driver(&sis900_pci_driver);
2475}
2476
2477module_init(sis900_init_module);
2478module_exit(sis900_cleanup_module);
2479