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Merge git://git.infradead.org/~dhowells/irq-2.6
[mirror_ubuntu-artful-kernel.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
14c85021 27#include <linux/in.h>
baef58b1
SH		 28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
4075400b 39#include <linux/dma-mapping.h>
2cd8e5d3 40#include <linux/mii.h>
baef58b1
SH		 41#include <asm/irq.h>
42
43#include "skge.h"
44
45#define DRV_NAME "skge"
f6aa1693 46#define DRV_VERSION "1.8"
baef58b1
SH		 47#define PFX DRV_NAME " "
48
49#define DEFAULT_TX_RING_SIZE 128
50#define DEFAULT_RX_RING_SIZE 512
51#define MAX_TX_RING_SIZE 1024
9db96479 52#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 53#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 54#define RX_COPY_THRESHOLD 128
55#define RX_BUF_SIZE 1536
baef58b1
SH		 56#define PHY_RETRIES 1000
57#define ETH_JUMBO_MTU 9000
58#define TX_WATCHDOG (5 * HZ)
59#define NAPI_WEIGHT 64
6abebb53 60#define BLINK_MS 250
64f6b64d 61#define LINK_HZ (HZ/2)
baef58b1
SH		 62
63MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
64MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
65MODULE_LICENSE("GPL");
66MODULE_VERSION(DRV_VERSION);
67
68static const u32 default_msg
69 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
70 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
71
72static int debug = -1; /* defaults above */
73module_param(debug, int, 0);
74MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
75
76static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
78 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
80 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
275834d1 81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
2d2a3871 82 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
84 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
85 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 86 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86f0cd50 87 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
baef58b1
SH		 88 { 0 }
89};
90MODULE_DEVICE_TABLE(pci, skge_id_table);
91
92static int skge_up(struct net_device *dev);
93static int skge_down(struct net_device *dev);
ee294dcd 94static void skge_phy_reset(struct skge_port *skge);
513f533e 95static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 96static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 98static void genesis_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_get_stats(struct skge_port *skge, u64 *data);
100static void yukon_init(struct skge_hw *hw, int port);
baef58b1 101static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 102static void genesis_link_up(struct skge_port *skge);
baef58b1 103
7e676d91 104/* Avoid conditionals by using array */
baef58b1
SH		 105static const int txqaddr[] = { Q_XA1, Q_XA2 };
106static const int rxqaddr[] = { Q_R1, Q_R2 };
107static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
108static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
513f533e 109static const u32 irqmask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
baef58b1 110
baef58b1
SH		 111static int skge_get_regs_len(struct net_device *dev)
112{
c3f8be96 113 return 0x4000;
baef58b1
SH		 114}
115
116/*
c3f8be96
SH		 117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
119 * cause bus hangs!
baef58b1
SH		 120 */
121static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
122 void *p)
123{
124 const struct skge_port *skge = netdev_priv(dev);
baef58b1 125 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 126
127 regs->version = 1;
c3f8be96
SH		 128 memset(p, 0, regs->len);
129 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 130
c3f8be96
SH		 131 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
132 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 133}
134
8f3f8193 135/* Wake on Lan only supported on Yukon chips with rev 1 or above */
baef58b1
SH		 136static int wol_supported(const struct skge_hw *hw)
137{
138 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 139 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 140}
141
142static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
143{
144 struct skge_port *skge = netdev_priv(dev);
145
146 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
147 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
148}
149
150static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
151{
152 struct skge_port *skge = netdev_priv(dev);
153 struct skge_hw *hw = skge->hw;
154
95566065 155 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 156 return -EOPNOTSUPP;
157
158 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
159 return -EOPNOTSUPP;
160
161 skge->wol = wol->wolopts == WAKE_MAGIC;
162
163 if (skge->wol) {
164 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
165
166 skge_write16(hw, WOL_CTRL_STAT,
167 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
168 WOL_CTL_ENA_MAGIC_PKT_UNIT);
169 } else
170 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
171
172 return 0;
173}
174
8f3f8193
SH		 175/* Determine supported/advertised modes based on hardware.
176 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 177 */
178static u32 skge_supported_modes(const struct skge_hw *hw)
179{
180 u32 supported;
181
5e1705dd 182 if (hw->copper) {
31b619c5
SH		 183 supported = SUPPORTED_10baseT_Half
184 | SUPPORTED_10baseT_Full
185 | SUPPORTED_100baseT_Half
186 | SUPPORTED_100baseT_Full
187 | SUPPORTED_1000baseT_Half
188 | SUPPORTED_1000baseT_Full
189 | SUPPORTED_Autoneg| SUPPORTED_TP;
190
191 if (hw->chip_id == CHIP_ID_GENESIS)
192 supported &= ~(SUPPORTED_10baseT_Half
193 | SUPPORTED_10baseT_Full
194 | SUPPORTED_100baseT_Half
195 | SUPPORTED_100baseT_Full);
196
197 else if (hw->chip_id == CHIP_ID_YUKON)
198 supported &= ~SUPPORTED_1000baseT_Half;
199 } else
200 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
201 | SUPPORTED_Autoneg;
202
203 return supported;
204}
baef58b1
SH		 205
206static int skge_get_settings(struct net_device *dev,
207 struct ethtool_cmd *ecmd)
208{
209 struct skge_port *skge = netdev_priv(dev);
210 struct skge_hw *hw = skge->hw;
211
212 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 213 ecmd->supported = skge_supported_modes(hw);
baef58b1 214
5e1705dd 215 if (hw->copper) {
baef58b1
SH		 216 ecmd->port = PORT_TP;
217 ecmd->phy_address = hw->phy_addr;
31b619c5 218 } else
baef58b1 219 ecmd->port = PORT_FIBRE;
baef58b1
SH		 220
221 ecmd->advertising = skge->advertising;
222 ecmd->autoneg = skge->autoneg;
223 ecmd->speed = skge->speed;
224 ecmd->duplex = skge->duplex;
225 return 0;
226}
227
baef58b1
SH		 228static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
229{
230 struct skge_port *skge = netdev_priv(dev);
231 const struct skge_hw *hw = skge->hw;
31b619c5 232 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 233
234 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 235 ecmd->advertising = supported;
236 skge->duplex = -1;
237 skge->speed = -1;
baef58b1 238 } else {
31b619c5
SH		 239 u32 setting;
240
2c668514 241 switch (ecmd->speed) {
baef58b1 242 case SPEED_1000:
31b619c5
SH		 243 if (ecmd->duplex == DUPLEX_FULL)
244 setting = SUPPORTED_1000baseT_Full;
245 else if (ecmd->duplex == DUPLEX_HALF)
246 setting = SUPPORTED_1000baseT_Half;
247 else
248 return -EINVAL;
baef58b1
SH		 249 break;
250 case SPEED_100:
31b619c5
SH		 251 if (ecmd->duplex == DUPLEX_FULL)
252 setting = SUPPORTED_100baseT_Full;
253 else if (ecmd->duplex == DUPLEX_HALF)
254 setting = SUPPORTED_100baseT_Half;
255 else
256 return -EINVAL;
257 break;
258
baef58b1 259 case SPEED_10:
31b619c5
SH		 260 if (ecmd->duplex == DUPLEX_FULL)
261 setting = SUPPORTED_10baseT_Full;
262 else if (ecmd->duplex == DUPLEX_HALF)
263 setting = SUPPORTED_10baseT_Half;
264 else
baef58b1
SH		 265 return -EINVAL;
266 break;
267 default:
268 return -EINVAL;
269 }
31b619c5
SH		 270
271 if ((setting & supported) == 0)
272 return -EINVAL;
273
274 skge->speed = ecmd->speed;
275 skge->duplex = ecmd->duplex;
baef58b1
SH		 276 }
277
278 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 279 skge->advertising = ecmd->advertising;
280
ee294dcd
SH		 281 if (netif_running(dev))
282 skge_phy_reset(skge);
283
baef58b1
SH		 284 return (0);
285}
286
287static void skge_get_drvinfo(struct net_device *dev,
288 struct ethtool_drvinfo *info)
289{
290 struct skge_port *skge = netdev_priv(dev);
291
292 strcpy(info->driver, DRV_NAME);
293 strcpy(info->version, DRV_VERSION);
294 strcpy(info->fw_version, "N/A");
295 strcpy(info->bus_info, pci_name(skge->hw->pdev));
296}
297
298static const struct skge_stat {
299 char name[ETH_GSTRING_LEN];
300 u16 xmac_offset;
301 u16 gma_offset;
302} skge_stats[] = {
303 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
304 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
305
306 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
307 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
308 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
309 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
310 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
311 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
312 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
313 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
314
315 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
316 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
317 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
318 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
319 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
320 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
321
322 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
323 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
324 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
325 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
326 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
327};
328
329static int skge_get_stats_count(struct net_device *dev)
330{
331 return ARRAY_SIZE(skge_stats);
332}
333
334static void skge_get_ethtool_stats(struct net_device *dev,
335 struct ethtool_stats *stats, u64 *data)
336{
337 struct skge_port *skge = netdev_priv(dev);
338
339 if (skge->hw->chip_id == CHIP_ID_GENESIS)
340 genesis_get_stats(skge, data);
341 else
342 yukon_get_stats(skge, data);
343}
344
345/* Use hardware MIB variables for critical path statistics and
346 * transmit feedback not reported at interrupt.
347 * Other errors are accounted for in interrupt handler.
348 */
349static struct net_device_stats *skge_get_stats(struct net_device *dev)
350{
351 struct skge_port *skge = netdev_priv(dev);
352 u64 data[ARRAY_SIZE(skge_stats)];
353
354 if (skge->hw->chip_id == CHIP_ID_GENESIS)
355 genesis_get_stats(skge, data);
356 else
357 yukon_get_stats(skge, data);
358
359 skge->net_stats.tx_bytes = data[0];
360 skge->net_stats.rx_bytes = data[1];
361 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
362 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
4c180fc4 363 skge->net_stats.multicast = data[3] + data[5];
baef58b1
SH		 364 skge->net_stats.collisions = data[10];
365 skge->net_stats.tx_aborted_errors = data[12];
366
367 return &skge->net_stats;
368}
369
370static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
371{
372 int i;
373
95566065 374 switch (stringset) {
baef58b1
SH		 375 case ETH_SS_STATS:
376 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
377 memcpy(data + i * ETH_GSTRING_LEN,
378 skge_stats[i].name, ETH_GSTRING_LEN);
379 break;
380 }
381}
382
383static void skge_get_ring_param(struct net_device *dev,
384 struct ethtool_ringparam *p)
385{
386 struct skge_port *skge = netdev_priv(dev);
387
388 p->rx_max_pending = MAX_RX_RING_SIZE;
389 p->tx_max_pending = MAX_TX_RING_SIZE;
390 p->rx_mini_max_pending = 0;
391 p->rx_jumbo_max_pending = 0;
392
393 p->rx_pending = skge->rx_ring.count;
394 p->tx_pending = skge->tx_ring.count;
395 p->rx_mini_pending = 0;
396 p->rx_jumbo_pending = 0;
397}
398
399static int skge_set_ring_param(struct net_device *dev,
400 struct ethtool_ringparam *p)
401{
402 struct skge_port *skge = netdev_priv(dev);
3b8bb472 403 int err;
baef58b1
SH		 404
405 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 406 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 407 return -EINVAL;
408
409 skge->rx_ring.count = p->rx_pending;
410 skge->tx_ring.count = p->tx_pending;
411
412 if (netif_running(dev)) {
413 skge_down(dev);
3b8bb472
SH		 414 err = skge_up(dev);
415 if (err)
416 dev_close(dev);
baef58b1
SH		 417 }
418
419 return 0;
420}
421
422static u32 skge_get_msglevel(struct net_device *netdev)
423{
424 struct skge_port *skge = netdev_priv(netdev);
425 return skge->msg_enable;
426}
427
428static void skge_set_msglevel(struct net_device *netdev, u32 value)
429{
430 struct skge_port *skge = netdev_priv(netdev);
431 skge->msg_enable = value;
432}
433
434static int skge_nway_reset(struct net_device *dev)
435{
436 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 437
438 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
439 return -EINVAL;
440
ee294dcd 441 skge_phy_reset(skge);
baef58b1
SH		 442 return 0;
443}
444
445static int skge_set_sg(struct net_device *dev, u32 data)
446{
447 struct skge_port *skge = netdev_priv(dev);
448 struct skge_hw *hw = skge->hw;
449
450 if (hw->chip_id == CHIP_ID_GENESIS && data)
451 return -EOPNOTSUPP;
452 return ethtool_op_set_sg(dev, data);
453}
454
455static int skge_set_tx_csum(struct net_device *dev, u32 data)
456{
457 struct skge_port *skge = netdev_priv(dev);
458 struct skge_hw *hw = skge->hw;
459
460 if (hw->chip_id == CHIP_ID_GENESIS && data)
461 return -EOPNOTSUPP;
462
463 return ethtool_op_set_tx_csum(dev, data);
464}
465
466static u32 skge_get_rx_csum(struct net_device *dev)
467{
468 struct skge_port *skge = netdev_priv(dev);
469
470 return skge->rx_csum;
471}
472
473/* Only Yukon supports checksum offload. */
474static int skge_set_rx_csum(struct net_device *dev, u32 data)
475{
476 struct skge_port *skge = netdev_priv(dev);
477
478 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
479 return -EOPNOTSUPP;
480
481 skge->rx_csum = data;
482 return 0;
483}
484
baef58b1
SH		 485static void skge_get_pauseparam(struct net_device *dev,
486 struct ethtool_pauseparam *ecmd)
487{
488 struct skge_port *skge = netdev_priv(dev);
489
490 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
491 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
492 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
493 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
494
495 ecmd->autoneg = skge->autoneg;
496}
497
498static int skge_set_pauseparam(struct net_device *dev,
499 struct ethtool_pauseparam *ecmd)
500{
501 struct skge_port *skge = netdev_priv(dev);
502
503 skge->autoneg = ecmd->autoneg;
504 if (ecmd->rx_pause && ecmd->tx_pause)
505 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 506 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 507 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 508 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 509 skge->flow_control = FLOW_MODE_LOC_SEND;
510 else
511 skge->flow_control = FLOW_MODE_NONE;
512
e8df8554
SH		 513 if (netif_running(dev))
514 skge_phy_reset(skge);
baef58b1
SH		 515 return 0;
516}
517
518/* Chip internal frequency for clock calculations */
519static inline u32 hwkhz(const struct skge_hw *hw)
520{
187ff3b8 521 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 522}
523
8f3f8193 524/* Chip HZ to microseconds */
baef58b1
SH		 525static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
526{
527 return (ticks * 1000) / hwkhz(hw);
528}
529
8f3f8193 530/* Microseconds to chip HZ */
baef58b1
SH		 531static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
532{
533 return hwkhz(hw) * usec / 1000;
534}
535
536static int skge_get_coalesce(struct net_device *dev,
537 struct ethtool_coalesce *ecmd)
538{
539 struct skge_port *skge = netdev_priv(dev);
540 struct skge_hw *hw = skge->hw;
541 int port = skge->port;
542
543 ecmd->rx_coalesce_usecs = 0;
544 ecmd->tx_coalesce_usecs = 0;
545
546 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
547 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
548 u32 msk = skge_read32(hw, B2_IRQM_MSK);
549
550 if (msk & rxirqmask[port])
551 ecmd->rx_coalesce_usecs = delay;
552 if (msk & txirqmask[port])
553 ecmd->tx_coalesce_usecs = delay;
554 }
555
556 return 0;
557}
558
559/* Note: interrupt timer is per board, but can turn on/off per port */
560static int skge_set_coalesce(struct net_device *dev,
561 struct ethtool_coalesce *ecmd)
562{
563 struct skge_port *skge = netdev_priv(dev);
564 struct skge_hw *hw = skge->hw;
565 int port = skge->port;
566 u32 msk = skge_read32(hw, B2_IRQM_MSK);
567 u32 delay = 25;
568
569 if (ecmd->rx_coalesce_usecs == 0)
570 msk &= ~rxirqmask[port];
571 else if (ecmd->rx_coalesce_usecs < 25 ||
572 ecmd->rx_coalesce_usecs > 33333)
573 return -EINVAL;
574 else {
575 msk |= rxirqmask[port];
576 delay = ecmd->rx_coalesce_usecs;
577 }
578
579 if (ecmd->tx_coalesce_usecs == 0)
580 msk &= ~txirqmask[port];
581 else if (ecmd->tx_coalesce_usecs < 25 ||
582 ecmd->tx_coalesce_usecs > 33333)
583 return -EINVAL;
584 else {
585 msk |= txirqmask[port];
586 delay = min(delay, ecmd->rx_coalesce_usecs);
587 }
588
589 skge_write32(hw, B2_IRQM_MSK, msk);
590 if (msk == 0)
591 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
592 else {
593 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
594 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
595 }
596 return 0;
597}
598
6abebb53
SH		 599enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
600static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 601{
6abebb53
SH		 602 struct skge_hw *hw = skge->hw;
603 int port = skge->port;
604
d85b514f 605 mutex_lock(&hw->phy_mutex);
baef58b1 606 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 607 switch (mode) {
608 case LED_MODE_OFF:
64f6b64d
SH		 609 if (hw->phy_type == SK_PHY_BCOM)
610 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
611 else {
612 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
613 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
614 }
6abebb53
SH		 615 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
616 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
617 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
618 break;
baef58b1 619
6abebb53
SH		 620 case LED_MODE_ON:
621 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
622 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 623
6abebb53
SH		 624 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
625 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 626
6abebb53 627 break;
baef58b1 628
6abebb53
SH		 629 case LED_MODE_TST:
630 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
631 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
632 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 633
64f6b64d
SH		 634 if (hw->phy_type == SK_PHY_BCOM)
635 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
636 else {
637 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
638 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
639 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
640 }
641
6abebb53 642 }
baef58b1 643 } else {
6abebb53
SH		 644 switch (mode) {
645 case LED_MODE_OFF:
646 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
647 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
648 PHY_M_LED_MO_DUP(MO_LED_OFF) |
649 PHY_M_LED_MO_10(MO_LED_OFF) |
650 PHY_M_LED_MO_100(MO_LED_OFF) |
651 PHY_M_LED_MO_1000(MO_LED_OFF) |
652 PHY_M_LED_MO_RX(MO_LED_OFF));
653 break;
654 case LED_MODE_ON:
655 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
656 PHY_M_LED_PULS_DUR(PULS_170MS) |
657 PHY_M_LED_BLINK_RT(BLINK_84MS) |
658 PHY_M_LEDC_TX_CTRL |
659 PHY_M_LEDC_DP_CTRL);
46a60f2d 660
6abebb53
SH		 661 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
662 PHY_M_LED_MO_RX(MO_LED_OFF) |
663 (skge->speed == SPEED_100 ?
664 PHY_M_LED_MO_100(MO_LED_ON) : 0));
665 break;
666 case LED_MODE_TST:
667 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
668 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
669 PHY_M_LED_MO_DUP(MO_LED_ON) |
670 PHY_M_LED_MO_10(MO_LED_ON) |
671 PHY_M_LED_MO_100(MO_LED_ON) |
672 PHY_M_LED_MO_1000(MO_LED_ON) |
673 PHY_M_LED_MO_RX(MO_LED_ON));
674 }
baef58b1 675 }
d85b514f 676 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 677}
678
679/* blink LED's for finding board */
680static int skge_phys_id(struct net_device *dev, u32 data)
681{
682 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 683 unsigned long ms;
684 enum led_mode mode = LED_MODE_TST;
baef58b1 685
95566065 686 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 687 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
688 else
689 ms = data * 1000;
baef58b1 690
6abebb53
SH		 691 while (ms > 0) {
692 skge_led(skge, mode);
693 mode ^= LED_MODE_TST;
baef58b1 694
6abebb53
SH		 695 if (msleep_interruptible(BLINK_MS))
696 break;
697 ms -= BLINK_MS;
698 }
baef58b1 699
6abebb53
SH		 700 /* back to regular LED state */
701 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 702
703 return 0;
704}
705
7282d491 706static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 707 .get_settings = skge_get_settings,
708 .set_settings = skge_set_settings,
709 .get_drvinfo = skge_get_drvinfo,
710 .get_regs_len = skge_get_regs_len,
711 .get_regs = skge_get_regs,
712 .get_wol = skge_get_wol,
713 .set_wol = skge_set_wol,
714 .get_msglevel = skge_get_msglevel,
715 .set_msglevel = skge_set_msglevel,
716 .nway_reset = skge_nway_reset,
717 .get_link = ethtool_op_get_link,
718 .get_ringparam = skge_get_ring_param,
719 .set_ringparam = skge_set_ring_param,
720 .get_pauseparam = skge_get_pauseparam,
721 .set_pauseparam = skge_set_pauseparam,
722 .get_coalesce = skge_get_coalesce,
723 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 724 .get_sg = ethtool_op_get_sg,
725 .set_sg = skge_set_sg,
726 .get_tx_csum = ethtool_op_get_tx_csum,
727 .set_tx_csum = skge_set_tx_csum,
728 .get_rx_csum = skge_get_rx_csum,
729 .set_rx_csum = skge_set_rx_csum,
730 .get_strings = skge_get_strings,
731 .phys_id = skge_phys_id,
732 .get_stats_count = skge_get_stats_count,
733 .get_ethtool_stats = skge_get_ethtool_stats,
56230d53 734 .get_perm_addr = ethtool_op_get_perm_addr,
baef58b1
SH		 735};
736
737/*
738 * Allocate ring elements and chain them together
739 * One-to-one association of board descriptors with ring elements
740 */
c3da1447 741static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 742{
743 struct skge_tx_desc *d;
744 struct skge_element *e;
745 int i;
746
ff7907ae 747 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
baef58b1
SH		 748 if (!ring->start)
749 return -ENOMEM;
750
751 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
752 e->desc = d;
753 if (i == ring->count - 1) {
754 e->next = ring->start;
755 d->next_offset = base;
756 } else {
757 e->next = e + 1;
758 d->next_offset = base + (i+1) * sizeof(*d);
759 }
760 }
761 ring->to_use = ring->to_clean = ring->start;
762
763 return 0;
764}
765
19a33d4e
SH		 766/* Allocate and setup a new buffer for receiving */
767static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
768 struct sk_buff *skb, unsigned int bufsize)
769{
770 struct skge_rx_desc *rd = e->desc;
771 u64 map;
baef58b1
SH		 772
773 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
774 PCI_DMA_FROMDEVICE);
775
776 rd->dma_lo = map;
777 rd->dma_hi = map >> 32;
778 e->skb = skb;
779 rd->csum1_start = ETH_HLEN;
780 rd->csum2_start = ETH_HLEN;
781 rd->csum1 = 0;
782 rd->csum2 = 0;
783
784 wmb();
785
786 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
787 pci_unmap_addr_set(e, mapaddr, map);
788 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 789}
790
19a33d4e
SH		 791/* Resume receiving using existing skb,
792 * Note: DMA address is not changed by chip.
793 * MTU not changed while receiver active.
794 */
5a011447 795static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 796{
797 struct skge_rx_desc *rd = e->desc;
798
799 rd->csum2 = 0;
800 rd->csum2_start = ETH_HLEN;
801
802 wmb();
803
804 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
805}
806
807
808/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 809static void skge_rx_clean(struct skge_port *skge)
810{
811 struct skge_hw *hw = skge->hw;
812 struct skge_ring *ring = &skge->rx_ring;
813 struct skge_element *e;
814
19a33d4e
SH		 815 e = ring->start;
816 do {
baef58b1
SH		 817 struct skge_rx_desc *rd = e->desc;
818 rd->control = 0;
19a33d4e
SH		 819 if (e->skb) {
820 pci_unmap_single(hw->pdev,
821 pci_unmap_addr(e, mapaddr),
822 pci_unmap_len(e, maplen),
823 PCI_DMA_FROMDEVICE);
824 dev_kfree_skb(e->skb);
825 e->skb = NULL;
826 }
827 } while ((e = e->next) != ring->start);
baef58b1
SH		 828}
829
19a33d4e 830
baef58b1 831/* Allocate buffers for receive ring
19a33d4e 832 * For receive: to_clean is next received frame.
baef58b1 833 */
c54f9765 834static int skge_rx_fill(struct net_device *dev)
baef58b1 835{
c54f9765 836 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 837 struct skge_ring *ring = &skge->rx_ring;
838 struct skge_element *e;
baef58b1 839
19a33d4e
SH		 840 e = ring->start;
841 do {
383181ac 842 struct sk_buff *skb;
baef58b1 843
c54f9765
SH		 844 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
845 GFP_KERNEL);
19a33d4e
SH		 846 if (!skb)
847 return -ENOMEM;
848
383181ac
SH		 849 skb_reserve(skb, NET_IP_ALIGN);
850 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 851 } while ( (e = e->next) != ring->start);
baef58b1 852
19a33d4e
SH		 853 ring->to_clean = ring->start;
854 return 0;
baef58b1
SH		 855}
856
857static void skge_link_up(struct skge_port *skge)
858{
46a60f2d 859 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 860 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
861
baef58b1 862 netif_carrier_on(skge->netdev);
29b4e886 863 netif_wake_queue(skge->netdev);
baef58b1
SH		 864
865 if (netif_msg_link(skge))
866 printk(KERN_INFO PFX
867 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
868 skge->netdev->name, skge->speed,
869 skge->duplex == DUPLEX_FULL ? "full" : "half",
870 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
871 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
872 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
873 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
874 "unknown");
875}
876
877static void skge_link_down(struct skge_port *skge)
878{
54cfb5aa 879 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 880 netif_carrier_off(skge->netdev);
881 netif_stop_queue(skge->netdev);
882
883 if (netif_msg_link(skge))
884 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
885}
886
2cd8e5d3 887static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 888{
889 int i;
baef58b1 890
6b0c1480 891 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 892 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 893
64f6b64d
SH		 894 if (hw->phy_type == SK_PHY_XMAC)
895 goto ready;
896
89bf5f23 897 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 898 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 899 goto ready;
0781191c 900 udelay(1);
baef58b1
SH		 901 }
902
2cd8e5d3 903 return -ETIMEDOUT;
89bf5f23 904 ready:
2cd8e5d3 905 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 906
2cd8e5d3
SH		 907 return 0;
908}
909
910static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
911{
912 u16 v = 0;
913 if (__xm_phy_read(hw, port, reg, &v))
914 printk(KERN_WARNING PFX "%s: phy read timed out\n",
915 hw->dev[port]->name);
baef58b1
SH		 916 return v;
917}
918
2cd8e5d3 919static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 920{
921 int i;
922
6b0c1480 923 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 924 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 925 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 926 goto ready;
89bf5f23 927 udelay(1);
baef58b1 928 }
2cd8e5d3 929 return -EIO;
baef58b1
SH		 930
931 ready:
6b0c1480 932 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 933 for (i = 0; i < PHY_RETRIES; i++) {
934 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
935 return 0;
936 udelay(1);
937 }
938 return -ETIMEDOUT;
baef58b1
SH		 939}
940
941static void genesis_init(struct skge_hw *hw)
942{
943 /* set blink source counter */
944 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
945 skge_write8(hw, B2_BSC_CTRL, BSC_START);
946
947 /* configure mac arbiter */
948 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
949
950 /* configure mac arbiter timeout values */
951 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
952 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
953 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
954 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
955
956 skge_write8(hw, B3_MA_RCINI_RX1, 0);
957 skge_write8(hw, B3_MA_RCINI_RX2, 0);
958 skge_write8(hw, B3_MA_RCINI_TX1, 0);
959 skge_write8(hw, B3_MA_RCINI_TX2, 0);
960
961 /* configure packet arbiter timeout */
962 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
963 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
964 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
965 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
966 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
967}
968
969static void genesis_reset(struct skge_hw *hw, int port)
970{
45bada65 971 const u8 zero[8] = { 0 };
baef58b1 972
46a60f2d
SH		 973 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
974
baef58b1 975 /* reset the statistics module */
6b0c1480
SH		 976 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
977 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
978 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
979 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
980 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 981
89bf5f23 982 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 983 if (hw->phy_type == SK_PHY_BCOM)
984 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 985
45bada65 986 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 987}
988
989
45bada65
SH		 990/* Convert mode to MII values */
991static const u16 phy_pause_map[] = {
992 [FLOW_MODE_NONE] = 0,
993 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
994 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
995 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
996};
997
998
999/* Check status of Broadcom phy link */
1000static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1001{
45bada65
SH		 1002 struct net_device *dev = hw->dev[port];
1003 struct skge_port *skge = netdev_priv(dev);
1004 u16 status;
1005
1006 /* read twice because of latch */
1007 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1008 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1009
45bada65
SH		 1010 if ((status & PHY_ST_LSYNC) == 0) {
1011 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1012 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1013 xm_write16(hw, port, XM_MMU_CMD, cmd);
1014 /* dummy read to ensure writing */
1015 (void) xm_read16(hw, port, XM_MMU_CMD);
1016
1017 if (netif_carrier_ok(dev))
1018 skge_link_down(skge);
64f6b64d
SH		 1019 return;
1020 }
45bada65 1021
64f6b64d
SH		 1022 if (skge->autoneg == AUTONEG_ENABLE) {
1023 u16 lpa, aux;
45bada65 1024
64f6b64d
SH		 1025 if (!(status & PHY_ST_AN_OVER))
1026 return;
45bada65 1027
64f6b64d
SH		 1028 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1029 if (lpa & PHY_B_AN_RF) {
1030 printk(KERN_NOTICE PFX "%s: remote fault\n",
1031 dev->name);
1032 return;
1033 }
45bada65 1034
64f6b64d
SH		 1035 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1036
1037 /* Check Duplex mismatch */
1038 switch (aux & PHY_B_AS_AN_RES_MSK) {
1039 case PHY_B_RES_1000FD:
1040 skge->duplex = DUPLEX_FULL;
1041 break;
1042 case PHY_B_RES_1000HD:
1043 skge->duplex = DUPLEX_HALF;
1044 break;
1045 default:
1046 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1047 dev->name);
1048 return;
45bada65
SH		 1049 }
1050
64f6b64d
SH		 1051
1052 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1053 switch (aux & PHY_B_AS_PAUSE_MSK) {
1054 case PHY_B_AS_PAUSE_MSK:
1055 skge->flow_control = FLOW_MODE_SYMMETRIC;
1056 break;
1057 case PHY_B_AS_PRR:
1058 skge->flow_control = FLOW_MODE_REM_SEND;
1059 break;
1060 case PHY_B_AS_PRT:
1061 skge->flow_control = FLOW_MODE_LOC_SEND;
1062 break;
1063 default:
1064 skge->flow_control = FLOW_MODE_NONE;
1065 }
1066 skge->speed = SPEED_1000;
45bada65 1067 }
64f6b64d
SH		 1068
1069 if (!netif_carrier_ok(dev))
1070 genesis_link_up(skge);
45bada65
SH		 1071}
1072
1073/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1074 * Phy on for 100 or 10Mbit operation
1075 */
64f6b64d 1076static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1077{
1078 struct skge_hw *hw = skge->hw;
1079 int port = skge->port;
baef58b1 1080 int i;
45bada65 1081 u16 id1, r, ext, ctl;
baef58b1
SH		 1082
1083 /* magic workaround patterns for Broadcom */
1084 static const struct {
1085 u16 reg;
1086 u16 val;
1087 } A1hack[] = {
1088 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1089 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1090 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1091 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1092 }, C0hack[] = {
1093 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1094 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1095 };
1096
45bada65
SH		 1097 /* read Id from external PHY (all have the same address) */
1098 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1099
1100 /* Optimize MDIO transfer by suppressing preamble. */
1101 r = xm_read16(hw, port, XM_MMU_CMD);
1102 r |= XM_MMU_NO_PRE;
1103 xm_write16(hw, port, XM_MMU_CMD,r);
1104
2c668514 1105 switch (id1) {
45bada65
SH		 1106 case PHY_BCOM_ID1_C0:
1107 /*
1108 * Workaround BCOM Errata for the C0 type.
1109 * Write magic patterns to reserved registers.
1110 */
1111 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1112 xm_phy_write(hw, port,
1113 C0hack[i].reg, C0hack[i].val);
1114
1115 break;
1116 case PHY_BCOM_ID1_A1:
1117 /*
1118 * Workaround BCOM Errata for the A1 type.
1119 * Write magic patterns to reserved registers.
1120 */
1121 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1122 xm_phy_write(hw, port,
1123 A1hack[i].reg, A1hack[i].val);
1124 break;
1125 }
1126
1127 /*
1128 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1129 * Disable Power Management after reset.
1130 */
1131 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1132 r |= PHY_B_AC_DIS_PM;
1133 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1134
1135 /* Dummy read */
1136 xm_read16(hw, port, XM_ISRC);
1137
1138 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1139 ctl = PHY_CT_SP1000; /* always 1000mbit */
1140
1141 if (skge->autoneg == AUTONEG_ENABLE) {
1142 /*
1143 * Workaround BCOM Errata #1 for the C5 type.
1144 * 1000Base-T Link Acquisition Failure in Slave Mode
1145 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1146 */
1147 u16 adv = PHY_B_1000C_RD;
1148 if (skge->advertising & ADVERTISED_1000baseT_Half)
1149 adv |= PHY_B_1000C_AHD;
1150 if (skge->advertising & ADVERTISED_1000baseT_Full)
1151 adv |= PHY_B_1000C_AFD;
1152 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1153
1154 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1155 } else {
1156 if (skge->duplex == DUPLEX_FULL)
1157 ctl |= PHY_CT_DUP_MD;
1158 /* Force to slave */
1159 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1160 }
1161
1162 /* Set autonegotiation pause parameters */
1163 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1164 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1165
1166 /* Handle Jumbo frames */
64f6b64d 1167 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1168 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1169 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1170
1171 ext |= PHY_B_PEC_HIGH_LA;
1172
1173 }
1174
1175 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1176 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1177
8f3f8193 1178 /* Use link status change interrupt */
45bada65 1179 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1180}
45bada65 1181
64f6b64d
SH		 1182static void xm_phy_init(struct skge_port *skge)
1183{
1184 struct skge_hw *hw = skge->hw;
1185 int port = skge->port;
1186 u16 ctrl = 0;
1187
1188 if (skge->autoneg == AUTONEG_ENABLE) {
1189 if (skge->advertising & ADVERTISED_1000baseT_Half)
1190 ctrl |= PHY_X_AN_HD;
1191 if (skge->advertising & ADVERTISED_1000baseT_Full)
1192 ctrl |= PHY_X_AN_FD;
1193
1194 switch(skge->flow_control) {
1195 case FLOW_MODE_NONE:
1196 ctrl |= PHY_X_P_NO_PAUSE;
1197 break;
1198 case FLOW_MODE_LOC_SEND:
1199 ctrl |= PHY_X_P_ASYM_MD;
1200 break;
1201 case FLOW_MODE_SYMMETRIC:
1202 ctrl |= PHY_X_P_BOTH_MD;
1203 break;
1204 }
1205
1206 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1207
1208 /* Restart Auto-negotiation */
1209 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1210 } else {
1211 /* Set DuplexMode in Config register */
1212 if (skge->duplex == DUPLEX_FULL)
1213 ctrl |= PHY_CT_DUP_MD;
1214 /*
1215 * Do NOT enable Auto-negotiation here. This would hold
1216 * the link down because no IDLEs are transmitted
1217 */
1218 }
1219
1220 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1221
1222 /* Poll PHY for status changes */
1223 schedule_delayed_work(&skge->link_thread, LINK_HZ);
1224}
1225
1226static void xm_check_link(struct net_device *dev)
1227{
1228 struct skge_port *skge = netdev_priv(dev);
1229 struct skge_hw *hw = skge->hw;
1230 int port = skge->port;
1231 u16 status;
1232
1233 /* read twice because of latch */
1234 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1235 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1236
1237 if ((status & PHY_ST_LSYNC) == 0) {
1238 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1239 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1240 xm_write16(hw, port, XM_MMU_CMD, cmd);
1241 /* dummy read to ensure writing */
1242 (void) xm_read16(hw, port, XM_MMU_CMD);
1243
1244 if (netif_carrier_ok(dev))
1245 skge_link_down(skge);
1246 return;
1247 }
1248
1249 if (skge->autoneg == AUTONEG_ENABLE) {
1250 u16 lpa, res;
1251
1252 if (!(status & PHY_ST_AN_OVER))
1253 return;
1254
1255 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1256 if (lpa & PHY_B_AN_RF) {
1257 printk(KERN_NOTICE PFX "%s: remote fault\n",
1258 dev->name);
1259 return;
1260 }
1261
1262 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1263
1264 /* Check Duplex mismatch */
1265 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1266 case PHY_X_RS_FD:
1267 skge->duplex = DUPLEX_FULL;
1268 break;
1269 case PHY_X_RS_HD:
1270 skge->duplex = DUPLEX_HALF;
1271 break;
1272 default:
1273 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1274 dev->name);
1275 return;
1276 }
1277
1278 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1279 if (lpa & PHY_X_P_SYM_MD)
1280 skge->flow_control = FLOW_MODE_SYMMETRIC;
1281 else if ((lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1282 skge->flow_control = FLOW_MODE_REM_SEND;
1283 else if ((lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1284 skge->flow_control = FLOW_MODE_LOC_SEND;
1285 else
1286 skge->flow_control = FLOW_MODE_NONE;
1287
1288
1289 skge->speed = SPEED_1000;
1290 }
1291
1292 if (!netif_carrier_ok(dev))
1293 genesis_link_up(skge);
1294}
1295
1296/* Poll to check for link coming up.
1297 * Since internal PHY is wired to a level triggered pin, can't
1298 * get an interrupt when carrier is detected.
1299 */
1300static void xm_link_timer(void *arg)
1301{
1302 struct net_device *dev = arg;
1303 struct skge_port *skge = netdev_priv(arg);
1304 struct skge_hw *hw = skge->hw;
1305 int port = skge->port;
1306
1307 if (!netif_running(dev))
1308 return;
1309
1310 if (netif_carrier_ok(dev)) {
1311 xm_read16(hw, port, XM_ISRC);
1312 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1313 goto nochange;
1314 } else {
1315 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1316 goto nochange;
1317 xm_read16(hw, port, XM_ISRC);
1318 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1319 goto nochange;
1320 }
1321
1322 mutex_lock(&hw->phy_mutex);
1323 xm_check_link(dev);
1324 mutex_unlock(&hw->phy_mutex);
1325
1326nochange:
1327 schedule_delayed_work(&skge->link_thread, LINK_HZ);
45bada65
SH		 1328}
1329
1330static void genesis_mac_init(struct skge_hw *hw, int port)
1331{
1332 struct net_device *dev = hw->dev[port];
1333 struct skge_port *skge = netdev_priv(dev);
1334 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1335 int i;
1336 u32 r;
1337 const u8 zero[6] = { 0 };
1338
0781191c
SH		 1339 for (i = 0; i < 10; i++) {
1340 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1341 MFF_SET_MAC_RST);
1342 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1343 goto reset_ok;
1344 udelay(1);
1345 }
baef58b1 1346
0781191c
SH		 1347 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1348
1349 reset_ok:
baef58b1 1350 /* Unreset the XMAC. */
6b0c1480 1351 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1352
1353 /*
1354 * Perform additional initialization for external PHYs,
1355 * namely for the 1000baseTX cards that use the XMAC's
1356 * GMII mode.
1357 */
64f6b64d
SH		 1358 if (hw->phy_type != SK_PHY_XMAC) {
1359 /* Take external Phy out of reset */
1360 r = skge_read32(hw, B2_GP_IO);
1361 if (port == 0)
1362 r |= GP_DIR_0|GP_IO_0;
1363 else
1364 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1365
64f6b64d 1366 skge_write32(hw, B2_GP_IO, r);
0781191c 1367
64f6b64d
SH		 1368 /* Enable GMII interface */
1369 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1370 }
89bf5f23 1371
89bf5f23 1372
64f6b64d
SH		 1373 switch(hw->phy_type) {
1374 case SK_PHY_XMAC:
1375 xm_phy_init(skge);
1376 break;
1377 case SK_PHY_BCOM:
1378 bcom_phy_init(skge);
1379 bcom_check_link(hw, port);
1380 }
89bf5f23 1381
45bada65
SH		 1382 /* Set Station Address */
1383 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1384
45bada65
SH		 1385 /* We don't use match addresses so clear */
1386 for (i = 1; i < 16; i++)
1387 xm_outaddr(hw, port, XM_EXM(i), zero);
1388
0781191c
SH		 1389 /* Clear MIB counters */
1390 xm_write16(hw, port, XM_STAT_CMD,
1391 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1392 /* Clear two times according to Errata #3 */
1393 xm_write16(hw, port, XM_STAT_CMD,
1394 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1395
45bada65
SH		 1396 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1397 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1398
1399 /* We don't need the FCS appended to the packet. */
1400 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1401 if (jumbo)
1402 r |= XM_RX_BIG_PK_OK;
89bf5f23 1403
45bada65 1404 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1405 /*
45bada65
SH		 1406 * If in manual half duplex mode the other side might be in
1407 * full duplex mode, so ignore if a carrier extension is not seen
1408 * on frames received
89bf5f23 1409 */
45bada65 1410 r |= XM_RX_DIS_CEXT;
baef58b1 1411 }
45bada65 1412 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1413
baef58b1
SH		 1414
1415 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1416 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1417
1418 /*
1419 * Bump up the transmit threshold. This helps hold off transmit
1420 * underruns when we're blasting traffic from both ports at once.
1421 */
1422 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1423
1424 /*
1425 * Enable the reception of all error frames. This is is
1426 * a necessary evil due to the design of the XMAC. The
1427 * XMAC's receive FIFO is only 8K in size, however jumbo
1428 * frames can be up to 9000 bytes in length. When bad
1429 * frame filtering is enabled, the XMAC's RX FIFO operates
1430 * in 'store and forward' mode. For this to work, the
1431 * entire frame has to fit into the FIFO, but that means
1432 * that jumbo frames larger than 8192 bytes will be
1433 * truncated. Disabling all bad frame filtering causes
1434 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1435 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1436 * RX FIFO as soon as the FIFO threshold is reached.
1437 */
45bada65 1438 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1439
baef58b1
SH		 1440
1441 /*
45bada65
SH		 1442 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1443 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1444 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1445 */
45bada65
SH		 1446 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1447
1448 /*
1449 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1450 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1451 * and 'Octets Tx OK Hi Cnt Ov'.
1452 */
1453 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1454
1455 /* Configure MAC arbiter */
1456 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1457
1458 /* configure timeout values */
1459 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1460 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1461 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1462 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1463
1464 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1465 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1466 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1467 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1468
1469 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1470 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1471 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1472 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1473
1474 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1475 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1476 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1477 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1478
45bada65 1479 if (jumbo) {
baef58b1 1480 /* Enable frame flushing if jumbo frames used */
6b0c1480 1481 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1482 } else {
1483 /* enable timeout timers if normal frames */
1484 skge_write16(hw, B3_PA_CTRL,
45bada65 1485 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1486 }
baef58b1
SH		 1487}
1488
1489static void genesis_stop(struct skge_port *skge)
1490{
1491 struct skge_hw *hw = skge->hw;
1492 int port = skge->port;
89bf5f23 1493 u32 reg;
baef58b1 1494
46a60f2d
SH		 1495 genesis_reset(hw, port);
1496
baef58b1
SH		 1497 /* Clear Tx packet arbiter timeout IRQ */
1498 skge_write16(hw, B3_PA_CTRL,
1499 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1500
1501 /*
8f3f8193 1502 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1503 * terminate if we don't flush the XMAC's transmit FIFO !
1504 */
6b0c1480
SH		 1505 xm_write32(hw, port, XM_MODE,
1506 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1507
1508
1509 /* Reset the MAC */
6b0c1480 1510 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1511
1512 /* For external PHYs there must be special handling */
64f6b64d
SH		 1513 if (hw->phy_type != SK_PHY_XMAC) {
1514 reg = skge_read32(hw, B2_GP_IO);
1515 if (port == 0) {
1516 reg |= GP_DIR_0;
1517 reg &= ~GP_IO_0;
1518 } else {
1519 reg |= GP_DIR_2;
1520 reg &= ~GP_IO_2;
1521 }
1522 skge_write32(hw, B2_GP_IO, reg);
1523 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1524 }
1525
6b0c1480
SH		 1526 xm_write16(hw, port, XM_MMU_CMD,
1527 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1528 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1529
6b0c1480 1530 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1531}
1532
1533
1534static void genesis_get_stats(struct skge_port *skge, u64 *data)
1535{
1536 struct skge_hw *hw = skge->hw;
1537 int port = skge->port;
1538 int i;
1539 unsigned long timeout = jiffies + HZ;
1540
6b0c1480 1541 xm_write16(hw, port,
baef58b1
SH		 1542 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1543
1544 /* wait for update to complete */
6b0c1480 1545 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1546 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1547 if (time_after(jiffies, timeout))
1548 break;
1549 udelay(10);
1550 }
1551
1552 /* special case for 64 bit octet counter */
6b0c1480
SH		 1553 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1554 | xm_read32(hw, port, XM_TXO_OK_LO);
1555 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1556 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1557
1558 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1559 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1560}
1561
1562static void genesis_mac_intr(struct skge_hw *hw, int port)
1563{
1564 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1565 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1566
7e676d91
SH		 1567 if (netif_msg_intr(skge))
1568 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1569 skge->netdev->name, status);
baef58b1
SH		 1570
1571 if (status & XM_IS_TXF_UR) {
6b0c1480 1572 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1573 ++skge->net_stats.tx_fifo_errors;
1574 }
1575 if (status & XM_IS_RXF_OV) {
6b0c1480 1576 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1577 ++skge->net_stats.rx_fifo_errors;
1578 }
1579}
1580
baef58b1
SH		 1581static void genesis_link_up(struct skge_port *skge)
1582{
1583 struct skge_hw *hw = skge->hw;
1584 int port = skge->port;
1585 u16 cmd;
64f6b64d 1586 u32 mode;
baef58b1 1587
6b0c1480 1588 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1589
1590 /*
1591 * enabling pause frame reception is required for 1000BT
1592 * because the XMAC is not reset if the link is going down
1593 */
1594 if (skge->flow_control == FLOW_MODE_NONE ||
1595 skge->flow_control == FLOW_MODE_LOC_SEND)
7e676d91 1596 /* Disable Pause Frame Reception */
baef58b1
SH		 1597 cmd |= XM_MMU_IGN_PF;
1598 else
1599 /* Enable Pause Frame Reception */
1600 cmd &= ~XM_MMU_IGN_PF;
1601
6b0c1480 1602 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1603
6b0c1480 1604 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1605 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1606 skge->flow_control == FLOW_MODE_LOC_SEND) {
1607 /*
1608 * Configure Pause Frame Generation
1609 * Use internal and external Pause Frame Generation.
1610 * Sending pause frames is edge triggered.
1611 * Send a Pause frame with the maximum pause time if
1612 * internal oder external FIFO full condition occurs.
1613 * Send a zero pause time frame to re-start transmission.
1614 */
1615 /* XM_PAUSE_DA = '010000C28001' (default) */
1616 /* XM_MAC_PTIME = 0xffff (maximum) */
1617 /* remember this value is defined in big endian (!) */
6b0c1480 1618 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1619
1620 mode |= XM_PAUSE_MODE;
6b0c1480 1621 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1622 } else {
1623 /*
1624 * disable pause frame generation is required for 1000BT
1625 * because the XMAC is not reset if the link is going down
1626 */
1627 /* Disable Pause Mode in Mode Register */
1628 mode &= ~XM_PAUSE_MODE;
1629
6b0c1480 1630 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1631 }
1632
6b0c1480 1633 xm_write32(hw, port, XM_MODE, mode);
64f6b64d 1634 xm_write16(hw, port, XM_IMSK, XM_DEF_MSK);
6b0c1480 1635 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1636
1637 /* get MMU Command Reg. */
6b0c1480 1638 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1639 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1640 cmd |= XM_MMU_GMII_FD;
1641
89bf5f23
SH		 1642 /*
1643 * Workaround BCOM Errata (#10523) for all BCom Phys
1644 * Enable Power Management after link up
1645 */
64f6b64d
SH		 1646 if (hw->phy_type == SK_PHY_BCOM) {
1647 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1648 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1649 & ~PHY_B_AC_DIS_PM);
1650 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1651 }
baef58b1
SH		 1652
1653 /* enable Rx/Tx */
6b0c1480 1654 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1655 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1656 skge_link_up(skge);
1657}
1658
1659
45bada65 1660static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1661{
1662 struct skge_hw *hw = skge->hw;
1663 int port = skge->port;
45bada65
SH		 1664 u16 isrc;
1665
1666 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1667 if (netif_msg_intr(skge))
1668 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1669 skge->netdev->name, isrc);
baef58b1 1670
45bada65
SH		 1671 if (isrc & PHY_B_IS_PSE)
1672 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1673 hw->dev[port]->name);
baef58b1
SH		 1674
1675 /* Workaround BCom Errata:
1676 * enable and disable loopback mode if "NO HCD" occurs.
1677 */
45bada65 1678 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1679 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1680 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1681 ctrl | PHY_CT_LOOP);
6b0c1480 1682 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1683 ctrl & ~PHY_CT_LOOP);
1684 }
1685
45bada65
SH		 1686 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1687 bcom_check_link(hw, port);
baef58b1 1688
baef58b1
SH		 1689}
1690
2cd8e5d3
SH		 1691static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1692{
1693 int i;
1694
1695 gma_write16(hw, port, GM_SMI_DATA, val);
1696 gma_write16(hw, port, GM_SMI_CTRL,
1697 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1698 for (i = 0; i < PHY_RETRIES; i++) {
1699 udelay(1);
1700
1701 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1702 return 0;
1703 }
1704
1705 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1706 hw->dev[port]->name);
1707 return -EIO;
1708}
1709
1710static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1711{
1712 int i;
1713
1714 gma_write16(hw, port, GM_SMI_CTRL,
1715 GM_SMI_CT_PHY_AD(hw->phy_addr)
1716 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1717
1718 for (i = 0; i < PHY_RETRIES; i++) {
1719 udelay(1);
1720 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1721 goto ready;
1722 }
1723
1724 return -ETIMEDOUT;
1725 ready:
1726 *val = gma_read16(hw, port, GM_SMI_DATA);
1727 return 0;
1728}
1729
1730static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1731{
1732 u16 v = 0;
1733 if (__gm_phy_read(hw, port, reg, &v))
1734 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1735 hw->dev[port]->name);
1736 return v;
1737}
1738
8f3f8193 1739/* Marvell Phy Initialization */
baef58b1
SH		 1740static void yukon_init(struct skge_hw *hw, int port)
1741{
1742 struct skge_port *skge = netdev_priv(hw->dev[port]);
1743 u16 ctrl, ct1000, adv;
baef58b1 1744
baef58b1 1745 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1746 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1747
1748 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1749 PHY_M_EC_MAC_S_MSK);
1750 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1751
c506a509 1752 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1753
6b0c1480 1754 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1755 }
1756
6b0c1480 1757 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1758 if (skge->autoneg == AUTONEG_DISABLE)
1759 ctrl &= ~PHY_CT_ANE;
1760
1761 ctrl |= PHY_CT_RESET;
6b0c1480 1762 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1763
1764 ctrl = 0;
1765 ct1000 = 0;
b18f2091 1766 adv = PHY_AN_CSMA;
baef58b1
SH		 1767
1768 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1769 if (hw->copper) {
baef58b1
SH		 1770 if (skge->advertising & ADVERTISED_1000baseT_Full)
1771 ct1000 |= PHY_M_1000C_AFD;
1772 if (skge->advertising & ADVERTISED_1000baseT_Half)
1773 ct1000 |= PHY_M_1000C_AHD;
1774 if (skge->advertising & ADVERTISED_100baseT_Full)
1775 adv |= PHY_M_AN_100_FD;
1776 if (skge->advertising & ADVERTISED_100baseT_Half)
1777 adv |= PHY_M_AN_100_HD;
1778 if (skge->advertising & ADVERTISED_10baseT_Full)
1779 adv |= PHY_M_AN_10_FD;
1780 if (skge->advertising & ADVERTISED_10baseT_Half)
1781 adv |= PHY_M_AN_10_HD;
45bada65 1782 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1783 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1784
45bada65
SH		 1785 /* Set Flow-control capabilities */
1786 adv |= phy_pause_map[skge->flow_control];
1787
baef58b1
SH		 1788 /* Restart Auto-negotiation */
1789 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1790 } else {
1791 /* forced speed/duplex settings */
1792 ct1000 = PHY_M_1000C_MSE;
1793
1794 if (skge->duplex == DUPLEX_FULL)
1795 ctrl |= PHY_CT_DUP_MD;
1796
1797 switch (skge->speed) {
1798 case SPEED_1000:
1799 ctrl |= PHY_CT_SP1000;
1800 break;
1801 case SPEED_100:
1802 ctrl |= PHY_CT_SP100;
1803 break;
1804 }
1805
1806 ctrl |= PHY_CT_RESET;
1807 }
1808
c506a509 1809 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1810
6b0c1480
SH		 1811 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1812 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1813
baef58b1
SH		 1814 /* Enable phy interrupt on autonegotiation complete (or link up) */
1815 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1816 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1817 else
4cde06ed 1818 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1819}
1820
1821static void yukon_reset(struct skge_hw *hw, int port)
1822{
6b0c1480
SH		 1823 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1824 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1825 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1826 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1827 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1828
6b0c1480
SH		 1829 gma_write16(hw, port, GM_RX_CTRL,
1830 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1831 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1832}
1833
c8868611
SH		 1834/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1835static int is_yukon_lite_a0(struct skge_hw *hw)
1836{
1837 u32 reg;
1838 int ret;
1839
1840 if (hw->chip_id != CHIP_ID_YUKON)
1841 return 0;
1842
1843 reg = skge_read32(hw, B2_FAR);
1844 skge_write8(hw, B2_FAR + 3, 0xff);
1845 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1846 skge_write32(hw, B2_FAR, reg);
1847 return ret;
1848}
1849
baef58b1
SH		 1850static void yukon_mac_init(struct skge_hw *hw, int port)
1851{
1852 struct skge_port *skge = netdev_priv(hw->dev[port]);
1853 int i;
1854 u32 reg;
1855 const u8 *addr = hw->dev[port]->dev_addr;
1856
1857 /* WA code for COMA mode -- set PHY reset */
1858 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1859 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1860 reg = skge_read32(hw, B2_GP_IO);
1861 reg |= GP_DIR_9 | GP_IO_9;
1862 skge_write32(hw, B2_GP_IO, reg);
1863 }
baef58b1
SH		 1864
1865 /* hard reset */
6b0c1480
SH		 1866 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1867 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1868
1869 /* WA code for COMA mode -- clear PHY reset */
1870 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1871 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1872 reg = skge_read32(hw, B2_GP_IO);
1873 reg |= GP_DIR_9;
1874 reg &= ~GP_IO_9;
1875 skge_write32(hw, B2_GP_IO, reg);
1876 }
baef58b1
SH		 1877
1878 /* Set hardware config mode */
1879 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1880 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 1881 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 1882
1883 /* Clear GMC reset */
6b0c1480
SH		 1884 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1885 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1886 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 1887
baef58b1
SH		 1888 if (skge->autoneg == AUTONEG_DISABLE) {
1889 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1890 gma_write16(hw, port, GM_GP_CTRL,
1891 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1892
1893 switch (skge->speed) {
1894 case SPEED_1000:
564f9abb 1895 reg &= ~GM_GPCR_SPEED_100;
baef58b1 1896 reg |= GM_GPCR_SPEED_1000;
564f9abb 1897 break;
baef58b1 1898 case SPEED_100:
564f9abb 1899 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 1900 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 1901 break;
1902 case SPEED_10:
1903 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1904 break;
baef58b1
SH		 1905 }
1906
1907 if (skge->duplex == DUPLEX_FULL)
1908 reg |= GM_GPCR_DUP_FULL;
1909 } else
1910 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 1911
baef58b1
SH		 1912 switch (skge->flow_control) {
1913 case FLOW_MODE_NONE:
6b0c1480 1914 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1915 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1916 break;
1917 case FLOW_MODE_LOC_SEND:
1918 /* disable Rx flow-control */
1919 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1920 }
1921
6b0c1480 1922 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 1923 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1924
baef58b1 1925 yukon_init(hw, port);
baef58b1
SH		 1926
1927 /* MIB clear */
6b0c1480
SH		 1928 reg = gma_read16(hw, port, GM_PHY_ADDR);
1929 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1930
1931 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1932 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1933 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1934
1935 /* transmit control */
6b0c1480 1936 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1937
1938 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1939 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1940 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1941
1942 /* transmit flow control */
6b0c1480 1943 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1944
1945 /* transmit parameter */
6b0c1480 1946 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1947 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1948 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1949 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1950
1951 /* serial mode register */
1952 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1953 if (hw->dev[port]->mtu > 1500)
1954 reg |= GM_SMOD_JUMBO_ENA;
1955
6b0c1480 1956 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1957
1958 /* physical address: used for pause frames */
6b0c1480 1959 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1960 /* virtual address for data */
6b0c1480 1961 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1962
1963 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1964 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1965 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1966 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1967
1968 /* Initialize Mac Fifo */
1969
1970 /* Configure Rx MAC FIFO */
6b0c1480 1971 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 1972 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 1973
1974 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1975 if (is_yukon_lite_a0(hw))
baef58b1 1976 reg &= ~GMF_RX_F_FL_ON;
c8868611 1977
6b0c1480
SH		 1978 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1979 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 1980 /*
1981 * because Pause Packet Truncation in GMAC is not working
1982 * we have to increase the Flush Threshold to 64 bytes
1983 * in order to flush pause packets in Rx FIFO on Yukon-1
1984 */
1985 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 1986
1987 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1988 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1989 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1990}
1991
355ec572
SH		 1992/* Go into power down mode */
1993static void yukon_suspend(struct skge_hw *hw, int port)
1994{
1995 u16 ctrl;
1996
1997 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1998 ctrl |= PHY_M_PC_POL_R_DIS;
1999 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2000
2001 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2002 ctrl |= PHY_CT_RESET;
2003 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2004
2005 /* switch IEEE compatible power down mode on */
2006 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2007 ctrl |= PHY_CT_PDOWN;
2008 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2009}
2010
baef58b1
SH		 2011static void yukon_stop(struct skge_port *skge)
2012{
2013 struct skge_hw *hw = skge->hw;
2014 int port = skge->port;
2015
46a60f2d
SH		 2016 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2017 yukon_reset(hw, port);
baef58b1 2018
6b0c1480
SH		 2019 gma_write16(hw, port, GM_GP_CTRL,
2020 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2021 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2022 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2023
355ec572 2024 yukon_suspend(hw, port);
46a60f2d 2025
baef58b1 2026 /* set GPHY Control reset */
46a60f2d
SH		 2027 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2028 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2029}
2030
2031static void yukon_get_stats(struct skge_port *skge, u64 *data)
2032{
2033 struct skge_hw *hw = skge->hw;
2034 int port = skge->port;
2035 int i;
2036
6b0c1480
SH		 2037 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2038 | gma_read32(hw, port, GM_TXO_OK_LO);
2039 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2040 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2041
2042 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2043 data[i] = gma_read32(hw, port,
baef58b1
SH		 2044 skge_stats[i].gma_offset);
2045}
2046
2047static void yukon_mac_intr(struct skge_hw *hw, int port)
2048{
7e676d91
SH		 2049 struct net_device *dev = hw->dev[port];
2050 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2051 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2052
7e676d91
SH		 2053 if (netif_msg_intr(skge))
2054 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2055 dev->name, status);
2056
baef58b1
SH		 2057 if (status & GM_IS_RX_FF_OR) {
2058 ++skge->net_stats.rx_fifo_errors;
d8a09943 2059 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2060 }
d8a09943 2061
baef58b1
SH		 2062 if (status & GM_IS_TX_FF_UR) {
2063 ++skge->net_stats.tx_fifo_errors;
d8a09943 2064 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2065 }
2066
2067}
2068
2069static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2070{
95566065 2071 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2072 case PHY_M_PS_SPEED_1000:
2073 return SPEED_1000;
2074 case PHY_M_PS_SPEED_100:
2075 return SPEED_100;
2076 default:
2077 return SPEED_10;
2078 }
2079}
2080
2081static void yukon_link_up(struct skge_port *skge)
2082{
2083 struct skge_hw *hw = skge->hw;
2084 int port = skge->port;
2085 u16 reg;
2086
baef58b1 2087 /* Enable Transmit FIFO Underrun */
46a60f2d 2088 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2089
6b0c1480 2090 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2091 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2092 reg |= GM_GPCR_DUP_FULL;
2093
2094 /* enable Rx/Tx */
2095 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2096 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2097
4cde06ed 2098 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2099 skge_link_up(skge);
2100}
2101
2102static void yukon_link_down(struct skge_port *skge)
2103{
2104 struct skge_hw *hw = skge->hw;
2105 int port = skge->port;
d8a09943 2106 u16 ctrl;
baef58b1 2107
6b0c1480 2108 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
d8a09943
SH		 2109
2110 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2111 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2112 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2113
c506a509 2114 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 2115 /* restore Asymmetric Pause bit */
6b0c1480
SH		 2116 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
2117 gm_phy_read(hw, port,
baef58b1
SH		 2118 PHY_MARV_AUNE_ADV)
2119 | PHY_M_AN_ASP);
2120
2121 }
2122
2123 yukon_reset(hw, port);
2124 skge_link_down(skge);
2125
2126 yukon_init(hw, port);
2127}
2128
2129static void yukon_phy_intr(struct skge_port *skge)
2130{
2131 struct skge_hw *hw = skge->hw;
2132 int port = skge->port;
2133 const char *reason = NULL;
2134 u16 istatus, phystat;
2135
6b0c1480
SH		 2136 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2137 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 2138
2139 if (netif_msg_intr(skge))
2140 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2141 skge->netdev->name, istatus, phystat);
baef58b1
SH		 2142
2143 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2144 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2145 & PHY_M_AN_RF) {
2146 reason = "remote fault";
2147 goto failed;
2148 }
2149
c506a509 2150 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2151 reason = "master/slave fault";
2152 goto failed;
2153 }
2154
2155 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2156 reason = "speed/duplex";
2157 goto failed;
2158 }
2159
2160 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2161 ? DUPLEX_FULL : DUPLEX_HALF;
2162 skge->speed = yukon_speed(hw, phystat);
2163
baef58b1
SH		 2164 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2165 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2166 case PHY_M_PS_PAUSE_MSK:
2167 skge->flow_control = FLOW_MODE_SYMMETRIC;
2168 break;
2169 case PHY_M_PS_RX_P_EN:
2170 skge->flow_control = FLOW_MODE_REM_SEND;
2171 break;
2172 case PHY_M_PS_TX_P_EN:
2173 skge->flow_control = FLOW_MODE_LOC_SEND;
2174 break;
2175 default:
2176 skge->flow_control = FLOW_MODE_NONE;
2177 }
2178
2179 if (skge->flow_control == FLOW_MODE_NONE ||
2180 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2181 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2182 else
6b0c1480 2183 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2184 yukon_link_up(skge);
2185 return;
2186 }
2187
2188 if (istatus & PHY_M_IS_LSP_CHANGE)
2189 skge->speed = yukon_speed(hw, phystat);
2190
2191 if (istatus & PHY_M_IS_DUP_CHANGE)
2192 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2193 if (istatus & PHY_M_IS_LST_CHANGE) {
2194 if (phystat & PHY_M_PS_LINK_UP)
2195 yukon_link_up(skge);
2196 else
2197 yukon_link_down(skge);
2198 }
2199 return;
2200 failed:
2201 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2202 skge->netdev->name, reason);
2203
2204 /* XXX restart autonegotiation? */
2205}
2206
ee294dcd
SH		 2207static void skge_phy_reset(struct skge_port *skge)
2208{
2209 struct skge_hw *hw = skge->hw;
2210 int port = skge->port;
2211
2212 netif_stop_queue(skge->netdev);
2213 netif_carrier_off(skge->netdev);
2214
d85b514f 2215 mutex_lock(&hw->phy_mutex);
ee294dcd
SH		 2216 if (hw->chip_id == CHIP_ID_GENESIS) {
2217 genesis_reset(hw, port);
2218 genesis_mac_init(hw, port);
2219 } else {
2220 yukon_reset(hw, port);
2221 yukon_init(hw, port);
2222 }
d85b514f 2223 mutex_unlock(&hw->phy_mutex);
ee294dcd
SH		 2224}
2225
2cd8e5d3
SH		 2226/* Basic MII support */
2227static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2228{
2229 struct mii_ioctl_data *data = if_mii(ifr);
2230 struct skge_port *skge = netdev_priv(dev);
2231 struct skge_hw *hw = skge->hw;
2232 int err = -EOPNOTSUPP;
2233
2234 if (!netif_running(dev))
2235 return -ENODEV; /* Phy still in reset */
2236
2237 switch(cmd) {
2238 case SIOCGMIIPHY:
2239 data->phy_id = hw->phy_addr;
2240
2241 /* fallthru */
2242 case SIOCGMIIREG: {
2243 u16 val = 0;
d85b514f 2244 mutex_lock(&hw->phy_mutex);
2cd8e5d3
SH		 2245 if (hw->chip_id == CHIP_ID_GENESIS)
2246 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2247 else
2248 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
d85b514f 2249 mutex_unlock(&hw->phy_mutex);
2cd8e5d3
SH		 2250 data->val_out = val;
2251 break;
2252 }
2253
2254 case SIOCSMIIREG:
2255 if (!capable(CAP_NET_ADMIN))
2256 return -EPERM;
2257
d85b514f 2258 mutex_lock(&hw->phy_mutex);
2cd8e5d3
SH		 2259 if (hw->chip_id == CHIP_ID_GENESIS)
2260 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2261 data->val_in);
2262 else
2263 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2264 data->val_in);
d85b514f 2265 mutex_unlock(&hw->phy_mutex);
2cd8e5d3
SH		 2266 break;
2267 }
2268 return err;
2269}
2270
baef58b1
SH		 2271static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2272{
2273 u32 end;
2274
2275 start /= 8;
2276 len /= 8;
2277 end = start + len - 1;
2278
2279 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2280 skge_write32(hw, RB_ADDR(q, RB_START), start);
2281 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2282 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2283 skge_write32(hw, RB_ADDR(q, RB_END), end);
2284
2285 if (q == Q_R1 || q == Q_R2) {
2286 /* Set thresholds on receive queue's */
2287 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2288 start + (2*len)/3);
2289 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2290 start + (len/3));
2291 } else {
2292 /* Enable store & forward on Tx queue's because
2293 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2294 */
2295 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2296 }
2297
2298 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2299}
2300
2301/* Setup Bus Memory Interface */
2302static void skge_qset(struct skge_port *skge, u16 q,
2303 const struct skge_element *e)
2304{
2305 struct skge_hw *hw = skge->hw;
2306 u32 watermark = 0x600;
2307 u64 base = skge->dma + (e->desc - skge->mem);
2308
2309 /* optimization to reduce window on 32bit/33mhz */
2310 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2311 watermark /= 2;
2312
2313 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2314 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2315 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2316 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2317}
2318
2319static int skge_up(struct net_device *dev)
2320{
2321 struct skge_port *skge = netdev_priv(dev);
2322 struct skge_hw *hw = skge->hw;
2323 int port = skge->port;
2324 u32 chunk, ram_addr;
2325 size_t rx_size, tx_size;
2326 int err;
2327
2328 if (netif_msg_ifup(skge))
2329 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2330
19a33d4e 2331 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2332 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2333 else
2334 skge->rx_buf_size = RX_BUF_SIZE;
2335
2336
baef58b1
SH		 2337 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2338 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2339 skge->mem_size = tx_size + rx_size;
2340 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2341 if (!skge->mem)
2342 return -ENOMEM;
2343
c3da1447
SH		 2344 BUG_ON(skge->dma & 7);
2345
2346 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2347 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2348 err = -EINVAL;
2349 goto free_pci_mem;
2350 }
2351
baef58b1
SH		 2352 memset(skge->mem, 0, skge->mem_size);
2353
203babb6
SH		 2354 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2355 if (err)
baef58b1
SH		 2356 goto free_pci_mem;
2357
c54f9765 2358 err = skge_rx_fill(dev);
19a33d4e 2359 if (err)
baef58b1
SH		 2360 goto free_rx_ring;
2361
203babb6
SH		 2362 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2363 skge->dma + rx_size);
2364 if (err)
baef58b1
SH		 2365 goto free_rx_ring;
2366
8f3f8193 2367 /* Initialize MAC */
d85b514f 2368 mutex_lock(&hw->phy_mutex);
baef58b1
SH		 2369 if (hw->chip_id == CHIP_ID_GENESIS)
2370 genesis_mac_init(hw, port);
2371 else
2372 yukon_mac_init(hw, port);
d85b514f 2373 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 2374
2375 /* Configure RAMbuffers */
981d0377 2376 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2377 ram_addr = hw->ram_offset + 2 * chunk * port;
2378
2379 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2380 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2381
2382 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2383 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2384 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2385
2386 /* Start receiver BMU */
2387 wmb();
2388 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2389 skge_led(skge, LED_MODE_ON);
baef58b1 2390
239e44e1 2391 netif_poll_enable(dev);
baef58b1
SH		 2392 return 0;
2393
2394 free_rx_ring:
2395 skge_rx_clean(skge);
2396 kfree(skge->rx_ring.start);
2397 free_pci_mem:
2398 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2399 skge->mem = NULL;
baef58b1
SH		 2400
2401 return err;
2402}
2403
2404static int skge_down(struct net_device *dev)
2405{
2406 struct skge_port *skge = netdev_priv(dev);
2407 struct skge_hw *hw = skge->hw;
2408 int port = skge->port;
2409
7731a4ea
SH		 2410 if (skge->mem == NULL)
2411 return 0;
2412
baef58b1
SH		 2413 if (netif_msg_ifdown(skge))
2414 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2415
2416 netif_stop_queue(dev);
64f6b64d
SH		 2417 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2418 cancel_rearming_delayed_work(&skge->link_thread);
baef58b1 2419
46a60f2d
SH		 2420 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2421 if (hw->chip_id == CHIP_ID_GENESIS)
2422 genesis_stop(skge);
2423 else
2424 yukon_stop(skge);
2425
baef58b1
SH		 2426 /* Stop transmitter */
2427 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2428 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2429 RB_RST_SET|RB_DIS_OP_MD);
2430
baef58b1
SH		 2431
2432 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2433 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2434 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2435
2436 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2437 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2438 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2439
2440 /* Reset PCI FIFO */
2441 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2442 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2443
2444 /* Reset the RAM Buffer async Tx queue */
2445 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2446 /* stop receiver */
2447 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2448 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2449 RB_RST_SET|RB_DIS_OP_MD);
2450 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2451
2452 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2453 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2454 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2455 } else {
6b0c1480
SH		 2456 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2457 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2458 }
2459
6abebb53 2460 skge_led(skge, LED_MODE_OFF);
baef58b1 2461
239e44e1 2462 netif_poll_disable(dev);
513f533e 2463 skge_tx_clean(dev);
baef58b1
SH		 2464 skge_rx_clean(skge);
2465
2466 kfree(skge->rx_ring.start);
2467 kfree(skge->tx_ring.start);
2468 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2469 skge->mem = NULL;
baef58b1
SH		 2470 return 0;
2471}
2472
29b4e886
SH		 2473static inline int skge_avail(const struct skge_ring *ring)
2474{
2475 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2476 + (ring->to_clean - ring->to_use) - 1;
2477}
2478
baef58b1
SH		 2479static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2480{
2481 struct skge_port *skge = netdev_priv(dev);
2482 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2483 struct skge_element *e;
2484 struct skge_tx_desc *td;
2485 int i;
2486 u32 control, len;
2487 u64 map;
baef58b1 2488
5b057c6b 2489 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2490 return NETDEV_TX_OK;
2491
513f533e 2492 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2493 return NETDEV_TX_BUSY;
baef58b1 2494
7c442fa1 2495 e = skge->tx_ring.to_use;
baef58b1 2496 td = e->desc;
7c442fa1 2497 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2498 e->skb = skb;
2499 len = skb_headlen(skb);
2500 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2501 pci_unmap_addr_set(e, mapaddr, map);
2502 pci_unmap_len_set(e, maplen, len);
2503
2504 td->dma_lo = map;
2505 td->dma_hi = map >> 32;
2506
84fa7933 2507 if (skb->ip_summed == CHECKSUM_PARTIAL) {
baef58b1
SH		 2508 int offset = skb->h.raw - skb->data;
2509
2510 /* This seems backwards, but it is what the sk98lin
2511 * does. Looks like hardware is wrong?
2512 */
ea182d4a 2513 if (skb->h.ipiph->protocol == IPPROTO_UDP
981d0377 2514 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2515 control = BMU_TCP_CHECK;
2516 else
2517 control = BMU_UDP_CHECK;
2518
2519 td->csum_offs = 0;
2520 td->csum_start = offset;
2521 td->csum_write = offset + skb->csum;
2522 } else
2523 control = BMU_CHECK;
2524
2525 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2526 control |= BMU_EOF| BMU_IRQ_EOF;
2527 else {
2528 struct skge_tx_desc *tf = td;
2529
2530 control |= BMU_STFWD;
2531 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2532 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2533
2534 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2535 frag->size, PCI_DMA_TODEVICE);
2536
2537 e = e->next;
7c442fa1 2538 e->skb = skb;
baef58b1 2539 tf = e->desc;
7c442fa1
SH		 2540 BUG_ON(tf->control & BMU_OWN);
2541
baef58b1
SH		 2542 tf->dma_lo = map;
2543 tf->dma_hi = (u64) map >> 32;
2544 pci_unmap_addr_set(e, mapaddr, map);
2545 pci_unmap_len_set(e, maplen, frag->size);
2546
2547 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2548 }
2549 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2550 }
2551 /* Make sure all the descriptors written */
2552 wmb();
2553 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2554 wmb();
2555
2556 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2557
7c442fa1 2558 if (unlikely(netif_msg_tx_queued(skge)))
0b2d7fea 2559 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
7c442fa1 2560 dev->name, e - skge->tx_ring.start, skb->len);
baef58b1 2561
7c442fa1 2562 skge->tx_ring.to_use = e->next;
9db96479 2563 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
baef58b1
SH		 2564 pr_debug("%s: transmit queue full\n", dev->name);
2565 netif_stop_queue(dev);
2566 }
2567
c68ce71a
SH		 2568 dev->trans_start = jiffies;
2569
baef58b1
SH		 2570 return NETDEV_TX_OK;
2571}
2572
7c442fa1
SH		 2573
2574/* Free resources associated with this reing element */
2575static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2576 u32 control)
866b4f3e
SH		 2577{
2578 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2579
7c442fa1 2580 BUG_ON(!e->skb);
866b4f3e 2581
7c442fa1
SH		 2582 /* skb header vs. fragment */
2583 if (control & BMU_STF)
866b4f3e 2584 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
7c442fa1
SH		 2585 pci_unmap_len(e, maplen),
2586 PCI_DMA_TODEVICE);
2587 else
2588 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2589 pci_unmap_len(e, maplen),
2590 PCI_DMA_TODEVICE);
866b4f3e 2591
7c442fa1
SH		 2592 if (control & BMU_EOF) {
2593 if (unlikely(netif_msg_tx_done(skge)))
2594 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2595 skge->netdev->name, e - skge->tx_ring.start);
866b4f3e 2596
513f533e 2597 dev_kfree_skb(e->skb);
baef58b1 2598 }
7c442fa1 2599 e->skb = NULL;
baef58b1
SH		 2600}
2601
7c442fa1 2602/* Free all buffers in transmit ring */
513f533e 2603static void skge_tx_clean(struct net_device *dev)
baef58b1 2604{
513f533e 2605 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2606 struct skge_element *e;
baef58b1 2607
513f533e 2608 netif_tx_lock_bh(dev);
7c442fa1
SH		 2609 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2610 struct skge_tx_desc *td = e->desc;
2611 skge_tx_free(skge, e, td->control);
2612 td->control = 0;
2613 }
2614
2615 skge->tx_ring.to_clean = e;
513f533e
SH		 2616 netif_wake_queue(dev);
2617 netif_tx_unlock_bh(dev);
baef58b1
SH		 2618}
2619
2620static void skge_tx_timeout(struct net_device *dev)
2621{
2622 struct skge_port *skge = netdev_priv(dev);
2623
2624 if (netif_msg_timer(skge))
2625 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2626
2627 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2628 skge_tx_clean(dev);
baef58b1
SH		 2629}
2630
2631static int skge_change_mtu(struct net_device *dev, int new_mtu)
2632{
7731a4ea 2633 int err;
baef58b1 2634
95566065 2635 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2636 return -EINVAL;
2637
7731a4ea
SH		 2638 if (!netif_running(dev)) {
2639 dev->mtu = new_mtu;
2640 return 0;
2641 }
2642
2643 skge_down(dev);
baef58b1 2644
19a33d4e 2645 dev->mtu = new_mtu;
7731a4ea
SH		 2646
2647 err = skge_up(dev);
2648 if (err)
2649 dev_close(dev);
baef58b1
SH		 2650
2651 return err;
2652}
2653
2654static void genesis_set_multicast(struct net_device *dev)
2655{
2656 struct skge_port *skge = netdev_priv(dev);
2657 struct skge_hw *hw = skge->hw;
2658 int port = skge->port;
2659 int i, count = dev->mc_count;
2660 struct dev_mc_list *list = dev->mc_list;
2661 u32 mode;
2662 u8 filter[8];
2663
6b0c1480 2664 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2665 mode |= XM_MD_ENA_HASH;
2666 if (dev->flags & IFF_PROMISC)
2667 mode |= XM_MD_ENA_PROM;
2668 else
2669 mode &= ~XM_MD_ENA_PROM;
2670
2671 if (dev->flags & IFF_ALLMULTI)
2672 memset(filter, 0xff, sizeof(filter));
2673 else {
2674 memset(filter, 0, sizeof(filter));
95566065 2675 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2676 u32 crc, bit;
2677 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2678 bit = ~crc & 0x3f;
baef58b1
SH		 2679 filter[bit/8] |= 1 << (bit%8);
2680 }
2681 }
2682
6b0c1480 2683 xm_write32(hw, port, XM_MODE, mode);
45bada65 2684 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2685}
2686
2687static void yukon_set_multicast(struct net_device *dev)
2688{
2689 struct skge_port *skge = netdev_priv(dev);
2690 struct skge_hw *hw = skge->hw;
2691 int port = skge->port;
2692 struct dev_mc_list *list = dev->mc_list;
2693 u16 reg;
2694 u8 filter[8];
2695
2696 memset(filter, 0, sizeof(filter));
2697
6b0c1480 2698 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2699 reg |= GM_RXCR_UCF_ENA;
2700
8f3f8193 2701 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2702 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2703 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2704 memset(filter, 0xff, sizeof(filter));
2705 else if (dev->mc_count == 0) /* no multicast */
2706 reg &= ~GM_RXCR_MCF_ENA;
2707 else {
2708 int i;
2709 reg |= GM_RXCR_MCF_ENA;
2710
95566065 2711 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2712 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2713 filter[bit/8] |= 1 << (bit%8);
2714 }
2715 }
2716
2717
6b0c1480 2718 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2719 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2720 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2721 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2722 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2723 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2724 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2725 (u16)filter[6] | ((u16)filter[7] << 8));
2726
6b0c1480 2727 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2728}
2729
383181ac
SH		 2730static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2731{
2732 if (hw->chip_id == CHIP_ID_GENESIS)
2733 return status >> XMR_FS_LEN_SHIFT;
2734 else
2735 return status >> GMR_FS_LEN_SHIFT;
2736}
2737
baef58b1
SH		 2738static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2739{
2740 if (hw->chip_id == CHIP_ID_GENESIS)
2741 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2742 else
2743 return (status & GMR_FS_ANY_ERR) ||
2744 (status & GMR_FS_RX_OK) == 0;
2745}
2746
19a33d4e
SH		 2747
2748/* Get receive buffer from descriptor.
2749 * Handles copy of small buffers and reallocation failures
2750 */
c54f9765
SH		 2751static struct sk_buff *skge_rx_get(struct net_device *dev,
2752 struct skge_element *e,
2753 u32 control, u32 status, u16 csum)
19a33d4e 2754{
c54f9765 2755 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 2756 struct sk_buff *skb;
2757 u16 len = control & BMU_BBC;
2758
2759 if (unlikely(netif_msg_rx_status(skge)))
2760 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
c54f9765 2761 dev->name, e - skge->rx_ring.start,
383181ac
SH		 2762 status, len);
2763
2764 if (len > skge->rx_buf_size)
2765 goto error;
2766
2767 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2768 goto error;
2769
2770 if (bad_phy_status(skge->hw, status))
2771 goto error;
2772
2773 if (phy_length(skge->hw, status) != len)
2774 goto error;
19a33d4e
SH		 2775
2776 if (len < RX_COPY_THRESHOLD) {
c54f9765 2777 skb = netdev_alloc_skb(dev, len + 2);
383181ac
SH		 2778 if (!skb)
2779 goto resubmit;
19a33d4e 2780
383181ac 2781 skb_reserve(skb, 2);
19a33d4e
SH		 2782 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2783 pci_unmap_addr(e, mapaddr),
2784 len, PCI_DMA_FROMDEVICE);
383181ac 2785 memcpy(skb->data, e->skb->data, len);
19a33d4e
SH		 2786 pci_dma_sync_single_for_device(skge->hw->pdev,
2787 pci_unmap_addr(e, mapaddr),
2788 len, PCI_DMA_FROMDEVICE);
19a33d4e 2789 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 2790 } else {
383181ac 2791 struct sk_buff *nskb;
c54f9765 2792 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
383181ac
SH		 2793 if (!nskb)
2794 goto resubmit;
19a33d4e 2795
901ccefb 2796 skb_reserve(nskb, NET_IP_ALIGN);
19a33d4e
SH		 2797 pci_unmap_single(skge->hw->pdev,
2798 pci_unmap_addr(e, mapaddr),
2799 pci_unmap_len(e, maplen),
2800 PCI_DMA_FROMDEVICE);
2801 skb = e->skb;
383181ac 2802 prefetch(skb->data);
19a33d4e 2803 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 2804 }
383181ac
SH		 2805
2806 skb_put(skb, len);
383181ac
SH		 2807 if (skge->rx_csum) {
2808 skb->csum = csum;
84fa7933 2809 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 2810 }
2811
c54f9765 2812 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 2813
2814 return skb;
2815error:
2816
2817 if (netif_msg_rx_err(skge))
2818 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
c54f9765 2819 dev->name, e - skge->rx_ring.start,
383181ac
SH		 2820 control, status);
2821
2822 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2823 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2824 skge->net_stats.rx_length_errors++;
2825 if (status & XMR_FS_FRA_ERR)
2826 skge->net_stats.rx_frame_errors++;
2827 if (status & XMR_FS_FCS_ERR)
2828 skge->net_stats.rx_crc_errors++;
2829 } else {
2830 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2831 skge->net_stats.rx_length_errors++;
2832 if (status & GMR_FS_FRAGMENT)
2833 skge->net_stats.rx_frame_errors++;
2834 if (status & GMR_FS_CRC_ERR)
2835 skge->net_stats.rx_crc_errors++;
2836 }
2837
2838resubmit:
2839 skge_rx_reuse(e, skge->rx_buf_size);
2840 return NULL;
baef58b1
SH		 2841}
2842
7c442fa1 2843/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 2844static void skge_tx_done(struct net_device *dev)
00a6cae2 2845{
7c442fa1 2846 struct skge_port *skge = netdev_priv(dev);
00a6cae2 2847 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 2848 struct skge_element *e;
2849
513f533e 2850 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 2851
513f533e 2852 netif_tx_lock(dev);
866b4f3e 2853 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
00a6cae2 2854 struct skge_tx_desc *td = e->desc;
00a6cae2 2855
866b4f3e 2856 if (td->control & BMU_OWN)
00a6cae2
SH		 2857 break;
2858
7c442fa1 2859 skge_tx_free(skge, e, td->control);
00a6cae2 2860 }
7c442fa1 2861 skge->tx_ring.to_clean = e;
866b4f3e 2862
513f533e
SH		 2863 if (skge_avail(&skge->tx_ring) > TX_LOW_WATER)
2864 netif_wake_queue(dev);
00a6cae2 2865
513f533e 2866 netif_tx_unlock(dev);
00a6cae2 2867}
19a33d4e 2868
baef58b1
SH		 2869static int skge_poll(struct net_device *dev, int *budget)
2870{
2871 struct skge_port *skge = netdev_priv(dev);
2872 struct skge_hw *hw = skge->hw;
2873 struct skge_ring *ring = &skge->rx_ring;
2874 struct skge_element *e;
00a6cae2
SH		 2875 int to_do = min(dev->quota, *budget);
2876 int work_done = 0;
2877
513f533e
SH		 2878 skge_tx_done(dev);
2879
2880 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2881
1631aef1 2882 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 2883 struct skge_rx_desc *rd = e->desc;
19a33d4e 2884 struct sk_buff *skb;
383181ac 2885 u32 control;
baef58b1
SH		 2886
2887 rmb();
2888 control = rd->control;
2889 if (control & BMU_OWN)
2890 break;
2891
c54f9765 2892 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 2893 if (likely(skb)) {
19a33d4e
SH		 2894 dev->last_rx = jiffies;
2895 netif_receive_skb(skb);
baef58b1 2896
19a33d4e 2897 ++work_done;
5a011447 2898 }
baef58b1
SH		 2899 }
2900 ring->to_clean = e;
2901
baef58b1
SH		 2902 /* restart receiver */
2903 wmb();
a9cdab86 2904 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 2905
19a33d4e
SH		 2906 *budget -= work_done;
2907 dev->quota -= work_done;
2908
2909 if (work_done >= to_do)
2910 return 1; /* not done */
baef58b1 2911
7c442fa1 2912 spin_lock_irq(&hw->hw_lock);
513f533e
SH		 2913 __netif_rx_complete(dev);
2914 hw->intr_mask |= irqmask[skge->port];
80dd857d 2915 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 2916 skge_read32(hw, B0_IMSK);
7c442fa1 2917 spin_unlock_irq(&hw->hw_lock);
1631aef1 2918
19a33d4e 2919 return 0;
baef58b1
SH		 2920}
2921
f6620cab
SH		 2922/* Parity errors seem to happen when Genesis is connected to a switch
2923 * with no other ports present. Heartbeat error??
2924 */
baef58b1
SH		 2925static void skge_mac_parity(struct skge_hw *hw, int port)
2926{
f6620cab
SH		 2927 struct net_device *dev = hw->dev[port];
2928
2929 if (dev) {
2930 struct skge_port *skge = netdev_priv(dev);
2931 ++skge->net_stats.tx_heartbeat_errors;
2932 }
baef58b1
SH		 2933
2934 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2935 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2936 MFF_CLR_PERR);
2937 else
2938 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2939 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2940 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2941 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2942}
2943
baef58b1
SH		 2944static void skge_mac_intr(struct skge_hw *hw, int port)
2945{
95566065 2946 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2947 genesis_mac_intr(hw, port);
2948 else
2949 yukon_mac_intr(hw, port);
2950}
2951
2952/* Handle device specific framing and timeout interrupts */
2953static void skge_error_irq(struct skge_hw *hw)
2954{
2955 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2956
2957 if (hw->chip_id == CHIP_ID_GENESIS) {
2958 /* clear xmac errors */
2959 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 2960 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 2961 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 2962 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 2963 } else {
2964 /* Timestamp (unused) overflow */
2965 if (hwstatus & IS_IRQ_TIST_OV)
2966 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 2967 }
2968
2969 if (hwstatus & IS_RAM_RD_PAR) {
2970 printk(KERN_ERR PFX "Ram read data parity error\n");
2971 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2972 }
2973
2974 if (hwstatus & IS_RAM_WR_PAR) {
2975 printk(KERN_ERR PFX "Ram write data parity error\n");
2976 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2977 }
2978
2979 if (hwstatus & IS_M1_PAR_ERR)
2980 skge_mac_parity(hw, 0);
2981
2982 if (hwstatus & IS_M2_PAR_ERR)
2983 skge_mac_parity(hw, 1);
2984
b9d64acc
SH		 2985 if (hwstatus & IS_R1_PAR_ERR) {
2986 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2987 hw->dev[0]->name);
baef58b1 2988 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 2989 }
baef58b1 2990
b9d64acc
SH		 2991 if (hwstatus & IS_R2_PAR_ERR) {
2992 printk(KERN_ERR PFX "%s: receive queue parity error\n",
2993 hw->dev[1]->name);
baef58b1 2994 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 2995 }
baef58b1
SH		 2996
2997 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 2998 u16 pci_status, pci_cmd;
2999
3000 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
3001 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
baef58b1 3002
b9d64acc
SH		 3003 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
3004 pci_name(hw->pdev), pci_cmd, pci_status);
3005
3006 /* Write the error bits back to clear them. */
3007 pci_status &= PCI_STATUS_ERROR_BITS;
3008 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3009 pci_write_config_word(hw->pdev, PCI_COMMAND,
3010 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3011 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
3012 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3013
050ec18a 3014 /* if error still set then just ignore it */
baef58b1
SH		 3015 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3016 if (hwstatus & IS_IRQ_STAT) {
b9d64acc 3017 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3018 hw->intr_mask &= ~IS_HW_ERR;
3019 }
3020 }
3021}
3022
3023/*
d85b514f 3024 * Interrupt from PHY are handled in work queue
baef58b1
SH		 3025 * because accessing phy registers requires spin wait which might
3026 * cause excess interrupt latency.
3027 */
d85b514f 3028static void skge_extirq(void *arg)
baef58b1 3029{
d85b514f 3030 struct skge_hw *hw = arg;
baef58b1
SH		 3031 int port;
3032
d85b514f 3033 mutex_lock(&hw->phy_mutex);
cfc3ed79 3034 for (port = 0; port < hw->ports; port++) {
baef58b1 3035 struct net_device *dev = hw->dev[port];
cfc3ed79 3036 struct skge_port *skge = netdev_priv(dev);
baef58b1 3037
cfc3ed79 3038 if (netif_running(dev)) {
baef58b1
SH		 3039 if (hw->chip_id != CHIP_ID_GENESIS)
3040 yukon_phy_intr(skge);
64f6b64d 3041 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3042 bcom_phy_intr(skge);
baef58b1
SH		 3043 }
3044 }
d85b514f 3045 mutex_unlock(&hw->phy_mutex);
baef58b1 3046
7c442fa1 3047 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3048 hw->intr_mask |= IS_EXT_REG;
3049 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3050 skge_read32(hw, B0_IMSK);
7c442fa1 3051 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3052}
3053
7d12e780 3054static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3055{
3056 struct skge_hw *hw = dev_id;
cfc3ed79 3057 u32 status;
29365c90 3058 int handled = 0;
baef58b1 3059
29365c90 3060 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3061 /* Reading this register masks IRQ */
3062 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3063 if (status == 0 || status == ~0)
29365c90 3064 goto out;
baef58b1 3065
29365c90 3066 handled = 1;
7c442fa1 3067 status &= hw->intr_mask;
cfc3ed79
SH		 3068 if (status & IS_EXT_REG) {
3069 hw->intr_mask &= ~IS_EXT_REG;
d85b514f 3070 schedule_work(&hw->phy_work);
cfc3ed79
SH		 3071 }
3072
513f533e
SH		 3073 if (status & (IS_XA1_F|IS_R1_F)) {
3074 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
7c442fa1 3075 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 3076 }
3077
7c442fa1
SH		 3078 if (status & IS_PA_TO_TX1)
3079 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3080
d25f5a67
SH		 3081 if (status & IS_PA_TO_RX1) {
3082 struct skge_port *skge = netdev_priv(hw->dev[0]);
d25f5a67 3083
d25f5a67 3084 ++skge->net_stats.rx_over_errors;
7c442fa1 3085 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3086 }
3087
d25f5a67 3088
baef58b1
SH		 3089 if (status & IS_MAC1)
3090 skge_mac_intr(hw, 0);
95566065 3091
7c442fa1 3092 if (hw->dev[1]) {
513f533e
SH		 3093 if (status & (IS_XA2_F|IS_R2_F)) {
3094 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
7c442fa1
SH		 3095 netif_rx_schedule(hw->dev[1]);
3096 }
3097
3098 if (status & IS_PA_TO_RX2) {
3099 struct skge_port *skge = netdev_priv(hw->dev[1]);
3100 ++skge->net_stats.rx_over_errors;
3101 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3102 }
3103
3104 if (status & IS_PA_TO_TX2)
3105 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3106
3107 if (status & IS_MAC2)
3108 skge_mac_intr(hw, 1);
3109 }
baef58b1
SH		 3110
3111 if (status & IS_HW_ERR)
3112 skge_error_irq(hw);
3113
7e676d91 3114 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3115 skge_read32(hw, B0_IMSK);
29365c90 3116out:
7c442fa1 3117 spin_unlock(&hw->hw_lock);
baef58b1 3118
29365c90 3119 return IRQ_RETVAL(handled);
baef58b1
SH		 3120}
3121
3122#ifdef CONFIG_NET_POLL_CONTROLLER
3123static void skge_netpoll(struct net_device *dev)
3124{
3125 struct skge_port *skge = netdev_priv(dev);
3126
3127 disable_irq(dev->irq);
7d12e780 3128 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3129 enable_irq(dev->irq);
3130}
3131#endif
3132
3133static int skge_set_mac_address(struct net_device *dev, void *p)
3134{
3135 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3136 struct skge_hw *hw = skge->hw;
3137 unsigned port = skge->port;
3138 const struct sockaddr *addr = p;
baef58b1
SH		 3139
3140 if (!is_valid_ether_addr(addr->sa_data))
3141 return -EADDRNOTAVAIL;
3142
d85b514f 3143 mutex_lock(&hw->phy_mutex);
baef58b1 3144 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3145 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
baef58b1 3146 dev->dev_addr, ETH_ALEN);
c2681dd8 3147 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
baef58b1 3148 dev->dev_addr, ETH_ALEN);
c2681dd8
SH		 3149
3150 if (hw->chip_id == CHIP_ID_GENESIS)
3151 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3152 else {
3153 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3154 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3155 }
d85b514f 3156 mutex_unlock(&hw->phy_mutex);
c2681dd8
SH		 3157
3158 return 0;
baef58b1
SH		 3159}
3160
3161static const struct {
3162 u8 id;
3163 const char *name;
3164} skge_chips[] = {
3165 { CHIP_ID_GENESIS, "Genesis" },
3166 { CHIP_ID_YUKON, "Yukon" },
3167 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3168 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3169};
3170
3171static const char *skge_board_name(const struct skge_hw *hw)
3172{
3173 int i;
3174 static char buf[16];
3175
3176 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3177 if (skge_chips[i].id == hw->chip_id)
3178 return skge_chips[i].name;
3179
3180 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3181 return buf;
3182}
3183
3184
3185/*
3186 * Setup the board data structure, but don't bring up
3187 * the port(s)
3188 */
3189static int skge_reset(struct skge_hw *hw)
3190{
adba9e23 3191 u32 reg;
b9d64acc 3192 u16 ctst, pci_status;
64f6b64d 3193 u8 t8, mac_cfg, pmd_type;
981d0377 3194 int i;
baef58b1
SH		 3195
3196 ctst = skge_read16(hw, B0_CTST);
3197
3198 /* do a SW reset */
3199 skge_write8(hw, B0_CTST, CS_RST_SET);
3200 skge_write8(hw, B0_CTST, CS_RST_CLR);
3201
3202 /* clear PCI errors, if any */
b9d64acc
SH		 3203 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3204 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3205
b9d64acc
SH		 3206 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3207 pci_write_config_word(hw->pdev, PCI_STATUS,
3208 pci_status | PCI_STATUS_ERROR_BITS);
3209 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3210 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3211
3212 /* restore CLK_RUN bits (for Yukon-Lite) */
3213 skge_write16(hw, B0_CTST,
3214 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3215
3216 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3217 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3218 pmd_type = skge_read8(hw, B2_PMD_TYP);
3219 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3220
95566065 3221 switch (hw->chip_id) {
baef58b1 3222 case CHIP_ID_GENESIS:
64f6b64d
SH		 3223 switch (hw->phy_type) {
3224 case SK_PHY_XMAC:
3225 hw->phy_addr = PHY_ADDR_XMAC;
3226 break;
baef58b1
SH		 3227 case SK_PHY_BCOM:
3228 hw->phy_addr = PHY_ADDR_BCOM;
3229 break;
3230 default:
3231 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
64f6b64d 3232 pci_name(hw->pdev), hw->phy_type);
baef58b1
SH		 3233 return -EOPNOTSUPP;
3234 }
3235 break;
3236
3237 case CHIP_ID_YUKON:
3238 case CHIP_ID_YUKON_LITE:
3239 case CHIP_ID_YUKON_LP:
64f6b64d 3240 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3241 hw->copper = 1;
baef58b1
SH		 3242
3243 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3244 break;
3245
3246 default:
3247 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3248 pci_name(hw->pdev), hw->chip_id);
3249 return -EOPNOTSUPP;
3250 }
3251
981d0377
SH		 3252 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3253 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3254 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3255
3256 /* read the adapters RAM size */
3257 t8 = skge_read8(hw, B2_E_0);
3258 if (hw->chip_id == CHIP_ID_GENESIS) {
3259 if (t8 == 3) {
3260 /* special case: 4 x 64k x 36, offset = 0x80000 */
3261 hw->ram_size = 0x100000;
3262 hw->ram_offset = 0x80000;
3263 } else
3264 hw->ram_size = t8 * 512;
3265 }
3266 else if (t8 == 0)
3267 hw->ram_size = 0x20000;
3268 else
3269 hw->ram_size = t8 * 4096;
3270
64f6b64d 3271 hw->intr_mask = IS_HW_ERR | IS_PORT_1;
cfc3ed79
SH		 3272 if (hw->ports > 1)
3273 hw->intr_mask |= IS_PORT_2;
3274
64f6b64d
SH		 3275 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3276 hw->intr_mask |= IS_EXT_REG;
3277
baef58b1
SH		 3278 if (hw->chip_id == CHIP_ID_GENESIS)
3279 genesis_init(hw);
3280 else {
3281 /* switch power to VCC (WA for VAUX problem) */
3282 skge_write8(hw, B0_POWER_CTRL,
3283 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3284
050ec18a
SH		 3285 /* avoid boards with stuck Hardware error bits */
3286 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3287 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3288 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3289 hw->intr_mask &= ~IS_HW_ERR;
3290 }
3291
adba9e23
SH		 3292 /* Clear PHY COMA */
3293 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3294 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3295 reg &= ~PCI_PHY_COMA;
3296 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3297 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3298
3299
981d0377 3300 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3301 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3302 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3303 }
3304 }
3305
3306 /* turn off hardware timer (unused) */
3307 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3308 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3309 skge_write8(hw, B0_LED, LED_STAT_ON);
3310
3311 /* enable the Tx Arbiters */
981d0377 3312 for (i = 0; i < hw->ports; i++)
6b0c1480 3313 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3314
3315 /* Initialize ram interface */
3316 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3317
3318 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3319 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3320 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3321 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3322 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3323 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3324 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3325 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3326 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3327 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3328 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3329 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3330
3331 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3332
3333 /* Set interrupt moderation for Transmit only
3334 * Receive interrupts avoided by NAPI
3335 */
3336 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3337 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3338 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3339
baef58b1
SH		 3340 skge_write32(hw, B0_IMSK, hw->intr_mask);
3341
d85b514f 3342 mutex_lock(&hw->phy_mutex);
981d0377 3343 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3344 if (hw->chip_id == CHIP_ID_GENESIS)
3345 genesis_reset(hw, i);
3346 else
3347 yukon_reset(hw, i);
3348 }
d85b514f 3349 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 3350
3351 return 0;
3352}
3353
3354/* Initialize network device */
981d0377
SH		 3355static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3356 int highmem)
baef58b1
SH		 3357{
3358 struct skge_port *skge;
3359 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3360
3361 if (!dev) {
3362 printk(KERN_ERR "skge etherdev alloc failed");
3363 return NULL;
3364 }
3365
3366 SET_MODULE_OWNER(dev);
3367 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3368 dev->open = skge_up;
3369 dev->stop = skge_down;
2cd8e5d3 3370 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3371 dev->hard_start_xmit = skge_xmit_frame;
3372 dev->get_stats = skge_get_stats;
3373 if (hw->chip_id == CHIP_ID_GENESIS)
3374 dev->set_multicast_list = genesis_set_multicast;
3375 else
3376 dev->set_multicast_list = yukon_set_multicast;
3377
3378 dev->set_mac_address = skge_set_mac_address;
3379 dev->change_mtu = skge_change_mtu;
3380 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3381 dev->tx_timeout = skge_tx_timeout;
3382 dev->watchdog_timeo = TX_WATCHDOG;
3383 dev->poll = skge_poll;
3384 dev->weight = NAPI_WEIGHT;
3385#ifdef CONFIG_NET_POLL_CONTROLLER
3386 dev->poll_controller = skge_netpoll;
3387#endif
3388 dev->irq = hw->pdev->irq;
513f533e 3389
981d0377
SH		 3390 if (highmem)
3391 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3392
3393 skge = netdev_priv(dev);
3394 skge->netdev = dev;
3395 skge->hw = hw;
3396 skge->msg_enable = netif_msg_init(debug, default_msg);
3397 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3398 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3399
3400 /* Auto speed and flow control */
3401 skge->autoneg = AUTONEG_ENABLE;
3402 skge->flow_control = FLOW_MODE_SYMMETRIC;
3403 skge->duplex = -1;
3404 skge->speed = -1;
31b619c5 3405 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3406
3407 hw->dev[port] = dev;
3408
3409 skge->port = port;
3410
64f6b64d
SH		 3411 /* Only used for Genesis XMAC */
3412 INIT_WORK(&skge->link_thread, xm_link_timer, dev);
3413
baef58b1
SH		 3414 if (hw->chip_id != CHIP_ID_GENESIS) {
3415 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3416 skge->rx_csum = 1;
3417 }
3418
3419 /* read the mac address */
3420 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3421 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3422
3423 /* device is off until link detection */
3424 netif_carrier_off(dev);
3425 netif_stop_queue(dev);
3426
3427 return dev;
3428}
3429
3430static void __devinit skge_show_addr(struct net_device *dev)
3431{
3432 const struct skge_port *skge = netdev_priv(dev);
3433
3434 if (netif_msg_probe(skge))
3435 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3436 dev->name,
3437 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3438 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3439}
3440
3441static int __devinit skge_probe(struct pci_dev *pdev,
3442 const struct pci_device_id *ent)
3443{
3444 struct net_device *dev, *dev1;
3445 struct skge_hw *hw;
3446 int err, using_dac = 0;
3447
203babb6
SH		 3448 err = pci_enable_device(pdev);
3449 if (err) {
baef58b1
SH		 3450 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3451 pci_name(pdev));
3452 goto err_out;
3453 }
3454
203babb6
SH		 3455 err = pci_request_regions(pdev, DRV_NAME);
3456 if (err) {
baef58b1
SH		 3457 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3458 pci_name(pdev));
3459 goto err_out_disable_pdev;
3460 }
3461
3462 pci_set_master(pdev);
3463
93aea718 3464 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
baef58b1 3465 using_dac = 1;
77783a78 3466 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
93aea718
SH		 3467 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3468 using_dac = 0;
3469 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3470 }
3471
3472 if (err) {
3473 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3474 pci_name(pdev));
3475 goto err_out_free_regions;
baef58b1
SH		 3476 }
3477
3478#ifdef __BIG_ENDIAN
8f3f8193 3479 /* byte swap descriptors in hardware */
baef58b1
SH		 3480 {
3481 u32 reg;
3482
3483 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3484 reg |= PCI_REV_DESC;
3485 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3486 }
3487#endif
3488
3489 err = -ENOMEM;
7e863061 3490 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1
SH		 3491 if (!hw) {
3492 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3493 pci_name(pdev));
3494 goto err_out_free_regions;
3495 }
3496
baef58b1 3497 hw->pdev = pdev;
d85b514f
SH		 3498 mutex_init(&hw->phy_mutex);
3499 INIT_WORK(&hw->phy_work, skge_extirq, hw);
d38efdd6 3500 spin_lock_init(&hw->hw_lock);
baef58b1
SH		 3501
3502 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3503 if (!hw->regs) {
3504 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3505 pci_name(pdev));
3506 goto err_out_free_hw;
3507 }
3508
baef58b1
SH		 3509 err = skge_reset(hw);
3510 if (err)
ccdaa2a9 3511 goto err_out_iounmap;
baef58b1 3512
7c7459d1
GKH		 3513 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3514 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
981d0377 3515 skge_board_name(hw), hw->chip_rev);
baef58b1 3516
ccdaa2a9
SH		 3517 dev = skge_devinit(hw, 0, using_dac);
3518 if (!dev)
baef58b1
SH		 3519 goto err_out_led_off;
3520
631ae320
SH		 3521 if (!is_valid_ether_addr(dev->dev_addr)) {
3522 printk(KERN_ERR PFX "%s: bad (zero?) ethernet address in rom\n",
3523 pci_name(pdev));
3524 err = -EIO;
3525 goto err_out_free_netdev;
3526 }
3527
203babb6
SH		 3528 err = register_netdev(dev);
3529 if (err) {
baef58b1
SH		 3530 printk(KERN_ERR PFX "%s: cannot register net device\n",
3531 pci_name(pdev));
3532 goto err_out_free_netdev;
3533 }
3534
ccdaa2a9
SH		 3535 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3536 if (err) {
3537 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3538 dev->name, pdev->irq);
3539 goto err_out_unregister;
3540 }
baef58b1
SH		 3541 skge_show_addr(dev);
3542
981d0377 3543 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3544 if (register_netdev(dev1) == 0)
3545 skge_show_addr(dev1);
3546 else {
3547 /* Failure to register second port need not be fatal */
3548 printk(KERN_WARNING PFX "register of second port failed\n");
3549 hw->dev[1] = NULL;
3550 free_netdev(dev1);
3551 }
3552 }
ccdaa2a9 3553 pci_set_drvdata(pdev, hw);
baef58b1
SH		 3554
3555 return 0;
3556
ccdaa2a9
SH		 3557err_out_unregister:
3558 unregister_netdev(dev);
baef58b1
SH		 3559err_out_free_netdev:
3560 free_netdev(dev);
3561err_out_led_off:
3562 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 3563err_out_iounmap:
3564 iounmap(hw->regs);
3565err_out_free_hw:
3566 kfree(hw);
3567err_out_free_regions:
3568 pci_release_regions(pdev);
3569err_out_disable_pdev:
3570 pci_disable_device(pdev);
3571 pci_set_drvdata(pdev, NULL);
3572err_out:
3573 return err;
3574}
3575
3576static void __devexit skge_remove(struct pci_dev *pdev)
3577{
3578 struct skge_hw *hw = pci_get_drvdata(pdev);
3579 struct net_device *dev0, *dev1;
3580
95566065 3581 if (!hw)
baef58b1
SH		 3582 return;
3583
3584 if ((dev1 = hw->dev[1]))
3585 unregister_netdev(dev1);
3586 dev0 = hw->dev[0];
3587 unregister_netdev(dev0);
3588
7c442fa1
SH		 3589 spin_lock_irq(&hw->hw_lock);
3590 hw->intr_mask = 0;
46a60f2d 3591 skge_write32(hw, B0_IMSK, 0);
78bc2186 3592 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 3593 spin_unlock_irq(&hw->hw_lock);
3594
46a60f2d 3595 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 3596 skge_write8(hw, B0_CTST, CS_RST_SET);
3597
d85b514f 3598 flush_scheduled_work();
baef58b1
SH		 3599
3600 free_irq(pdev->irq, hw);
3601 pci_release_regions(pdev);
3602 pci_disable_device(pdev);
3603 if (dev1)
3604 free_netdev(dev1);
3605 free_netdev(dev0);
46a60f2d 3606
baef58b1
SH		 3607 iounmap(hw->regs);
3608 kfree(hw);
3609 pci_set_drvdata(pdev, NULL);
3610}
3611
3612#ifdef CONFIG_PM
2a569579 3613static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3614{
3615 struct skge_hw *hw = pci_get_drvdata(pdev);
3616 int i, wol = 0;
3617
d38efdd6
SH		 3618 pci_save_state(pdev);
3619 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3620 struct net_device *dev = hw->dev[i];
3621
d38efdd6 3622 if (netif_running(dev)) {
baef58b1 3623 struct skge_port *skge = netdev_priv(dev);
d38efdd6
SH		 3624
3625 netif_carrier_off(dev);
3626 if (skge->wol)
3627 netif_stop_queue(dev);
3628 else
3629 skge_down(dev);
baef58b1
SH		 3630 wol |= skge->wol;
3631 }
d38efdd6 3632 netif_device_detach(dev);
baef58b1
SH		 3633 }
3634
d38efdd6 3635 skge_write32(hw, B0_IMSK, 0);
2a569579 3636 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3637 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3638
3639 return 0;
3640}
3641
3642static int skge_resume(struct pci_dev *pdev)
3643{
3644 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 3645 int i, err;
baef58b1
SH		 3646
3647 pci_set_power_state(pdev, PCI_D0);
3648 pci_restore_state(pdev);
3649 pci_enable_wake(pdev, PCI_D0, 0);
3650
d38efdd6
SH		 3651 err = skge_reset(hw);
3652 if (err)
3653 goto out;
baef58b1 3654
d38efdd6 3655 for (i = 0; i < hw->ports; i++) {
baef58b1 3656 struct net_device *dev = hw->dev[i];
d38efdd6
SH		 3657
3658 netif_device_attach(dev);
3659 if (netif_running(dev)) {
3660 err = skge_up(dev);
3661
3662 if (err) {
3663 printk(KERN_ERR PFX "%s: could not up: %d\n",
3664 dev->name, err);
edd702e8 3665 dev_close(dev);
d38efdd6
SH		 3666 goto out;
3667 }
baef58b1
SH		 3668 }
3669 }
d38efdd6
SH		 3670out:
3671 return err;
baef58b1
SH		 3672}
3673#endif
3674
3675static struct pci_driver skge_driver = {
3676 .name = DRV_NAME,
3677 .id_table = skge_id_table,
3678 .probe = skge_probe,
3679 .remove = __devexit_p(skge_remove),
3680#ifdef CONFIG_PM
3681 .suspend = skge_suspend,
3682 .resume = skge_resume,
3683#endif
3684};
3685
3686static int __init skge_init_module(void)
3687{
29917620 3688 return pci_register_driver(&skge_driver);
baef58b1
SH		 3689}
3690
3691static void __exit skge_cleanup_module(void)
3692{
3693 pci_unregister_driver(&skge_driver);
3694}
3695
3696module_init(skge_init_module);
3697module_exit(skge_cleanup_module);
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