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Merge git://git.kernel.org/pub/scm/linux/kernel/git/sfrench/cifs-2.6
[mirror_ubuntu-artful-kernel.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
14c85021 26#include <linux/in.h>
baef58b1
SH		 27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/if_vlan.h>
35#include <linux/ip.h>
36#include <linux/delay.h>
37#include <linux/crc32.h>
4075400b 38#include <linux/dma-mapping.h>
2cd8e5d3 39#include <linux/mii.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
a407a6a0 45#define DRV_VERSION "1.10"
baef58b1
SH		 46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
9db96479 51#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 52#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 53#define RX_COPY_THRESHOLD 128
54#define RX_BUF_SIZE 1536
baef58b1
SH		 55#define PHY_RETRIES 1000
56#define ETH_JUMBO_MTU 9000
57#define TX_WATCHDOG (5 * HZ)
58#define NAPI_WEIGHT 64
6abebb53 59#define BLINK_MS 250
64f6b64d 60#define LINK_HZ (HZ/2)
baef58b1
SH		 61
62MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
65ebe634 63MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
baef58b1
SH		 64MODULE_LICENSE("GPL");
65MODULE_VERSION(DRV_VERSION);
66
67static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71static int debug = -1; /* defaults above */
72module_param(debug, int, 0);
73MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
f19841f5 80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
2d2a3871 81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
f19841f5 86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
baef58b1
SH		 87 { 0 }
88};
89MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91static int skge_up(struct net_device *dev);
92static int skge_down(struct net_device *dev);
ee294dcd 93static void skge_phy_reset(struct skge_port *skge);
513f533e 94static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 95static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 97static void genesis_get_stats(struct skge_port *skge, u64 *data);
98static void yukon_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_init(struct skge_hw *hw, int port);
baef58b1 100static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 101static void genesis_link_up(struct skge_port *skge);
baef58b1 102
7e676d91 103/* Avoid conditionals by using array */
baef58b1
SH		 104static const int txqaddr[] = { Q_XA1, Q_XA2 };
105static const int rxqaddr[] = { Q_R1, Q_R2 };
106static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
513f533e 108static const u32 irqmask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
baef58b1 109
baef58b1
SH		 110static int skge_get_regs_len(struct net_device *dev)
111{
c3f8be96 112 return 0x4000;
baef58b1
SH		 113}
114
115/*
c3f8be96
SH		 116 * Returns copy of whole control register region
117 * Note: skip RAM address register because accessing it will
118 * cause bus hangs!
baef58b1
SH		 119 */
120static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
121 void *p)
122{
123 const struct skge_port *skge = netdev_priv(dev);
baef58b1 124 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 125
126 regs->version = 1;
c3f8be96
SH		 127 memset(p, 0, regs->len);
128 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 129
c3f8be96
SH		 130 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
131 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 132}
133
8f3f8193 134/* Wake on Lan only supported on Yukon chips with rev 1 or above */
a504e64a 135static u32 wol_supported(const struct skge_hw *hw)
baef58b1 136{
a504e64a
SH		 137 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev != 0)
138 return WAKE_MAGIC | WAKE_PHY;
139 else
140 return 0;
141}
142
143static u32 pci_wake_enabled(struct pci_dev *dev)
144{
145 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
146 u16 value;
147
148 /* If device doesn't support PM Capabilities, but request is to disable
149 * wake events, it's a nop; otherwise fail */
150 if (!pm)
151 return 0;
152
153 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
154
155 value &= PCI_PM_CAP_PME_MASK;
156 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
157
158 return value != 0;
159}
160
161static void skge_wol_init(struct skge_port *skge)
162{
163 struct skge_hw *hw = skge->hw;
164 int port = skge->port;
165 enum pause_control save_mode;
166 u32 ctrl;
167
168 /* Bring hardware out of reset */
169 skge_write16(hw, B0_CTST, CS_RST_CLR);
170 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
171
172 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
173 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
174
175 /* Force to 10/100 skge_reset will re-enable on resume */
176 save_mode = skge->flow_control;
177 skge->flow_control = FLOW_MODE_SYMMETRIC;
178
179 ctrl = skge->advertising;
180 skge->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
181
182 skge_phy_reset(skge);
183
184 skge->flow_control = save_mode;
185 skge->advertising = ctrl;
186
187 /* Set GMAC to no flow control and auto update for speed/duplex */
188 gma_write16(hw, port, GM_GP_CTRL,
189 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
190 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
191
192 /* Set WOL address */
193 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
194 skge->netdev->dev_addr, ETH_ALEN);
195
196 /* Turn on appropriate WOL control bits */
197 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
198 ctrl = 0;
199 if (skge->wol & WAKE_PHY)
200 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
201 else
202 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
203
204 if (skge->wol & WAKE_MAGIC)
205 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
206 else
207 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
208
209 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
210 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
211
212 /* block receiver */
213 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 214}
215
216static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
217{
218 struct skge_port *skge = netdev_priv(dev);
219
a504e64a
SH		 220 wol->supported = wol_supported(skge->hw);
221 wol->wolopts = skge->wol;
baef58b1
SH		 222}
223
224static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
225{
226 struct skge_port *skge = netdev_priv(dev);
227 struct skge_hw *hw = skge->hw;
228
a504e64a 229 if (wol->wolopts & wol_supported(hw))
baef58b1
SH		 230 return -EOPNOTSUPP;
231
a504e64a
SH		 232 skge->wol = wol->wolopts;
233 if (!netif_running(dev))
234 skge_wol_init(skge);
baef58b1
SH		 235 return 0;
236}
237
8f3f8193
SH		 238/* Determine supported/advertised modes based on hardware.
239 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 240 */
241static u32 skge_supported_modes(const struct skge_hw *hw)
242{
243 u32 supported;
244
5e1705dd 245 if (hw->copper) {
31b619c5
SH		 246 supported = SUPPORTED_10baseT_Half
247 | SUPPORTED_10baseT_Full
248 | SUPPORTED_100baseT_Half
249 | SUPPORTED_100baseT_Full
250 | SUPPORTED_1000baseT_Half
251 | SUPPORTED_1000baseT_Full
252 | SUPPORTED_Autoneg| SUPPORTED_TP;
253
254 if (hw->chip_id == CHIP_ID_GENESIS)
255 supported &= ~(SUPPORTED_10baseT_Half
256 | SUPPORTED_10baseT_Full
257 | SUPPORTED_100baseT_Half
258 | SUPPORTED_100baseT_Full);
259
260 else if (hw->chip_id == CHIP_ID_YUKON)
261 supported &= ~SUPPORTED_1000baseT_Half;
262 } else
4b67be99
SH		 263 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
264 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
31b619c5
SH		 265
266 return supported;
267}
baef58b1
SH		 268
269static int skge_get_settings(struct net_device *dev,
270 struct ethtool_cmd *ecmd)
271{
272 struct skge_port *skge = netdev_priv(dev);
273 struct skge_hw *hw = skge->hw;
274
275 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 276 ecmd->supported = skge_supported_modes(hw);
baef58b1 277
5e1705dd 278 if (hw->copper) {
baef58b1
SH		 279 ecmd->port = PORT_TP;
280 ecmd->phy_address = hw->phy_addr;
31b619c5 281 } else
baef58b1 282 ecmd->port = PORT_FIBRE;
baef58b1
SH		 283
284 ecmd->advertising = skge->advertising;
285 ecmd->autoneg = skge->autoneg;
286 ecmd->speed = skge->speed;
287 ecmd->duplex = skge->duplex;
288 return 0;
289}
290
baef58b1
SH		 291static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
292{
293 struct skge_port *skge = netdev_priv(dev);
294 const struct skge_hw *hw = skge->hw;
31b619c5 295 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 296
297 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 298 ecmd->advertising = supported;
299 skge->duplex = -1;
300 skge->speed = -1;
baef58b1 301 } else {
31b619c5
SH		 302 u32 setting;
303
2c668514 304 switch (ecmd->speed) {
baef58b1 305 case SPEED_1000:
31b619c5
SH		 306 if (ecmd->duplex == DUPLEX_FULL)
307 setting = SUPPORTED_1000baseT_Full;
308 else if (ecmd->duplex == DUPLEX_HALF)
309 setting = SUPPORTED_1000baseT_Half;
310 else
311 return -EINVAL;
baef58b1
SH		 312 break;
313 case SPEED_100:
31b619c5
SH		 314 if (ecmd->duplex == DUPLEX_FULL)
315 setting = SUPPORTED_100baseT_Full;
316 else if (ecmd->duplex == DUPLEX_HALF)
317 setting = SUPPORTED_100baseT_Half;
318 else
319 return -EINVAL;
320 break;
321
baef58b1 322 case SPEED_10:
31b619c5
SH		 323 if (ecmd->duplex == DUPLEX_FULL)
324 setting = SUPPORTED_10baseT_Full;
325 else if (ecmd->duplex == DUPLEX_HALF)
326 setting = SUPPORTED_10baseT_Half;
327 else
baef58b1
SH		 328 return -EINVAL;
329 break;
330 default:
331 return -EINVAL;
332 }
31b619c5
SH		 333
334 if ((setting & supported) == 0)
335 return -EINVAL;
336
337 skge->speed = ecmd->speed;
338 skge->duplex = ecmd->duplex;
baef58b1
SH		 339 }
340
341 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 342 skge->advertising = ecmd->advertising;
343
ee294dcd
SH		 344 if (netif_running(dev))
345 skge_phy_reset(skge);
346
baef58b1
SH		 347 return (0);
348}
349
350static void skge_get_drvinfo(struct net_device *dev,
351 struct ethtool_drvinfo *info)
352{
353 struct skge_port *skge = netdev_priv(dev);
354
355 strcpy(info->driver, DRV_NAME);
356 strcpy(info->version, DRV_VERSION);
357 strcpy(info->fw_version, "N/A");
358 strcpy(info->bus_info, pci_name(skge->hw->pdev));
359}
360
361static const struct skge_stat {
362 char name[ETH_GSTRING_LEN];
363 u16 xmac_offset;
364 u16 gma_offset;
365} skge_stats[] = {
366 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
367 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
368
369 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
370 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
371 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
372 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
373 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
374 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
375 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
376 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
377
378 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
379 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
380 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
381 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
382 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
383 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
384
385 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
386 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
387 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
388 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
389 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
390};
391
392static int skge_get_stats_count(struct net_device *dev)
393{
394 return ARRAY_SIZE(skge_stats);
395}
396
397static void skge_get_ethtool_stats(struct net_device *dev,
398 struct ethtool_stats *stats, u64 *data)
399{
400 struct skge_port *skge = netdev_priv(dev);
401
402 if (skge->hw->chip_id == CHIP_ID_GENESIS)
403 genesis_get_stats(skge, data);
404 else
405 yukon_get_stats(skge, data);
406}
407
408/* Use hardware MIB variables for critical path statistics and
409 * transmit feedback not reported at interrupt.
410 * Other errors are accounted for in interrupt handler.
411 */
412static struct net_device_stats *skge_get_stats(struct net_device *dev)
413{
414 struct skge_port *skge = netdev_priv(dev);
415 u64 data[ARRAY_SIZE(skge_stats)];
416
417 if (skge->hw->chip_id == CHIP_ID_GENESIS)
418 genesis_get_stats(skge, data);
419 else
420 yukon_get_stats(skge, data);
421
422 skge->net_stats.tx_bytes = data[0];
423 skge->net_stats.rx_bytes = data[1];
424 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
425 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
4c180fc4 426 skge->net_stats.multicast = data[3] + data[5];
baef58b1
SH		 427 skge->net_stats.collisions = data[10];
428 skge->net_stats.tx_aborted_errors = data[12];
429
430 return &skge->net_stats;
431}
432
433static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
434{
435 int i;
436
95566065 437 switch (stringset) {
baef58b1
SH		 438 case ETH_SS_STATS:
439 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
440 memcpy(data + i * ETH_GSTRING_LEN,
441 skge_stats[i].name, ETH_GSTRING_LEN);
442 break;
443 }
444}
445
446static void skge_get_ring_param(struct net_device *dev,
447 struct ethtool_ringparam *p)
448{
449 struct skge_port *skge = netdev_priv(dev);
450
451 p->rx_max_pending = MAX_RX_RING_SIZE;
452 p->tx_max_pending = MAX_TX_RING_SIZE;
453 p->rx_mini_max_pending = 0;
454 p->rx_jumbo_max_pending = 0;
455
456 p->rx_pending = skge->rx_ring.count;
457 p->tx_pending = skge->tx_ring.count;
458 p->rx_mini_pending = 0;
459 p->rx_jumbo_pending = 0;
460}
461
462static int skge_set_ring_param(struct net_device *dev,
463 struct ethtool_ringparam *p)
464{
465 struct skge_port *skge = netdev_priv(dev);
3b8bb472 466 int err;
baef58b1
SH		 467
468 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 469 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 470 return -EINVAL;
471
472 skge->rx_ring.count = p->rx_pending;
473 skge->tx_ring.count = p->tx_pending;
474
475 if (netif_running(dev)) {
476 skge_down(dev);
3b8bb472
SH		 477 err = skge_up(dev);
478 if (err)
479 dev_close(dev);
baef58b1
SH		 480 }
481
482 return 0;
483}
484
485static u32 skge_get_msglevel(struct net_device *netdev)
486{
487 struct skge_port *skge = netdev_priv(netdev);
488 return skge->msg_enable;
489}
490
491static void skge_set_msglevel(struct net_device *netdev, u32 value)
492{
493 struct skge_port *skge = netdev_priv(netdev);
494 skge->msg_enable = value;
495}
496
497static int skge_nway_reset(struct net_device *dev)
498{
499 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 500
501 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
502 return -EINVAL;
503
ee294dcd 504 skge_phy_reset(skge);
baef58b1
SH		 505 return 0;
506}
507
508static int skge_set_sg(struct net_device *dev, u32 data)
509{
510 struct skge_port *skge = netdev_priv(dev);
511 struct skge_hw *hw = skge->hw;
512
513 if (hw->chip_id == CHIP_ID_GENESIS && data)
514 return -EOPNOTSUPP;
515 return ethtool_op_set_sg(dev, data);
516}
517
518static int skge_set_tx_csum(struct net_device *dev, u32 data)
519{
520 struct skge_port *skge = netdev_priv(dev);
521 struct skge_hw *hw = skge->hw;
522
523 if (hw->chip_id == CHIP_ID_GENESIS && data)
524 return -EOPNOTSUPP;
525
526 return ethtool_op_set_tx_csum(dev, data);
527}
528
529static u32 skge_get_rx_csum(struct net_device *dev)
530{
531 struct skge_port *skge = netdev_priv(dev);
532
533 return skge->rx_csum;
534}
535
536/* Only Yukon supports checksum offload. */
537static int skge_set_rx_csum(struct net_device *dev, u32 data)
538{
539 struct skge_port *skge = netdev_priv(dev);
540
541 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
542 return -EOPNOTSUPP;
543
544 skge->rx_csum = data;
545 return 0;
546}
547
baef58b1
SH		 548static void skge_get_pauseparam(struct net_device *dev,
549 struct ethtool_pauseparam *ecmd)
550{
551 struct skge_port *skge = netdev_priv(dev);
552
5d5c8e03
SH		 553 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
554 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
555 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
baef58b1 556
5d5c8e03 557 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 558}
559
560static int skge_set_pauseparam(struct net_device *dev,
561 struct ethtool_pauseparam *ecmd)
562{
563 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 564 struct ethtool_pauseparam old;
baef58b1 565
5d5c8e03
SH		 566 skge_get_pauseparam(dev, &old);
567
568 if (ecmd->autoneg != old.autoneg)
569 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
570 else {
571 if (ecmd->rx_pause && ecmd->tx_pause)
572 skge->flow_control = FLOW_MODE_SYMMETRIC;
573 else if (ecmd->rx_pause && !ecmd->tx_pause)
574 skge->flow_control = FLOW_MODE_SYM_OR_REM;
575 else if (!ecmd->rx_pause && ecmd->tx_pause)
576 skge->flow_control = FLOW_MODE_LOC_SEND;
577 else
578 skge->flow_control = FLOW_MODE_NONE;
579 }
baef58b1 580
e8df8554
SH		 581 if (netif_running(dev))
582 skge_phy_reset(skge);
5d5c8e03 583
baef58b1
SH		 584 return 0;
585}
586
587/* Chip internal frequency for clock calculations */
588static inline u32 hwkhz(const struct skge_hw *hw)
589{
187ff3b8 590 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 591}
592
8f3f8193 593/* Chip HZ to microseconds */
baef58b1
SH		 594static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
595{
596 return (ticks * 1000) / hwkhz(hw);
597}
598
8f3f8193 599/* Microseconds to chip HZ */
baef58b1
SH		 600static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
601{
602 return hwkhz(hw) * usec / 1000;
603}
604
605static int skge_get_coalesce(struct net_device *dev,
606 struct ethtool_coalesce *ecmd)
607{
608 struct skge_port *skge = netdev_priv(dev);
609 struct skge_hw *hw = skge->hw;
610 int port = skge->port;
611
612 ecmd->rx_coalesce_usecs = 0;
613 ecmd->tx_coalesce_usecs = 0;
614
615 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
616 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
617 u32 msk = skge_read32(hw, B2_IRQM_MSK);
618
619 if (msk & rxirqmask[port])
620 ecmd->rx_coalesce_usecs = delay;
621 if (msk & txirqmask[port])
622 ecmd->tx_coalesce_usecs = delay;
623 }
624
625 return 0;
626}
627
628/* Note: interrupt timer is per board, but can turn on/off per port */
629static int skge_set_coalesce(struct net_device *dev,
630 struct ethtool_coalesce *ecmd)
631{
632 struct skge_port *skge = netdev_priv(dev);
633 struct skge_hw *hw = skge->hw;
634 int port = skge->port;
635 u32 msk = skge_read32(hw, B2_IRQM_MSK);
636 u32 delay = 25;
637
638 if (ecmd->rx_coalesce_usecs == 0)
639 msk &= ~rxirqmask[port];
640 else if (ecmd->rx_coalesce_usecs < 25 ||
641 ecmd->rx_coalesce_usecs > 33333)
642 return -EINVAL;
643 else {
644 msk |= rxirqmask[port];
645 delay = ecmd->rx_coalesce_usecs;
646 }
647
648 if (ecmd->tx_coalesce_usecs == 0)
649 msk &= ~txirqmask[port];
650 else if (ecmd->tx_coalesce_usecs < 25 ||
651 ecmd->tx_coalesce_usecs > 33333)
652 return -EINVAL;
653 else {
654 msk |= txirqmask[port];
655 delay = min(delay, ecmd->rx_coalesce_usecs);
656 }
657
658 skge_write32(hw, B2_IRQM_MSK, msk);
659 if (msk == 0)
660 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
661 else {
662 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
663 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
664 }
665 return 0;
666}
667
6abebb53
SH		 668enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
669static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 670{
6abebb53
SH		 671 struct skge_hw *hw = skge->hw;
672 int port = skge->port;
673
d85b514f 674 mutex_lock(&hw->phy_mutex);
baef58b1 675 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 676 switch (mode) {
677 case LED_MODE_OFF:
64f6b64d
SH		 678 if (hw->phy_type == SK_PHY_BCOM)
679 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
680 else {
681 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
682 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
683 }
6abebb53
SH		 684 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
685 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
686 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
687 break;
baef58b1 688
6abebb53
SH		 689 case LED_MODE_ON:
690 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
691 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 692
6abebb53
SH		 693 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
694 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 695
6abebb53 696 break;
baef58b1 697
6abebb53
SH		 698 case LED_MODE_TST:
699 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
700 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
701 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 702
64f6b64d
SH		 703 if (hw->phy_type == SK_PHY_BCOM)
704 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
705 else {
706 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
707 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
708 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
709 }
710
6abebb53 711 }
baef58b1 712 } else {
6abebb53
SH		 713 switch (mode) {
714 case LED_MODE_OFF:
715 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
716 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
717 PHY_M_LED_MO_DUP(MO_LED_OFF) |
718 PHY_M_LED_MO_10(MO_LED_OFF) |
719 PHY_M_LED_MO_100(MO_LED_OFF) |
720 PHY_M_LED_MO_1000(MO_LED_OFF) |
721 PHY_M_LED_MO_RX(MO_LED_OFF));
722 break;
723 case LED_MODE_ON:
724 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
725 PHY_M_LED_PULS_DUR(PULS_170MS) |
726 PHY_M_LED_BLINK_RT(BLINK_84MS) |
727 PHY_M_LEDC_TX_CTRL |
728 PHY_M_LEDC_DP_CTRL);
46a60f2d 729
6abebb53
SH		 730 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
731 PHY_M_LED_MO_RX(MO_LED_OFF) |
732 (skge->speed == SPEED_100 ?
733 PHY_M_LED_MO_100(MO_LED_ON) : 0));
734 break;
735 case LED_MODE_TST:
736 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
737 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
738 PHY_M_LED_MO_DUP(MO_LED_ON) |
739 PHY_M_LED_MO_10(MO_LED_ON) |
740 PHY_M_LED_MO_100(MO_LED_ON) |
741 PHY_M_LED_MO_1000(MO_LED_ON) |
742 PHY_M_LED_MO_RX(MO_LED_ON));
743 }
baef58b1 744 }
d85b514f 745 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 746}
747
748/* blink LED's for finding board */
749static int skge_phys_id(struct net_device *dev, u32 data)
750{
751 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 752 unsigned long ms;
753 enum led_mode mode = LED_MODE_TST;
baef58b1 754
95566065 755 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 756 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
757 else
758 ms = data * 1000;
baef58b1 759
6abebb53
SH		 760 while (ms > 0) {
761 skge_led(skge, mode);
762 mode ^= LED_MODE_TST;
baef58b1 763
6abebb53
SH		 764 if (msleep_interruptible(BLINK_MS))
765 break;
766 ms -= BLINK_MS;
767 }
baef58b1 768
6abebb53
SH		 769 /* back to regular LED state */
770 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 771
772 return 0;
773}
774
7282d491 775static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 776 .get_settings = skge_get_settings,
777 .set_settings = skge_set_settings,
778 .get_drvinfo = skge_get_drvinfo,
779 .get_regs_len = skge_get_regs_len,
780 .get_regs = skge_get_regs,
781 .get_wol = skge_get_wol,
782 .set_wol = skge_set_wol,
783 .get_msglevel = skge_get_msglevel,
784 .set_msglevel = skge_set_msglevel,
785 .nway_reset = skge_nway_reset,
786 .get_link = ethtool_op_get_link,
787 .get_ringparam = skge_get_ring_param,
788 .set_ringparam = skge_set_ring_param,
789 .get_pauseparam = skge_get_pauseparam,
790 .set_pauseparam = skge_set_pauseparam,
791 .get_coalesce = skge_get_coalesce,
792 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 793 .get_sg = ethtool_op_get_sg,
794 .set_sg = skge_set_sg,
795 .get_tx_csum = ethtool_op_get_tx_csum,
796 .set_tx_csum = skge_set_tx_csum,
797 .get_rx_csum = skge_get_rx_csum,
798 .set_rx_csum = skge_set_rx_csum,
799 .get_strings = skge_get_strings,
800 .phys_id = skge_phys_id,
801 .get_stats_count = skge_get_stats_count,
802 .get_ethtool_stats = skge_get_ethtool_stats,
56230d53 803 .get_perm_addr = ethtool_op_get_perm_addr,
baef58b1
SH		 804};
805
806/*
807 * Allocate ring elements and chain them together
808 * One-to-one association of board descriptors with ring elements
809 */
c3da1447 810static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 811{
812 struct skge_tx_desc *d;
813 struct skge_element *e;
814 int i;
815
cd861280 816 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
baef58b1
SH		 817 if (!ring->start)
818 return -ENOMEM;
819
820 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
821 e->desc = d;
822 if (i == ring->count - 1) {
823 e->next = ring->start;
824 d->next_offset = base;
825 } else {
826 e->next = e + 1;
827 d->next_offset = base + (i+1) * sizeof(*d);
828 }
829 }
830 ring->to_use = ring->to_clean = ring->start;
831
832 return 0;
833}
834
19a33d4e
SH		 835/* Allocate and setup a new buffer for receiving */
836static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
837 struct sk_buff *skb, unsigned int bufsize)
838{
839 struct skge_rx_desc *rd = e->desc;
840 u64 map;
baef58b1
SH		 841
842 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
843 PCI_DMA_FROMDEVICE);
844
845 rd->dma_lo = map;
846 rd->dma_hi = map >> 32;
847 e->skb = skb;
848 rd->csum1_start = ETH_HLEN;
849 rd->csum2_start = ETH_HLEN;
850 rd->csum1 = 0;
851 rd->csum2 = 0;
852
853 wmb();
854
855 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
856 pci_unmap_addr_set(e, mapaddr, map);
857 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 858}
859
19a33d4e
SH		 860/* Resume receiving using existing skb,
861 * Note: DMA address is not changed by chip.
862 * MTU not changed while receiver active.
863 */
5a011447 864static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 865{
866 struct skge_rx_desc *rd = e->desc;
867
868 rd->csum2 = 0;
869 rd->csum2_start = ETH_HLEN;
870
871 wmb();
872
873 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
874}
875
876
877/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 878static void skge_rx_clean(struct skge_port *skge)
879{
880 struct skge_hw *hw = skge->hw;
881 struct skge_ring *ring = &skge->rx_ring;
882 struct skge_element *e;
883
19a33d4e
SH		 884 e = ring->start;
885 do {
baef58b1
SH		 886 struct skge_rx_desc *rd = e->desc;
887 rd->control = 0;
19a33d4e
SH		 888 if (e->skb) {
889 pci_unmap_single(hw->pdev,
890 pci_unmap_addr(e, mapaddr),
891 pci_unmap_len(e, maplen),
892 PCI_DMA_FROMDEVICE);
893 dev_kfree_skb(e->skb);
894 e->skb = NULL;
895 }
896 } while ((e = e->next) != ring->start);
baef58b1
SH		 897}
898
19a33d4e 899
baef58b1 900/* Allocate buffers for receive ring
19a33d4e 901 * For receive: to_clean is next received frame.
baef58b1 902 */
c54f9765 903static int skge_rx_fill(struct net_device *dev)
baef58b1 904{
c54f9765 905 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 906 struct skge_ring *ring = &skge->rx_ring;
907 struct skge_element *e;
baef58b1 908
19a33d4e
SH		 909 e = ring->start;
910 do {
383181ac 911 struct sk_buff *skb;
baef58b1 912
c54f9765
SH		 913 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
914 GFP_KERNEL);
19a33d4e
SH		 915 if (!skb)
916 return -ENOMEM;
917
383181ac
SH		 918 skb_reserve(skb, NET_IP_ALIGN);
919 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 920 } while ( (e = e->next) != ring->start);
baef58b1 921
19a33d4e
SH		 922 ring->to_clean = ring->start;
923 return 0;
baef58b1
SH		 924}
925
5d5c8e03
SH		 926static const char *skge_pause(enum pause_status status)
927{
928 switch(status) {
929 case FLOW_STAT_NONE:
930 return "none";
931 case FLOW_STAT_REM_SEND:
932 return "rx only";
933 case FLOW_STAT_LOC_SEND:
934 return "tx_only";
935 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
936 return "both";
937 default:
938 return "indeterminated";
939 }
940}
941
942
baef58b1
SH		 943static void skge_link_up(struct skge_port *skge)
944{
46a60f2d 945 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 946 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
947
baef58b1 948 netif_carrier_on(skge->netdev);
29b4e886 949 netif_wake_queue(skge->netdev);
baef58b1 950
5d5c8e03 951 if (netif_msg_link(skge)) {
baef58b1
SH		 952 printk(KERN_INFO PFX
953 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
954 skge->netdev->name, skge->speed,
955 skge->duplex == DUPLEX_FULL ? "full" : "half",
5d5c8e03
SH		 956 skge_pause(skge->flow_status));
957 }
baef58b1
SH		 958}
959
960static void skge_link_down(struct skge_port *skge)
961{
54cfb5aa 962 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 963 netif_carrier_off(skge->netdev);
964 netif_stop_queue(skge->netdev);
965
966 if (netif_msg_link(skge))
967 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
968}
969
a1bc9b87
SH		 970
971static void xm_link_down(struct skge_hw *hw, int port)
972{
973 struct net_device *dev = hw->dev[port];
974 struct skge_port *skge = netdev_priv(dev);
975 u16 cmd, msk;
976
977 if (hw->phy_type == SK_PHY_XMAC) {
978 msk = xm_read16(hw, port, XM_IMSK);
979 msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
980 xm_write16(hw, port, XM_IMSK, msk);
981 }
982
983 cmd = xm_read16(hw, port, XM_MMU_CMD);
984 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
985 xm_write16(hw, port, XM_MMU_CMD, cmd);
986 /* dummy read to ensure writing */
987 (void) xm_read16(hw, port, XM_MMU_CMD);
988
989 if (netif_carrier_ok(dev))
990 skge_link_down(skge);
991}
992
2cd8e5d3 993static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 994{
995 int i;
baef58b1 996
6b0c1480 997 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 998 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 999
64f6b64d
SH		 1000 if (hw->phy_type == SK_PHY_XMAC)
1001 goto ready;
1002
89bf5f23 1003 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 1004 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 1005 goto ready;
0781191c 1006 udelay(1);
baef58b1
SH		 1007 }
1008
2cd8e5d3 1009 return -ETIMEDOUT;
89bf5f23 1010 ready:
2cd8e5d3 1011 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 1012
2cd8e5d3
SH		 1013 return 0;
1014}
1015
1016static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1017{
1018 u16 v = 0;
1019 if (__xm_phy_read(hw, port, reg, &v))
1020 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1021 hw->dev[port]->name);
baef58b1
SH		 1022 return v;
1023}
1024
2cd8e5d3 1025static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1026{
1027 int i;
1028
6b0c1480 1029 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 1030 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 1031 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 1032 goto ready;
89bf5f23 1033 udelay(1);
baef58b1 1034 }
2cd8e5d3 1035 return -EIO;
baef58b1
SH		 1036
1037 ready:
6b0c1480 1038 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 1039 for (i = 0; i < PHY_RETRIES; i++) {
1040 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1041 return 0;
1042 udelay(1);
1043 }
1044 return -ETIMEDOUT;
baef58b1
SH		 1045}
1046
1047static void genesis_init(struct skge_hw *hw)
1048{
1049 /* set blink source counter */
1050 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1051 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1052
1053 /* configure mac arbiter */
1054 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1055
1056 /* configure mac arbiter timeout values */
1057 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1058 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1059 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1060 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1061
1062 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1063 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1064 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1065 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1066
1067 /* configure packet arbiter timeout */
1068 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1069 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1070 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1071 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1072 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1073}
1074
1075static void genesis_reset(struct skge_hw *hw, int port)
1076{
45bada65 1077 const u8 zero[8] = { 0 };
baef58b1 1078
46a60f2d
SH		 1079 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1080
baef58b1 1081 /* reset the statistics module */
6b0c1480
SH		 1082 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1083 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1084 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1085 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1086 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1087
89bf5f23 1088 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1089 if (hw->phy_type == SK_PHY_BCOM)
1090 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1091
45bada65 1092 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 1093}
1094
1095
45bada65
SH		 1096/* Convert mode to MII values */
1097static const u16 phy_pause_map[] = {
1098 [FLOW_MODE_NONE] = 0,
1099 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1100 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1101 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1102};
1103
4b67be99
SH		 1104/* special defines for FIBER (88E1011S only) */
1105static const u16 fiber_pause_map[] = {
1106 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1107 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1108 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1109 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1110};
1111
45bada65
SH		 1112
1113/* Check status of Broadcom phy link */
1114static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1115{
45bada65
SH		 1116 struct net_device *dev = hw->dev[port];
1117 struct skge_port *skge = netdev_priv(dev);
1118 u16 status;
1119
1120 /* read twice because of latch */
1121 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1122 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1123
45bada65 1124 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1125 xm_link_down(hw, port);
64f6b64d
SH		 1126 return;
1127 }
45bada65 1128
64f6b64d
SH		 1129 if (skge->autoneg == AUTONEG_ENABLE) {
1130 u16 lpa, aux;
45bada65 1131
64f6b64d
SH		 1132 if (!(status & PHY_ST_AN_OVER))
1133 return;
45bada65 1134
64f6b64d
SH		 1135 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1136 if (lpa & PHY_B_AN_RF) {
1137 printk(KERN_NOTICE PFX "%s: remote fault\n",
1138 dev->name);
1139 return;
1140 }
45bada65 1141
64f6b64d
SH		 1142 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1143
1144 /* Check Duplex mismatch */
1145 switch (aux & PHY_B_AS_AN_RES_MSK) {
1146 case PHY_B_RES_1000FD:
1147 skge->duplex = DUPLEX_FULL;
1148 break;
1149 case PHY_B_RES_1000HD:
1150 skge->duplex = DUPLEX_HALF;
1151 break;
1152 default:
1153 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1154 dev->name);
1155 return;
45bada65
SH		 1156 }
1157
64f6b64d
SH		 1158 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1159 switch (aux & PHY_B_AS_PAUSE_MSK) {
1160 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1161 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1162 break;
1163 case PHY_B_AS_PRR:
5d5c8e03 1164 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1165 break;
1166 case PHY_B_AS_PRT:
5d5c8e03 1167 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1168 break;
1169 default:
5d5c8e03 1170 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1171 }
1172 skge->speed = SPEED_1000;
45bada65 1173 }
64f6b64d
SH		 1174
1175 if (!netif_carrier_ok(dev))
1176 genesis_link_up(skge);
45bada65
SH		 1177}
1178
1179/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1180 * Phy on for 100 or 10Mbit operation
1181 */
64f6b64d 1182static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1183{
1184 struct skge_hw *hw = skge->hw;
1185 int port = skge->port;
baef58b1 1186 int i;
45bada65 1187 u16 id1, r, ext, ctl;
baef58b1
SH		 1188
1189 /* magic workaround patterns for Broadcom */
1190 static const struct {
1191 u16 reg;
1192 u16 val;
1193 } A1hack[] = {
1194 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1195 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1196 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1197 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1198 }, C0hack[] = {
1199 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1200 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1201 };
1202
45bada65
SH		 1203 /* read Id from external PHY (all have the same address) */
1204 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1205
1206 /* Optimize MDIO transfer by suppressing preamble. */
1207 r = xm_read16(hw, port, XM_MMU_CMD);
1208 r |= XM_MMU_NO_PRE;
1209 xm_write16(hw, port, XM_MMU_CMD,r);
1210
2c668514 1211 switch (id1) {
45bada65
SH		 1212 case PHY_BCOM_ID1_C0:
1213 /*
1214 * Workaround BCOM Errata for the C0 type.
1215 * Write magic patterns to reserved registers.
1216 */
1217 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1218 xm_phy_write(hw, port,
1219 C0hack[i].reg, C0hack[i].val);
1220
1221 break;
1222 case PHY_BCOM_ID1_A1:
1223 /*
1224 * Workaround BCOM Errata for the A1 type.
1225 * Write magic patterns to reserved registers.
1226 */
1227 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1228 xm_phy_write(hw, port,
1229 A1hack[i].reg, A1hack[i].val);
1230 break;
1231 }
1232
1233 /*
1234 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1235 * Disable Power Management after reset.
1236 */
1237 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1238 r |= PHY_B_AC_DIS_PM;
1239 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1240
1241 /* Dummy read */
1242 xm_read16(hw, port, XM_ISRC);
1243
1244 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1245 ctl = PHY_CT_SP1000; /* always 1000mbit */
1246
1247 if (skge->autoneg == AUTONEG_ENABLE) {
1248 /*
1249 * Workaround BCOM Errata #1 for the C5 type.
1250 * 1000Base-T Link Acquisition Failure in Slave Mode
1251 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1252 */
1253 u16 adv = PHY_B_1000C_RD;
1254 if (skge->advertising & ADVERTISED_1000baseT_Half)
1255 adv |= PHY_B_1000C_AHD;
1256 if (skge->advertising & ADVERTISED_1000baseT_Full)
1257 adv |= PHY_B_1000C_AFD;
1258 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1259
1260 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1261 } else {
1262 if (skge->duplex == DUPLEX_FULL)
1263 ctl |= PHY_CT_DUP_MD;
1264 /* Force to slave */
1265 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1266 }
1267
1268 /* Set autonegotiation pause parameters */
1269 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1270 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1271
1272 /* Handle Jumbo frames */
64f6b64d 1273 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1274 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1275 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1276
1277 ext |= PHY_B_PEC_HIGH_LA;
1278
1279 }
1280
1281 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1282 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1283
8f3f8193 1284 /* Use link status change interrupt */
45bada65 1285 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1286}
45bada65 1287
64f6b64d
SH		 1288static void xm_phy_init(struct skge_port *skge)
1289{
1290 struct skge_hw *hw = skge->hw;
1291 int port = skge->port;
1292 u16 ctrl = 0;
1293
1294 if (skge->autoneg == AUTONEG_ENABLE) {
1295 if (skge->advertising & ADVERTISED_1000baseT_Half)
1296 ctrl |= PHY_X_AN_HD;
1297 if (skge->advertising & ADVERTISED_1000baseT_Full)
1298 ctrl |= PHY_X_AN_FD;
1299
4b67be99 1300 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1301
1302 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1303
1304 /* Restart Auto-negotiation */
1305 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1306 } else {
1307 /* Set DuplexMode in Config register */
1308 if (skge->duplex == DUPLEX_FULL)
1309 ctrl |= PHY_CT_DUP_MD;
1310 /*
1311 * Do NOT enable Auto-negotiation here. This would hold
1312 * the link down because no IDLEs are transmitted
1313 */
1314 }
1315
1316 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1317
1318 /* Poll PHY for status changes */
1319 schedule_delayed_work(&skge->link_thread, LINK_HZ);
1320}
1321
1322static void xm_check_link(struct net_device *dev)
1323{
1324 struct skge_port *skge = netdev_priv(dev);
1325 struct skge_hw *hw = skge->hw;
1326 int port = skge->port;
1327 u16 status;
1328
1329 /* read twice because of latch */
1330 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1331 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1332
1333 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1334 xm_link_down(hw, port);
64f6b64d
SH		 1335 return;
1336 }
1337
1338 if (skge->autoneg == AUTONEG_ENABLE) {
1339 u16 lpa, res;
1340
1341 if (!(status & PHY_ST_AN_OVER))
1342 return;
1343
1344 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1345 if (lpa & PHY_B_AN_RF) {
1346 printk(KERN_NOTICE PFX "%s: remote fault\n",
1347 dev->name);
1348 return;
1349 }
1350
1351 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1352
1353 /* Check Duplex mismatch */
1354 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1355 case PHY_X_RS_FD:
1356 skge->duplex = DUPLEX_FULL;
1357 break;
1358 case PHY_X_RS_HD:
1359 skge->duplex = DUPLEX_HALF;
1360 break;
1361 default:
1362 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1363 dev->name);
1364 return;
1365 }
1366
1367 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1368 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1369 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1370 (lpa & PHY_X_P_SYM_MD))
1371 skge->flow_status = FLOW_STAT_SYMMETRIC;
1372 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1373 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1374 /* Enable PAUSE receive, disable PAUSE transmit */
1375 skge->flow_status = FLOW_STAT_REM_SEND;
1376 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1377 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1378 /* Disable PAUSE receive, enable PAUSE transmit */
1379 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1380 else
5d5c8e03 1381 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1382
1383 skge->speed = SPEED_1000;
1384 }
1385
1386 if (!netif_carrier_ok(dev))
1387 genesis_link_up(skge);
1388}
1389
1390/* Poll to check for link coming up.
1391 * Since internal PHY is wired to a level triggered pin, can't
1392 * get an interrupt when carrier is detected.
1393 */
c4028958 1394static void xm_link_timer(struct work_struct *work)
64f6b64d 1395{
c4028958
DH		 1396 struct skge_port *skge =
1397 container_of(work, struct skge_port, link_thread.work);
1398 struct net_device *dev = skge->netdev;
64f6b64d
SH		 1399 struct skge_hw *hw = skge->hw;
1400 int port = skge->port;
1401
1402 if (!netif_running(dev))
1403 return;
1404
1405 if (netif_carrier_ok(dev)) {
1406 xm_read16(hw, port, XM_ISRC);
1407 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1408 goto nochange;
1409 } else {
1410 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1411 goto nochange;
1412 xm_read16(hw, port, XM_ISRC);
1413 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1414 goto nochange;
1415 }
1416
1417 mutex_lock(&hw->phy_mutex);
1418 xm_check_link(dev);
1419 mutex_unlock(&hw->phy_mutex);
1420
1421nochange:
208491d8
SH		 1422 if (netif_running(dev))
1423 schedule_delayed_work(&skge->link_thread, LINK_HZ);
45bada65
SH		 1424}
1425
1426static void genesis_mac_init(struct skge_hw *hw, int port)
1427{
1428 struct net_device *dev = hw->dev[port];
1429 struct skge_port *skge = netdev_priv(dev);
1430 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1431 int i;
1432 u32 r;
1433 const u8 zero[6] = { 0 };
1434
0781191c
SH		 1435 for (i = 0; i < 10; i++) {
1436 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1437 MFF_SET_MAC_RST);
1438 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1439 goto reset_ok;
1440 udelay(1);
1441 }
baef58b1 1442
0781191c
SH		 1443 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1444
1445 reset_ok:
baef58b1 1446 /* Unreset the XMAC. */
6b0c1480 1447 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1448
1449 /*
1450 * Perform additional initialization for external PHYs,
1451 * namely for the 1000baseTX cards that use the XMAC's
1452 * GMII mode.
1453 */
64f6b64d
SH		 1454 if (hw->phy_type != SK_PHY_XMAC) {
1455 /* Take external Phy out of reset */
1456 r = skge_read32(hw, B2_GP_IO);
1457 if (port == 0)
1458 r |= GP_DIR_0|GP_IO_0;
1459 else
1460 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1461
64f6b64d 1462 skge_write32(hw, B2_GP_IO, r);
0781191c 1463
64f6b64d
SH		 1464 /* Enable GMII interface */
1465 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1466 }
89bf5f23 1467
89bf5f23 1468
64f6b64d
SH		 1469 switch(hw->phy_type) {
1470 case SK_PHY_XMAC:
1471 xm_phy_init(skge);
1472 break;
1473 case SK_PHY_BCOM:
1474 bcom_phy_init(skge);
1475 bcom_check_link(hw, port);
1476 }
89bf5f23 1477
45bada65
SH		 1478 /* Set Station Address */
1479 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1480
45bada65
SH		 1481 /* We don't use match addresses so clear */
1482 for (i = 1; i < 16; i++)
1483 xm_outaddr(hw, port, XM_EXM(i), zero);
1484
0781191c
SH		 1485 /* Clear MIB counters */
1486 xm_write16(hw, port, XM_STAT_CMD,
1487 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1488 /* Clear two times according to Errata #3 */
1489 xm_write16(hw, port, XM_STAT_CMD,
1490 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1491
45bada65
SH		 1492 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1493 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1494
1495 /* We don't need the FCS appended to the packet. */
1496 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1497 if (jumbo)
1498 r |= XM_RX_BIG_PK_OK;
89bf5f23 1499
45bada65 1500 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1501 /*
45bada65
SH		 1502 * If in manual half duplex mode the other side might be in
1503 * full duplex mode, so ignore if a carrier extension is not seen
1504 * on frames received
89bf5f23 1505 */
45bada65 1506 r |= XM_RX_DIS_CEXT;
baef58b1 1507 }
45bada65 1508 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1509
baef58b1
SH		 1510
1511 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1512 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1513
1514 /*
1515 * Bump up the transmit threshold. This helps hold off transmit
1516 * underruns when we're blasting traffic from both ports at once.
1517 */
1518 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1519
1520 /*
1521 * Enable the reception of all error frames. This is is
1522 * a necessary evil due to the design of the XMAC. The
1523 * XMAC's receive FIFO is only 8K in size, however jumbo
1524 * frames can be up to 9000 bytes in length. When bad
1525 * frame filtering is enabled, the XMAC's RX FIFO operates
1526 * in 'store and forward' mode. For this to work, the
1527 * entire frame has to fit into the FIFO, but that means
1528 * that jumbo frames larger than 8192 bytes will be
1529 * truncated. Disabling all bad frame filtering causes
1530 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1531 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1532 * RX FIFO as soon as the FIFO threshold is reached.
1533 */
45bada65 1534 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1535
baef58b1
SH		 1536
1537 /*
45bada65
SH		 1538 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1539 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1540 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1541 */
45bada65
SH		 1542 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1543
1544 /*
1545 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1546 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1547 * and 'Octets Tx OK Hi Cnt Ov'.
1548 */
1549 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1550
1551 /* Configure MAC arbiter */
1552 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1553
1554 /* configure timeout values */
1555 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1556 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1557 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1558 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1559
1560 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1561 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1562 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1563 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1564
1565 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1566 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1567 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1568 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1569
1570 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1571 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1572 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1573 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1574
45bada65 1575 if (jumbo) {
baef58b1 1576 /* Enable frame flushing if jumbo frames used */
6b0c1480 1577 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1578 } else {
1579 /* enable timeout timers if normal frames */
1580 skge_write16(hw, B3_PA_CTRL,
45bada65 1581 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1582 }
baef58b1
SH		 1583}
1584
1585static void genesis_stop(struct skge_port *skge)
1586{
1587 struct skge_hw *hw = skge->hw;
1588 int port = skge->port;
89bf5f23 1589 u32 reg;
baef58b1 1590
46a60f2d
SH		 1591 genesis_reset(hw, port);
1592
baef58b1
SH		 1593 /* Clear Tx packet arbiter timeout IRQ */
1594 skge_write16(hw, B3_PA_CTRL,
1595 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1596
1597 /*
8f3f8193 1598 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1599 * terminate if we don't flush the XMAC's transmit FIFO !
1600 */
6b0c1480
SH		 1601 xm_write32(hw, port, XM_MODE,
1602 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1603
1604
1605 /* Reset the MAC */
6b0c1480 1606 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1607
1608 /* For external PHYs there must be special handling */
64f6b64d
SH		 1609 if (hw->phy_type != SK_PHY_XMAC) {
1610 reg = skge_read32(hw, B2_GP_IO);
1611 if (port == 0) {
1612 reg |= GP_DIR_0;
1613 reg &= ~GP_IO_0;
1614 } else {
1615 reg |= GP_DIR_2;
1616 reg &= ~GP_IO_2;
1617 }
1618 skge_write32(hw, B2_GP_IO, reg);
1619 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1620 }
1621
6b0c1480
SH		 1622 xm_write16(hw, port, XM_MMU_CMD,
1623 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1624 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1625
6b0c1480 1626 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1627}
1628
1629
1630static void genesis_get_stats(struct skge_port *skge, u64 *data)
1631{
1632 struct skge_hw *hw = skge->hw;
1633 int port = skge->port;
1634 int i;
1635 unsigned long timeout = jiffies + HZ;
1636
6b0c1480 1637 xm_write16(hw, port,
baef58b1
SH		 1638 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1639
1640 /* wait for update to complete */
6b0c1480 1641 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1642 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1643 if (time_after(jiffies, timeout))
1644 break;
1645 udelay(10);
1646 }
1647
1648 /* special case for 64 bit octet counter */
6b0c1480
SH		 1649 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1650 | xm_read32(hw, port, XM_TXO_OK_LO);
1651 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1652 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1653
1654 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1655 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1656}
1657
1658static void genesis_mac_intr(struct skge_hw *hw, int port)
1659{
1660 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1661 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1662
7e676d91
SH		 1663 if (netif_msg_intr(skge))
1664 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1665 skge->netdev->name, status);
baef58b1 1666
a1bc9b87
SH		 1667 if (hw->phy_type == SK_PHY_XMAC &&
1668 (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
1669 xm_link_down(hw, port);
1670
baef58b1 1671 if (status & XM_IS_TXF_UR) {
6b0c1480 1672 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1673 ++skge->net_stats.tx_fifo_errors;
1674 }
1675 if (status & XM_IS_RXF_OV) {
6b0c1480 1676 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1677 ++skge->net_stats.rx_fifo_errors;
1678 }
1679}
1680
baef58b1
SH		 1681static void genesis_link_up(struct skge_port *skge)
1682{
1683 struct skge_hw *hw = skge->hw;
1684 int port = skge->port;
a1bc9b87 1685 u16 cmd, msk;
64f6b64d 1686 u32 mode;
baef58b1 1687
6b0c1480 1688 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1689
1690 /*
1691 * enabling pause frame reception is required for 1000BT
1692 * because the XMAC is not reset if the link is going down
1693 */
5d5c8e03
SH		 1694 if (skge->flow_status == FLOW_STAT_NONE ||
1695 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1696 /* Disable Pause Frame Reception */
baef58b1
SH		 1697 cmd |= XM_MMU_IGN_PF;
1698 else
1699 /* Enable Pause Frame Reception */
1700 cmd &= ~XM_MMU_IGN_PF;
1701
6b0c1480 1702 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1703
6b0c1480 1704 mode = xm_read32(hw, port, XM_MODE);
5d5c8e03
SH		 1705 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1706 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1707 /*
1708 * Configure Pause Frame Generation
1709 * Use internal and external Pause Frame Generation.
1710 * Sending pause frames is edge triggered.
1711 * Send a Pause frame with the maximum pause time if
1712 * internal oder external FIFO full condition occurs.
1713 * Send a zero pause time frame to re-start transmission.
1714 */
1715 /* XM_PAUSE_DA = '010000C28001' (default) */
1716 /* XM_MAC_PTIME = 0xffff (maximum) */
1717 /* remember this value is defined in big endian (!) */
6b0c1480 1718 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1719
1720 mode |= XM_PAUSE_MODE;
6b0c1480 1721 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1722 } else {
1723 /*
1724 * disable pause frame generation is required for 1000BT
1725 * because the XMAC is not reset if the link is going down
1726 */
1727 /* Disable Pause Mode in Mode Register */
1728 mode &= ~XM_PAUSE_MODE;
1729
6b0c1480 1730 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1731 }
1732
6b0c1480 1733 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87
SH		 1734 msk = XM_DEF_MSK;
1735 if (hw->phy_type != SK_PHY_XMAC)
1736 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1737
1738 xm_write16(hw, port, XM_IMSK, msk);
6b0c1480 1739 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1740
1741 /* get MMU Command Reg. */
6b0c1480 1742 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1743 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1744 cmd |= XM_MMU_GMII_FD;
1745
89bf5f23
SH		 1746 /*
1747 * Workaround BCOM Errata (#10523) for all BCom Phys
1748 * Enable Power Management after link up
1749 */
64f6b64d
SH		 1750 if (hw->phy_type == SK_PHY_BCOM) {
1751 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1752 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1753 & ~PHY_B_AC_DIS_PM);
1754 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1755 }
baef58b1
SH		 1756
1757 /* enable Rx/Tx */
6b0c1480 1758 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1759 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1760 skge_link_up(skge);
1761}
1762
1763
45bada65 1764static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1765{
1766 struct skge_hw *hw = skge->hw;
1767 int port = skge->port;
45bada65
SH		 1768 u16 isrc;
1769
1770 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1771 if (netif_msg_intr(skge))
1772 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1773 skge->netdev->name, isrc);
baef58b1 1774
45bada65
SH		 1775 if (isrc & PHY_B_IS_PSE)
1776 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1777 hw->dev[port]->name);
baef58b1
SH		 1778
1779 /* Workaround BCom Errata:
1780 * enable and disable loopback mode if "NO HCD" occurs.
1781 */
45bada65 1782 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1783 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1784 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1785 ctrl | PHY_CT_LOOP);
6b0c1480 1786 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1787 ctrl & ~PHY_CT_LOOP);
1788 }
1789
45bada65
SH		 1790 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1791 bcom_check_link(hw, port);
baef58b1 1792
baef58b1
SH		 1793}
1794
2cd8e5d3
SH		 1795static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1796{
1797 int i;
1798
1799 gma_write16(hw, port, GM_SMI_DATA, val);
1800 gma_write16(hw, port, GM_SMI_CTRL,
1801 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1802 for (i = 0; i < PHY_RETRIES; i++) {
1803 udelay(1);
1804
1805 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1806 return 0;
1807 }
1808
1809 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1810 hw->dev[port]->name);
1811 return -EIO;
1812}
1813
1814static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1815{
1816 int i;
1817
1818 gma_write16(hw, port, GM_SMI_CTRL,
1819 GM_SMI_CT_PHY_AD(hw->phy_addr)
1820 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1821
1822 for (i = 0; i < PHY_RETRIES; i++) {
1823 udelay(1);
1824 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1825 goto ready;
1826 }
1827
1828 return -ETIMEDOUT;
1829 ready:
1830 *val = gma_read16(hw, port, GM_SMI_DATA);
1831 return 0;
1832}
1833
1834static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1835{
1836 u16 v = 0;
1837 if (__gm_phy_read(hw, port, reg, &v))
1838 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1839 hw->dev[port]->name);
1840 return v;
1841}
1842
8f3f8193 1843/* Marvell Phy Initialization */
baef58b1
SH		 1844static void yukon_init(struct skge_hw *hw, int port)
1845{
1846 struct skge_port *skge = netdev_priv(hw->dev[port]);
1847 u16 ctrl, ct1000, adv;
baef58b1 1848
baef58b1 1849 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1850 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1851
1852 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1853 PHY_M_EC_MAC_S_MSK);
1854 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1855
c506a509 1856 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1857
6b0c1480 1858 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1859 }
1860
6b0c1480 1861 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1862 if (skge->autoneg == AUTONEG_DISABLE)
1863 ctrl &= ~PHY_CT_ANE;
1864
1865 ctrl |= PHY_CT_RESET;
6b0c1480 1866 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1867
1868 ctrl = 0;
1869 ct1000 = 0;
b18f2091 1870 adv = PHY_AN_CSMA;
baef58b1
SH		 1871
1872 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1873 if (hw->copper) {
baef58b1
SH		 1874 if (skge->advertising & ADVERTISED_1000baseT_Full)
1875 ct1000 |= PHY_M_1000C_AFD;
1876 if (skge->advertising & ADVERTISED_1000baseT_Half)
1877 ct1000 |= PHY_M_1000C_AHD;
1878 if (skge->advertising & ADVERTISED_100baseT_Full)
1879 adv |= PHY_M_AN_100_FD;
1880 if (skge->advertising & ADVERTISED_100baseT_Half)
1881 adv |= PHY_M_AN_100_HD;
1882 if (skge->advertising & ADVERTISED_10baseT_Full)
1883 adv |= PHY_M_AN_10_FD;
1884 if (skge->advertising & ADVERTISED_10baseT_Half)
1885 adv |= PHY_M_AN_10_HD;
baef58b1 1886
4b67be99
SH		 1887 /* Set Flow-control capabilities */
1888 adv |= phy_pause_map[skge->flow_control];
1889 } else {
1890 if (skge->advertising & ADVERTISED_1000baseT_Full)
1891 adv |= PHY_M_AN_1000X_AFD;
1892 if (skge->advertising & ADVERTISED_1000baseT_Half)
1893 adv |= PHY_M_AN_1000X_AHD;
1894
1895 adv |= fiber_pause_map[skge->flow_control];
1896 }
45bada65 1897
baef58b1
SH		 1898 /* Restart Auto-negotiation */
1899 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1900 } else {
1901 /* forced speed/duplex settings */
1902 ct1000 = PHY_M_1000C_MSE;
1903
1904 if (skge->duplex == DUPLEX_FULL)
1905 ctrl |= PHY_CT_DUP_MD;
1906
1907 switch (skge->speed) {
1908 case SPEED_1000:
1909 ctrl |= PHY_CT_SP1000;
1910 break;
1911 case SPEED_100:
1912 ctrl |= PHY_CT_SP100;
1913 break;
1914 }
1915
1916 ctrl |= PHY_CT_RESET;
1917 }
1918
c506a509 1919 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1920
6b0c1480
SH		 1921 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1922 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1923
baef58b1
SH		 1924 /* Enable phy interrupt on autonegotiation complete (or link up) */
1925 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1926 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1927 else
4cde06ed 1928 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1929}
1930
1931static void yukon_reset(struct skge_hw *hw, int port)
1932{
6b0c1480
SH		 1933 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1934 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1935 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1936 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1937 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1938
6b0c1480
SH		 1939 gma_write16(hw, port, GM_RX_CTRL,
1940 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1941 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1942}
1943
c8868611
SH		 1944/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1945static int is_yukon_lite_a0(struct skge_hw *hw)
1946{
1947 u32 reg;
1948 int ret;
1949
1950 if (hw->chip_id != CHIP_ID_YUKON)
1951 return 0;
1952
1953 reg = skge_read32(hw, B2_FAR);
1954 skge_write8(hw, B2_FAR + 3, 0xff);
1955 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1956 skge_write32(hw, B2_FAR, reg);
1957 return ret;
1958}
1959
baef58b1
SH		 1960static void yukon_mac_init(struct skge_hw *hw, int port)
1961{
1962 struct skge_port *skge = netdev_priv(hw->dev[port]);
1963 int i;
1964 u32 reg;
1965 const u8 *addr = hw->dev[port]->dev_addr;
1966
1967 /* WA code for COMA mode -- set PHY reset */
1968 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1969 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1970 reg = skge_read32(hw, B2_GP_IO);
1971 reg |= GP_DIR_9 | GP_IO_9;
1972 skge_write32(hw, B2_GP_IO, reg);
1973 }
baef58b1
SH		 1974
1975 /* hard reset */
6b0c1480
SH		 1976 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1977 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1978
1979 /* WA code for COMA mode -- clear PHY reset */
1980 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1981 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1982 reg = skge_read32(hw, B2_GP_IO);
1983 reg |= GP_DIR_9;
1984 reg &= ~GP_IO_9;
1985 skge_write32(hw, B2_GP_IO, reg);
1986 }
baef58b1
SH		 1987
1988 /* Set hardware config mode */
1989 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1990 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 1991 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 1992
1993 /* Clear GMC reset */
6b0c1480
SH		 1994 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1995 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1996 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 1997
baef58b1
SH		 1998 if (skge->autoneg == AUTONEG_DISABLE) {
1999 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 2000 gma_write16(hw, port, GM_GP_CTRL,
2001 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 2002
2003 switch (skge->speed) {
2004 case SPEED_1000:
564f9abb 2005 reg &= ~GM_GPCR_SPEED_100;
baef58b1 2006 reg |= GM_GPCR_SPEED_1000;
564f9abb 2007 break;
baef58b1 2008 case SPEED_100:
564f9abb 2009 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 2010 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 2011 break;
2012 case SPEED_10:
2013 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2014 break;
baef58b1
SH		 2015 }
2016
2017 if (skge->duplex == DUPLEX_FULL)
2018 reg |= GM_GPCR_DUP_FULL;
2019 } else
2020 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 2021
baef58b1
SH		 2022 switch (skge->flow_control) {
2023 case FLOW_MODE_NONE:
6b0c1480 2024 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 2025 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2026 break;
2027 case FLOW_MODE_LOC_SEND:
2028 /* disable Rx flow-control */
2029 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 2030 break;
2031 case FLOW_MODE_SYMMETRIC:
2032 case FLOW_MODE_SYM_OR_REM:
2033 /* enable Tx & Rx flow-control */
2034 break;
baef58b1
SH		 2035 }
2036
6b0c1480 2037 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 2038 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2039
baef58b1 2040 yukon_init(hw, port);
baef58b1
SH		 2041
2042 /* MIB clear */
6b0c1480
SH		 2043 reg = gma_read16(hw, port, GM_PHY_ADDR);
2044 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 2045
2046 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 2047 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2048 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 2049
2050 /* transmit control */
6b0c1480 2051 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 2052
2053 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 2054 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 2055 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2056
2057 /* transmit flow control */
6b0c1480 2058 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 2059
2060 /* transmit parameter */
6b0c1480 2061 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 2062 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2063 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2064 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2065
2066 /* serial mode register */
2067 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2068 if (hw->dev[port]->mtu > 1500)
2069 reg |= GM_SMOD_JUMBO_ENA;
2070
6b0c1480 2071 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2072
2073 /* physical address: used for pause frames */
6b0c1480 2074 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2075 /* virtual address for data */
6b0c1480 2076 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2077
2078 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2079 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2080 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2081 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2082
2083 /* Initialize Mac Fifo */
2084
2085 /* Configure Rx MAC FIFO */
6b0c1480 2086 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2087 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2088
2089 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2090 if (is_yukon_lite_a0(hw))
baef58b1 2091 reg &= ~GMF_RX_F_FL_ON;
c8868611 2092
6b0c1480
SH		 2093 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2094 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2095 /*
2096 * because Pause Packet Truncation in GMAC is not working
2097 * we have to increase the Flush Threshold to 64 bytes
2098 * in order to flush pause packets in Rx FIFO on Yukon-1
2099 */
2100 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2101
2102 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2103 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2104 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2105}
2106
355ec572
SH		 2107/* Go into power down mode */
2108static void yukon_suspend(struct skge_hw *hw, int port)
2109{
2110 u16 ctrl;
2111
2112 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2113 ctrl |= PHY_M_PC_POL_R_DIS;
2114 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2115
2116 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2117 ctrl |= PHY_CT_RESET;
2118 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2119
2120 /* switch IEEE compatible power down mode on */
2121 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2122 ctrl |= PHY_CT_PDOWN;
2123 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2124}
2125
baef58b1
SH		 2126static void yukon_stop(struct skge_port *skge)
2127{
2128 struct skge_hw *hw = skge->hw;
2129 int port = skge->port;
2130
46a60f2d
SH		 2131 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2132 yukon_reset(hw, port);
baef58b1 2133
6b0c1480
SH		 2134 gma_write16(hw, port, GM_GP_CTRL,
2135 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2136 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2137 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2138
355ec572 2139 yukon_suspend(hw, port);
46a60f2d 2140
baef58b1 2141 /* set GPHY Control reset */
46a60f2d
SH		 2142 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2143 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2144}
2145
2146static void yukon_get_stats(struct skge_port *skge, u64 *data)
2147{
2148 struct skge_hw *hw = skge->hw;
2149 int port = skge->port;
2150 int i;
2151
6b0c1480
SH		 2152 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2153 | gma_read32(hw, port, GM_TXO_OK_LO);
2154 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2155 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2156
2157 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2158 data[i] = gma_read32(hw, port,
baef58b1
SH		 2159 skge_stats[i].gma_offset);
2160}
2161
2162static void yukon_mac_intr(struct skge_hw *hw, int port)
2163{
7e676d91
SH		 2164 struct net_device *dev = hw->dev[port];
2165 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2166 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2167
7e676d91
SH		 2168 if (netif_msg_intr(skge))
2169 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2170 dev->name, status);
2171
baef58b1
SH		 2172 if (status & GM_IS_RX_FF_OR) {
2173 ++skge->net_stats.rx_fifo_errors;
d8a09943 2174 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2175 }
d8a09943 2176
baef58b1
SH		 2177 if (status & GM_IS_TX_FF_UR) {
2178 ++skge->net_stats.tx_fifo_errors;
d8a09943 2179 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2180 }
2181
2182}
2183
2184static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2185{
95566065 2186 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2187 case PHY_M_PS_SPEED_1000:
2188 return SPEED_1000;
2189 case PHY_M_PS_SPEED_100:
2190 return SPEED_100;
2191 default:
2192 return SPEED_10;
2193 }
2194}
2195
2196static void yukon_link_up(struct skge_port *skge)
2197{
2198 struct skge_hw *hw = skge->hw;
2199 int port = skge->port;
2200 u16 reg;
2201
baef58b1 2202 /* Enable Transmit FIFO Underrun */
46a60f2d 2203 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2204
6b0c1480 2205 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2206 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2207 reg |= GM_GPCR_DUP_FULL;
2208
2209 /* enable Rx/Tx */
2210 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2211 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2212
4cde06ed 2213 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2214 skge_link_up(skge);
2215}
2216
2217static void yukon_link_down(struct skge_port *skge)
2218{
2219 struct skge_hw *hw = skge->hw;
2220 int port = skge->port;
d8a09943 2221 u16 ctrl;
baef58b1 2222
d8a09943
SH		 2223 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2224 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2225 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2226
5d5c8e03
SH		 2227 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2228 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2229 ctrl |= PHY_M_AN_ASP;
baef58b1 2230 /* restore Asymmetric Pause bit */
5d5c8e03 2231 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2232 }
2233
baef58b1
SH		 2234 skge_link_down(skge);
2235
2236 yukon_init(hw, port);
2237}
2238
2239static void yukon_phy_intr(struct skge_port *skge)
2240{
2241 struct skge_hw *hw = skge->hw;
2242 int port = skge->port;
2243 const char *reason = NULL;
2244 u16 istatus, phystat;
2245
6b0c1480
SH		 2246 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2247 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 2248
2249 if (netif_msg_intr(skge))
2250 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2251 skge->netdev->name, istatus, phystat);
baef58b1
SH		 2252
2253 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2254 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2255 & PHY_M_AN_RF) {
2256 reason = "remote fault";
2257 goto failed;
2258 }
2259
c506a509 2260 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2261 reason = "master/slave fault";
2262 goto failed;
2263 }
2264
2265 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2266 reason = "speed/duplex";
2267 goto failed;
2268 }
2269
2270 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2271 ? DUPLEX_FULL : DUPLEX_HALF;
2272 skge->speed = yukon_speed(hw, phystat);
2273
baef58b1
SH		 2274 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2275 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2276 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2277 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2278 break;
2279 case PHY_M_PS_RX_P_EN:
5d5c8e03 2280 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2281 break;
2282 case PHY_M_PS_TX_P_EN:
5d5c8e03 2283 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2284 break;
2285 default:
5d5c8e03 2286 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2287 }
2288
5d5c8e03 2289 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2290 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2291 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2292 else
6b0c1480 2293 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2294 yukon_link_up(skge);
2295 return;
2296 }
2297
2298 if (istatus & PHY_M_IS_LSP_CHANGE)
2299 skge->speed = yukon_speed(hw, phystat);
2300
2301 if (istatus & PHY_M_IS_DUP_CHANGE)
2302 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2303 if (istatus & PHY_M_IS_LST_CHANGE) {
2304 if (phystat & PHY_M_PS_LINK_UP)
2305 yukon_link_up(skge);
2306 else
2307 yukon_link_down(skge);
2308 }
2309 return;
2310 failed:
2311 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2312 skge->netdev->name, reason);
2313
2314 /* XXX restart autonegotiation? */
2315}
2316
ee294dcd
SH		 2317static void skge_phy_reset(struct skge_port *skge)
2318{
2319 struct skge_hw *hw = skge->hw;
2320 int port = skge->port;
aae343d4 2321 struct net_device *dev = hw->dev[port];
ee294dcd
SH		 2322
2323 netif_stop_queue(skge->netdev);
2324 netif_carrier_off(skge->netdev);
2325
d85b514f 2326 mutex_lock(&hw->phy_mutex);
ee294dcd
SH		 2327 if (hw->chip_id == CHIP_ID_GENESIS) {
2328 genesis_reset(hw, port);
2329 genesis_mac_init(hw, port);
2330 } else {
2331 yukon_reset(hw, port);
2332 yukon_init(hw, port);
2333 }
d85b514f 2334 mutex_unlock(&hw->phy_mutex);
75814090
SH		 2335
2336 dev->set_multicast_list(dev);
ee294dcd
SH		 2337}
2338
2cd8e5d3
SH		 2339/* Basic MII support */
2340static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2341{
2342 struct mii_ioctl_data *data = if_mii(ifr);
2343 struct skge_port *skge = netdev_priv(dev);
2344 struct skge_hw *hw = skge->hw;
2345 int err = -EOPNOTSUPP;
2346
2347 if (!netif_running(dev))
2348 return -ENODEV; /* Phy still in reset */
2349
2350 switch(cmd) {
2351 case SIOCGMIIPHY:
2352 data->phy_id = hw->phy_addr;
2353
2354 /* fallthru */
2355 case SIOCGMIIREG: {
2356 u16 val = 0;
d85b514f 2357 mutex_lock(&hw->phy_mutex);
2cd8e5d3
SH		 2358 if (hw->chip_id == CHIP_ID_GENESIS)
2359 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2360 else
2361 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
d85b514f 2362 mutex_unlock(&hw->phy_mutex);
2cd8e5d3
SH		 2363 data->val_out = val;
2364 break;
2365 }
2366
2367 case SIOCSMIIREG:
2368 if (!capable(CAP_NET_ADMIN))
2369 return -EPERM;
2370
d85b514f 2371 mutex_lock(&hw->phy_mutex);
2cd8e5d3
SH		 2372 if (hw->chip_id == CHIP_ID_GENESIS)
2373 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2374 data->val_in);
2375 else
2376 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2377 data->val_in);
d85b514f 2378 mutex_unlock(&hw->phy_mutex);
2cd8e5d3
SH		 2379 break;
2380 }
2381 return err;
2382}
2383
baef58b1
SH		 2384static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2385{
2386 u32 end;
2387
2388 start /= 8;
2389 len /= 8;
2390 end = start + len - 1;
2391
2392 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2393 skge_write32(hw, RB_ADDR(q, RB_START), start);
2394 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2395 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2396 skge_write32(hw, RB_ADDR(q, RB_END), end);
2397
2398 if (q == Q_R1 || q == Q_R2) {
2399 /* Set thresholds on receive queue's */
2400 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2401 start + (2*len)/3);
2402 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2403 start + (len/3));
2404 } else {
2405 /* Enable store & forward on Tx queue's because
2406 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2407 */
2408 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2409 }
2410
2411 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2412}
2413
2414/* Setup Bus Memory Interface */
2415static void skge_qset(struct skge_port *skge, u16 q,
2416 const struct skge_element *e)
2417{
2418 struct skge_hw *hw = skge->hw;
2419 u32 watermark = 0x600;
2420 u64 base = skge->dma + (e->desc - skge->mem);
2421
2422 /* optimization to reduce window on 32bit/33mhz */
2423 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2424 watermark /= 2;
2425
2426 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2427 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2428 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2429 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2430}
2431
2432static int skge_up(struct net_device *dev)
2433{
2434 struct skge_port *skge = netdev_priv(dev);
2435 struct skge_hw *hw = skge->hw;
2436 int port = skge->port;
2437 u32 chunk, ram_addr;
2438 size_t rx_size, tx_size;
2439 int err;
2440
fae87592
SH		 2441 if (!is_valid_ether_addr(dev->dev_addr))
2442 return -EINVAL;
2443
baef58b1
SH		 2444 if (netif_msg_ifup(skge))
2445 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2446
19a33d4e 2447 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2448 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2449 else
2450 skge->rx_buf_size = RX_BUF_SIZE;
2451
2452
baef58b1
SH		 2453 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2454 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2455 skge->mem_size = tx_size + rx_size;
2456 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2457 if (!skge->mem)
2458 return -ENOMEM;
2459
c3da1447
SH		 2460 BUG_ON(skge->dma & 7);
2461
2462 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
1479d13c 2463 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
c3da1447
SH		 2464 err = -EINVAL;
2465 goto free_pci_mem;
2466 }
2467
baef58b1
SH		 2468 memset(skge->mem, 0, skge->mem_size);
2469
203babb6
SH		 2470 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2471 if (err)
baef58b1
SH		 2472 goto free_pci_mem;
2473
c54f9765 2474 err = skge_rx_fill(dev);
19a33d4e 2475 if (err)
baef58b1
SH		 2476 goto free_rx_ring;
2477
203babb6
SH		 2478 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2479 skge->dma + rx_size);
2480 if (err)
baef58b1
SH		 2481 goto free_rx_ring;
2482
8f3f8193 2483 /* Initialize MAC */
d85b514f 2484 mutex_lock(&hw->phy_mutex);
baef58b1
SH		 2485 if (hw->chip_id == CHIP_ID_GENESIS)
2486 genesis_mac_init(hw, port);
2487 else
2488 yukon_mac_init(hw, port);
d85b514f 2489 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 2490
2491 /* Configure RAMbuffers */
981d0377 2492 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2493 ram_addr = hw->ram_offset + 2 * chunk * port;
2494
2495 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2496 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2497
2498 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2499 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2500 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2501
2502 /* Start receiver BMU */
2503 wmb();
2504 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2505 skge_led(skge, LED_MODE_ON);
baef58b1 2506
239e44e1 2507 netif_poll_enable(dev);
baef58b1
SH		 2508 return 0;
2509
2510 free_rx_ring:
2511 skge_rx_clean(skge);
2512 kfree(skge->rx_ring.start);
2513 free_pci_mem:
2514 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2515 skge->mem = NULL;
baef58b1
SH		 2516
2517 return err;
2518}
2519
2520static int skge_down(struct net_device *dev)
2521{
2522 struct skge_port *skge = netdev_priv(dev);
2523 struct skge_hw *hw = skge->hw;
2524 int port = skge->port;
2525
7731a4ea
SH		 2526 if (skge->mem == NULL)
2527 return 0;
2528
baef58b1
SH		 2529 if (netif_msg_ifdown(skge))
2530 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2531
2532 netif_stop_queue(dev);
64f6b64d 2533 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
208491d8 2534 cancel_delayed_work(&skge->link_thread);
baef58b1 2535
46a60f2d
SH		 2536 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2537 if (hw->chip_id == CHIP_ID_GENESIS)
2538 genesis_stop(skge);
2539 else
2540 yukon_stop(skge);
2541
baef58b1
SH		 2542 /* Stop transmitter */
2543 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2544 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2545 RB_RST_SET|RB_DIS_OP_MD);
2546
baef58b1
SH		 2547
2548 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2549 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2550 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2551
2552 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2553 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2554 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2555
2556 /* Reset PCI FIFO */
2557 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2558 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2559
2560 /* Reset the RAM Buffer async Tx queue */
2561 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2562 /* stop receiver */
2563 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2564 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2565 RB_RST_SET|RB_DIS_OP_MD);
2566 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2567
2568 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2569 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2570 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2571 } else {
6b0c1480
SH		 2572 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2573 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2574 }
2575
6abebb53 2576 skge_led(skge, LED_MODE_OFF);
baef58b1 2577
239e44e1 2578 netif_poll_disable(dev);
513f533e 2579 skge_tx_clean(dev);
baef58b1
SH		 2580 skge_rx_clean(skge);
2581
2582 kfree(skge->rx_ring.start);
2583 kfree(skge->tx_ring.start);
2584 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2585 skge->mem = NULL;
baef58b1
SH		 2586 return 0;
2587}
2588
29b4e886
SH		 2589static inline int skge_avail(const struct skge_ring *ring)
2590{
2591 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2592 + (ring->to_clean - ring->to_use) - 1;
2593}
2594
baef58b1
SH		 2595static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2596{
2597 struct skge_port *skge = netdev_priv(dev);
2598 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2599 struct skge_element *e;
2600 struct skge_tx_desc *td;
2601 int i;
2602 u32 control, len;
2603 u64 map;
baef58b1 2604
5b057c6b 2605 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2606 return NETDEV_TX_OK;
2607
513f533e 2608 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2609 return NETDEV_TX_BUSY;
baef58b1 2610
7c442fa1 2611 e = skge->tx_ring.to_use;
baef58b1 2612 td = e->desc;
7c442fa1 2613 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2614 e->skb = skb;
2615 len = skb_headlen(skb);
2616 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2617 pci_unmap_addr_set(e, mapaddr, map);
2618 pci_unmap_len_set(e, maplen, len);
2619
2620 td->dma_lo = map;
2621 td->dma_hi = map >> 32;
2622
84fa7933 2623 if (skb->ip_summed == CHECKSUM_PARTIAL) {
baef58b1
SH		 2624 int offset = skb->h.raw - skb->data;
2625
2626 /* This seems backwards, but it is what the sk98lin
2627 * does. Looks like hardware is wrong?
2628 */
ea182d4a 2629 if (skb->h.ipiph->protocol == IPPROTO_UDP
981d0377 2630 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2631 control = BMU_TCP_CHECK;
2632 else
2633 control = BMU_UDP_CHECK;
2634
2635 td->csum_offs = 0;
2636 td->csum_start = offset;
ff1dcadb 2637 td->csum_write = offset + skb->csum_offset;
baef58b1
SH		 2638 } else
2639 control = BMU_CHECK;
2640
2641 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2642 control |= BMU_EOF| BMU_IRQ_EOF;
2643 else {
2644 struct skge_tx_desc *tf = td;
2645
2646 control |= BMU_STFWD;
2647 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2648 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2649
2650 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2651 frag->size, PCI_DMA_TODEVICE);
2652
2653 e = e->next;
7c442fa1 2654 e->skb = skb;
baef58b1 2655 tf = e->desc;
7c442fa1
SH		 2656 BUG_ON(tf->control & BMU_OWN);
2657
baef58b1
SH		 2658 tf->dma_lo = map;
2659 tf->dma_hi = (u64) map >> 32;
2660 pci_unmap_addr_set(e, mapaddr, map);
2661 pci_unmap_len_set(e, maplen, frag->size);
2662
2663 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2664 }
2665 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2666 }
2667 /* Make sure all the descriptors written */
2668 wmb();
2669 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2670 wmb();
2671
2672 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2673
7c442fa1 2674 if (unlikely(netif_msg_tx_queued(skge)))
0b2d7fea 2675 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
7c442fa1 2676 dev->name, e - skge->tx_ring.start, skb->len);
baef58b1 2677
7c442fa1 2678 skge->tx_ring.to_use = e->next;
9db96479 2679 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
baef58b1
SH		 2680 pr_debug("%s: transmit queue full\n", dev->name);
2681 netif_stop_queue(dev);
2682 }
2683
c68ce71a
SH		 2684 dev->trans_start = jiffies;
2685
baef58b1
SH		 2686 return NETDEV_TX_OK;
2687}
2688
7c442fa1
SH		 2689
2690/* Free resources associated with this reing element */
2691static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2692 u32 control)
866b4f3e
SH		 2693{
2694 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2695
7c442fa1 2696 BUG_ON(!e->skb);
866b4f3e 2697
7c442fa1
SH		 2698 /* skb header vs. fragment */
2699 if (control & BMU_STF)
866b4f3e 2700 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
7c442fa1
SH		 2701 pci_unmap_len(e, maplen),
2702 PCI_DMA_TODEVICE);
2703 else
2704 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2705 pci_unmap_len(e, maplen),
2706 PCI_DMA_TODEVICE);
866b4f3e 2707
7c442fa1
SH		 2708 if (control & BMU_EOF) {
2709 if (unlikely(netif_msg_tx_done(skge)))
2710 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2711 skge->netdev->name, e - skge->tx_ring.start);
866b4f3e 2712
513f533e 2713 dev_kfree_skb(e->skb);
baef58b1 2714 }
7c442fa1 2715 e->skb = NULL;
baef58b1
SH		 2716}
2717
7c442fa1 2718/* Free all buffers in transmit ring */
513f533e 2719static void skge_tx_clean(struct net_device *dev)
baef58b1 2720{
513f533e 2721 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2722 struct skge_element *e;
baef58b1 2723
513f533e 2724 netif_tx_lock_bh(dev);
7c442fa1
SH		 2725 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2726 struct skge_tx_desc *td = e->desc;
2727 skge_tx_free(skge, e, td->control);
2728 td->control = 0;
2729 }
2730
2731 skge->tx_ring.to_clean = e;
513f533e
SH		 2732 netif_wake_queue(dev);
2733 netif_tx_unlock_bh(dev);
baef58b1
SH		 2734}
2735
2736static void skge_tx_timeout(struct net_device *dev)
2737{
2738 struct skge_port *skge = netdev_priv(dev);
2739
2740 if (netif_msg_timer(skge))
2741 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2742
2743 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2744 skge_tx_clean(dev);
baef58b1
SH		 2745}
2746
2747static int skge_change_mtu(struct net_device *dev, int new_mtu)
2748{
7731a4ea 2749 int err;
baef58b1 2750
95566065 2751 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2752 return -EINVAL;
2753
7731a4ea
SH		 2754 if (!netif_running(dev)) {
2755 dev->mtu = new_mtu;
2756 return 0;
2757 }
2758
2759 skge_down(dev);
baef58b1 2760
19a33d4e 2761 dev->mtu = new_mtu;
7731a4ea
SH		 2762
2763 err = skge_up(dev);
2764 if (err)
2765 dev_close(dev);
baef58b1
SH		 2766
2767 return err;
2768}
2769
c4cd29d2
SH		 2770static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2771
2772static void genesis_add_filter(u8 filter[8], const u8 *addr)
2773{
2774 u32 crc, bit;
2775
2776 crc = ether_crc_le(ETH_ALEN, addr);
2777 bit = ~crc & 0x3f;
2778 filter[bit/8] |= 1 << (bit%8);
2779}
2780
baef58b1
SH		 2781static void genesis_set_multicast(struct net_device *dev)
2782{
2783 struct skge_port *skge = netdev_priv(dev);
2784 struct skge_hw *hw = skge->hw;
2785 int port = skge->port;
2786 int i, count = dev->mc_count;
2787 struct dev_mc_list *list = dev->mc_list;
2788 u32 mode;
2789 u8 filter[8];
2790
6b0c1480 2791 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2792 mode |= XM_MD_ENA_HASH;
2793 if (dev->flags & IFF_PROMISC)
2794 mode |= XM_MD_ENA_PROM;
2795 else
2796 mode &= ~XM_MD_ENA_PROM;
2797
2798 if (dev->flags & IFF_ALLMULTI)
2799 memset(filter, 0xff, sizeof(filter));
2800 else {
2801 memset(filter, 0, sizeof(filter));
c4cd29d2
SH		 2802
2803 if (skge->flow_status == FLOW_STAT_REM_SEND
2804 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2805 genesis_add_filter(filter, pause_mc_addr);
2806
2807 for (i = 0; list && i < count; i++, list = list->next)
2808 genesis_add_filter(filter, list->dmi_addr);
baef58b1
SH		 2809 }
2810
6b0c1480 2811 xm_write32(hw, port, XM_MODE, mode);
45bada65 2812 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2813}
2814
c4cd29d2
SH		 2815static void yukon_add_filter(u8 filter[8], const u8 *addr)
2816{
2817 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2818 filter[bit/8] |= 1 << (bit%8);
2819}
2820
baef58b1
SH		 2821static void yukon_set_multicast(struct net_device *dev)
2822{
2823 struct skge_port *skge = netdev_priv(dev);
2824 struct skge_hw *hw = skge->hw;
2825 int port = skge->port;
2826 struct dev_mc_list *list = dev->mc_list;
c4cd29d2
SH		 2827 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
2828 || skge->flow_status == FLOW_STAT_SYMMETRIC);
baef58b1
SH		 2829 u16 reg;
2830 u8 filter[8];
2831
2832 memset(filter, 0, sizeof(filter));
2833
6b0c1480 2834 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2835 reg |= GM_RXCR_UCF_ENA;
2836
8f3f8193 2837 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2838 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2839 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2840 memset(filter, 0xff, sizeof(filter));
c4cd29d2 2841 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
baef58b1
SH		 2842 reg &= ~GM_RXCR_MCF_ENA;
2843 else {
2844 int i;
2845 reg |= GM_RXCR_MCF_ENA;
2846
c4cd29d2
SH		 2847 if (rx_pause)
2848 yukon_add_filter(filter, pause_mc_addr);
2849
2850 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2851 yukon_add_filter(filter, list->dmi_addr);
baef58b1
SH		 2852 }
2853
2854
6b0c1480 2855 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2856 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2857 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2858 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2859 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2860 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2861 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2862 (u16)filter[6] | ((u16)filter[7] << 8));
2863
6b0c1480 2864 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2865}
2866
383181ac
SH		 2867static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2868{
2869 if (hw->chip_id == CHIP_ID_GENESIS)
2870 return status >> XMR_FS_LEN_SHIFT;
2871 else
2872 return status >> GMR_FS_LEN_SHIFT;
2873}
2874
baef58b1
SH		 2875static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2876{
2877 if (hw->chip_id == CHIP_ID_GENESIS)
2878 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2879 else
2880 return (status & GMR_FS_ANY_ERR) ||
2881 (status & GMR_FS_RX_OK) == 0;
2882}
2883
19a33d4e
SH		 2884
2885/* Get receive buffer from descriptor.
2886 * Handles copy of small buffers and reallocation failures
2887 */
c54f9765
SH		 2888static struct sk_buff *skge_rx_get(struct net_device *dev,
2889 struct skge_element *e,
2890 u32 control, u32 status, u16 csum)
19a33d4e 2891{
c54f9765 2892 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 2893 struct sk_buff *skb;
2894 u16 len = control & BMU_BBC;
2895
2896 if (unlikely(netif_msg_rx_status(skge)))
2897 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
c54f9765 2898 dev->name, e - skge->rx_ring.start,
383181ac
SH		 2899 status, len);
2900
2901 if (len > skge->rx_buf_size)
2902 goto error;
2903
2904 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2905 goto error;
2906
2907 if (bad_phy_status(skge->hw, status))
2908 goto error;
2909
2910 if (phy_length(skge->hw, status) != len)
2911 goto error;
19a33d4e
SH		 2912
2913 if (len < RX_COPY_THRESHOLD) {
c54f9765 2914 skb = netdev_alloc_skb(dev, len + 2);
383181ac
SH		 2915 if (!skb)
2916 goto resubmit;
19a33d4e 2917
383181ac 2918 skb_reserve(skb, 2);
19a33d4e
SH		 2919 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2920 pci_unmap_addr(e, mapaddr),
2921 len, PCI_DMA_FROMDEVICE);
383181ac 2922 memcpy(skb->data, e->skb->data, len);
19a33d4e
SH		 2923 pci_dma_sync_single_for_device(skge->hw->pdev,
2924 pci_unmap_addr(e, mapaddr),
2925 len, PCI_DMA_FROMDEVICE);
19a33d4e 2926 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 2927 } else {
383181ac 2928 struct sk_buff *nskb;
c54f9765 2929 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
383181ac
SH		 2930 if (!nskb)
2931 goto resubmit;
19a33d4e 2932
901ccefb 2933 skb_reserve(nskb, NET_IP_ALIGN);
19a33d4e
SH		 2934 pci_unmap_single(skge->hw->pdev,
2935 pci_unmap_addr(e, mapaddr),
2936 pci_unmap_len(e, maplen),
2937 PCI_DMA_FROMDEVICE);
2938 skb = e->skb;
383181ac 2939 prefetch(skb->data);
19a33d4e 2940 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 2941 }
383181ac
SH		 2942
2943 skb_put(skb, len);
383181ac
SH		 2944 if (skge->rx_csum) {
2945 skb->csum = csum;
84fa7933 2946 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 2947 }
2948
c54f9765 2949 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 2950
2951 return skb;
2952error:
2953
2954 if (netif_msg_rx_err(skge))
2955 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
c54f9765 2956 dev->name, e - skge->rx_ring.start,
383181ac
SH		 2957 control, status);
2958
2959 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2960 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2961 skge->net_stats.rx_length_errors++;
2962 if (status & XMR_FS_FRA_ERR)
2963 skge->net_stats.rx_frame_errors++;
2964 if (status & XMR_FS_FCS_ERR)
2965 skge->net_stats.rx_crc_errors++;
2966 } else {
2967 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2968 skge->net_stats.rx_length_errors++;
2969 if (status & GMR_FS_FRAGMENT)
2970 skge->net_stats.rx_frame_errors++;
2971 if (status & GMR_FS_CRC_ERR)
2972 skge->net_stats.rx_crc_errors++;
2973 }
2974
2975resubmit:
2976 skge_rx_reuse(e, skge->rx_buf_size);
2977 return NULL;
baef58b1
SH		 2978}
2979
7c442fa1 2980/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 2981static void skge_tx_done(struct net_device *dev)
00a6cae2 2982{
7c442fa1 2983 struct skge_port *skge = netdev_priv(dev);
00a6cae2 2984 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 2985 struct skge_element *e;
2986
513f533e 2987 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 2988
513f533e 2989 netif_tx_lock(dev);
866b4f3e 2990 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
00a6cae2 2991 struct skge_tx_desc *td = e->desc;
00a6cae2 2992
866b4f3e 2993 if (td->control & BMU_OWN)
00a6cae2
SH		 2994 break;
2995
7c442fa1 2996 skge_tx_free(skge, e, td->control);
00a6cae2 2997 }
7c442fa1 2998 skge->tx_ring.to_clean = e;
866b4f3e 2999
513f533e
SH		 3000 if (skge_avail(&skge->tx_ring) > TX_LOW_WATER)
3001 netif_wake_queue(dev);
00a6cae2 3002
513f533e 3003 netif_tx_unlock(dev);
00a6cae2 3004}
19a33d4e 3005
baef58b1
SH		 3006static int skge_poll(struct net_device *dev, int *budget)
3007{
3008 struct skge_port *skge = netdev_priv(dev);
3009 struct skge_hw *hw = skge->hw;
3010 struct skge_ring *ring = &skge->rx_ring;
3011 struct skge_element *e;
d15e9c4d 3012 unsigned long flags;
00a6cae2
SH		 3013 int to_do = min(dev->quota, *budget);
3014 int work_done = 0;
3015
513f533e
SH		 3016 skge_tx_done(dev);
3017
3018 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3019
1631aef1 3020 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 3021 struct skge_rx_desc *rd = e->desc;
19a33d4e 3022 struct sk_buff *skb;
383181ac 3023 u32 control;
baef58b1
SH		 3024
3025 rmb();
3026 control = rd->control;
3027 if (control & BMU_OWN)
3028 break;
3029
c54f9765 3030 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 3031 if (likely(skb)) {
19a33d4e
SH		 3032 dev->last_rx = jiffies;
3033 netif_receive_skb(skb);
baef58b1 3034
19a33d4e 3035 ++work_done;
5a011447 3036 }
baef58b1
SH		 3037 }
3038 ring->to_clean = e;
3039
baef58b1
SH		 3040 /* restart receiver */
3041 wmb();
a9cdab86 3042 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 3043
19a33d4e
SH		 3044 *budget -= work_done;
3045 dev->quota -= work_done;
3046
3047 if (work_done >= to_do)
3048 return 1; /* not done */
baef58b1 3049
d15e9c4d 3050 spin_lock_irqsave(&hw->hw_lock, flags);
513f533e
SH		 3051 __netif_rx_complete(dev);
3052 hw->intr_mask |= irqmask[skge->port];
80dd857d 3053 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3054 skge_read32(hw, B0_IMSK);
d15e9c4d 3055 spin_unlock_irqrestore(&hw->hw_lock, flags);
1631aef1 3056
19a33d4e 3057 return 0;
baef58b1
SH		 3058}
3059
f6620cab
SH		 3060/* Parity errors seem to happen when Genesis is connected to a switch
3061 * with no other ports present. Heartbeat error??
3062 */
baef58b1
SH		 3063static void skge_mac_parity(struct skge_hw *hw, int port)
3064{
f6620cab
SH		 3065 struct net_device *dev = hw->dev[port];
3066
3067 if (dev) {
3068 struct skge_port *skge = netdev_priv(dev);
3069 ++skge->net_stats.tx_heartbeat_errors;
3070 }
baef58b1
SH		 3071
3072 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 3073 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 3074 MFF_CLR_PERR);
3075 else
3076 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 3077 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 3078 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 3079 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3080}
3081
baef58b1
SH		 3082static void skge_mac_intr(struct skge_hw *hw, int port)
3083{
95566065 3084 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 3085 genesis_mac_intr(hw, port);
3086 else
3087 yukon_mac_intr(hw, port);
3088}
3089
3090/* Handle device specific framing and timeout interrupts */
3091static void skge_error_irq(struct skge_hw *hw)
3092{
1479d13c 3093 struct pci_dev *pdev = hw->pdev;
baef58b1
SH		 3094 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3095
3096 if (hw->chip_id == CHIP_ID_GENESIS) {
3097 /* clear xmac errors */
3098 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3099 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3100 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3101 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3102 } else {
3103 /* Timestamp (unused) overflow */
3104 if (hwstatus & IS_IRQ_TIST_OV)
3105 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3106 }
3107
3108 if (hwstatus & IS_RAM_RD_PAR) {
1479d13c 3109 dev_err(&pdev->dev, "Ram read data parity error\n");
baef58b1
SH		 3110 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3111 }
3112
3113 if (hwstatus & IS_RAM_WR_PAR) {
1479d13c 3114 dev_err(&pdev->dev, "Ram write data parity error\n");
baef58b1
SH		 3115 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3116 }
3117
3118 if (hwstatus & IS_M1_PAR_ERR)
3119 skge_mac_parity(hw, 0);
3120
3121 if (hwstatus & IS_M2_PAR_ERR)
3122 skge_mac_parity(hw, 1);
3123
b9d64acc 3124 if (hwstatus & IS_R1_PAR_ERR) {
1479d13c
SH		 3125 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3126 hw->dev[0]->name);
baef58b1 3127 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3128 }
baef58b1 3129
b9d64acc 3130 if (hwstatus & IS_R2_PAR_ERR) {
1479d13c
SH		 3131 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3132 hw->dev[1]->name);
baef58b1 3133 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3134 }
baef58b1
SH		 3135
3136 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3137 u16 pci_status, pci_cmd;
3138
1479d13c
SH		 3139 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3140 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
baef58b1 3141
1479d13c
SH		 3142 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3143 pci_cmd, pci_status);
b9d64acc
SH		 3144
3145 /* Write the error bits back to clear them. */
3146 pci_status &= PCI_STATUS_ERROR_BITS;
3147 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1479d13c 3148 pci_write_config_word(pdev, PCI_COMMAND,
b9d64acc 3149 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
1479d13c 3150 pci_write_config_word(pdev, PCI_STATUS, pci_status);
b9d64acc 3151 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3152
050ec18a 3153 /* if error still set then just ignore it */
baef58b1
SH		 3154 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3155 if (hwstatus & IS_IRQ_STAT) {
1479d13c 3156 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3157 hw->intr_mask &= ~IS_HW_ERR;
3158 }
3159 }
3160}
3161
3162/*
d85b514f 3163 * Interrupt from PHY are handled in work queue
baef58b1
SH		 3164 * because accessing phy registers requires spin wait which might
3165 * cause excess interrupt latency.
3166 */
c4028958 3167static void skge_extirq(struct work_struct *work)
baef58b1 3168{
c4028958 3169 struct skge_hw *hw = container_of(work, struct skge_hw, phy_work);
baef58b1
SH		 3170 int port;
3171
d85b514f 3172 mutex_lock(&hw->phy_mutex);
cfc3ed79 3173 for (port = 0; port < hw->ports; port++) {
baef58b1 3174 struct net_device *dev = hw->dev[port];
cfc3ed79 3175 struct skge_port *skge = netdev_priv(dev);
baef58b1 3176
cfc3ed79 3177 if (netif_running(dev)) {
baef58b1
SH		 3178 if (hw->chip_id != CHIP_ID_GENESIS)
3179 yukon_phy_intr(skge);
64f6b64d 3180 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3181 bcom_phy_intr(skge);
baef58b1
SH		 3182 }
3183 }
d85b514f 3184 mutex_unlock(&hw->phy_mutex);
baef58b1 3185
7c442fa1 3186 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3187 hw->intr_mask |= IS_EXT_REG;
3188 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3189 skge_read32(hw, B0_IMSK);
7c442fa1 3190 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3191}
3192
7d12e780 3193static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3194{
3195 struct skge_hw *hw = dev_id;
cfc3ed79 3196 u32 status;
29365c90 3197 int handled = 0;
baef58b1 3198
29365c90 3199 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3200 /* Reading this register masks IRQ */
3201 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3202 if (status == 0 || status == ~0)
29365c90 3203 goto out;
baef58b1 3204
29365c90 3205 handled = 1;
7c442fa1 3206 status &= hw->intr_mask;
cfc3ed79
SH		 3207 if (status & IS_EXT_REG) {
3208 hw->intr_mask &= ~IS_EXT_REG;
d85b514f 3209 schedule_work(&hw->phy_work);
cfc3ed79
SH		 3210 }
3211
513f533e
SH		 3212 if (status & (IS_XA1_F|IS_R1_F)) {
3213 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
7c442fa1 3214 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 3215 }
3216
7c442fa1
SH		 3217 if (status & IS_PA_TO_TX1)
3218 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3219
d25f5a67
SH		 3220 if (status & IS_PA_TO_RX1) {
3221 struct skge_port *skge = netdev_priv(hw->dev[0]);
d25f5a67 3222
d25f5a67 3223 ++skge->net_stats.rx_over_errors;
7c442fa1 3224 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3225 }
3226
d25f5a67 3227
baef58b1
SH		 3228 if (status & IS_MAC1)
3229 skge_mac_intr(hw, 0);
95566065 3230
7c442fa1 3231 if (hw->dev[1]) {
513f533e
SH		 3232 if (status & (IS_XA2_F|IS_R2_F)) {
3233 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
7c442fa1
SH		 3234 netif_rx_schedule(hw->dev[1]);
3235 }
3236
3237 if (status & IS_PA_TO_RX2) {
3238 struct skge_port *skge = netdev_priv(hw->dev[1]);
3239 ++skge->net_stats.rx_over_errors;
3240 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3241 }
3242
3243 if (status & IS_PA_TO_TX2)
3244 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3245
3246 if (status & IS_MAC2)
3247 skge_mac_intr(hw, 1);
3248 }
baef58b1
SH		 3249
3250 if (status & IS_HW_ERR)
3251 skge_error_irq(hw);
3252
7e676d91 3253 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3254 skge_read32(hw, B0_IMSK);
29365c90 3255out:
7c442fa1 3256 spin_unlock(&hw->hw_lock);
baef58b1 3257
29365c90 3258 return IRQ_RETVAL(handled);
baef58b1
SH		 3259}
3260
3261#ifdef CONFIG_NET_POLL_CONTROLLER
3262static void skge_netpoll(struct net_device *dev)
3263{
3264 struct skge_port *skge = netdev_priv(dev);
3265
3266 disable_irq(dev->irq);
7d12e780 3267 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3268 enable_irq(dev->irq);
3269}
3270#endif
3271
3272static int skge_set_mac_address(struct net_device *dev, void *p)
3273{
3274 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3275 struct skge_hw *hw = skge->hw;
3276 unsigned port = skge->port;
3277 const struct sockaddr *addr = p;
2eb3e621 3278 u16 ctrl;
baef58b1
SH		 3279
3280 if (!is_valid_ether_addr(addr->sa_data))
3281 return -EADDRNOTAVAIL;
3282
baef58b1 3283 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3284
2eb3e621
SH		 3285 /* disable Rx */
3286 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3287 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3288
3289 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3290 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3291
3292 if (netif_running(dev)) {
3293 if (hw->chip_id == CHIP_ID_GENESIS)
3294 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3295 else {
3296 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3297 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3298 }
c2681dd8 3299 }
2eb3e621
SH		 3300
3301 gma_write16(hw, port, GM_GP_CTRL, ctrl);
c2681dd8
SH		 3302
3303 return 0;
baef58b1
SH		 3304}
3305
3306static const struct {
3307 u8 id;
3308 const char *name;
3309} skge_chips[] = {
3310 { CHIP_ID_GENESIS, "Genesis" },
3311 { CHIP_ID_YUKON, "Yukon" },
3312 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3313 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3314};
3315
3316static const char *skge_board_name(const struct skge_hw *hw)
3317{
3318 int i;
3319 static char buf[16];
3320
3321 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3322 if (skge_chips[i].id == hw->chip_id)
3323 return skge_chips[i].name;
3324
3325 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3326 return buf;
3327}
3328
3329
3330/*
3331 * Setup the board data structure, but don't bring up
3332 * the port(s)
3333 */
3334static int skge_reset(struct skge_hw *hw)
3335{
adba9e23 3336 u32 reg;
b9d64acc 3337 u16 ctst, pci_status;
64f6b64d 3338 u8 t8, mac_cfg, pmd_type;
981d0377 3339 int i;
baef58b1
SH		 3340
3341 ctst = skge_read16(hw, B0_CTST);
3342
3343 /* do a SW reset */
3344 skge_write8(hw, B0_CTST, CS_RST_SET);
3345 skge_write8(hw, B0_CTST, CS_RST_CLR);
3346
3347 /* clear PCI errors, if any */
b9d64acc
SH		 3348 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3349 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3350
b9d64acc
SH		 3351 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3352 pci_write_config_word(hw->pdev, PCI_STATUS,
3353 pci_status | PCI_STATUS_ERROR_BITS);
3354 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3355 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3356
3357 /* restore CLK_RUN bits (for Yukon-Lite) */
3358 skge_write16(hw, B0_CTST,
3359 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3360
3361 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3362 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3363 pmd_type = skge_read8(hw, B2_PMD_TYP);
3364 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3365
95566065 3366 switch (hw->chip_id) {
baef58b1 3367 case CHIP_ID_GENESIS:
64f6b64d
SH		 3368 switch (hw->phy_type) {
3369 case SK_PHY_XMAC:
3370 hw->phy_addr = PHY_ADDR_XMAC;
3371 break;
baef58b1
SH		 3372 case SK_PHY_BCOM:
3373 hw->phy_addr = PHY_ADDR_BCOM;
3374 break;
3375 default:
1479d13c
SH		 3376 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3377 hw->phy_type);
baef58b1
SH		 3378 return -EOPNOTSUPP;
3379 }
3380 break;
3381
3382 case CHIP_ID_YUKON:
3383 case CHIP_ID_YUKON_LITE:
3384 case CHIP_ID_YUKON_LP:
64f6b64d 3385 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3386 hw->copper = 1;
baef58b1
SH		 3387
3388 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3389 break;
3390
3391 default:
1479d13c
SH		 3392 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3393 hw->chip_id);
baef58b1
SH		 3394 return -EOPNOTSUPP;
3395 }
3396
981d0377
SH		 3397 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3398 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3399 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3400
3401 /* read the adapters RAM size */
3402 t8 = skge_read8(hw, B2_E_0);
3403 if (hw->chip_id == CHIP_ID_GENESIS) {
3404 if (t8 == 3) {
3405 /* special case: 4 x 64k x 36, offset = 0x80000 */
3406 hw->ram_size = 0x100000;
3407 hw->ram_offset = 0x80000;
3408 } else
3409 hw->ram_size = t8 * 512;
3410 }
3411 else if (t8 == 0)
3412 hw->ram_size = 0x20000;
3413 else
3414 hw->ram_size = t8 * 4096;
3415
64f6b64d 3416 hw->intr_mask = IS_HW_ERR | IS_PORT_1;
cfc3ed79
SH		 3417 if (hw->ports > 1)
3418 hw->intr_mask |= IS_PORT_2;
3419
64f6b64d
SH		 3420 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3421 hw->intr_mask |= IS_EXT_REG;
3422
baef58b1
SH		 3423 if (hw->chip_id == CHIP_ID_GENESIS)
3424 genesis_init(hw);
3425 else {
3426 /* switch power to VCC (WA for VAUX problem) */
3427 skge_write8(hw, B0_POWER_CTRL,
3428 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3429
050ec18a
SH		 3430 /* avoid boards with stuck Hardware error bits */
3431 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3432 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
1479d13c 3433 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
050ec18a
SH		 3434 hw->intr_mask &= ~IS_HW_ERR;
3435 }
3436
adba9e23
SH		 3437 /* Clear PHY COMA */
3438 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3439 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3440 reg &= ~PCI_PHY_COMA;
3441 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3442 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3443
3444
981d0377 3445 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3446 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3447 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3448 }
3449 }
3450
3451 /* turn off hardware timer (unused) */
3452 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3453 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3454 skge_write8(hw, B0_LED, LED_STAT_ON);
3455
3456 /* enable the Tx Arbiters */
981d0377 3457 for (i = 0; i < hw->ports; i++)
6b0c1480 3458 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3459
3460 /* Initialize ram interface */
3461 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3462
3463 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3464 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3465 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3466 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3467 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3468 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3469 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3470 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3471 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3472 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3473 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3474 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3475
3476 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3477
3478 /* Set interrupt moderation for Transmit only
3479 * Receive interrupts avoided by NAPI
3480 */
3481 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3482 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3483 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3484
baef58b1
SH		 3485 skge_write32(hw, B0_IMSK, hw->intr_mask);
3486
d85b514f 3487 mutex_lock(&hw->phy_mutex);
981d0377 3488 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3489 if (hw->chip_id == CHIP_ID_GENESIS)
3490 genesis_reset(hw, i);
3491 else
3492 yukon_reset(hw, i);
3493 }
d85b514f 3494 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 3495
3496 return 0;
3497}
3498
3499/* Initialize network device */
981d0377
SH		 3500static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3501 int highmem)
baef58b1
SH		 3502{
3503 struct skge_port *skge;
3504 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3505
3506 if (!dev) {
1479d13c 3507 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
baef58b1
SH		 3508 return NULL;
3509 }
3510
3511 SET_MODULE_OWNER(dev);
3512 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3513 dev->open = skge_up;
3514 dev->stop = skge_down;
2cd8e5d3 3515 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3516 dev->hard_start_xmit = skge_xmit_frame;
3517 dev->get_stats = skge_get_stats;
3518 if (hw->chip_id == CHIP_ID_GENESIS)
3519 dev->set_multicast_list = genesis_set_multicast;
3520 else
3521 dev->set_multicast_list = yukon_set_multicast;
3522
3523 dev->set_mac_address = skge_set_mac_address;
3524 dev->change_mtu = skge_change_mtu;
3525 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3526 dev->tx_timeout = skge_tx_timeout;
3527 dev->watchdog_timeo = TX_WATCHDOG;
3528 dev->poll = skge_poll;
3529 dev->weight = NAPI_WEIGHT;
3530#ifdef CONFIG_NET_POLL_CONTROLLER
3531 dev->poll_controller = skge_netpoll;
3532#endif
3533 dev->irq = hw->pdev->irq;
513f533e 3534
981d0377
SH		 3535 if (highmem)
3536 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3537
3538 skge = netdev_priv(dev);
3539 skge->netdev = dev;
3540 skge->hw = hw;
3541 skge->msg_enable = netif_msg_init(debug, default_msg);
3542 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3543 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3544
3545 /* Auto speed and flow control */
3546 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3547 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3548 skge->duplex = -1;
3549 skge->speed = -1;
31b619c5 3550 skge->advertising = skge_supported_modes(hw);
a504e64a 3551 skge->wol = pci_wake_enabled(hw->pdev) ? wol_supported(hw) : 0;
baef58b1
SH		 3552
3553 hw->dev[port] = dev;
3554
3555 skge->port = port;
3556
64f6b64d 3557 /* Only used for Genesis XMAC */
c4028958 3558 INIT_DELAYED_WORK(&skge->link_thread, xm_link_timer);
64f6b64d 3559
baef58b1
SH		 3560 if (hw->chip_id != CHIP_ID_GENESIS) {
3561 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3562 skge->rx_csum = 1;
3563 }
3564
3565 /* read the mac address */
3566 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3567 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3568
3569 /* device is off until link detection */
3570 netif_carrier_off(dev);
3571 netif_stop_queue(dev);
3572
3573 return dev;
3574}
3575
3576static void __devinit skge_show_addr(struct net_device *dev)
3577{
3578 const struct skge_port *skge = netdev_priv(dev);
3579
3580 if (netif_msg_probe(skge))
3581 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3582 dev->name,
3583 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3584 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3585}
3586
3587static int __devinit skge_probe(struct pci_dev *pdev,
3588 const struct pci_device_id *ent)
3589{
3590 struct net_device *dev, *dev1;
3591 struct skge_hw *hw;
3592 int err, using_dac = 0;
3593
203babb6
SH		 3594 err = pci_enable_device(pdev);
3595 if (err) {
1479d13c 3596 dev_err(&pdev->dev, "cannot enable PCI device\n");
baef58b1
SH		 3597 goto err_out;
3598 }
3599
203babb6
SH		 3600 err = pci_request_regions(pdev, DRV_NAME);
3601 if (err) {
1479d13c 3602 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
baef58b1
SH		 3603 goto err_out_disable_pdev;
3604 }
3605
3606 pci_set_master(pdev);
3607
93aea718 3608 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
baef58b1 3609 using_dac = 1;
77783a78 3610 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
93aea718
SH		 3611 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3612 using_dac = 0;
3613 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3614 }
3615
3616 if (err) {
1479d13c 3617 dev_err(&pdev->dev, "no usable DMA configuration\n");
93aea718 3618 goto err_out_free_regions;
baef58b1
SH		 3619 }
3620
3621#ifdef __BIG_ENDIAN
8f3f8193 3622 /* byte swap descriptors in hardware */
baef58b1
SH		 3623 {
3624 u32 reg;
3625
3626 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3627 reg |= PCI_REV_DESC;
3628 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3629 }
3630#endif
3631
3632 err = -ENOMEM;
7e863061 3633 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1 3634 if (!hw) {
1479d13c 3635 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
baef58b1
SH		 3636 goto err_out_free_regions;
3637 }
3638
baef58b1 3639 hw->pdev = pdev;
d85b514f 3640 mutex_init(&hw->phy_mutex);
c4028958 3641 INIT_WORK(&hw->phy_work, skge_extirq);
d38efdd6 3642 spin_lock_init(&hw->hw_lock);
baef58b1
SH		 3643
3644 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3645 if (!hw->regs) {
1479d13c 3646 dev_err(&pdev->dev, "cannot map device registers\n");
baef58b1
SH		 3647 goto err_out_free_hw;
3648 }
3649
baef58b1
SH		 3650 err = skge_reset(hw);
3651 if (err)
ccdaa2a9 3652 goto err_out_iounmap;
baef58b1 3653
7c7459d1
GKH		 3654 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3655 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
981d0377 3656 skge_board_name(hw), hw->chip_rev);
baef58b1 3657
ccdaa2a9
SH		 3658 dev = skge_devinit(hw, 0, using_dac);
3659 if (!dev)
baef58b1
SH		 3660 goto err_out_led_off;
3661
fae87592 3662 /* Some motherboards are broken and has zero in ROM. */
1479d13c
SH		 3663 if (!is_valid_ether_addr(dev->dev_addr))
3664 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
631ae320 3665
203babb6
SH		 3666 err = register_netdev(dev);
3667 if (err) {
1479d13c 3668 dev_err(&pdev->dev, "cannot register net device\n");
baef58b1
SH		 3669 goto err_out_free_netdev;
3670 }
3671
ccdaa2a9
SH		 3672 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3673 if (err) {
1479d13c 3674 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
ccdaa2a9
SH		 3675 dev->name, pdev->irq);
3676 goto err_out_unregister;
3677 }
baef58b1
SH		 3678 skge_show_addr(dev);
3679
981d0377 3680 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3681 if (register_netdev(dev1) == 0)
3682 skge_show_addr(dev1);
3683 else {
3684 /* Failure to register second port need not be fatal */
1479d13c 3685 dev_warn(&pdev->dev, "register of second port failed\n");
baef58b1
SH		 3686 hw->dev[1] = NULL;
3687 free_netdev(dev1);
3688 }
3689 }
ccdaa2a9 3690 pci_set_drvdata(pdev, hw);
baef58b1
SH		 3691
3692 return 0;
3693
ccdaa2a9
SH		 3694err_out_unregister:
3695 unregister_netdev(dev);
baef58b1
SH		 3696err_out_free_netdev:
3697 free_netdev(dev);
3698err_out_led_off:
3699 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 3700err_out_iounmap:
3701 iounmap(hw->regs);
3702err_out_free_hw:
3703 kfree(hw);
3704err_out_free_regions:
3705 pci_release_regions(pdev);
3706err_out_disable_pdev:
3707 pci_disable_device(pdev);
3708 pci_set_drvdata(pdev, NULL);
3709err_out:
3710 return err;
3711}
3712
3713static void __devexit skge_remove(struct pci_dev *pdev)
3714{
3715 struct skge_hw *hw = pci_get_drvdata(pdev);
3716 struct net_device *dev0, *dev1;
3717
95566065 3718 if (!hw)
baef58b1
SH		 3719 return;
3720
208491d8
SH		 3721 flush_scheduled_work();
3722
baef58b1
SH		 3723 if ((dev1 = hw->dev[1]))
3724 unregister_netdev(dev1);
3725 dev0 = hw->dev[0];
3726 unregister_netdev(dev0);
3727
7c442fa1
SH		 3728 spin_lock_irq(&hw->hw_lock);
3729 hw->intr_mask = 0;
46a60f2d 3730 skge_write32(hw, B0_IMSK, 0);
78bc2186 3731 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 3732 spin_unlock_irq(&hw->hw_lock);
3733
46a60f2d 3734 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 3735 skge_write8(hw, B0_CTST, CS_RST_SET);
3736
baef58b1
SH		 3737 free_irq(pdev->irq, hw);
3738 pci_release_regions(pdev);
3739 pci_disable_device(pdev);
3740 if (dev1)
3741 free_netdev(dev1);
3742 free_netdev(dev0);
46a60f2d 3743
baef58b1
SH		 3744 iounmap(hw->regs);
3745 kfree(hw);
3746 pci_set_drvdata(pdev, NULL);
3747}
3748
3749#ifdef CONFIG_PM
a504e64a
SH		 3750static int vaux_avail(struct pci_dev *pdev)
3751{
3752 int pm_cap;
3753
3754 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3755 if (pm_cap) {
3756 u16 ctl;
3757 pci_read_config_word(pdev, pm_cap + PCI_PM_PMC, &ctl);
3758 if (ctl & PCI_PM_CAP_AUX_POWER)
3759 return 1;
3760 }
3761 return 0;
3762}
3763
3764
2a569579 3765static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3766{
3767 struct skge_hw *hw = pci_get_drvdata(pdev);
a504e64a
SH		 3768 int i, err, wol = 0;
3769
3770 err = pci_save_state(pdev);
3771 if (err)
3772 return err;
baef58b1 3773
d38efdd6 3774 for (i = 0; i < hw->ports; i++) {
baef58b1 3775 struct net_device *dev = hw->dev[i];
a504e64a 3776 struct skge_port *skge = netdev_priv(dev);
baef58b1 3777
a504e64a
SH		 3778 if (netif_running(dev))
3779 skge_down(dev);
3780 if (skge->wol)
3781 skge_wol_init(skge);
d38efdd6 3782
a504e64a 3783 wol |= skge->wol;
baef58b1
SH		 3784 }
3785
a504e64a
SH		 3786 if (wol && vaux_avail(pdev))
3787 skge_write8(hw, B0_POWER_CTRL,
3788 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
3789
d38efdd6 3790 skge_write32(hw, B0_IMSK, 0);
2a569579 3791 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3792 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3793
3794 return 0;
3795}
3796
3797static int skge_resume(struct pci_dev *pdev)
3798{
3799 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 3800 int i, err;
baef58b1 3801
a504e64a
SH		 3802 err = pci_set_power_state(pdev, PCI_D0);
3803 if (err)
3804 goto out;
3805
3806 err = pci_restore_state(pdev);
3807 if (err)
3808 goto out;
3809
baef58b1
SH		 3810 pci_enable_wake(pdev, PCI_D0, 0);
3811
d38efdd6
SH		 3812 err = skge_reset(hw);
3813 if (err)
3814 goto out;
baef58b1 3815
d38efdd6 3816 for (i = 0; i < hw->ports; i++) {
baef58b1 3817 struct net_device *dev = hw->dev[i];
d38efdd6 3818
d38efdd6
SH		 3819 if (netif_running(dev)) {
3820 err = skge_up(dev);
3821
3822 if (err) {
3823 printk(KERN_ERR PFX "%s: could not up: %d\n",
3824 dev->name, err);
edd702e8 3825 dev_close(dev);
d38efdd6
SH		 3826 goto out;
3827 }
baef58b1
SH		 3828 }
3829 }
d38efdd6
SH		 3830out:
3831 return err;
baef58b1
SH		 3832}
3833#endif
3834
3835static struct pci_driver skge_driver = {
3836 .name = DRV_NAME,
3837 .id_table = skge_id_table,
3838 .probe = skge_probe,
3839 .remove = __devexit_p(skge_remove),
3840#ifdef CONFIG_PM
3841 .suspend = skge_suspend,
3842 .resume = skge_resume,
3843#endif
3844};
3845
3846static int __init skge_init_module(void)
3847{
29917620 3848 return pci_register_driver(&skge_driver);
baef58b1
SH		 3849}
3850
3851static void __exit skge_cleanup_module(void)
3852{
3853 pci_unregister_driver(&skge_driver);
3854}
3855
3856module_init(skge_init_module);
3857module_exit(skge_cleanup_module);
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