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[PATCH] skge: whitespace fixes
[mirror_ubuntu-artful-kernel.git] / drivers / net / skge.c
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baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
4075400b 39#include <linux/dma-mapping.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
747802ab 45#define DRV_VERSION "0.7"
baef58b1
SH		 46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
51#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 52#define RX_COPY_THRESHOLD 128
53#define RX_BUF_SIZE 1536
baef58b1
SH		 54#define PHY_RETRIES 1000
55#define ETH_JUMBO_MTU 9000
56#define TX_WATCHDOG (5 * HZ)
57#define NAPI_WEIGHT 64
58#define BLINK_HZ (HZ/4)
baef58b1
SH		 59
60MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
61MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
62MODULE_LICENSE("GPL");
63MODULE_VERSION(DRV_VERSION);
64
65static const u32 default_msg
66 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
67 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
68
69static int debug = -1; /* defaults above */
70module_param(debug, int, 0);
71MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
72
73static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 74 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
275834d1
SH		 78 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
81 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
baef58b1
SH		 84 { 0 }
85};
86MODULE_DEVICE_TABLE(pci, skge_id_table);
87
88static int skge_up(struct net_device *dev);
89static int skge_down(struct net_device *dev);
90static void skge_tx_clean(struct skge_port *skge);
6b0c1480
SH		 91static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
92static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 93static void genesis_get_stats(struct skge_port *skge, u64 *data);
94static void yukon_get_stats(struct skge_port *skge, u64 *data);
95static void yukon_init(struct skge_hw *hw, int port);
96static void yukon_reset(struct skge_hw *hw, int port);
97static void genesis_mac_init(struct skge_hw *hw, int port);
98static void genesis_reset(struct skge_hw *hw, int port);
45bada65 99static void genesis_link_up(struct skge_port *skge);
baef58b1 100
7e676d91 101/* Avoid conditionals by using array */
baef58b1
SH		 102static const int txqaddr[] = { Q_XA1, Q_XA2 };
103static const int rxqaddr[] = { Q_R1, Q_R2 };
104static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
7e676d91 106static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1
SH		 107
108/* Don't need to look at whole 16K.
109 * last interesting register is descriptor poll timer.
110 */
111#define SKGE_REGS_LEN (29*128)
112
113static int skge_get_regs_len(struct net_device *dev)
114{
115 return SKGE_REGS_LEN;
116}
117
118/*
119 * Returns copy of control register region
120 * I/O region is divided into banks and certain regions are unreadable
121 */
122static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
123 void *p)
124{
125 const struct skge_port *skge = netdev_priv(dev);
126 unsigned long offs;
127 const void __iomem *io = skge->hw->regs;
128 static const unsigned long bankmap
129 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
130 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
131 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
132 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
133
134 regs->version = 1;
135 for (offs = 0; offs < regs->len; offs += 128) {
136 u32 len = min_t(u32, 128, regs->len - offs);
137
138 if (bankmap & (1<<(offs/128)))
139 memcpy_fromio(p + offs, io + offs, len);
140 else
141 memset(p + offs, 0, len);
142 }
143}
144
145/* Wake on Lan only supported on Yukon chps with rev 1 or above */
146static int wol_supported(const struct skge_hw *hw)
147{
148 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 149 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 150}
151
152static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
153{
154 struct skge_port *skge = netdev_priv(dev);
155
156 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
157 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
158}
159
160static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
161{
162 struct skge_port *skge = netdev_priv(dev);
163 struct skge_hw *hw = skge->hw;
164
95566065 165 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 166 return -EOPNOTSUPP;
167
168 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
169 return -EOPNOTSUPP;
170
171 skge->wol = wol->wolopts == WAKE_MAGIC;
172
173 if (skge->wol) {
174 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
175
176 skge_write16(hw, WOL_CTRL_STAT,
177 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
178 WOL_CTL_ENA_MAGIC_PKT_UNIT);
179 } else
180 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
181
182 return 0;
183}
184
31b619c5
SH		 185/* Determine supported/adverised modes based on hardware.
186 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
187 */
188static u32 skge_supported_modes(const struct skge_hw *hw)
189{
190 u32 supported;
191
192 if (iscopper(hw)) {
193 supported = SUPPORTED_10baseT_Half
194 | SUPPORTED_10baseT_Full
195 | SUPPORTED_100baseT_Half
196 | SUPPORTED_100baseT_Full
197 | SUPPORTED_1000baseT_Half
198 | SUPPORTED_1000baseT_Full
199 | SUPPORTED_Autoneg| SUPPORTED_TP;
200
201 if (hw->chip_id == CHIP_ID_GENESIS)
202 supported &= ~(SUPPORTED_10baseT_Half
203 | SUPPORTED_10baseT_Full
204 | SUPPORTED_100baseT_Half
205 | SUPPORTED_100baseT_Full);
206
207 else if (hw->chip_id == CHIP_ID_YUKON)
208 supported &= ~SUPPORTED_1000baseT_Half;
209 } else
210 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
211 | SUPPORTED_Autoneg;
212
213 return supported;
214}
baef58b1
SH		 215
216static int skge_get_settings(struct net_device *dev,
217 struct ethtool_cmd *ecmd)
218{
219 struct skge_port *skge = netdev_priv(dev);
220 struct skge_hw *hw = skge->hw;
221
222 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 223 ecmd->supported = skge_supported_modes(hw);
baef58b1
SH		 224
225 if (iscopper(hw)) {
baef58b1
SH		 226 ecmd->port = PORT_TP;
227 ecmd->phy_address = hw->phy_addr;
31b619c5 228 } else
baef58b1 229 ecmd->port = PORT_FIBRE;
baef58b1
SH		 230
231 ecmd->advertising = skge->advertising;
232 ecmd->autoneg = skge->autoneg;
233 ecmd->speed = skge->speed;
234 ecmd->duplex = skge->duplex;
235 return 0;
236}
237
baef58b1
SH		 238static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
239{
240 struct skge_port *skge = netdev_priv(dev);
241 const struct skge_hw *hw = skge->hw;
31b619c5 242 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 243
244 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 245 ecmd->advertising = supported;
246 skge->duplex = -1;
247 skge->speed = -1;
baef58b1 248 } else {
31b619c5
SH		 249 u32 setting;
250
2c668514 251 switch (ecmd->speed) {
baef58b1 252 case SPEED_1000:
31b619c5
SH		 253 if (ecmd->duplex == DUPLEX_FULL)
254 setting = SUPPORTED_1000baseT_Full;
255 else if (ecmd->duplex == DUPLEX_HALF)
256 setting = SUPPORTED_1000baseT_Half;
257 else
258 return -EINVAL;
baef58b1
SH		 259 break;
260 case SPEED_100:
31b619c5
SH		 261 if (ecmd->duplex == DUPLEX_FULL)
262 setting = SUPPORTED_100baseT_Full;
263 else if (ecmd->duplex == DUPLEX_HALF)
264 setting = SUPPORTED_100baseT_Half;
265 else
266 return -EINVAL;
267 break;
268
baef58b1 269 case SPEED_10:
31b619c5
SH		 270 if (ecmd->duplex == DUPLEX_FULL)
271 setting = SUPPORTED_10baseT_Full;
272 else if (ecmd->duplex == DUPLEX_HALF)
273 setting = SUPPORTED_10baseT_Half;
274 else
baef58b1
SH		 275 return -EINVAL;
276 break;
277 default:
278 return -EINVAL;
279 }
31b619c5
SH		 280
281 if ((setting & supported) == 0)
282 return -EINVAL;
283
284 skge->speed = ecmd->speed;
285 skge->duplex = ecmd->duplex;
baef58b1
SH		 286 }
287
288 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 289 skge->advertising = ecmd->advertising;
290
291 if (netif_running(dev)) {
292 skge_down(dev);
293 skge_up(dev);
294 }
295 return (0);
296}
297
298static void skge_get_drvinfo(struct net_device *dev,
299 struct ethtool_drvinfo *info)
300{
301 struct skge_port *skge = netdev_priv(dev);
302
303 strcpy(info->driver, DRV_NAME);
304 strcpy(info->version, DRV_VERSION);
305 strcpy(info->fw_version, "N/A");
306 strcpy(info->bus_info, pci_name(skge->hw->pdev));
307}
308
309static const struct skge_stat {
310 char name[ETH_GSTRING_LEN];
311 u16 xmac_offset;
312 u16 gma_offset;
313} skge_stats[] = {
314 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
315 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
316
317 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
318 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
319 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
320 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
321 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
322 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
323 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
324 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
325
326 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
327 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
328 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
329 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
330 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
331 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
332
333 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
334 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
335 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
336 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
337 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
338};
339
340static int skge_get_stats_count(struct net_device *dev)
341{
342 return ARRAY_SIZE(skge_stats);
343}
344
345static void skge_get_ethtool_stats(struct net_device *dev,
346 struct ethtool_stats *stats, u64 *data)
347{
348 struct skge_port *skge = netdev_priv(dev);
349
350 if (skge->hw->chip_id == CHIP_ID_GENESIS)
351 genesis_get_stats(skge, data);
352 else
353 yukon_get_stats(skge, data);
354}
355
356/* Use hardware MIB variables for critical path statistics and
357 * transmit feedback not reported at interrupt.
358 * Other errors are accounted for in interrupt handler.
359 */
360static struct net_device_stats *skge_get_stats(struct net_device *dev)
361{
362 struct skge_port *skge = netdev_priv(dev);
363 u64 data[ARRAY_SIZE(skge_stats)];
364
365 if (skge->hw->chip_id == CHIP_ID_GENESIS)
366 genesis_get_stats(skge, data);
367 else
368 yukon_get_stats(skge, data);
369
370 skge->net_stats.tx_bytes = data[0];
371 skge->net_stats.rx_bytes = data[1];
372 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
373 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
374 skge->net_stats.multicast = data[5] + data[7];
375 skge->net_stats.collisions = data[10];
376 skge->net_stats.tx_aborted_errors = data[12];
377
378 return &skge->net_stats;
379}
380
381static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
382{
383 int i;
384
95566065 385 switch (stringset) {
baef58b1
SH		 386 case ETH_SS_STATS:
387 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
388 memcpy(data + i * ETH_GSTRING_LEN,
389 skge_stats[i].name, ETH_GSTRING_LEN);
390 break;
391 }
392}
393
394static void skge_get_ring_param(struct net_device *dev,
395 struct ethtool_ringparam *p)
396{
397 struct skge_port *skge = netdev_priv(dev);
398
399 p->rx_max_pending = MAX_RX_RING_SIZE;
400 p->tx_max_pending = MAX_TX_RING_SIZE;
401 p->rx_mini_max_pending = 0;
402 p->rx_jumbo_max_pending = 0;
403
404 p->rx_pending = skge->rx_ring.count;
405 p->tx_pending = skge->tx_ring.count;
406 p->rx_mini_pending = 0;
407 p->rx_jumbo_pending = 0;
408}
409
410static int skge_set_ring_param(struct net_device *dev,
411 struct ethtool_ringparam *p)
412{
413 struct skge_port *skge = netdev_priv(dev);
414
415 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
416 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
417 return -EINVAL;
418
419 skge->rx_ring.count = p->rx_pending;
420 skge->tx_ring.count = p->tx_pending;
421
422 if (netif_running(dev)) {
423 skge_down(dev);
424 skge_up(dev);
425 }
426
427 return 0;
428}
429
430static u32 skge_get_msglevel(struct net_device *netdev)
431{
432 struct skge_port *skge = netdev_priv(netdev);
433 return skge->msg_enable;
434}
435
436static void skge_set_msglevel(struct net_device *netdev, u32 value)
437{
438 struct skge_port *skge = netdev_priv(netdev);
439 skge->msg_enable = value;
440}
441
442static int skge_nway_reset(struct net_device *dev)
443{
444 struct skge_port *skge = netdev_priv(dev);
445 struct skge_hw *hw = skge->hw;
446 int port = skge->port;
447
448 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
449 return -EINVAL;
450
451 spin_lock_bh(&hw->phy_lock);
452 if (hw->chip_id == CHIP_ID_GENESIS) {
453 genesis_reset(hw, port);
454 genesis_mac_init(hw, port);
455 } else {
456 yukon_reset(hw, port);
457 yukon_init(hw, port);
458 }
459 spin_unlock_bh(&hw->phy_lock);
460 return 0;
461}
462
463static int skge_set_sg(struct net_device *dev, u32 data)
464{
465 struct skge_port *skge = netdev_priv(dev);
466 struct skge_hw *hw = skge->hw;
467
468 if (hw->chip_id == CHIP_ID_GENESIS && data)
469 return -EOPNOTSUPP;
470 return ethtool_op_set_sg(dev, data);
471}
472
473static int skge_set_tx_csum(struct net_device *dev, u32 data)
474{
475 struct skge_port *skge = netdev_priv(dev);
476 struct skge_hw *hw = skge->hw;
477
478 if (hw->chip_id == CHIP_ID_GENESIS && data)
479 return -EOPNOTSUPP;
480
481 return ethtool_op_set_tx_csum(dev, data);
482}
483
484static u32 skge_get_rx_csum(struct net_device *dev)
485{
486 struct skge_port *skge = netdev_priv(dev);
487
488 return skge->rx_csum;
489}
490
491/* Only Yukon supports checksum offload. */
492static int skge_set_rx_csum(struct net_device *dev, u32 data)
493{
494 struct skge_port *skge = netdev_priv(dev);
495
496 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
497 return -EOPNOTSUPP;
498
499 skge->rx_csum = data;
500 return 0;
501}
502
baef58b1
SH		 503static void skge_get_pauseparam(struct net_device *dev,
504 struct ethtool_pauseparam *ecmd)
505{
506 struct skge_port *skge = netdev_priv(dev);
507
508 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
509 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
510 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
511 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
512
513 ecmd->autoneg = skge->autoneg;
514}
515
516static int skge_set_pauseparam(struct net_device *dev,
517 struct ethtool_pauseparam *ecmd)
518{
519 struct skge_port *skge = netdev_priv(dev);
520
521 skge->autoneg = ecmd->autoneg;
522 if (ecmd->rx_pause && ecmd->tx_pause)
523 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 524 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 525 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 526 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 527 skge->flow_control = FLOW_MODE_LOC_SEND;
528 else
529 skge->flow_control = FLOW_MODE_NONE;
530
531 if (netif_running(dev)) {
532 skge_down(dev);
533 skge_up(dev);
534 }
535 return 0;
536}
537
538/* Chip internal frequency for clock calculations */
539static inline u32 hwkhz(const struct skge_hw *hw)
540{
541 if (hw->chip_id == CHIP_ID_GENESIS)
542 return 53215; /* or: 53.125 MHz */
baef58b1
SH		 543 else
544 return 78215; /* or: 78.125 MHz */
545}
546
547/* Chip hz to microseconds */
548static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
549{
550 return (ticks * 1000) / hwkhz(hw);
551}
552
553/* Microseconds to chip hz */
554static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
555{
556 return hwkhz(hw) * usec / 1000;
557}
558
559static int skge_get_coalesce(struct net_device *dev,
560 struct ethtool_coalesce *ecmd)
561{
562 struct skge_port *skge = netdev_priv(dev);
563 struct skge_hw *hw = skge->hw;
564 int port = skge->port;
565
566 ecmd->rx_coalesce_usecs = 0;
567 ecmd->tx_coalesce_usecs = 0;
568
569 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
570 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
571 u32 msk = skge_read32(hw, B2_IRQM_MSK);
572
573 if (msk & rxirqmask[port])
574 ecmd->rx_coalesce_usecs = delay;
575 if (msk & txirqmask[port])
576 ecmd->tx_coalesce_usecs = delay;
577 }
578
579 return 0;
580}
581
582/* Note: interrupt timer is per board, but can turn on/off per port */
583static int skge_set_coalesce(struct net_device *dev,
584 struct ethtool_coalesce *ecmd)
585{
586 struct skge_port *skge = netdev_priv(dev);
587 struct skge_hw *hw = skge->hw;
588 int port = skge->port;
589 u32 msk = skge_read32(hw, B2_IRQM_MSK);
590 u32 delay = 25;
591
592 if (ecmd->rx_coalesce_usecs == 0)
593 msk &= ~rxirqmask[port];
594 else if (ecmd->rx_coalesce_usecs < 25 ||
595 ecmd->rx_coalesce_usecs > 33333)
596 return -EINVAL;
597 else {
598 msk |= rxirqmask[port];
599 delay = ecmd->rx_coalesce_usecs;
600 }
601
602 if (ecmd->tx_coalesce_usecs == 0)
603 msk &= ~txirqmask[port];
604 else if (ecmd->tx_coalesce_usecs < 25 ||
605 ecmd->tx_coalesce_usecs > 33333)
606 return -EINVAL;
607 else {
608 msk |= txirqmask[port];
609 delay = min(delay, ecmd->rx_coalesce_usecs);
610 }
611
612 skge_write32(hw, B2_IRQM_MSK, msk);
613 if (msk == 0)
614 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
615 else {
616 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
617 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
618 }
619 return 0;
620}
621
622static void skge_led_on(struct skge_hw *hw, int port)
623{
624 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 625 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
baef58b1
SH		 626 skge_write8(hw, B0_LED, LED_STAT_ON);
627
6b0c1480
SH		 628 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
629 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
630 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 631
89bf5f23
SH		 632 /* For Broadcom Phy only */
633 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
baef58b1 634 } else {
6b0c1480
SH		 635 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
636 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 637 PHY_M_LED_MO_DUP(MO_LED_ON) |
638 PHY_M_LED_MO_10(MO_LED_ON) |
639 PHY_M_LED_MO_100(MO_LED_ON) |
640 PHY_M_LED_MO_1000(MO_LED_ON) |
641 PHY_M_LED_MO_RX(MO_LED_ON));
642 }
643}
644
645static void skge_led_off(struct skge_hw *hw, int port)
646{
647 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 648 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
baef58b1
SH		 649 skge_write8(hw, B0_LED, LED_STAT_OFF);
650
6b0c1480
SH		 651 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
652 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
baef58b1 653
89bf5f23
SH		 654 /* Broadcom only */
655 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
baef58b1 656 } else {
6b0c1480
SH		 657 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
658 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 659 PHY_M_LED_MO_DUP(MO_LED_OFF) |
660 PHY_M_LED_MO_10(MO_LED_OFF) |
661 PHY_M_LED_MO_100(MO_LED_OFF) |
662 PHY_M_LED_MO_1000(MO_LED_OFF) |
663 PHY_M_LED_MO_RX(MO_LED_OFF));
664 }
665}
666
667static void skge_blink_timer(unsigned long data)
668{
669 struct skge_port *skge = (struct skge_port *) data;
670 struct skge_hw *hw = skge->hw;
baef58b1 671
4ff6ac05 672 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 673 if (skge->blink_on)
674 skge_led_on(hw, skge->port);
675 else
676 skge_led_off(hw, skge->port);
4ff6ac05 677 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 678
679 skge->blink_on = !skge->blink_on;
680 mod_timer(&skge->led_blink, jiffies + BLINK_HZ);
681}
682
683/* blink LED's for finding board */
684static int skge_phys_id(struct net_device *dev, u32 data)
685{
686 struct skge_port *skge = netdev_priv(dev);
687
95566065 688 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
baef58b1
SH		 689 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
690
691 /* start blinking */
692 skge->blink_on = 1;
693 mod_timer(&skge->led_blink, jiffies+1);
694
695 msleep_interruptible(data * 1000);
696 del_timer_sync(&skge->led_blink);
697
698 skge_led_off(skge->hw, skge->port);
699
700 return 0;
701}
702
703static struct ethtool_ops skge_ethtool_ops = {
704 .get_settings = skge_get_settings,
705 .set_settings = skge_set_settings,
706 .get_drvinfo = skge_get_drvinfo,
707 .get_regs_len = skge_get_regs_len,
708 .get_regs = skge_get_regs,
709 .get_wol = skge_get_wol,
710 .set_wol = skge_set_wol,
711 .get_msglevel = skge_get_msglevel,
712 .set_msglevel = skge_set_msglevel,
713 .nway_reset = skge_nway_reset,
714 .get_link = ethtool_op_get_link,
715 .get_ringparam = skge_get_ring_param,
716 .set_ringparam = skge_set_ring_param,
717 .get_pauseparam = skge_get_pauseparam,
718 .set_pauseparam = skge_set_pauseparam,
719 .get_coalesce = skge_get_coalesce,
720 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 721 .get_sg = ethtool_op_get_sg,
722 .set_sg = skge_set_sg,
723 .get_tx_csum = ethtool_op_get_tx_csum,
724 .set_tx_csum = skge_set_tx_csum,
725 .get_rx_csum = skge_get_rx_csum,
726 .set_rx_csum = skge_set_rx_csum,
727 .get_strings = skge_get_strings,
728 .phys_id = skge_phys_id,
729 .get_stats_count = skge_get_stats_count,
730 .get_ethtool_stats = skge_get_ethtool_stats,
731};
732
733/*
734 * Allocate ring elements and chain them together
735 * One-to-one association of board descriptors with ring elements
736 */
737static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
738{
739 struct skge_tx_desc *d;
740 struct skge_element *e;
741 int i;
742
743 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
744 if (!ring->start)
745 return -ENOMEM;
746
747 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
748 e->desc = d;
19a33d4e 749 e->skb = NULL;
baef58b1
SH		 750 if (i == ring->count - 1) {
751 e->next = ring->start;
752 d->next_offset = base;
753 } else {
754 e->next = e + 1;
755 d->next_offset = base + (i+1) * sizeof(*d);
756 }
757 }
758 ring->to_use = ring->to_clean = ring->start;
759
760 return 0;
761}
762
19a33d4e 763static struct sk_buff *skge_rx_alloc(struct net_device *dev, unsigned int size)
baef58b1 764{
19a33d4e 765 struct sk_buff *skb = dev_alloc_skb(size);
baef58b1 766
19a33d4e
SH		 767 if (likely(skb)) {
768 skb->dev = dev;
769 skb_reserve(skb, NET_IP_ALIGN);
baef58b1 770 }
19a33d4e
SH		 771 return skb;
772}
baef58b1 773
19a33d4e
SH		 774/* Allocate and setup a new buffer for receiving */
775static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
776 struct sk_buff *skb, unsigned int bufsize)
777{
778 struct skge_rx_desc *rd = e->desc;
779 u64 map;
baef58b1
SH		 780
781 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
782 PCI_DMA_FROMDEVICE);
783
784 rd->dma_lo = map;
785 rd->dma_hi = map >> 32;
786 e->skb = skb;
787 rd->csum1_start = ETH_HLEN;
788 rd->csum2_start = ETH_HLEN;
789 rd->csum1 = 0;
790 rd->csum2 = 0;
791
792 wmb();
793
794 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
795 pci_unmap_addr_set(e, mapaddr, map);
796 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 797}
798
19a33d4e
SH		 799/* Resume receiving using existing skb,
800 * Note: DMA address is not changed by chip.
801 * MTU not changed while receiver active.
802 */
803static void skge_rx_reuse(struct skge_element *e, unsigned int size)
804{
805 struct skge_rx_desc *rd = e->desc;
806
807 rd->csum2 = 0;
808 rd->csum2_start = ETH_HLEN;
809
810 wmb();
811
812 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
813}
814
815
816/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 817static void skge_rx_clean(struct skge_port *skge)
818{
819 struct skge_hw *hw = skge->hw;
820 struct skge_ring *ring = &skge->rx_ring;
821 struct skge_element *e;
822
19a33d4e
SH		 823 e = ring->start;
824 do {
baef58b1
SH		 825 struct skge_rx_desc *rd = e->desc;
826 rd->control = 0;
19a33d4e
SH		 827 if (e->skb) {
828 pci_unmap_single(hw->pdev,
829 pci_unmap_addr(e, mapaddr),
830 pci_unmap_len(e, maplen),
831 PCI_DMA_FROMDEVICE);
832 dev_kfree_skb(e->skb);
833 e->skb = NULL;
834 }
835 } while ((e = e->next) != ring->start);
baef58b1
SH		 836}
837
19a33d4e 838
baef58b1 839/* Allocate buffers for receive ring
19a33d4e 840 * For receive: to_clean is next received frame.
baef58b1
SH		 841 */
842static int skge_rx_fill(struct skge_port *skge)
843{
844 struct skge_ring *ring = &skge->rx_ring;
845 struct skge_element *e;
19a33d4e 846 unsigned int bufsize = skge->rx_buf_size;
baef58b1 847
19a33d4e
SH		 848 e = ring->start;
849 do {
850 struct sk_buff *skb = skge_rx_alloc(skge->netdev, bufsize);
baef58b1 851
19a33d4e
SH		 852 if (!skb)
853 return -ENOMEM;
854
855 skge_rx_setup(skge, e, skb, bufsize);
856 } while ( (e = e->next) != ring->start);
baef58b1 857
19a33d4e
SH		 858 ring->to_clean = ring->start;
859 return 0;
baef58b1
SH		 860}
861
862static void skge_link_up(struct skge_port *skge)
863{
864 netif_carrier_on(skge->netdev);
865 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
866 netif_wake_queue(skge->netdev);
867
868 if (netif_msg_link(skge))
869 printk(KERN_INFO PFX
870 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
871 skge->netdev->name, skge->speed,
872 skge->duplex == DUPLEX_FULL ? "full" : "half",
873 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
874 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
875 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
876 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
877 "unknown");
878}
879
880static void skge_link_down(struct skge_port *skge)
881{
882 netif_carrier_off(skge->netdev);
883 netif_stop_queue(skge->netdev);
884
885 if (netif_msg_link(skge))
886 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
887}
888
6b0c1480 889static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 890{
891 int i;
892 u16 v;
893
6b0c1480
SH		 894 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
895 v = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 896
89bf5f23
SH		 897 /* Need to wait for external PHY */
898 for (i = 0; i < PHY_RETRIES; i++) {
899 udelay(1);
900 if (xm_read16(hw, port, XM_MMU_CMD)
901 & XM_MMU_PHY_RDY)
902 goto ready;
baef58b1
SH		 903 }
904
89bf5f23
SH		 905 printk(KERN_WARNING PFX "%s: phy read timed out\n",
906 hw->dev[port]->name);
907 return 0;
908 ready:
909 v = xm_read16(hw, port, XM_PHY_DATA);
910
baef58b1
SH		 911 return v;
912}
913
6b0c1480 914static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 915{
916 int i;
917
6b0c1480 918 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 919 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 920 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 921 goto ready;
89bf5f23 922 udelay(1);
baef58b1
SH		 923 }
924 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
925 hw->dev[port]->name);
926
927
928 ready:
6b0c1480 929 xm_write16(hw, port, XM_PHY_DATA, val);
baef58b1
SH		 930 for (i = 0; i < PHY_RETRIES; i++) {
931 udelay(1);
6b0c1480 932 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1
SH		 933 return;
934 }
935 printk(KERN_WARNING PFX "%s: phy write timed out\n",
936 hw->dev[port]->name);
937}
938
939static void genesis_init(struct skge_hw *hw)
940{
941 /* set blink source counter */
942 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
943 skge_write8(hw, B2_BSC_CTRL, BSC_START);
944
945 /* configure mac arbiter */
946 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
947
948 /* configure mac arbiter timeout values */
949 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
950 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
951 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
952 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
953
954 skge_write8(hw, B3_MA_RCINI_RX1, 0);
955 skge_write8(hw, B3_MA_RCINI_RX2, 0);
956 skge_write8(hw, B3_MA_RCINI_TX1, 0);
957 skge_write8(hw, B3_MA_RCINI_TX2, 0);
958
959 /* configure packet arbiter timeout */
960 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
961 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
962 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
963 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
964 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
965}
966
967static void genesis_reset(struct skge_hw *hw, int port)
968{
45bada65 969 const u8 zero[8] = { 0 };
baef58b1
SH		 970
971 /* reset the statistics module */
6b0c1480
SH		 972 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
973 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
974 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
975 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
976 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 977
89bf5f23
SH		 978 /* disable Broadcom PHY IRQ */
979 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 980
45bada65 981 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 982}
983
984
45bada65
SH		 985/* Convert mode to MII values */
986static const u16 phy_pause_map[] = {
987 [FLOW_MODE_NONE] = 0,
988 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
989 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
990 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
991};
992
993
994/* Check status of Broadcom phy link */
995static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 996{
45bada65
SH		 997 struct net_device *dev = hw->dev[port];
998 struct skge_port *skge = netdev_priv(dev);
999 u16 status;
1000
1001 /* read twice because of latch */
1002 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1003 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1004
1005 pr_debug("bcom_check_link status=0x%x\n", status);
1006
1007 if ((status & PHY_ST_LSYNC) == 0) {
1008 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
1009 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1010 xm_write16(hw, port, XM_MMU_CMD, cmd);
1011 /* dummy read to ensure writing */
1012 (void) xm_read16(hw, port, XM_MMU_CMD);
1013
1014 if (netif_carrier_ok(dev))
1015 skge_link_down(skge);
1016 } else {
1017 if (skge->autoneg == AUTONEG_ENABLE &&
1018 (status & PHY_ST_AN_OVER)) {
1019 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1020 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1021
1022 if (lpa & PHY_B_AN_RF) {
1023 printk(KERN_NOTICE PFX "%s: remote fault\n",
1024 dev->name);
1025 return;
1026 }
1027
1028 /* Check Duplex mismatch */
2c668514 1029 switch (aux & PHY_B_AS_AN_RES_MSK) {
45bada65
SH		 1030 case PHY_B_RES_1000FD:
1031 skge->duplex = DUPLEX_FULL;
1032 break;
1033 case PHY_B_RES_1000HD:
1034 skge->duplex = DUPLEX_HALF;
1035 break;
1036 default:
1037 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1038 dev->name);
1039 return;
1040 }
1041
1042
1043 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1044 switch (aux & PHY_B_AS_PAUSE_MSK) {
1045 case PHY_B_AS_PAUSE_MSK:
1046 skge->flow_control = FLOW_MODE_SYMMETRIC;
1047 break;
1048 case PHY_B_AS_PRR:
1049 skge->flow_control = FLOW_MODE_REM_SEND;
1050 break;
1051 case PHY_B_AS_PRT:
1052 skge->flow_control = FLOW_MODE_LOC_SEND;
1053 break;
1054 default:
1055 skge->flow_control = FLOW_MODE_NONE;
1056 }
1057
1058 skge->speed = SPEED_1000;
1059 }
1060
1061 if (!netif_carrier_ok(dev))
1062 genesis_link_up(skge);
1063 }
1064}
1065
1066/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1067 * Phy on for 100 or 10Mbit operation
1068 */
1069static void bcom_phy_init(struct skge_port *skge, int jumbo)
1070{
1071 struct skge_hw *hw = skge->hw;
1072 int port = skge->port;
baef58b1 1073 int i;
45bada65 1074 u16 id1, r, ext, ctl;
baef58b1
SH		 1075
1076 /* magic workaround patterns for Broadcom */
1077 static const struct {
1078 u16 reg;
1079 u16 val;
1080 } A1hack[] = {
1081 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1082 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1083 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1084 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1085 }, C0hack[] = {
1086 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1087 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1088 };
1089
45bada65
SH		 1090 pr_debug("bcom_phy_init\n");
1091
1092 /* read Id from external PHY (all have the same address) */
1093 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1094
1095 /* Optimize MDIO transfer by suppressing preamble. */
1096 r = xm_read16(hw, port, XM_MMU_CMD);
1097 r |= XM_MMU_NO_PRE;
1098 xm_write16(hw, port, XM_MMU_CMD,r);
1099
2c668514 1100 switch (id1) {
45bada65
SH		 1101 case PHY_BCOM_ID1_C0:
1102 /*
1103 * Workaround BCOM Errata for the C0 type.
1104 * Write magic patterns to reserved registers.
1105 */
1106 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1107 xm_phy_write(hw, port,
1108 C0hack[i].reg, C0hack[i].val);
1109
1110 break;
1111 case PHY_BCOM_ID1_A1:
1112 /*
1113 * Workaround BCOM Errata for the A1 type.
1114 * Write magic patterns to reserved registers.
1115 */
1116 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1117 xm_phy_write(hw, port,
1118 A1hack[i].reg, A1hack[i].val);
1119 break;
1120 }
1121
1122 /*
1123 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1124 * Disable Power Management after reset.
1125 */
1126 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1127 r |= PHY_B_AC_DIS_PM;
1128 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1129
1130 /* Dummy read */
1131 xm_read16(hw, port, XM_ISRC);
1132
1133 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1134 ctl = PHY_CT_SP1000; /* always 1000mbit */
1135
1136 if (skge->autoneg == AUTONEG_ENABLE) {
1137 /*
1138 * Workaround BCOM Errata #1 for the C5 type.
1139 * 1000Base-T Link Acquisition Failure in Slave Mode
1140 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1141 */
1142 u16 adv = PHY_B_1000C_RD;
1143 if (skge->advertising & ADVERTISED_1000baseT_Half)
1144 adv |= PHY_B_1000C_AHD;
1145 if (skge->advertising & ADVERTISED_1000baseT_Full)
1146 adv |= PHY_B_1000C_AFD;
1147 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1148
1149 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1150 } else {
1151 if (skge->duplex == DUPLEX_FULL)
1152 ctl |= PHY_CT_DUP_MD;
1153 /* Force to slave */
1154 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1155 }
1156
1157 /* Set autonegotiation pause parameters */
1158 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1159 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1160
1161 /* Handle Jumbo frames */
1162 if (jumbo) {
1163 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1164 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1165
1166 ext |= PHY_B_PEC_HIGH_LA;
1167
1168 }
1169
1170 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1171 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1172
1173 /* Use link status change interrrupt */
1174 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1175
1176 bcom_check_link(hw, port);
1177}
1178
1179static void genesis_mac_init(struct skge_hw *hw, int port)
1180{
1181 struct net_device *dev = hw->dev[port];
1182 struct skge_port *skge = netdev_priv(dev);
1183 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1184 int i;
1185 u32 r;
1186 const u8 zero[6] = { 0 };
1187
1188 /* Clear MIB counters */
1189 xm_write16(hw, port, XM_STAT_CMD,
1190 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1191 /* Clear two times according to Errata #3 */
1192 xm_write16(hw, port, XM_STAT_CMD,
1193 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
baef58b1
SH		 1194
1195 /* initialize Rx, Tx and Link LED */
6b0c1480
SH		 1196 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
1197 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 1198
6b0c1480
SH		 1199 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
1200 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1
SH		 1201
1202 /* Unreset the XMAC. */
6b0c1480 1203 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1204
1205 /*
1206 * Perform additional initialization for external PHYs,
1207 * namely for the 1000baseTX cards that use the XMAC's
1208 * GMII mode.
1209 */
45bada65 1210 /* Take external Phy out of reset */
89bf5f23
SH		 1211 r = skge_read32(hw, B2_GP_IO);
1212 if (port == 0)
1213 r |= GP_DIR_0|GP_IO_0;
1214 else
1215 r |= GP_DIR_2|GP_IO_2;
1216
1217 skge_write32(hw, B2_GP_IO, r);
1218 skge_read32(hw, B2_GP_IO);
1219
45bada65 1220 /* Enable GMII interfac */
89bf5f23
SH		 1221 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1222
45bada65 1223 bcom_phy_init(skge, jumbo);
89bf5f23 1224
45bada65
SH		 1225 /* Set Station Address */
1226 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1227
45bada65
SH		 1228 /* We don't use match addresses so clear */
1229 for (i = 1; i < 16; i++)
1230 xm_outaddr(hw, port, XM_EXM(i), zero);
1231
1232 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1233 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1234
1235 /* We don't need the FCS appended to the packet. */
1236 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1237 if (jumbo)
1238 r |= XM_RX_BIG_PK_OK;
89bf5f23 1239
45bada65 1240 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1241 /*
45bada65
SH		 1242 * If in manual half duplex mode the other side might be in
1243 * full duplex mode, so ignore if a carrier extension is not seen
1244 * on frames received
89bf5f23 1245 */
45bada65 1246 r |= XM_RX_DIS_CEXT;
baef58b1 1247 }
45bada65 1248 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1249
baef58b1
SH		 1250
1251 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1252 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1253
1254 /*
1255 * Bump up the transmit threshold. This helps hold off transmit
1256 * underruns when we're blasting traffic from both ports at once.
1257 */
1258 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1259
1260 /*
1261 * Enable the reception of all error frames. This is is
1262 * a necessary evil due to the design of the XMAC. The
1263 * XMAC's receive FIFO is only 8K in size, however jumbo
1264 * frames can be up to 9000 bytes in length. When bad
1265 * frame filtering is enabled, the XMAC's RX FIFO operates
1266 * in 'store and forward' mode. For this to work, the
1267 * entire frame has to fit into the FIFO, but that means
1268 * that jumbo frames larger than 8192 bytes will be
1269 * truncated. Disabling all bad frame filtering causes
1270 * the RX FIFO to operate in streaming mode, in which
1271 * case the XMAC will start transfering frames out of the
1272 * RX FIFO as soon as the FIFO threshold is reached.
1273 */
45bada65 1274 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1275
baef58b1
SH		 1276
1277 /*
45bada65
SH		 1278 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1279 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1280 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1281 */
45bada65
SH		 1282 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1283
1284 /*
1285 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1286 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1287 * and 'Octets Tx OK Hi Cnt Ov'.
1288 */
1289 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1290
1291 /* Configure MAC arbiter */
1292 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1293
1294 /* configure timeout values */
1295 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1296 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1297 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1298 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1299
1300 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1301 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1302 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1303 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1304
1305 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1306 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1307 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1308 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1309
1310 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1311 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1312 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1313 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1314
45bada65 1315 if (jumbo) {
baef58b1 1316 /* Enable frame flushing if jumbo frames used */
6b0c1480 1317 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1318 } else {
1319 /* enable timeout timers if normal frames */
1320 skge_write16(hw, B3_PA_CTRL,
45bada65 1321 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1322 }
baef58b1
SH		 1323}
1324
1325static void genesis_stop(struct skge_port *skge)
1326{
1327 struct skge_hw *hw = skge->hw;
1328 int port = skge->port;
89bf5f23 1329 u32 reg;
baef58b1
SH		 1330
1331 /* Clear Tx packet arbiter timeout IRQ */
1332 skge_write16(hw, B3_PA_CTRL,
1333 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1334
1335 /*
1336 * If the transfer stucks at the MAC the STOP command will not
1337 * terminate if we don't flush the XMAC's transmit FIFO !
1338 */
6b0c1480
SH		 1339 xm_write32(hw, port, XM_MODE,
1340 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1341
1342
1343 /* Reset the MAC */
6b0c1480 1344 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1345
1346 /* For external PHYs there must be special handling */
89bf5f23
SH		 1347 reg = skge_read32(hw, B2_GP_IO);
1348 if (port == 0) {
1349 reg |= GP_DIR_0;
1350 reg &= ~GP_IO_0;
1351 } else {
1352 reg |= GP_DIR_2;
1353 reg &= ~GP_IO_2;
baef58b1 1354 }
89bf5f23
SH		 1355 skge_write32(hw, B2_GP_IO, reg);
1356 skge_read32(hw, B2_GP_IO);
baef58b1 1357
6b0c1480
SH		 1358 xm_write16(hw, port, XM_MMU_CMD,
1359 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1360 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1361
6b0c1480 1362 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1363}
1364
1365
1366static void genesis_get_stats(struct skge_port *skge, u64 *data)
1367{
1368 struct skge_hw *hw = skge->hw;
1369 int port = skge->port;
1370 int i;
1371 unsigned long timeout = jiffies + HZ;
1372
6b0c1480 1373 xm_write16(hw, port,
baef58b1
SH		 1374 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1375
1376 /* wait for update to complete */
6b0c1480 1377 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1378 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1379 if (time_after(jiffies, timeout))
1380 break;
1381 udelay(10);
1382 }
1383
1384 /* special case for 64 bit octet counter */
6b0c1480
SH		 1385 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1386 | xm_read32(hw, port, XM_TXO_OK_LO);
1387 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1388 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1389
1390 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1391 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1392}
1393
1394static void genesis_mac_intr(struct skge_hw *hw, int port)
1395{
1396 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1397 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1398
7e676d91
SH		 1399 if (netif_msg_intr(skge))
1400 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1401 skge->netdev->name, status);
baef58b1
SH		 1402
1403 if (status & XM_IS_TXF_UR) {
6b0c1480 1404 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1405 ++skge->net_stats.tx_fifo_errors;
1406 }
1407 if (status & XM_IS_RXF_OV) {
6b0c1480 1408 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1409 ++skge->net_stats.rx_fifo_errors;
1410 }
1411}
1412
6b0c1480 1413static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1414{
1415 int i;
1416
6b0c1480
SH		 1417 gma_write16(hw, port, GM_SMI_DATA, val);
1418 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1419 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1420 for (i = 0; i < PHY_RETRIES; i++) {
1421 udelay(1);
1422
6b0c1480 1423 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
baef58b1
SH		 1424 break;
1425 }
1426}
1427
6b0c1480 1428static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 1429{
1430 int i;
1431
6b0c1480 1432 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1433 GM_SMI_CT_PHY_AD(hw->phy_addr)
1434 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1435
1436 for (i = 0; i < PHY_RETRIES; i++) {
1437 udelay(1);
6b0c1480 1438 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
baef58b1
SH		 1439 goto ready;
1440 }
1441
1442 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1443 hw->dev[port]->name);
1444 return 0;
1445 ready:
6b0c1480 1446 return gma_read16(hw, port, GM_SMI_DATA);
baef58b1
SH		 1447}
1448
baef58b1
SH		 1449static void genesis_link_up(struct skge_port *skge)
1450{
1451 struct skge_hw *hw = skge->hw;
1452 int port = skge->port;
1453 u16 cmd;
1454 u32 mode, msk;
1455
1456 pr_debug("genesis_link_up\n");
6b0c1480 1457 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1458
1459 /*
1460 * enabling pause frame reception is required for 1000BT
1461 * because the XMAC is not reset if the link is going down
1462 */
1463 if (skge->flow_control == FLOW_MODE_NONE ||
1464 skge->flow_control == FLOW_MODE_LOC_SEND)
7e676d91 1465 /* Disable Pause Frame Reception */
baef58b1
SH		 1466 cmd |= XM_MMU_IGN_PF;
1467 else
1468 /* Enable Pause Frame Reception */
1469 cmd &= ~XM_MMU_IGN_PF;
1470
6b0c1480 1471 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1472
6b0c1480 1473 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1474 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1475 skge->flow_control == FLOW_MODE_LOC_SEND) {
1476 /*
1477 * Configure Pause Frame Generation
1478 * Use internal and external Pause Frame Generation.
1479 * Sending pause frames is edge triggered.
1480 * Send a Pause frame with the maximum pause time if
1481 * internal oder external FIFO full condition occurs.
1482 * Send a zero pause time frame to re-start transmission.
1483 */
1484 /* XM_PAUSE_DA = '010000C28001' (default) */
1485 /* XM_MAC_PTIME = 0xffff (maximum) */
1486 /* remember this value is defined in big endian (!) */
6b0c1480 1487 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1488
1489 mode |= XM_PAUSE_MODE;
6b0c1480 1490 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1491 } else {
1492 /*
1493 * disable pause frame generation is required for 1000BT
1494 * because the XMAC is not reset if the link is going down
1495 */
1496 /* Disable Pause Mode in Mode Register */
1497 mode &= ~XM_PAUSE_MODE;
1498
6b0c1480 1499 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1500 }
1501
6b0c1480 1502 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1503
1504 msk = XM_DEF_MSK;
89bf5f23
SH		 1505 /* disable GP0 interrupt bit for external Phy */
1506 msk |= XM_IS_INP_ASS;
baef58b1 1507
6b0c1480
SH		 1508 xm_write16(hw, port, XM_IMSK, msk);
1509 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1510
1511 /* get MMU Command Reg. */
6b0c1480 1512 cmd = xm_read16(hw, port, XM_MMU_CMD);
89bf5f23 1513 if (skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1514 cmd |= XM_MMU_GMII_FD;
1515
89bf5f23
SH		 1516 /*
1517 * Workaround BCOM Errata (#10523) for all BCom Phys
1518 * Enable Power Management after link up
1519 */
1520 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1521 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1522 & ~PHY_B_AC_DIS_PM);
1523 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
baef58b1
SH		 1524
1525 /* enable Rx/Tx */
6b0c1480 1526 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1527 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1528 skge_link_up(skge);
1529}
1530
1531
45bada65 1532static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1533{
1534 struct skge_hw *hw = skge->hw;
1535 int port = skge->port;
45bada65
SH		 1536 u16 isrc;
1537
1538 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1539 if (netif_msg_intr(skge))
1540 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1541 skge->netdev->name, isrc);
baef58b1 1542
45bada65
SH		 1543 if (isrc & PHY_B_IS_PSE)
1544 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1545 hw->dev[port]->name);
baef58b1
SH		 1546
1547 /* Workaround BCom Errata:
1548 * enable and disable loopback mode if "NO HCD" occurs.
1549 */
45bada65 1550 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1551 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1552 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1553 ctrl | PHY_CT_LOOP);
6b0c1480 1554 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1555 ctrl & ~PHY_CT_LOOP);
1556 }
1557
45bada65
SH		 1558 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1559 bcom_check_link(hw, port);
baef58b1 1560
baef58b1
SH		 1561}
1562
1563/* Marvell Phy Initailization */
1564static void yukon_init(struct skge_hw *hw, int port)
1565{
1566 struct skge_port *skge = netdev_priv(hw->dev[port]);
1567 u16 ctrl, ct1000, adv;
1568 u16 ledctrl, ledover;
1569
1570 pr_debug("yukon_init\n");
1571 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1572 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1573
1574 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1575 PHY_M_EC_MAC_S_MSK);
1576 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1577
c506a509 1578 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1579
6b0c1480 1580 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1581 }
1582
6b0c1480 1583 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1584 if (skge->autoneg == AUTONEG_DISABLE)
1585 ctrl &= ~PHY_CT_ANE;
1586
1587 ctrl |= PHY_CT_RESET;
6b0c1480 1588 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1589
1590 ctrl = 0;
1591 ct1000 = 0;
b18f2091 1592 adv = PHY_AN_CSMA;
baef58b1
SH		 1593
1594 if (skge->autoneg == AUTONEG_ENABLE) {
1595 if (iscopper(hw)) {
1596 if (skge->advertising & ADVERTISED_1000baseT_Full)
1597 ct1000 |= PHY_M_1000C_AFD;
1598 if (skge->advertising & ADVERTISED_1000baseT_Half)
1599 ct1000 |= PHY_M_1000C_AHD;
1600 if (skge->advertising & ADVERTISED_100baseT_Full)
1601 adv |= PHY_M_AN_100_FD;
1602 if (skge->advertising & ADVERTISED_100baseT_Half)
1603 adv |= PHY_M_AN_100_HD;
1604 if (skge->advertising & ADVERTISED_10baseT_Full)
1605 adv |= PHY_M_AN_10_FD;
1606 if (skge->advertising & ADVERTISED_10baseT_Half)
1607 adv |= PHY_M_AN_10_HD;
45bada65 1608 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1609 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1610
45bada65
SH		 1611 /* Set Flow-control capabilities */
1612 adv |= phy_pause_map[skge->flow_control];
1613
baef58b1
SH		 1614 /* Restart Auto-negotiation */
1615 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1616 } else {
1617 /* forced speed/duplex settings */
1618 ct1000 = PHY_M_1000C_MSE;
1619
1620 if (skge->duplex == DUPLEX_FULL)
1621 ctrl |= PHY_CT_DUP_MD;
1622
1623 switch (skge->speed) {
1624 case SPEED_1000:
1625 ctrl |= PHY_CT_SP1000;
1626 break;
1627 case SPEED_100:
1628 ctrl |= PHY_CT_SP100;
1629 break;
1630 }
1631
1632 ctrl |= PHY_CT_RESET;
1633 }
1634
c506a509 1635 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1636
6b0c1480
SH		 1637 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1638 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1639
1640 /* Setup Phy LED's */
1641 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
1642 ledover = 0;
1643
c506a509 1644 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
baef58b1 1645
c506a509
SH		 1646 /* turn off the Rx LED (LED_RX) */
1647 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
baef58b1
SH		 1648
1649 /* disable blink mode (LED_DUPLEX) on collisions */
1650 ctrl |= PHY_M_LEDC_DP_CTRL;
6b0c1480 1651 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
baef58b1
SH		 1652
1653 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1654 /* turn on 100 Mbps LED (LED_LINK100) */
1655 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
1656 }
1657
1658 if (ledover)
6b0c1480 1659 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
baef58b1
SH		 1660
1661 /* Enable phy interrupt on autonegotiation complete (or link up) */
1662 if (skge->autoneg == AUTONEG_ENABLE)
6b0c1480 1663 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
baef58b1 1664 else
6b0c1480 1665 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1666}
1667
1668static void yukon_reset(struct skge_hw *hw, int port)
1669{
6b0c1480
SH		 1670 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1671 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1672 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1673 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1674 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1675
6b0c1480
SH		 1676 gma_write16(hw, port, GM_RX_CTRL,
1677 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1678 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1679}
1680
1681static void yukon_mac_init(struct skge_hw *hw, int port)
1682{
1683 struct skge_port *skge = netdev_priv(hw->dev[port]);
1684 int i;
1685 u32 reg;
1686 const u8 *addr = hw->dev[port]->dev_addr;
1687
1688 /* WA code for COMA mode -- set PHY reset */
1689 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
38231713 1690 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
baef58b1
SH		 1691 skge_write32(hw, B2_GP_IO,
1692 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1693
1694 /* hard reset */
6b0c1480
SH		 1695 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1696 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1697
1698 /* WA code for COMA mode -- clear PHY reset */
1699 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
38231713 1700 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
baef58b1
SH		 1701 skge_write32(hw, B2_GP_IO,
1702 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1703 & ~GP_IO_9);
1704
1705 /* Set hardware config mode */
1706 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1707 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1708 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1709
1710 /* Clear GMC reset */
6b0c1480
SH		 1711 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1712 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1713 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
baef58b1
SH		 1714 if (skge->autoneg == AUTONEG_DISABLE) {
1715 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1716 gma_write16(hw, port, GM_GP_CTRL,
1717 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1718
1719 switch (skge->speed) {
1720 case SPEED_1000:
1721 reg |= GM_GPCR_SPEED_1000;
1722 /* fallthru */
1723 case SPEED_100:
1724 reg |= GM_GPCR_SPEED_100;
1725 }
1726
1727 if (skge->duplex == DUPLEX_FULL)
1728 reg |= GM_GPCR_DUP_FULL;
1729 } else
1730 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1731 switch (skge->flow_control) {
1732 case FLOW_MODE_NONE:
6b0c1480 1733 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1734 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1735 break;
1736 case FLOW_MODE_LOC_SEND:
1737 /* disable Rx flow-control */
1738 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1739 }
1740
6b0c1480 1741 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1
SH		 1742 skge_read16(hw, GMAC_IRQ_SRC);
1743
baef58b1 1744 yukon_init(hw, port);
baef58b1
SH		 1745
1746 /* MIB clear */
6b0c1480
SH		 1747 reg = gma_read16(hw, port, GM_PHY_ADDR);
1748 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1749
1750 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1751 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1752 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1753
1754 /* transmit control */
6b0c1480 1755 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1756
1757 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1758 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1759 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1760
1761 /* transmit flow control */
6b0c1480 1762 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1763
1764 /* transmit parameter */
6b0c1480 1765 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1766 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1767 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1768 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1769
1770 /* serial mode register */
1771 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1772 if (hw->dev[port]->mtu > 1500)
1773 reg |= GM_SMOD_JUMBO_ENA;
1774
6b0c1480 1775 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1776
1777 /* physical address: used for pause frames */
6b0c1480 1778 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1779 /* virtual address for data */
6b0c1480 1780 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1781
1782 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1783 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1784 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1785 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1786
1787 /* Initialize Mac Fifo */
1788
1789 /* Configure Rx MAC FIFO */
6b0c1480 1790 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1
SH		 1791 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1792 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
38231713 1793 hw->chip_rev >= CHIP_REV_YU_LITE_A3)
baef58b1 1794 reg &= ~GMF_RX_F_FL_ON;
6b0c1480
SH		 1795 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1796 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1797 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
baef58b1
SH		 1798
1799 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1800 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1801 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1802}
1803
1804static void yukon_stop(struct skge_port *skge)
1805{
1806 struct skge_hw *hw = skge->hw;
1807 int port = skge->port;
1808
1809 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
38231713 1810 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
baef58b1
SH		 1811 skge_write32(hw, B2_GP_IO,
1812 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1813 }
1814
6b0c1480
SH		 1815 gma_write16(hw, port, GM_GP_CTRL,
1816 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 1817 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1818 gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1819
1820 /* set GPHY Control reset */
6b0c1480
SH		 1821 gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1822 gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
baef58b1
SH		 1823}
1824
1825static void yukon_get_stats(struct skge_port *skge, u64 *data)
1826{
1827 struct skge_hw *hw = skge->hw;
1828 int port = skge->port;
1829 int i;
1830
6b0c1480
SH		 1831 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1832 | gma_read32(hw, port, GM_TXO_OK_LO);
1833 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1834 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1835
1836 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1837 data[i] = gma_read32(hw, port,
baef58b1
SH		 1838 skge_stats[i].gma_offset);
1839}
1840
1841static void yukon_mac_intr(struct skge_hw *hw, int port)
1842{
7e676d91
SH		 1843 struct net_device *dev = hw->dev[port];
1844 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1845 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1846
7e676d91
SH		 1847 if (netif_msg_intr(skge))
1848 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1849 dev->name, status);
1850
baef58b1
SH		 1851 if (status & GM_IS_RX_FF_OR) {
1852 ++skge->net_stats.rx_fifo_errors;
6b0c1480 1853 gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
baef58b1
SH		 1854 }
1855 if (status & GM_IS_TX_FF_UR) {
1856 ++skge->net_stats.tx_fifo_errors;
6b0c1480 1857 gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
baef58b1
SH		 1858 }
1859
1860}
1861
1862static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1863{
95566065 1864 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1865 case PHY_M_PS_SPEED_1000:
1866 return SPEED_1000;
1867 case PHY_M_PS_SPEED_100:
1868 return SPEED_100;
1869 default:
1870 return SPEED_10;
1871 }
1872}
1873
1874static void yukon_link_up(struct skge_port *skge)
1875{
1876 struct skge_hw *hw = skge->hw;
1877 int port = skge->port;
1878 u16 reg;
1879
1880 pr_debug("yukon_link_up\n");
1881
1882 /* Enable Transmit FIFO Underrun */
1883 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1884
6b0c1480 1885 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1886 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1887 reg |= GM_GPCR_DUP_FULL;
1888
1889 /* enable Rx/Tx */
1890 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1891 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1892
6b0c1480 1893 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1894 skge_link_up(skge);
1895}
1896
1897static void yukon_link_down(struct skge_port *skge)
1898{
1899 struct skge_hw *hw = skge->hw;
1900 int port = skge->port;
1901
1902 pr_debug("yukon_link_down\n");
6b0c1480
SH		 1903 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1904 gm_phy_write(hw, port, GM_GP_CTRL,
1905 gm_phy_read(hw, port, GM_GP_CTRL)
baef58b1
SH		 1906 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
1907
c506a509 1908 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 1909 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1910 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1911 gm_phy_read(hw, port,
baef58b1
SH		 1912 PHY_MARV_AUNE_ADV)
1913 | PHY_M_AN_ASP);
1914
1915 }
1916
1917 yukon_reset(hw, port);
1918 skge_link_down(skge);
1919
1920 yukon_init(hw, port);
1921}
1922
1923static void yukon_phy_intr(struct skge_port *skge)
1924{
1925 struct skge_hw *hw = skge->hw;
1926 int port = skge->port;
1927 const char *reason = NULL;
1928 u16 istatus, phystat;
1929
6b0c1480
SH		 1930 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1931 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 1932
1933 if (netif_msg_intr(skge))
1934 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1935 skge->netdev->name, istatus, phystat);
baef58b1
SH		 1936
1937 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 1938 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 1939 & PHY_M_AN_RF) {
1940 reason = "remote fault";
1941 goto failed;
1942 }
1943
c506a509 1944 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 1945 reason = "master/slave fault";
1946 goto failed;
1947 }
1948
1949 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1950 reason = "speed/duplex";
1951 goto failed;
1952 }
1953
1954 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1955 ? DUPLEX_FULL : DUPLEX_HALF;
1956 skge->speed = yukon_speed(hw, phystat);
1957
baef58b1
SH		 1958 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1959 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1960 case PHY_M_PS_PAUSE_MSK:
1961 skge->flow_control = FLOW_MODE_SYMMETRIC;
1962 break;
1963 case PHY_M_PS_RX_P_EN:
1964 skge->flow_control = FLOW_MODE_REM_SEND;
1965 break;
1966 case PHY_M_PS_TX_P_EN:
1967 skge->flow_control = FLOW_MODE_LOC_SEND;
1968 break;
1969 default:
1970 skge->flow_control = FLOW_MODE_NONE;
1971 }
1972
1973 if (skge->flow_control == FLOW_MODE_NONE ||
1974 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 1975 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 1976 else
6b0c1480 1977 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 1978 yukon_link_up(skge);
1979 return;
1980 }
1981
1982 if (istatus & PHY_M_IS_LSP_CHANGE)
1983 skge->speed = yukon_speed(hw, phystat);
1984
1985 if (istatus & PHY_M_IS_DUP_CHANGE)
1986 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1987 if (istatus & PHY_M_IS_LST_CHANGE) {
1988 if (phystat & PHY_M_PS_LINK_UP)
1989 yukon_link_up(skge);
1990 else
1991 yukon_link_down(skge);
1992 }
1993 return;
1994 failed:
1995 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
1996 skge->netdev->name, reason);
1997
1998 /* XXX restart autonegotiation? */
1999}
2000
2001static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2002{
2003 u32 end;
2004
2005 start /= 8;
2006 len /= 8;
2007 end = start + len - 1;
2008
2009 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2010 skge_write32(hw, RB_ADDR(q, RB_START), start);
2011 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2012 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2013 skge_write32(hw, RB_ADDR(q, RB_END), end);
2014
2015 if (q == Q_R1 || q == Q_R2) {
2016 /* Set thresholds on receive queue's */
2017 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2018 start + (2*len)/3);
2019 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2020 start + (len/3));
2021 } else {
2022 /* Enable store & forward on Tx queue's because
2023 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2024 */
2025 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2026 }
2027
2028 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2029}
2030
2031/* Setup Bus Memory Interface */
2032static void skge_qset(struct skge_port *skge, u16 q,
2033 const struct skge_element *e)
2034{
2035 struct skge_hw *hw = skge->hw;
2036 u32 watermark = 0x600;
2037 u64 base = skge->dma + (e->desc - skge->mem);
2038
2039 /* optimization to reduce window on 32bit/33mhz */
2040 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2041 watermark /= 2;
2042
2043 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2044 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2045 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2046 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2047}
2048
2049static int skge_up(struct net_device *dev)
2050{
2051 struct skge_port *skge = netdev_priv(dev);
2052 struct skge_hw *hw = skge->hw;
2053 int port = skge->port;
2054 u32 chunk, ram_addr;
2055 size_t rx_size, tx_size;
2056 int err;
2057
2058 if (netif_msg_ifup(skge))
2059 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2060
19a33d4e
SH		 2061 if (dev->mtu > RX_BUF_SIZE)
2062 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2063 else
2064 skge->rx_buf_size = RX_BUF_SIZE;
2065
2066
baef58b1
SH		 2067 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2068 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2069 skge->mem_size = tx_size + rx_size;
2070 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2071 if (!skge->mem)
2072 return -ENOMEM;
2073
2074 memset(skge->mem, 0, skge->mem_size);
2075
2076 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2077 goto free_pci_mem;
2078
19a33d4e
SH		 2079 err = skge_rx_fill(skge);
2080 if (err)
baef58b1
SH		 2081 goto free_rx_ring;
2082
2083 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2084 skge->dma + rx_size)))
2085 goto free_rx_ring;
2086
2087 skge->tx_avail = skge->tx_ring.count - 1;
2088
7e676d91
SH		 2089 /* Enable IRQ from port */
2090 hw->intr_mask |= portirqmask[port];
2091 skge_write32(hw, B0_IMSK, hw->intr_mask);
2092
baef58b1 2093 /* Initialze MAC */
4ff6ac05 2094 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2095 if (hw->chip_id == CHIP_ID_GENESIS)
2096 genesis_mac_init(hw, port);
2097 else
2098 yukon_mac_init(hw, port);
4ff6ac05 2099 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 2100
2101 /* Configure RAMbuffers */
981d0377 2102 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2103 ram_addr = hw->ram_offset + 2 * chunk * port;
2104
2105 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2106 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2107
2108 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2109 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2110 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2111
2112 /* Start receiver BMU */
2113 wmb();
2114 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2115
2116 pr_debug("skge_up completed\n");
2117 return 0;
2118
2119 free_rx_ring:
2120 skge_rx_clean(skge);
2121 kfree(skge->rx_ring.start);
2122 free_pci_mem:
2123 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2124
2125 return err;
2126}
2127
2128static int skge_down(struct net_device *dev)
2129{
2130 struct skge_port *skge = netdev_priv(dev);
2131 struct skge_hw *hw = skge->hw;
2132 int port = skge->port;
2133
2134 if (netif_msg_ifdown(skge))
2135 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2136
2137 netif_stop_queue(dev);
2138
2139 del_timer_sync(&skge->led_blink);
baef58b1
SH		 2140
2141 /* Stop transmitter */
2142 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2143 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2144 RB_RST_SET|RB_DIS_OP_MD);
2145
2146 if (hw->chip_id == CHIP_ID_GENESIS)
2147 genesis_stop(skge);
2148 else
2149 yukon_stop(skge);
2150
2151 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2152 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2153 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2154
2155 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2156 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2157 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2158
2159 /* Reset PCI FIFO */
2160 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2161 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2162
2163 /* Reset the RAM Buffer async Tx queue */
2164 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2165 /* stop receiver */
2166 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2167 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2168 RB_RST_SET|RB_DIS_OP_MD);
2169 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2170
2171 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2172 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2173 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2174 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
2175 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
baef58b1 2176 } else {
6b0c1480
SH		 2177 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2178 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2179 }
2180
2181 /* turn off led's */
2182 skge_write16(hw, B0_LED, LED_STAT_OFF);
2183
2184 skge_tx_clean(skge);
2185 skge_rx_clean(skge);
2186
2187 kfree(skge->rx_ring.start);
2188 kfree(skge->tx_ring.start);
2189 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2190 return 0;
2191}
2192
2193static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2194{
2195 struct skge_port *skge = netdev_priv(dev);
2196 struct skge_hw *hw = skge->hw;
2197 struct skge_ring *ring = &skge->tx_ring;
2198 struct skge_element *e;
2199 struct skge_tx_desc *td;
2200 int i;
2201 u32 control, len;
2202 u64 map;
2203 unsigned long flags;
2204
2205 skb = skb_padto(skb, ETH_ZLEN);
2206 if (!skb)
2207 return NETDEV_TX_OK;
2208
2209 local_irq_save(flags);
2210 if (!spin_trylock(&skge->tx_lock)) {
95566065
SH		 2211 /* Collision - tell upper layer to requeue */
2212 local_irq_restore(flags);
2213 return NETDEV_TX_LOCKED;
2214 }
baef58b1
SH		 2215
2216 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2217 netif_stop_queue(dev);
2218 spin_unlock_irqrestore(&skge->tx_lock, flags);
2219
2220 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2221 dev->name);
2222 return NETDEV_TX_BUSY;
2223 }
2224
2225 e = ring->to_use;
2226 td = e->desc;
2227 e->skb = skb;
2228 len = skb_headlen(skb);
2229 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2230 pci_unmap_addr_set(e, mapaddr, map);
2231 pci_unmap_len_set(e, maplen, len);
2232
2233 td->dma_lo = map;
2234 td->dma_hi = map >> 32;
2235
2236 if (skb->ip_summed == CHECKSUM_HW) {
2237 const struct iphdr *ip
2238 = (const struct iphdr *) (skb->data + ETH_HLEN);
2239 int offset = skb->h.raw - skb->data;
2240
2241 /* This seems backwards, but it is what the sk98lin
2242 * does. Looks like hardware is wrong?
2243 */
2244 if (ip->protocol == IPPROTO_UDP
981d0377 2245 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2246 control = BMU_TCP_CHECK;
2247 else
2248 control = BMU_UDP_CHECK;
2249
2250 td->csum_offs = 0;
2251 td->csum_start = offset;
2252 td->csum_write = offset + skb->csum;
2253 } else
2254 control = BMU_CHECK;
2255
2256 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2257 control |= BMU_EOF| BMU_IRQ_EOF;
2258 else {
2259 struct skge_tx_desc *tf = td;
2260
2261 control |= BMU_STFWD;
2262 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2263 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2264
2265 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2266 frag->size, PCI_DMA_TODEVICE);
2267
2268 e = e->next;
2269 e->skb = NULL;
2270 tf = e->desc;
2271 tf->dma_lo = map;
2272 tf->dma_hi = (u64) map >> 32;
2273 pci_unmap_addr_set(e, mapaddr, map);
2274 pci_unmap_len_set(e, maplen, frag->size);
2275
2276 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2277 }
2278 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2279 }
2280 /* Make sure all the descriptors written */
2281 wmb();
2282 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2283 wmb();
2284
2285 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2286
2287 if (netif_msg_tx_queued(skge))
0b2d7fea 2288 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2289 dev->name, e - ring->start, skb->len);
2290
2291 ring->to_use = e->next;
2292 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2293 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2294 pr_debug("%s: transmit queue full\n", dev->name);
2295 netif_stop_queue(dev);
2296 }
2297
2298 dev->trans_start = jiffies;
2299 spin_unlock_irqrestore(&skge->tx_lock, flags);
2300
2301 return NETDEV_TX_OK;
2302}
2303
2304static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2305{
19a33d4e 2306 /* This ring element can be skb or fragment */
baef58b1
SH		 2307 if (e->skb) {
2308 pci_unmap_single(hw->pdev,
2309 pci_unmap_addr(e, mapaddr),
2310 pci_unmap_len(e, maplen),
2311 PCI_DMA_TODEVICE);
2312 dev_kfree_skb_any(e->skb);
2313 e->skb = NULL;
2314 } else {
2315 pci_unmap_page(hw->pdev,
2316 pci_unmap_addr(e, mapaddr),
2317 pci_unmap_len(e, maplen),
2318 PCI_DMA_TODEVICE);
2319 }
2320}
2321
2322static void skge_tx_clean(struct skge_port *skge)
2323{
2324 struct skge_ring *ring = &skge->tx_ring;
2325 struct skge_element *e;
2326 unsigned long flags;
2327
2328 spin_lock_irqsave(&skge->tx_lock, flags);
2329 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2330 ++skge->tx_avail;
2331 skge_tx_free(skge->hw, e);
2332 }
2333 ring->to_clean = e;
2334 spin_unlock_irqrestore(&skge->tx_lock, flags);
2335}
2336
2337static void skge_tx_timeout(struct net_device *dev)
2338{
2339 struct skge_port *skge = netdev_priv(dev);
2340
2341 if (netif_msg_timer(skge))
2342 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2343
2344 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2345 skge_tx_clean(skge);
2346}
2347
2348static int skge_change_mtu(struct net_device *dev, int new_mtu)
2349{
2350 int err = 0;
19a33d4e 2351 int running = netif_running(dev);
baef58b1 2352
95566065 2353 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2354 return -EINVAL;
2355
baef58b1 2356
19a33d4e 2357 if (running)
baef58b1 2358 skge_down(dev);
19a33d4e
SH		 2359 dev->mtu = new_mtu;
2360 if (running)
baef58b1 2361 skge_up(dev);
baef58b1
SH		 2362
2363 return err;
2364}
2365
2366static void genesis_set_multicast(struct net_device *dev)
2367{
2368 struct skge_port *skge = netdev_priv(dev);
2369 struct skge_hw *hw = skge->hw;
2370 int port = skge->port;
2371 int i, count = dev->mc_count;
2372 struct dev_mc_list *list = dev->mc_list;
2373 u32 mode;
2374 u8 filter[8];
2375
45bada65
SH		 2376 pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
2377
6b0c1480 2378 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2379 mode |= XM_MD_ENA_HASH;
2380 if (dev->flags & IFF_PROMISC)
2381 mode |= XM_MD_ENA_PROM;
2382 else
2383 mode &= ~XM_MD_ENA_PROM;
2384
2385 if (dev->flags & IFF_ALLMULTI)
2386 memset(filter, 0xff, sizeof(filter));
2387 else {
2388 memset(filter, 0, sizeof(filter));
95566065 2389 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2390 u32 crc, bit;
2391 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2392 bit = ~crc & 0x3f;
baef58b1
SH		 2393 filter[bit/8] |= 1 << (bit%8);
2394 }
2395 }
2396
6b0c1480 2397 xm_write32(hw, port, XM_MODE, mode);
45bada65 2398 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2399}
2400
2401static void yukon_set_multicast(struct net_device *dev)
2402{
2403 struct skge_port *skge = netdev_priv(dev);
2404 struct skge_hw *hw = skge->hw;
2405 int port = skge->port;
2406 struct dev_mc_list *list = dev->mc_list;
2407 u16 reg;
2408 u8 filter[8];
2409
2410 memset(filter, 0, sizeof(filter));
2411
6b0c1480 2412 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2413 reg |= GM_RXCR_UCF_ENA;
2414
2415 if (dev->flags & IFF_PROMISC) /* promiscious */
2416 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2417 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2418 memset(filter, 0xff, sizeof(filter));
2419 else if (dev->mc_count == 0) /* no multicast */
2420 reg &= ~GM_RXCR_MCF_ENA;
2421 else {
2422 int i;
2423 reg |= GM_RXCR_MCF_ENA;
2424
95566065 2425 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2426 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2427 filter[bit/8] |= 1 << (bit%8);
2428 }
2429 }
2430
2431
6b0c1480 2432 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2433 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2434 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2435 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2436 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2437 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2438 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2439 (u16)filter[6] | ((u16)filter[7] << 8));
2440
6b0c1480 2441 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2442}
2443
2444static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2445{
2446 if (hw->chip_id == CHIP_ID_GENESIS)
2447 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2448 else
2449 return (status & GMR_FS_ANY_ERR) ||
2450 (status & GMR_FS_RX_OK) == 0;
2451}
2452
2453static void skge_rx_error(struct skge_port *skge, int slot,
2454 u32 control, u32 status)
2455{
2456 if (netif_msg_rx_err(skge))
2457 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2458 skge->netdev->name, slot, control, status);
2459
19a33d4e 2460 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
baef58b1 2461 skge->net_stats.rx_length_errors++;
19a33d4e
SH		 2462 else if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2463 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2464 skge->net_stats.rx_length_errors++;
2465 if (status & XMR_FS_FRA_ERR)
2466 skge->net_stats.rx_frame_errors++;
2467 if (status & XMR_FS_FCS_ERR)
2468 skge->net_stats.rx_crc_errors++;
2469 } else {
2470 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2471 skge->net_stats.rx_length_errors++;
2472 if (status & GMR_FS_FRAGMENT)
2473 skge->net_stats.rx_frame_errors++;
2474 if (status & GMR_FS_CRC_ERR)
2475 skge->net_stats.rx_crc_errors++;
2476 }
2477}
2478
2479/* Get receive buffer from descriptor.
2480 * Handles copy of small buffers and reallocation failures
2481 */
2482static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2483 struct skge_element *e,
2484 unsigned int len)
2485{
2486 struct sk_buff *nskb, *skb;
2487
2488 if (len < RX_COPY_THRESHOLD) {
2489 nskb = skge_rx_alloc(skge->netdev, len + NET_IP_ALIGN);
2490 if (unlikely(!nskb))
2491 return NULL;
2492
2493 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2494 pci_unmap_addr(e, mapaddr),
2495 len, PCI_DMA_FROMDEVICE);
2496 memcpy(nskb->data, e->skb->data, len);
2497 pci_dma_sync_single_for_device(skge->hw->pdev,
2498 pci_unmap_addr(e, mapaddr),
2499 len, PCI_DMA_FROMDEVICE);
2500
2501 if (skge->rx_csum) {
2502 struct skge_rx_desc *rd = e->desc;
2503 nskb->csum = le16_to_cpu(rd->csum2);
2504 nskb->ip_summed = CHECKSUM_HW;
baef58b1 2505 }
19a33d4e
SH		 2506 skge_rx_reuse(e, skge->rx_buf_size);
2507 return nskb;
2508 } else {
2509 nskb = skge_rx_alloc(skge->netdev, skge->rx_buf_size);
2510 if (unlikely(!nskb))
2511 return NULL;
2512
2513 pci_unmap_single(skge->hw->pdev,
2514 pci_unmap_addr(e, mapaddr),
2515 pci_unmap_len(e, maplen),
2516 PCI_DMA_FROMDEVICE);
2517 skb = e->skb;
2518 if (skge->rx_csum) {
2519 struct skge_rx_desc *rd = e->desc;
2520 skb->csum = le16_to_cpu(rd->csum2);
2521 skb->ip_summed = CHECKSUM_HW;
2522 }
2523
2524 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2525 return skb;
baef58b1
SH		 2526 }
2527}
2528
19a33d4e 2529
baef58b1
SH		 2530static int skge_poll(struct net_device *dev, int *budget)
2531{
2532 struct skge_port *skge = netdev_priv(dev);
2533 struct skge_hw *hw = skge->hw;
2534 struct skge_ring *ring = &skge->rx_ring;
2535 struct skge_element *e;
2536 unsigned int to_do = min(dev->quota, *budget);
2537 unsigned int work_done = 0;
7e676d91
SH		 2538
2539 pr_debug("skge_poll\n");
baef58b1 2540
19a33d4e 2541 for (e = ring->to_clean; work_done < to_do; e = e->next) {
baef58b1 2542 struct skge_rx_desc *rd = e->desc;
19a33d4e 2543 struct sk_buff *skb;
baef58b1
SH		 2544 u32 control, len, status;
2545
2546 rmb();
2547 control = rd->control;
2548 if (control & BMU_OWN)
2549 break;
2550
2551 len = control & BMU_BBC;
baef58b1 2552 status = rd->status;
19a33d4e
SH		 2553
2554 if (unlikely((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2555 || bad_phy_status(hw, status))) {
baef58b1 2556 skge_rx_error(skge, e - ring->start, control, status);
19a33d4e 2557 skge_rx_reuse(e, skge->rx_buf_size);
baef58b1
SH		 2558 continue;
2559 }
2560
2561 if (netif_msg_rx_status(skge))
0b2d7fea 2562 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
baef58b1
SH		 2563 dev->name, e - ring->start, rd->status, len);
2564
19a33d4e
SH		 2565 skb = skge_rx_get(skge, e, len);
2566 if (likely(skb)) {
2567 skb_put(skb, len);
2568 skb->protocol = eth_type_trans(skb, dev);
baef58b1 2569
19a33d4e
SH		 2570 dev->last_rx = jiffies;
2571 netif_receive_skb(skb);
baef58b1 2572
19a33d4e
SH		 2573 ++work_done;
2574 } else
2575 skge_rx_reuse(e, skge->rx_buf_size);
baef58b1
SH		 2576 }
2577 ring->to_clean = e;
2578
baef58b1
SH		 2579 /* restart receiver */
2580 wmb();
2581 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2582 CSR_START | CSR_IRQ_CL_F);
2583
19a33d4e
SH		 2584 *budget -= work_done;
2585 dev->quota -= work_done;
2586
2587 if (work_done >= to_do)
2588 return 1; /* not done */
baef58b1 2589
19a33d4e
SH		 2590 local_irq_disable();
2591 __netif_rx_complete(dev);
2592 hw->intr_mask |= portirqmask[skge->port];
2593 skge_write32(hw, B0_IMSK, hw->intr_mask);
2594 local_irq_enable();
2595 return 0;
baef58b1
SH		 2596}
2597
2598static inline void skge_tx_intr(struct net_device *dev)
2599{
2600 struct skge_port *skge = netdev_priv(dev);
2601 struct skge_hw *hw = skge->hw;
2602 struct skge_ring *ring = &skge->tx_ring;
2603 struct skge_element *e;
2604
2605 spin_lock(&skge->tx_lock);
95566065 2606 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
baef58b1
SH		 2607 struct skge_tx_desc *td = e->desc;
2608 u32 control;
2609
2610 rmb();
2611 control = td->control;
2612 if (control & BMU_OWN)
2613 break;
2614
2615 if (unlikely(netif_msg_tx_done(skge)))
0b2d7fea 2616 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
baef58b1
SH		 2617 dev->name, e - ring->start, td->status);
2618
2619 skge_tx_free(hw, e);
2620 e->skb = NULL;
2621 ++skge->tx_avail;
2622 }
2623 ring->to_clean = e;
2624 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2625
2626 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2627 netif_wake_queue(dev);
2628
2629 spin_unlock(&skge->tx_lock);
2630}
2631
f6620cab
SH		 2632/* Parity errors seem to happen when Genesis is connected to a switch
2633 * with no other ports present. Heartbeat error??
2634 */
baef58b1
SH		 2635static void skge_mac_parity(struct skge_hw *hw, int port)
2636{
f6620cab
SH		 2637 struct net_device *dev = hw->dev[port];
2638
2639 if (dev) {
2640 struct skge_port *skge = netdev_priv(dev);
2641 ++skge->net_stats.tx_heartbeat_errors;
2642 }
baef58b1
SH		 2643
2644 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2645 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2646 MFF_CLR_PERR);
2647 else
2648 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2649 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2650 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2651 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2652}
2653
2654static void skge_pci_clear(struct skge_hw *hw)
2655{
2656 u16 status;
2657
467b3417 2658 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
baef58b1 2659 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
467b3417
SH		 2660 pci_write_config_word(hw->pdev, PCI_STATUS,
2661 status | PCI_STATUS_ERROR_BITS);
baef58b1
SH		 2662 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2663}
2664
2665static void skge_mac_intr(struct skge_hw *hw, int port)
2666{
95566065 2667 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2668 genesis_mac_intr(hw, port);
2669 else
2670 yukon_mac_intr(hw, port);
2671}
2672
2673/* Handle device specific framing and timeout interrupts */
2674static void skge_error_irq(struct skge_hw *hw)
2675{
2676 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2677
2678 if (hw->chip_id == CHIP_ID_GENESIS) {
2679 /* clear xmac errors */
2680 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
6b0c1480 2681 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
baef58b1 2682 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
6b0c1480 2683 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
baef58b1
SH		 2684 } else {
2685 /* Timestamp (unused) overflow */
2686 if (hwstatus & IS_IRQ_TIST_OV)
2687 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2688
2689 if (hwstatus & IS_IRQ_SENSOR) {
2690 /* no sensors on 32-bit Yukon */
2691 if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
2692 printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
2693 skge_write32(hw, B0_HWE_IMSK,
2694 IS_ERR_MSK & ~IS_IRQ_SENSOR);
2695 } else
2696 printk(KERN_WARNING PFX "sensor interrupt\n");
2697 }
2698
2699
2700 }
2701
2702 if (hwstatus & IS_RAM_RD_PAR) {
2703 printk(KERN_ERR PFX "Ram read data parity error\n");
2704 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2705 }
2706
2707 if (hwstatus & IS_RAM_WR_PAR) {
2708 printk(KERN_ERR PFX "Ram write data parity error\n");
2709 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2710 }
2711
2712 if (hwstatus & IS_M1_PAR_ERR)
2713 skge_mac_parity(hw, 0);
2714
2715 if (hwstatus & IS_M2_PAR_ERR)
2716 skge_mac_parity(hw, 1);
2717
2718 if (hwstatus & IS_R1_PAR_ERR)
2719 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2720
2721 if (hwstatus & IS_R2_PAR_ERR)
2722 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2723
2724 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2725 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2726 hwstatus);
2727
2728 skge_pci_clear(hw);
2729
2730 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2731 if (hwstatus & IS_IRQ_STAT) {
2732 printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
2733 hwstatus);
2734 hw->intr_mask &= ~IS_HW_ERR;
2735 }
2736 }
2737}
2738
2739/*
2740 * Interrrupt from PHY are handled in tasklet (soft irq)
2741 * because accessing phy registers requires spin wait which might
2742 * cause excess interrupt latency.
2743 */
2744static void skge_extirq(unsigned long data)
2745{
2746 struct skge_hw *hw = (struct skge_hw *) data;
2747 int port;
2748
2749 spin_lock(&hw->phy_lock);
2750 for (port = 0; port < 2; port++) {
2751 struct net_device *dev = hw->dev[port];
2752
2753 if (dev && netif_running(dev)) {
2754 struct skge_port *skge = netdev_priv(dev);
2755
2756 if (hw->chip_id != CHIP_ID_GENESIS)
2757 yukon_phy_intr(skge);
89bf5f23 2758 else
45bada65 2759 bcom_phy_intr(skge);
baef58b1
SH		 2760 }
2761 }
2762 spin_unlock(&hw->phy_lock);
2763
2764 local_irq_disable();
2765 hw->intr_mask |= IS_EXT_REG;
2766 skge_write32(hw, B0_IMSK, hw->intr_mask);
2767 local_irq_enable();
2768}
2769
2770static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2771{
2772 struct skge_hw *hw = dev_id;
2773 u32 status = skge_read32(hw, B0_SP_ISRC);
2774
2775 if (status == 0 || status == ~0) /* hotplug or shared irq */
2776 return IRQ_NONE;
2777
2778 status &= hw->intr_mask;
7e676d91 2779 if (status & IS_R1_F) {
baef58b1 2780 hw->intr_mask &= ~IS_R1_F;
7e676d91 2781 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 2782 }
2783
7e676d91 2784 if (status & IS_R2_F) {
baef58b1 2785 hw->intr_mask &= ~IS_R2_F;
7e676d91 2786 netif_rx_schedule(hw->dev[1]);
baef58b1
SH		 2787 }
2788
2789 if (status & IS_XA1_F)
2790 skge_tx_intr(hw->dev[0]);
2791
2792 if (status & IS_XA2_F)
2793 skge_tx_intr(hw->dev[1]);
2794
d25f5a67
SH		 2795 if (status & IS_PA_TO_RX1) {
2796 struct skge_port *skge = netdev_priv(hw->dev[0]);
2797 ++skge->net_stats.rx_over_errors;
2798 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2799 }
2800
2801 if (status & IS_PA_TO_RX2) {
2802 struct skge_port *skge = netdev_priv(hw->dev[1]);
2803 ++skge->net_stats.rx_over_errors;
2804 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2805 }
2806
2807 if (status & IS_PA_TO_TX1)
2808 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2809
2810 if (status & IS_PA_TO_TX2)
2811 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2812
baef58b1
SH		 2813 if (status & IS_MAC1)
2814 skge_mac_intr(hw, 0);
95566065 2815
baef58b1
SH		 2816 if (status & IS_MAC2)
2817 skge_mac_intr(hw, 1);
2818
2819 if (status & IS_HW_ERR)
2820 skge_error_irq(hw);
2821
2822 if (status & IS_EXT_REG) {
2823 hw->intr_mask &= ~IS_EXT_REG;
2824 tasklet_schedule(&hw->ext_tasklet);
2825 }
2826
7e676d91 2827 skge_write32(hw, B0_IMSK, hw->intr_mask);
baef58b1
SH		 2828
2829 return IRQ_HANDLED;
2830}
2831
2832#ifdef CONFIG_NET_POLL_CONTROLLER
2833static void skge_netpoll(struct net_device *dev)
2834{
2835 struct skge_port *skge = netdev_priv(dev);
2836
2837 disable_irq(dev->irq);
2838 skge_intr(dev->irq, skge->hw, NULL);
2839 enable_irq(dev->irq);
2840}
2841#endif
2842
2843static int skge_set_mac_address(struct net_device *dev, void *p)
2844{
2845 struct skge_port *skge = netdev_priv(dev);
2846 struct sockaddr *addr = p;
2847 int err = 0;
2848
2849 if (!is_valid_ether_addr(addr->sa_data))
2850 return -EADDRNOTAVAIL;
2851
2852 skge_down(dev);
2853 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2854 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2855 dev->dev_addr, ETH_ALEN);
2856 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2857 dev->dev_addr, ETH_ALEN);
2858 if (dev->flags & IFF_UP)
2859 err = skge_up(dev);
2860 return err;
2861}
2862
2863static const struct {
2864 u8 id;
2865 const char *name;
2866} skge_chips[] = {
2867 { CHIP_ID_GENESIS, "Genesis" },
2868 { CHIP_ID_YUKON, "Yukon" },
2869 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2870 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 2871};
2872
2873static const char *skge_board_name(const struct skge_hw *hw)
2874{
2875 int i;
2876 static char buf[16];
2877
2878 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2879 if (skge_chips[i].id == hw->chip_id)
2880 return skge_chips[i].name;
2881
2882 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2883 return buf;
2884}
2885
2886
2887/*
2888 * Setup the board data structure, but don't bring up
2889 * the port(s)
2890 */
2891static int skge_reset(struct skge_hw *hw)
2892{
2893 u16 ctst;
981d0377
SH		 2894 u8 t8, mac_cfg;
2895 int i;
baef58b1
SH		 2896
2897 ctst = skge_read16(hw, B0_CTST);
2898
2899 /* do a SW reset */
2900 skge_write8(hw, B0_CTST, CS_RST_SET);
2901 skge_write8(hw, B0_CTST, CS_RST_CLR);
2902
2903 /* clear PCI errors, if any */
2904 skge_pci_clear(hw);
2905
2906 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2907
2908 /* restore CLK_RUN bits (for Yukon-Lite) */
2909 skge_write16(hw, B0_CTST,
2910 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2911
2912 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2913 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2914 hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
2915
95566065 2916 switch (hw->chip_id) {
baef58b1
SH		 2917 case CHIP_ID_GENESIS:
2918 switch (hw->phy_type) {
baef58b1
SH		 2919 case SK_PHY_BCOM:
2920 hw->phy_addr = PHY_ADDR_BCOM;
2921 break;
2922 default:
2923 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2924 pci_name(hw->pdev), hw->phy_type);
2925 return -EOPNOTSUPP;
2926 }
2927 break;
2928
2929 case CHIP_ID_YUKON:
2930 case CHIP_ID_YUKON_LITE:
2931 case CHIP_ID_YUKON_LP:
2932 if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
2933 hw->phy_type = SK_PHY_MARV_COPPER;
2934
2935 hw->phy_addr = PHY_ADDR_MARV;
2936 if (!iscopper(hw))
2937 hw->phy_type = SK_PHY_MARV_FIBER;
2938
2939 break;
2940
2941 default:
2942 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2943 pci_name(hw->pdev), hw->chip_id);
2944 return -EOPNOTSUPP;
2945 }
2946
981d0377
SH		 2947 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2948 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2949 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 2950
2951 /* read the adapters RAM size */
2952 t8 = skge_read8(hw, B2_E_0);
2953 if (hw->chip_id == CHIP_ID_GENESIS) {
2954 if (t8 == 3) {
2955 /* special case: 4 x 64k x 36, offset = 0x80000 */
2956 hw->ram_size = 0x100000;
2957 hw->ram_offset = 0x80000;
2958 } else
2959 hw->ram_size = t8 * 512;
2960 }
2961 else if (t8 == 0)
2962 hw->ram_size = 0x20000;
2963 else
2964 hw->ram_size = t8 * 4096;
2965
2966 if (hw->chip_id == CHIP_ID_GENESIS)
2967 genesis_init(hw);
2968 else {
2969 /* switch power to VCC (WA for VAUX problem) */
2970 skge_write8(hw, B0_POWER_CTRL,
2971 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
981d0377 2972 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 2973 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2974 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 2975 }
2976 }
2977
2978 /* turn off hardware timer (unused) */
2979 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2980 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2981 skge_write8(hw, B0_LED, LED_STAT_ON);
2982
2983 /* enable the Tx Arbiters */
981d0377 2984 for (i = 0; i < hw->ports; i++)
6b0c1480 2985 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 2986
2987 /* Initialize ram interface */
2988 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2989
2990 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2991 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2992 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2993 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2994 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2995 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2996 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2997 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2998 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2999 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3000 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3001 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3002
3003 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3004
3005 /* Set interrupt moderation for Transmit only
3006 * Receive interrupts avoided by NAPI
3007 */
3008 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3009 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3010 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3011
7e676d91 3012 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
baef58b1
SH		 3013 skge_write32(hw, B0_IMSK, hw->intr_mask);
3014
3015 if (hw->chip_id != CHIP_ID_GENESIS)
3016 skge_write8(hw, GMAC_IRQ_MSK, 0);
3017
3018 spin_lock_bh(&hw->phy_lock);
981d0377 3019 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3020 if (hw->chip_id == CHIP_ID_GENESIS)
3021 genesis_reset(hw, i);
3022 else
3023 yukon_reset(hw, i);
3024 }
3025 spin_unlock_bh(&hw->phy_lock);
3026
3027 return 0;
3028}
3029
3030/* Initialize network device */
981d0377
SH		 3031static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3032 int highmem)
baef58b1
SH		 3033{
3034 struct skge_port *skge;
3035 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3036
3037 if (!dev) {
3038 printk(KERN_ERR "skge etherdev alloc failed");
3039 return NULL;
3040 }
3041
3042 SET_MODULE_OWNER(dev);
3043 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3044 dev->open = skge_up;
3045 dev->stop = skge_down;
3046 dev->hard_start_xmit = skge_xmit_frame;
3047 dev->get_stats = skge_get_stats;
3048 if (hw->chip_id == CHIP_ID_GENESIS)
3049 dev->set_multicast_list = genesis_set_multicast;
3050 else
3051 dev->set_multicast_list = yukon_set_multicast;
3052
3053 dev->set_mac_address = skge_set_mac_address;
3054 dev->change_mtu = skge_change_mtu;
3055 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3056 dev->tx_timeout = skge_tx_timeout;
3057 dev->watchdog_timeo = TX_WATCHDOG;
3058 dev->poll = skge_poll;
3059 dev->weight = NAPI_WEIGHT;
3060#ifdef CONFIG_NET_POLL_CONTROLLER
3061 dev->poll_controller = skge_netpoll;
3062#endif
3063 dev->irq = hw->pdev->irq;
3064 dev->features = NETIF_F_LLTX;
981d0377
SH		 3065 if (highmem)
3066 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3067
3068 skge = netdev_priv(dev);
3069 skge->netdev = dev;
3070 skge->hw = hw;
3071 skge->msg_enable = netif_msg_init(debug, default_msg);
3072 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3073 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3074
3075 /* Auto speed and flow control */
3076 skge->autoneg = AUTONEG_ENABLE;
3077 skge->flow_control = FLOW_MODE_SYMMETRIC;
3078 skge->duplex = -1;
3079 skge->speed = -1;
31b619c5 3080 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3081
3082 hw->dev[port] = dev;
3083
3084 skge->port = port;
3085
3086 spin_lock_init(&skge->tx_lock);
3087
baef58b1
SH		 3088 init_timer(&skge->led_blink);
3089 skge->led_blink.function = skge_blink_timer;
3090 skge->led_blink.data = (unsigned long) skge;
3091
3092 if (hw->chip_id != CHIP_ID_GENESIS) {
3093 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3094 skge->rx_csum = 1;
3095 }
3096
3097 /* read the mac address */
3098 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3099
3100 /* device is off until link detection */
3101 netif_carrier_off(dev);
3102 netif_stop_queue(dev);
3103
3104 return dev;
3105}
3106
3107static void __devinit skge_show_addr(struct net_device *dev)
3108{
3109 const struct skge_port *skge = netdev_priv(dev);
3110
3111 if (netif_msg_probe(skge))
3112 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3113 dev->name,
3114 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3115 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3116}
3117
3118static int __devinit skge_probe(struct pci_dev *pdev,
3119 const struct pci_device_id *ent)
3120{
3121 struct net_device *dev, *dev1;
3122 struct skge_hw *hw;
3123 int err, using_dac = 0;
3124
3125 if ((err = pci_enable_device(pdev))) {
3126 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3127 pci_name(pdev));
3128 goto err_out;
3129 }
3130
3131 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3132 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3133 pci_name(pdev));
3134 goto err_out_disable_pdev;
3135 }
3136
3137 pci_set_master(pdev);
3138
3139 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3140 using_dac = 1;
3141 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3142 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3143 pci_name(pdev));
3144 goto err_out_free_regions;
3145 }
3146
3147#ifdef __BIG_ENDIAN
3148 /* byte swap decriptors in hardware */
3149 {
3150 u32 reg;
3151
3152 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3153 reg |= PCI_REV_DESC;
3154 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3155 }
3156#endif
3157
3158 err = -ENOMEM;
3159 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3160 if (!hw) {
3161 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3162 pci_name(pdev));
3163 goto err_out_free_regions;
3164 }
3165
3166 memset(hw, 0, sizeof(*hw));
3167 hw->pdev = pdev;
3168 spin_lock_init(&hw->phy_lock);
3169 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3170
3171 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3172 if (!hw->regs) {
3173 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3174 pci_name(pdev));
3175 goto err_out_free_hw;
3176 }
3177
3178 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3179 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3180 pci_name(pdev), pdev->irq);
3181 goto err_out_iounmap;
3182 }
3183 pci_set_drvdata(pdev, hw);
3184
3185 err = skge_reset(hw);
3186 if (err)
3187 goto err_out_free_irq;
3188
3189 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3190 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3191 skge_board_name(hw), hw->chip_rev);
baef58b1 3192
981d0377 3193 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3194 goto err_out_led_off;
3195
baef58b1
SH		 3196 if ((err = register_netdev(dev))) {
3197 printk(KERN_ERR PFX "%s: cannot register net device\n",
3198 pci_name(pdev));
3199 goto err_out_free_netdev;
3200 }
3201
3202 skge_show_addr(dev);
3203
981d0377 3204 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3205 if (register_netdev(dev1) == 0)
3206 skge_show_addr(dev1);
3207 else {
3208 /* Failure to register second port need not be fatal */
3209 printk(KERN_WARNING PFX "register of second port failed\n");
3210 hw->dev[1] = NULL;
3211 free_netdev(dev1);
3212 }
3213 }
3214
3215 return 0;
3216
3217err_out_free_netdev:
3218 free_netdev(dev);
3219err_out_led_off:
3220 skge_write16(hw, B0_LED, LED_STAT_OFF);
3221err_out_free_irq:
3222 free_irq(pdev->irq, hw);
3223err_out_iounmap:
3224 iounmap(hw->regs);
3225err_out_free_hw:
3226 kfree(hw);
3227err_out_free_regions:
3228 pci_release_regions(pdev);
3229err_out_disable_pdev:
3230 pci_disable_device(pdev);
3231 pci_set_drvdata(pdev, NULL);
3232err_out:
3233 return err;
3234}
3235
3236static void __devexit skge_remove(struct pci_dev *pdev)
3237{
3238 struct skge_hw *hw = pci_get_drvdata(pdev);
3239 struct net_device *dev0, *dev1;
3240
95566065 3241 if (!hw)
baef58b1
SH		 3242 return;
3243
3244 if ((dev1 = hw->dev[1]))
3245 unregister_netdev(dev1);
3246 dev0 = hw->dev[0];
3247 unregister_netdev(dev0);
3248
3249 tasklet_kill(&hw->ext_tasklet);
3250
3251 free_irq(pdev->irq, hw);
3252 pci_release_regions(pdev);
3253 pci_disable_device(pdev);
3254 if (dev1)
3255 free_netdev(dev1);
3256 free_netdev(dev0);
3257 skge_write16(hw, B0_LED, LED_STAT_OFF);
3258 iounmap(hw->regs);
3259 kfree(hw);
3260 pci_set_drvdata(pdev, NULL);
3261}
3262
3263#ifdef CONFIG_PM
2a569579 3264static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3265{
3266 struct skge_hw *hw = pci_get_drvdata(pdev);
3267 int i, wol = 0;
3268
95566065 3269 for (i = 0; i < 2; i++) {
baef58b1
SH		 3270 struct net_device *dev = hw->dev[i];
3271
3272 if (dev) {
3273 struct skge_port *skge = netdev_priv(dev);
3274 if (netif_running(dev)) {
3275 netif_carrier_off(dev);
3276 skge_down(dev);
3277 }
3278 netif_device_detach(dev);
3279 wol |= skge->wol;
3280 }
3281 }
3282
3283 pci_save_state(pdev);
2a569579 3284 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3285 pci_disable_device(pdev);
3286 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3287
3288 return 0;
3289}
3290
3291static int skge_resume(struct pci_dev *pdev)
3292{
3293 struct skge_hw *hw = pci_get_drvdata(pdev);
3294 int i;
3295
3296 pci_set_power_state(pdev, PCI_D0);
3297 pci_restore_state(pdev);
3298 pci_enable_wake(pdev, PCI_D0, 0);
3299
3300 skge_reset(hw);
3301
95566065 3302 for (i = 0; i < 2; i++) {
baef58b1
SH		 3303 struct net_device *dev = hw->dev[i];
3304 if (dev) {
3305 netif_device_attach(dev);
95566065 3306 if (netif_running(dev))
baef58b1
SH		 3307 skge_up(dev);
3308 }
3309 }
3310 return 0;
3311}
3312#endif
3313
3314static struct pci_driver skge_driver = {
3315 .name = DRV_NAME,
3316 .id_table = skge_id_table,
3317 .probe = skge_probe,
3318 .remove = __devexit_p(skge_remove),
3319#ifdef CONFIG_PM
3320 .suspend = skge_suspend,
3321 .resume = skge_resume,
3322#endif
3323};
3324
3325static int __init skge_init_module(void)
3326{
3327 return pci_module_init(&skge_driver);
3328}
3329
3330static void __exit skge_cleanup_module(void)
3331{
3332 pci_unregister_driver(&skge_driver);
3333}
3334
3335module_init(skge_init_module);
3336module_exit(skge_cleanup_module);
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