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Commit | Line | Data |
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baef58b1 SH |
1 | /* |
2 | * New driver for Marvell Yukon chipset and SysKonnect Gigabit | |
3 | * Ethernet adapters. Based on earlier sk98lin, e100 and | |
4 | * FreeBSD if_sk drivers. | |
5 | * | |
6 | * This driver intentionally does not support all the features | |
7 | * of the original driver such as link fail-over and link management because | |
8 | * those should be done at higher levels. | |
9 | * | |
747802ab | 10 | * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org> |
baef58b1 SH |
11 | * |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | */ | |
26 | ||
14c85021 | 27 | #include <linux/in.h> |
baef58b1 SH |
28 | #include <linux/kernel.h> |
29 | #include <linux/module.h> | |
30 | #include <linux/moduleparam.h> | |
31 | #include <linux/netdevice.h> | |
32 | #include <linux/etherdevice.h> | |
33 | #include <linux/ethtool.h> | |
34 | #include <linux/pci.h> | |
35 | #include <linux/if_vlan.h> | |
36 | #include <linux/ip.h> | |
37 | #include <linux/delay.h> | |
38 | #include <linux/crc32.h> | |
4075400b | 39 | #include <linux/dma-mapping.h> |
2cd8e5d3 | 40 | #include <linux/mii.h> |
baef58b1 SH |
41 | #include <asm/irq.h> |
42 | ||
43 | #include "skge.h" | |
44 | ||
45 | #define DRV_NAME "skge" | |
6fc47e31 | 46 | #define DRV_VERSION "1.7" |
baef58b1 SH |
47 | #define PFX DRV_NAME " " |
48 | ||
49 | #define DEFAULT_TX_RING_SIZE 128 | |
50 | #define DEFAULT_RX_RING_SIZE 512 | |
51 | #define MAX_TX_RING_SIZE 1024 | |
9db96479 | 52 | #define TX_LOW_WATER (MAX_SKB_FRAGS + 1) |
baef58b1 | 53 | #define MAX_RX_RING_SIZE 4096 |
19a33d4e SH |
54 | #define RX_COPY_THRESHOLD 128 |
55 | #define RX_BUF_SIZE 1536 | |
baef58b1 SH |
56 | #define PHY_RETRIES 1000 |
57 | #define ETH_JUMBO_MTU 9000 | |
58 | #define TX_WATCHDOG (5 * HZ) | |
59 | #define NAPI_WEIGHT 64 | |
6abebb53 | 60 | #define BLINK_MS 250 |
baef58b1 SH |
61 | |
62 | MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver"); | |
63 | MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); | |
64 | MODULE_LICENSE("GPL"); | |
65 | MODULE_VERSION(DRV_VERSION); | |
66 | ||
67 | static const u32 default_msg | |
68 | = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK | |
69 | | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN; | |
70 | ||
71 | static int debug = -1; /* defaults above */ | |
72 | module_param(debug, int, 0); | |
73 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
74 | ||
75 | static const struct pci_device_id skge_id_table[] = { | |
275834d1 SH |
76 | { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) }, |
77 | { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) }, | |
78 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) }, | |
79 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) }, | |
275834d1 | 80 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), }, |
2d2a3871 | 81 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */ |
275834d1 SH |
82 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) }, |
83 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */ | |
84 | { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) }, | |
275834d1 | 85 | { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) }, |
86f0cd50 | 86 | { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, }, |
baef58b1 SH |
87 | { 0 } |
88 | }; | |
89 | MODULE_DEVICE_TABLE(pci, skge_id_table); | |
90 | ||
91 | static int skge_up(struct net_device *dev); | |
92 | static int skge_down(struct net_device *dev); | |
ee294dcd | 93 | static void skge_phy_reset(struct skge_port *skge); |
513f533e | 94 | static void skge_tx_clean(struct net_device *dev); |
2cd8e5d3 SH |
95 | static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); |
96 | static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val); | |
baef58b1 SH |
97 | static void genesis_get_stats(struct skge_port *skge, u64 *data); |
98 | static void yukon_get_stats(struct skge_port *skge, u64 *data); | |
99 | static void yukon_init(struct skge_hw *hw, int port); | |
baef58b1 | 100 | static void genesis_mac_init(struct skge_hw *hw, int port); |
45bada65 | 101 | static void genesis_link_up(struct skge_port *skge); |
baef58b1 | 102 | |
7e676d91 | 103 | /* Avoid conditionals by using array */ |
baef58b1 SH |
104 | static const int txqaddr[] = { Q_XA1, Q_XA2 }; |
105 | static const int rxqaddr[] = { Q_R1, Q_R2 }; | |
106 | static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F }; | |
107 | static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F }; | |
513f533e | 108 | static const u32 irqmask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F }; |
baef58b1 | 109 | |
baef58b1 SH |
110 | static int skge_get_regs_len(struct net_device *dev) |
111 | { | |
c3f8be96 | 112 | return 0x4000; |
baef58b1 SH |
113 | } |
114 | ||
115 | /* | |
c3f8be96 SH |
116 | * Returns copy of whole control register region |
117 | * Note: skip RAM address register because accessing it will | |
118 | * cause bus hangs! | |
baef58b1 SH |
119 | */ |
120 | static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
121 | void *p) | |
122 | { | |
123 | const struct skge_port *skge = netdev_priv(dev); | |
baef58b1 | 124 | const void __iomem *io = skge->hw->regs; |
baef58b1 SH |
125 | |
126 | regs->version = 1; | |
c3f8be96 SH |
127 | memset(p, 0, regs->len); |
128 | memcpy_fromio(p, io, B3_RAM_ADDR); | |
baef58b1 | 129 | |
c3f8be96 SH |
130 | memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1, |
131 | regs->len - B3_RI_WTO_R1); | |
baef58b1 SH |
132 | } |
133 | ||
8f3f8193 | 134 | /* Wake on Lan only supported on Yukon chips with rev 1 or above */ |
baef58b1 SH |
135 | static int wol_supported(const struct skge_hw *hw) |
136 | { | |
137 | return !((hw->chip_id == CHIP_ID_GENESIS || | |
981d0377 | 138 | (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0))); |
baef58b1 SH |
139 | } |
140 | ||
141 | static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
142 | { | |
143 | struct skge_port *skge = netdev_priv(dev); | |
144 | ||
145 | wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0; | |
146 | wol->wolopts = skge->wol ? WAKE_MAGIC : 0; | |
147 | } | |
148 | ||
149 | static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | |
150 | { | |
151 | struct skge_port *skge = netdev_priv(dev); | |
152 | struct skge_hw *hw = skge->hw; | |
153 | ||
95566065 | 154 | if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0) |
baef58b1 SH |
155 | return -EOPNOTSUPP; |
156 | ||
157 | if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw)) | |
158 | return -EOPNOTSUPP; | |
159 | ||
160 | skge->wol = wol->wolopts == WAKE_MAGIC; | |
161 | ||
162 | if (skge->wol) { | |
163 | memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN); | |
164 | ||
165 | skge_write16(hw, WOL_CTRL_STAT, | |
166 | WOL_CTL_ENA_PME_ON_MAGIC_PKT | | |
167 | WOL_CTL_ENA_MAGIC_PKT_UNIT); | |
168 | } else | |
169 | skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT); | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
8f3f8193 SH |
174 | /* Determine supported/advertised modes based on hardware. |
175 | * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx | |
31b619c5 SH |
176 | */ |
177 | static u32 skge_supported_modes(const struct skge_hw *hw) | |
178 | { | |
179 | u32 supported; | |
180 | ||
5e1705dd | 181 | if (hw->copper) { |
31b619c5 SH |
182 | supported = SUPPORTED_10baseT_Half |
183 | | SUPPORTED_10baseT_Full | |
184 | | SUPPORTED_100baseT_Half | |
185 | | SUPPORTED_100baseT_Full | |
186 | | SUPPORTED_1000baseT_Half | |
187 | | SUPPORTED_1000baseT_Full | |
188 | | SUPPORTED_Autoneg| SUPPORTED_TP; | |
189 | ||
190 | if (hw->chip_id == CHIP_ID_GENESIS) | |
191 | supported &= ~(SUPPORTED_10baseT_Half | |
192 | | SUPPORTED_10baseT_Full | |
193 | | SUPPORTED_100baseT_Half | |
194 | | SUPPORTED_100baseT_Full); | |
195 | ||
196 | else if (hw->chip_id == CHIP_ID_YUKON) | |
197 | supported &= ~SUPPORTED_1000baseT_Half; | |
198 | } else | |
199 | supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | |
200 | | SUPPORTED_Autoneg; | |
201 | ||
202 | return supported; | |
203 | } | |
baef58b1 SH |
204 | |
205 | static int skge_get_settings(struct net_device *dev, | |
206 | struct ethtool_cmd *ecmd) | |
207 | { | |
208 | struct skge_port *skge = netdev_priv(dev); | |
209 | struct skge_hw *hw = skge->hw; | |
210 | ||
211 | ecmd->transceiver = XCVR_INTERNAL; | |
31b619c5 | 212 | ecmd->supported = skge_supported_modes(hw); |
baef58b1 | 213 | |
5e1705dd | 214 | if (hw->copper) { |
baef58b1 SH |
215 | ecmd->port = PORT_TP; |
216 | ecmd->phy_address = hw->phy_addr; | |
31b619c5 | 217 | } else |
baef58b1 | 218 | ecmd->port = PORT_FIBRE; |
baef58b1 SH |
219 | |
220 | ecmd->advertising = skge->advertising; | |
221 | ecmd->autoneg = skge->autoneg; | |
222 | ecmd->speed = skge->speed; | |
223 | ecmd->duplex = skge->duplex; | |
224 | return 0; | |
225 | } | |
226 | ||
baef58b1 SH |
227 | static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
228 | { | |
229 | struct skge_port *skge = netdev_priv(dev); | |
230 | const struct skge_hw *hw = skge->hw; | |
31b619c5 | 231 | u32 supported = skge_supported_modes(hw); |
baef58b1 SH |
232 | |
233 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
31b619c5 SH |
234 | ecmd->advertising = supported; |
235 | skge->duplex = -1; | |
236 | skge->speed = -1; | |
baef58b1 | 237 | } else { |
31b619c5 SH |
238 | u32 setting; |
239 | ||
2c668514 | 240 | switch (ecmd->speed) { |
baef58b1 | 241 | case SPEED_1000: |
31b619c5 SH |
242 | if (ecmd->duplex == DUPLEX_FULL) |
243 | setting = SUPPORTED_1000baseT_Full; | |
244 | else if (ecmd->duplex == DUPLEX_HALF) | |
245 | setting = SUPPORTED_1000baseT_Half; | |
246 | else | |
247 | return -EINVAL; | |
baef58b1 SH |
248 | break; |
249 | case SPEED_100: | |
31b619c5 SH |
250 | if (ecmd->duplex == DUPLEX_FULL) |
251 | setting = SUPPORTED_100baseT_Full; | |
252 | else if (ecmd->duplex == DUPLEX_HALF) | |
253 | setting = SUPPORTED_100baseT_Half; | |
254 | else | |
255 | return -EINVAL; | |
256 | break; | |
257 | ||
baef58b1 | 258 | case SPEED_10: |
31b619c5 SH |
259 | if (ecmd->duplex == DUPLEX_FULL) |
260 | setting = SUPPORTED_10baseT_Full; | |
261 | else if (ecmd->duplex == DUPLEX_HALF) | |
262 | setting = SUPPORTED_10baseT_Half; | |
263 | else | |
baef58b1 SH |
264 | return -EINVAL; |
265 | break; | |
266 | default: | |
267 | return -EINVAL; | |
268 | } | |
31b619c5 SH |
269 | |
270 | if ((setting & supported) == 0) | |
271 | return -EINVAL; | |
272 | ||
273 | skge->speed = ecmd->speed; | |
274 | skge->duplex = ecmd->duplex; | |
baef58b1 SH |
275 | } |
276 | ||
277 | skge->autoneg = ecmd->autoneg; | |
baef58b1 SH |
278 | skge->advertising = ecmd->advertising; |
279 | ||
ee294dcd SH |
280 | if (netif_running(dev)) |
281 | skge_phy_reset(skge); | |
282 | ||
baef58b1 SH |
283 | return (0); |
284 | } | |
285 | ||
286 | static void skge_get_drvinfo(struct net_device *dev, | |
287 | struct ethtool_drvinfo *info) | |
288 | { | |
289 | struct skge_port *skge = netdev_priv(dev); | |
290 | ||
291 | strcpy(info->driver, DRV_NAME); | |
292 | strcpy(info->version, DRV_VERSION); | |
293 | strcpy(info->fw_version, "N/A"); | |
294 | strcpy(info->bus_info, pci_name(skge->hw->pdev)); | |
295 | } | |
296 | ||
297 | static const struct skge_stat { | |
298 | char name[ETH_GSTRING_LEN]; | |
299 | u16 xmac_offset; | |
300 | u16 gma_offset; | |
301 | } skge_stats[] = { | |
302 | { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI }, | |
303 | { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI }, | |
304 | ||
305 | { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK }, | |
306 | { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK }, | |
307 | { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK }, | |
308 | { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK }, | |
309 | { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK }, | |
310 | { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK }, | |
311 | { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE }, | |
312 | { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE }, | |
313 | ||
314 | { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL }, | |
315 | { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL }, | |
316 | { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL }, | |
317 | { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL }, | |
318 | { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR }, | |
319 | { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV }, | |
320 | ||
321 | { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, | |
322 | { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT }, | |
323 | { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG }, | |
324 | { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR }, | |
325 | { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR }, | |
326 | }; | |
327 | ||
328 | static int skge_get_stats_count(struct net_device *dev) | |
329 | { | |
330 | return ARRAY_SIZE(skge_stats); | |
331 | } | |
332 | ||
333 | static void skge_get_ethtool_stats(struct net_device *dev, | |
334 | struct ethtool_stats *stats, u64 *data) | |
335 | { | |
336 | struct skge_port *skge = netdev_priv(dev); | |
337 | ||
338 | if (skge->hw->chip_id == CHIP_ID_GENESIS) | |
339 | genesis_get_stats(skge, data); | |
340 | else | |
341 | yukon_get_stats(skge, data); | |
342 | } | |
343 | ||
344 | /* Use hardware MIB variables for critical path statistics and | |
345 | * transmit feedback not reported at interrupt. | |
346 | * Other errors are accounted for in interrupt handler. | |
347 | */ | |
348 | static struct net_device_stats *skge_get_stats(struct net_device *dev) | |
349 | { | |
350 | struct skge_port *skge = netdev_priv(dev); | |
351 | u64 data[ARRAY_SIZE(skge_stats)]; | |
352 | ||
353 | if (skge->hw->chip_id == CHIP_ID_GENESIS) | |
354 | genesis_get_stats(skge, data); | |
355 | else | |
356 | yukon_get_stats(skge, data); | |
357 | ||
358 | skge->net_stats.tx_bytes = data[0]; | |
359 | skge->net_stats.rx_bytes = data[1]; | |
360 | skge->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
361 | skge->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
4c180fc4 | 362 | skge->net_stats.multicast = data[3] + data[5]; |
baef58b1 SH |
363 | skge->net_stats.collisions = data[10]; |
364 | skge->net_stats.tx_aborted_errors = data[12]; | |
365 | ||
366 | return &skge->net_stats; | |
367 | } | |
368 | ||
369 | static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data) | |
370 | { | |
371 | int i; | |
372 | ||
95566065 | 373 | switch (stringset) { |
baef58b1 SH |
374 | case ETH_SS_STATS: |
375 | for (i = 0; i < ARRAY_SIZE(skge_stats); i++) | |
376 | memcpy(data + i * ETH_GSTRING_LEN, | |
377 | skge_stats[i].name, ETH_GSTRING_LEN); | |
378 | break; | |
379 | } | |
380 | } | |
381 | ||
382 | static void skge_get_ring_param(struct net_device *dev, | |
383 | struct ethtool_ringparam *p) | |
384 | { | |
385 | struct skge_port *skge = netdev_priv(dev); | |
386 | ||
387 | p->rx_max_pending = MAX_RX_RING_SIZE; | |
388 | p->tx_max_pending = MAX_TX_RING_SIZE; | |
389 | p->rx_mini_max_pending = 0; | |
390 | p->rx_jumbo_max_pending = 0; | |
391 | ||
392 | p->rx_pending = skge->rx_ring.count; | |
393 | p->tx_pending = skge->tx_ring.count; | |
394 | p->rx_mini_pending = 0; | |
395 | p->rx_jumbo_pending = 0; | |
396 | } | |
397 | ||
398 | static int skge_set_ring_param(struct net_device *dev, | |
399 | struct ethtool_ringparam *p) | |
400 | { | |
401 | struct skge_port *skge = netdev_priv(dev); | |
3b8bb472 | 402 | int err; |
baef58b1 SH |
403 | |
404 | if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE || | |
9db96479 | 405 | p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE) |
baef58b1 SH |
406 | return -EINVAL; |
407 | ||
408 | skge->rx_ring.count = p->rx_pending; | |
409 | skge->tx_ring.count = p->tx_pending; | |
410 | ||
411 | if (netif_running(dev)) { | |
412 | skge_down(dev); | |
3b8bb472 SH |
413 | err = skge_up(dev); |
414 | if (err) | |
415 | dev_close(dev); | |
baef58b1 SH |
416 | } |
417 | ||
418 | return 0; | |
419 | } | |
420 | ||
421 | static u32 skge_get_msglevel(struct net_device *netdev) | |
422 | { | |
423 | struct skge_port *skge = netdev_priv(netdev); | |
424 | return skge->msg_enable; | |
425 | } | |
426 | ||
427 | static void skge_set_msglevel(struct net_device *netdev, u32 value) | |
428 | { | |
429 | struct skge_port *skge = netdev_priv(netdev); | |
430 | skge->msg_enable = value; | |
431 | } | |
432 | ||
433 | static int skge_nway_reset(struct net_device *dev) | |
434 | { | |
435 | struct skge_port *skge = netdev_priv(dev); | |
baef58b1 SH |
436 | |
437 | if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev)) | |
438 | return -EINVAL; | |
439 | ||
ee294dcd | 440 | skge_phy_reset(skge); |
baef58b1 SH |
441 | return 0; |
442 | } | |
443 | ||
444 | static int skge_set_sg(struct net_device *dev, u32 data) | |
445 | { | |
446 | struct skge_port *skge = netdev_priv(dev); | |
447 | struct skge_hw *hw = skge->hw; | |
448 | ||
449 | if (hw->chip_id == CHIP_ID_GENESIS && data) | |
450 | return -EOPNOTSUPP; | |
451 | return ethtool_op_set_sg(dev, data); | |
452 | } | |
453 | ||
454 | static int skge_set_tx_csum(struct net_device *dev, u32 data) | |
455 | { | |
456 | struct skge_port *skge = netdev_priv(dev); | |
457 | struct skge_hw *hw = skge->hw; | |
458 | ||
459 | if (hw->chip_id == CHIP_ID_GENESIS && data) | |
460 | return -EOPNOTSUPP; | |
461 | ||
462 | return ethtool_op_set_tx_csum(dev, data); | |
463 | } | |
464 | ||
465 | static u32 skge_get_rx_csum(struct net_device *dev) | |
466 | { | |
467 | struct skge_port *skge = netdev_priv(dev); | |
468 | ||
469 | return skge->rx_csum; | |
470 | } | |
471 | ||
472 | /* Only Yukon supports checksum offload. */ | |
473 | static int skge_set_rx_csum(struct net_device *dev, u32 data) | |
474 | { | |
475 | struct skge_port *skge = netdev_priv(dev); | |
476 | ||
477 | if (skge->hw->chip_id == CHIP_ID_GENESIS && data) | |
478 | return -EOPNOTSUPP; | |
479 | ||
480 | skge->rx_csum = data; | |
481 | return 0; | |
482 | } | |
483 | ||
baef58b1 SH |
484 | static void skge_get_pauseparam(struct net_device *dev, |
485 | struct ethtool_pauseparam *ecmd) | |
486 | { | |
487 | struct skge_port *skge = netdev_priv(dev); | |
488 | ||
489 | ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND) | |
490 | || (skge->flow_control == FLOW_MODE_SYMMETRIC); | |
491 | ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND) | |
492 | || (skge->flow_control == FLOW_MODE_SYMMETRIC); | |
493 | ||
494 | ecmd->autoneg = skge->autoneg; | |
495 | } | |
496 | ||
497 | static int skge_set_pauseparam(struct net_device *dev, | |
498 | struct ethtool_pauseparam *ecmd) | |
499 | { | |
500 | struct skge_port *skge = netdev_priv(dev); | |
501 | ||
502 | skge->autoneg = ecmd->autoneg; | |
503 | if (ecmd->rx_pause && ecmd->tx_pause) | |
504 | skge->flow_control = FLOW_MODE_SYMMETRIC; | |
95566065 | 505 | else if (ecmd->rx_pause && !ecmd->tx_pause) |
baef58b1 | 506 | skge->flow_control = FLOW_MODE_REM_SEND; |
95566065 | 507 | else if (!ecmd->rx_pause && ecmd->tx_pause) |
baef58b1 SH |
508 | skge->flow_control = FLOW_MODE_LOC_SEND; |
509 | else | |
510 | skge->flow_control = FLOW_MODE_NONE; | |
511 | ||
e8df8554 SH |
512 | if (netif_running(dev)) |
513 | skge_phy_reset(skge); | |
baef58b1 SH |
514 | return 0; |
515 | } | |
516 | ||
517 | /* Chip internal frequency for clock calculations */ | |
518 | static inline u32 hwkhz(const struct skge_hw *hw) | |
519 | { | |
187ff3b8 | 520 | return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125; |
baef58b1 SH |
521 | } |
522 | ||
8f3f8193 | 523 | /* Chip HZ to microseconds */ |
baef58b1 SH |
524 | static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks) |
525 | { | |
526 | return (ticks * 1000) / hwkhz(hw); | |
527 | } | |
528 | ||
8f3f8193 | 529 | /* Microseconds to chip HZ */ |
baef58b1 SH |
530 | static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec) |
531 | { | |
532 | return hwkhz(hw) * usec / 1000; | |
533 | } | |
534 | ||
535 | static int skge_get_coalesce(struct net_device *dev, | |
536 | struct ethtool_coalesce *ecmd) | |
537 | { | |
538 | struct skge_port *skge = netdev_priv(dev); | |
539 | struct skge_hw *hw = skge->hw; | |
540 | int port = skge->port; | |
541 | ||
542 | ecmd->rx_coalesce_usecs = 0; | |
543 | ecmd->tx_coalesce_usecs = 0; | |
544 | ||
545 | if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) { | |
546 | u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI)); | |
547 | u32 msk = skge_read32(hw, B2_IRQM_MSK); | |
548 | ||
549 | if (msk & rxirqmask[port]) | |
550 | ecmd->rx_coalesce_usecs = delay; | |
551 | if (msk & txirqmask[port]) | |
552 | ecmd->tx_coalesce_usecs = delay; | |
553 | } | |
554 | ||
555 | return 0; | |
556 | } | |
557 | ||
558 | /* Note: interrupt timer is per board, but can turn on/off per port */ | |
559 | static int skge_set_coalesce(struct net_device *dev, | |
560 | struct ethtool_coalesce *ecmd) | |
561 | { | |
562 | struct skge_port *skge = netdev_priv(dev); | |
563 | struct skge_hw *hw = skge->hw; | |
564 | int port = skge->port; | |
565 | u32 msk = skge_read32(hw, B2_IRQM_MSK); | |
566 | u32 delay = 25; | |
567 | ||
568 | if (ecmd->rx_coalesce_usecs == 0) | |
569 | msk &= ~rxirqmask[port]; | |
570 | else if (ecmd->rx_coalesce_usecs < 25 || | |
571 | ecmd->rx_coalesce_usecs > 33333) | |
572 | return -EINVAL; | |
573 | else { | |
574 | msk |= rxirqmask[port]; | |
575 | delay = ecmd->rx_coalesce_usecs; | |
576 | } | |
577 | ||
578 | if (ecmd->tx_coalesce_usecs == 0) | |
579 | msk &= ~txirqmask[port]; | |
580 | else if (ecmd->tx_coalesce_usecs < 25 || | |
581 | ecmd->tx_coalesce_usecs > 33333) | |
582 | return -EINVAL; | |
583 | else { | |
584 | msk |= txirqmask[port]; | |
585 | delay = min(delay, ecmd->rx_coalesce_usecs); | |
586 | } | |
587 | ||
588 | skge_write32(hw, B2_IRQM_MSK, msk); | |
589 | if (msk == 0) | |
590 | skge_write32(hw, B2_IRQM_CTRL, TIM_STOP); | |
591 | else { | |
592 | skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay)); | |
593 | skge_write32(hw, B2_IRQM_CTRL, TIM_START); | |
594 | } | |
595 | return 0; | |
596 | } | |
597 | ||
6abebb53 SH |
598 | enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST }; |
599 | static void skge_led(struct skge_port *skge, enum led_mode mode) | |
baef58b1 | 600 | { |
6abebb53 SH |
601 | struct skge_hw *hw = skge->hw; |
602 | int port = skge->port; | |
603 | ||
d85b514f | 604 | mutex_lock(&hw->phy_mutex); |
baef58b1 | 605 | if (hw->chip_id == CHIP_ID_GENESIS) { |
6abebb53 SH |
606 | switch (mode) { |
607 | case LED_MODE_OFF: | |
608 | xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF); | |
609 | skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); | |
610 | skge_write32(hw, SK_REG(port, RX_LED_VAL), 0); | |
611 | skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF); | |
612 | break; | |
baef58b1 | 613 | |
6abebb53 SH |
614 | case LED_MODE_ON: |
615 | skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON); | |
616 | skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON); | |
baef58b1 | 617 | |
6abebb53 SH |
618 | skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); |
619 | skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START); | |
baef58b1 | 620 | |
6abebb53 | 621 | break; |
baef58b1 | 622 | |
6abebb53 SH |
623 | case LED_MODE_TST: |
624 | skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON); | |
625 | skge_write32(hw, SK_REG(port, RX_LED_VAL), 100); | |
626 | skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START); | |
baef58b1 | 627 | |
6abebb53 SH |
628 | xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON); |
629 | break; | |
630 | } | |
baef58b1 | 631 | } else { |
6abebb53 SH |
632 | switch (mode) { |
633 | case LED_MODE_OFF: | |
634 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
635 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, | |
636 | PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
637 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
638 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
639 | PHY_M_LED_MO_1000(MO_LED_OFF) | | |
640 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
641 | break; | |
642 | case LED_MODE_ON: | |
643 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, | |
644 | PHY_M_LED_PULS_DUR(PULS_170MS) | | |
645 | PHY_M_LED_BLINK_RT(BLINK_84MS) | | |
646 | PHY_M_LEDC_TX_CTRL | | |
647 | PHY_M_LEDC_DP_CTRL); | |
46a60f2d | 648 | |
6abebb53 SH |
649 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
650 | PHY_M_LED_MO_RX(MO_LED_OFF) | | |
651 | (skge->speed == SPEED_100 ? | |
652 | PHY_M_LED_MO_100(MO_LED_ON) : 0)); | |
653 | break; | |
654 | case LED_MODE_TST: | |
655 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
656 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, | |
657 | PHY_M_LED_MO_DUP(MO_LED_ON) | | |
658 | PHY_M_LED_MO_10(MO_LED_ON) | | |
659 | PHY_M_LED_MO_100(MO_LED_ON) | | |
660 | PHY_M_LED_MO_1000(MO_LED_ON) | | |
661 | PHY_M_LED_MO_RX(MO_LED_ON)); | |
662 | } | |
baef58b1 | 663 | } |
d85b514f | 664 | mutex_unlock(&hw->phy_mutex); |
baef58b1 SH |
665 | } |
666 | ||
667 | /* blink LED's for finding board */ | |
668 | static int skge_phys_id(struct net_device *dev, u32 data) | |
669 | { | |
670 | struct skge_port *skge = netdev_priv(dev); | |
6abebb53 SH |
671 | unsigned long ms; |
672 | enum led_mode mode = LED_MODE_TST; | |
baef58b1 | 673 | |
95566065 | 674 | if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)) |
6abebb53 SH |
675 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000; |
676 | else | |
677 | ms = data * 1000; | |
baef58b1 | 678 | |
6abebb53 SH |
679 | while (ms > 0) { |
680 | skge_led(skge, mode); | |
681 | mode ^= LED_MODE_TST; | |
baef58b1 | 682 | |
6abebb53 SH |
683 | if (msleep_interruptible(BLINK_MS)) |
684 | break; | |
685 | ms -= BLINK_MS; | |
686 | } | |
baef58b1 | 687 | |
6abebb53 SH |
688 | /* back to regular LED state */ |
689 | skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF); | |
baef58b1 SH |
690 | |
691 | return 0; | |
692 | } | |
693 | ||
694 | static struct ethtool_ops skge_ethtool_ops = { | |
695 | .get_settings = skge_get_settings, | |
696 | .set_settings = skge_set_settings, | |
697 | .get_drvinfo = skge_get_drvinfo, | |
698 | .get_regs_len = skge_get_regs_len, | |
699 | .get_regs = skge_get_regs, | |
700 | .get_wol = skge_get_wol, | |
701 | .set_wol = skge_set_wol, | |
702 | .get_msglevel = skge_get_msglevel, | |
703 | .set_msglevel = skge_set_msglevel, | |
704 | .nway_reset = skge_nway_reset, | |
705 | .get_link = ethtool_op_get_link, | |
706 | .get_ringparam = skge_get_ring_param, | |
707 | .set_ringparam = skge_set_ring_param, | |
708 | .get_pauseparam = skge_get_pauseparam, | |
709 | .set_pauseparam = skge_set_pauseparam, | |
710 | .get_coalesce = skge_get_coalesce, | |
711 | .set_coalesce = skge_set_coalesce, | |
baef58b1 SH |
712 | .get_sg = ethtool_op_get_sg, |
713 | .set_sg = skge_set_sg, | |
714 | .get_tx_csum = ethtool_op_get_tx_csum, | |
715 | .set_tx_csum = skge_set_tx_csum, | |
716 | .get_rx_csum = skge_get_rx_csum, | |
717 | .set_rx_csum = skge_set_rx_csum, | |
718 | .get_strings = skge_get_strings, | |
719 | .phys_id = skge_phys_id, | |
720 | .get_stats_count = skge_get_stats_count, | |
721 | .get_ethtool_stats = skge_get_ethtool_stats, | |
56230d53 | 722 | .get_perm_addr = ethtool_op_get_perm_addr, |
baef58b1 SH |
723 | }; |
724 | ||
725 | /* | |
726 | * Allocate ring elements and chain them together | |
727 | * One-to-one association of board descriptors with ring elements | |
728 | */ | |
c3da1447 | 729 | static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base) |
baef58b1 SH |
730 | { |
731 | struct skge_tx_desc *d; | |
732 | struct skge_element *e; | |
733 | int i; | |
734 | ||
ff7907ae | 735 | ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL); |
baef58b1 SH |
736 | if (!ring->start) |
737 | return -ENOMEM; | |
738 | ||
739 | for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) { | |
740 | e->desc = d; | |
741 | if (i == ring->count - 1) { | |
742 | e->next = ring->start; | |
743 | d->next_offset = base; | |
744 | } else { | |
745 | e->next = e + 1; | |
746 | d->next_offset = base + (i+1) * sizeof(*d); | |
747 | } | |
748 | } | |
749 | ring->to_use = ring->to_clean = ring->start; | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
19a33d4e SH |
754 | /* Allocate and setup a new buffer for receiving */ |
755 | static void skge_rx_setup(struct skge_port *skge, struct skge_element *e, | |
756 | struct sk_buff *skb, unsigned int bufsize) | |
757 | { | |
758 | struct skge_rx_desc *rd = e->desc; | |
759 | u64 map; | |
baef58b1 SH |
760 | |
761 | map = pci_map_single(skge->hw->pdev, skb->data, bufsize, | |
762 | PCI_DMA_FROMDEVICE); | |
763 | ||
764 | rd->dma_lo = map; | |
765 | rd->dma_hi = map >> 32; | |
766 | e->skb = skb; | |
767 | rd->csum1_start = ETH_HLEN; | |
768 | rd->csum2_start = ETH_HLEN; | |
769 | rd->csum1 = 0; | |
770 | rd->csum2 = 0; | |
771 | ||
772 | wmb(); | |
773 | ||
774 | rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize; | |
775 | pci_unmap_addr_set(e, mapaddr, map); | |
776 | pci_unmap_len_set(e, maplen, bufsize); | |
baef58b1 SH |
777 | } |
778 | ||
19a33d4e SH |
779 | /* Resume receiving using existing skb, |
780 | * Note: DMA address is not changed by chip. | |
781 | * MTU not changed while receiver active. | |
782 | */ | |
5a011447 | 783 | static inline void skge_rx_reuse(struct skge_element *e, unsigned int size) |
19a33d4e SH |
784 | { |
785 | struct skge_rx_desc *rd = e->desc; | |
786 | ||
787 | rd->csum2 = 0; | |
788 | rd->csum2_start = ETH_HLEN; | |
789 | ||
790 | wmb(); | |
791 | ||
792 | rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size; | |
793 | } | |
794 | ||
795 | ||
796 | /* Free all buffers in receive ring, assumes receiver stopped */ | |
baef58b1 SH |
797 | static void skge_rx_clean(struct skge_port *skge) |
798 | { | |
799 | struct skge_hw *hw = skge->hw; | |
800 | struct skge_ring *ring = &skge->rx_ring; | |
801 | struct skge_element *e; | |
802 | ||
19a33d4e SH |
803 | e = ring->start; |
804 | do { | |
baef58b1 SH |
805 | struct skge_rx_desc *rd = e->desc; |
806 | rd->control = 0; | |
19a33d4e SH |
807 | if (e->skb) { |
808 | pci_unmap_single(hw->pdev, | |
809 | pci_unmap_addr(e, mapaddr), | |
810 | pci_unmap_len(e, maplen), | |
811 | PCI_DMA_FROMDEVICE); | |
812 | dev_kfree_skb(e->skb); | |
813 | e->skb = NULL; | |
814 | } | |
815 | } while ((e = e->next) != ring->start); | |
baef58b1 SH |
816 | } |
817 | ||
19a33d4e | 818 | |
baef58b1 | 819 | /* Allocate buffers for receive ring |
19a33d4e | 820 | * For receive: to_clean is next received frame. |
baef58b1 | 821 | */ |
c54f9765 | 822 | static int skge_rx_fill(struct net_device *dev) |
baef58b1 | 823 | { |
c54f9765 | 824 | struct skge_port *skge = netdev_priv(dev); |
baef58b1 SH |
825 | struct skge_ring *ring = &skge->rx_ring; |
826 | struct skge_element *e; | |
baef58b1 | 827 | |
19a33d4e SH |
828 | e = ring->start; |
829 | do { | |
383181ac | 830 | struct sk_buff *skb; |
baef58b1 | 831 | |
c54f9765 SH |
832 | skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN, |
833 | GFP_KERNEL); | |
19a33d4e SH |
834 | if (!skb) |
835 | return -ENOMEM; | |
836 | ||
383181ac SH |
837 | skb_reserve(skb, NET_IP_ALIGN); |
838 | skge_rx_setup(skge, e, skb, skge->rx_buf_size); | |
19a33d4e | 839 | } while ( (e = e->next) != ring->start); |
baef58b1 | 840 | |
19a33d4e SH |
841 | ring->to_clean = ring->start; |
842 | return 0; | |
baef58b1 SH |
843 | } |
844 | ||
845 | static void skge_link_up(struct skge_port *skge) | |
846 | { | |
46a60f2d | 847 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), |
54cfb5aa SH |
848 | LED_BLK_OFF|LED_SYNC_OFF|LED_ON); |
849 | ||
baef58b1 | 850 | netif_carrier_on(skge->netdev); |
29b4e886 | 851 | netif_wake_queue(skge->netdev); |
baef58b1 SH |
852 | |
853 | if (netif_msg_link(skge)) | |
854 | printk(KERN_INFO PFX | |
855 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", | |
856 | skge->netdev->name, skge->speed, | |
857 | skge->duplex == DUPLEX_FULL ? "full" : "half", | |
858 | (skge->flow_control == FLOW_MODE_NONE) ? "none" : | |
859 | (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" : | |
860 | (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" : | |
861 | (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" : | |
862 | "unknown"); | |
863 | } | |
864 | ||
865 | static void skge_link_down(struct skge_port *skge) | |
866 | { | |
54cfb5aa | 867 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); |
baef58b1 SH |
868 | netif_carrier_off(skge->netdev); |
869 | netif_stop_queue(skge->netdev); | |
870 | ||
871 | if (netif_msg_link(skge)) | |
872 | printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name); | |
873 | } | |
874 | ||
2cd8e5d3 | 875 | static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) |
baef58b1 SH |
876 | { |
877 | int i; | |
baef58b1 | 878 | |
6b0c1480 | 879 | xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); |
0781191c | 880 | *val = xm_read16(hw, port, XM_PHY_DATA); |
baef58b1 | 881 | |
89bf5f23 | 882 | for (i = 0; i < PHY_RETRIES; i++) { |
2cd8e5d3 | 883 | if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY) |
89bf5f23 | 884 | goto ready; |
0781191c | 885 | udelay(1); |
baef58b1 SH |
886 | } |
887 | ||
2cd8e5d3 | 888 | return -ETIMEDOUT; |
89bf5f23 | 889 | ready: |
2cd8e5d3 | 890 | *val = xm_read16(hw, port, XM_PHY_DATA); |
89bf5f23 | 891 | |
2cd8e5d3 SH |
892 | return 0; |
893 | } | |
894 | ||
895 | static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg) | |
896 | { | |
897 | u16 v = 0; | |
898 | if (__xm_phy_read(hw, port, reg, &v)) | |
899 | printk(KERN_WARNING PFX "%s: phy read timed out\n", | |
900 | hw->dev[port]->name); | |
baef58b1 SH |
901 | return v; |
902 | } | |
903 | ||
2cd8e5d3 | 904 | static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) |
baef58b1 SH |
905 | { |
906 | int i; | |
907 | ||
6b0c1480 | 908 | xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr); |
baef58b1 | 909 | for (i = 0; i < PHY_RETRIES; i++) { |
6b0c1480 | 910 | if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) |
baef58b1 | 911 | goto ready; |
89bf5f23 | 912 | udelay(1); |
baef58b1 | 913 | } |
2cd8e5d3 | 914 | return -EIO; |
baef58b1 SH |
915 | |
916 | ready: | |
6b0c1480 | 917 | xm_write16(hw, port, XM_PHY_DATA, val); |
0781191c SH |
918 | for (i = 0; i < PHY_RETRIES; i++) { |
919 | if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY)) | |
920 | return 0; | |
921 | udelay(1); | |
922 | } | |
923 | return -ETIMEDOUT; | |
baef58b1 SH |
924 | } |
925 | ||
926 | static void genesis_init(struct skge_hw *hw) | |
927 | { | |
928 | /* set blink source counter */ | |
929 | skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100); | |
930 | skge_write8(hw, B2_BSC_CTRL, BSC_START); | |
931 | ||
932 | /* configure mac arbiter */ | |
933 | skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); | |
934 | ||
935 | /* configure mac arbiter timeout values */ | |
936 | skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53); | |
937 | skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53); | |
938 | skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53); | |
939 | skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53); | |
940 | ||
941 | skge_write8(hw, B3_MA_RCINI_RX1, 0); | |
942 | skge_write8(hw, B3_MA_RCINI_RX2, 0); | |
943 | skge_write8(hw, B3_MA_RCINI_TX1, 0); | |
944 | skge_write8(hw, B3_MA_RCINI_TX2, 0); | |
945 | ||
946 | /* configure packet arbiter timeout */ | |
947 | skge_write16(hw, B3_PA_CTRL, PA_RST_CLR); | |
948 | skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX); | |
949 | skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX); | |
950 | skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX); | |
951 | skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX); | |
952 | } | |
953 | ||
954 | static void genesis_reset(struct skge_hw *hw, int port) | |
955 | { | |
45bada65 | 956 | const u8 zero[8] = { 0 }; |
baef58b1 | 957 | |
46a60f2d SH |
958 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); |
959 | ||
baef58b1 | 960 | /* reset the statistics module */ |
6b0c1480 SH |
961 | xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT); |
962 | xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */ | |
963 | xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */ | |
964 | xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */ | |
965 | xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */ | |
baef58b1 | 966 | |
89bf5f23 SH |
967 | /* disable Broadcom PHY IRQ */ |
968 | xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff); | |
baef58b1 | 969 | |
45bada65 | 970 | xm_outhash(hw, port, XM_HSM, zero); |
baef58b1 SH |
971 | } |
972 | ||
973 | ||
45bada65 SH |
974 | /* Convert mode to MII values */ |
975 | static const u16 phy_pause_map[] = { | |
976 | [FLOW_MODE_NONE] = 0, | |
977 | [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM, | |
978 | [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP, | |
979 | [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM, | |
980 | }; | |
981 | ||
982 | ||
983 | /* Check status of Broadcom phy link */ | |
984 | static void bcom_check_link(struct skge_hw *hw, int port) | |
baef58b1 | 985 | { |
45bada65 SH |
986 | struct net_device *dev = hw->dev[port]; |
987 | struct skge_port *skge = netdev_priv(dev); | |
988 | u16 status; | |
989 | ||
990 | /* read twice because of latch */ | |
991 | (void) xm_phy_read(hw, port, PHY_BCOM_STAT); | |
992 | status = xm_phy_read(hw, port, PHY_BCOM_STAT); | |
993 | ||
45bada65 SH |
994 | if ((status & PHY_ST_LSYNC) == 0) { |
995 | u16 cmd = xm_read16(hw, port, XM_MMU_CMD); | |
996 | cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX); | |
997 | xm_write16(hw, port, XM_MMU_CMD, cmd); | |
998 | /* dummy read to ensure writing */ | |
999 | (void) xm_read16(hw, port, XM_MMU_CMD); | |
1000 | ||
1001 | if (netif_carrier_ok(dev)) | |
1002 | skge_link_down(skge); | |
1003 | } else { | |
1004 | if (skge->autoneg == AUTONEG_ENABLE && | |
1005 | (status & PHY_ST_AN_OVER)) { | |
1006 | u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP); | |
1007 | u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT); | |
1008 | ||
1009 | if (lpa & PHY_B_AN_RF) { | |
1010 | printk(KERN_NOTICE PFX "%s: remote fault\n", | |
1011 | dev->name); | |
1012 | return; | |
1013 | } | |
1014 | ||
1015 | /* Check Duplex mismatch */ | |
2c668514 | 1016 | switch (aux & PHY_B_AS_AN_RES_MSK) { |
45bada65 SH |
1017 | case PHY_B_RES_1000FD: |
1018 | skge->duplex = DUPLEX_FULL; | |
1019 | break; | |
1020 | case PHY_B_RES_1000HD: | |
1021 | skge->duplex = DUPLEX_HALF; | |
1022 | break; | |
1023 | default: | |
1024 | printk(KERN_NOTICE PFX "%s: duplex mismatch\n", | |
1025 | dev->name); | |
1026 | return; | |
1027 | } | |
1028 | ||
1029 | ||
1030 | /* We are using IEEE 802.3z/D5.0 Table 37-4 */ | |
1031 | switch (aux & PHY_B_AS_PAUSE_MSK) { | |
1032 | case PHY_B_AS_PAUSE_MSK: | |
1033 | skge->flow_control = FLOW_MODE_SYMMETRIC; | |
1034 | break; | |
1035 | case PHY_B_AS_PRR: | |
1036 | skge->flow_control = FLOW_MODE_REM_SEND; | |
1037 | break; | |
1038 | case PHY_B_AS_PRT: | |
1039 | skge->flow_control = FLOW_MODE_LOC_SEND; | |
1040 | break; | |
1041 | default: | |
1042 | skge->flow_control = FLOW_MODE_NONE; | |
1043 | } | |
1044 | ||
1045 | skge->speed = SPEED_1000; | |
1046 | } | |
1047 | ||
1048 | if (!netif_carrier_ok(dev)) | |
1049 | genesis_link_up(skge); | |
1050 | } | |
1051 | } | |
1052 | ||
1053 | /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional | |
1054 | * Phy on for 100 or 10Mbit operation | |
1055 | */ | |
1056 | static void bcom_phy_init(struct skge_port *skge, int jumbo) | |
1057 | { | |
1058 | struct skge_hw *hw = skge->hw; | |
1059 | int port = skge->port; | |
baef58b1 | 1060 | int i; |
45bada65 | 1061 | u16 id1, r, ext, ctl; |
baef58b1 SH |
1062 | |
1063 | /* magic workaround patterns for Broadcom */ | |
1064 | static const struct { | |
1065 | u16 reg; | |
1066 | u16 val; | |
1067 | } A1hack[] = { | |
1068 | { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 }, | |
1069 | { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 }, | |
1070 | { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 }, | |
1071 | { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 }, | |
1072 | }, C0hack[] = { | |
1073 | { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 }, | |
1074 | { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 }, | |
1075 | }; | |
1076 | ||
45bada65 SH |
1077 | /* read Id from external PHY (all have the same address) */ |
1078 | id1 = xm_phy_read(hw, port, PHY_XMAC_ID1); | |
1079 | ||
1080 | /* Optimize MDIO transfer by suppressing preamble. */ | |
1081 | r = xm_read16(hw, port, XM_MMU_CMD); | |
1082 | r |= XM_MMU_NO_PRE; | |
1083 | xm_write16(hw, port, XM_MMU_CMD,r); | |
1084 | ||
2c668514 | 1085 | switch (id1) { |
45bada65 SH |
1086 | case PHY_BCOM_ID1_C0: |
1087 | /* | |
1088 | * Workaround BCOM Errata for the C0 type. | |
1089 | * Write magic patterns to reserved registers. | |
1090 | */ | |
1091 | for (i = 0; i < ARRAY_SIZE(C0hack); i++) | |
1092 | xm_phy_write(hw, port, | |
1093 | C0hack[i].reg, C0hack[i].val); | |
1094 | ||
1095 | break; | |
1096 | case PHY_BCOM_ID1_A1: | |
1097 | /* | |
1098 | * Workaround BCOM Errata for the A1 type. | |
1099 | * Write magic patterns to reserved registers. | |
1100 | */ | |
1101 | for (i = 0; i < ARRAY_SIZE(A1hack); i++) | |
1102 | xm_phy_write(hw, port, | |
1103 | A1hack[i].reg, A1hack[i].val); | |
1104 | break; | |
1105 | } | |
1106 | ||
1107 | /* | |
1108 | * Workaround BCOM Errata (#10523) for all BCom PHYs. | |
1109 | * Disable Power Management after reset. | |
1110 | */ | |
1111 | r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL); | |
1112 | r |= PHY_B_AC_DIS_PM; | |
1113 | xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r); | |
1114 | ||
1115 | /* Dummy read */ | |
1116 | xm_read16(hw, port, XM_ISRC); | |
1117 | ||
1118 | ext = PHY_B_PEC_EN_LTR; /* enable tx led */ | |
1119 | ctl = PHY_CT_SP1000; /* always 1000mbit */ | |
1120 | ||
1121 | if (skge->autoneg == AUTONEG_ENABLE) { | |
1122 | /* | |
1123 | * Workaround BCOM Errata #1 for the C5 type. | |
1124 | * 1000Base-T Link Acquisition Failure in Slave Mode | |
1125 | * Set Repeater/DTE bit 10 of the 1000Base-T Control Register | |
1126 | */ | |
1127 | u16 adv = PHY_B_1000C_RD; | |
1128 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1129 | adv |= PHY_B_1000C_AHD; | |
1130 | if (skge->advertising & ADVERTISED_1000baseT_Full) | |
1131 | adv |= PHY_B_1000C_AFD; | |
1132 | xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv); | |
1133 | ||
1134 | ctl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
1135 | } else { | |
1136 | if (skge->duplex == DUPLEX_FULL) | |
1137 | ctl |= PHY_CT_DUP_MD; | |
1138 | /* Force to slave */ | |
1139 | xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE); | |
1140 | } | |
1141 | ||
1142 | /* Set autonegotiation pause parameters */ | |
1143 | xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV, | |
1144 | phy_pause_map[skge->flow_control] | PHY_AN_CSMA); | |
1145 | ||
1146 | /* Handle Jumbo frames */ | |
1147 | if (jumbo) { | |
1148 | xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, | |
1149 | PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK); | |
1150 | ||
1151 | ext |= PHY_B_PEC_HIGH_LA; | |
1152 | ||
1153 | } | |
1154 | ||
1155 | xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext); | |
1156 | xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl); | |
1157 | ||
8f3f8193 | 1158 | /* Use link status change interrupt */ |
45bada65 SH |
1159 | xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); |
1160 | ||
1161 | bcom_check_link(hw, port); | |
1162 | } | |
1163 | ||
1164 | static void genesis_mac_init(struct skge_hw *hw, int port) | |
1165 | { | |
1166 | struct net_device *dev = hw->dev[port]; | |
1167 | struct skge_port *skge = netdev_priv(dev); | |
1168 | int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN; | |
1169 | int i; | |
1170 | u32 r; | |
1171 | const u8 zero[6] = { 0 }; | |
1172 | ||
0781191c SH |
1173 | for (i = 0; i < 10; i++) { |
1174 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), | |
1175 | MFF_SET_MAC_RST); | |
1176 | if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST) | |
1177 | goto reset_ok; | |
1178 | udelay(1); | |
1179 | } | |
baef58b1 | 1180 | |
0781191c SH |
1181 | printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name); |
1182 | ||
1183 | reset_ok: | |
baef58b1 | 1184 | /* Unreset the XMAC. */ |
6b0c1480 | 1185 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST); |
baef58b1 SH |
1186 | |
1187 | /* | |
1188 | * Perform additional initialization for external PHYs, | |
1189 | * namely for the 1000baseTX cards that use the XMAC's | |
1190 | * GMII mode. | |
1191 | */ | |
45bada65 | 1192 | /* Take external Phy out of reset */ |
89bf5f23 SH |
1193 | r = skge_read32(hw, B2_GP_IO); |
1194 | if (port == 0) | |
1195 | r |= GP_DIR_0|GP_IO_0; | |
1196 | else | |
1197 | r |= GP_DIR_2|GP_IO_2; | |
1198 | ||
1199 | skge_write32(hw, B2_GP_IO, r); | |
0781191c | 1200 | |
89bf5f23 | 1201 | |
8f3f8193 | 1202 | /* Enable GMII interface */ |
89bf5f23 SH |
1203 | xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD); |
1204 | ||
45bada65 | 1205 | bcom_phy_init(skge, jumbo); |
89bf5f23 | 1206 | |
45bada65 SH |
1207 | /* Set Station Address */ |
1208 | xm_outaddr(hw, port, XM_SA, dev->dev_addr); | |
89bf5f23 | 1209 | |
45bada65 SH |
1210 | /* We don't use match addresses so clear */ |
1211 | for (i = 1; i < 16; i++) | |
1212 | xm_outaddr(hw, port, XM_EXM(i), zero); | |
1213 | ||
0781191c SH |
1214 | /* Clear MIB counters */ |
1215 | xm_write16(hw, port, XM_STAT_CMD, | |
1216 | XM_SC_CLR_RXC | XM_SC_CLR_TXC); | |
1217 | /* Clear two times according to Errata #3 */ | |
1218 | xm_write16(hw, port, XM_STAT_CMD, | |
1219 | XM_SC_CLR_RXC | XM_SC_CLR_TXC); | |
1220 | ||
45bada65 SH |
1221 | /* configure Rx High Water Mark (XM_RX_HI_WM) */ |
1222 | xm_write16(hw, port, XM_RX_HI_WM, 1450); | |
1223 | ||
1224 | /* We don't need the FCS appended to the packet. */ | |
1225 | r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS; | |
1226 | if (jumbo) | |
1227 | r |= XM_RX_BIG_PK_OK; | |
89bf5f23 | 1228 | |
45bada65 | 1229 | if (skge->duplex == DUPLEX_HALF) { |
89bf5f23 | 1230 | /* |
45bada65 SH |
1231 | * If in manual half duplex mode the other side might be in |
1232 | * full duplex mode, so ignore if a carrier extension is not seen | |
1233 | * on frames received | |
89bf5f23 | 1234 | */ |
45bada65 | 1235 | r |= XM_RX_DIS_CEXT; |
baef58b1 | 1236 | } |
45bada65 | 1237 | xm_write16(hw, port, XM_RX_CMD, r); |
baef58b1 | 1238 | |
baef58b1 SH |
1239 | |
1240 | /* We want short frames padded to 60 bytes. */ | |
45bada65 SH |
1241 | xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD); |
1242 | ||
1243 | /* | |
1244 | * Bump up the transmit threshold. This helps hold off transmit | |
1245 | * underruns when we're blasting traffic from both ports at once. | |
1246 | */ | |
1247 | xm_write16(hw, port, XM_TX_THR, 512); | |
baef58b1 SH |
1248 | |
1249 | /* | |
1250 | * Enable the reception of all error frames. This is is | |
1251 | * a necessary evil due to the design of the XMAC. The | |
1252 | * XMAC's receive FIFO is only 8K in size, however jumbo | |
1253 | * frames can be up to 9000 bytes in length. When bad | |
1254 | * frame filtering is enabled, the XMAC's RX FIFO operates | |
1255 | * in 'store and forward' mode. For this to work, the | |
1256 | * entire frame has to fit into the FIFO, but that means | |
1257 | * that jumbo frames larger than 8192 bytes will be | |
1258 | * truncated. Disabling all bad frame filtering causes | |
1259 | * the RX FIFO to operate in streaming mode, in which | |
8f3f8193 | 1260 | * case the XMAC will start transferring frames out of the |
baef58b1 SH |
1261 | * RX FIFO as soon as the FIFO threshold is reached. |
1262 | */ | |
45bada65 | 1263 | xm_write32(hw, port, XM_MODE, XM_DEF_MODE); |
baef58b1 | 1264 | |
baef58b1 SH |
1265 | |
1266 | /* | |
45bada65 SH |
1267 | * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK) |
1268 | * - Enable all bits excepting 'Octets Rx OK Low CntOv' | |
1269 | * and 'Octets Rx OK Hi Cnt Ov'. | |
baef58b1 | 1270 | */ |
45bada65 SH |
1271 | xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK); |
1272 | ||
1273 | /* | |
1274 | * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK) | |
1275 | * - Enable all bits excepting 'Octets Tx OK Low CntOv' | |
1276 | * and 'Octets Tx OK Hi Cnt Ov'. | |
1277 | */ | |
1278 | xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK); | |
baef58b1 SH |
1279 | |
1280 | /* Configure MAC arbiter */ | |
1281 | skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR); | |
1282 | ||
1283 | /* configure timeout values */ | |
1284 | skge_write8(hw, B3_MA_TOINI_RX1, 72); | |
1285 | skge_write8(hw, B3_MA_TOINI_RX2, 72); | |
1286 | skge_write8(hw, B3_MA_TOINI_TX1, 72); | |
1287 | skge_write8(hw, B3_MA_TOINI_TX2, 72); | |
1288 | ||
1289 | skge_write8(hw, B3_MA_RCINI_RX1, 0); | |
1290 | skge_write8(hw, B3_MA_RCINI_RX2, 0); | |
1291 | skge_write8(hw, B3_MA_RCINI_TX1, 0); | |
1292 | skge_write8(hw, B3_MA_RCINI_TX2, 0); | |
1293 | ||
1294 | /* Configure Rx MAC FIFO */ | |
6b0c1480 SH |
1295 | skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR); |
1296 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT); | |
1297 | skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD); | |
baef58b1 SH |
1298 | |
1299 | /* Configure Tx MAC FIFO */ | |
6b0c1480 SH |
1300 | skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR); |
1301 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF); | |
1302 | skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD); | |
baef58b1 | 1303 | |
45bada65 | 1304 | if (jumbo) { |
baef58b1 | 1305 | /* Enable frame flushing if jumbo frames used */ |
6b0c1480 | 1306 | skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH); |
baef58b1 SH |
1307 | } else { |
1308 | /* enable timeout timers if normal frames */ | |
1309 | skge_write16(hw, B3_PA_CTRL, | |
45bada65 | 1310 | (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2); |
baef58b1 | 1311 | } |
baef58b1 SH |
1312 | } |
1313 | ||
1314 | static void genesis_stop(struct skge_port *skge) | |
1315 | { | |
1316 | struct skge_hw *hw = skge->hw; | |
1317 | int port = skge->port; | |
89bf5f23 | 1318 | u32 reg; |
baef58b1 | 1319 | |
46a60f2d SH |
1320 | genesis_reset(hw, port); |
1321 | ||
baef58b1 SH |
1322 | /* Clear Tx packet arbiter timeout IRQ */ |
1323 | skge_write16(hw, B3_PA_CTRL, | |
1324 | port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2); | |
1325 | ||
1326 | /* | |
8f3f8193 | 1327 | * If the transfer sticks at the MAC the STOP command will not |
baef58b1 SH |
1328 | * terminate if we don't flush the XMAC's transmit FIFO ! |
1329 | */ | |
6b0c1480 SH |
1330 | xm_write32(hw, port, XM_MODE, |
1331 | xm_read32(hw, port, XM_MODE)|XM_MD_FTF); | |
baef58b1 SH |
1332 | |
1333 | ||
1334 | /* Reset the MAC */ | |
6b0c1480 | 1335 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST); |
baef58b1 SH |
1336 | |
1337 | /* For external PHYs there must be special handling */ | |
89bf5f23 SH |
1338 | reg = skge_read32(hw, B2_GP_IO); |
1339 | if (port == 0) { | |
1340 | reg |= GP_DIR_0; | |
1341 | reg &= ~GP_IO_0; | |
1342 | } else { | |
1343 | reg |= GP_DIR_2; | |
1344 | reg &= ~GP_IO_2; | |
baef58b1 | 1345 | } |
89bf5f23 SH |
1346 | skge_write32(hw, B2_GP_IO, reg); |
1347 | skge_read32(hw, B2_GP_IO); | |
baef58b1 | 1348 | |
6b0c1480 SH |
1349 | xm_write16(hw, port, XM_MMU_CMD, |
1350 | xm_read16(hw, port, XM_MMU_CMD) | |
baef58b1 SH |
1351 | & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX)); |
1352 | ||
6b0c1480 | 1353 | xm_read16(hw, port, XM_MMU_CMD); |
baef58b1 SH |
1354 | } |
1355 | ||
1356 | ||
1357 | static void genesis_get_stats(struct skge_port *skge, u64 *data) | |
1358 | { | |
1359 | struct skge_hw *hw = skge->hw; | |
1360 | int port = skge->port; | |
1361 | int i; | |
1362 | unsigned long timeout = jiffies + HZ; | |
1363 | ||
6b0c1480 | 1364 | xm_write16(hw, port, |
baef58b1 SH |
1365 | XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC); |
1366 | ||
1367 | /* wait for update to complete */ | |
6b0c1480 | 1368 | while (xm_read16(hw, port, XM_STAT_CMD) |
baef58b1 SH |
1369 | & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) { |
1370 | if (time_after(jiffies, timeout)) | |
1371 | break; | |
1372 | udelay(10); | |
1373 | } | |
1374 | ||
1375 | /* special case for 64 bit octet counter */ | |
6b0c1480 SH |
1376 | data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32 |
1377 | | xm_read32(hw, port, XM_TXO_OK_LO); | |
1378 | data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32 | |
1379 | | xm_read32(hw, port, XM_RXO_OK_LO); | |
baef58b1 SH |
1380 | |
1381 | for (i = 2; i < ARRAY_SIZE(skge_stats); i++) | |
6b0c1480 | 1382 | data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset); |
baef58b1 SH |
1383 | } |
1384 | ||
1385 | static void genesis_mac_intr(struct skge_hw *hw, int port) | |
1386 | { | |
1387 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
6b0c1480 | 1388 | u16 status = xm_read16(hw, port, XM_ISRC); |
baef58b1 | 1389 | |
7e676d91 SH |
1390 | if (netif_msg_intr(skge)) |
1391 | printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n", | |
1392 | skge->netdev->name, status); | |
baef58b1 SH |
1393 | |
1394 | if (status & XM_IS_TXF_UR) { | |
6b0c1480 | 1395 | xm_write32(hw, port, XM_MODE, XM_MD_FTF); |
baef58b1 SH |
1396 | ++skge->net_stats.tx_fifo_errors; |
1397 | } | |
1398 | if (status & XM_IS_RXF_OV) { | |
6b0c1480 | 1399 | xm_write32(hw, port, XM_MODE, XM_MD_FRF); |
baef58b1 SH |
1400 | ++skge->net_stats.rx_fifo_errors; |
1401 | } | |
1402 | } | |
1403 | ||
baef58b1 SH |
1404 | static void genesis_link_up(struct skge_port *skge) |
1405 | { | |
1406 | struct skge_hw *hw = skge->hw; | |
1407 | int port = skge->port; | |
1408 | u16 cmd; | |
1409 | u32 mode, msk; | |
1410 | ||
6b0c1480 | 1411 | cmd = xm_read16(hw, port, XM_MMU_CMD); |
baef58b1 SH |
1412 | |
1413 | /* | |
1414 | * enabling pause frame reception is required for 1000BT | |
1415 | * because the XMAC is not reset if the link is going down | |
1416 | */ | |
1417 | if (skge->flow_control == FLOW_MODE_NONE || | |
1418 | skge->flow_control == FLOW_MODE_LOC_SEND) | |
7e676d91 | 1419 | /* Disable Pause Frame Reception */ |
baef58b1 SH |
1420 | cmd |= XM_MMU_IGN_PF; |
1421 | else | |
1422 | /* Enable Pause Frame Reception */ | |
1423 | cmd &= ~XM_MMU_IGN_PF; | |
1424 | ||
6b0c1480 | 1425 | xm_write16(hw, port, XM_MMU_CMD, cmd); |
baef58b1 | 1426 | |
6b0c1480 | 1427 | mode = xm_read32(hw, port, XM_MODE); |
baef58b1 SH |
1428 | if (skge->flow_control == FLOW_MODE_SYMMETRIC || |
1429 | skge->flow_control == FLOW_MODE_LOC_SEND) { | |
1430 | /* | |
1431 | * Configure Pause Frame Generation | |
1432 | * Use internal and external Pause Frame Generation. | |
1433 | * Sending pause frames is edge triggered. | |
1434 | * Send a Pause frame with the maximum pause time if | |
1435 | * internal oder external FIFO full condition occurs. | |
1436 | * Send a zero pause time frame to re-start transmission. | |
1437 | */ | |
1438 | /* XM_PAUSE_DA = '010000C28001' (default) */ | |
1439 | /* XM_MAC_PTIME = 0xffff (maximum) */ | |
1440 | /* remember this value is defined in big endian (!) */ | |
6b0c1480 | 1441 | xm_write16(hw, port, XM_MAC_PTIME, 0xffff); |
baef58b1 SH |
1442 | |
1443 | mode |= XM_PAUSE_MODE; | |
6b0c1480 | 1444 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE); |
baef58b1 SH |
1445 | } else { |
1446 | /* | |
1447 | * disable pause frame generation is required for 1000BT | |
1448 | * because the XMAC is not reset if the link is going down | |
1449 | */ | |
1450 | /* Disable Pause Mode in Mode Register */ | |
1451 | mode &= ~XM_PAUSE_MODE; | |
1452 | ||
6b0c1480 | 1453 | skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE); |
baef58b1 SH |
1454 | } |
1455 | ||
6b0c1480 | 1456 | xm_write32(hw, port, XM_MODE, mode); |
baef58b1 SH |
1457 | |
1458 | msk = XM_DEF_MSK; | |
89bf5f23 SH |
1459 | /* disable GP0 interrupt bit for external Phy */ |
1460 | msk |= XM_IS_INP_ASS; | |
baef58b1 | 1461 | |
6b0c1480 SH |
1462 | xm_write16(hw, port, XM_IMSK, msk); |
1463 | xm_read16(hw, port, XM_ISRC); | |
baef58b1 SH |
1464 | |
1465 | /* get MMU Command Reg. */ | |
6b0c1480 | 1466 | cmd = xm_read16(hw, port, XM_MMU_CMD); |
89bf5f23 | 1467 | if (skge->duplex == DUPLEX_FULL) |
baef58b1 SH |
1468 | cmd |= XM_MMU_GMII_FD; |
1469 | ||
89bf5f23 SH |
1470 | /* |
1471 | * Workaround BCOM Errata (#10523) for all BCom Phys | |
1472 | * Enable Power Management after link up | |
1473 | */ | |
1474 | xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, | |
1475 | xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL) | |
1476 | & ~PHY_B_AC_DIS_PM); | |
1477 | xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK); | |
baef58b1 SH |
1478 | |
1479 | /* enable Rx/Tx */ | |
6b0c1480 | 1480 | xm_write16(hw, port, XM_MMU_CMD, |
baef58b1 SH |
1481 | cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX); |
1482 | skge_link_up(skge); | |
1483 | } | |
1484 | ||
1485 | ||
45bada65 | 1486 | static inline void bcom_phy_intr(struct skge_port *skge) |
baef58b1 SH |
1487 | { |
1488 | struct skge_hw *hw = skge->hw; | |
1489 | int port = skge->port; | |
45bada65 SH |
1490 | u16 isrc; |
1491 | ||
1492 | isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT); | |
7e676d91 SH |
1493 | if (netif_msg_intr(skge)) |
1494 | printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n", | |
1495 | skge->netdev->name, isrc); | |
baef58b1 | 1496 | |
45bada65 SH |
1497 | if (isrc & PHY_B_IS_PSE) |
1498 | printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n", | |
1499 | hw->dev[port]->name); | |
baef58b1 SH |
1500 | |
1501 | /* Workaround BCom Errata: | |
1502 | * enable and disable loopback mode if "NO HCD" occurs. | |
1503 | */ | |
45bada65 | 1504 | if (isrc & PHY_B_IS_NO_HDCL) { |
6b0c1480 SH |
1505 | u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL); |
1506 | xm_phy_write(hw, port, PHY_BCOM_CTRL, | |
baef58b1 | 1507 | ctrl | PHY_CT_LOOP); |
6b0c1480 | 1508 | xm_phy_write(hw, port, PHY_BCOM_CTRL, |
baef58b1 SH |
1509 | ctrl & ~PHY_CT_LOOP); |
1510 | } | |
1511 | ||
45bada65 SH |
1512 | if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE)) |
1513 | bcom_check_link(hw, port); | |
baef58b1 | 1514 | |
baef58b1 SH |
1515 | } |
1516 | ||
2cd8e5d3 SH |
1517 | static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val) |
1518 | { | |
1519 | int i; | |
1520 | ||
1521 | gma_write16(hw, port, GM_SMI_DATA, val); | |
1522 | gma_write16(hw, port, GM_SMI_CTRL, | |
1523 | GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg)); | |
1524 | for (i = 0; i < PHY_RETRIES; i++) { | |
1525 | udelay(1); | |
1526 | ||
1527 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) | |
1528 | return 0; | |
1529 | } | |
1530 | ||
1531 | printk(KERN_WARNING PFX "%s: phy write timeout\n", | |
1532 | hw->dev[port]->name); | |
1533 | return -EIO; | |
1534 | } | |
1535 | ||
1536 | static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val) | |
1537 | { | |
1538 | int i; | |
1539 | ||
1540 | gma_write16(hw, port, GM_SMI_CTRL, | |
1541 | GM_SMI_CT_PHY_AD(hw->phy_addr) | |
1542 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); | |
1543 | ||
1544 | for (i = 0; i < PHY_RETRIES; i++) { | |
1545 | udelay(1); | |
1546 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) | |
1547 | goto ready; | |
1548 | } | |
1549 | ||
1550 | return -ETIMEDOUT; | |
1551 | ready: | |
1552 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
1553 | return 0; | |
1554 | } | |
1555 | ||
1556 | static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg) | |
1557 | { | |
1558 | u16 v = 0; | |
1559 | if (__gm_phy_read(hw, port, reg, &v)) | |
1560 | printk(KERN_WARNING PFX "%s: phy read timeout\n", | |
1561 | hw->dev[port]->name); | |
1562 | return v; | |
1563 | } | |
1564 | ||
8f3f8193 | 1565 | /* Marvell Phy Initialization */ |
baef58b1 SH |
1566 | static void yukon_init(struct skge_hw *hw, int port) |
1567 | { | |
1568 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
1569 | u16 ctrl, ct1000, adv; | |
baef58b1 | 1570 | |
baef58b1 | 1571 | if (skge->autoneg == AUTONEG_ENABLE) { |
6b0c1480 | 1572 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
baef58b1 SH |
1573 | |
1574 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
1575 | PHY_M_EC_MAC_S_MSK); | |
1576 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); | |
1577 | ||
c506a509 | 1578 | ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1); |
baef58b1 | 1579 | |
6b0c1480 | 1580 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); |
baef58b1 SH |
1581 | } |
1582 | ||
6b0c1480 | 1583 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); |
baef58b1 SH |
1584 | if (skge->autoneg == AUTONEG_DISABLE) |
1585 | ctrl &= ~PHY_CT_ANE; | |
1586 | ||
1587 | ctrl |= PHY_CT_RESET; | |
6b0c1480 | 1588 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); |
baef58b1 SH |
1589 | |
1590 | ctrl = 0; | |
1591 | ct1000 = 0; | |
b18f2091 | 1592 | adv = PHY_AN_CSMA; |
baef58b1 SH |
1593 | |
1594 | if (skge->autoneg == AUTONEG_ENABLE) { | |
5e1705dd | 1595 | if (hw->copper) { |
baef58b1 SH |
1596 | if (skge->advertising & ADVERTISED_1000baseT_Full) |
1597 | ct1000 |= PHY_M_1000C_AFD; | |
1598 | if (skge->advertising & ADVERTISED_1000baseT_Half) | |
1599 | ct1000 |= PHY_M_1000C_AHD; | |
1600 | if (skge->advertising & ADVERTISED_100baseT_Full) | |
1601 | adv |= PHY_M_AN_100_FD; | |
1602 | if (skge->advertising & ADVERTISED_100baseT_Half) | |
1603 | adv |= PHY_M_AN_100_HD; | |
1604 | if (skge->advertising & ADVERTISED_10baseT_Full) | |
1605 | adv |= PHY_M_AN_10_FD; | |
1606 | if (skge->advertising & ADVERTISED_10baseT_Half) | |
1607 | adv |= PHY_M_AN_10_HD; | |
45bada65 | 1608 | } else /* special defines for FIBER (88E1011S only) */ |
baef58b1 SH |
1609 | adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; |
1610 | ||
45bada65 SH |
1611 | /* Set Flow-control capabilities */ |
1612 | adv |= phy_pause_map[skge->flow_control]; | |
1613 | ||
baef58b1 SH |
1614 | /* Restart Auto-negotiation */ |
1615 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
1616 | } else { | |
1617 | /* forced speed/duplex settings */ | |
1618 | ct1000 = PHY_M_1000C_MSE; | |
1619 | ||
1620 | if (skge->duplex == DUPLEX_FULL) | |
1621 | ctrl |= PHY_CT_DUP_MD; | |
1622 | ||
1623 | switch (skge->speed) { | |
1624 | case SPEED_1000: | |
1625 | ctrl |= PHY_CT_SP1000; | |
1626 | break; | |
1627 | case SPEED_100: | |
1628 | ctrl |= PHY_CT_SP100; | |
1629 | break; | |
1630 | } | |
1631 | ||
1632 | ctrl |= PHY_CT_RESET; | |
1633 | } | |
1634 | ||
c506a509 | 1635 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); |
baef58b1 | 1636 | |
6b0c1480 SH |
1637 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); |
1638 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
baef58b1 | 1639 | |
baef58b1 SH |
1640 | /* Enable phy interrupt on autonegotiation complete (or link up) */ |
1641 | if (skge->autoneg == AUTONEG_ENABLE) | |
4cde06ed | 1642 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK); |
baef58b1 | 1643 | else |
4cde06ed | 1644 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); |
baef58b1 SH |
1645 | } |
1646 | ||
1647 | static void yukon_reset(struct skge_hw *hw, int port) | |
1648 | { | |
6b0c1480 SH |
1649 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */ |
1650 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ | |
1651 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
1652 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
1653 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
baef58b1 | 1654 | |
6b0c1480 SH |
1655 | gma_write16(hw, port, GM_RX_CTRL, |
1656 | gma_read16(hw, port, GM_RX_CTRL) | |
baef58b1 SH |
1657 | | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
1658 | } | |
1659 | ||
c8868611 SH |
1660 | /* Apparently, early versions of Yukon-Lite had wrong chip_id? */ |
1661 | static int is_yukon_lite_a0(struct skge_hw *hw) | |
1662 | { | |
1663 | u32 reg; | |
1664 | int ret; | |
1665 | ||
1666 | if (hw->chip_id != CHIP_ID_YUKON) | |
1667 | return 0; | |
1668 | ||
1669 | reg = skge_read32(hw, B2_FAR); | |
1670 | skge_write8(hw, B2_FAR + 3, 0xff); | |
1671 | ret = (skge_read8(hw, B2_FAR + 3) != 0); | |
1672 | skge_write32(hw, B2_FAR, reg); | |
1673 | return ret; | |
1674 | } | |
1675 | ||
baef58b1 SH |
1676 | static void yukon_mac_init(struct skge_hw *hw, int port) |
1677 | { | |
1678 | struct skge_port *skge = netdev_priv(hw->dev[port]); | |
1679 | int i; | |
1680 | u32 reg; | |
1681 | const u8 *addr = hw->dev[port]->dev_addr; | |
1682 | ||
1683 | /* WA code for COMA mode -- set PHY reset */ | |
1684 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
46a60f2d SH |
1685 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
1686 | reg = skge_read32(hw, B2_GP_IO); | |
1687 | reg |= GP_DIR_9 | GP_IO_9; | |
1688 | skge_write32(hw, B2_GP_IO, reg); | |
1689 | } | |
baef58b1 SH |
1690 | |
1691 | /* hard reset */ | |
6b0c1480 SH |
1692 | skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
1693 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); | |
baef58b1 SH |
1694 | |
1695 | /* WA code for COMA mode -- clear PHY reset */ | |
1696 | if (hw->chip_id == CHIP_ID_YUKON_LITE && | |
46a60f2d SH |
1697 | hw->chip_rev >= CHIP_REV_YU_LITE_A3) { |
1698 | reg = skge_read32(hw, B2_GP_IO); | |
1699 | reg |= GP_DIR_9; | |
1700 | reg &= ~GP_IO_9; | |
1701 | skge_write32(hw, B2_GP_IO, reg); | |
1702 | } | |
baef58b1 SH |
1703 | |
1704 | /* Set hardware config mode */ | |
1705 | reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP | | |
1706 | GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE; | |
5e1705dd | 1707 | reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB; |
baef58b1 SH |
1708 | |
1709 | /* Clear GMC reset */ | |
6b0c1480 SH |
1710 | skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET); |
1711 | skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR); | |
1712 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR); | |
564f9abb | 1713 | |
baef58b1 SH |
1714 | if (skge->autoneg == AUTONEG_DISABLE) { |
1715 | reg = GM_GPCR_AU_ALL_DIS; | |
6b0c1480 SH |
1716 | gma_write16(hw, port, GM_GP_CTRL, |
1717 | gma_read16(hw, port, GM_GP_CTRL) | reg); | |
baef58b1 SH |
1718 | |
1719 | switch (skge->speed) { | |
1720 | case SPEED_1000: | |
564f9abb | 1721 | reg &= ~GM_GPCR_SPEED_100; |
baef58b1 | 1722 | reg |= GM_GPCR_SPEED_1000; |
564f9abb | 1723 | break; |
baef58b1 | 1724 | case SPEED_100: |
564f9abb | 1725 | reg &= ~GM_GPCR_SPEED_1000; |
baef58b1 | 1726 | reg |= GM_GPCR_SPEED_100; |
564f9abb SH |
1727 | break; |
1728 | case SPEED_10: | |
1729 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
1730 | break; | |
baef58b1 SH |
1731 | } |
1732 | ||
1733 | if (skge->duplex == DUPLEX_FULL) | |
1734 | reg |= GM_GPCR_DUP_FULL; | |
1735 | } else | |
1736 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
564f9abb | 1737 | |
baef58b1 SH |
1738 | switch (skge->flow_control) { |
1739 | case FLOW_MODE_NONE: | |
6b0c1480 | 1740 | skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); |
baef58b1 SH |
1741 | reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; |
1742 | break; | |
1743 | case FLOW_MODE_LOC_SEND: | |
1744 | /* disable Rx flow-control */ | |
1745 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
1746 | } | |
1747 | ||
6b0c1480 | 1748 | gma_write16(hw, port, GM_GP_CTRL, reg); |
46a60f2d | 1749 | skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
baef58b1 | 1750 | |
baef58b1 | 1751 | yukon_init(hw, port); |
baef58b1 SH |
1752 | |
1753 | /* MIB clear */ | |
6b0c1480 SH |
1754 | reg = gma_read16(hw, port, GM_PHY_ADDR); |
1755 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
baef58b1 SH |
1756 | |
1757 | for (i = 0; i < GM_MIB_CNT_SIZE; i++) | |
6b0c1480 SH |
1758 | gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i); |
1759 | gma_write16(hw, port, GM_PHY_ADDR, reg); | |
baef58b1 SH |
1760 | |
1761 | /* transmit control */ | |
6b0c1480 | 1762 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); |
baef58b1 SH |
1763 | |
1764 | /* receive control reg: unicast + multicast + no FCS */ | |
6b0c1480 | 1765 | gma_write16(hw, port, GM_RX_CTRL, |
baef58b1 SH |
1766 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
1767 | ||
1768 | /* transmit flow control */ | |
6b0c1480 | 1769 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); |
baef58b1 SH |
1770 | |
1771 | /* transmit parameter */ | |
6b0c1480 | 1772 | gma_write16(hw, port, GM_TX_PARAM, |
baef58b1 SH |
1773 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | |
1774 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
1775 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF)); | |
1776 | ||
1777 | /* serial mode register */ | |
1778 | reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
1779 | if (hw->dev[port]->mtu > 1500) | |
1780 | reg |= GM_SMOD_JUMBO_ENA; | |
1781 | ||
6b0c1480 | 1782 | gma_write16(hw, port, GM_SERIAL_MODE, reg); |
baef58b1 SH |
1783 | |
1784 | /* physical address: used for pause frames */ | |
6b0c1480 | 1785 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); |
baef58b1 | 1786 | /* virtual address for data */ |
6b0c1480 | 1787 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); |
baef58b1 SH |
1788 | |
1789 | /* enable interrupt mask for counter overflows */ | |
6b0c1480 SH |
1790 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
1791 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
1792 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
baef58b1 SH |
1793 | |
1794 | /* Initialize Mac Fifo */ | |
1795 | ||
1796 | /* Configure Rx MAC FIFO */ | |
6b0c1480 | 1797 | skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK); |
baef58b1 | 1798 | reg = GMF_OPER_ON | GMF_RX_F_FL_ON; |
c8868611 SH |
1799 | |
1800 | /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */ | |
1801 | if (is_yukon_lite_a0(hw)) | |
baef58b1 | 1802 | reg &= ~GMF_RX_F_FL_ON; |
c8868611 | 1803 | |
6b0c1480 SH |
1804 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); |
1805 | skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg); | |
c5923081 SH |
1806 | /* |
1807 | * because Pause Packet Truncation in GMAC is not working | |
1808 | * we have to increase the Flush Threshold to 64 bytes | |
1809 | * in order to flush pause packets in Rx FIFO on Yukon-1 | |
1810 | */ | |
1811 | skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1); | |
baef58b1 SH |
1812 | |
1813 | /* Configure Tx MAC FIFO */ | |
6b0c1480 SH |
1814 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); |
1815 | skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
baef58b1 SH |
1816 | } |
1817 | ||
355ec572 SH |
1818 | /* Go into power down mode */ |
1819 | static void yukon_suspend(struct skge_hw *hw, int port) | |
1820 | { | |
1821 | u16 ctrl; | |
1822 | ||
1823 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
1824 | ctrl |= PHY_M_PC_POL_R_DIS; | |
1825 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
1826 | ||
1827 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
1828 | ctrl |= PHY_CT_RESET; | |
1829 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
1830 | ||
1831 | /* switch IEEE compatible power down mode on */ | |
1832 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
1833 | ctrl |= PHY_CT_PDOWN; | |
1834 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
1835 | } | |
1836 | ||
baef58b1 SH |
1837 | static void yukon_stop(struct skge_port *skge) |
1838 | { | |
1839 | struct skge_hw *hw = skge->hw; | |
1840 | int port = skge->port; | |
1841 | ||
46a60f2d SH |
1842 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); |
1843 | yukon_reset(hw, port); | |
baef58b1 | 1844 | |
6b0c1480 SH |
1845 | gma_write16(hw, port, GM_GP_CTRL, |
1846 | gma_read16(hw, port, GM_GP_CTRL) | |
0eedf4ac | 1847 | & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA)); |
6b0c1480 | 1848 | gma_read16(hw, port, GM_GP_CTRL); |
baef58b1 | 1849 | |
355ec572 | 1850 | yukon_suspend(hw, port); |
46a60f2d | 1851 | |
baef58b1 | 1852 | /* set GPHY Control reset */ |
46a60f2d SH |
1853 | skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
1854 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); | |
baef58b1 SH |
1855 | } |
1856 | ||
1857 | static void yukon_get_stats(struct skge_port *skge, u64 *data) | |
1858 | { | |
1859 | struct skge_hw *hw = skge->hw; | |
1860 | int port = skge->port; | |
1861 | int i; | |
1862 | ||
6b0c1480 SH |
1863 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 |
1864 | | gma_read32(hw, port, GM_TXO_OK_LO); | |
1865 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 | |
1866 | | gma_read32(hw, port, GM_RXO_OK_LO); | |
baef58b1 SH |
1867 | |
1868 | for (i = 2; i < ARRAY_SIZE(skge_stats); i++) | |
6b0c1480 | 1869 | data[i] = gma_read32(hw, port, |
baef58b1 SH |
1870 | skge_stats[i].gma_offset); |
1871 | } | |
1872 | ||
1873 | static void yukon_mac_intr(struct skge_hw *hw, int port) | |
1874 | { | |
7e676d91 SH |
1875 | struct net_device *dev = hw->dev[port]; |
1876 | struct skge_port *skge = netdev_priv(dev); | |
6b0c1480 | 1877 | u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); |
baef58b1 | 1878 | |
7e676d91 SH |
1879 | if (netif_msg_intr(skge)) |
1880 | printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n", | |
1881 | dev->name, status); | |
1882 | ||
baef58b1 SH |
1883 | if (status & GM_IS_RX_FF_OR) { |
1884 | ++skge->net_stats.rx_fifo_errors; | |
d8a09943 | 1885 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); |
baef58b1 | 1886 | } |
d8a09943 | 1887 | |
baef58b1 SH |
1888 | if (status & GM_IS_TX_FF_UR) { |
1889 | ++skge->net_stats.tx_fifo_errors; | |
d8a09943 | 1890 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); |
baef58b1 SH |
1891 | } |
1892 | ||
1893 | } | |
1894 | ||
1895 | static u16 yukon_speed(const struct skge_hw *hw, u16 aux) | |
1896 | { | |
95566065 | 1897 | switch (aux & PHY_M_PS_SPEED_MSK) { |
baef58b1 SH |
1898 | case PHY_M_PS_SPEED_1000: |
1899 | return SPEED_1000; | |
1900 | case PHY_M_PS_SPEED_100: | |
1901 | return SPEED_100; | |
1902 | default: | |
1903 | return SPEED_10; | |
1904 | } | |
1905 | } | |
1906 | ||
1907 | static void yukon_link_up(struct skge_port *skge) | |
1908 | { | |
1909 | struct skge_hw *hw = skge->hw; | |
1910 | int port = skge->port; | |
1911 | u16 reg; | |
1912 | ||
baef58b1 | 1913 | /* Enable Transmit FIFO Underrun */ |
46a60f2d | 1914 | skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
baef58b1 | 1915 | |
6b0c1480 | 1916 | reg = gma_read16(hw, port, GM_GP_CTRL); |
baef58b1 SH |
1917 | if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE) |
1918 | reg |= GM_GPCR_DUP_FULL; | |
1919 | ||
1920 | /* enable Rx/Tx */ | |
1921 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
6b0c1480 | 1922 | gma_write16(hw, port, GM_GP_CTRL, reg); |
baef58b1 | 1923 | |
4cde06ed | 1924 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK); |
baef58b1 SH |
1925 | skge_link_up(skge); |
1926 | } | |
1927 | ||
1928 | static void yukon_link_down(struct skge_port *skge) | |
1929 | { | |
1930 | struct skge_hw *hw = skge->hw; | |
1931 | int port = skge->port; | |
d8a09943 | 1932 | u16 ctrl; |
baef58b1 | 1933 | |
6b0c1480 | 1934 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); |
d8a09943 SH |
1935 | |
1936 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
1937 | ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
1938 | gma_write16(hw, port, GM_GP_CTRL, ctrl); | |
baef58b1 | 1939 | |
c506a509 | 1940 | if (skge->flow_control == FLOW_MODE_REM_SEND) { |
baef58b1 | 1941 | /* restore Asymmetric Pause bit */ |
6b0c1480 SH |
1942 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, |
1943 | gm_phy_read(hw, port, | |
baef58b1 SH |
1944 | PHY_MARV_AUNE_ADV) |
1945 | | PHY_M_AN_ASP); | |
1946 | ||
1947 | } | |
1948 | ||
1949 | yukon_reset(hw, port); | |
1950 | skge_link_down(skge); | |
1951 | ||
1952 | yukon_init(hw, port); | |
1953 | } | |
1954 | ||
1955 | static void yukon_phy_intr(struct skge_port *skge) | |
1956 | { | |
1957 | struct skge_hw *hw = skge->hw; | |
1958 | int port = skge->port; | |
1959 | const char *reason = NULL; | |
1960 | u16 istatus, phystat; | |
1961 | ||
6b0c1480 SH |
1962 | istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); |
1963 | phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); | |
7e676d91 SH |
1964 | |
1965 | if (netif_msg_intr(skge)) | |
1966 | printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
1967 | skge->netdev->name, istatus, phystat); | |
baef58b1 SH |
1968 | |
1969 | if (istatus & PHY_M_IS_AN_COMPL) { | |
6b0c1480 | 1970 | if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP) |
baef58b1 SH |
1971 | & PHY_M_AN_RF) { |
1972 | reason = "remote fault"; | |
1973 | goto failed; | |
1974 | } | |
1975 | ||
c506a509 | 1976 | if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { |
baef58b1 SH |
1977 | reason = "master/slave fault"; |
1978 | goto failed; | |
1979 | } | |
1980 | ||
1981 | if (!(phystat & PHY_M_PS_SPDUP_RES)) { | |
1982 | reason = "speed/duplex"; | |
1983 | goto failed; | |
1984 | } | |
1985 | ||
1986 | skge->duplex = (phystat & PHY_M_PS_FULL_DUP) | |
1987 | ? DUPLEX_FULL : DUPLEX_HALF; | |
1988 | skge->speed = yukon_speed(hw, phystat); | |
1989 | ||
baef58b1 SH |
1990 | /* We are using IEEE 802.3z/D5.0 Table 37-4 */ |
1991 | switch (phystat & PHY_M_PS_PAUSE_MSK) { | |
1992 | case PHY_M_PS_PAUSE_MSK: | |
1993 | skge->flow_control = FLOW_MODE_SYMMETRIC; | |
1994 | break; | |
1995 | case PHY_M_PS_RX_P_EN: | |
1996 | skge->flow_control = FLOW_MODE_REM_SEND; | |
1997 | break; | |
1998 | case PHY_M_PS_TX_P_EN: | |
1999 | skge->flow_control = FLOW_MODE_LOC_SEND; | |
2000 | break; | |
2001 | default: | |
2002 | skge->flow_control = FLOW_MODE_NONE; | |
2003 | } | |
2004 | ||
2005 | if (skge->flow_control == FLOW_MODE_NONE || | |
2006 | (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF)) | |
6b0c1480 | 2007 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); |
baef58b1 | 2008 | else |
6b0c1480 | 2009 | skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
baef58b1 SH |
2010 | yukon_link_up(skge); |
2011 | return; | |
2012 | } | |
2013 | ||
2014 | if (istatus & PHY_M_IS_LSP_CHANGE) | |
2015 | skge->speed = yukon_speed(hw, phystat); | |
2016 | ||
2017 | if (istatus & PHY_M_IS_DUP_CHANGE) | |
2018 | skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
2019 | if (istatus & PHY_M_IS_LST_CHANGE) { | |
2020 | if (phystat & PHY_M_PS_LINK_UP) | |
2021 | yukon_link_up(skge); | |
2022 | else | |
2023 | yukon_link_down(skge); | |
2024 | } | |
2025 | return; | |
2026 | failed: | |
2027 | printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n", | |
2028 | skge->netdev->name, reason); | |
2029 | ||
2030 | /* XXX restart autonegotiation? */ | |
2031 | } | |
2032 | ||
ee294dcd SH |
2033 | static void skge_phy_reset(struct skge_port *skge) |
2034 | { | |
2035 | struct skge_hw *hw = skge->hw; | |
2036 | int port = skge->port; | |
2037 | ||
2038 | netif_stop_queue(skge->netdev); | |
2039 | netif_carrier_off(skge->netdev); | |
2040 | ||
d85b514f | 2041 | mutex_lock(&hw->phy_mutex); |
ee294dcd SH |
2042 | if (hw->chip_id == CHIP_ID_GENESIS) { |
2043 | genesis_reset(hw, port); | |
2044 | genesis_mac_init(hw, port); | |
2045 | } else { | |
2046 | yukon_reset(hw, port); | |
2047 | yukon_init(hw, port); | |
2048 | } | |
d85b514f | 2049 | mutex_unlock(&hw->phy_mutex); |
ee294dcd SH |
2050 | } |
2051 | ||
2cd8e5d3 SH |
2052 | /* Basic MII support */ |
2053 | static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
2054 | { | |
2055 | struct mii_ioctl_data *data = if_mii(ifr); | |
2056 | struct skge_port *skge = netdev_priv(dev); | |
2057 | struct skge_hw *hw = skge->hw; | |
2058 | int err = -EOPNOTSUPP; | |
2059 | ||
2060 | if (!netif_running(dev)) | |
2061 | return -ENODEV; /* Phy still in reset */ | |
2062 | ||
2063 | switch(cmd) { | |
2064 | case SIOCGMIIPHY: | |
2065 | data->phy_id = hw->phy_addr; | |
2066 | ||
2067 | /* fallthru */ | |
2068 | case SIOCGMIIREG: { | |
2069 | u16 val = 0; | |
d85b514f | 2070 | mutex_lock(&hw->phy_mutex); |
2cd8e5d3 SH |
2071 | if (hw->chip_id == CHIP_ID_GENESIS) |
2072 | err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); | |
2073 | else | |
2074 | err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val); | |
d85b514f | 2075 | mutex_unlock(&hw->phy_mutex); |
2cd8e5d3 SH |
2076 | data->val_out = val; |
2077 | break; | |
2078 | } | |
2079 | ||
2080 | case SIOCSMIIREG: | |
2081 | if (!capable(CAP_NET_ADMIN)) | |
2082 | return -EPERM; | |
2083 | ||
d85b514f | 2084 | mutex_lock(&hw->phy_mutex); |
2cd8e5d3 SH |
2085 | if (hw->chip_id == CHIP_ID_GENESIS) |
2086 | err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f, | |
2087 | data->val_in); | |
2088 | else | |
2089 | err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f, | |
2090 | data->val_in); | |
d85b514f | 2091 | mutex_unlock(&hw->phy_mutex); |
2cd8e5d3 SH |
2092 | break; |
2093 | } | |
2094 | return err; | |
2095 | } | |
2096 | ||
baef58b1 SH |
2097 | static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len) |
2098 | { | |
2099 | u32 end; | |
2100 | ||
2101 | start /= 8; | |
2102 | len /= 8; | |
2103 | end = start + len - 1; | |
2104 | ||
2105 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); | |
2106 | skge_write32(hw, RB_ADDR(q, RB_START), start); | |
2107 | skge_write32(hw, RB_ADDR(q, RB_WP), start); | |
2108 | skge_write32(hw, RB_ADDR(q, RB_RP), start); | |
2109 | skge_write32(hw, RB_ADDR(q, RB_END), end); | |
2110 | ||
2111 | if (q == Q_R1 || q == Q_R2) { | |
2112 | /* Set thresholds on receive queue's */ | |
2113 | skge_write32(hw, RB_ADDR(q, RB_RX_UTPP), | |
2114 | start + (2*len)/3); | |
2115 | skge_write32(hw, RB_ADDR(q, RB_RX_LTPP), | |
2116 | start + (len/3)); | |
2117 | } else { | |
2118 | /* Enable store & forward on Tx queue's because | |
2119 | * Tx FIFO is only 4K on Genesis and 1K on Yukon | |
2120 | */ | |
2121 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
2122 | } | |
2123 | ||
2124 | skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
2125 | } | |
2126 | ||
2127 | /* Setup Bus Memory Interface */ | |
2128 | static void skge_qset(struct skge_port *skge, u16 q, | |
2129 | const struct skge_element *e) | |
2130 | { | |
2131 | struct skge_hw *hw = skge->hw; | |
2132 | u32 watermark = 0x600; | |
2133 | u64 base = skge->dma + (e->desc - skge->mem); | |
2134 | ||
2135 | /* optimization to reduce window on 32bit/33mhz */ | |
2136 | if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0) | |
2137 | watermark /= 2; | |
2138 | ||
2139 | skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET); | |
2140 | skge_write32(hw, Q_ADDR(q, Q_F), watermark); | |
2141 | skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32)); | |
2142 | skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base); | |
2143 | } | |
2144 | ||
2145 | static int skge_up(struct net_device *dev) | |
2146 | { | |
2147 | struct skge_port *skge = netdev_priv(dev); | |
2148 | struct skge_hw *hw = skge->hw; | |
2149 | int port = skge->port; | |
2150 | u32 chunk, ram_addr; | |
2151 | size_t rx_size, tx_size; | |
2152 | int err; | |
2153 | ||
2154 | if (netif_msg_ifup(skge)) | |
2155 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
2156 | ||
19a33d4e | 2157 | if (dev->mtu > RX_BUF_SIZE) |
901ccefb | 2158 | skge->rx_buf_size = dev->mtu + ETH_HLEN; |
19a33d4e SH |
2159 | else |
2160 | skge->rx_buf_size = RX_BUF_SIZE; | |
2161 | ||
2162 | ||
baef58b1 SH |
2163 | rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc); |
2164 | tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc); | |
2165 | skge->mem_size = tx_size + rx_size; | |
2166 | skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma); | |
2167 | if (!skge->mem) | |
2168 | return -ENOMEM; | |
2169 | ||
c3da1447 SH |
2170 | BUG_ON(skge->dma & 7); |
2171 | ||
2172 | if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) { | |
2173 | printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n"); | |
2174 | err = -EINVAL; | |
2175 | goto free_pci_mem; | |
2176 | } | |
2177 | ||
baef58b1 SH |
2178 | memset(skge->mem, 0, skge->mem_size); |
2179 | ||
203babb6 SH |
2180 | err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma); |
2181 | if (err) | |
baef58b1 SH |
2182 | goto free_pci_mem; |
2183 | ||
c54f9765 | 2184 | err = skge_rx_fill(dev); |
19a33d4e | 2185 | if (err) |
baef58b1 SH |
2186 | goto free_rx_ring; |
2187 | ||
203babb6 SH |
2188 | err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size, |
2189 | skge->dma + rx_size); | |
2190 | if (err) | |
baef58b1 SH |
2191 | goto free_rx_ring; |
2192 | ||
8f3f8193 | 2193 | /* Initialize MAC */ |
d85b514f | 2194 | mutex_lock(&hw->phy_mutex); |
baef58b1 SH |
2195 | if (hw->chip_id == CHIP_ID_GENESIS) |
2196 | genesis_mac_init(hw, port); | |
2197 | else | |
2198 | yukon_mac_init(hw, port); | |
d85b514f | 2199 | mutex_unlock(&hw->phy_mutex); |
baef58b1 SH |
2200 | |
2201 | /* Configure RAMbuffers */ | |
981d0377 | 2202 | chunk = hw->ram_size / ((hw->ports + 1)*2); |
baef58b1 SH |
2203 | ram_addr = hw->ram_offset + 2 * chunk * port; |
2204 | ||
2205 | skge_ramset(hw, rxqaddr[port], ram_addr, chunk); | |
2206 | skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean); | |
2207 | ||
2208 | BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean); | |
2209 | skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk); | |
2210 | skge_qset(skge, txqaddr[port], skge->tx_ring.to_use); | |
2211 | ||
2212 | /* Start receiver BMU */ | |
2213 | wmb(); | |
2214 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); | |
6abebb53 | 2215 | skge_led(skge, LED_MODE_ON); |
baef58b1 | 2216 | |
239e44e1 | 2217 | netif_poll_enable(dev); |
baef58b1 SH |
2218 | return 0; |
2219 | ||
2220 | free_rx_ring: | |
2221 | skge_rx_clean(skge); | |
2222 | kfree(skge->rx_ring.start); | |
2223 | free_pci_mem: | |
2224 | pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); | |
7731a4ea | 2225 | skge->mem = NULL; |
baef58b1 SH |
2226 | |
2227 | return err; | |
2228 | } | |
2229 | ||
2230 | static int skge_down(struct net_device *dev) | |
2231 | { | |
2232 | struct skge_port *skge = netdev_priv(dev); | |
2233 | struct skge_hw *hw = skge->hw; | |
2234 | int port = skge->port; | |
2235 | ||
7731a4ea SH |
2236 | if (skge->mem == NULL) |
2237 | return 0; | |
2238 | ||
baef58b1 SH |
2239 | if (netif_msg_ifdown(skge)) |
2240 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
2241 | ||
2242 | netif_stop_queue(dev); | |
2243 | ||
46a60f2d SH |
2244 | skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF); |
2245 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2246 | genesis_stop(skge); | |
2247 | else | |
2248 | yukon_stop(skge); | |
2249 | ||
baef58b1 SH |
2250 | /* Stop transmitter */ |
2251 | skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP); | |
2252 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
2253 | RB_RST_SET|RB_DIS_OP_MD); | |
2254 | ||
baef58b1 SH |
2255 | |
2256 | /* Disable Force Sync bit and Enable Alloc bit */ | |
6b0c1480 | 2257 | skge_write8(hw, SK_REG(port, TXA_CTRL), |
baef58b1 SH |
2258 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); |
2259 | ||
2260 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
6b0c1480 SH |
2261 | skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); |
2262 | skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
baef58b1 SH |
2263 | |
2264 | /* Reset PCI FIFO */ | |
2265 | skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET); | |
2266 | skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
2267 | ||
2268 | /* Reset the RAM Buffer async Tx queue */ | |
2269 | skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET); | |
2270 | /* stop receiver */ | |
2271 | skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); | |
2272 | skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL), | |
2273 | RB_RST_SET|RB_DIS_OP_MD); | |
2274 | skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); | |
2275 | ||
2276 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
6b0c1480 SH |
2277 | skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET); |
2278 | skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET); | |
baef58b1 | 2279 | } else { |
6b0c1480 SH |
2280 | skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); |
2281 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
baef58b1 SH |
2282 | } |
2283 | ||
6abebb53 | 2284 | skge_led(skge, LED_MODE_OFF); |
baef58b1 | 2285 | |
239e44e1 | 2286 | netif_poll_disable(dev); |
513f533e | 2287 | skge_tx_clean(dev); |
baef58b1 SH |
2288 | skge_rx_clean(skge); |
2289 | ||
2290 | kfree(skge->rx_ring.start); | |
2291 | kfree(skge->tx_ring.start); | |
2292 | pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma); | |
7731a4ea | 2293 | skge->mem = NULL; |
baef58b1 SH |
2294 | return 0; |
2295 | } | |
2296 | ||
29b4e886 SH |
2297 | static inline int skge_avail(const struct skge_ring *ring) |
2298 | { | |
2299 | return ((ring->to_clean > ring->to_use) ? 0 : ring->count) | |
2300 | + (ring->to_clean - ring->to_use) - 1; | |
2301 | } | |
2302 | ||
baef58b1 SH |
2303 | static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
2304 | { | |
2305 | struct skge_port *skge = netdev_priv(dev); | |
2306 | struct skge_hw *hw = skge->hw; | |
baef58b1 SH |
2307 | struct skge_element *e; |
2308 | struct skge_tx_desc *td; | |
2309 | int i; | |
2310 | u32 control, len; | |
2311 | u64 map; | |
baef58b1 | 2312 | |
5b057c6b | 2313 | if (skb_padto(skb, ETH_ZLEN)) |
baef58b1 SH |
2314 | return NETDEV_TX_OK; |
2315 | ||
513f533e | 2316 | if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1)) |
baef58b1 | 2317 | return NETDEV_TX_BUSY; |
baef58b1 | 2318 | |
7c442fa1 | 2319 | e = skge->tx_ring.to_use; |
baef58b1 | 2320 | td = e->desc; |
7c442fa1 | 2321 | BUG_ON(td->control & BMU_OWN); |
baef58b1 SH |
2322 | e->skb = skb; |
2323 | len = skb_headlen(skb); | |
2324 | map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
2325 | pci_unmap_addr_set(e, mapaddr, map); | |
2326 | pci_unmap_len_set(e, maplen, len); | |
2327 | ||
2328 | td->dma_lo = map; | |
2329 | td->dma_hi = map >> 32; | |
2330 | ||
2331 | if (skb->ip_summed == CHECKSUM_HW) { | |
baef58b1 SH |
2332 | int offset = skb->h.raw - skb->data; |
2333 | ||
2334 | /* This seems backwards, but it is what the sk98lin | |
2335 | * does. Looks like hardware is wrong? | |
2336 | */ | |
ea182d4a | 2337 | if (skb->h.ipiph->protocol == IPPROTO_UDP |
981d0377 | 2338 | && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON) |
baef58b1 SH |
2339 | control = BMU_TCP_CHECK; |
2340 | else | |
2341 | control = BMU_UDP_CHECK; | |
2342 | ||
2343 | td->csum_offs = 0; | |
2344 | td->csum_start = offset; | |
2345 | td->csum_write = offset + skb->csum; | |
2346 | } else | |
2347 | control = BMU_CHECK; | |
2348 | ||
2349 | if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */ | |
2350 | control |= BMU_EOF| BMU_IRQ_EOF; | |
2351 | else { | |
2352 | struct skge_tx_desc *tf = td; | |
2353 | ||
2354 | control |= BMU_STFWD; | |
2355 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
2356 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
2357 | ||
2358 | map = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
2359 | frag->size, PCI_DMA_TODEVICE); | |
2360 | ||
2361 | e = e->next; | |
7c442fa1 | 2362 | e->skb = skb; |
baef58b1 | 2363 | tf = e->desc; |
7c442fa1 SH |
2364 | BUG_ON(tf->control & BMU_OWN); |
2365 | ||
baef58b1 SH |
2366 | tf->dma_lo = map; |
2367 | tf->dma_hi = (u64) map >> 32; | |
2368 | pci_unmap_addr_set(e, mapaddr, map); | |
2369 | pci_unmap_len_set(e, maplen, frag->size); | |
2370 | ||
2371 | tf->control = BMU_OWN | BMU_SW | control | frag->size; | |
2372 | } | |
2373 | tf->control |= BMU_EOF | BMU_IRQ_EOF; | |
2374 | } | |
2375 | /* Make sure all the descriptors written */ | |
2376 | wmb(); | |
2377 | td->control = BMU_OWN | BMU_SW | BMU_STF | control | len; | |
2378 | wmb(); | |
2379 | ||
2380 | skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START); | |
2381 | ||
7c442fa1 | 2382 | if (unlikely(netif_msg_tx_queued(skge))) |
0b2d7fea | 2383 | printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n", |
7c442fa1 | 2384 | dev->name, e - skge->tx_ring.start, skb->len); |
baef58b1 | 2385 | |
7c442fa1 | 2386 | skge->tx_ring.to_use = e->next; |
9db96479 | 2387 | if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) { |
baef58b1 SH |
2388 | pr_debug("%s: transmit queue full\n", dev->name); |
2389 | netif_stop_queue(dev); | |
2390 | } | |
2391 | ||
c68ce71a SH |
2392 | dev->trans_start = jiffies; |
2393 | ||
baef58b1 SH |
2394 | return NETDEV_TX_OK; |
2395 | } | |
2396 | ||
7c442fa1 SH |
2397 | |
2398 | /* Free resources associated with this reing element */ | |
2399 | static void skge_tx_free(struct skge_port *skge, struct skge_element *e, | |
2400 | u32 control) | |
866b4f3e SH |
2401 | { |
2402 | struct pci_dev *pdev = skge->hw->pdev; | |
866b4f3e | 2403 | |
7c442fa1 | 2404 | BUG_ON(!e->skb); |
866b4f3e | 2405 | |
7c442fa1 SH |
2406 | /* skb header vs. fragment */ |
2407 | if (control & BMU_STF) | |
866b4f3e | 2408 | pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr), |
7c442fa1 SH |
2409 | pci_unmap_len(e, maplen), |
2410 | PCI_DMA_TODEVICE); | |
2411 | else | |
2412 | pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr), | |
2413 | pci_unmap_len(e, maplen), | |
2414 | PCI_DMA_TODEVICE); | |
866b4f3e | 2415 | |
7c442fa1 SH |
2416 | if (control & BMU_EOF) { |
2417 | if (unlikely(netif_msg_tx_done(skge))) | |
2418 | printk(KERN_DEBUG PFX "%s: tx done slot %td\n", | |
2419 | skge->netdev->name, e - skge->tx_ring.start); | |
866b4f3e | 2420 | |
513f533e | 2421 | dev_kfree_skb(e->skb); |
baef58b1 | 2422 | } |
7c442fa1 | 2423 | e->skb = NULL; |
baef58b1 SH |
2424 | } |
2425 | ||
7c442fa1 | 2426 | /* Free all buffers in transmit ring */ |
513f533e | 2427 | static void skge_tx_clean(struct net_device *dev) |
baef58b1 | 2428 | { |
513f533e | 2429 | struct skge_port *skge = netdev_priv(dev); |
7c442fa1 | 2430 | struct skge_element *e; |
baef58b1 | 2431 | |
513f533e | 2432 | netif_tx_lock_bh(dev); |
7c442fa1 SH |
2433 | for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) { |
2434 | struct skge_tx_desc *td = e->desc; | |
2435 | skge_tx_free(skge, e, td->control); | |
2436 | td->control = 0; | |
2437 | } | |
2438 | ||
2439 | skge->tx_ring.to_clean = e; | |
513f533e SH |
2440 | netif_wake_queue(dev); |
2441 | netif_tx_unlock_bh(dev); | |
baef58b1 SH |
2442 | } |
2443 | ||
2444 | static void skge_tx_timeout(struct net_device *dev) | |
2445 | { | |
2446 | struct skge_port *skge = netdev_priv(dev); | |
2447 | ||
2448 | if (netif_msg_timer(skge)) | |
2449 | printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name); | |
2450 | ||
2451 | skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP); | |
513f533e | 2452 | skge_tx_clean(dev); |
baef58b1 SH |
2453 | } |
2454 | ||
2455 | static int skge_change_mtu(struct net_device *dev, int new_mtu) | |
2456 | { | |
7731a4ea | 2457 | int err; |
baef58b1 | 2458 | |
95566065 | 2459 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) |
baef58b1 SH |
2460 | return -EINVAL; |
2461 | ||
7731a4ea SH |
2462 | if (!netif_running(dev)) { |
2463 | dev->mtu = new_mtu; | |
2464 | return 0; | |
2465 | } | |
2466 | ||
2467 | skge_down(dev); | |
baef58b1 | 2468 | |
19a33d4e | 2469 | dev->mtu = new_mtu; |
7731a4ea SH |
2470 | |
2471 | err = skge_up(dev); | |
2472 | if (err) | |
2473 | dev_close(dev); | |
baef58b1 SH |
2474 | |
2475 | return err; | |
2476 | } | |
2477 | ||
2478 | static void genesis_set_multicast(struct net_device *dev) | |
2479 | { | |
2480 | struct skge_port *skge = netdev_priv(dev); | |
2481 | struct skge_hw *hw = skge->hw; | |
2482 | int port = skge->port; | |
2483 | int i, count = dev->mc_count; | |
2484 | struct dev_mc_list *list = dev->mc_list; | |
2485 | u32 mode; | |
2486 | u8 filter[8]; | |
2487 | ||
6b0c1480 | 2488 | mode = xm_read32(hw, port, XM_MODE); |
baef58b1 SH |
2489 | mode |= XM_MD_ENA_HASH; |
2490 | if (dev->flags & IFF_PROMISC) | |
2491 | mode |= XM_MD_ENA_PROM; | |
2492 | else | |
2493 | mode &= ~XM_MD_ENA_PROM; | |
2494 | ||
2495 | if (dev->flags & IFF_ALLMULTI) | |
2496 | memset(filter, 0xff, sizeof(filter)); | |
2497 | else { | |
2498 | memset(filter, 0, sizeof(filter)); | |
95566065 | 2499 | for (i = 0; list && i < count; i++, list = list->next) { |
45bada65 SH |
2500 | u32 crc, bit; |
2501 | crc = ether_crc_le(ETH_ALEN, list->dmi_addr); | |
2502 | bit = ~crc & 0x3f; | |
baef58b1 SH |
2503 | filter[bit/8] |= 1 << (bit%8); |
2504 | } | |
2505 | } | |
2506 | ||
6b0c1480 | 2507 | xm_write32(hw, port, XM_MODE, mode); |
45bada65 | 2508 | xm_outhash(hw, port, XM_HSM, filter); |
baef58b1 SH |
2509 | } |
2510 | ||
2511 | static void yukon_set_multicast(struct net_device *dev) | |
2512 | { | |
2513 | struct skge_port *skge = netdev_priv(dev); | |
2514 | struct skge_hw *hw = skge->hw; | |
2515 | int port = skge->port; | |
2516 | struct dev_mc_list *list = dev->mc_list; | |
2517 | u16 reg; | |
2518 | u8 filter[8]; | |
2519 | ||
2520 | memset(filter, 0, sizeof(filter)); | |
2521 | ||
6b0c1480 | 2522 | reg = gma_read16(hw, port, GM_RX_CTRL); |
baef58b1 SH |
2523 | reg |= GM_RXCR_UCF_ENA; |
2524 | ||
8f3f8193 | 2525 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
baef58b1 SH |
2526 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
2527 | else if (dev->flags & IFF_ALLMULTI) /* all multicast */ | |
2528 | memset(filter, 0xff, sizeof(filter)); | |
2529 | else if (dev->mc_count == 0) /* no multicast */ | |
2530 | reg &= ~GM_RXCR_MCF_ENA; | |
2531 | else { | |
2532 | int i; | |
2533 | reg |= GM_RXCR_MCF_ENA; | |
2534 | ||
95566065 | 2535 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) { |
baef58b1 SH |
2536 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; |
2537 | filter[bit/8] |= 1 << (bit%8); | |
2538 | } | |
2539 | } | |
2540 | ||
2541 | ||
6b0c1480 | 2542 | gma_write16(hw, port, GM_MC_ADDR_H1, |
baef58b1 | 2543 | (u16)filter[0] | ((u16)filter[1] << 8)); |
6b0c1480 | 2544 | gma_write16(hw, port, GM_MC_ADDR_H2, |
baef58b1 | 2545 | (u16)filter[2] | ((u16)filter[3] << 8)); |
6b0c1480 | 2546 | gma_write16(hw, port, GM_MC_ADDR_H3, |
baef58b1 | 2547 | (u16)filter[4] | ((u16)filter[5] << 8)); |
6b0c1480 | 2548 | gma_write16(hw, port, GM_MC_ADDR_H4, |
baef58b1 SH |
2549 | (u16)filter[6] | ((u16)filter[7] << 8)); |
2550 | ||
6b0c1480 | 2551 | gma_write16(hw, port, GM_RX_CTRL, reg); |
baef58b1 SH |
2552 | } |
2553 | ||
383181ac SH |
2554 | static inline u16 phy_length(const struct skge_hw *hw, u32 status) |
2555 | { | |
2556 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2557 | return status >> XMR_FS_LEN_SHIFT; | |
2558 | else | |
2559 | return status >> GMR_FS_LEN_SHIFT; | |
2560 | } | |
2561 | ||
baef58b1 SH |
2562 | static inline int bad_phy_status(const struct skge_hw *hw, u32 status) |
2563 | { | |
2564 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2565 | return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0; | |
2566 | else | |
2567 | return (status & GMR_FS_ANY_ERR) || | |
2568 | (status & GMR_FS_RX_OK) == 0; | |
2569 | } | |
2570 | ||
19a33d4e SH |
2571 | |
2572 | /* Get receive buffer from descriptor. | |
2573 | * Handles copy of small buffers and reallocation failures | |
2574 | */ | |
c54f9765 SH |
2575 | static struct sk_buff *skge_rx_get(struct net_device *dev, |
2576 | struct skge_element *e, | |
2577 | u32 control, u32 status, u16 csum) | |
19a33d4e | 2578 | { |
c54f9765 | 2579 | struct skge_port *skge = netdev_priv(dev); |
383181ac SH |
2580 | struct sk_buff *skb; |
2581 | u16 len = control & BMU_BBC; | |
2582 | ||
2583 | if (unlikely(netif_msg_rx_status(skge))) | |
2584 | printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n", | |
c54f9765 | 2585 | dev->name, e - skge->rx_ring.start, |
383181ac SH |
2586 | status, len); |
2587 | ||
2588 | if (len > skge->rx_buf_size) | |
2589 | goto error; | |
2590 | ||
2591 | if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)) | |
2592 | goto error; | |
2593 | ||
2594 | if (bad_phy_status(skge->hw, status)) | |
2595 | goto error; | |
2596 | ||
2597 | if (phy_length(skge->hw, status) != len) | |
2598 | goto error; | |
19a33d4e SH |
2599 | |
2600 | if (len < RX_COPY_THRESHOLD) { | |
c54f9765 | 2601 | skb = netdev_alloc_skb(dev, len + 2); |
383181ac SH |
2602 | if (!skb) |
2603 | goto resubmit; | |
19a33d4e | 2604 | |
383181ac | 2605 | skb_reserve(skb, 2); |
19a33d4e SH |
2606 | pci_dma_sync_single_for_cpu(skge->hw->pdev, |
2607 | pci_unmap_addr(e, mapaddr), | |
2608 | len, PCI_DMA_FROMDEVICE); | |
383181ac | 2609 | memcpy(skb->data, e->skb->data, len); |
19a33d4e SH |
2610 | pci_dma_sync_single_for_device(skge->hw->pdev, |
2611 | pci_unmap_addr(e, mapaddr), | |
2612 | len, PCI_DMA_FROMDEVICE); | |
19a33d4e | 2613 | skge_rx_reuse(e, skge->rx_buf_size); |
19a33d4e | 2614 | } else { |
383181ac | 2615 | struct sk_buff *nskb; |
c54f9765 | 2616 | nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN); |
383181ac SH |
2617 | if (!nskb) |
2618 | goto resubmit; | |
19a33d4e | 2619 | |
901ccefb | 2620 | skb_reserve(nskb, NET_IP_ALIGN); |
19a33d4e SH |
2621 | pci_unmap_single(skge->hw->pdev, |
2622 | pci_unmap_addr(e, mapaddr), | |
2623 | pci_unmap_len(e, maplen), | |
2624 | PCI_DMA_FROMDEVICE); | |
2625 | skb = e->skb; | |
383181ac | 2626 | prefetch(skb->data); |
19a33d4e | 2627 | skge_rx_setup(skge, e, nskb, skge->rx_buf_size); |
baef58b1 | 2628 | } |
383181ac SH |
2629 | |
2630 | skb_put(skb, len); | |
383181ac SH |
2631 | if (skge->rx_csum) { |
2632 | skb->csum = csum; | |
2633 | skb->ip_summed = CHECKSUM_HW; | |
2634 | } | |
2635 | ||
c54f9765 | 2636 | skb->protocol = eth_type_trans(skb, dev); |
383181ac SH |
2637 | |
2638 | return skb; | |
2639 | error: | |
2640 | ||
2641 | if (netif_msg_rx_err(skge)) | |
2642 | printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n", | |
c54f9765 | 2643 | dev->name, e - skge->rx_ring.start, |
383181ac SH |
2644 | control, status); |
2645 | ||
2646 | if (skge->hw->chip_id == CHIP_ID_GENESIS) { | |
2647 | if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR)) | |
2648 | skge->net_stats.rx_length_errors++; | |
2649 | if (status & XMR_FS_FRA_ERR) | |
2650 | skge->net_stats.rx_frame_errors++; | |
2651 | if (status & XMR_FS_FCS_ERR) | |
2652 | skge->net_stats.rx_crc_errors++; | |
2653 | } else { | |
2654 | if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE)) | |
2655 | skge->net_stats.rx_length_errors++; | |
2656 | if (status & GMR_FS_FRAGMENT) | |
2657 | skge->net_stats.rx_frame_errors++; | |
2658 | if (status & GMR_FS_CRC_ERR) | |
2659 | skge->net_stats.rx_crc_errors++; | |
2660 | } | |
2661 | ||
2662 | resubmit: | |
2663 | skge_rx_reuse(e, skge->rx_buf_size); | |
2664 | return NULL; | |
baef58b1 SH |
2665 | } |
2666 | ||
7c442fa1 | 2667 | /* Free all buffers in Tx ring which are no longer owned by device */ |
513f533e | 2668 | static void skge_tx_done(struct net_device *dev) |
00a6cae2 | 2669 | { |
7c442fa1 | 2670 | struct skge_port *skge = netdev_priv(dev); |
00a6cae2 | 2671 | struct skge_ring *ring = &skge->tx_ring; |
7c442fa1 SH |
2672 | struct skge_element *e; |
2673 | ||
513f533e | 2674 | skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); |
00a6cae2 | 2675 | |
513f533e | 2676 | netif_tx_lock(dev); |
866b4f3e | 2677 | for (e = ring->to_clean; e != ring->to_use; e = e->next) { |
00a6cae2 | 2678 | struct skge_tx_desc *td = e->desc; |
00a6cae2 | 2679 | |
866b4f3e | 2680 | if (td->control & BMU_OWN) |
00a6cae2 SH |
2681 | break; |
2682 | ||
7c442fa1 | 2683 | skge_tx_free(skge, e, td->control); |
00a6cae2 | 2684 | } |
7c442fa1 | 2685 | skge->tx_ring.to_clean = e; |
866b4f3e | 2686 | |
513f533e SH |
2687 | if (skge_avail(&skge->tx_ring) > TX_LOW_WATER) |
2688 | netif_wake_queue(dev); | |
00a6cae2 | 2689 | |
513f533e | 2690 | netif_tx_unlock(dev); |
00a6cae2 | 2691 | } |
19a33d4e | 2692 | |
baef58b1 SH |
2693 | static int skge_poll(struct net_device *dev, int *budget) |
2694 | { | |
2695 | struct skge_port *skge = netdev_priv(dev); | |
2696 | struct skge_hw *hw = skge->hw; | |
2697 | struct skge_ring *ring = &skge->rx_ring; | |
2698 | struct skge_element *e; | |
00a6cae2 SH |
2699 | int to_do = min(dev->quota, *budget); |
2700 | int work_done = 0; | |
2701 | ||
513f533e SH |
2702 | skge_tx_done(dev); |
2703 | ||
2704 | skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); | |
2705 | ||
1631aef1 | 2706 | for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) { |
baef58b1 | 2707 | struct skge_rx_desc *rd = e->desc; |
19a33d4e | 2708 | struct sk_buff *skb; |
383181ac | 2709 | u32 control; |
baef58b1 SH |
2710 | |
2711 | rmb(); | |
2712 | control = rd->control; | |
2713 | if (control & BMU_OWN) | |
2714 | break; | |
2715 | ||
c54f9765 | 2716 | skb = skge_rx_get(dev, e, control, rd->status, rd->csum2); |
19a33d4e | 2717 | if (likely(skb)) { |
19a33d4e SH |
2718 | dev->last_rx = jiffies; |
2719 | netif_receive_skb(skb); | |
baef58b1 | 2720 | |
19a33d4e | 2721 | ++work_done; |
5a011447 | 2722 | } |
baef58b1 SH |
2723 | } |
2724 | ring->to_clean = e; | |
2725 | ||
baef58b1 SH |
2726 | /* restart receiver */ |
2727 | wmb(); | |
a9cdab86 | 2728 | skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); |
baef58b1 | 2729 | |
19a33d4e SH |
2730 | *budget -= work_done; |
2731 | dev->quota -= work_done; | |
2732 | ||
2733 | if (work_done >= to_do) | |
2734 | return 1; /* not done */ | |
baef58b1 | 2735 | |
7c442fa1 | 2736 | spin_lock_irq(&hw->hw_lock); |
513f533e SH |
2737 | __netif_rx_complete(dev); |
2738 | hw->intr_mask |= irqmask[skge->port]; | |
80dd857d | 2739 | skge_write32(hw, B0_IMSK, hw->intr_mask); |
78bc2186 | 2740 | skge_read32(hw, B0_IMSK); |
7c442fa1 | 2741 | spin_unlock_irq(&hw->hw_lock); |
1631aef1 | 2742 | |
19a33d4e | 2743 | return 0; |
baef58b1 SH |
2744 | } |
2745 | ||
f6620cab SH |
2746 | /* Parity errors seem to happen when Genesis is connected to a switch |
2747 | * with no other ports present. Heartbeat error?? | |
2748 | */ | |
baef58b1 SH |
2749 | static void skge_mac_parity(struct skge_hw *hw, int port) |
2750 | { | |
f6620cab SH |
2751 | struct net_device *dev = hw->dev[port]; |
2752 | ||
2753 | if (dev) { | |
2754 | struct skge_port *skge = netdev_priv(dev); | |
2755 | ++skge->net_stats.tx_heartbeat_errors; | |
2756 | } | |
baef58b1 SH |
2757 | |
2758 | if (hw->chip_id == CHIP_ID_GENESIS) | |
6b0c1480 | 2759 | skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), |
baef58b1 SH |
2760 | MFF_CLR_PERR); |
2761 | else | |
2762 | /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */ | |
6b0c1480 | 2763 | skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), |
981d0377 | 2764 | (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0) |
baef58b1 SH |
2765 | ? GMF_CLI_TX_FC : GMF_CLI_TX_PE); |
2766 | } | |
2767 | ||
baef58b1 SH |
2768 | static void skge_mac_intr(struct skge_hw *hw, int port) |
2769 | { | |
95566065 | 2770 | if (hw->chip_id == CHIP_ID_GENESIS) |
baef58b1 SH |
2771 | genesis_mac_intr(hw, port); |
2772 | else | |
2773 | yukon_mac_intr(hw, port); | |
2774 | } | |
2775 | ||
2776 | /* Handle device specific framing and timeout interrupts */ | |
2777 | static void skge_error_irq(struct skge_hw *hw) | |
2778 | { | |
2779 | u32 hwstatus = skge_read32(hw, B0_HWE_ISRC); | |
2780 | ||
2781 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
2782 | /* clear xmac errors */ | |
2783 | if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1)) | |
46a60f2d | 2784 | skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT); |
baef58b1 | 2785 | if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2)) |
46a60f2d | 2786 | skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT); |
baef58b1 SH |
2787 | } else { |
2788 | /* Timestamp (unused) overflow */ | |
2789 | if (hwstatus & IS_IRQ_TIST_OV) | |
2790 | skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); | |
baef58b1 SH |
2791 | } |
2792 | ||
2793 | if (hwstatus & IS_RAM_RD_PAR) { | |
2794 | printk(KERN_ERR PFX "Ram read data parity error\n"); | |
2795 | skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR); | |
2796 | } | |
2797 | ||
2798 | if (hwstatus & IS_RAM_WR_PAR) { | |
2799 | printk(KERN_ERR PFX "Ram write data parity error\n"); | |
2800 | skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR); | |
2801 | } | |
2802 | ||
2803 | if (hwstatus & IS_M1_PAR_ERR) | |
2804 | skge_mac_parity(hw, 0); | |
2805 | ||
2806 | if (hwstatus & IS_M2_PAR_ERR) | |
2807 | skge_mac_parity(hw, 1); | |
2808 | ||
b9d64acc SH |
2809 | if (hwstatus & IS_R1_PAR_ERR) { |
2810 | printk(KERN_ERR PFX "%s: receive queue parity error\n", | |
2811 | hw->dev[0]->name); | |
baef58b1 | 2812 | skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P); |
b9d64acc | 2813 | } |
baef58b1 | 2814 | |
b9d64acc SH |
2815 | if (hwstatus & IS_R2_PAR_ERR) { |
2816 | printk(KERN_ERR PFX "%s: receive queue parity error\n", | |
2817 | hw->dev[1]->name); | |
baef58b1 | 2818 | skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); |
b9d64acc | 2819 | } |
baef58b1 SH |
2820 | |
2821 | if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) { | |
b9d64acc SH |
2822 | u16 pci_status, pci_cmd; |
2823 | ||
2824 | pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd); | |
2825 | pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); | |
baef58b1 | 2826 | |
b9d64acc SH |
2827 | printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n", |
2828 | pci_name(hw->pdev), pci_cmd, pci_status); | |
2829 | ||
2830 | /* Write the error bits back to clear them. */ | |
2831 | pci_status &= PCI_STATUS_ERROR_BITS; | |
2832 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
2833 | pci_write_config_word(hw->pdev, PCI_COMMAND, | |
2834 | pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY); | |
2835 | pci_write_config_word(hw->pdev, PCI_STATUS, pci_status); | |
2836 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
baef58b1 | 2837 | |
050ec18a | 2838 | /* if error still set then just ignore it */ |
baef58b1 SH |
2839 | hwstatus = skge_read32(hw, B0_HWE_ISRC); |
2840 | if (hwstatus & IS_IRQ_STAT) { | |
b9d64acc | 2841 | printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n"); |
baef58b1 SH |
2842 | hw->intr_mask &= ~IS_HW_ERR; |
2843 | } | |
2844 | } | |
2845 | } | |
2846 | ||
2847 | /* | |
d85b514f | 2848 | * Interrupt from PHY are handled in work queue |
baef58b1 SH |
2849 | * because accessing phy registers requires spin wait which might |
2850 | * cause excess interrupt latency. | |
2851 | */ | |
d85b514f | 2852 | static void skge_extirq(void *arg) |
baef58b1 | 2853 | { |
d85b514f | 2854 | struct skge_hw *hw = arg; |
baef58b1 SH |
2855 | int port; |
2856 | ||
d85b514f | 2857 | mutex_lock(&hw->phy_mutex); |
cfc3ed79 | 2858 | for (port = 0; port < hw->ports; port++) { |
baef58b1 | 2859 | struct net_device *dev = hw->dev[port]; |
cfc3ed79 | 2860 | struct skge_port *skge = netdev_priv(dev); |
baef58b1 | 2861 | |
cfc3ed79 | 2862 | if (netif_running(dev)) { |
baef58b1 SH |
2863 | if (hw->chip_id != CHIP_ID_GENESIS) |
2864 | yukon_phy_intr(skge); | |
89bf5f23 | 2865 | else |
45bada65 | 2866 | bcom_phy_intr(skge); |
baef58b1 SH |
2867 | } |
2868 | } | |
d85b514f | 2869 | mutex_unlock(&hw->phy_mutex); |
baef58b1 | 2870 | |
7c442fa1 | 2871 | spin_lock_irq(&hw->hw_lock); |
baef58b1 SH |
2872 | hw->intr_mask |= IS_EXT_REG; |
2873 | skge_write32(hw, B0_IMSK, hw->intr_mask); | |
78bc2186 | 2874 | skge_read32(hw, B0_IMSK); |
7c442fa1 | 2875 | spin_unlock_irq(&hw->hw_lock); |
baef58b1 SH |
2876 | } |
2877 | ||
2878 | static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs) | |
2879 | { | |
2880 | struct skge_hw *hw = dev_id; | |
cfc3ed79 | 2881 | u32 status; |
29365c90 | 2882 | int handled = 0; |
baef58b1 | 2883 | |
29365c90 | 2884 | spin_lock(&hw->hw_lock); |
cfc3ed79 SH |
2885 | /* Reading this register masks IRQ */ |
2886 | status = skge_read32(hw, B0_SP_ISRC); | |
2887 | if (status == 0) | |
29365c90 | 2888 | goto out; |
baef58b1 | 2889 | |
29365c90 | 2890 | handled = 1; |
7c442fa1 | 2891 | status &= hw->intr_mask; |
cfc3ed79 SH |
2892 | if (status & IS_EXT_REG) { |
2893 | hw->intr_mask &= ~IS_EXT_REG; | |
d85b514f | 2894 | schedule_work(&hw->phy_work); |
cfc3ed79 SH |
2895 | } |
2896 | ||
513f533e SH |
2897 | if (status & (IS_XA1_F|IS_R1_F)) { |
2898 | hw->intr_mask &= ~(IS_XA1_F|IS_R1_F); | |
7c442fa1 | 2899 | netif_rx_schedule(hw->dev[0]); |
baef58b1 SH |
2900 | } |
2901 | ||
7c442fa1 SH |
2902 | if (status & IS_PA_TO_TX1) |
2903 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1); | |
cfc3ed79 | 2904 | |
d25f5a67 SH |
2905 | if (status & IS_PA_TO_RX1) { |
2906 | struct skge_port *skge = netdev_priv(hw->dev[0]); | |
d25f5a67 | 2907 | |
d25f5a67 | 2908 | ++skge->net_stats.rx_over_errors; |
7c442fa1 | 2909 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1); |
d25f5a67 SH |
2910 | } |
2911 | ||
d25f5a67 | 2912 | |
baef58b1 SH |
2913 | if (status & IS_MAC1) |
2914 | skge_mac_intr(hw, 0); | |
95566065 | 2915 | |
7c442fa1 | 2916 | if (hw->dev[1]) { |
513f533e SH |
2917 | if (status & (IS_XA2_F|IS_R2_F)) { |
2918 | hw->intr_mask &= ~(IS_XA2_F|IS_R2_F); | |
7c442fa1 SH |
2919 | netif_rx_schedule(hw->dev[1]); |
2920 | } | |
2921 | ||
2922 | if (status & IS_PA_TO_RX2) { | |
2923 | struct skge_port *skge = netdev_priv(hw->dev[1]); | |
2924 | ++skge->net_stats.rx_over_errors; | |
2925 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2); | |
2926 | } | |
2927 | ||
2928 | if (status & IS_PA_TO_TX2) | |
2929 | skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2); | |
2930 | ||
2931 | if (status & IS_MAC2) | |
2932 | skge_mac_intr(hw, 1); | |
2933 | } | |
baef58b1 SH |
2934 | |
2935 | if (status & IS_HW_ERR) | |
2936 | skge_error_irq(hw); | |
2937 | ||
7e676d91 | 2938 | skge_write32(hw, B0_IMSK, hw->intr_mask); |
78bc2186 | 2939 | skge_read32(hw, B0_IMSK); |
29365c90 | 2940 | out: |
7c442fa1 | 2941 | spin_unlock(&hw->hw_lock); |
baef58b1 | 2942 | |
29365c90 | 2943 | return IRQ_RETVAL(handled); |
baef58b1 SH |
2944 | } |
2945 | ||
2946 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2947 | static void skge_netpoll(struct net_device *dev) | |
2948 | { | |
2949 | struct skge_port *skge = netdev_priv(dev); | |
2950 | ||
2951 | disable_irq(dev->irq); | |
2952 | skge_intr(dev->irq, skge->hw, NULL); | |
2953 | enable_irq(dev->irq); | |
2954 | } | |
2955 | #endif | |
2956 | ||
2957 | static int skge_set_mac_address(struct net_device *dev, void *p) | |
2958 | { | |
2959 | struct skge_port *skge = netdev_priv(dev); | |
c2681dd8 SH |
2960 | struct skge_hw *hw = skge->hw; |
2961 | unsigned port = skge->port; | |
2962 | const struct sockaddr *addr = p; | |
baef58b1 SH |
2963 | |
2964 | if (!is_valid_ether_addr(addr->sa_data)) | |
2965 | return -EADDRNOTAVAIL; | |
2966 | ||
d85b514f | 2967 | mutex_lock(&hw->phy_mutex); |
baef58b1 | 2968 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
c2681dd8 | 2969 | memcpy_toio(hw->regs + B2_MAC_1 + port*8, |
baef58b1 | 2970 | dev->dev_addr, ETH_ALEN); |
c2681dd8 | 2971 | memcpy_toio(hw->regs + B2_MAC_2 + port*8, |
baef58b1 | 2972 | dev->dev_addr, ETH_ALEN); |
c2681dd8 SH |
2973 | |
2974 | if (hw->chip_id == CHIP_ID_GENESIS) | |
2975 | xm_outaddr(hw, port, XM_SA, dev->dev_addr); | |
2976 | else { | |
2977 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
2978 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
2979 | } | |
d85b514f | 2980 | mutex_unlock(&hw->phy_mutex); |
c2681dd8 SH |
2981 | |
2982 | return 0; | |
baef58b1 SH |
2983 | } |
2984 | ||
2985 | static const struct { | |
2986 | u8 id; | |
2987 | const char *name; | |
2988 | } skge_chips[] = { | |
2989 | { CHIP_ID_GENESIS, "Genesis" }, | |
2990 | { CHIP_ID_YUKON, "Yukon" }, | |
2991 | { CHIP_ID_YUKON_LITE, "Yukon-Lite"}, | |
2992 | { CHIP_ID_YUKON_LP, "Yukon-LP"}, | |
baef58b1 SH |
2993 | }; |
2994 | ||
2995 | static const char *skge_board_name(const struct skge_hw *hw) | |
2996 | { | |
2997 | int i; | |
2998 | static char buf[16]; | |
2999 | ||
3000 | for (i = 0; i < ARRAY_SIZE(skge_chips); i++) | |
3001 | if (skge_chips[i].id == hw->chip_id) | |
3002 | return skge_chips[i].name; | |
3003 | ||
3004 | snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id); | |
3005 | return buf; | |
3006 | } | |
3007 | ||
3008 | ||
3009 | /* | |
3010 | * Setup the board data structure, but don't bring up | |
3011 | * the port(s) | |
3012 | */ | |
3013 | static int skge_reset(struct skge_hw *hw) | |
3014 | { | |
adba9e23 | 3015 | u32 reg; |
b9d64acc | 3016 | u16 ctst, pci_status; |
5e1705dd | 3017 | u8 t8, mac_cfg, pmd_type, phy_type; |
981d0377 | 3018 | int i; |
baef58b1 SH |
3019 | |
3020 | ctst = skge_read16(hw, B0_CTST); | |
3021 | ||
3022 | /* do a SW reset */ | |
3023 | skge_write8(hw, B0_CTST, CS_RST_SET); | |
3024 | skge_write8(hw, B0_CTST, CS_RST_CLR); | |
3025 | ||
3026 | /* clear PCI errors, if any */ | |
b9d64acc SH |
3027 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
3028 | skge_write8(hw, B2_TST_CTRL2, 0); | |
baef58b1 | 3029 | |
b9d64acc SH |
3030 | pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status); |
3031 | pci_write_config_word(hw->pdev, PCI_STATUS, | |
3032 | pci_status | PCI_STATUS_ERROR_BITS); | |
3033 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
baef58b1 SH |
3034 | skge_write8(hw, B0_CTST, CS_MRST_CLR); |
3035 | ||
3036 | /* restore CLK_RUN bits (for Yukon-Lite) */ | |
3037 | skge_write16(hw, B0_CTST, | |
3038 | ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA)); | |
3039 | ||
3040 | hw->chip_id = skge_read8(hw, B2_CHIP_ID); | |
5e1705dd SH |
3041 | phy_type = skge_read8(hw, B2_E_1) & 0xf; |
3042 | pmd_type = skge_read8(hw, B2_PMD_TYP); | |
3043 | hw->copper = (pmd_type == 'T' || pmd_type == '1'); | |
baef58b1 | 3044 | |
95566065 | 3045 | switch (hw->chip_id) { |
baef58b1 | 3046 | case CHIP_ID_GENESIS: |
5e1705dd | 3047 | switch (phy_type) { |
baef58b1 SH |
3048 | case SK_PHY_BCOM: |
3049 | hw->phy_addr = PHY_ADDR_BCOM; | |
3050 | break; | |
3051 | default: | |
3052 | printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n", | |
5e1705dd | 3053 | pci_name(hw->pdev), phy_type); |
baef58b1 SH |
3054 | return -EOPNOTSUPP; |
3055 | } | |
3056 | break; | |
3057 | ||
3058 | case CHIP_ID_YUKON: | |
3059 | case CHIP_ID_YUKON_LITE: | |
3060 | case CHIP_ID_YUKON_LP: | |
5e1705dd SH |
3061 | if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S') |
3062 | hw->copper = 1; | |
baef58b1 SH |
3063 | |
3064 | hw->phy_addr = PHY_ADDR_MARV; | |
baef58b1 SH |
3065 | break; |
3066 | ||
3067 | default: | |
3068 | printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", | |
3069 | pci_name(hw->pdev), hw->chip_id); | |
3070 | return -EOPNOTSUPP; | |
3071 | } | |
3072 | ||
981d0377 SH |
3073 | mac_cfg = skge_read8(hw, B2_MAC_CFG); |
3074 | hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2; | |
3075 | hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4; | |
baef58b1 SH |
3076 | |
3077 | /* read the adapters RAM size */ | |
3078 | t8 = skge_read8(hw, B2_E_0); | |
3079 | if (hw->chip_id == CHIP_ID_GENESIS) { | |
3080 | if (t8 == 3) { | |
3081 | /* special case: 4 x 64k x 36, offset = 0x80000 */ | |
3082 | hw->ram_size = 0x100000; | |
3083 | hw->ram_offset = 0x80000; | |
3084 | } else | |
3085 | hw->ram_size = t8 * 512; | |
3086 | } | |
3087 | else if (t8 == 0) | |
3088 | hw->ram_size = 0x20000; | |
3089 | else | |
3090 | hw->ram_size = t8 * 4096; | |
3091 | ||
cfc3ed79 SH |
3092 | hw->intr_mask = IS_HW_ERR | IS_EXT_REG | IS_PORT_1; |
3093 | if (hw->ports > 1) | |
3094 | hw->intr_mask |= IS_PORT_2; | |
3095 | ||
baef58b1 SH |
3096 | if (hw->chip_id == CHIP_ID_GENESIS) |
3097 | genesis_init(hw); | |
3098 | else { | |
3099 | /* switch power to VCC (WA for VAUX problem) */ | |
3100 | skge_write8(hw, B0_POWER_CTRL, | |
3101 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
adba9e23 | 3102 | |
050ec18a SH |
3103 | /* avoid boards with stuck Hardware error bits */ |
3104 | if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) && | |
3105 | (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) { | |
3106 | printk(KERN_WARNING PFX "stuck hardware sensor bit\n"); | |
3107 | hw->intr_mask &= ~IS_HW_ERR; | |
3108 | } | |
3109 | ||
adba9e23 SH |
3110 | /* Clear PHY COMA */ |
3111 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
3112 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®); | |
3113 | reg &= ~PCI_PHY_COMA; | |
3114 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg); | |
3115 | skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
3116 | ||
3117 | ||
981d0377 | 3118 | for (i = 0; i < hw->ports; i++) { |
6b0c1480 SH |
3119 | skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); |
3120 | skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
baef58b1 SH |
3121 | } |
3122 | } | |
3123 | ||
3124 | /* turn off hardware timer (unused) */ | |
3125 | skge_write8(hw, B2_TI_CTRL, TIM_STOP); | |
3126 | skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
3127 | skge_write8(hw, B0_LED, LED_STAT_ON); | |
3128 | ||
3129 | /* enable the Tx Arbiters */ | |
981d0377 | 3130 | for (i = 0; i < hw->ports; i++) |
6b0c1480 | 3131 | skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); |
baef58b1 SH |
3132 | |
3133 | /* Initialize ram interface */ | |
3134 | skge_write16(hw, B3_RI_CTRL, RI_RST_CLR); | |
3135 | ||
3136 | skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53); | |
3137 | skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53); | |
3138 | skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53); | |
3139 | skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53); | |
3140 | skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53); | |
3141 | skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53); | |
3142 | skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53); | |
3143 | skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53); | |
3144 | skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53); | |
3145 | skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53); | |
3146 | skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53); | |
3147 | skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53); | |
3148 | ||
3149 | skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK); | |
3150 | ||
3151 | /* Set interrupt moderation for Transmit only | |
3152 | * Receive interrupts avoided by NAPI | |
3153 | */ | |
3154 | skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F); | |
3155 | skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100)); | |
3156 | skge_write32(hw, B2_IRQM_CTRL, TIM_START); | |
3157 | ||
baef58b1 SH |
3158 | skge_write32(hw, B0_IMSK, hw->intr_mask); |
3159 | ||
d85b514f | 3160 | mutex_lock(&hw->phy_mutex); |
981d0377 | 3161 | for (i = 0; i < hw->ports; i++) { |
baef58b1 SH |
3162 | if (hw->chip_id == CHIP_ID_GENESIS) |
3163 | genesis_reset(hw, i); | |
3164 | else | |
3165 | yukon_reset(hw, i); | |
3166 | } | |
d85b514f | 3167 | mutex_unlock(&hw->phy_mutex); |
baef58b1 SH |
3168 | |
3169 | return 0; | |
3170 | } | |
3171 | ||
3172 | /* Initialize network device */ | |
981d0377 SH |
3173 | static struct net_device *skge_devinit(struct skge_hw *hw, int port, |
3174 | int highmem) | |
baef58b1 SH |
3175 | { |
3176 | struct skge_port *skge; | |
3177 | struct net_device *dev = alloc_etherdev(sizeof(*skge)); | |
3178 | ||
3179 | if (!dev) { | |
3180 | printk(KERN_ERR "skge etherdev alloc failed"); | |
3181 | return NULL; | |
3182 | } | |
3183 | ||
3184 | SET_MODULE_OWNER(dev); | |
3185 | SET_NETDEV_DEV(dev, &hw->pdev->dev); | |
3186 | dev->open = skge_up; | |
3187 | dev->stop = skge_down; | |
2cd8e5d3 | 3188 | dev->do_ioctl = skge_ioctl; |
baef58b1 SH |
3189 | dev->hard_start_xmit = skge_xmit_frame; |
3190 | dev->get_stats = skge_get_stats; | |
3191 | if (hw->chip_id == CHIP_ID_GENESIS) | |
3192 | dev->set_multicast_list = genesis_set_multicast; | |
3193 | else | |
3194 | dev->set_multicast_list = yukon_set_multicast; | |
3195 | ||
3196 | dev->set_mac_address = skge_set_mac_address; | |
3197 | dev->change_mtu = skge_change_mtu; | |
3198 | SET_ETHTOOL_OPS(dev, &skge_ethtool_ops); | |
3199 | dev->tx_timeout = skge_tx_timeout; | |
3200 | dev->watchdog_timeo = TX_WATCHDOG; | |
3201 | dev->poll = skge_poll; | |
3202 | dev->weight = NAPI_WEIGHT; | |
3203 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3204 | dev->poll_controller = skge_netpoll; | |
3205 | #endif | |
3206 | dev->irq = hw->pdev->irq; | |
513f533e | 3207 | |
981d0377 SH |
3208 | if (highmem) |
3209 | dev->features |= NETIF_F_HIGHDMA; | |
baef58b1 SH |
3210 | |
3211 | skge = netdev_priv(dev); | |
3212 | skge->netdev = dev; | |
3213 | skge->hw = hw; | |
3214 | skge->msg_enable = netif_msg_init(debug, default_msg); | |
3215 | skge->tx_ring.count = DEFAULT_TX_RING_SIZE; | |
3216 | skge->rx_ring.count = DEFAULT_RX_RING_SIZE; | |
3217 | ||
3218 | /* Auto speed and flow control */ | |
3219 | skge->autoneg = AUTONEG_ENABLE; | |
3220 | skge->flow_control = FLOW_MODE_SYMMETRIC; | |
3221 | skge->duplex = -1; | |
3222 | skge->speed = -1; | |
31b619c5 | 3223 | skge->advertising = skge_supported_modes(hw); |
baef58b1 SH |
3224 | |
3225 | hw->dev[port] = dev; | |
3226 | ||
3227 | skge->port = port; | |
3228 | ||
baef58b1 SH |
3229 | if (hw->chip_id != CHIP_ID_GENESIS) { |
3230 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; | |
3231 | skge->rx_csum = 1; | |
3232 | } | |
3233 | ||
3234 | /* read the mac address */ | |
3235 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN); | |
56230d53 | 3236 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
baef58b1 SH |
3237 | |
3238 | /* device is off until link detection */ | |
3239 | netif_carrier_off(dev); | |
3240 | netif_stop_queue(dev); | |
3241 | ||
3242 | return dev; | |
3243 | } | |
3244 | ||
3245 | static void __devinit skge_show_addr(struct net_device *dev) | |
3246 | { | |
3247 | const struct skge_port *skge = netdev_priv(dev); | |
3248 | ||
3249 | if (netif_msg_probe(skge)) | |
3250 | printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
3251 | dev->name, | |
3252 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
3253 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
3254 | } | |
3255 | ||
3256 | static int __devinit skge_probe(struct pci_dev *pdev, | |
3257 | const struct pci_device_id *ent) | |
3258 | { | |
3259 | struct net_device *dev, *dev1; | |
3260 | struct skge_hw *hw; | |
3261 | int err, using_dac = 0; | |
3262 | ||
203babb6 SH |
3263 | err = pci_enable_device(pdev); |
3264 | if (err) { | |
baef58b1 SH |
3265 | printk(KERN_ERR PFX "%s cannot enable PCI device\n", |
3266 | pci_name(pdev)); | |
3267 | goto err_out; | |
3268 | } | |
3269 | ||
203babb6 SH |
3270 | err = pci_request_regions(pdev, DRV_NAME); |
3271 | if (err) { | |
baef58b1 SH |
3272 | printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", |
3273 | pci_name(pdev)); | |
3274 | goto err_out_disable_pdev; | |
3275 | } | |
3276 | ||
3277 | pci_set_master(pdev); | |
3278 | ||
93aea718 | 3279 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
baef58b1 | 3280 | using_dac = 1; |
77783a78 | 3281 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); |
93aea718 SH |
3282 | } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) { |
3283 | using_dac = 0; | |
3284 | err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
3285 | } | |
3286 | ||
3287 | if (err) { | |
3288 | printk(KERN_ERR PFX "%s no usable DMA configuration\n", | |
3289 | pci_name(pdev)); | |
3290 | goto err_out_free_regions; | |
baef58b1 SH |
3291 | } |
3292 | ||
3293 | #ifdef __BIG_ENDIAN | |
8f3f8193 | 3294 | /* byte swap descriptors in hardware */ |
baef58b1 SH |
3295 | { |
3296 | u32 reg; | |
3297 | ||
3298 | pci_read_config_dword(pdev, PCI_DEV_REG2, ®); | |
3299 | reg |= PCI_REV_DESC; | |
3300 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | |
3301 | } | |
3302 | #endif | |
3303 | ||
3304 | err = -ENOMEM; | |
7e863061 | 3305 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
baef58b1 SH |
3306 | if (!hw) { |
3307 | printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", | |
3308 | pci_name(pdev)); | |
3309 | goto err_out_free_regions; | |
3310 | } | |
3311 | ||
baef58b1 | 3312 | hw->pdev = pdev; |
d85b514f SH |
3313 | mutex_init(&hw->phy_mutex); |
3314 | INIT_WORK(&hw->phy_work, skge_extirq, hw); | |
d38efdd6 | 3315 | spin_lock_init(&hw->hw_lock); |
baef58b1 SH |
3316 | |
3317 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
3318 | if (!hw->regs) { | |
3319 | printk(KERN_ERR PFX "%s: cannot map device registers\n", | |
3320 | pci_name(pdev)); | |
3321 | goto err_out_free_hw; | |
3322 | } | |
3323 | ||
baef58b1 SH |
3324 | err = skge_reset(hw); |
3325 | if (err) | |
ccdaa2a9 | 3326 | goto err_out_iounmap; |
baef58b1 | 3327 | |
7c7459d1 GKH |
3328 | printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n", |
3329 | (unsigned long long)pci_resource_start(pdev, 0), pdev->irq, | |
981d0377 | 3330 | skge_board_name(hw), hw->chip_rev); |
baef58b1 | 3331 | |
ccdaa2a9 SH |
3332 | dev = skge_devinit(hw, 0, using_dac); |
3333 | if (!dev) | |
baef58b1 SH |
3334 | goto err_out_led_off; |
3335 | ||
631ae320 SH |
3336 | if (!is_valid_ether_addr(dev->dev_addr)) { |
3337 | printk(KERN_ERR PFX "%s: bad (zero?) ethernet address in rom\n", | |
3338 | pci_name(pdev)); | |
3339 | err = -EIO; | |
3340 | goto err_out_free_netdev; | |
3341 | } | |
3342 | ||
203babb6 SH |
3343 | err = register_netdev(dev); |
3344 | if (err) { | |
baef58b1 SH |
3345 | printk(KERN_ERR PFX "%s: cannot register net device\n", |
3346 | pci_name(pdev)); | |
3347 | goto err_out_free_netdev; | |
3348 | } | |
3349 | ||
ccdaa2a9 SH |
3350 | err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw); |
3351 | if (err) { | |
3352 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3353 | dev->name, pdev->irq); | |
3354 | goto err_out_unregister; | |
3355 | } | |
baef58b1 SH |
3356 | skge_show_addr(dev); |
3357 | ||
981d0377 | 3358 | if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) { |
baef58b1 SH |
3359 | if (register_netdev(dev1) == 0) |
3360 | skge_show_addr(dev1); | |
3361 | else { | |
3362 | /* Failure to register second port need not be fatal */ | |
3363 | printk(KERN_WARNING PFX "register of second port failed\n"); | |
3364 | hw->dev[1] = NULL; | |
3365 | free_netdev(dev1); | |
3366 | } | |
3367 | } | |
ccdaa2a9 | 3368 | pci_set_drvdata(pdev, hw); |
baef58b1 SH |
3369 | |
3370 | return 0; | |
3371 | ||
ccdaa2a9 SH |
3372 | err_out_unregister: |
3373 | unregister_netdev(dev); | |
baef58b1 SH |
3374 | err_out_free_netdev: |
3375 | free_netdev(dev); | |
3376 | err_out_led_off: | |
3377 | skge_write16(hw, B0_LED, LED_STAT_OFF); | |
baef58b1 SH |
3378 | err_out_iounmap: |
3379 | iounmap(hw->regs); | |
3380 | err_out_free_hw: | |
3381 | kfree(hw); | |
3382 | err_out_free_regions: | |
3383 | pci_release_regions(pdev); | |
3384 | err_out_disable_pdev: | |
3385 | pci_disable_device(pdev); | |
3386 | pci_set_drvdata(pdev, NULL); | |
3387 | err_out: | |
3388 | return err; | |
3389 | } | |
3390 | ||
3391 | static void __devexit skge_remove(struct pci_dev *pdev) | |
3392 | { | |
3393 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
3394 | struct net_device *dev0, *dev1; | |
3395 | ||
95566065 | 3396 | if (!hw) |
baef58b1 SH |
3397 | return; |
3398 | ||
3399 | if ((dev1 = hw->dev[1])) | |
3400 | unregister_netdev(dev1); | |
3401 | dev0 = hw->dev[0]; | |
3402 | unregister_netdev(dev0); | |
3403 | ||
7c442fa1 SH |
3404 | spin_lock_irq(&hw->hw_lock); |
3405 | hw->intr_mask = 0; | |
46a60f2d | 3406 | skge_write32(hw, B0_IMSK, 0); |
78bc2186 | 3407 | skge_read32(hw, B0_IMSK); |
7c442fa1 SH |
3408 | spin_unlock_irq(&hw->hw_lock); |
3409 | ||
46a60f2d | 3410 | skge_write16(hw, B0_LED, LED_STAT_OFF); |
46a60f2d SH |
3411 | skge_write8(hw, B0_CTST, CS_RST_SET); |
3412 | ||
d85b514f | 3413 | flush_scheduled_work(); |
baef58b1 SH |
3414 | |
3415 | free_irq(pdev->irq, hw); | |
3416 | pci_release_regions(pdev); | |
3417 | pci_disable_device(pdev); | |
3418 | if (dev1) | |
3419 | free_netdev(dev1); | |
3420 | free_netdev(dev0); | |
46a60f2d | 3421 | |
baef58b1 SH |
3422 | iounmap(hw->regs); |
3423 | kfree(hw); | |
3424 | pci_set_drvdata(pdev, NULL); | |
3425 | } | |
3426 | ||
3427 | #ifdef CONFIG_PM | |
2a569579 | 3428 | static int skge_suspend(struct pci_dev *pdev, pm_message_t state) |
baef58b1 SH |
3429 | { |
3430 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
3431 | int i, wol = 0; | |
3432 | ||
d38efdd6 SH |
3433 | pci_save_state(pdev); |
3434 | for (i = 0; i < hw->ports; i++) { | |
baef58b1 SH |
3435 | struct net_device *dev = hw->dev[i]; |
3436 | ||
d38efdd6 | 3437 | if (netif_running(dev)) { |
baef58b1 | 3438 | struct skge_port *skge = netdev_priv(dev); |
d38efdd6 SH |
3439 | |
3440 | netif_carrier_off(dev); | |
3441 | if (skge->wol) | |
3442 | netif_stop_queue(dev); | |
3443 | else | |
3444 | skge_down(dev); | |
baef58b1 SH |
3445 | wol |= skge->wol; |
3446 | } | |
d38efdd6 | 3447 | netif_device_detach(dev); |
baef58b1 SH |
3448 | } |
3449 | ||
d38efdd6 | 3450 | skge_write32(hw, B0_IMSK, 0); |
2a569579 | 3451 | pci_enable_wake(pdev, pci_choose_state(pdev, state), wol); |
baef58b1 SH |
3452 | pci_set_power_state(pdev, pci_choose_state(pdev, state)); |
3453 | ||
3454 | return 0; | |
3455 | } | |
3456 | ||
3457 | static int skge_resume(struct pci_dev *pdev) | |
3458 | { | |
3459 | struct skge_hw *hw = pci_get_drvdata(pdev); | |
d38efdd6 | 3460 | int i, err; |
baef58b1 SH |
3461 | |
3462 | pci_set_power_state(pdev, PCI_D0); | |
3463 | pci_restore_state(pdev); | |
3464 | pci_enable_wake(pdev, PCI_D0, 0); | |
3465 | ||
d38efdd6 SH |
3466 | err = skge_reset(hw); |
3467 | if (err) | |
3468 | goto out; | |
baef58b1 | 3469 | |
d38efdd6 | 3470 | for (i = 0; i < hw->ports; i++) { |
baef58b1 | 3471 | struct net_device *dev = hw->dev[i]; |
d38efdd6 SH |
3472 | |
3473 | netif_device_attach(dev); | |
3474 | if (netif_running(dev)) { | |
3475 | err = skge_up(dev); | |
3476 | ||
3477 | if (err) { | |
3478 | printk(KERN_ERR PFX "%s: could not up: %d\n", | |
3479 | dev->name, err); | |
edd702e8 | 3480 | dev_close(dev); |
d38efdd6 SH |
3481 | goto out; |
3482 | } | |
baef58b1 SH |
3483 | } |
3484 | } | |
d38efdd6 SH |
3485 | out: |
3486 | return err; | |
baef58b1 SH |
3487 | } |
3488 | #endif | |
3489 | ||
3490 | static struct pci_driver skge_driver = { | |
3491 | .name = DRV_NAME, | |
3492 | .id_table = skge_id_table, | |
3493 | .probe = skge_probe, | |
3494 | .remove = __devexit_p(skge_remove), | |
3495 | #ifdef CONFIG_PM | |
3496 | .suspend = skge_suspend, | |
3497 | .resume = skge_resume, | |
3498 | #endif | |
3499 | }; | |
3500 | ||
3501 | static int __init skge_init_module(void) | |
3502 | { | |
29917620 | 3503 | return pci_register_driver(&skge_driver); |
baef58b1 SH |
3504 | } |
3505 | ||
3506 | static void __exit skge_cleanup_module(void) | |
3507 | { | |
3508 | pci_unregister_driver(&skge_driver); | |
3509 | } | |
3510 | ||
3511 | module_init(skge_init_module); | |
3512 | module_exit(skge_cleanup_module); |