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[mirror_ubuntu-zesty-kernel.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
14c85021 26#include <linux/in.h>
baef58b1
SH		 27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/if_vlan.h>
35#include <linux/ip.h>
36#include <linux/delay.h>
37#include <linux/crc32.h>
4075400b 38#include <linux/dma-mapping.h>
2cd8e5d3 39#include <linux/mii.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
370de6cd 45#define DRV_VERSION "1.9"
baef58b1
SH		 46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
9db96479 51#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 52#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 53#define RX_COPY_THRESHOLD 128
54#define RX_BUF_SIZE 1536
baef58b1
SH		 55#define PHY_RETRIES 1000
56#define ETH_JUMBO_MTU 9000
57#define TX_WATCHDOG (5 * HZ)
58#define NAPI_WEIGHT 64
6abebb53 59#define BLINK_MS 250
64f6b64d 60#define LINK_HZ (HZ/2)
baef58b1
SH		 61
62MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
64MODULE_LICENSE("GPL");
65MODULE_VERSION(DRV_VERSION);
66
67static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71static int debug = -1; /* defaults above */
72module_param(debug, int, 0);
73MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
275834d1 80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
2d2a3871 81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86f0cd50 86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
baef58b1
SH		 87 { 0 }
88};
89MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91static int skge_up(struct net_device *dev);
92static int skge_down(struct net_device *dev);
ee294dcd 93static void skge_phy_reset(struct skge_port *skge);
513f533e 94static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 95static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 97static void genesis_get_stats(struct skge_port *skge, u64 *data);
98static void yukon_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_init(struct skge_hw *hw, int port);
baef58b1 100static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 101static void genesis_link_up(struct skge_port *skge);
baef58b1 102
7e676d91 103/* Avoid conditionals by using array */
baef58b1
SH		 104static const int txqaddr[] = { Q_XA1, Q_XA2 };
105static const int rxqaddr[] = { Q_R1, Q_R2 };
106static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
513f533e 108static const u32 irqmask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
baef58b1 109
baef58b1
SH		 110static int skge_get_regs_len(struct net_device *dev)
111{
c3f8be96 112 return 0x4000;
baef58b1
SH		 113}
114
115/*
c3f8be96
SH		 116 * Returns copy of whole control register region
117 * Note: skip RAM address register because accessing it will
118 * cause bus hangs!
baef58b1
SH		 119 */
120static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
121 void *p)
122{
123 const struct skge_port *skge = netdev_priv(dev);
baef58b1 124 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 125
126 regs->version = 1;
c3f8be96
SH		 127 memset(p, 0, regs->len);
128 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 129
c3f8be96
SH		 130 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
131 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 132}
133
8f3f8193 134/* Wake on Lan only supported on Yukon chips with rev 1 or above */
baef58b1
SH		 135static int wol_supported(const struct skge_hw *hw)
136{
137 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 138 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 139}
140
141static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
142{
143 struct skge_port *skge = netdev_priv(dev);
144
145 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
146 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
147}
148
149static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
150{
151 struct skge_port *skge = netdev_priv(dev);
152 struct skge_hw *hw = skge->hw;
153
95566065 154 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 155 return -EOPNOTSUPP;
156
157 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
158 return -EOPNOTSUPP;
159
160 skge->wol = wol->wolopts == WAKE_MAGIC;
161
162 if (skge->wol) {
163 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
164
165 skge_write16(hw, WOL_CTRL_STAT,
166 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
167 WOL_CTL_ENA_MAGIC_PKT_UNIT);
168 } else
169 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
170
171 return 0;
172}
173
8f3f8193
SH		 174/* Determine supported/advertised modes based on hardware.
175 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 176 */
177static u32 skge_supported_modes(const struct skge_hw *hw)
178{
179 u32 supported;
180
5e1705dd 181 if (hw->copper) {
31b619c5
SH		 182 supported = SUPPORTED_10baseT_Half
183 | SUPPORTED_10baseT_Full
184 | SUPPORTED_100baseT_Half
185 | SUPPORTED_100baseT_Full
186 | SUPPORTED_1000baseT_Half
187 | SUPPORTED_1000baseT_Full
188 | SUPPORTED_Autoneg| SUPPORTED_TP;
189
190 if (hw->chip_id == CHIP_ID_GENESIS)
191 supported &= ~(SUPPORTED_10baseT_Half
192 | SUPPORTED_10baseT_Full
193 | SUPPORTED_100baseT_Half
194 | SUPPORTED_100baseT_Full);
195
196 else if (hw->chip_id == CHIP_ID_YUKON)
197 supported &= ~SUPPORTED_1000baseT_Half;
198 } else
4b67be99
SH		 199 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
200 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
31b619c5
SH		 201
202 return supported;
203}
baef58b1
SH		 204
205static int skge_get_settings(struct net_device *dev,
206 struct ethtool_cmd *ecmd)
207{
208 struct skge_port *skge = netdev_priv(dev);
209 struct skge_hw *hw = skge->hw;
210
211 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 212 ecmd->supported = skge_supported_modes(hw);
baef58b1 213
5e1705dd 214 if (hw->copper) {
baef58b1
SH		 215 ecmd->port = PORT_TP;
216 ecmd->phy_address = hw->phy_addr;
31b619c5 217 } else
baef58b1 218 ecmd->port = PORT_FIBRE;
baef58b1
SH		 219
220 ecmd->advertising = skge->advertising;
221 ecmd->autoneg = skge->autoneg;
222 ecmd->speed = skge->speed;
223 ecmd->duplex = skge->duplex;
224 return 0;
225}
226
baef58b1
SH		 227static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
228{
229 struct skge_port *skge = netdev_priv(dev);
230 const struct skge_hw *hw = skge->hw;
31b619c5 231 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 232
233 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 234 ecmd->advertising = supported;
235 skge->duplex = -1;
236 skge->speed = -1;
baef58b1 237 } else {
31b619c5
SH		 238 u32 setting;
239
2c668514 240 switch (ecmd->speed) {
baef58b1 241 case SPEED_1000:
31b619c5
SH		 242 if (ecmd->duplex == DUPLEX_FULL)
243 setting = SUPPORTED_1000baseT_Full;
244 else if (ecmd->duplex == DUPLEX_HALF)
245 setting = SUPPORTED_1000baseT_Half;
246 else
247 return -EINVAL;
baef58b1
SH		 248 break;
249 case SPEED_100:
31b619c5
SH		 250 if (ecmd->duplex == DUPLEX_FULL)
251 setting = SUPPORTED_100baseT_Full;
252 else if (ecmd->duplex == DUPLEX_HALF)
253 setting = SUPPORTED_100baseT_Half;
254 else
255 return -EINVAL;
256 break;
257
baef58b1 258 case SPEED_10:
31b619c5
SH		 259 if (ecmd->duplex == DUPLEX_FULL)
260 setting = SUPPORTED_10baseT_Full;
261 else if (ecmd->duplex == DUPLEX_HALF)
262 setting = SUPPORTED_10baseT_Half;
263 else
baef58b1
SH		 264 return -EINVAL;
265 break;
266 default:
267 return -EINVAL;
268 }
31b619c5
SH		 269
270 if ((setting & supported) == 0)
271 return -EINVAL;
272
273 skge->speed = ecmd->speed;
274 skge->duplex = ecmd->duplex;
baef58b1
SH		 275 }
276
277 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 278 skge->advertising = ecmd->advertising;
279
ee294dcd
SH		 280 if (netif_running(dev))
281 skge_phy_reset(skge);
282
baef58b1
SH		 283 return (0);
284}
285
286static void skge_get_drvinfo(struct net_device *dev,
287 struct ethtool_drvinfo *info)
288{
289 struct skge_port *skge = netdev_priv(dev);
290
291 strcpy(info->driver, DRV_NAME);
292 strcpy(info->version, DRV_VERSION);
293 strcpy(info->fw_version, "N/A");
294 strcpy(info->bus_info, pci_name(skge->hw->pdev));
295}
296
297static const struct skge_stat {
298 char name[ETH_GSTRING_LEN];
299 u16 xmac_offset;
300 u16 gma_offset;
301} skge_stats[] = {
302 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
303 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
304
305 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
306 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
307 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
308 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
309 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
310 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
311 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
312 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
313
314 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
315 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
316 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
317 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
318 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
319 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
320
321 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
322 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
323 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
324 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
325 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
326};
327
328static int skge_get_stats_count(struct net_device *dev)
329{
330 return ARRAY_SIZE(skge_stats);
331}
332
333static void skge_get_ethtool_stats(struct net_device *dev,
334 struct ethtool_stats *stats, u64 *data)
335{
336 struct skge_port *skge = netdev_priv(dev);
337
338 if (skge->hw->chip_id == CHIP_ID_GENESIS)
339 genesis_get_stats(skge, data);
340 else
341 yukon_get_stats(skge, data);
342}
343
344/* Use hardware MIB variables for critical path statistics and
345 * transmit feedback not reported at interrupt.
346 * Other errors are accounted for in interrupt handler.
347 */
348static struct net_device_stats *skge_get_stats(struct net_device *dev)
349{
350 struct skge_port *skge = netdev_priv(dev);
351 u64 data[ARRAY_SIZE(skge_stats)];
352
353 if (skge->hw->chip_id == CHIP_ID_GENESIS)
354 genesis_get_stats(skge, data);
355 else
356 yukon_get_stats(skge, data);
357
358 skge->net_stats.tx_bytes = data[0];
359 skge->net_stats.rx_bytes = data[1];
360 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
361 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
4c180fc4 362 skge->net_stats.multicast = data[3] + data[5];
baef58b1
SH		 363 skge->net_stats.collisions = data[10];
364 skge->net_stats.tx_aborted_errors = data[12];
365
366 return &skge->net_stats;
367}
368
369static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
370{
371 int i;
372
95566065 373 switch (stringset) {
baef58b1
SH		 374 case ETH_SS_STATS:
375 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
376 memcpy(data + i * ETH_GSTRING_LEN,
377 skge_stats[i].name, ETH_GSTRING_LEN);
378 break;
379 }
380}
381
382static void skge_get_ring_param(struct net_device *dev,
383 struct ethtool_ringparam *p)
384{
385 struct skge_port *skge = netdev_priv(dev);
386
387 p->rx_max_pending = MAX_RX_RING_SIZE;
388 p->tx_max_pending = MAX_TX_RING_SIZE;
389 p->rx_mini_max_pending = 0;
390 p->rx_jumbo_max_pending = 0;
391
392 p->rx_pending = skge->rx_ring.count;
393 p->tx_pending = skge->tx_ring.count;
394 p->rx_mini_pending = 0;
395 p->rx_jumbo_pending = 0;
396}
397
398static int skge_set_ring_param(struct net_device *dev,
399 struct ethtool_ringparam *p)
400{
401 struct skge_port *skge = netdev_priv(dev);
3b8bb472 402 int err;
baef58b1
SH		 403
404 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 405 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 406 return -EINVAL;
407
408 skge->rx_ring.count = p->rx_pending;
409 skge->tx_ring.count = p->tx_pending;
410
411 if (netif_running(dev)) {
412 skge_down(dev);
3b8bb472
SH		 413 err = skge_up(dev);
414 if (err)
415 dev_close(dev);
baef58b1
SH		 416 }
417
418 return 0;
419}
420
421static u32 skge_get_msglevel(struct net_device *netdev)
422{
423 struct skge_port *skge = netdev_priv(netdev);
424 return skge->msg_enable;
425}
426
427static void skge_set_msglevel(struct net_device *netdev, u32 value)
428{
429 struct skge_port *skge = netdev_priv(netdev);
430 skge->msg_enable = value;
431}
432
433static int skge_nway_reset(struct net_device *dev)
434{
435 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 436
437 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
438 return -EINVAL;
439
ee294dcd 440 skge_phy_reset(skge);
baef58b1
SH		 441 return 0;
442}
443
444static int skge_set_sg(struct net_device *dev, u32 data)
445{
446 struct skge_port *skge = netdev_priv(dev);
447 struct skge_hw *hw = skge->hw;
448
449 if (hw->chip_id == CHIP_ID_GENESIS && data)
450 return -EOPNOTSUPP;
451 return ethtool_op_set_sg(dev, data);
452}
453
454static int skge_set_tx_csum(struct net_device *dev, u32 data)
455{
456 struct skge_port *skge = netdev_priv(dev);
457 struct skge_hw *hw = skge->hw;
458
459 if (hw->chip_id == CHIP_ID_GENESIS && data)
460 return -EOPNOTSUPP;
461
462 return ethtool_op_set_tx_csum(dev, data);
463}
464
465static u32 skge_get_rx_csum(struct net_device *dev)
466{
467 struct skge_port *skge = netdev_priv(dev);
468
469 return skge->rx_csum;
470}
471
472/* Only Yukon supports checksum offload. */
473static int skge_set_rx_csum(struct net_device *dev, u32 data)
474{
475 struct skge_port *skge = netdev_priv(dev);
476
477 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
478 return -EOPNOTSUPP;
479
480 skge->rx_csum = data;
481 return 0;
482}
483
baef58b1
SH		 484static void skge_get_pauseparam(struct net_device *dev,
485 struct ethtool_pauseparam *ecmd)
486{
487 struct skge_port *skge = netdev_priv(dev);
488
5d5c8e03
SH		 489 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
490 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
491 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
baef58b1 492
5d5c8e03 493 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 494}
495
496static int skge_set_pauseparam(struct net_device *dev,
497 struct ethtool_pauseparam *ecmd)
498{
499 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 500 struct ethtool_pauseparam old;
baef58b1 501
5d5c8e03
SH		 502 skge_get_pauseparam(dev, &old);
503
504 if (ecmd->autoneg != old.autoneg)
505 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
506 else {
507 if (ecmd->rx_pause && ecmd->tx_pause)
508 skge->flow_control = FLOW_MODE_SYMMETRIC;
509 else if (ecmd->rx_pause && !ecmd->tx_pause)
510 skge->flow_control = FLOW_MODE_SYM_OR_REM;
511 else if (!ecmd->rx_pause && ecmd->tx_pause)
512 skge->flow_control = FLOW_MODE_LOC_SEND;
513 else
514 skge->flow_control = FLOW_MODE_NONE;
515 }
baef58b1 516
e8df8554
SH		 517 if (netif_running(dev))
518 skge_phy_reset(skge);
5d5c8e03 519
baef58b1
SH		 520 return 0;
521}
522
523/* Chip internal frequency for clock calculations */
524static inline u32 hwkhz(const struct skge_hw *hw)
525{
187ff3b8 526 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 527}
528
8f3f8193 529/* Chip HZ to microseconds */
baef58b1
SH		 530static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
531{
532 return (ticks * 1000) / hwkhz(hw);
533}
534
8f3f8193 535/* Microseconds to chip HZ */
baef58b1
SH		 536static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
537{
538 return hwkhz(hw) * usec / 1000;
539}
540
541static int skge_get_coalesce(struct net_device *dev,
542 struct ethtool_coalesce *ecmd)
543{
544 struct skge_port *skge = netdev_priv(dev);
545 struct skge_hw *hw = skge->hw;
546 int port = skge->port;
547
548 ecmd->rx_coalesce_usecs = 0;
549 ecmd->tx_coalesce_usecs = 0;
550
551 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
552 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
553 u32 msk = skge_read32(hw, B2_IRQM_MSK);
554
555 if (msk & rxirqmask[port])
556 ecmd->rx_coalesce_usecs = delay;
557 if (msk & txirqmask[port])
558 ecmd->tx_coalesce_usecs = delay;
559 }
560
561 return 0;
562}
563
564/* Note: interrupt timer is per board, but can turn on/off per port */
565static int skge_set_coalesce(struct net_device *dev,
566 struct ethtool_coalesce *ecmd)
567{
568 struct skge_port *skge = netdev_priv(dev);
569 struct skge_hw *hw = skge->hw;
570 int port = skge->port;
571 u32 msk = skge_read32(hw, B2_IRQM_MSK);
572 u32 delay = 25;
573
574 if (ecmd->rx_coalesce_usecs == 0)
575 msk &= ~rxirqmask[port];
576 else if (ecmd->rx_coalesce_usecs < 25 ||
577 ecmd->rx_coalesce_usecs > 33333)
578 return -EINVAL;
579 else {
580 msk |= rxirqmask[port];
581 delay = ecmd->rx_coalesce_usecs;
582 }
583
584 if (ecmd->tx_coalesce_usecs == 0)
585 msk &= ~txirqmask[port];
586 else if (ecmd->tx_coalesce_usecs < 25 ||
587 ecmd->tx_coalesce_usecs > 33333)
588 return -EINVAL;
589 else {
590 msk |= txirqmask[port];
591 delay = min(delay, ecmd->rx_coalesce_usecs);
592 }
593
594 skge_write32(hw, B2_IRQM_MSK, msk);
595 if (msk == 0)
596 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
597 else {
598 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
599 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
600 }
601 return 0;
602}
603
6abebb53
SH		 604enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
605static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 606{
6abebb53
SH		 607 struct skge_hw *hw = skge->hw;
608 int port = skge->port;
609
d85b514f 610 mutex_lock(&hw->phy_mutex);
baef58b1 611 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 612 switch (mode) {
613 case LED_MODE_OFF:
64f6b64d
SH		 614 if (hw->phy_type == SK_PHY_BCOM)
615 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
616 else {
617 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
618 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
619 }
6abebb53
SH		 620 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
621 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
622 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
623 break;
baef58b1 624
6abebb53
SH		 625 case LED_MODE_ON:
626 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
627 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 628
6abebb53
SH		 629 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
630 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 631
6abebb53 632 break;
baef58b1 633
6abebb53
SH		 634 case LED_MODE_TST:
635 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
636 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
637 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 638
64f6b64d
SH		 639 if (hw->phy_type == SK_PHY_BCOM)
640 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
641 else {
642 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
643 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
644 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
645 }
646
6abebb53 647 }
baef58b1 648 } else {
6abebb53
SH		 649 switch (mode) {
650 case LED_MODE_OFF:
651 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
652 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
653 PHY_M_LED_MO_DUP(MO_LED_OFF) |
654 PHY_M_LED_MO_10(MO_LED_OFF) |
655 PHY_M_LED_MO_100(MO_LED_OFF) |
656 PHY_M_LED_MO_1000(MO_LED_OFF) |
657 PHY_M_LED_MO_RX(MO_LED_OFF));
658 break;
659 case LED_MODE_ON:
660 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
661 PHY_M_LED_PULS_DUR(PULS_170MS) |
662 PHY_M_LED_BLINK_RT(BLINK_84MS) |
663 PHY_M_LEDC_TX_CTRL |
664 PHY_M_LEDC_DP_CTRL);
46a60f2d 665
6abebb53
SH		 666 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
667 PHY_M_LED_MO_RX(MO_LED_OFF) |
668 (skge->speed == SPEED_100 ?
669 PHY_M_LED_MO_100(MO_LED_ON) : 0));
670 break;
671 case LED_MODE_TST:
672 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
673 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
674 PHY_M_LED_MO_DUP(MO_LED_ON) |
675 PHY_M_LED_MO_10(MO_LED_ON) |
676 PHY_M_LED_MO_100(MO_LED_ON) |
677 PHY_M_LED_MO_1000(MO_LED_ON) |
678 PHY_M_LED_MO_RX(MO_LED_ON));
679 }
baef58b1 680 }
d85b514f 681 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 682}
683
684/* blink LED's for finding board */
685static int skge_phys_id(struct net_device *dev, u32 data)
686{
687 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 688 unsigned long ms;
689 enum led_mode mode = LED_MODE_TST;
baef58b1 690
95566065 691 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 692 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
693 else
694 ms = data * 1000;
baef58b1 695
6abebb53
SH		 696 while (ms > 0) {
697 skge_led(skge, mode);
698 mode ^= LED_MODE_TST;
baef58b1 699
6abebb53
SH		 700 if (msleep_interruptible(BLINK_MS))
701 break;
702 ms -= BLINK_MS;
703 }
baef58b1 704
6abebb53
SH		 705 /* back to regular LED state */
706 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 707
708 return 0;
709}
710
7282d491 711static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 712 .get_settings = skge_get_settings,
713 .set_settings = skge_set_settings,
714 .get_drvinfo = skge_get_drvinfo,
715 .get_regs_len = skge_get_regs_len,
716 .get_regs = skge_get_regs,
717 .get_wol = skge_get_wol,
718 .set_wol = skge_set_wol,
719 .get_msglevel = skge_get_msglevel,
720 .set_msglevel = skge_set_msglevel,
721 .nway_reset = skge_nway_reset,
722 .get_link = ethtool_op_get_link,
723 .get_ringparam = skge_get_ring_param,
724 .set_ringparam = skge_set_ring_param,
725 .get_pauseparam = skge_get_pauseparam,
726 .set_pauseparam = skge_set_pauseparam,
727 .get_coalesce = skge_get_coalesce,
728 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 729 .get_sg = ethtool_op_get_sg,
730 .set_sg = skge_set_sg,
731 .get_tx_csum = ethtool_op_get_tx_csum,
732 .set_tx_csum = skge_set_tx_csum,
733 .get_rx_csum = skge_get_rx_csum,
734 .set_rx_csum = skge_set_rx_csum,
735 .get_strings = skge_get_strings,
736 .phys_id = skge_phys_id,
737 .get_stats_count = skge_get_stats_count,
738 .get_ethtool_stats = skge_get_ethtool_stats,
56230d53 739 .get_perm_addr = ethtool_op_get_perm_addr,
baef58b1
SH		 740};
741
742/*
743 * Allocate ring elements and chain them together
744 * One-to-one association of board descriptors with ring elements
745 */
c3da1447 746static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 747{
748 struct skge_tx_desc *d;
749 struct skge_element *e;
750 int i;
751
ff7907ae 752 ring->start = kcalloc(sizeof(*e), ring->count, GFP_KERNEL);
baef58b1
SH		 753 if (!ring->start)
754 return -ENOMEM;
755
756 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
757 e->desc = d;
758 if (i == ring->count - 1) {
759 e->next = ring->start;
760 d->next_offset = base;
761 } else {
762 e->next = e + 1;
763 d->next_offset = base + (i+1) * sizeof(*d);
764 }
765 }
766 ring->to_use = ring->to_clean = ring->start;
767
768 return 0;
769}
770
19a33d4e
SH		 771/* Allocate and setup a new buffer for receiving */
772static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
773 struct sk_buff *skb, unsigned int bufsize)
774{
775 struct skge_rx_desc *rd = e->desc;
776 u64 map;
baef58b1
SH		 777
778 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
779 PCI_DMA_FROMDEVICE);
780
781 rd->dma_lo = map;
782 rd->dma_hi = map >> 32;
783 e->skb = skb;
784 rd->csum1_start = ETH_HLEN;
785 rd->csum2_start = ETH_HLEN;
786 rd->csum1 = 0;
787 rd->csum2 = 0;
788
789 wmb();
790
791 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
792 pci_unmap_addr_set(e, mapaddr, map);
793 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 794}
795
19a33d4e
SH		 796/* Resume receiving using existing skb,
797 * Note: DMA address is not changed by chip.
798 * MTU not changed while receiver active.
799 */
5a011447 800static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 801{
802 struct skge_rx_desc *rd = e->desc;
803
804 rd->csum2 = 0;
805 rd->csum2_start = ETH_HLEN;
806
807 wmb();
808
809 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
810}
811
812
813/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 814static void skge_rx_clean(struct skge_port *skge)
815{
816 struct skge_hw *hw = skge->hw;
817 struct skge_ring *ring = &skge->rx_ring;
818 struct skge_element *e;
819
19a33d4e
SH		 820 e = ring->start;
821 do {
baef58b1
SH		 822 struct skge_rx_desc *rd = e->desc;
823 rd->control = 0;
19a33d4e
SH		 824 if (e->skb) {
825 pci_unmap_single(hw->pdev,
826 pci_unmap_addr(e, mapaddr),
827 pci_unmap_len(e, maplen),
828 PCI_DMA_FROMDEVICE);
829 dev_kfree_skb(e->skb);
830 e->skb = NULL;
831 }
832 } while ((e = e->next) != ring->start);
baef58b1
SH		 833}
834
19a33d4e 835
baef58b1 836/* Allocate buffers for receive ring
19a33d4e 837 * For receive: to_clean is next received frame.
baef58b1 838 */
c54f9765 839static int skge_rx_fill(struct net_device *dev)
baef58b1 840{
c54f9765 841 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 842 struct skge_ring *ring = &skge->rx_ring;
843 struct skge_element *e;
baef58b1 844
19a33d4e
SH		 845 e = ring->start;
846 do {
383181ac 847 struct sk_buff *skb;
baef58b1 848
c54f9765
SH		 849 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
850 GFP_KERNEL);
19a33d4e
SH		 851 if (!skb)
852 return -ENOMEM;
853
383181ac
SH		 854 skb_reserve(skb, NET_IP_ALIGN);
855 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 856 } while ( (e = e->next) != ring->start);
baef58b1 857
19a33d4e
SH		 858 ring->to_clean = ring->start;
859 return 0;
baef58b1
SH		 860}
861
5d5c8e03
SH		 862static const char *skge_pause(enum pause_status status)
863{
864 switch(status) {
865 case FLOW_STAT_NONE:
866 return "none";
867 case FLOW_STAT_REM_SEND:
868 return "rx only";
869 case FLOW_STAT_LOC_SEND:
870 return "tx_only";
871 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
872 return "both";
873 default:
874 return "indeterminated";
875 }
876}
877
878
baef58b1
SH		 879static void skge_link_up(struct skge_port *skge)
880{
46a60f2d 881 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 882 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
883
baef58b1 884 netif_carrier_on(skge->netdev);
29b4e886 885 netif_wake_queue(skge->netdev);
baef58b1 886
5d5c8e03 887 if (netif_msg_link(skge)) {
baef58b1
SH		 888 printk(KERN_INFO PFX
889 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
890 skge->netdev->name, skge->speed,
891 skge->duplex == DUPLEX_FULL ? "full" : "half",
5d5c8e03
SH		 892 skge_pause(skge->flow_status));
893 }
baef58b1
SH		 894}
895
896static void skge_link_down(struct skge_port *skge)
897{
54cfb5aa 898 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 899 netif_carrier_off(skge->netdev);
900 netif_stop_queue(skge->netdev);
901
902 if (netif_msg_link(skge))
903 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
904}
905
a1bc9b87
SH		 906
907static void xm_link_down(struct skge_hw *hw, int port)
908{
909 struct net_device *dev = hw->dev[port];
910 struct skge_port *skge = netdev_priv(dev);
911 u16 cmd, msk;
912
913 if (hw->phy_type == SK_PHY_XMAC) {
914 msk = xm_read16(hw, port, XM_IMSK);
915 msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
916 xm_write16(hw, port, XM_IMSK, msk);
917 }
918
919 cmd = xm_read16(hw, port, XM_MMU_CMD);
920 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
921 xm_write16(hw, port, XM_MMU_CMD, cmd);
922 /* dummy read to ensure writing */
923 (void) xm_read16(hw, port, XM_MMU_CMD);
924
925 if (netif_carrier_ok(dev))
926 skge_link_down(skge);
927}
928
2cd8e5d3 929static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 930{
931 int i;
baef58b1 932
6b0c1480 933 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 934 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 935
64f6b64d
SH		 936 if (hw->phy_type == SK_PHY_XMAC)
937 goto ready;
938
89bf5f23 939 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 940 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 941 goto ready;
0781191c 942 udelay(1);
baef58b1
SH		 943 }
944
2cd8e5d3 945 return -ETIMEDOUT;
89bf5f23 946 ready:
2cd8e5d3 947 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 948
2cd8e5d3
SH		 949 return 0;
950}
951
952static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
953{
954 u16 v = 0;
955 if (__xm_phy_read(hw, port, reg, &v))
956 printk(KERN_WARNING PFX "%s: phy read timed out\n",
957 hw->dev[port]->name);
baef58b1
SH		 958 return v;
959}
960
2cd8e5d3 961static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 962{
963 int i;
964
6b0c1480 965 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 966 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 967 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 968 goto ready;
89bf5f23 969 udelay(1);
baef58b1 970 }
2cd8e5d3 971 return -EIO;
baef58b1
SH		 972
973 ready:
6b0c1480 974 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 975 for (i = 0; i < PHY_RETRIES; i++) {
976 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
977 return 0;
978 udelay(1);
979 }
980 return -ETIMEDOUT;
baef58b1
SH		 981}
982
983static void genesis_init(struct skge_hw *hw)
984{
985 /* set blink source counter */
986 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
987 skge_write8(hw, B2_BSC_CTRL, BSC_START);
988
989 /* configure mac arbiter */
990 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
991
992 /* configure mac arbiter timeout values */
993 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
994 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
995 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
996 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
997
998 skge_write8(hw, B3_MA_RCINI_RX1, 0);
999 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1000 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1001 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1002
1003 /* configure packet arbiter timeout */
1004 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1005 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1006 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1007 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1008 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1009}
1010
1011static void genesis_reset(struct skge_hw *hw, int port)
1012{
45bada65 1013 const u8 zero[8] = { 0 };
baef58b1 1014
46a60f2d
SH		 1015 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1016
baef58b1 1017 /* reset the statistics module */
6b0c1480
SH		 1018 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1019 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1020 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1021 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1022 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1023
89bf5f23 1024 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1025 if (hw->phy_type == SK_PHY_BCOM)
1026 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1027
45bada65 1028 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 1029}
1030
1031
45bada65
SH		 1032/* Convert mode to MII values */
1033static const u16 phy_pause_map[] = {
1034 [FLOW_MODE_NONE] = 0,
1035 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1036 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1037 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1038};
1039
4b67be99
SH		 1040/* special defines for FIBER (88E1011S only) */
1041static const u16 fiber_pause_map[] = {
1042 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1043 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1044 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1045 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1046};
1047
45bada65
SH		 1048
1049/* Check status of Broadcom phy link */
1050static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1051{
45bada65
SH		 1052 struct net_device *dev = hw->dev[port];
1053 struct skge_port *skge = netdev_priv(dev);
1054 u16 status;
1055
1056 /* read twice because of latch */
1057 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1058 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1059
45bada65 1060 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1061 xm_link_down(hw, port);
64f6b64d
SH		 1062 return;
1063 }
45bada65 1064
64f6b64d
SH		 1065 if (skge->autoneg == AUTONEG_ENABLE) {
1066 u16 lpa, aux;
45bada65 1067
64f6b64d
SH		 1068 if (!(status & PHY_ST_AN_OVER))
1069 return;
45bada65 1070
64f6b64d
SH		 1071 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1072 if (lpa & PHY_B_AN_RF) {
1073 printk(KERN_NOTICE PFX "%s: remote fault\n",
1074 dev->name);
1075 return;
1076 }
45bada65 1077
64f6b64d
SH		 1078 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1079
1080 /* Check Duplex mismatch */
1081 switch (aux & PHY_B_AS_AN_RES_MSK) {
1082 case PHY_B_RES_1000FD:
1083 skge->duplex = DUPLEX_FULL;
1084 break;
1085 case PHY_B_RES_1000HD:
1086 skge->duplex = DUPLEX_HALF;
1087 break;
1088 default:
1089 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1090 dev->name);
1091 return;
45bada65
SH		 1092 }
1093
64f6b64d
SH		 1094 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1095 switch (aux & PHY_B_AS_PAUSE_MSK) {
1096 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1097 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1098 break;
1099 case PHY_B_AS_PRR:
5d5c8e03 1100 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1101 break;
1102 case PHY_B_AS_PRT:
5d5c8e03 1103 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1104 break;
1105 default:
5d5c8e03 1106 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1107 }
1108 skge->speed = SPEED_1000;
45bada65 1109 }
64f6b64d
SH		 1110
1111 if (!netif_carrier_ok(dev))
1112 genesis_link_up(skge);
45bada65
SH		 1113}
1114
1115/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1116 * Phy on for 100 or 10Mbit operation
1117 */
64f6b64d 1118static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1119{
1120 struct skge_hw *hw = skge->hw;
1121 int port = skge->port;
baef58b1 1122 int i;
45bada65 1123 u16 id1, r, ext, ctl;
baef58b1
SH		 1124
1125 /* magic workaround patterns for Broadcom */
1126 static const struct {
1127 u16 reg;
1128 u16 val;
1129 } A1hack[] = {
1130 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1131 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1132 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1133 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1134 }, C0hack[] = {
1135 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1136 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1137 };
1138
45bada65
SH		 1139 /* read Id from external PHY (all have the same address) */
1140 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1141
1142 /* Optimize MDIO transfer by suppressing preamble. */
1143 r = xm_read16(hw, port, XM_MMU_CMD);
1144 r |= XM_MMU_NO_PRE;
1145 xm_write16(hw, port, XM_MMU_CMD,r);
1146
2c668514 1147 switch (id1) {
45bada65
SH		 1148 case PHY_BCOM_ID1_C0:
1149 /*
1150 * Workaround BCOM Errata for the C0 type.
1151 * Write magic patterns to reserved registers.
1152 */
1153 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1154 xm_phy_write(hw, port,
1155 C0hack[i].reg, C0hack[i].val);
1156
1157 break;
1158 case PHY_BCOM_ID1_A1:
1159 /*
1160 * Workaround BCOM Errata for the A1 type.
1161 * Write magic patterns to reserved registers.
1162 */
1163 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1164 xm_phy_write(hw, port,
1165 A1hack[i].reg, A1hack[i].val);
1166 break;
1167 }
1168
1169 /*
1170 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1171 * Disable Power Management after reset.
1172 */
1173 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1174 r |= PHY_B_AC_DIS_PM;
1175 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1176
1177 /* Dummy read */
1178 xm_read16(hw, port, XM_ISRC);
1179
1180 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1181 ctl = PHY_CT_SP1000; /* always 1000mbit */
1182
1183 if (skge->autoneg == AUTONEG_ENABLE) {
1184 /*
1185 * Workaround BCOM Errata #1 for the C5 type.
1186 * 1000Base-T Link Acquisition Failure in Slave Mode
1187 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1188 */
1189 u16 adv = PHY_B_1000C_RD;
1190 if (skge->advertising & ADVERTISED_1000baseT_Half)
1191 adv |= PHY_B_1000C_AHD;
1192 if (skge->advertising & ADVERTISED_1000baseT_Full)
1193 adv |= PHY_B_1000C_AFD;
1194 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1195
1196 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1197 } else {
1198 if (skge->duplex == DUPLEX_FULL)
1199 ctl |= PHY_CT_DUP_MD;
1200 /* Force to slave */
1201 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1202 }
1203
1204 /* Set autonegotiation pause parameters */
1205 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1206 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1207
1208 /* Handle Jumbo frames */
64f6b64d 1209 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1210 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1211 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1212
1213 ext |= PHY_B_PEC_HIGH_LA;
1214
1215 }
1216
1217 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1218 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1219
8f3f8193 1220 /* Use link status change interrupt */
45bada65 1221 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1222}
45bada65 1223
64f6b64d
SH		 1224static void xm_phy_init(struct skge_port *skge)
1225{
1226 struct skge_hw *hw = skge->hw;
1227 int port = skge->port;
1228 u16 ctrl = 0;
1229
1230 if (skge->autoneg == AUTONEG_ENABLE) {
1231 if (skge->advertising & ADVERTISED_1000baseT_Half)
1232 ctrl |= PHY_X_AN_HD;
1233 if (skge->advertising & ADVERTISED_1000baseT_Full)
1234 ctrl |= PHY_X_AN_FD;
1235
4b67be99 1236 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1237
1238 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1239
1240 /* Restart Auto-negotiation */
1241 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1242 } else {
1243 /* Set DuplexMode in Config register */
1244 if (skge->duplex == DUPLEX_FULL)
1245 ctrl |= PHY_CT_DUP_MD;
1246 /*
1247 * Do NOT enable Auto-negotiation here. This would hold
1248 * the link down because no IDLEs are transmitted
1249 */
1250 }
1251
1252 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1253
1254 /* Poll PHY for status changes */
1255 schedule_delayed_work(&skge->link_thread, LINK_HZ);
1256}
1257
1258static void xm_check_link(struct net_device *dev)
1259{
1260 struct skge_port *skge = netdev_priv(dev);
1261 struct skge_hw *hw = skge->hw;
1262 int port = skge->port;
1263 u16 status;
1264
1265 /* read twice because of latch */
1266 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1267 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1268
1269 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1270 xm_link_down(hw, port);
64f6b64d
SH		 1271 return;
1272 }
1273
1274 if (skge->autoneg == AUTONEG_ENABLE) {
1275 u16 lpa, res;
1276
1277 if (!(status & PHY_ST_AN_OVER))
1278 return;
1279
1280 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1281 if (lpa & PHY_B_AN_RF) {
1282 printk(KERN_NOTICE PFX "%s: remote fault\n",
1283 dev->name);
1284 return;
1285 }
1286
1287 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1288
1289 /* Check Duplex mismatch */
1290 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1291 case PHY_X_RS_FD:
1292 skge->duplex = DUPLEX_FULL;
1293 break;
1294 case PHY_X_RS_HD:
1295 skge->duplex = DUPLEX_HALF;
1296 break;
1297 default:
1298 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1299 dev->name);
1300 return;
1301 }
1302
1303 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1304 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1305 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1306 (lpa & PHY_X_P_SYM_MD))
1307 skge->flow_status = FLOW_STAT_SYMMETRIC;
1308 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1309 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1310 /* Enable PAUSE receive, disable PAUSE transmit */
1311 skge->flow_status = FLOW_STAT_REM_SEND;
1312 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1313 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1314 /* Disable PAUSE receive, enable PAUSE transmit */
1315 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1316 else
5d5c8e03 1317 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1318
1319 skge->speed = SPEED_1000;
1320 }
1321
1322 if (!netif_carrier_ok(dev))
1323 genesis_link_up(skge);
1324}
1325
1326/* Poll to check for link coming up.
1327 * Since internal PHY is wired to a level triggered pin, can't
1328 * get an interrupt when carrier is detected.
1329 */
c4028958 1330static void xm_link_timer(struct work_struct *work)
64f6b64d 1331{
c4028958
DH		 1332 struct skge_port *skge =
1333 container_of(work, struct skge_port, link_thread.work);
1334 struct net_device *dev = skge->netdev;
64f6b64d
SH		 1335 struct skge_hw *hw = skge->hw;
1336 int port = skge->port;
1337
1338 if (!netif_running(dev))
1339 return;
1340
1341 if (netif_carrier_ok(dev)) {
1342 xm_read16(hw, port, XM_ISRC);
1343 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1344 goto nochange;
1345 } else {
1346 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1347 goto nochange;
1348 xm_read16(hw, port, XM_ISRC);
1349 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1350 goto nochange;
1351 }
1352
1353 mutex_lock(&hw->phy_mutex);
1354 xm_check_link(dev);
1355 mutex_unlock(&hw->phy_mutex);
1356
1357nochange:
1358 schedule_delayed_work(&skge->link_thread, LINK_HZ);
45bada65
SH		 1359}
1360
1361static void genesis_mac_init(struct skge_hw *hw, int port)
1362{
1363 struct net_device *dev = hw->dev[port];
1364 struct skge_port *skge = netdev_priv(dev);
1365 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1366 int i;
1367 u32 r;
1368 const u8 zero[6] = { 0 };
1369
0781191c
SH		 1370 for (i = 0; i < 10; i++) {
1371 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1372 MFF_SET_MAC_RST);
1373 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1374 goto reset_ok;
1375 udelay(1);
1376 }
baef58b1 1377
0781191c
SH		 1378 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1379
1380 reset_ok:
baef58b1 1381 /* Unreset the XMAC. */
6b0c1480 1382 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1383
1384 /*
1385 * Perform additional initialization for external PHYs,
1386 * namely for the 1000baseTX cards that use the XMAC's
1387 * GMII mode.
1388 */
64f6b64d
SH		 1389 if (hw->phy_type != SK_PHY_XMAC) {
1390 /* Take external Phy out of reset */
1391 r = skge_read32(hw, B2_GP_IO);
1392 if (port == 0)
1393 r |= GP_DIR_0|GP_IO_0;
1394 else
1395 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1396
64f6b64d 1397 skge_write32(hw, B2_GP_IO, r);
0781191c 1398
64f6b64d
SH		 1399 /* Enable GMII interface */
1400 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1401 }
89bf5f23 1402
89bf5f23 1403
64f6b64d
SH		 1404 switch(hw->phy_type) {
1405 case SK_PHY_XMAC:
1406 xm_phy_init(skge);
1407 break;
1408 case SK_PHY_BCOM:
1409 bcom_phy_init(skge);
1410 bcom_check_link(hw, port);
1411 }
89bf5f23 1412
45bada65
SH		 1413 /* Set Station Address */
1414 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1415
45bada65
SH		 1416 /* We don't use match addresses so clear */
1417 for (i = 1; i < 16; i++)
1418 xm_outaddr(hw, port, XM_EXM(i), zero);
1419
0781191c
SH		 1420 /* Clear MIB counters */
1421 xm_write16(hw, port, XM_STAT_CMD,
1422 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1423 /* Clear two times according to Errata #3 */
1424 xm_write16(hw, port, XM_STAT_CMD,
1425 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1426
45bada65
SH		 1427 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1428 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1429
1430 /* We don't need the FCS appended to the packet. */
1431 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1432 if (jumbo)
1433 r |= XM_RX_BIG_PK_OK;
89bf5f23 1434
45bada65 1435 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1436 /*
45bada65
SH		 1437 * If in manual half duplex mode the other side might be in
1438 * full duplex mode, so ignore if a carrier extension is not seen
1439 * on frames received
89bf5f23 1440 */
45bada65 1441 r |= XM_RX_DIS_CEXT;
baef58b1 1442 }
45bada65 1443 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1444
baef58b1
SH		 1445
1446 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1447 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1448
1449 /*
1450 * Bump up the transmit threshold. This helps hold off transmit
1451 * underruns when we're blasting traffic from both ports at once.
1452 */
1453 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1454
1455 /*
1456 * Enable the reception of all error frames. This is is
1457 * a necessary evil due to the design of the XMAC. The
1458 * XMAC's receive FIFO is only 8K in size, however jumbo
1459 * frames can be up to 9000 bytes in length. When bad
1460 * frame filtering is enabled, the XMAC's RX FIFO operates
1461 * in 'store and forward' mode. For this to work, the
1462 * entire frame has to fit into the FIFO, but that means
1463 * that jumbo frames larger than 8192 bytes will be
1464 * truncated. Disabling all bad frame filtering causes
1465 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1466 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1467 * RX FIFO as soon as the FIFO threshold is reached.
1468 */
45bada65 1469 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1470
baef58b1
SH		 1471
1472 /*
45bada65
SH		 1473 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1474 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1475 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1476 */
45bada65
SH		 1477 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1478
1479 /*
1480 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1481 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1482 * and 'Octets Tx OK Hi Cnt Ov'.
1483 */
1484 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1485
1486 /* Configure MAC arbiter */
1487 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1488
1489 /* configure timeout values */
1490 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1491 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1492 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1493 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1494
1495 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1496 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1497 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1498 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1499
1500 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1501 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1502 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1503 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1504
1505 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1506 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1507 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1508 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1509
45bada65 1510 if (jumbo) {
baef58b1 1511 /* Enable frame flushing if jumbo frames used */
6b0c1480 1512 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1513 } else {
1514 /* enable timeout timers if normal frames */
1515 skge_write16(hw, B3_PA_CTRL,
45bada65 1516 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1517 }
baef58b1
SH		 1518}
1519
1520static void genesis_stop(struct skge_port *skge)
1521{
1522 struct skge_hw *hw = skge->hw;
1523 int port = skge->port;
89bf5f23 1524 u32 reg;
baef58b1 1525
46a60f2d
SH		 1526 genesis_reset(hw, port);
1527
baef58b1
SH		 1528 /* Clear Tx packet arbiter timeout IRQ */
1529 skge_write16(hw, B3_PA_CTRL,
1530 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1531
1532 /*
8f3f8193 1533 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1534 * terminate if we don't flush the XMAC's transmit FIFO !
1535 */
6b0c1480
SH		 1536 xm_write32(hw, port, XM_MODE,
1537 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1538
1539
1540 /* Reset the MAC */
6b0c1480 1541 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1542
1543 /* For external PHYs there must be special handling */
64f6b64d
SH		 1544 if (hw->phy_type != SK_PHY_XMAC) {
1545 reg = skge_read32(hw, B2_GP_IO);
1546 if (port == 0) {
1547 reg |= GP_DIR_0;
1548 reg &= ~GP_IO_0;
1549 } else {
1550 reg |= GP_DIR_2;
1551 reg &= ~GP_IO_2;
1552 }
1553 skge_write32(hw, B2_GP_IO, reg);
1554 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1555 }
1556
6b0c1480
SH		 1557 xm_write16(hw, port, XM_MMU_CMD,
1558 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1559 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1560
6b0c1480 1561 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1562}
1563
1564
1565static void genesis_get_stats(struct skge_port *skge, u64 *data)
1566{
1567 struct skge_hw *hw = skge->hw;
1568 int port = skge->port;
1569 int i;
1570 unsigned long timeout = jiffies + HZ;
1571
6b0c1480 1572 xm_write16(hw, port,
baef58b1
SH		 1573 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1574
1575 /* wait for update to complete */
6b0c1480 1576 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1577 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1578 if (time_after(jiffies, timeout))
1579 break;
1580 udelay(10);
1581 }
1582
1583 /* special case for 64 bit octet counter */
6b0c1480
SH		 1584 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1585 | xm_read32(hw, port, XM_TXO_OK_LO);
1586 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1587 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1588
1589 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1590 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1591}
1592
1593static void genesis_mac_intr(struct skge_hw *hw, int port)
1594{
1595 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1596 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1597
7e676d91
SH		 1598 if (netif_msg_intr(skge))
1599 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1600 skge->netdev->name, status);
baef58b1 1601
a1bc9b87
SH		 1602 if (hw->phy_type == SK_PHY_XMAC &&
1603 (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
1604 xm_link_down(hw, port);
1605
baef58b1 1606 if (status & XM_IS_TXF_UR) {
6b0c1480 1607 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1608 ++skge->net_stats.tx_fifo_errors;
1609 }
1610 if (status & XM_IS_RXF_OV) {
6b0c1480 1611 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1612 ++skge->net_stats.rx_fifo_errors;
1613 }
1614}
1615
baef58b1
SH		 1616static void genesis_link_up(struct skge_port *skge)
1617{
1618 struct skge_hw *hw = skge->hw;
1619 int port = skge->port;
a1bc9b87 1620 u16 cmd, msk;
64f6b64d 1621 u32 mode;
baef58b1 1622
6b0c1480 1623 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1624
1625 /*
1626 * enabling pause frame reception is required for 1000BT
1627 * because the XMAC is not reset if the link is going down
1628 */
5d5c8e03
SH		 1629 if (skge->flow_status == FLOW_STAT_NONE ||
1630 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1631 /* Disable Pause Frame Reception */
baef58b1
SH		 1632 cmd |= XM_MMU_IGN_PF;
1633 else
1634 /* Enable Pause Frame Reception */
1635 cmd &= ~XM_MMU_IGN_PF;
1636
6b0c1480 1637 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1638
6b0c1480 1639 mode = xm_read32(hw, port, XM_MODE);
5d5c8e03
SH		 1640 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1641 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1642 /*
1643 * Configure Pause Frame Generation
1644 * Use internal and external Pause Frame Generation.
1645 * Sending pause frames is edge triggered.
1646 * Send a Pause frame with the maximum pause time if
1647 * internal oder external FIFO full condition occurs.
1648 * Send a zero pause time frame to re-start transmission.
1649 */
1650 /* XM_PAUSE_DA = '010000C28001' (default) */
1651 /* XM_MAC_PTIME = 0xffff (maximum) */
1652 /* remember this value is defined in big endian (!) */
6b0c1480 1653 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1654
1655 mode |= XM_PAUSE_MODE;
6b0c1480 1656 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1657 } else {
1658 /*
1659 * disable pause frame generation is required for 1000BT
1660 * because the XMAC is not reset if the link is going down
1661 */
1662 /* Disable Pause Mode in Mode Register */
1663 mode &= ~XM_PAUSE_MODE;
1664
6b0c1480 1665 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1666 }
1667
6b0c1480 1668 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87
SH		 1669 msk = XM_DEF_MSK;
1670 if (hw->phy_type != SK_PHY_XMAC)
1671 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1672
1673 xm_write16(hw, port, XM_IMSK, msk);
6b0c1480 1674 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1675
1676 /* get MMU Command Reg. */
6b0c1480 1677 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1678 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1679 cmd |= XM_MMU_GMII_FD;
1680
89bf5f23
SH		 1681 /*
1682 * Workaround BCOM Errata (#10523) for all BCom Phys
1683 * Enable Power Management after link up
1684 */
64f6b64d
SH		 1685 if (hw->phy_type == SK_PHY_BCOM) {
1686 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1687 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1688 & ~PHY_B_AC_DIS_PM);
1689 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1690 }
baef58b1
SH		 1691
1692 /* enable Rx/Tx */
6b0c1480 1693 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1694 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1695 skge_link_up(skge);
1696}
1697
1698
45bada65 1699static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1700{
1701 struct skge_hw *hw = skge->hw;
1702 int port = skge->port;
45bada65
SH		 1703 u16 isrc;
1704
1705 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1706 if (netif_msg_intr(skge))
1707 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1708 skge->netdev->name, isrc);
baef58b1 1709
45bada65
SH		 1710 if (isrc & PHY_B_IS_PSE)
1711 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1712 hw->dev[port]->name);
baef58b1
SH		 1713
1714 /* Workaround BCom Errata:
1715 * enable and disable loopback mode if "NO HCD" occurs.
1716 */
45bada65 1717 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1718 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1719 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1720 ctrl | PHY_CT_LOOP);
6b0c1480 1721 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1722 ctrl & ~PHY_CT_LOOP);
1723 }
1724
45bada65
SH		 1725 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1726 bcom_check_link(hw, port);
baef58b1 1727
baef58b1
SH		 1728}
1729
2cd8e5d3
SH		 1730static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1731{
1732 int i;
1733
1734 gma_write16(hw, port, GM_SMI_DATA, val);
1735 gma_write16(hw, port, GM_SMI_CTRL,
1736 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1737 for (i = 0; i < PHY_RETRIES; i++) {
1738 udelay(1);
1739
1740 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1741 return 0;
1742 }
1743
1744 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1745 hw->dev[port]->name);
1746 return -EIO;
1747}
1748
1749static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1750{
1751 int i;
1752
1753 gma_write16(hw, port, GM_SMI_CTRL,
1754 GM_SMI_CT_PHY_AD(hw->phy_addr)
1755 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1756
1757 for (i = 0; i < PHY_RETRIES; i++) {
1758 udelay(1);
1759 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1760 goto ready;
1761 }
1762
1763 return -ETIMEDOUT;
1764 ready:
1765 *val = gma_read16(hw, port, GM_SMI_DATA);
1766 return 0;
1767}
1768
1769static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1770{
1771 u16 v = 0;
1772 if (__gm_phy_read(hw, port, reg, &v))
1773 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1774 hw->dev[port]->name);
1775 return v;
1776}
1777
8f3f8193 1778/* Marvell Phy Initialization */
baef58b1
SH		 1779static void yukon_init(struct skge_hw *hw, int port)
1780{
1781 struct skge_port *skge = netdev_priv(hw->dev[port]);
1782 u16 ctrl, ct1000, adv;
baef58b1 1783
baef58b1 1784 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1785 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1786
1787 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1788 PHY_M_EC_MAC_S_MSK);
1789 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1790
c506a509 1791 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1792
6b0c1480 1793 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1794 }
1795
6b0c1480 1796 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1797 if (skge->autoneg == AUTONEG_DISABLE)
1798 ctrl &= ~PHY_CT_ANE;
1799
1800 ctrl |= PHY_CT_RESET;
6b0c1480 1801 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1802
1803 ctrl = 0;
1804 ct1000 = 0;
b18f2091 1805 adv = PHY_AN_CSMA;
baef58b1
SH		 1806
1807 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1808 if (hw->copper) {
baef58b1
SH		 1809 if (skge->advertising & ADVERTISED_1000baseT_Full)
1810 ct1000 |= PHY_M_1000C_AFD;
1811 if (skge->advertising & ADVERTISED_1000baseT_Half)
1812 ct1000 |= PHY_M_1000C_AHD;
1813 if (skge->advertising & ADVERTISED_100baseT_Full)
1814 adv |= PHY_M_AN_100_FD;
1815 if (skge->advertising & ADVERTISED_100baseT_Half)
1816 adv |= PHY_M_AN_100_HD;
1817 if (skge->advertising & ADVERTISED_10baseT_Full)
1818 adv |= PHY_M_AN_10_FD;
1819 if (skge->advertising & ADVERTISED_10baseT_Half)
1820 adv |= PHY_M_AN_10_HD;
baef58b1 1821
4b67be99
SH		 1822 /* Set Flow-control capabilities */
1823 adv |= phy_pause_map[skge->flow_control];
1824 } else {
1825 if (skge->advertising & ADVERTISED_1000baseT_Full)
1826 adv |= PHY_M_AN_1000X_AFD;
1827 if (skge->advertising & ADVERTISED_1000baseT_Half)
1828 adv |= PHY_M_AN_1000X_AHD;
1829
1830 adv |= fiber_pause_map[skge->flow_control];
1831 }
45bada65 1832
baef58b1
SH		 1833 /* Restart Auto-negotiation */
1834 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1835 } else {
1836 /* forced speed/duplex settings */
1837 ct1000 = PHY_M_1000C_MSE;
1838
1839 if (skge->duplex == DUPLEX_FULL)
1840 ctrl |= PHY_CT_DUP_MD;
1841
1842 switch (skge->speed) {
1843 case SPEED_1000:
1844 ctrl |= PHY_CT_SP1000;
1845 break;
1846 case SPEED_100:
1847 ctrl |= PHY_CT_SP100;
1848 break;
1849 }
1850
1851 ctrl |= PHY_CT_RESET;
1852 }
1853
c506a509 1854 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1855
6b0c1480
SH		 1856 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1857 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1858
baef58b1
SH		 1859 /* Enable phy interrupt on autonegotiation complete (or link up) */
1860 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1861 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1862 else
4cde06ed 1863 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1864}
1865
1866static void yukon_reset(struct skge_hw *hw, int port)
1867{
6b0c1480
SH		 1868 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1869 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1870 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1871 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1872 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1873
6b0c1480
SH		 1874 gma_write16(hw, port, GM_RX_CTRL,
1875 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1876 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1877}
1878
c8868611
SH		 1879/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1880static int is_yukon_lite_a0(struct skge_hw *hw)
1881{
1882 u32 reg;
1883 int ret;
1884
1885 if (hw->chip_id != CHIP_ID_YUKON)
1886 return 0;
1887
1888 reg = skge_read32(hw, B2_FAR);
1889 skge_write8(hw, B2_FAR + 3, 0xff);
1890 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1891 skge_write32(hw, B2_FAR, reg);
1892 return ret;
1893}
1894
baef58b1
SH		 1895static void yukon_mac_init(struct skge_hw *hw, int port)
1896{
1897 struct skge_port *skge = netdev_priv(hw->dev[port]);
1898 int i;
1899 u32 reg;
1900 const u8 *addr = hw->dev[port]->dev_addr;
1901
1902 /* WA code for COMA mode -- set PHY reset */
1903 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1904 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1905 reg = skge_read32(hw, B2_GP_IO);
1906 reg |= GP_DIR_9 | GP_IO_9;
1907 skge_write32(hw, B2_GP_IO, reg);
1908 }
baef58b1
SH		 1909
1910 /* hard reset */
6b0c1480
SH		 1911 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1912 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1913
1914 /* WA code for COMA mode -- clear PHY reset */
1915 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1916 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1917 reg = skge_read32(hw, B2_GP_IO);
1918 reg |= GP_DIR_9;
1919 reg &= ~GP_IO_9;
1920 skge_write32(hw, B2_GP_IO, reg);
1921 }
baef58b1
SH		 1922
1923 /* Set hardware config mode */
1924 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1925 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 1926 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 1927
1928 /* Clear GMC reset */
6b0c1480
SH		 1929 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1930 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1931 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 1932
baef58b1
SH		 1933 if (skge->autoneg == AUTONEG_DISABLE) {
1934 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1935 gma_write16(hw, port, GM_GP_CTRL,
1936 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1937
1938 switch (skge->speed) {
1939 case SPEED_1000:
564f9abb 1940 reg &= ~GM_GPCR_SPEED_100;
baef58b1 1941 reg |= GM_GPCR_SPEED_1000;
564f9abb 1942 break;
baef58b1 1943 case SPEED_100:
564f9abb 1944 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 1945 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 1946 break;
1947 case SPEED_10:
1948 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1949 break;
baef58b1
SH		 1950 }
1951
1952 if (skge->duplex == DUPLEX_FULL)
1953 reg |= GM_GPCR_DUP_FULL;
1954 } else
1955 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 1956
baef58b1
SH		 1957 switch (skge->flow_control) {
1958 case FLOW_MODE_NONE:
6b0c1480 1959 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1960 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1961 break;
1962 case FLOW_MODE_LOC_SEND:
1963 /* disable Rx flow-control */
1964 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 1965 break;
1966 case FLOW_MODE_SYMMETRIC:
1967 case FLOW_MODE_SYM_OR_REM:
1968 /* enable Tx & Rx flow-control */
1969 break;
baef58b1
SH		 1970 }
1971
6b0c1480 1972 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 1973 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1974
baef58b1 1975 yukon_init(hw, port);
baef58b1
SH		 1976
1977 /* MIB clear */
6b0c1480
SH		 1978 reg = gma_read16(hw, port, GM_PHY_ADDR);
1979 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1980
1981 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1982 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1983 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1984
1985 /* transmit control */
6b0c1480 1986 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1987
1988 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1989 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1990 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1991
1992 /* transmit flow control */
6b0c1480 1993 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1994
1995 /* transmit parameter */
6b0c1480 1996 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1997 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1998 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1999 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2000
2001 /* serial mode register */
2002 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2003 if (hw->dev[port]->mtu > 1500)
2004 reg |= GM_SMOD_JUMBO_ENA;
2005
6b0c1480 2006 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2007
2008 /* physical address: used for pause frames */
6b0c1480 2009 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2010 /* virtual address for data */
6b0c1480 2011 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2012
2013 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2014 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2015 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2016 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2017
2018 /* Initialize Mac Fifo */
2019
2020 /* Configure Rx MAC FIFO */
6b0c1480 2021 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2022 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2023
2024 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2025 if (is_yukon_lite_a0(hw))
baef58b1 2026 reg &= ~GMF_RX_F_FL_ON;
c8868611 2027
6b0c1480
SH		 2028 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2029 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2030 /*
2031 * because Pause Packet Truncation in GMAC is not working
2032 * we have to increase the Flush Threshold to 64 bytes
2033 * in order to flush pause packets in Rx FIFO on Yukon-1
2034 */
2035 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2036
2037 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2038 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2039 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2040}
2041
355ec572
SH		 2042/* Go into power down mode */
2043static void yukon_suspend(struct skge_hw *hw, int port)
2044{
2045 u16 ctrl;
2046
2047 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2048 ctrl |= PHY_M_PC_POL_R_DIS;
2049 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2050
2051 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2052 ctrl |= PHY_CT_RESET;
2053 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2054
2055 /* switch IEEE compatible power down mode on */
2056 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2057 ctrl |= PHY_CT_PDOWN;
2058 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2059}
2060
baef58b1
SH		 2061static void yukon_stop(struct skge_port *skge)
2062{
2063 struct skge_hw *hw = skge->hw;
2064 int port = skge->port;
2065
46a60f2d
SH		 2066 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2067 yukon_reset(hw, port);
baef58b1 2068
6b0c1480
SH		 2069 gma_write16(hw, port, GM_GP_CTRL,
2070 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2071 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2072 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2073
355ec572 2074 yukon_suspend(hw, port);
46a60f2d 2075
baef58b1 2076 /* set GPHY Control reset */
46a60f2d
SH		 2077 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2078 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2079}
2080
2081static void yukon_get_stats(struct skge_port *skge, u64 *data)
2082{
2083 struct skge_hw *hw = skge->hw;
2084 int port = skge->port;
2085 int i;
2086
6b0c1480
SH		 2087 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2088 | gma_read32(hw, port, GM_TXO_OK_LO);
2089 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2090 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2091
2092 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2093 data[i] = gma_read32(hw, port,
baef58b1
SH		 2094 skge_stats[i].gma_offset);
2095}
2096
2097static void yukon_mac_intr(struct skge_hw *hw, int port)
2098{
7e676d91
SH		 2099 struct net_device *dev = hw->dev[port];
2100 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2101 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2102
7e676d91
SH		 2103 if (netif_msg_intr(skge))
2104 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2105 dev->name, status);
2106
baef58b1
SH		 2107 if (status & GM_IS_RX_FF_OR) {
2108 ++skge->net_stats.rx_fifo_errors;
d8a09943 2109 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2110 }
d8a09943 2111
baef58b1
SH		 2112 if (status & GM_IS_TX_FF_UR) {
2113 ++skge->net_stats.tx_fifo_errors;
d8a09943 2114 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2115 }
2116
2117}
2118
2119static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2120{
95566065 2121 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2122 case PHY_M_PS_SPEED_1000:
2123 return SPEED_1000;
2124 case PHY_M_PS_SPEED_100:
2125 return SPEED_100;
2126 default:
2127 return SPEED_10;
2128 }
2129}
2130
2131static void yukon_link_up(struct skge_port *skge)
2132{
2133 struct skge_hw *hw = skge->hw;
2134 int port = skge->port;
2135 u16 reg;
2136
baef58b1 2137 /* Enable Transmit FIFO Underrun */
46a60f2d 2138 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2139
6b0c1480 2140 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2141 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2142 reg |= GM_GPCR_DUP_FULL;
2143
2144 /* enable Rx/Tx */
2145 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2146 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2147
4cde06ed 2148 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2149 skge_link_up(skge);
2150}
2151
2152static void yukon_link_down(struct skge_port *skge)
2153{
2154 struct skge_hw *hw = skge->hw;
2155 int port = skge->port;
d8a09943 2156 u16 ctrl;
baef58b1 2157
d8a09943
SH		 2158 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2159 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2160 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2161
5d5c8e03
SH		 2162 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2163 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2164 ctrl |= PHY_M_AN_ASP;
baef58b1 2165 /* restore Asymmetric Pause bit */
5d5c8e03 2166 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2167 }
2168
baef58b1
SH		 2169 skge_link_down(skge);
2170
2171 yukon_init(hw, port);
2172}
2173
2174static void yukon_phy_intr(struct skge_port *skge)
2175{
2176 struct skge_hw *hw = skge->hw;
2177 int port = skge->port;
2178 const char *reason = NULL;
2179 u16 istatus, phystat;
2180
6b0c1480
SH		 2181 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2182 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 2183
2184 if (netif_msg_intr(skge))
2185 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2186 skge->netdev->name, istatus, phystat);
baef58b1
SH		 2187
2188 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2189 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2190 & PHY_M_AN_RF) {
2191 reason = "remote fault";
2192 goto failed;
2193 }
2194
c506a509 2195 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2196 reason = "master/slave fault";
2197 goto failed;
2198 }
2199
2200 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2201 reason = "speed/duplex";
2202 goto failed;
2203 }
2204
2205 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2206 ? DUPLEX_FULL : DUPLEX_HALF;
2207 skge->speed = yukon_speed(hw, phystat);
2208
baef58b1
SH		 2209 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2210 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2211 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2212 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2213 break;
2214 case PHY_M_PS_RX_P_EN:
5d5c8e03 2215 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2216 break;
2217 case PHY_M_PS_TX_P_EN:
5d5c8e03 2218 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2219 break;
2220 default:
5d5c8e03 2221 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2222 }
2223
5d5c8e03 2224 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2225 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2226 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2227 else
6b0c1480 2228 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2229 yukon_link_up(skge);
2230 return;
2231 }
2232
2233 if (istatus & PHY_M_IS_LSP_CHANGE)
2234 skge->speed = yukon_speed(hw, phystat);
2235
2236 if (istatus & PHY_M_IS_DUP_CHANGE)
2237 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2238 if (istatus & PHY_M_IS_LST_CHANGE) {
2239 if (phystat & PHY_M_PS_LINK_UP)
2240 yukon_link_up(skge);
2241 else
2242 yukon_link_down(skge);
2243 }
2244 return;
2245 failed:
2246 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2247 skge->netdev->name, reason);
2248
2249 /* XXX restart autonegotiation? */
2250}
2251
ee294dcd
SH		 2252static void skge_phy_reset(struct skge_port *skge)
2253{
2254 struct skge_hw *hw = skge->hw;
2255 int port = skge->port;
aae343d4 2256 struct net_device *dev = hw->dev[port];
ee294dcd
SH		 2257
2258 netif_stop_queue(skge->netdev);
2259 netif_carrier_off(skge->netdev);
2260
d85b514f 2261 mutex_lock(&hw->phy_mutex);
ee294dcd
SH		 2262 if (hw->chip_id == CHIP_ID_GENESIS) {
2263 genesis_reset(hw, port);
2264 genesis_mac_init(hw, port);
2265 } else {
2266 yukon_reset(hw, port);
2267 yukon_init(hw, port);
2268 }
d85b514f 2269 mutex_unlock(&hw->phy_mutex);
75814090
SH		 2270
2271 dev->set_multicast_list(dev);
ee294dcd
SH		 2272}
2273
2cd8e5d3
SH		 2274/* Basic MII support */
2275static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2276{
2277 struct mii_ioctl_data *data = if_mii(ifr);
2278 struct skge_port *skge = netdev_priv(dev);
2279 struct skge_hw *hw = skge->hw;
2280 int err = -EOPNOTSUPP;
2281
2282 if (!netif_running(dev))
2283 return -ENODEV; /* Phy still in reset */
2284
2285 switch(cmd) {
2286 case SIOCGMIIPHY:
2287 data->phy_id = hw->phy_addr;
2288
2289 /* fallthru */
2290 case SIOCGMIIREG: {
2291 u16 val = 0;
d85b514f 2292 mutex_lock(&hw->phy_mutex);
2cd8e5d3
SH		 2293 if (hw->chip_id == CHIP_ID_GENESIS)
2294 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2295 else
2296 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
d85b514f 2297 mutex_unlock(&hw->phy_mutex);
2cd8e5d3
SH		 2298 data->val_out = val;
2299 break;
2300 }
2301
2302 case SIOCSMIIREG:
2303 if (!capable(CAP_NET_ADMIN))
2304 return -EPERM;
2305
d85b514f 2306 mutex_lock(&hw->phy_mutex);
2cd8e5d3
SH		 2307 if (hw->chip_id == CHIP_ID_GENESIS)
2308 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2309 data->val_in);
2310 else
2311 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2312 data->val_in);
d85b514f 2313 mutex_unlock(&hw->phy_mutex);
2cd8e5d3
SH		 2314 break;
2315 }
2316 return err;
2317}
2318
baef58b1
SH		 2319static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2320{
2321 u32 end;
2322
2323 start /= 8;
2324 len /= 8;
2325 end = start + len - 1;
2326
2327 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2328 skge_write32(hw, RB_ADDR(q, RB_START), start);
2329 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2330 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2331 skge_write32(hw, RB_ADDR(q, RB_END), end);
2332
2333 if (q == Q_R1 || q == Q_R2) {
2334 /* Set thresholds on receive queue's */
2335 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2336 start + (2*len)/3);
2337 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2338 start + (len/3));
2339 } else {
2340 /* Enable store & forward on Tx queue's because
2341 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2342 */
2343 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2344 }
2345
2346 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2347}
2348
2349/* Setup Bus Memory Interface */
2350static void skge_qset(struct skge_port *skge, u16 q,
2351 const struct skge_element *e)
2352{
2353 struct skge_hw *hw = skge->hw;
2354 u32 watermark = 0x600;
2355 u64 base = skge->dma + (e->desc - skge->mem);
2356
2357 /* optimization to reduce window on 32bit/33mhz */
2358 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2359 watermark /= 2;
2360
2361 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2362 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2363 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2364 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2365}
2366
2367static int skge_up(struct net_device *dev)
2368{
2369 struct skge_port *skge = netdev_priv(dev);
2370 struct skge_hw *hw = skge->hw;
2371 int port = skge->port;
2372 u32 chunk, ram_addr;
2373 size_t rx_size, tx_size;
2374 int err;
2375
2376 if (netif_msg_ifup(skge))
2377 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2378
19a33d4e 2379 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2380 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2381 else
2382 skge->rx_buf_size = RX_BUF_SIZE;
2383
2384
baef58b1
SH		 2385 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2386 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2387 skge->mem_size = tx_size + rx_size;
2388 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2389 if (!skge->mem)
2390 return -ENOMEM;
2391
c3da1447
SH		 2392 BUG_ON(skge->dma & 7);
2393
2394 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2395 printk(KERN_ERR PFX "pci_alloc_consistent region crosses 4G boundary\n");
2396 err = -EINVAL;
2397 goto free_pci_mem;
2398 }
2399
baef58b1
SH		 2400 memset(skge->mem, 0, skge->mem_size);
2401
203babb6
SH		 2402 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2403 if (err)
baef58b1
SH		 2404 goto free_pci_mem;
2405
c54f9765 2406 err = skge_rx_fill(dev);
19a33d4e 2407 if (err)
baef58b1
SH		 2408 goto free_rx_ring;
2409
203babb6
SH		 2410 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2411 skge->dma + rx_size);
2412 if (err)
baef58b1
SH		 2413 goto free_rx_ring;
2414
8f3f8193 2415 /* Initialize MAC */
d85b514f 2416 mutex_lock(&hw->phy_mutex);
baef58b1
SH		 2417 if (hw->chip_id == CHIP_ID_GENESIS)
2418 genesis_mac_init(hw, port);
2419 else
2420 yukon_mac_init(hw, port);
d85b514f 2421 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 2422
2423 /* Configure RAMbuffers */
981d0377 2424 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2425 ram_addr = hw->ram_offset + 2 * chunk * port;
2426
2427 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2428 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2429
2430 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2431 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2432 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2433
2434 /* Start receiver BMU */
2435 wmb();
2436 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2437 skge_led(skge, LED_MODE_ON);
baef58b1 2438
239e44e1 2439 netif_poll_enable(dev);
baef58b1
SH		 2440 return 0;
2441
2442 free_rx_ring:
2443 skge_rx_clean(skge);
2444 kfree(skge->rx_ring.start);
2445 free_pci_mem:
2446 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2447 skge->mem = NULL;
baef58b1
SH		 2448
2449 return err;
2450}
2451
2452static int skge_down(struct net_device *dev)
2453{
2454 struct skge_port *skge = netdev_priv(dev);
2455 struct skge_hw *hw = skge->hw;
2456 int port = skge->port;
2457
7731a4ea
SH		 2458 if (skge->mem == NULL)
2459 return 0;
2460
baef58b1
SH		 2461 if (netif_msg_ifdown(skge))
2462 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2463
2464 netif_stop_queue(dev);
64f6b64d
SH		 2465 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2466 cancel_rearming_delayed_work(&skge->link_thread);
baef58b1 2467
46a60f2d
SH		 2468 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2469 if (hw->chip_id == CHIP_ID_GENESIS)
2470 genesis_stop(skge);
2471 else
2472 yukon_stop(skge);
2473
baef58b1
SH		 2474 /* Stop transmitter */
2475 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2476 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2477 RB_RST_SET|RB_DIS_OP_MD);
2478
baef58b1
SH		 2479
2480 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2481 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2482 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2483
2484 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2485 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2486 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2487
2488 /* Reset PCI FIFO */
2489 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2490 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2491
2492 /* Reset the RAM Buffer async Tx queue */
2493 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2494 /* stop receiver */
2495 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2496 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2497 RB_RST_SET|RB_DIS_OP_MD);
2498 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2499
2500 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2501 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2502 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2503 } else {
6b0c1480
SH		 2504 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2505 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2506 }
2507
6abebb53 2508 skge_led(skge, LED_MODE_OFF);
baef58b1 2509
239e44e1 2510 netif_poll_disable(dev);
513f533e 2511 skge_tx_clean(dev);
baef58b1
SH		 2512 skge_rx_clean(skge);
2513
2514 kfree(skge->rx_ring.start);
2515 kfree(skge->tx_ring.start);
2516 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2517 skge->mem = NULL;
baef58b1
SH		 2518 return 0;
2519}
2520
29b4e886
SH		 2521static inline int skge_avail(const struct skge_ring *ring)
2522{
2523 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2524 + (ring->to_clean - ring->to_use) - 1;
2525}
2526
baef58b1
SH		 2527static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2528{
2529 struct skge_port *skge = netdev_priv(dev);
2530 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2531 struct skge_element *e;
2532 struct skge_tx_desc *td;
2533 int i;
2534 u32 control, len;
2535 u64 map;
baef58b1 2536
5b057c6b 2537 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2538 return NETDEV_TX_OK;
2539
513f533e 2540 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2541 return NETDEV_TX_BUSY;
baef58b1 2542
7c442fa1 2543 e = skge->tx_ring.to_use;
baef58b1 2544 td = e->desc;
7c442fa1 2545 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2546 e->skb = skb;
2547 len = skb_headlen(skb);
2548 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2549 pci_unmap_addr_set(e, mapaddr, map);
2550 pci_unmap_len_set(e, maplen, len);
2551
2552 td->dma_lo = map;
2553 td->dma_hi = map >> 32;
2554
84fa7933 2555 if (skb->ip_summed == CHECKSUM_PARTIAL) {
baef58b1
SH		 2556 int offset = skb->h.raw - skb->data;
2557
2558 /* This seems backwards, but it is what the sk98lin
2559 * does. Looks like hardware is wrong?
2560 */
ea182d4a 2561 if (skb->h.ipiph->protocol == IPPROTO_UDP
981d0377 2562 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2563 control = BMU_TCP_CHECK;
2564 else
2565 control = BMU_UDP_CHECK;
2566
2567 td->csum_offs = 0;
2568 td->csum_start = offset;
ff1dcadb 2569 td->csum_write = offset + skb->csum_offset;
baef58b1
SH		 2570 } else
2571 control = BMU_CHECK;
2572
2573 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2574 control |= BMU_EOF| BMU_IRQ_EOF;
2575 else {
2576 struct skge_tx_desc *tf = td;
2577
2578 control |= BMU_STFWD;
2579 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2580 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2581
2582 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2583 frag->size, PCI_DMA_TODEVICE);
2584
2585 e = e->next;
7c442fa1 2586 e->skb = skb;
baef58b1 2587 tf = e->desc;
7c442fa1
SH		 2588 BUG_ON(tf->control & BMU_OWN);
2589
baef58b1
SH		 2590 tf->dma_lo = map;
2591 tf->dma_hi = (u64) map >> 32;
2592 pci_unmap_addr_set(e, mapaddr, map);
2593 pci_unmap_len_set(e, maplen, frag->size);
2594
2595 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2596 }
2597 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2598 }
2599 /* Make sure all the descriptors written */
2600 wmb();
2601 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2602 wmb();
2603
2604 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2605
7c442fa1 2606 if (unlikely(netif_msg_tx_queued(skge)))
0b2d7fea 2607 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
7c442fa1 2608 dev->name, e - skge->tx_ring.start, skb->len);
baef58b1 2609
7c442fa1 2610 skge->tx_ring.to_use = e->next;
9db96479 2611 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
baef58b1
SH		 2612 pr_debug("%s: transmit queue full\n", dev->name);
2613 netif_stop_queue(dev);
2614 }
2615
c68ce71a
SH		 2616 dev->trans_start = jiffies;
2617
baef58b1
SH		 2618 return NETDEV_TX_OK;
2619}
2620
7c442fa1
SH		 2621
2622/* Free resources associated with this reing element */
2623static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2624 u32 control)
866b4f3e
SH		 2625{
2626 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2627
7c442fa1 2628 BUG_ON(!e->skb);
866b4f3e 2629
7c442fa1
SH		 2630 /* skb header vs. fragment */
2631 if (control & BMU_STF)
866b4f3e 2632 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
7c442fa1
SH		 2633 pci_unmap_len(e, maplen),
2634 PCI_DMA_TODEVICE);
2635 else
2636 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2637 pci_unmap_len(e, maplen),
2638 PCI_DMA_TODEVICE);
866b4f3e 2639
7c442fa1
SH		 2640 if (control & BMU_EOF) {
2641 if (unlikely(netif_msg_tx_done(skge)))
2642 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2643 skge->netdev->name, e - skge->tx_ring.start);
866b4f3e 2644
513f533e 2645 dev_kfree_skb(e->skb);
baef58b1 2646 }
7c442fa1 2647 e->skb = NULL;
baef58b1
SH		 2648}
2649
7c442fa1 2650/* Free all buffers in transmit ring */
513f533e 2651static void skge_tx_clean(struct net_device *dev)
baef58b1 2652{
513f533e 2653 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2654 struct skge_element *e;
baef58b1 2655
513f533e 2656 netif_tx_lock_bh(dev);
7c442fa1
SH		 2657 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2658 struct skge_tx_desc *td = e->desc;
2659 skge_tx_free(skge, e, td->control);
2660 td->control = 0;
2661 }
2662
2663 skge->tx_ring.to_clean = e;
513f533e
SH		 2664 netif_wake_queue(dev);
2665 netif_tx_unlock_bh(dev);
baef58b1
SH		 2666}
2667
2668static void skge_tx_timeout(struct net_device *dev)
2669{
2670 struct skge_port *skge = netdev_priv(dev);
2671
2672 if (netif_msg_timer(skge))
2673 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2674
2675 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2676 skge_tx_clean(dev);
baef58b1
SH		 2677}
2678
2679static int skge_change_mtu(struct net_device *dev, int new_mtu)
2680{
7731a4ea 2681 int err;
baef58b1 2682
95566065 2683 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2684 return -EINVAL;
2685
7731a4ea
SH		 2686 if (!netif_running(dev)) {
2687 dev->mtu = new_mtu;
2688 return 0;
2689 }
2690
2691 skge_down(dev);
baef58b1 2692
19a33d4e 2693 dev->mtu = new_mtu;
7731a4ea
SH		 2694
2695 err = skge_up(dev);
2696 if (err)
2697 dev_close(dev);
baef58b1
SH		 2698
2699 return err;
2700}
2701
2702static void genesis_set_multicast(struct net_device *dev)
2703{
2704 struct skge_port *skge = netdev_priv(dev);
2705 struct skge_hw *hw = skge->hw;
2706 int port = skge->port;
2707 int i, count = dev->mc_count;
2708 struct dev_mc_list *list = dev->mc_list;
2709 u32 mode;
2710 u8 filter[8];
2711
6b0c1480 2712 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2713 mode |= XM_MD_ENA_HASH;
2714 if (dev->flags & IFF_PROMISC)
2715 mode |= XM_MD_ENA_PROM;
2716 else
2717 mode &= ~XM_MD_ENA_PROM;
2718
2719 if (dev->flags & IFF_ALLMULTI)
2720 memset(filter, 0xff, sizeof(filter));
2721 else {
2722 memset(filter, 0, sizeof(filter));
95566065 2723 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2724 u32 crc, bit;
2725 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2726 bit = ~crc & 0x3f;
baef58b1
SH		 2727 filter[bit/8] |= 1 << (bit%8);
2728 }
2729 }
2730
6b0c1480 2731 xm_write32(hw, port, XM_MODE, mode);
45bada65 2732 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2733}
2734
2735static void yukon_set_multicast(struct net_device *dev)
2736{
2737 struct skge_port *skge = netdev_priv(dev);
2738 struct skge_hw *hw = skge->hw;
2739 int port = skge->port;
2740 struct dev_mc_list *list = dev->mc_list;
2741 u16 reg;
2742 u8 filter[8];
2743
2744 memset(filter, 0, sizeof(filter));
2745
6b0c1480 2746 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2747 reg |= GM_RXCR_UCF_ENA;
2748
8f3f8193 2749 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2750 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2751 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2752 memset(filter, 0xff, sizeof(filter));
2753 else if (dev->mc_count == 0) /* no multicast */
2754 reg &= ~GM_RXCR_MCF_ENA;
2755 else {
2756 int i;
2757 reg |= GM_RXCR_MCF_ENA;
2758
95566065 2759 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2760 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2761 filter[bit/8] |= 1 << (bit%8);
2762 }
2763 }
2764
2765
6b0c1480 2766 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2767 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2768 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2769 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2770 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2771 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2772 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2773 (u16)filter[6] | ((u16)filter[7] << 8));
2774
6b0c1480 2775 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2776}
2777
383181ac
SH		 2778static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2779{
2780 if (hw->chip_id == CHIP_ID_GENESIS)
2781 return status >> XMR_FS_LEN_SHIFT;
2782 else
2783 return status >> GMR_FS_LEN_SHIFT;
2784}
2785
baef58b1
SH		 2786static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2787{
2788 if (hw->chip_id == CHIP_ID_GENESIS)
2789 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2790 else
2791 return (status & GMR_FS_ANY_ERR) ||
2792 (status & GMR_FS_RX_OK) == 0;
2793}
2794
19a33d4e
SH		 2795
2796/* Get receive buffer from descriptor.
2797 * Handles copy of small buffers and reallocation failures
2798 */
c54f9765
SH		 2799static struct sk_buff *skge_rx_get(struct net_device *dev,
2800 struct skge_element *e,
2801 u32 control, u32 status, u16 csum)
19a33d4e 2802{
c54f9765 2803 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 2804 struct sk_buff *skb;
2805 u16 len = control & BMU_BBC;
2806
2807 if (unlikely(netif_msg_rx_status(skge)))
2808 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
c54f9765 2809 dev->name, e - skge->rx_ring.start,
383181ac
SH		 2810 status, len);
2811
2812 if (len > skge->rx_buf_size)
2813 goto error;
2814
2815 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2816 goto error;
2817
2818 if (bad_phy_status(skge->hw, status))
2819 goto error;
2820
2821 if (phy_length(skge->hw, status) != len)
2822 goto error;
19a33d4e
SH		 2823
2824 if (len < RX_COPY_THRESHOLD) {
c54f9765 2825 skb = netdev_alloc_skb(dev, len + 2);
383181ac
SH		 2826 if (!skb)
2827 goto resubmit;
19a33d4e 2828
383181ac 2829 skb_reserve(skb, 2);
19a33d4e
SH		 2830 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2831 pci_unmap_addr(e, mapaddr),
2832 len, PCI_DMA_FROMDEVICE);
383181ac 2833 memcpy(skb->data, e->skb->data, len);
19a33d4e
SH		 2834 pci_dma_sync_single_for_device(skge->hw->pdev,
2835 pci_unmap_addr(e, mapaddr),
2836 len, PCI_DMA_FROMDEVICE);
19a33d4e 2837 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 2838 } else {
383181ac 2839 struct sk_buff *nskb;
c54f9765 2840 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
383181ac
SH		 2841 if (!nskb)
2842 goto resubmit;
19a33d4e 2843
901ccefb 2844 skb_reserve(nskb, NET_IP_ALIGN);
19a33d4e
SH		 2845 pci_unmap_single(skge->hw->pdev,
2846 pci_unmap_addr(e, mapaddr),
2847 pci_unmap_len(e, maplen),
2848 PCI_DMA_FROMDEVICE);
2849 skb = e->skb;
383181ac 2850 prefetch(skb->data);
19a33d4e 2851 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 2852 }
383181ac
SH		 2853
2854 skb_put(skb, len);
383181ac
SH		 2855 if (skge->rx_csum) {
2856 skb->csum = csum;
84fa7933 2857 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 2858 }
2859
c54f9765 2860 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 2861
2862 return skb;
2863error:
2864
2865 if (netif_msg_rx_err(skge))
2866 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
c54f9765 2867 dev->name, e - skge->rx_ring.start,
383181ac
SH		 2868 control, status);
2869
2870 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2871 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2872 skge->net_stats.rx_length_errors++;
2873 if (status & XMR_FS_FRA_ERR)
2874 skge->net_stats.rx_frame_errors++;
2875 if (status & XMR_FS_FCS_ERR)
2876 skge->net_stats.rx_crc_errors++;
2877 } else {
2878 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2879 skge->net_stats.rx_length_errors++;
2880 if (status & GMR_FS_FRAGMENT)
2881 skge->net_stats.rx_frame_errors++;
2882 if (status & GMR_FS_CRC_ERR)
2883 skge->net_stats.rx_crc_errors++;
2884 }
2885
2886resubmit:
2887 skge_rx_reuse(e, skge->rx_buf_size);
2888 return NULL;
baef58b1
SH		 2889}
2890
7c442fa1 2891/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 2892static void skge_tx_done(struct net_device *dev)
00a6cae2 2893{
7c442fa1 2894 struct skge_port *skge = netdev_priv(dev);
00a6cae2 2895 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 2896 struct skge_element *e;
2897
513f533e 2898 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 2899
513f533e 2900 netif_tx_lock(dev);
866b4f3e 2901 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
00a6cae2 2902 struct skge_tx_desc *td = e->desc;
00a6cae2 2903
866b4f3e 2904 if (td->control & BMU_OWN)
00a6cae2
SH		 2905 break;
2906
7c442fa1 2907 skge_tx_free(skge, e, td->control);
00a6cae2 2908 }
7c442fa1 2909 skge->tx_ring.to_clean = e;
866b4f3e 2910
513f533e
SH		 2911 if (skge_avail(&skge->tx_ring) > TX_LOW_WATER)
2912 netif_wake_queue(dev);
00a6cae2 2913
513f533e 2914 netif_tx_unlock(dev);
00a6cae2 2915}
19a33d4e 2916
baef58b1
SH		 2917static int skge_poll(struct net_device *dev, int *budget)
2918{
2919 struct skge_port *skge = netdev_priv(dev);
2920 struct skge_hw *hw = skge->hw;
2921 struct skge_ring *ring = &skge->rx_ring;
2922 struct skge_element *e;
00a6cae2
SH		 2923 int to_do = min(dev->quota, *budget);
2924 int work_done = 0;
2925
513f533e
SH		 2926 skge_tx_done(dev);
2927
2928 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2929
1631aef1 2930 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 2931 struct skge_rx_desc *rd = e->desc;
19a33d4e 2932 struct sk_buff *skb;
383181ac 2933 u32 control;
baef58b1
SH		 2934
2935 rmb();
2936 control = rd->control;
2937 if (control & BMU_OWN)
2938 break;
2939
c54f9765 2940 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 2941 if (likely(skb)) {
19a33d4e
SH		 2942 dev->last_rx = jiffies;
2943 netif_receive_skb(skb);
baef58b1 2944
19a33d4e 2945 ++work_done;
5a011447 2946 }
baef58b1
SH		 2947 }
2948 ring->to_clean = e;
2949
baef58b1
SH		 2950 /* restart receiver */
2951 wmb();
a9cdab86 2952 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 2953
19a33d4e
SH		 2954 *budget -= work_done;
2955 dev->quota -= work_done;
2956
2957 if (work_done >= to_do)
2958 return 1; /* not done */
baef58b1 2959
7c442fa1 2960 spin_lock_irq(&hw->hw_lock);
513f533e
SH		 2961 __netif_rx_complete(dev);
2962 hw->intr_mask |= irqmask[skge->port];
80dd857d 2963 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 2964 skge_read32(hw, B0_IMSK);
7c442fa1 2965 spin_unlock_irq(&hw->hw_lock);
1631aef1 2966
19a33d4e 2967 return 0;
baef58b1
SH		 2968}
2969
f6620cab
SH		 2970/* Parity errors seem to happen when Genesis is connected to a switch
2971 * with no other ports present. Heartbeat error??
2972 */
baef58b1
SH		 2973static void skge_mac_parity(struct skge_hw *hw, int port)
2974{
f6620cab
SH		 2975 struct net_device *dev = hw->dev[port];
2976
2977 if (dev) {
2978 struct skge_port *skge = netdev_priv(dev);
2979 ++skge->net_stats.tx_heartbeat_errors;
2980 }
baef58b1
SH		 2981
2982 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2983 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2984 MFF_CLR_PERR);
2985 else
2986 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2987 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2988 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2989 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2990}
2991
baef58b1
SH		 2992static void skge_mac_intr(struct skge_hw *hw, int port)
2993{
95566065 2994 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2995 genesis_mac_intr(hw, port);
2996 else
2997 yukon_mac_intr(hw, port);
2998}
2999
3000/* Handle device specific framing and timeout interrupts */
3001static void skge_error_irq(struct skge_hw *hw)
3002{
3003 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3004
3005 if (hw->chip_id == CHIP_ID_GENESIS) {
3006 /* clear xmac errors */
3007 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3008 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3009 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3010 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3011 } else {
3012 /* Timestamp (unused) overflow */
3013 if (hwstatus & IS_IRQ_TIST_OV)
3014 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3015 }
3016
3017 if (hwstatus & IS_RAM_RD_PAR) {
3018 printk(KERN_ERR PFX "Ram read data parity error\n");
3019 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3020 }
3021
3022 if (hwstatus & IS_RAM_WR_PAR) {
3023 printk(KERN_ERR PFX "Ram write data parity error\n");
3024 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3025 }
3026
3027 if (hwstatus & IS_M1_PAR_ERR)
3028 skge_mac_parity(hw, 0);
3029
3030 if (hwstatus & IS_M2_PAR_ERR)
3031 skge_mac_parity(hw, 1);
3032
b9d64acc
SH		 3033 if (hwstatus & IS_R1_PAR_ERR) {
3034 printk(KERN_ERR PFX "%s: receive queue parity error\n",
3035 hw->dev[0]->name);
baef58b1 3036 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3037 }
baef58b1 3038
b9d64acc
SH		 3039 if (hwstatus & IS_R2_PAR_ERR) {
3040 printk(KERN_ERR PFX "%s: receive queue parity error\n",
3041 hw->dev[1]->name);
baef58b1 3042 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3043 }
baef58b1
SH		 3044
3045 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3046 u16 pci_status, pci_cmd;
3047
3048 pci_read_config_word(hw->pdev, PCI_COMMAND, &pci_cmd);
3049 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
baef58b1 3050
b9d64acc
SH		 3051 printk(KERN_ERR PFX "%s: PCI error cmd=%#x status=%#x\n",
3052 pci_name(hw->pdev), pci_cmd, pci_status);
3053
3054 /* Write the error bits back to clear them. */
3055 pci_status &= PCI_STATUS_ERROR_BITS;
3056 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3057 pci_write_config_word(hw->pdev, PCI_COMMAND,
3058 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3059 pci_write_config_word(hw->pdev, PCI_STATUS, pci_status);
3060 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3061
050ec18a 3062 /* if error still set then just ignore it */
baef58b1
SH		 3063 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3064 if (hwstatus & IS_IRQ_STAT) {
b9d64acc 3065 printk(KERN_INFO PFX "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3066 hw->intr_mask &= ~IS_HW_ERR;
3067 }
3068 }
3069}
3070
3071/*
d85b514f 3072 * Interrupt from PHY are handled in work queue
baef58b1
SH		 3073 * because accessing phy registers requires spin wait which might
3074 * cause excess interrupt latency.
3075 */
c4028958 3076static void skge_extirq(struct work_struct *work)
baef58b1 3077{
c4028958 3078 struct skge_hw *hw = container_of(work, struct skge_hw, phy_work);
baef58b1
SH		 3079 int port;
3080
d85b514f 3081 mutex_lock(&hw->phy_mutex);
cfc3ed79 3082 for (port = 0; port < hw->ports; port++) {
baef58b1 3083 struct net_device *dev = hw->dev[port];
cfc3ed79 3084 struct skge_port *skge = netdev_priv(dev);
baef58b1 3085
cfc3ed79 3086 if (netif_running(dev)) {
baef58b1
SH		 3087 if (hw->chip_id != CHIP_ID_GENESIS)
3088 yukon_phy_intr(skge);
64f6b64d 3089 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3090 bcom_phy_intr(skge);
baef58b1
SH		 3091 }
3092 }
d85b514f 3093 mutex_unlock(&hw->phy_mutex);
baef58b1 3094
7c442fa1 3095 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3096 hw->intr_mask |= IS_EXT_REG;
3097 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3098 skge_read32(hw, B0_IMSK);
7c442fa1 3099 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3100}
3101
7d12e780 3102static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3103{
3104 struct skge_hw *hw = dev_id;
cfc3ed79 3105 u32 status;
29365c90 3106 int handled = 0;
baef58b1 3107
29365c90 3108 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3109 /* Reading this register masks IRQ */
3110 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3111 if (status == 0 || status == ~0)
29365c90 3112 goto out;
baef58b1 3113
29365c90 3114 handled = 1;
7c442fa1 3115 status &= hw->intr_mask;
cfc3ed79
SH		 3116 if (status & IS_EXT_REG) {
3117 hw->intr_mask &= ~IS_EXT_REG;
d85b514f 3118 schedule_work(&hw->phy_work);
cfc3ed79
SH		 3119 }
3120
513f533e
SH		 3121 if (status & (IS_XA1_F|IS_R1_F)) {
3122 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
7c442fa1 3123 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 3124 }
3125
7c442fa1
SH		 3126 if (status & IS_PA_TO_TX1)
3127 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3128
d25f5a67
SH		 3129 if (status & IS_PA_TO_RX1) {
3130 struct skge_port *skge = netdev_priv(hw->dev[0]);
d25f5a67 3131
d25f5a67 3132 ++skge->net_stats.rx_over_errors;
7c442fa1 3133 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3134 }
3135
d25f5a67 3136
baef58b1
SH		 3137 if (status & IS_MAC1)
3138 skge_mac_intr(hw, 0);
95566065 3139
7c442fa1 3140 if (hw->dev[1]) {
513f533e
SH		 3141 if (status & (IS_XA2_F|IS_R2_F)) {
3142 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
7c442fa1
SH		 3143 netif_rx_schedule(hw->dev[1]);
3144 }
3145
3146 if (status & IS_PA_TO_RX2) {
3147 struct skge_port *skge = netdev_priv(hw->dev[1]);
3148 ++skge->net_stats.rx_over_errors;
3149 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3150 }
3151
3152 if (status & IS_PA_TO_TX2)
3153 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3154
3155 if (status & IS_MAC2)
3156 skge_mac_intr(hw, 1);
3157 }
baef58b1
SH		 3158
3159 if (status & IS_HW_ERR)
3160 skge_error_irq(hw);
3161
7e676d91 3162 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3163 skge_read32(hw, B0_IMSK);
29365c90 3164out:
7c442fa1 3165 spin_unlock(&hw->hw_lock);
baef58b1 3166
29365c90 3167 return IRQ_RETVAL(handled);
baef58b1
SH		 3168}
3169
3170#ifdef CONFIG_NET_POLL_CONTROLLER
3171static void skge_netpoll(struct net_device *dev)
3172{
3173 struct skge_port *skge = netdev_priv(dev);
3174
3175 disable_irq(dev->irq);
7d12e780 3176 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3177 enable_irq(dev->irq);
3178}
3179#endif
3180
3181static int skge_set_mac_address(struct net_device *dev, void *p)
3182{
3183 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3184 struct skge_hw *hw = skge->hw;
3185 unsigned port = skge->port;
3186 const struct sockaddr *addr = p;
baef58b1
SH		 3187
3188 if (!is_valid_ether_addr(addr->sa_data))
3189 return -EADDRNOTAVAIL;
3190
d85b514f 3191 mutex_lock(&hw->phy_mutex);
baef58b1 3192 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3193 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
baef58b1 3194 dev->dev_addr, ETH_ALEN);
c2681dd8 3195 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
baef58b1 3196 dev->dev_addr, ETH_ALEN);
c2681dd8
SH		 3197
3198 if (hw->chip_id == CHIP_ID_GENESIS)
3199 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3200 else {
3201 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3202 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3203 }
d85b514f 3204 mutex_unlock(&hw->phy_mutex);
c2681dd8
SH		 3205
3206 return 0;
baef58b1
SH		 3207}
3208
3209static const struct {
3210 u8 id;
3211 const char *name;
3212} skge_chips[] = {
3213 { CHIP_ID_GENESIS, "Genesis" },
3214 { CHIP_ID_YUKON, "Yukon" },
3215 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3216 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3217};
3218
3219static const char *skge_board_name(const struct skge_hw *hw)
3220{
3221 int i;
3222 static char buf[16];
3223
3224 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3225 if (skge_chips[i].id == hw->chip_id)
3226 return skge_chips[i].name;
3227
3228 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3229 return buf;
3230}
3231
3232
3233/*
3234 * Setup the board data structure, but don't bring up
3235 * the port(s)
3236 */
3237static int skge_reset(struct skge_hw *hw)
3238{
adba9e23 3239 u32 reg;
b9d64acc 3240 u16 ctst, pci_status;
64f6b64d 3241 u8 t8, mac_cfg, pmd_type;
981d0377 3242 int i;
baef58b1
SH		 3243
3244 ctst = skge_read16(hw, B0_CTST);
3245
3246 /* do a SW reset */
3247 skge_write8(hw, B0_CTST, CS_RST_SET);
3248 skge_write8(hw, B0_CTST, CS_RST_CLR);
3249
3250 /* clear PCI errors, if any */
b9d64acc
SH		 3251 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3252 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3253
b9d64acc
SH		 3254 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3255 pci_write_config_word(hw->pdev, PCI_STATUS,
3256 pci_status | PCI_STATUS_ERROR_BITS);
3257 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3258 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3259
3260 /* restore CLK_RUN bits (for Yukon-Lite) */
3261 skge_write16(hw, B0_CTST,
3262 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3263
3264 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3265 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3266 pmd_type = skge_read8(hw, B2_PMD_TYP);
3267 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3268
95566065 3269 switch (hw->chip_id) {
baef58b1 3270 case CHIP_ID_GENESIS:
64f6b64d
SH		 3271 switch (hw->phy_type) {
3272 case SK_PHY_XMAC:
3273 hw->phy_addr = PHY_ADDR_XMAC;
3274 break;
baef58b1
SH		 3275 case SK_PHY_BCOM:
3276 hw->phy_addr = PHY_ADDR_BCOM;
3277 break;
3278 default:
3279 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
64f6b64d 3280 pci_name(hw->pdev), hw->phy_type);
baef58b1
SH		 3281 return -EOPNOTSUPP;
3282 }
3283 break;
3284
3285 case CHIP_ID_YUKON:
3286 case CHIP_ID_YUKON_LITE:
3287 case CHIP_ID_YUKON_LP:
64f6b64d 3288 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3289 hw->copper = 1;
baef58b1
SH		 3290
3291 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3292 break;
3293
3294 default:
3295 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3296 pci_name(hw->pdev), hw->chip_id);
3297 return -EOPNOTSUPP;
3298 }
3299
981d0377
SH		 3300 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3301 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3302 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3303
3304 /* read the adapters RAM size */
3305 t8 = skge_read8(hw, B2_E_0);
3306 if (hw->chip_id == CHIP_ID_GENESIS) {
3307 if (t8 == 3) {
3308 /* special case: 4 x 64k x 36, offset = 0x80000 */
3309 hw->ram_size = 0x100000;
3310 hw->ram_offset = 0x80000;
3311 } else
3312 hw->ram_size = t8 * 512;
3313 }
3314 else if (t8 == 0)
3315 hw->ram_size = 0x20000;
3316 else
3317 hw->ram_size = t8 * 4096;
3318
64f6b64d 3319 hw->intr_mask = IS_HW_ERR | IS_PORT_1;
cfc3ed79
SH		 3320 if (hw->ports > 1)
3321 hw->intr_mask |= IS_PORT_2;
3322
64f6b64d
SH		 3323 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3324 hw->intr_mask |= IS_EXT_REG;
3325
baef58b1
SH		 3326 if (hw->chip_id == CHIP_ID_GENESIS)
3327 genesis_init(hw);
3328 else {
3329 /* switch power to VCC (WA for VAUX problem) */
3330 skge_write8(hw, B0_POWER_CTRL,
3331 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3332
050ec18a
SH		 3333 /* avoid boards with stuck Hardware error bits */
3334 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3335 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3336 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3337 hw->intr_mask &= ~IS_HW_ERR;
3338 }
3339
adba9e23
SH		 3340 /* Clear PHY COMA */
3341 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3342 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3343 reg &= ~PCI_PHY_COMA;
3344 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3345 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3346
3347
981d0377 3348 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3349 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3350 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3351 }
3352 }
3353
3354 /* turn off hardware timer (unused) */
3355 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3356 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3357 skge_write8(hw, B0_LED, LED_STAT_ON);
3358
3359 /* enable the Tx Arbiters */
981d0377 3360 for (i = 0; i < hw->ports; i++)
6b0c1480 3361 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3362
3363 /* Initialize ram interface */
3364 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3365
3366 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3367 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3368 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3369 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3370 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3371 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3372 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3373 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3374 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3375 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3376 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3377 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3378
3379 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3380
3381 /* Set interrupt moderation for Transmit only
3382 * Receive interrupts avoided by NAPI
3383 */
3384 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3385 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3386 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3387
baef58b1
SH		 3388 skge_write32(hw, B0_IMSK, hw->intr_mask);
3389
d85b514f 3390 mutex_lock(&hw->phy_mutex);
981d0377 3391 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3392 if (hw->chip_id == CHIP_ID_GENESIS)
3393 genesis_reset(hw, i);
3394 else
3395 yukon_reset(hw, i);
3396 }
d85b514f 3397 mutex_unlock(&hw->phy_mutex);
baef58b1
SH		 3398
3399 return 0;
3400}
3401
3402/* Initialize network device */
981d0377
SH		 3403static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3404 int highmem)
baef58b1
SH		 3405{
3406 struct skge_port *skge;
3407 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3408
3409 if (!dev) {
3410 printk(KERN_ERR "skge etherdev alloc failed");
3411 return NULL;
3412 }
3413
3414 SET_MODULE_OWNER(dev);
3415 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3416 dev->open = skge_up;
3417 dev->stop = skge_down;
2cd8e5d3 3418 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3419 dev->hard_start_xmit = skge_xmit_frame;
3420 dev->get_stats = skge_get_stats;
3421 if (hw->chip_id == CHIP_ID_GENESIS)
3422 dev->set_multicast_list = genesis_set_multicast;
3423 else
3424 dev->set_multicast_list = yukon_set_multicast;
3425
3426 dev->set_mac_address = skge_set_mac_address;
3427 dev->change_mtu = skge_change_mtu;
3428 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3429 dev->tx_timeout = skge_tx_timeout;
3430 dev->watchdog_timeo = TX_WATCHDOG;
3431 dev->poll = skge_poll;
3432 dev->weight = NAPI_WEIGHT;
3433#ifdef CONFIG_NET_POLL_CONTROLLER
3434 dev->poll_controller = skge_netpoll;
3435#endif
3436 dev->irq = hw->pdev->irq;
513f533e 3437
981d0377
SH		 3438 if (highmem)
3439 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3440
3441 skge = netdev_priv(dev);
3442 skge->netdev = dev;
3443 skge->hw = hw;
3444 skge->msg_enable = netif_msg_init(debug, default_msg);
3445 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3446 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3447
3448 /* Auto speed and flow control */
3449 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3450 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3451 skge->duplex = -1;
3452 skge->speed = -1;
31b619c5 3453 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3454
3455 hw->dev[port] = dev;
3456
3457 skge->port = port;
3458
64f6b64d 3459 /* Only used for Genesis XMAC */
c4028958 3460 INIT_DELAYED_WORK(&skge->link_thread, xm_link_timer);
64f6b64d 3461
baef58b1
SH		 3462 if (hw->chip_id != CHIP_ID_GENESIS) {
3463 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3464 skge->rx_csum = 1;
3465 }
3466
3467 /* read the mac address */
3468 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3469 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3470
3471 /* device is off until link detection */
3472 netif_carrier_off(dev);
3473 netif_stop_queue(dev);
3474
3475 return dev;
3476}
3477
3478static void __devinit skge_show_addr(struct net_device *dev)
3479{
3480 const struct skge_port *skge = netdev_priv(dev);
3481
3482 if (netif_msg_probe(skge))
3483 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3484 dev->name,
3485 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3486 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3487}
3488
3489static int __devinit skge_probe(struct pci_dev *pdev,
3490 const struct pci_device_id *ent)
3491{
3492 struct net_device *dev, *dev1;
3493 struct skge_hw *hw;
3494 int err, using_dac = 0;
3495
203babb6
SH		 3496 err = pci_enable_device(pdev);
3497 if (err) {
baef58b1
SH		 3498 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3499 pci_name(pdev));
3500 goto err_out;
3501 }
3502
203babb6
SH		 3503 err = pci_request_regions(pdev, DRV_NAME);
3504 if (err) {
baef58b1
SH		 3505 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3506 pci_name(pdev));
3507 goto err_out_disable_pdev;
3508 }
3509
3510 pci_set_master(pdev);
3511
93aea718 3512 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
baef58b1 3513 using_dac = 1;
77783a78 3514 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
93aea718
SH		 3515 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3516 using_dac = 0;
3517 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3518 }
3519
3520 if (err) {
3521 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3522 pci_name(pdev));
3523 goto err_out_free_regions;
baef58b1
SH		 3524 }
3525
3526#ifdef __BIG_ENDIAN
8f3f8193 3527 /* byte swap descriptors in hardware */
baef58b1
SH		 3528 {
3529 u32 reg;
3530
3531 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3532 reg |= PCI_REV_DESC;
3533 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3534 }
3535#endif
3536
3537 err = -ENOMEM;
7e863061 3538 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1
SH		 3539 if (!hw) {
3540 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3541 pci_name(pdev));
3542 goto err_out_free_regions;
3543 }
3544
baef58b1 3545 hw->pdev = pdev;
d85b514f 3546 mutex_init(&hw->phy_mutex);
c4028958 3547 INIT_WORK(&hw->phy_work, skge_extirq);
d38efdd6 3548 spin_lock_init(&hw->hw_lock);
baef58b1
SH		 3549
3550 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3551 if (!hw->regs) {
3552 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3553 pci_name(pdev));
3554 goto err_out_free_hw;
3555 }
3556
baef58b1
SH		 3557 err = skge_reset(hw);
3558 if (err)
ccdaa2a9 3559 goto err_out_iounmap;
baef58b1 3560
7c7459d1
GKH		 3561 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3562 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
981d0377 3563 skge_board_name(hw), hw->chip_rev);
baef58b1 3564
ccdaa2a9
SH		 3565 dev = skge_devinit(hw, 0, using_dac);
3566 if (!dev)
baef58b1
SH		 3567 goto err_out_led_off;
3568
631ae320
SH		 3569 if (!is_valid_ether_addr(dev->dev_addr)) {
3570 printk(KERN_ERR PFX "%s: bad (zero?) ethernet address in rom\n",
3571 pci_name(pdev));
3572 err = -EIO;
3573 goto err_out_free_netdev;
3574 }
3575
203babb6
SH		 3576 err = register_netdev(dev);
3577 if (err) {
baef58b1
SH		 3578 printk(KERN_ERR PFX "%s: cannot register net device\n",
3579 pci_name(pdev));
3580 goto err_out_free_netdev;
3581 }
3582
ccdaa2a9
SH		 3583 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3584 if (err) {
3585 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3586 dev->name, pdev->irq);
3587 goto err_out_unregister;
3588 }
baef58b1
SH		 3589 skge_show_addr(dev);
3590
981d0377 3591 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3592 if (register_netdev(dev1) == 0)
3593 skge_show_addr(dev1);
3594 else {
3595 /* Failure to register second port need not be fatal */
3596 printk(KERN_WARNING PFX "register of second port failed\n");
3597 hw->dev[1] = NULL;
3598 free_netdev(dev1);
3599 }
3600 }
ccdaa2a9 3601 pci_set_drvdata(pdev, hw);
baef58b1
SH		 3602
3603 return 0;
3604
ccdaa2a9
SH		 3605err_out_unregister:
3606 unregister_netdev(dev);
baef58b1
SH		 3607err_out_free_netdev:
3608 free_netdev(dev);
3609err_out_led_off:
3610 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 3611err_out_iounmap:
3612 iounmap(hw->regs);
3613err_out_free_hw:
3614 kfree(hw);
3615err_out_free_regions:
3616 pci_release_regions(pdev);
3617err_out_disable_pdev:
3618 pci_disable_device(pdev);
3619 pci_set_drvdata(pdev, NULL);
3620err_out:
3621 return err;
3622}
3623
3624static void __devexit skge_remove(struct pci_dev *pdev)
3625{
3626 struct skge_hw *hw = pci_get_drvdata(pdev);
3627 struct net_device *dev0, *dev1;
3628
95566065 3629 if (!hw)
baef58b1
SH		 3630 return;
3631
3632 if ((dev1 = hw->dev[1]))
3633 unregister_netdev(dev1);
3634 dev0 = hw->dev[0];
3635 unregister_netdev(dev0);
3636
7c442fa1
SH		 3637 spin_lock_irq(&hw->hw_lock);
3638 hw->intr_mask = 0;
46a60f2d 3639 skge_write32(hw, B0_IMSK, 0);
78bc2186 3640 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 3641 spin_unlock_irq(&hw->hw_lock);
3642
46a60f2d 3643 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 3644 skge_write8(hw, B0_CTST, CS_RST_SET);
3645
d85b514f 3646 flush_scheduled_work();
baef58b1
SH		 3647
3648 free_irq(pdev->irq, hw);
3649 pci_release_regions(pdev);
3650 pci_disable_device(pdev);
3651 if (dev1)
3652 free_netdev(dev1);
3653 free_netdev(dev0);
46a60f2d 3654
baef58b1
SH		 3655 iounmap(hw->regs);
3656 kfree(hw);
3657 pci_set_drvdata(pdev, NULL);
3658}
3659
3660#ifdef CONFIG_PM
2a569579 3661static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3662{
3663 struct skge_hw *hw = pci_get_drvdata(pdev);
3664 int i, wol = 0;
3665
d38efdd6
SH		 3666 pci_save_state(pdev);
3667 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3668 struct net_device *dev = hw->dev[i];
3669
d38efdd6 3670 if (netif_running(dev)) {
baef58b1 3671 struct skge_port *skge = netdev_priv(dev);
d38efdd6
SH		 3672
3673 netif_carrier_off(dev);
3674 if (skge->wol)
3675 netif_stop_queue(dev);
3676 else
3677 skge_down(dev);
baef58b1
SH		 3678 wol |= skge->wol;
3679 }
d38efdd6 3680 netif_device_detach(dev);
baef58b1
SH		 3681 }
3682
d38efdd6 3683 skge_write32(hw, B0_IMSK, 0);
2a569579 3684 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3685 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3686
3687 return 0;
3688}
3689
3690static int skge_resume(struct pci_dev *pdev)
3691{
3692 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 3693 int i, err;
baef58b1
SH		 3694
3695 pci_set_power_state(pdev, PCI_D0);
3696 pci_restore_state(pdev);
3697 pci_enable_wake(pdev, PCI_D0, 0);
3698
d38efdd6
SH		 3699 err = skge_reset(hw);
3700 if (err)
3701 goto out;
baef58b1 3702
d38efdd6 3703 for (i = 0; i < hw->ports; i++) {
baef58b1 3704 struct net_device *dev = hw->dev[i];
d38efdd6
SH		 3705
3706 netif_device_attach(dev);
3707 if (netif_running(dev)) {
3708 err = skge_up(dev);
3709
3710 if (err) {
3711 printk(KERN_ERR PFX "%s: could not up: %d\n",
3712 dev->name, err);
edd702e8 3713 dev_close(dev);
d38efdd6
SH		 3714 goto out;
3715 }
baef58b1
SH		 3716 }
3717 }
d38efdd6
SH		 3718out:
3719 return err;
baef58b1
SH		 3720}
3721#endif
3722
3723static struct pci_driver skge_driver = {
3724 .name = DRV_NAME,
3725 .id_table = skge_id_table,
3726 .probe = skge_probe,
3727 .remove = __devexit_p(skge_remove),
3728#ifdef CONFIG_PM
3729 .suspend = skge_suspend,
3730 .resume = skge_resume,
3731#endif
3732};
3733
3734static int __init skge_init_module(void)
3735{
29917620 3736 return pci_register_driver(&skge_driver);
baef58b1
SH		 3737}
3738
3739static void __exit skge_cleanup_module(void)
3740{
3741 pci_unregister_driver(&skge_driver);
3742}
3743
3744module_init(skge_init_module);
3745module_exit(skge_cleanup_module);
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