]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/net/skge.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
sky2: phy workarounds for Yukon EC-U A1
[mirror_ubuntu-artful-kernel.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
798b6b19 14 * the Free Software Foundation; either version 2 of the License.
baef58b1
SH		 15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
14c85021 26#include <linux/in.h>
baef58b1
SH		 27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include <linux/netdevice.h>
31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/if_vlan.h>
35#include <linux/ip.h>
36#include <linux/delay.h>
37#include <linux/crc32.h>
4075400b 38#include <linux/dma-mapping.h>
2cd8e5d3 39#include <linux/mii.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
a407a6a0 45#define DRV_VERSION "1.10"
baef58b1
SH		 46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
9db96479 51#define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
baef58b1 52#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 53#define RX_COPY_THRESHOLD 128
54#define RX_BUF_SIZE 1536
baef58b1
SH		 55#define PHY_RETRIES 1000
56#define ETH_JUMBO_MTU 9000
57#define TX_WATCHDOG (5 * HZ)
58#define NAPI_WEIGHT 64
6abebb53 59#define BLINK_MS 250
64f6b64d 60#define LINK_HZ (HZ/2)
baef58b1
SH		 61
62MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
65ebe634 63MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
baef58b1
SH		 64MODULE_LICENSE("GPL");
65MODULE_VERSION(DRV_VERSION);
66
67static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71static int debug = -1; /* defaults above */
72module_param(debug, int, 0);
73MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
f19841f5 80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
2d2a3871 81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
275834d1
SH		 82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
f19841f5 86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
baef58b1
SH		 87 { 0 }
88};
89MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91static int skge_up(struct net_device *dev);
92static int skge_down(struct net_device *dev);
ee294dcd 93static void skge_phy_reset(struct skge_port *skge);
513f533e 94static void skge_tx_clean(struct net_device *dev);
2cd8e5d3
SH		 95static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 97static void genesis_get_stats(struct skge_port *skge, u64 *data);
98static void yukon_get_stats(struct skge_port *skge, u64 *data);
99static void yukon_init(struct skge_hw *hw, int port);
baef58b1 100static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 101static void genesis_link_up(struct skge_port *skge);
baef58b1 102
7e676d91 103/* Avoid conditionals by using array */
baef58b1
SH		 104static const int txqaddr[] = { Q_XA1, Q_XA2 };
105static const int rxqaddr[] = { Q_R1, Q_R2 };
106static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
4ebabfcb
SH		 108static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
109static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 110
baef58b1
SH		 111static int skge_get_regs_len(struct net_device *dev)
112{
c3f8be96 113 return 0x4000;
baef58b1
SH		 114}
115
116/*
c3f8be96
SH		 117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
119 * cause bus hangs!
baef58b1
SH		 120 */
121static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
122 void *p)
123{
124 const struct skge_port *skge = netdev_priv(dev);
baef58b1 125 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 126
127 regs->version = 1;
c3f8be96
SH		 128 memset(p, 0, regs->len);
129 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 130
c3f8be96
SH		 131 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
132 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 133}
134
8f3f8193 135/* Wake on Lan only supported on Yukon chips with rev 1 or above */
a504e64a 136static u32 wol_supported(const struct skge_hw *hw)
baef58b1 137{
a504e64a
SH		 138 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev != 0)
139 return WAKE_MAGIC | WAKE_PHY;
140 else
141 return 0;
142}
143
144static u32 pci_wake_enabled(struct pci_dev *dev)
145{
146 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
147 u16 value;
148
149 /* If device doesn't support PM Capabilities, but request is to disable
150 * wake events, it's a nop; otherwise fail */
151 if (!pm)
152 return 0;
153
154 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
155
156 value &= PCI_PM_CAP_PME_MASK;
157 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
158
159 return value != 0;
160}
161
162static void skge_wol_init(struct skge_port *skge)
163{
164 struct skge_hw *hw = skge->hw;
165 int port = skge->port;
166 enum pause_control save_mode;
167 u32 ctrl;
168
169 /* Bring hardware out of reset */
170 skge_write16(hw, B0_CTST, CS_RST_CLR);
171 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
172
173 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
174 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
175
176 /* Force to 10/100 skge_reset will re-enable on resume */
177 save_mode = skge->flow_control;
178 skge->flow_control = FLOW_MODE_SYMMETRIC;
179
180 ctrl = skge->advertising;
181 skge->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
182
183 skge_phy_reset(skge);
184
185 skge->flow_control = save_mode;
186 skge->advertising = ctrl;
187
188 /* Set GMAC to no flow control and auto update for speed/duplex */
189 gma_write16(hw, port, GM_GP_CTRL,
190 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
191 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
192
193 /* Set WOL address */
194 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
195 skge->netdev->dev_addr, ETH_ALEN);
196
197 /* Turn on appropriate WOL control bits */
198 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
199 ctrl = 0;
200 if (skge->wol & WAKE_PHY)
201 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
202 else
203 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
204
205 if (skge->wol & WAKE_MAGIC)
206 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
207 else
208 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
209
210 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
211 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
212
213 /* block receiver */
214 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 215}
216
217static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
218{
219 struct skge_port *skge = netdev_priv(dev);
220
a504e64a
SH		 221 wol->supported = wol_supported(skge->hw);
222 wol->wolopts = skge->wol;
baef58b1
SH		 223}
224
225static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
226{
227 struct skge_port *skge = netdev_priv(dev);
228 struct skge_hw *hw = skge->hw;
229
a504e64a 230 if (wol->wolopts & wol_supported(hw))
baef58b1
SH		 231 return -EOPNOTSUPP;
232
a504e64a
SH		 233 skge->wol = wol->wolopts;
234 if (!netif_running(dev))
235 skge_wol_init(skge);
baef58b1
SH		 236 return 0;
237}
238
8f3f8193
SH		 239/* Determine supported/advertised modes based on hardware.
240 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 241 */
242static u32 skge_supported_modes(const struct skge_hw *hw)
243{
244 u32 supported;
245
5e1705dd 246 if (hw->copper) {
31b619c5
SH		 247 supported = SUPPORTED_10baseT_Half
248 | SUPPORTED_10baseT_Full
249 | SUPPORTED_100baseT_Half
250 | SUPPORTED_100baseT_Full
251 | SUPPORTED_1000baseT_Half
252 | SUPPORTED_1000baseT_Full
253 | SUPPORTED_Autoneg| SUPPORTED_TP;
254
255 if (hw->chip_id == CHIP_ID_GENESIS)
256 supported &= ~(SUPPORTED_10baseT_Half
257 | SUPPORTED_10baseT_Full
258 | SUPPORTED_100baseT_Half
259 | SUPPORTED_100baseT_Full);
260
261 else if (hw->chip_id == CHIP_ID_YUKON)
262 supported &= ~SUPPORTED_1000baseT_Half;
263 } else
4b67be99
SH		 264 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
265 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
31b619c5
SH		 266
267 return supported;
268}
baef58b1
SH		 269
270static int skge_get_settings(struct net_device *dev,
271 struct ethtool_cmd *ecmd)
272{
273 struct skge_port *skge = netdev_priv(dev);
274 struct skge_hw *hw = skge->hw;
275
276 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 277 ecmd->supported = skge_supported_modes(hw);
baef58b1 278
5e1705dd 279 if (hw->copper) {
baef58b1
SH		 280 ecmd->port = PORT_TP;
281 ecmd->phy_address = hw->phy_addr;
31b619c5 282 } else
baef58b1 283 ecmd->port = PORT_FIBRE;
baef58b1
SH		 284
285 ecmd->advertising = skge->advertising;
286 ecmd->autoneg = skge->autoneg;
287 ecmd->speed = skge->speed;
288 ecmd->duplex = skge->duplex;
289 return 0;
290}
291
baef58b1
SH		 292static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
293{
294 struct skge_port *skge = netdev_priv(dev);
295 const struct skge_hw *hw = skge->hw;
31b619c5 296 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 297
298 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 299 ecmd->advertising = supported;
300 skge->duplex = -1;
301 skge->speed = -1;
baef58b1 302 } else {
31b619c5
SH		 303 u32 setting;
304
2c668514 305 switch (ecmd->speed) {
baef58b1 306 case SPEED_1000:
31b619c5
SH		 307 if (ecmd->duplex == DUPLEX_FULL)
308 setting = SUPPORTED_1000baseT_Full;
309 else if (ecmd->duplex == DUPLEX_HALF)
310 setting = SUPPORTED_1000baseT_Half;
311 else
312 return -EINVAL;
baef58b1
SH		 313 break;
314 case SPEED_100:
31b619c5
SH		 315 if (ecmd->duplex == DUPLEX_FULL)
316 setting = SUPPORTED_100baseT_Full;
317 else if (ecmd->duplex == DUPLEX_HALF)
318 setting = SUPPORTED_100baseT_Half;
319 else
320 return -EINVAL;
321 break;
322
baef58b1 323 case SPEED_10:
31b619c5
SH		 324 if (ecmd->duplex == DUPLEX_FULL)
325 setting = SUPPORTED_10baseT_Full;
326 else if (ecmd->duplex == DUPLEX_HALF)
327 setting = SUPPORTED_10baseT_Half;
328 else
baef58b1
SH		 329 return -EINVAL;
330 break;
331 default:
332 return -EINVAL;
333 }
31b619c5
SH		 334
335 if ((setting & supported) == 0)
336 return -EINVAL;
337
338 skge->speed = ecmd->speed;
339 skge->duplex = ecmd->duplex;
baef58b1
SH		 340 }
341
342 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 343 skge->advertising = ecmd->advertising;
344
ee294dcd
SH		 345 if (netif_running(dev))
346 skge_phy_reset(skge);
347
baef58b1
SH		 348 return (0);
349}
350
351static void skge_get_drvinfo(struct net_device *dev,
352 struct ethtool_drvinfo *info)
353{
354 struct skge_port *skge = netdev_priv(dev);
355
356 strcpy(info->driver, DRV_NAME);
357 strcpy(info->version, DRV_VERSION);
358 strcpy(info->fw_version, "N/A");
359 strcpy(info->bus_info, pci_name(skge->hw->pdev));
360}
361
362static const struct skge_stat {
363 char name[ETH_GSTRING_LEN];
364 u16 xmac_offset;
365 u16 gma_offset;
366} skge_stats[] = {
367 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
368 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
369
370 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
371 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
372 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
373 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
374 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
375 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
376 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
377 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
378
379 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
380 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
381 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
382 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
383 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
384 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
385
386 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
387 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
388 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
389 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
390 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
391};
392
393static int skge_get_stats_count(struct net_device *dev)
394{
395 return ARRAY_SIZE(skge_stats);
396}
397
398static void skge_get_ethtool_stats(struct net_device *dev,
399 struct ethtool_stats *stats, u64 *data)
400{
401 struct skge_port *skge = netdev_priv(dev);
402
403 if (skge->hw->chip_id == CHIP_ID_GENESIS)
404 genesis_get_stats(skge, data);
405 else
406 yukon_get_stats(skge, data);
407}
408
409/* Use hardware MIB variables for critical path statistics and
410 * transmit feedback not reported at interrupt.
411 * Other errors are accounted for in interrupt handler.
412 */
413static struct net_device_stats *skge_get_stats(struct net_device *dev)
414{
415 struct skge_port *skge = netdev_priv(dev);
416 u64 data[ARRAY_SIZE(skge_stats)];
417
418 if (skge->hw->chip_id == CHIP_ID_GENESIS)
419 genesis_get_stats(skge, data);
420 else
421 yukon_get_stats(skge, data);
422
423 skge->net_stats.tx_bytes = data[0];
424 skge->net_stats.rx_bytes = data[1];
425 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
426 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
4c180fc4 427 skge->net_stats.multicast = data[3] + data[5];
baef58b1
SH		 428 skge->net_stats.collisions = data[10];
429 skge->net_stats.tx_aborted_errors = data[12];
430
431 return &skge->net_stats;
432}
433
434static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
435{
436 int i;
437
95566065 438 switch (stringset) {
baef58b1
SH		 439 case ETH_SS_STATS:
440 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
441 memcpy(data + i * ETH_GSTRING_LEN,
442 skge_stats[i].name, ETH_GSTRING_LEN);
443 break;
444 }
445}
446
447static void skge_get_ring_param(struct net_device *dev,
448 struct ethtool_ringparam *p)
449{
450 struct skge_port *skge = netdev_priv(dev);
451
452 p->rx_max_pending = MAX_RX_RING_SIZE;
453 p->tx_max_pending = MAX_TX_RING_SIZE;
454 p->rx_mini_max_pending = 0;
455 p->rx_jumbo_max_pending = 0;
456
457 p->rx_pending = skge->rx_ring.count;
458 p->tx_pending = skge->tx_ring.count;
459 p->rx_mini_pending = 0;
460 p->rx_jumbo_pending = 0;
461}
462
463static int skge_set_ring_param(struct net_device *dev,
464 struct ethtool_ringparam *p)
465{
466 struct skge_port *skge = netdev_priv(dev);
3b8bb472 467 int err;
baef58b1
SH		 468
469 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
9db96479 470 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
baef58b1
SH		 471 return -EINVAL;
472
473 skge->rx_ring.count = p->rx_pending;
474 skge->tx_ring.count = p->tx_pending;
475
476 if (netif_running(dev)) {
477 skge_down(dev);
3b8bb472
SH		 478 err = skge_up(dev);
479 if (err)
480 dev_close(dev);
baef58b1
SH		 481 }
482
483 return 0;
484}
485
486static u32 skge_get_msglevel(struct net_device *netdev)
487{
488 struct skge_port *skge = netdev_priv(netdev);
489 return skge->msg_enable;
490}
491
492static void skge_set_msglevel(struct net_device *netdev, u32 value)
493{
494 struct skge_port *skge = netdev_priv(netdev);
495 skge->msg_enable = value;
496}
497
498static int skge_nway_reset(struct net_device *dev)
499{
500 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 501
502 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
503 return -EINVAL;
504
ee294dcd 505 skge_phy_reset(skge);
baef58b1
SH		 506 return 0;
507}
508
509static int skge_set_sg(struct net_device *dev, u32 data)
510{
511 struct skge_port *skge = netdev_priv(dev);
512 struct skge_hw *hw = skge->hw;
513
514 if (hw->chip_id == CHIP_ID_GENESIS && data)
515 return -EOPNOTSUPP;
516 return ethtool_op_set_sg(dev, data);
517}
518
519static int skge_set_tx_csum(struct net_device *dev, u32 data)
520{
521 struct skge_port *skge = netdev_priv(dev);
522 struct skge_hw *hw = skge->hw;
523
524 if (hw->chip_id == CHIP_ID_GENESIS && data)
525 return -EOPNOTSUPP;
526
527 return ethtool_op_set_tx_csum(dev, data);
528}
529
530static u32 skge_get_rx_csum(struct net_device *dev)
531{
532 struct skge_port *skge = netdev_priv(dev);
533
534 return skge->rx_csum;
535}
536
537/* Only Yukon supports checksum offload. */
538static int skge_set_rx_csum(struct net_device *dev, u32 data)
539{
540 struct skge_port *skge = netdev_priv(dev);
541
542 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
543 return -EOPNOTSUPP;
544
545 skge->rx_csum = data;
546 return 0;
547}
548
baef58b1
SH		 549static void skge_get_pauseparam(struct net_device *dev,
550 struct ethtool_pauseparam *ecmd)
551{
552 struct skge_port *skge = netdev_priv(dev);
553
5d5c8e03
SH		 554 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
555 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
556 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
baef58b1 557
5d5c8e03 558 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
baef58b1
SH		 559}
560
561static int skge_set_pauseparam(struct net_device *dev,
562 struct ethtool_pauseparam *ecmd)
563{
564 struct skge_port *skge = netdev_priv(dev);
5d5c8e03 565 struct ethtool_pauseparam old;
baef58b1 566
5d5c8e03
SH		 567 skge_get_pauseparam(dev, &old);
568
569 if (ecmd->autoneg != old.autoneg)
570 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
571 else {
572 if (ecmd->rx_pause && ecmd->tx_pause)
573 skge->flow_control = FLOW_MODE_SYMMETRIC;
574 else if (ecmd->rx_pause && !ecmd->tx_pause)
575 skge->flow_control = FLOW_MODE_SYM_OR_REM;
576 else if (!ecmd->rx_pause && ecmd->tx_pause)
577 skge->flow_control = FLOW_MODE_LOC_SEND;
578 else
579 skge->flow_control = FLOW_MODE_NONE;
580 }
baef58b1 581
e8df8554
SH		 582 if (netif_running(dev))
583 skge_phy_reset(skge);
5d5c8e03 584
baef58b1
SH		 585 return 0;
586}
587
588/* Chip internal frequency for clock calculations */
589static inline u32 hwkhz(const struct skge_hw *hw)
590{
187ff3b8 591 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
baef58b1
SH		 592}
593
8f3f8193 594/* Chip HZ to microseconds */
baef58b1
SH		 595static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
596{
597 return (ticks * 1000) / hwkhz(hw);
598}
599
8f3f8193 600/* Microseconds to chip HZ */
baef58b1
SH		 601static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
602{
603 return hwkhz(hw) * usec / 1000;
604}
605
606static int skge_get_coalesce(struct net_device *dev,
607 struct ethtool_coalesce *ecmd)
608{
609 struct skge_port *skge = netdev_priv(dev);
610 struct skge_hw *hw = skge->hw;
611 int port = skge->port;
612
613 ecmd->rx_coalesce_usecs = 0;
614 ecmd->tx_coalesce_usecs = 0;
615
616 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
617 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
618 u32 msk = skge_read32(hw, B2_IRQM_MSK);
619
620 if (msk & rxirqmask[port])
621 ecmd->rx_coalesce_usecs = delay;
622 if (msk & txirqmask[port])
623 ecmd->tx_coalesce_usecs = delay;
624 }
625
626 return 0;
627}
628
629/* Note: interrupt timer is per board, but can turn on/off per port */
630static int skge_set_coalesce(struct net_device *dev,
631 struct ethtool_coalesce *ecmd)
632{
633 struct skge_port *skge = netdev_priv(dev);
634 struct skge_hw *hw = skge->hw;
635 int port = skge->port;
636 u32 msk = skge_read32(hw, B2_IRQM_MSK);
637 u32 delay = 25;
638
639 if (ecmd->rx_coalesce_usecs == 0)
640 msk &= ~rxirqmask[port];
641 else if (ecmd->rx_coalesce_usecs < 25 ||
642 ecmd->rx_coalesce_usecs > 33333)
643 return -EINVAL;
644 else {
645 msk |= rxirqmask[port];
646 delay = ecmd->rx_coalesce_usecs;
647 }
648
649 if (ecmd->tx_coalesce_usecs == 0)
650 msk &= ~txirqmask[port];
651 else if (ecmd->tx_coalesce_usecs < 25 ||
652 ecmd->tx_coalesce_usecs > 33333)
653 return -EINVAL;
654 else {
655 msk |= txirqmask[port];
656 delay = min(delay, ecmd->rx_coalesce_usecs);
657 }
658
659 skge_write32(hw, B2_IRQM_MSK, msk);
660 if (msk == 0)
661 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
662 else {
663 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
664 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
665 }
666 return 0;
667}
668
6abebb53
SH		 669enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
670static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 671{
6abebb53
SH		 672 struct skge_hw *hw = skge->hw;
673 int port = skge->port;
674
9cbe330f 675 spin_lock_bh(&hw->phy_lock);
baef58b1 676 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 677 switch (mode) {
678 case LED_MODE_OFF:
64f6b64d
SH		 679 if (hw->phy_type == SK_PHY_BCOM)
680 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
681 else {
682 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
683 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
684 }
6abebb53
SH		 685 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
686 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
687 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
688 break;
baef58b1 689
6abebb53
SH		 690 case LED_MODE_ON:
691 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
692 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 693
6abebb53
SH		 694 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
695 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 696
6abebb53 697 break;
baef58b1 698
6abebb53
SH		 699 case LED_MODE_TST:
700 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
701 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
702 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 703
64f6b64d
SH		 704 if (hw->phy_type == SK_PHY_BCOM)
705 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
706 else {
707 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
708 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
709 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
710 }
711
6abebb53 712 }
baef58b1 713 } else {
6abebb53
SH		 714 switch (mode) {
715 case LED_MODE_OFF:
716 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
717 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
718 PHY_M_LED_MO_DUP(MO_LED_OFF) |
719 PHY_M_LED_MO_10(MO_LED_OFF) |
720 PHY_M_LED_MO_100(MO_LED_OFF) |
721 PHY_M_LED_MO_1000(MO_LED_OFF) |
722 PHY_M_LED_MO_RX(MO_LED_OFF));
723 break;
724 case LED_MODE_ON:
725 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
726 PHY_M_LED_PULS_DUR(PULS_170MS) |
727 PHY_M_LED_BLINK_RT(BLINK_84MS) |
728 PHY_M_LEDC_TX_CTRL |
729 PHY_M_LEDC_DP_CTRL);
46a60f2d 730
6abebb53
SH		 731 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
732 PHY_M_LED_MO_RX(MO_LED_OFF) |
733 (skge->speed == SPEED_100 ?
734 PHY_M_LED_MO_100(MO_LED_ON) : 0));
735 break;
736 case LED_MODE_TST:
737 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
738 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
739 PHY_M_LED_MO_DUP(MO_LED_ON) |
740 PHY_M_LED_MO_10(MO_LED_ON) |
741 PHY_M_LED_MO_100(MO_LED_ON) |
742 PHY_M_LED_MO_1000(MO_LED_ON) |
743 PHY_M_LED_MO_RX(MO_LED_ON));
744 }
baef58b1 745 }
9cbe330f 746 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 747}
748
749/* blink LED's for finding board */
750static int skge_phys_id(struct net_device *dev, u32 data)
751{
752 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 753 unsigned long ms;
754 enum led_mode mode = LED_MODE_TST;
baef58b1 755
95566065 756 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 757 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
758 else
759 ms = data * 1000;
baef58b1 760
6abebb53
SH		 761 while (ms > 0) {
762 skge_led(skge, mode);
763 mode ^= LED_MODE_TST;
baef58b1 764
6abebb53
SH		 765 if (msleep_interruptible(BLINK_MS))
766 break;
767 ms -= BLINK_MS;
768 }
baef58b1 769
6abebb53
SH		 770 /* back to regular LED state */
771 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 772
773 return 0;
774}
775
7282d491 776static const struct ethtool_ops skge_ethtool_ops = {
baef58b1
SH		 777 .get_settings = skge_get_settings,
778 .set_settings = skge_set_settings,
779 .get_drvinfo = skge_get_drvinfo,
780 .get_regs_len = skge_get_regs_len,
781 .get_regs = skge_get_regs,
782 .get_wol = skge_get_wol,
783 .set_wol = skge_set_wol,
784 .get_msglevel = skge_get_msglevel,
785 .set_msglevel = skge_set_msglevel,
786 .nway_reset = skge_nway_reset,
787 .get_link = ethtool_op_get_link,
788 .get_ringparam = skge_get_ring_param,
789 .set_ringparam = skge_set_ring_param,
790 .get_pauseparam = skge_get_pauseparam,
791 .set_pauseparam = skge_set_pauseparam,
792 .get_coalesce = skge_get_coalesce,
793 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 794 .get_sg = ethtool_op_get_sg,
795 .set_sg = skge_set_sg,
796 .get_tx_csum = ethtool_op_get_tx_csum,
797 .set_tx_csum = skge_set_tx_csum,
798 .get_rx_csum = skge_get_rx_csum,
799 .set_rx_csum = skge_set_rx_csum,
800 .get_strings = skge_get_strings,
801 .phys_id = skge_phys_id,
802 .get_stats_count = skge_get_stats_count,
803 .get_ethtool_stats = skge_get_ethtool_stats,
56230d53 804 .get_perm_addr = ethtool_op_get_perm_addr,
baef58b1
SH		 805};
806
807/*
808 * Allocate ring elements and chain them together
809 * One-to-one association of board descriptors with ring elements
810 */
c3da1447 811static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
baef58b1
SH		 812{
813 struct skge_tx_desc *d;
814 struct skge_element *e;
815 int i;
816
cd861280 817 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
baef58b1
SH		 818 if (!ring->start)
819 return -ENOMEM;
820
821 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
822 e->desc = d;
823 if (i == ring->count - 1) {
824 e->next = ring->start;
825 d->next_offset = base;
826 } else {
827 e->next = e + 1;
828 d->next_offset = base + (i+1) * sizeof(*d);
829 }
830 }
831 ring->to_use = ring->to_clean = ring->start;
832
833 return 0;
834}
835
19a33d4e
SH		 836/* Allocate and setup a new buffer for receiving */
837static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
838 struct sk_buff *skb, unsigned int bufsize)
839{
840 struct skge_rx_desc *rd = e->desc;
841 u64 map;
baef58b1
SH		 842
843 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
844 PCI_DMA_FROMDEVICE);
845
846 rd->dma_lo = map;
847 rd->dma_hi = map >> 32;
848 e->skb = skb;
849 rd->csum1_start = ETH_HLEN;
850 rd->csum2_start = ETH_HLEN;
851 rd->csum1 = 0;
852 rd->csum2 = 0;
853
854 wmb();
855
856 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
857 pci_unmap_addr_set(e, mapaddr, map);
858 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 859}
860
19a33d4e
SH		 861/* Resume receiving using existing skb,
862 * Note: DMA address is not changed by chip.
863 * MTU not changed while receiver active.
864 */
5a011447 865static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
19a33d4e
SH		 866{
867 struct skge_rx_desc *rd = e->desc;
868
869 rd->csum2 = 0;
870 rd->csum2_start = ETH_HLEN;
871
872 wmb();
873
874 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
875}
876
877
878/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 879static void skge_rx_clean(struct skge_port *skge)
880{
881 struct skge_hw *hw = skge->hw;
882 struct skge_ring *ring = &skge->rx_ring;
883 struct skge_element *e;
884
19a33d4e
SH		 885 e = ring->start;
886 do {
baef58b1
SH		 887 struct skge_rx_desc *rd = e->desc;
888 rd->control = 0;
19a33d4e
SH		 889 if (e->skb) {
890 pci_unmap_single(hw->pdev,
891 pci_unmap_addr(e, mapaddr),
892 pci_unmap_len(e, maplen),
893 PCI_DMA_FROMDEVICE);
894 dev_kfree_skb(e->skb);
895 e->skb = NULL;
896 }
897 } while ((e = e->next) != ring->start);
baef58b1
SH		 898}
899
19a33d4e 900
baef58b1 901/* Allocate buffers for receive ring
19a33d4e 902 * For receive: to_clean is next received frame.
baef58b1 903 */
c54f9765 904static int skge_rx_fill(struct net_device *dev)
baef58b1 905{
c54f9765 906 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 907 struct skge_ring *ring = &skge->rx_ring;
908 struct skge_element *e;
baef58b1 909
19a33d4e
SH		 910 e = ring->start;
911 do {
383181ac 912 struct sk_buff *skb;
baef58b1 913
c54f9765
SH		 914 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
915 GFP_KERNEL);
19a33d4e
SH		 916 if (!skb)
917 return -ENOMEM;
918
383181ac
SH		 919 skb_reserve(skb, NET_IP_ALIGN);
920 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 921 } while ( (e = e->next) != ring->start);
baef58b1 922
19a33d4e
SH		 923 ring->to_clean = ring->start;
924 return 0;
baef58b1
SH		 925}
926
5d5c8e03
SH		 927static const char *skge_pause(enum pause_status status)
928{
929 switch(status) {
930 case FLOW_STAT_NONE:
931 return "none";
932 case FLOW_STAT_REM_SEND:
933 return "rx only";
934 case FLOW_STAT_LOC_SEND:
935 return "tx_only";
936 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
937 return "both";
938 default:
939 return "indeterminated";
940 }
941}
942
943
baef58b1
SH		 944static void skge_link_up(struct skge_port *skge)
945{
46a60f2d 946 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 947 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
948
baef58b1 949 netif_carrier_on(skge->netdev);
29b4e886 950 netif_wake_queue(skge->netdev);
baef58b1 951
5d5c8e03 952 if (netif_msg_link(skge)) {
baef58b1
SH		 953 printk(KERN_INFO PFX
954 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
955 skge->netdev->name, skge->speed,
956 skge->duplex == DUPLEX_FULL ? "full" : "half",
5d5c8e03
SH		 957 skge_pause(skge->flow_status));
958 }
baef58b1
SH		 959}
960
961static void skge_link_down(struct skge_port *skge)
962{
54cfb5aa 963 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 964 netif_carrier_off(skge->netdev);
965 netif_stop_queue(skge->netdev);
966
967 if (netif_msg_link(skge))
968 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
969}
970
a1bc9b87
SH		 971
972static void xm_link_down(struct skge_hw *hw, int port)
973{
974 struct net_device *dev = hw->dev[port];
975 struct skge_port *skge = netdev_priv(dev);
976 u16 cmd, msk;
977
978 if (hw->phy_type == SK_PHY_XMAC) {
979 msk = xm_read16(hw, port, XM_IMSK);
980 msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
981 xm_write16(hw, port, XM_IMSK, msk);
982 }
983
984 cmd = xm_read16(hw, port, XM_MMU_CMD);
985 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
986 xm_write16(hw, port, XM_MMU_CMD, cmd);
987 /* dummy read to ensure writing */
988 (void) xm_read16(hw, port, XM_MMU_CMD);
989
990 if (netif_carrier_ok(dev))
991 skge_link_down(skge);
992}
993
2cd8e5d3 994static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 995{
996 int i;
baef58b1 997
6b0c1480 998 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
0781191c 999 *val = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 1000
64f6b64d
SH		 1001 if (hw->phy_type == SK_PHY_XMAC)
1002 goto ready;
1003
89bf5f23 1004 for (i = 0; i < PHY_RETRIES; i++) {
2cd8e5d3 1005 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 1006 goto ready;
0781191c 1007 udelay(1);
baef58b1
SH		 1008 }
1009
2cd8e5d3 1010 return -ETIMEDOUT;
89bf5f23 1011 ready:
2cd8e5d3 1012 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 1013
2cd8e5d3
SH		 1014 return 0;
1015}
1016
1017static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1018{
1019 u16 v = 0;
1020 if (__xm_phy_read(hw, port, reg, &v))
1021 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1022 hw->dev[port]->name);
baef58b1
SH		 1023 return v;
1024}
1025
2cd8e5d3 1026static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1027{
1028 int i;
1029
6b0c1480 1030 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 1031 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 1032 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 1033 goto ready;
89bf5f23 1034 udelay(1);
baef58b1 1035 }
2cd8e5d3 1036 return -EIO;
baef58b1
SH		 1037
1038 ready:
6b0c1480 1039 xm_write16(hw, port, XM_PHY_DATA, val);
0781191c
SH		 1040 for (i = 0; i < PHY_RETRIES; i++) {
1041 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1042 return 0;
1043 udelay(1);
1044 }
1045 return -ETIMEDOUT;
baef58b1
SH		 1046}
1047
1048static void genesis_init(struct skge_hw *hw)
1049{
1050 /* set blink source counter */
1051 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1052 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1053
1054 /* configure mac arbiter */
1055 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1056
1057 /* configure mac arbiter timeout values */
1058 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1059 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1060 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1061 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1062
1063 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1064 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1065 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1066 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1067
1068 /* configure packet arbiter timeout */
1069 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1070 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1071 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1072 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1073 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1074}
1075
1076static void genesis_reset(struct skge_hw *hw, int port)
1077{
45bada65 1078 const u8 zero[8] = { 0 };
baef58b1 1079
46a60f2d
SH		 1080 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1081
baef58b1 1082 /* reset the statistics module */
6b0c1480
SH		 1083 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1084 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1085 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1086 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1087 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 1088
89bf5f23 1089 /* disable Broadcom PHY IRQ */
64f6b64d
SH		 1090 if (hw->phy_type == SK_PHY_BCOM)
1091 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 1092
45bada65 1093 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 1094}
1095
1096
45bada65
SH		 1097/* Convert mode to MII values */
1098static const u16 phy_pause_map[] = {
1099 [FLOW_MODE_NONE] = 0,
1100 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1101 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
5d5c8e03 1102 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
45bada65
SH		 1103};
1104
4b67be99
SH		 1105/* special defines for FIBER (88E1011S only) */
1106static const u16 fiber_pause_map[] = {
1107 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1108 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1109 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
5d5c8e03 1110 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
4b67be99
SH		 1111};
1112
45bada65
SH		 1113
1114/* Check status of Broadcom phy link */
1115static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 1116{
45bada65
SH		 1117 struct net_device *dev = hw->dev[port];
1118 struct skge_port *skge = netdev_priv(dev);
1119 u16 status;
1120
1121 /* read twice because of latch */
1122 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1123 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1124
45bada65 1125 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1126 xm_link_down(hw, port);
64f6b64d
SH		 1127 return;
1128 }
45bada65 1129
64f6b64d
SH		 1130 if (skge->autoneg == AUTONEG_ENABLE) {
1131 u16 lpa, aux;
45bada65 1132
64f6b64d
SH		 1133 if (!(status & PHY_ST_AN_OVER))
1134 return;
45bada65 1135
64f6b64d
SH		 1136 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1137 if (lpa & PHY_B_AN_RF) {
1138 printk(KERN_NOTICE PFX "%s: remote fault\n",
1139 dev->name);
1140 return;
1141 }
45bada65 1142
64f6b64d
SH		 1143 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1144
1145 /* Check Duplex mismatch */
1146 switch (aux & PHY_B_AS_AN_RES_MSK) {
1147 case PHY_B_RES_1000FD:
1148 skge->duplex = DUPLEX_FULL;
1149 break;
1150 case PHY_B_RES_1000HD:
1151 skge->duplex = DUPLEX_HALF;
1152 break;
1153 default:
1154 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1155 dev->name);
1156 return;
45bada65
SH		 1157 }
1158
64f6b64d
SH		 1159 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1160 switch (aux & PHY_B_AS_PAUSE_MSK) {
1161 case PHY_B_AS_PAUSE_MSK:
5d5c8e03 1162 skge->flow_status = FLOW_STAT_SYMMETRIC;
64f6b64d
SH		 1163 break;
1164 case PHY_B_AS_PRR:
5d5c8e03 1165 skge->flow_status = FLOW_STAT_REM_SEND;
64f6b64d
SH		 1166 break;
1167 case PHY_B_AS_PRT:
5d5c8e03 1168 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d
SH		 1169 break;
1170 default:
5d5c8e03 1171 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1172 }
1173 skge->speed = SPEED_1000;
45bada65 1174 }
64f6b64d
SH		 1175
1176 if (!netif_carrier_ok(dev))
1177 genesis_link_up(skge);
45bada65
SH		 1178}
1179
1180/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1181 * Phy on for 100 or 10Mbit operation
1182 */
64f6b64d 1183static void bcom_phy_init(struct skge_port *skge)
45bada65
SH		 1184{
1185 struct skge_hw *hw = skge->hw;
1186 int port = skge->port;
baef58b1 1187 int i;
45bada65 1188 u16 id1, r, ext, ctl;
baef58b1
SH		 1189
1190 /* magic workaround patterns for Broadcom */
1191 static const struct {
1192 u16 reg;
1193 u16 val;
1194 } A1hack[] = {
1195 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1196 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1197 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1198 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1199 }, C0hack[] = {
1200 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1201 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1202 };
1203
45bada65
SH		 1204 /* read Id from external PHY (all have the same address) */
1205 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1206
1207 /* Optimize MDIO transfer by suppressing preamble. */
1208 r = xm_read16(hw, port, XM_MMU_CMD);
1209 r |= XM_MMU_NO_PRE;
1210 xm_write16(hw, port, XM_MMU_CMD,r);
1211
2c668514 1212 switch (id1) {
45bada65
SH		 1213 case PHY_BCOM_ID1_C0:
1214 /*
1215 * Workaround BCOM Errata for the C0 type.
1216 * Write magic patterns to reserved registers.
1217 */
1218 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1219 xm_phy_write(hw, port,
1220 C0hack[i].reg, C0hack[i].val);
1221
1222 break;
1223 case PHY_BCOM_ID1_A1:
1224 /*
1225 * Workaround BCOM Errata for the A1 type.
1226 * Write magic patterns to reserved registers.
1227 */
1228 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1229 xm_phy_write(hw, port,
1230 A1hack[i].reg, A1hack[i].val);
1231 break;
1232 }
1233
1234 /*
1235 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1236 * Disable Power Management after reset.
1237 */
1238 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1239 r |= PHY_B_AC_DIS_PM;
1240 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1241
1242 /* Dummy read */
1243 xm_read16(hw, port, XM_ISRC);
1244
1245 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1246 ctl = PHY_CT_SP1000; /* always 1000mbit */
1247
1248 if (skge->autoneg == AUTONEG_ENABLE) {
1249 /*
1250 * Workaround BCOM Errata #1 for the C5 type.
1251 * 1000Base-T Link Acquisition Failure in Slave Mode
1252 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1253 */
1254 u16 adv = PHY_B_1000C_RD;
1255 if (skge->advertising & ADVERTISED_1000baseT_Half)
1256 adv |= PHY_B_1000C_AHD;
1257 if (skge->advertising & ADVERTISED_1000baseT_Full)
1258 adv |= PHY_B_1000C_AFD;
1259 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1260
1261 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1262 } else {
1263 if (skge->duplex == DUPLEX_FULL)
1264 ctl |= PHY_CT_DUP_MD;
1265 /* Force to slave */
1266 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1267 }
1268
1269 /* Set autonegotiation pause parameters */
1270 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1271 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1272
1273 /* Handle Jumbo frames */
64f6b64d 1274 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
45bada65
SH		 1275 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1276 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1277
1278 ext |= PHY_B_PEC_HIGH_LA;
1279
1280 }
1281
1282 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1283 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1284
8f3f8193 1285 /* Use link status change interrupt */
45bada65 1286 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
64f6b64d 1287}
45bada65 1288
64f6b64d
SH		 1289static void xm_phy_init(struct skge_port *skge)
1290{
1291 struct skge_hw *hw = skge->hw;
1292 int port = skge->port;
1293 u16 ctrl = 0;
1294
1295 if (skge->autoneg == AUTONEG_ENABLE) {
1296 if (skge->advertising & ADVERTISED_1000baseT_Half)
1297 ctrl |= PHY_X_AN_HD;
1298 if (skge->advertising & ADVERTISED_1000baseT_Full)
1299 ctrl |= PHY_X_AN_FD;
1300
4b67be99 1301 ctrl |= fiber_pause_map[skge->flow_control];
64f6b64d
SH		 1302
1303 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1304
1305 /* Restart Auto-negotiation */
1306 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1307 } else {
1308 /* Set DuplexMode in Config register */
1309 if (skge->duplex == DUPLEX_FULL)
1310 ctrl |= PHY_CT_DUP_MD;
1311 /*
1312 * Do NOT enable Auto-negotiation here. This would hold
1313 * the link down because no IDLEs are transmitted
1314 */
1315 }
1316
1317 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1318
1319 /* Poll PHY for status changes */
9cbe330f 1320 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
64f6b64d
SH		 1321}
1322
1323static void xm_check_link(struct net_device *dev)
1324{
1325 struct skge_port *skge = netdev_priv(dev);
1326 struct skge_hw *hw = skge->hw;
1327 int port = skge->port;
1328 u16 status;
1329
1330 /* read twice because of latch */
1331 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1332 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1333
1334 if ((status & PHY_ST_LSYNC) == 0) {
a1bc9b87 1335 xm_link_down(hw, port);
64f6b64d
SH		 1336 return;
1337 }
1338
1339 if (skge->autoneg == AUTONEG_ENABLE) {
1340 u16 lpa, res;
1341
1342 if (!(status & PHY_ST_AN_OVER))
1343 return;
1344
1345 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1346 if (lpa & PHY_B_AN_RF) {
1347 printk(KERN_NOTICE PFX "%s: remote fault\n",
1348 dev->name);
1349 return;
1350 }
1351
1352 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1353
1354 /* Check Duplex mismatch */
1355 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1356 case PHY_X_RS_FD:
1357 skge->duplex = DUPLEX_FULL;
1358 break;
1359 case PHY_X_RS_HD:
1360 skge->duplex = DUPLEX_HALF;
1361 break;
1362 default:
1363 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1364 dev->name);
1365 return;
1366 }
1367
1368 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
5d5c8e03
SH		 1369 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1370 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1371 (lpa & PHY_X_P_SYM_MD))
1372 skge->flow_status = FLOW_STAT_SYMMETRIC;
1373 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1374 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1375 /* Enable PAUSE receive, disable PAUSE transmit */
1376 skge->flow_status = FLOW_STAT_REM_SEND;
1377 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1378 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1379 /* Disable PAUSE receive, enable PAUSE transmit */
1380 skge->flow_status = FLOW_STAT_LOC_SEND;
64f6b64d 1381 else
5d5c8e03 1382 skge->flow_status = FLOW_STAT_NONE;
64f6b64d
SH		 1383
1384 skge->speed = SPEED_1000;
1385 }
1386
1387 if (!netif_carrier_ok(dev))
1388 genesis_link_up(skge);
1389}
1390
1391/* Poll to check for link coming up.
1392 * Since internal PHY is wired to a level triggered pin, can't
1393 * get an interrupt when carrier is detected.
1394 */
9cbe330f 1395static void xm_link_timer(unsigned long arg)
64f6b64d 1396{
9cbe330f 1397 struct skge_port *skge = (struct skge_port *) arg;
c4028958 1398 struct net_device *dev = skge->netdev;
64f6b64d
SH		 1399 struct skge_hw *hw = skge->hw;
1400 int port = skge->port;
1401
1402 if (!netif_running(dev))
1403 return;
1404
1405 if (netif_carrier_ok(dev)) {
1406 xm_read16(hw, port, XM_ISRC);
1407 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1408 goto nochange;
1409 } else {
1410 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1411 goto nochange;
1412 xm_read16(hw, port, XM_ISRC);
1413 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1414 goto nochange;
1415 }
1416
9cbe330f 1417 spin_lock(&hw->phy_lock);
64f6b64d 1418 xm_check_link(dev);
9cbe330f 1419 spin_unlock(&hw->phy_lock);
64f6b64d
SH		 1420
1421nochange:
208491d8 1422 if (netif_running(dev))
9cbe330f 1423 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
45bada65
SH		 1424}
1425
1426static void genesis_mac_init(struct skge_hw *hw, int port)
1427{
1428 struct net_device *dev = hw->dev[port];
1429 struct skge_port *skge = netdev_priv(dev);
1430 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1431 int i;
1432 u32 r;
1433 const u8 zero[6] = { 0 };
1434
0781191c
SH		 1435 for (i = 0; i < 10; i++) {
1436 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1437 MFF_SET_MAC_RST);
1438 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1439 goto reset_ok;
1440 udelay(1);
1441 }
baef58b1 1442
0781191c
SH		 1443 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1444
1445 reset_ok:
baef58b1 1446 /* Unreset the XMAC. */
6b0c1480 1447 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1448
1449 /*
1450 * Perform additional initialization for external PHYs,
1451 * namely for the 1000baseTX cards that use the XMAC's
1452 * GMII mode.
1453 */
64f6b64d
SH		 1454 if (hw->phy_type != SK_PHY_XMAC) {
1455 /* Take external Phy out of reset */
1456 r = skge_read32(hw, B2_GP_IO);
1457 if (port == 0)
1458 r |= GP_DIR_0|GP_IO_0;
1459 else
1460 r |= GP_DIR_2|GP_IO_2;
89bf5f23 1461
64f6b64d 1462 skge_write32(hw, B2_GP_IO, r);
0781191c 1463
64f6b64d
SH		 1464 /* Enable GMII interface */
1465 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1466 }
89bf5f23 1467
89bf5f23 1468
64f6b64d
SH		 1469 switch(hw->phy_type) {
1470 case SK_PHY_XMAC:
1471 xm_phy_init(skge);
1472 break;
1473 case SK_PHY_BCOM:
1474 bcom_phy_init(skge);
1475 bcom_check_link(hw, port);
1476 }
89bf5f23 1477
45bada65
SH		 1478 /* Set Station Address */
1479 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1480
45bada65
SH		 1481 /* We don't use match addresses so clear */
1482 for (i = 1; i < 16; i++)
1483 xm_outaddr(hw, port, XM_EXM(i), zero);
1484
0781191c
SH		 1485 /* Clear MIB counters */
1486 xm_write16(hw, port, XM_STAT_CMD,
1487 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1488 /* Clear two times according to Errata #3 */
1489 xm_write16(hw, port, XM_STAT_CMD,
1490 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1491
45bada65
SH		 1492 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1493 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1494
1495 /* We don't need the FCS appended to the packet. */
1496 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1497 if (jumbo)
1498 r |= XM_RX_BIG_PK_OK;
89bf5f23 1499
45bada65 1500 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1501 /*
45bada65
SH		 1502 * If in manual half duplex mode the other side might be in
1503 * full duplex mode, so ignore if a carrier extension is not seen
1504 * on frames received
89bf5f23 1505 */
45bada65 1506 r |= XM_RX_DIS_CEXT;
baef58b1 1507 }
45bada65 1508 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1509
baef58b1
SH		 1510
1511 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1512 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1513
1514 /*
1515 * Bump up the transmit threshold. This helps hold off transmit
1516 * underruns when we're blasting traffic from both ports at once.
1517 */
1518 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1519
1520 /*
1521 * Enable the reception of all error frames. This is is
1522 * a necessary evil due to the design of the XMAC. The
1523 * XMAC's receive FIFO is only 8K in size, however jumbo
1524 * frames can be up to 9000 bytes in length. When bad
1525 * frame filtering is enabled, the XMAC's RX FIFO operates
1526 * in 'store and forward' mode. For this to work, the
1527 * entire frame has to fit into the FIFO, but that means
1528 * that jumbo frames larger than 8192 bytes will be
1529 * truncated. Disabling all bad frame filtering causes
1530 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1531 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1532 * RX FIFO as soon as the FIFO threshold is reached.
1533 */
45bada65 1534 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1535
baef58b1
SH		 1536
1537 /*
45bada65
SH		 1538 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1539 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1540 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1541 */
45bada65
SH		 1542 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1543
1544 /*
1545 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1546 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1547 * and 'Octets Tx OK Hi Cnt Ov'.
1548 */
1549 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1550
1551 /* Configure MAC arbiter */
1552 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1553
1554 /* configure timeout values */
1555 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1556 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1557 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1558 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1559
1560 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1561 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1562 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1563 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1564
1565 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1566 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1567 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1568 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1569
1570 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1571 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1572 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1573 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1574
45bada65 1575 if (jumbo) {
baef58b1 1576 /* Enable frame flushing if jumbo frames used */
6b0c1480 1577 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1578 } else {
1579 /* enable timeout timers if normal frames */
1580 skge_write16(hw, B3_PA_CTRL,
45bada65 1581 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1582 }
baef58b1
SH		 1583}
1584
1585static void genesis_stop(struct skge_port *skge)
1586{
1587 struct skge_hw *hw = skge->hw;
1588 int port = skge->port;
89bf5f23 1589 u32 reg;
baef58b1 1590
46a60f2d
SH		 1591 genesis_reset(hw, port);
1592
baef58b1
SH		 1593 /* Clear Tx packet arbiter timeout IRQ */
1594 skge_write16(hw, B3_PA_CTRL,
1595 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1596
1597 /*
8f3f8193 1598 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1599 * terminate if we don't flush the XMAC's transmit FIFO !
1600 */
6b0c1480
SH		 1601 xm_write32(hw, port, XM_MODE,
1602 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1603
1604
1605 /* Reset the MAC */
6b0c1480 1606 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1607
1608 /* For external PHYs there must be special handling */
64f6b64d
SH		 1609 if (hw->phy_type != SK_PHY_XMAC) {
1610 reg = skge_read32(hw, B2_GP_IO);
1611 if (port == 0) {
1612 reg |= GP_DIR_0;
1613 reg &= ~GP_IO_0;
1614 } else {
1615 reg |= GP_DIR_2;
1616 reg &= ~GP_IO_2;
1617 }
1618 skge_write32(hw, B2_GP_IO, reg);
1619 skge_read32(hw, B2_GP_IO);
baef58b1
SH		 1620 }
1621
6b0c1480
SH		 1622 xm_write16(hw, port, XM_MMU_CMD,
1623 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1624 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1625
6b0c1480 1626 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1627}
1628
1629
1630static void genesis_get_stats(struct skge_port *skge, u64 *data)
1631{
1632 struct skge_hw *hw = skge->hw;
1633 int port = skge->port;
1634 int i;
1635 unsigned long timeout = jiffies + HZ;
1636
6b0c1480 1637 xm_write16(hw, port,
baef58b1
SH		 1638 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1639
1640 /* wait for update to complete */
6b0c1480 1641 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1642 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1643 if (time_after(jiffies, timeout))
1644 break;
1645 udelay(10);
1646 }
1647
1648 /* special case for 64 bit octet counter */
6b0c1480
SH		 1649 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1650 | xm_read32(hw, port, XM_TXO_OK_LO);
1651 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1652 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1653
1654 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1655 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1656}
1657
1658static void genesis_mac_intr(struct skge_hw *hw, int port)
1659{
1660 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1661 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1662
7e676d91
SH		 1663 if (netif_msg_intr(skge))
1664 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1665 skge->netdev->name, status);
baef58b1 1666
a1bc9b87
SH		 1667 if (hw->phy_type == SK_PHY_XMAC &&
1668 (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
1669 xm_link_down(hw, port);
1670
baef58b1 1671 if (status & XM_IS_TXF_UR) {
6b0c1480 1672 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1673 ++skge->net_stats.tx_fifo_errors;
1674 }
1675 if (status & XM_IS_RXF_OV) {
6b0c1480 1676 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1677 ++skge->net_stats.rx_fifo_errors;
1678 }
1679}
1680
baef58b1
SH		 1681static void genesis_link_up(struct skge_port *skge)
1682{
1683 struct skge_hw *hw = skge->hw;
1684 int port = skge->port;
a1bc9b87 1685 u16 cmd, msk;
64f6b64d 1686 u32 mode;
baef58b1 1687
6b0c1480 1688 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1689
1690 /*
1691 * enabling pause frame reception is required for 1000BT
1692 * because the XMAC is not reset if the link is going down
1693 */
5d5c8e03
SH		 1694 if (skge->flow_status == FLOW_STAT_NONE ||
1695 skge->flow_status == FLOW_STAT_LOC_SEND)
7e676d91 1696 /* Disable Pause Frame Reception */
baef58b1
SH		 1697 cmd |= XM_MMU_IGN_PF;
1698 else
1699 /* Enable Pause Frame Reception */
1700 cmd &= ~XM_MMU_IGN_PF;
1701
6b0c1480 1702 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1703
6b0c1480 1704 mode = xm_read32(hw, port, XM_MODE);
5d5c8e03
SH		 1705 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1706 skge->flow_status == FLOW_STAT_LOC_SEND) {
baef58b1
SH		 1707 /*
1708 * Configure Pause Frame Generation
1709 * Use internal and external Pause Frame Generation.
1710 * Sending pause frames is edge triggered.
1711 * Send a Pause frame with the maximum pause time if
1712 * internal oder external FIFO full condition occurs.
1713 * Send a zero pause time frame to re-start transmission.
1714 */
1715 /* XM_PAUSE_DA = '010000C28001' (default) */
1716 /* XM_MAC_PTIME = 0xffff (maximum) */
1717 /* remember this value is defined in big endian (!) */
6b0c1480 1718 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1719
1720 mode |= XM_PAUSE_MODE;
6b0c1480 1721 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1722 } else {
1723 /*
1724 * disable pause frame generation is required for 1000BT
1725 * because the XMAC is not reset if the link is going down
1726 */
1727 /* Disable Pause Mode in Mode Register */
1728 mode &= ~XM_PAUSE_MODE;
1729
6b0c1480 1730 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1731 }
1732
6b0c1480 1733 xm_write32(hw, port, XM_MODE, mode);
a1bc9b87
SH		 1734 msk = XM_DEF_MSK;
1735 if (hw->phy_type != SK_PHY_XMAC)
1736 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1737
1738 xm_write16(hw, port, XM_IMSK, msk);
6b0c1480 1739 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1740
1741 /* get MMU Command Reg. */
6b0c1480 1742 cmd = xm_read16(hw, port, XM_MMU_CMD);
64f6b64d 1743 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1744 cmd |= XM_MMU_GMII_FD;
1745
89bf5f23
SH		 1746 /*
1747 * Workaround BCOM Errata (#10523) for all BCom Phys
1748 * Enable Power Management after link up
1749 */
64f6b64d
SH		 1750 if (hw->phy_type == SK_PHY_BCOM) {
1751 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1752 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1753 & ~PHY_B_AC_DIS_PM);
1754 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1755 }
baef58b1
SH		 1756
1757 /* enable Rx/Tx */
6b0c1480 1758 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1759 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1760 skge_link_up(skge);
1761}
1762
1763
45bada65 1764static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1765{
1766 struct skge_hw *hw = skge->hw;
1767 int port = skge->port;
45bada65
SH		 1768 u16 isrc;
1769
1770 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1771 if (netif_msg_intr(skge))
1772 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1773 skge->netdev->name, isrc);
baef58b1 1774
45bada65
SH		 1775 if (isrc & PHY_B_IS_PSE)
1776 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1777 hw->dev[port]->name);
baef58b1
SH		 1778
1779 /* Workaround BCom Errata:
1780 * enable and disable loopback mode if "NO HCD" occurs.
1781 */
45bada65 1782 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1783 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1784 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1785 ctrl | PHY_CT_LOOP);
6b0c1480 1786 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1787 ctrl & ~PHY_CT_LOOP);
1788 }
1789
45bada65
SH		 1790 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1791 bcom_check_link(hw, port);
baef58b1 1792
baef58b1
SH		 1793}
1794
2cd8e5d3
SH		 1795static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1796{
1797 int i;
1798
1799 gma_write16(hw, port, GM_SMI_DATA, val);
1800 gma_write16(hw, port, GM_SMI_CTRL,
1801 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1802 for (i = 0; i < PHY_RETRIES; i++) {
1803 udelay(1);
1804
1805 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1806 return 0;
1807 }
1808
1809 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1810 hw->dev[port]->name);
1811 return -EIO;
1812}
1813
1814static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1815{
1816 int i;
1817
1818 gma_write16(hw, port, GM_SMI_CTRL,
1819 GM_SMI_CT_PHY_AD(hw->phy_addr)
1820 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1821
1822 for (i = 0; i < PHY_RETRIES; i++) {
1823 udelay(1);
1824 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1825 goto ready;
1826 }
1827
1828 return -ETIMEDOUT;
1829 ready:
1830 *val = gma_read16(hw, port, GM_SMI_DATA);
1831 return 0;
1832}
1833
1834static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1835{
1836 u16 v = 0;
1837 if (__gm_phy_read(hw, port, reg, &v))
1838 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1839 hw->dev[port]->name);
1840 return v;
1841}
1842
8f3f8193 1843/* Marvell Phy Initialization */
baef58b1
SH		 1844static void yukon_init(struct skge_hw *hw, int port)
1845{
1846 struct skge_port *skge = netdev_priv(hw->dev[port]);
1847 u16 ctrl, ct1000, adv;
baef58b1 1848
baef58b1 1849 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1850 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1851
1852 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1853 PHY_M_EC_MAC_S_MSK);
1854 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1855
c506a509 1856 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1857
6b0c1480 1858 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1859 }
1860
6b0c1480 1861 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1862 if (skge->autoneg == AUTONEG_DISABLE)
1863 ctrl &= ~PHY_CT_ANE;
1864
1865 ctrl |= PHY_CT_RESET;
6b0c1480 1866 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1867
1868 ctrl = 0;
1869 ct1000 = 0;
b18f2091 1870 adv = PHY_AN_CSMA;
baef58b1
SH		 1871
1872 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1873 if (hw->copper) {
baef58b1
SH		 1874 if (skge->advertising & ADVERTISED_1000baseT_Full)
1875 ct1000 |= PHY_M_1000C_AFD;
1876 if (skge->advertising & ADVERTISED_1000baseT_Half)
1877 ct1000 |= PHY_M_1000C_AHD;
1878 if (skge->advertising & ADVERTISED_100baseT_Full)
1879 adv |= PHY_M_AN_100_FD;
1880 if (skge->advertising & ADVERTISED_100baseT_Half)
1881 adv |= PHY_M_AN_100_HD;
1882 if (skge->advertising & ADVERTISED_10baseT_Full)
1883 adv |= PHY_M_AN_10_FD;
1884 if (skge->advertising & ADVERTISED_10baseT_Half)
1885 adv |= PHY_M_AN_10_HD;
baef58b1 1886
4b67be99
SH		 1887 /* Set Flow-control capabilities */
1888 adv |= phy_pause_map[skge->flow_control];
1889 } else {
1890 if (skge->advertising & ADVERTISED_1000baseT_Full)
1891 adv |= PHY_M_AN_1000X_AFD;
1892 if (skge->advertising & ADVERTISED_1000baseT_Half)
1893 adv |= PHY_M_AN_1000X_AHD;
1894
1895 adv |= fiber_pause_map[skge->flow_control];
1896 }
45bada65 1897
baef58b1
SH		 1898 /* Restart Auto-negotiation */
1899 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1900 } else {
1901 /* forced speed/duplex settings */
1902 ct1000 = PHY_M_1000C_MSE;
1903
1904 if (skge->duplex == DUPLEX_FULL)
1905 ctrl |= PHY_CT_DUP_MD;
1906
1907 switch (skge->speed) {
1908 case SPEED_1000:
1909 ctrl |= PHY_CT_SP1000;
1910 break;
1911 case SPEED_100:
1912 ctrl |= PHY_CT_SP100;
1913 break;
1914 }
1915
1916 ctrl |= PHY_CT_RESET;
1917 }
1918
c506a509 1919 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1920
6b0c1480
SH		 1921 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1922 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1923
baef58b1
SH		 1924 /* Enable phy interrupt on autonegotiation complete (or link up) */
1925 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1926 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1927 else
4cde06ed 1928 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1929}
1930
1931static void yukon_reset(struct skge_hw *hw, int port)
1932{
6b0c1480
SH		 1933 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1934 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1935 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1936 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1937 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1938
6b0c1480
SH		 1939 gma_write16(hw, port, GM_RX_CTRL,
1940 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1941 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1942}
1943
c8868611
SH		 1944/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1945static int is_yukon_lite_a0(struct skge_hw *hw)
1946{
1947 u32 reg;
1948 int ret;
1949
1950 if (hw->chip_id != CHIP_ID_YUKON)
1951 return 0;
1952
1953 reg = skge_read32(hw, B2_FAR);
1954 skge_write8(hw, B2_FAR + 3, 0xff);
1955 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1956 skge_write32(hw, B2_FAR, reg);
1957 return ret;
1958}
1959
baef58b1
SH		 1960static void yukon_mac_init(struct skge_hw *hw, int port)
1961{
1962 struct skge_port *skge = netdev_priv(hw->dev[port]);
1963 int i;
1964 u32 reg;
1965 const u8 *addr = hw->dev[port]->dev_addr;
1966
1967 /* WA code for COMA mode -- set PHY reset */
1968 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1969 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1970 reg = skge_read32(hw, B2_GP_IO);
1971 reg |= GP_DIR_9 | GP_IO_9;
1972 skge_write32(hw, B2_GP_IO, reg);
1973 }
baef58b1
SH		 1974
1975 /* hard reset */
6b0c1480
SH		 1976 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1977 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1978
1979 /* WA code for COMA mode -- clear PHY reset */
1980 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1981 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1982 reg = skge_read32(hw, B2_GP_IO);
1983 reg |= GP_DIR_9;
1984 reg &= ~GP_IO_9;
1985 skge_write32(hw, B2_GP_IO, reg);
1986 }
baef58b1
SH		 1987
1988 /* Set hardware config mode */
1989 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1990 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 1991 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 1992
1993 /* Clear GMC reset */
6b0c1480
SH		 1994 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1995 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1996 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
564f9abb 1997
baef58b1
SH		 1998 if (skge->autoneg == AUTONEG_DISABLE) {
1999 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 2000 gma_write16(hw, port, GM_GP_CTRL,
2001 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 2002
2003 switch (skge->speed) {
2004 case SPEED_1000:
564f9abb 2005 reg &= ~GM_GPCR_SPEED_100;
baef58b1 2006 reg |= GM_GPCR_SPEED_1000;
564f9abb 2007 break;
baef58b1 2008 case SPEED_100:
564f9abb 2009 reg &= ~GM_GPCR_SPEED_1000;
baef58b1 2010 reg |= GM_GPCR_SPEED_100;
564f9abb
SH		 2011 break;
2012 case SPEED_10:
2013 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2014 break;
baef58b1
SH		 2015 }
2016
2017 if (skge->duplex == DUPLEX_FULL)
2018 reg |= GM_GPCR_DUP_FULL;
2019 } else
2020 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
564f9abb 2021
baef58b1
SH		 2022 switch (skge->flow_control) {
2023 case FLOW_MODE_NONE:
6b0c1480 2024 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 2025 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2026 break;
2027 case FLOW_MODE_LOC_SEND:
2028 /* disable Rx flow-control */
2029 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
5d5c8e03
SH		 2030 break;
2031 case FLOW_MODE_SYMMETRIC:
2032 case FLOW_MODE_SYM_OR_REM:
2033 /* enable Tx & Rx flow-control */
2034 break;
baef58b1
SH		 2035 }
2036
6b0c1480 2037 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 2038 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2039
baef58b1 2040 yukon_init(hw, port);
baef58b1
SH		 2041
2042 /* MIB clear */
6b0c1480
SH		 2043 reg = gma_read16(hw, port, GM_PHY_ADDR);
2044 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 2045
2046 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 2047 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2048 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 2049
2050 /* transmit control */
6b0c1480 2051 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 2052
2053 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 2054 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 2055 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2056
2057 /* transmit flow control */
6b0c1480 2058 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 2059
2060 /* transmit parameter */
6b0c1480 2061 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 2062 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2063 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2064 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2065
2066 /* serial mode register */
2067 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2068 if (hw->dev[port]->mtu > 1500)
2069 reg |= GM_SMOD_JUMBO_ENA;
2070
6b0c1480 2071 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 2072
2073 /* physical address: used for pause frames */
6b0c1480 2074 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 2075 /* virtual address for data */
6b0c1480 2076 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 2077
2078 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 2079 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2080 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2081 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 2082
2083 /* Initialize Mac Fifo */
2084
2085 /* Configure Rx MAC FIFO */
6b0c1480 2086 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 2087 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 2088
2089 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2090 if (is_yukon_lite_a0(hw))
baef58b1 2091 reg &= ~GMF_RX_F_FL_ON;
c8868611 2092
6b0c1480
SH		 2093 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2094 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 2095 /*
2096 * because Pause Packet Truncation in GMAC is not working
2097 * we have to increase the Flush Threshold to 64 bytes
2098 * in order to flush pause packets in Rx FIFO on Yukon-1
2099 */
2100 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 2101
2102 /* Configure Tx MAC FIFO */
6b0c1480
SH		 2103 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2104 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 2105}
2106
355ec572
SH		 2107/* Go into power down mode */
2108static void yukon_suspend(struct skge_hw *hw, int port)
2109{
2110 u16 ctrl;
2111
2112 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2113 ctrl |= PHY_M_PC_POL_R_DIS;
2114 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2115
2116 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2117 ctrl |= PHY_CT_RESET;
2118 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2119
2120 /* switch IEEE compatible power down mode on */
2121 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2122 ctrl |= PHY_CT_PDOWN;
2123 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2124}
2125
baef58b1
SH		 2126static void yukon_stop(struct skge_port *skge)
2127{
2128 struct skge_hw *hw = skge->hw;
2129 int port = skge->port;
2130
46a60f2d
SH		 2131 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2132 yukon_reset(hw, port);
baef58b1 2133
6b0c1480
SH		 2134 gma_write16(hw, port, GM_GP_CTRL,
2135 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 2136 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 2137 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 2138
355ec572 2139 yukon_suspend(hw, port);
46a60f2d 2140
baef58b1 2141 /* set GPHY Control reset */
46a60f2d
SH		 2142 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2143 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 2144}
2145
2146static void yukon_get_stats(struct skge_port *skge, u64 *data)
2147{
2148 struct skge_hw *hw = skge->hw;
2149 int port = skge->port;
2150 int i;
2151
6b0c1480
SH		 2152 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2153 | gma_read32(hw, port, GM_TXO_OK_LO);
2154 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2155 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 2156
2157 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 2158 data[i] = gma_read32(hw, port,
baef58b1
SH		 2159 skge_stats[i].gma_offset);
2160}
2161
2162static void yukon_mac_intr(struct skge_hw *hw, int port)
2163{
7e676d91
SH		 2164 struct net_device *dev = hw->dev[port];
2165 struct skge_port *skge = netdev_priv(dev);
6b0c1480 2166 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 2167
7e676d91
SH		 2168 if (netif_msg_intr(skge))
2169 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2170 dev->name, status);
2171
baef58b1
SH		 2172 if (status & GM_IS_RX_FF_OR) {
2173 ++skge->net_stats.rx_fifo_errors;
d8a09943 2174 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 2175 }
d8a09943 2176
baef58b1
SH		 2177 if (status & GM_IS_TX_FF_UR) {
2178 ++skge->net_stats.tx_fifo_errors;
d8a09943 2179 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 2180 }
2181
2182}
2183
2184static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2185{
95566065 2186 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 2187 case PHY_M_PS_SPEED_1000:
2188 return SPEED_1000;
2189 case PHY_M_PS_SPEED_100:
2190 return SPEED_100;
2191 default:
2192 return SPEED_10;
2193 }
2194}
2195
2196static void yukon_link_up(struct skge_port *skge)
2197{
2198 struct skge_hw *hw = skge->hw;
2199 int port = skge->port;
2200 u16 reg;
2201
baef58b1 2202 /* Enable Transmit FIFO Underrun */
46a60f2d 2203 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 2204
6b0c1480 2205 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 2206 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2207 reg |= GM_GPCR_DUP_FULL;
2208
2209 /* enable Rx/Tx */
2210 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 2211 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 2212
4cde06ed 2213 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 2214 skge_link_up(skge);
2215}
2216
2217static void yukon_link_down(struct skge_port *skge)
2218{
2219 struct skge_hw *hw = skge->hw;
2220 int port = skge->port;
d8a09943 2221 u16 ctrl;
baef58b1 2222
d8a09943
SH		 2223 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2224 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2225 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 2226
5d5c8e03
SH		 2227 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2228 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2229 ctrl |= PHY_M_AN_ASP;
baef58b1 2230 /* restore Asymmetric Pause bit */
5d5c8e03 2231 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
baef58b1
SH		 2232 }
2233
baef58b1
SH		 2234 skge_link_down(skge);
2235
2236 yukon_init(hw, port);
2237}
2238
2239static void yukon_phy_intr(struct skge_port *skge)
2240{
2241 struct skge_hw *hw = skge->hw;
2242 int port = skge->port;
2243 const char *reason = NULL;
2244 u16 istatus, phystat;
2245
6b0c1480
SH		 2246 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2247 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 2248
2249 if (netif_msg_intr(skge))
2250 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2251 skge->netdev->name, istatus, phystat);
baef58b1
SH		 2252
2253 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 2254 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 2255 & PHY_M_AN_RF) {
2256 reason = "remote fault";
2257 goto failed;
2258 }
2259
c506a509 2260 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 2261 reason = "master/slave fault";
2262 goto failed;
2263 }
2264
2265 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2266 reason = "speed/duplex";
2267 goto failed;
2268 }
2269
2270 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2271 ? DUPLEX_FULL : DUPLEX_HALF;
2272 skge->speed = yukon_speed(hw, phystat);
2273
baef58b1
SH		 2274 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2275 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2276 case PHY_M_PS_PAUSE_MSK:
5d5c8e03 2277 skge->flow_status = FLOW_STAT_SYMMETRIC;
baef58b1
SH		 2278 break;
2279 case PHY_M_PS_RX_P_EN:
5d5c8e03 2280 skge->flow_status = FLOW_STAT_REM_SEND;
baef58b1
SH		 2281 break;
2282 case PHY_M_PS_TX_P_EN:
5d5c8e03 2283 skge->flow_status = FLOW_STAT_LOC_SEND;
baef58b1
SH		 2284 break;
2285 default:
5d5c8e03 2286 skge->flow_status = FLOW_STAT_NONE;
baef58b1
SH		 2287 }
2288
5d5c8e03 2289 if (skge->flow_status == FLOW_STAT_NONE ||
baef58b1 2290 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 2291 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 2292 else
6b0c1480 2293 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 2294 yukon_link_up(skge);
2295 return;
2296 }
2297
2298 if (istatus & PHY_M_IS_LSP_CHANGE)
2299 skge->speed = yukon_speed(hw, phystat);
2300
2301 if (istatus & PHY_M_IS_DUP_CHANGE)
2302 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2303 if (istatus & PHY_M_IS_LST_CHANGE) {
2304 if (phystat & PHY_M_PS_LINK_UP)
2305 yukon_link_up(skge);
2306 else
2307 yukon_link_down(skge);
2308 }
2309 return;
2310 failed:
2311 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2312 skge->netdev->name, reason);
2313
2314 /* XXX restart autonegotiation? */
2315}
2316
ee294dcd
SH		 2317static void skge_phy_reset(struct skge_port *skge)
2318{
2319 struct skge_hw *hw = skge->hw;
2320 int port = skge->port;
aae343d4 2321 struct net_device *dev = hw->dev[port];
ee294dcd
SH		 2322
2323 netif_stop_queue(skge->netdev);
2324 netif_carrier_off(skge->netdev);
2325
9cbe330f 2326 spin_lock_bh(&hw->phy_lock);
ee294dcd
SH		 2327 if (hw->chip_id == CHIP_ID_GENESIS) {
2328 genesis_reset(hw, port);
2329 genesis_mac_init(hw, port);
2330 } else {
2331 yukon_reset(hw, port);
2332 yukon_init(hw, port);
2333 }
9cbe330f 2334 spin_unlock_bh(&hw->phy_lock);
75814090
SH		 2335
2336 dev->set_multicast_list(dev);
ee294dcd
SH		 2337}
2338
2cd8e5d3
SH		 2339/* Basic MII support */
2340static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2341{
2342 struct mii_ioctl_data *data = if_mii(ifr);
2343 struct skge_port *skge = netdev_priv(dev);
2344 struct skge_hw *hw = skge->hw;
2345 int err = -EOPNOTSUPP;
2346
2347 if (!netif_running(dev))
2348 return -ENODEV; /* Phy still in reset */
2349
2350 switch(cmd) {
2351 case SIOCGMIIPHY:
2352 data->phy_id = hw->phy_addr;
2353
2354 /* fallthru */
2355 case SIOCGMIIREG: {
2356 u16 val = 0;
9cbe330f 2357 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2358 if (hw->chip_id == CHIP_ID_GENESIS)
2359 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2360 else
2361 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
9cbe330f 2362 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2363 data->val_out = val;
2364 break;
2365 }
2366
2367 case SIOCSMIIREG:
2368 if (!capable(CAP_NET_ADMIN))
2369 return -EPERM;
2370
9cbe330f 2371 spin_lock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2372 if (hw->chip_id == CHIP_ID_GENESIS)
2373 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2374 data->val_in);
2375 else
2376 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2377 data->val_in);
9cbe330f 2378 spin_unlock_bh(&hw->phy_lock);
2cd8e5d3
SH		 2379 break;
2380 }
2381 return err;
2382}
2383
baef58b1
SH		 2384static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2385{
2386 u32 end;
2387
2388 start /= 8;
2389 len /= 8;
2390 end = start + len - 1;
2391
2392 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2393 skge_write32(hw, RB_ADDR(q, RB_START), start);
2394 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2395 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2396 skge_write32(hw, RB_ADDR(q, RB_END), end);
2397
2398 if (q == Q_R1 || q == Q_R2) {
2399 /* Set thresholds on receive queue's */
2400 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2401 start + (2*len)/3);
2402 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2403 start + (len/3));
2404 } else {
2405 /* Enable store & forward on Tx queue's because
2406 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2407 */
2408 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2409 }
2410
2411 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2412}
2413
2414/* Setup Bus Memory Interface */
2415static void skge_qset(struct skge_port *skge, u16 q,
2416 const struct skge_element *e)
2417{
2418 struct skge_hw *hw = skge->hw;
2419 u32 watermark = 0x600;
2420 u64 base = skge->dma + (e->desc - skge->mem);
2421
2422 /* optimization to reduce window on 32bit/33mhz */
2423 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2424 watermark /= 2;
2425
2426 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2427 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2428 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2429 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2430}
2431
2432static int skge_up(struct net_device *dev)
2433{
2434 struct skge_port *skge = netdev_priv(dev);
2435 struct skge_hw *hw = skge->hw;
2436 int port = skge->port;
2437 u32 chunk, ram_addr;
2438 size_t rx_size, tx_size;
2439 int err;
2440
fae87592
SH		 2441 if (!is_valid_ether_addr(dev->dev_addr))
2442 return -EINVAL;
2443
baef58b1
SH		 2444 if (netif_msg_ifup(skge))
2445 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2446
19a33d4e 2447 if (dev->mtu > RX_BUF_SIZE)
901ccefb 2448 skge->rx_buf_size = dev->mtu + ETH_HLEN;
19a33d4e
SH		 2449 else
2450 skge->rx_buf_size = RX_BUF_SIZE;
2451
2452
baef58b1
SH		 2453 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2454 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2455 skge->mem_size = tx_size + rx_size;
2456 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2457 if (!skge->mem)
2458 return -ENOMEM;
2459
c3da1447
SH		 2460 BUG_ON(skge->dma & 7);
2461
2462 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
1479d13c 2463 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
c3da1447
SH		 2464 err = -EINVAL;
2465 goto free_pci_mem;
2466 }
2467
baef58b1
SH		 2468 memset(skge->mem, 0, skge->mem_size);
2469
203babb6
SH		 2470 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2471 if (err)
baef58b1
SH		 2472 goto free_pci_mem;
2473
c54f9765 2474 err = skge_rx_fill(dev);
19a33d4e 2475 if (err)
baef58b1
SH		 2476 goto free_rx_ring;
2477
203babb6
SH		 2478 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2479 skge->dma + rx_size);
2480 if (err)
baef58b1
SH		 2481 goto free_rx_ring;
2482
8f3f8193 2483 /* Initialize MAC */
9cbe330f 2484 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2485 if (hw->chip_id == CHIP_ID_GENESIS)
2486 genesis_mac_init(hw, port);
2487 else
2488 yukon_mac_init(hw, port);
9cbe330f 2489 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 2490
2491 /* Configure RAMbuffers */
981d0377 2492 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2493 ram_addr = hw->ram_offset + 2 * chunk * port;
2494
2495 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2496 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2497
2498 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2499 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2500 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2501
2502 /* Start receiver BMU */
2503 wmb();
2504 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2505 skge_led(skge, LED_MODE_ON);
baef58b1 2506
4ebabfcb
SH		 2507 spin_lock_irq(&hw->hw_lock);
2508 hw->intr_mask |= portmask[port];
2509 skge_write32(hw, B0_IMSK, hw->intr_mask);
2510 spin_unlock_irq(&hw->hw_lock);
2511
239e44e1 2512 netif_poll_enable(dev);
baef58b1
SH		 2513 return 0;
2514
2515 free_rx_ring:
2516 skge_rx_clean(skge);
2517 kfree(skge->rx_ring.start);
2518 free_pci_mem:
2519 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2520 skge->mem = NULL;
baef58b1
SH		 2521
2522 return err;
2523}
2524
2525static int skge_down(struct net_device *dev)
2526{
2527 struct skge_port *skge = netdev_priv(dev);
2528 struct skge_hw *hw = skge->hw;
2529 int port = skge->port;
2530
7731a4ea
SH		 2531 if (skge->mem == NULL)
2532 return 0;
2533
baef58b1
SH		 2534 if (netif_msg_ifdown(skge))
2535 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2536
2537 netif_stop_queue(dev);
e5b9ddd9 2538 netif_carrier_off(dev);
64f6b64d 2539 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
9cbe330f 2540 del_timer_sync(&skge->link_timer);
baef58b1 2541
4ebabfcb
SH		 2542 netif_poll_disable(dev);
2543
2544 spin_lock_irq(&hw->hw_lock);
2545 hw->intr_mask &= ~portmask[port];
2546 skge_write32(hw, B0_IMSK, hw->intr_mask);
2547 spin_unlock_irq(&hw->hw_lock);
2548
46a60f2d
SH		 2549 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2550 if (hw->chip_id == CHIP_ID_GENESIS)
2551 genesis_stop(skge);
2552 else
2553 yukon_stop(skge);
2554
baef58b1
SH		 2555 /* Stop transmitter */
2556 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2557 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2558 RB_RST_SET|RB_DIS_OP_MD);
2559
baef58b1
SH		 2560
2561 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2562 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2563 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2564
2565 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2566 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2567 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2568
2569 /* Reset PCI FIFO */
2570 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2571 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2572
2573 /* Reset the RAM Buffer async Tx queue */
2574 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2575 /* stop receiver */
2576 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2577 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2578 RB_RST_SET|RB_DIS_OP_MD);
2579 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2580
2581 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2582 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2583 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2584 } else {
6b0c1480
SH		 2585 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2586 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2587 }
2588
6abebb53 2589 skge_led(skge, LED_MODE_OFF);
baef58b1 2590
e3a1b99f 2591 netif_tx_lock_bh(dev);
513f533e 2592 skge_tx_clean(dev);
e3a1b99f
SH		 2593 netif_tx_unlock_bh(dev);
2594
baef58b1
SH		 2595 skge_rx_clean(skge);
2596
2597 kfree(skge->rx_ring.start);
2598 kfree(skge->tx_ring.start);
2599 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
7731a4ea 2600 skge->mem = NULL;
baef58b1
SH		 2601 return 0;
2602}
2603
29b4e886
SH		 2604static inline int skge_avail(const struct skge_ring *ring)
2605{
2606 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2607 + (ring->to_clean - ring->to_use) - 1;
2608}
2609
baef58b1
SH		 2610static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2611{
2612 struct skge_port *skge = netdev_priv(dev);
2613 struct skge_hw *hw = skge->hw;
baef58b1
SH		 2614 struct skge_element *e;
2615 struct skge_tx_desc *td;
2616 int i;
2617 u32 control, len;
2618 u64 map;
baef58b1 2619
5b057c6b 2620 if (skb_padto(skb, ETH_ZLEN))
baef58b1
SH		 2621 return NETDEV_TX_OK;
2622
513f533e 2623 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
baef58b1 2624 return NETDEV_TX_BUSY;
baef58b1 2625
7c442fa1 2626 e = skge->tx_ring.to_use;
baef58b1 2627 td = e->desc;
7c442fa1 2628 BUG_ON(td->control & BMU_OWN);
baef58b1
SH		 2629 e->skb = skb;
2630 len = skb_headlen(skb);
2631 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2632 pci_unmap_addr_set(e, mapaddr, map);
2633 pci_unmap_len_set(e, maplen, len);
2634
2635 td->dma_lo = map;
2636 td->dma_hi = map >> 32;
2637
84fa7933 2638 if (skb->ip_summed == CHECKSUM_PARTIAL) {
baef58b1
SH		 2639 int offset = skb->h.raw - skb->data;
2640
2641 /* This seems backwards, but it is what the sk98lin
2642 * does. Looks like hardware is wrong?
2643 */
ea182d4a 2644 if (skb->h.ipiph->protocol == IPPROTO_UDP
981d0377 2645 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2646 control = BMU_TCP_CHECK;
2647 else
2648 control = BMU_UDP_CHECK;
2649
2650 td->csum_offs = 0;
2651 td->csum_start = offset;
ff1dcadb 2652 td->csum_write = offset + skb->csum_offset;
baef58b1
SH		 2653 } else
2654 control = BMU_CHECK;
2655
2656 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2657 control |= BMU_EOF| BMU_IRQ_EOF;
2658 else {
2659 struct skge_tx_desc *tf = td;
2660
2661 control |= BMU_STFWD;
2662 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2663 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2664
2665 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2666 frag->size, PCI_DMA_TODEVICE);
2667
2668 e = e->next;
7c442fa1 2669 e->skb = skb;
baef58b1 2670 tf = e->desc;
7c442fa1
SH		 2671 BUG_ON(tf->control & BMU_OWN);
2672
baef58b1
SH		 2673 tf->dma_lo = map;
2674 tf->dma_hi = (u64) map >> 32;
2675 pci_unmap_addr_set(e, mapaddr, map);
2676 pci_unmap_len_set(e, maplen, frag->size);
2677
2678 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2679 }
2680 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2681 }
2682 /* Make sure all the descriptors written */
2683 wmb();
2684 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2685 wmb();
2686
2687 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2688
7c442fa1 2689 if (unlikely(netif_msg_tx_queued(skge)))
0b2d7fea 2690 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
7c442fa1 2691 dev->name, e - skge->tx_ring.start, skb->len);
baef58b1 2692
7c442fa1 2693 skge->tx_ring.to_use = e->next;
9db96479 2694 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
baef58b1
SH		 2695 pr_debug("%s: transmit queue full\n", dev->name);
2696 netif_stop_queue(dev);
2697 }
2698
c68ce71a
SH		 2699 dev->trans_start = jiffies;
2700
baef58b1
SH		 2701 return NETDEV_TX_OK;
2702}
2703
7c442fa1
SH		 2704
2705/* Free resources associated with this reing element */
2706static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2707 u32 control)
866b4f3e
SH		 2708{
2709 struct pci_dev *pdev = skge->hw->pdev;
866b4f3e 2710
7c442fa1 2711 BUG_ON(!e->skb);
866b4f3e 2712
7c442fa1
SH		 2713 /* skb header vs. fragment */
2714 if (control & BMU_STF)
866b4f3e 2715 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
7c442fa1
SH		 2716 pci_unmap_len(e, maplen),
2717 PCI_DMA_TODEVICE);
2718 else
2719 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2720 pci_unmap_len(e, maplen),
2721 PCI_DMA_TODEVICE);
866b4f3e 2722
7c442fa1
SH		 2723 if (control & BMU_EOF) {
2724 if (unlikely(netif_msg_tx_done(skge)))
2725 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2726 skge->netdev->name, e - skge->tx_ring.start);
866b4f3e 2727
513f533e 2728 dev_kfree_skb(e->skb);
baef58b1 2729 }
7c442fa1 2730 e->skb = NULL;
baef58b1
SH		 2731}
2732
7c442fa1 2733/* Free all buffers in transmit ring */
513f533e 2734static void skge_tx_clean(struct net_device *dev)
baef58b1 2735{
513f533e 2736 struct skge_port *skge = netdev_priv(dev);
7c442fa1 2737 struct skge_element *e;
baef58b1 2738
7c442fa1
SH		 2739 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2740 struct skge_tx_desc *td = e->desc;
2741 skge_tx_free(skge, e, td->control);
2742 td->control = 0;
2743 }
2744
2745 skge->tx_ring.to_clean = e;
513f533e 2746 netif_wake_queue(dev);
baef58b1
SH		 2747}
2748
2749static void skge_tx_timeout(struct net_device *dev)
2750{
2751 struct skge_port *skge = netdev_priv(dev);
2752
2753 if (netif_msg_timer(skge))
2754 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2755
2756 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
513f533e 2757 skge_tx_clean(dev);
baef58b1
SH		 2758}
2759
2760static int skge_change_mtu(struct net_device *dev, int new_mtu)
2761{
7731a4ea 2762 int err;
baef58b1 2763
95566065 2764 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2765 return -EINVAL;
2766
7731a4ea
SH		 2767 if (!netif_running(dev)) {
2768 dev->mtu = new_mtu;
2769 return 0;
2770 }
2771
2772 skge_down(dev);
baef58b1 2773
19a33d4e 2774 dev->mtu = new_mtu;
7731a4ea
SH		 2775
2776 err = skge_up(dev);
2777 if (err)
2778 dev_close(dev);
baef58b1
SH		 2779
2780 return err;
2781}
2782
c4cd29d2
SH		 2783static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2784
2785static void genesis_add_filter(u8 filter[8], const u8 *addr)
2786{
2787 u32 crc, bit;
2788
2789 crc = ether_crc_le(ETH_ALEN, addr);
2790 bit = ~crc & 0x3f;
2791 filter[bit/8] |= 1 << (bit%8);
2792}
2793
baef58b1
SH		 2794static void genesis_set_multicast(struct net_device *dev)
2795{
2796 struct skge_port *skge = netdev_priv(dev);
2797 struct skge_hw *hw = skge->hw;
2798 int port = skge->port;
2799 int i, count = dev->mc_count;
2800 struct dev_mc_list *list = dev->mc_list;
2801 u32 mode;
2802 u8 filter[8];
2803
6b0c1480 2804 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2805 mode |= XM_MD_ENA_HASH;
2806 if (dev->flags & IFF_PROMISC)
2807 mode |= XM_MD_ENA_PROM;
2808 else
2809 mode &= ~XM_MD_ENA_PROM;
2810
2811 if (dev->flags & IFF_ALLMULTI)
2812 memset(filter, 0xff, sizeof(filter));
2813 else {
2814 memset(filter, 0, sizeof(filter));
c4cd29d2
SH		 2815
2816 if (skge->flow_status == FLOW_STAT_REM_SEND
2817 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2818 genesis_add_filter(filter, pause_mc_addr);
2819
2820 for (i = 0; list && i < count; i++, list = list->next)
2821 genesis_add_filter(filter, list->dmi_addr);
baef58b1
SH		 2822 }
2823
6b0c1480 2824 xm_write32(hw, port, XM_MODE, mode);
45bada65 2825 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2826}
2827
c4cd29d2
SH		 2828static void yukon_add_filter(u8 filter[8], const u8 *addr)
2829{
2830 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2831 filter[bit/8] |= 1 << (bit%8);
2832}
2833
baef58b1
SH		 2834static void yukon_set_multicast(struct net_device *dev)
2835{
2836 struct skge_port *skge = netdev_priv(dev);
2837 struct skge_hw *hw = skge->hw;
2838 int port = skge->port;
2839 struct dev_mc_list *list = dev->mc_list;
c4cd29d2
SH		 2840 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
2841 || skge->flow_status == FLOW_STAT_SYMMETRIC);
baef58b1
SH		 2842 u16 reg;
2843 u8 filter[8];
2844
2845 memset(filter, 0, sizeof(filter));
2846
6b0c1480 2847 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2848 reg |= GM_RXCR_UCF_ENA;
2849
8f3f8193 2850 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2851 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2852 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2853 memset(filter, 0xff, sizeof(filter));
c4cd29d2 2854 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
baef58b1
SH		 2855 reg &= ~GM_RXCR_MCF_ENA;
2856 else {
2857 int i;
2858 reg |= GM_RXCR_MCF_ENA;
2859
c4cd29d2
SH		 2860 if (rx_pause)
2861 yukon_add_filter(filter, pause_mc_addr);
2862
2863 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2864 yukon_add_filter(filter, list->dmi_addr);
baef58b1
SH		 2865 }
2866
2867
6b0c1480 2868 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2869 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2870 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2871 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2872 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2873 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2874 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2875 (u16)filter[6] | ((u16)filter[7] << 8));
2876
6b0c1480 2877 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2878}
2879
383181ac
SH		 2880static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2881{
2882 if (hw->chip_id == CHIP_ID_GENESIS)
2883 return status >> XMR_FS_LEN_SHIFT;
2884 else
2885 return status >> GMR_FS_LEN_SHIFT;
2886}
2887
baef58b1
SH		 2888static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2889{
2890 if (hw->chip_id == CHIP_ID_GENESIS)
2891 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2892 else
2893 return (status & GMR_FS_ANY_ERR) ||
2894 (status & GMR_FS_RX_OK) == 0;
2895}
2896
19a33d4e
SH		 2897
2898/* Get receive buffer from descriptor.
2899 * Handles copy of small buffers and reallocation failures
2900 */
c54f9765
SH		 2901static struct sk_buff *skge_rx_get(struct net_device *dev,
2902 struct skge_element *e,
2903 u32 control, u32 status, u16 csum)
19a33d4e 2904{
c54f9765 2905 struct skge_port *skge = netdev_priv(dev);
383181ac
SH		 2906 struct sk_buff *skb;
2907 u16 len = control & BMU_BBC;
2908
2909 if (unlikely(netif_msg_rx_status(skge)))
2910 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
c54f9765 2911 dev->name, e - skge->rx_ring.start,
383181ac
SH		 2912 status, len);
2913
2914 if (len > skge->rx_buf_size)
2915 goto error;
2916
2917 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2918 goto error;
2919
2920 if (bad_phy_status(skge->hw, status))
2921 goto error;
2922
2923 if (phy_length(skge->hw, status) != len)
2924 goto error;
19a33d4e
SH		 2925
2926 if (len < RX_COPY_THRESHOLD) {
c54f9765 2927 skb = netdev_alloc_skb(dev, len + 2);
383181ac
SH		 2928 if (!skb)
2929 goto resubmit;
19a33d4e 2930
383181ac 2931 skb_reserve(skb, 2);
19a33d4e
SH		 2932 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2933 pci_unmap_addr(e, mapaddr),
2934 len, PCI_DMA_FROMDEVICE);
383181ac 2935 memcpy(skb->data, e->skb->data, len);
19a33d4e
SH		 2936 pci_dma_sync_single_for_device(skge->hw->pdev,
2937 pci_unmap_addr(e, mapaddr),
2938 len, PCI_DMA_FROMDEVICE);
19a33d4e 2939 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 2940 } else {
383181ac 2941 struct sk_buff *nskb;
c54f9765 2942 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
383181ac
SH		 2943 if (!nskb)
2944 goto resubmit;
19a33d4e 2945
901ccefb 2946 skb_reserve(nskb, NET_IP_ALIGN);
19a33d4e
SH		 2947 pci_unmap_single(skge->hw->pdev,
2948 pci_unmap_addr(e, mapaddr),
2949 pci_unmap_len(e, maplen),
2950 PCI_DMA_FROMDEVICE);
2951 skb = e->skb;
383181ac 2952 prefetch(skb->data);
19a33d4e 2953 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 2954 }
383181ac
SH		 2955
2956 skb_put(skb, len);
383181ac
SH		 2957 if (skge->rx_csum) {
2958 skb->csum = csum;
84fa7933 2959 skb->ip_summed = CHECKSUM_COMPLETE;
383181ac
SH		 2960 }
2961
c54f9765 2962 skb->protocol = eth_type_trans(skb, dev);
383181ac
SH		 2963
2964 return skb;
2965error:
2966
2967 if (netif_msg_rx_err(skge))
2968 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
c54f9765 2969 dev->name, e - skge->rx_ring.start,
383181ac
SH		 2970 control, status);
2971
2972 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2973 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2974 skge->net_stats.rx_length_errors++;
2975 if (status & XMR_FS_FRA_ERR)
2976 skge->net_stats.rx_frame_errors++;
2977 if (status & XMR_FS_FCS_ERR)
2978 skge->net_stats.rx_crc_errors++;
2979 } else {
2980 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2981 skge->net_stats.rx_length_errors++;
2982 if (status & GMR_FS_FRAGMENT)
2983 skge->net_stats.rx_frame_errors++;
2984 if (status & GMR_FS_CRC_ERR)
2985 skge->net_stats.rx_crc_errors++;
2986 }
2987
2988resubmit:
2989 skge_rx_reuse(e, skge->rx_buf_size);
2990 return NULL;
baef58b1
SH		 2991}
2992
7c442fa1 2993/* Free all buffers in Tx ring which are no longer owned by device */
513f533e 2994static void skge_tx_done(struct net_device *dev)
00a6cae2 2995{
7c442fa1 2996 struct skge_port *skge = netdev_priv(dev);
00a6cae2 2997 struct skge_ring *ring = &skge->tx_ring;
7c442fa1
SH		 2998 struct skge_element *e;
2999
513f533e 3000 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
00a6cae2 3001
513f533e 3002 netif_tx_lock(dev);
866b4f3e 3003 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
00a6cae2 3004 struct skge_tx_desc *td = e->desc;
00a6cae2 3005
866b4f3e 3006 if (td->control & BMU_OWN)
00a6cae2
SH		 3007 break;
3008
7c442fa1 3009 skge_tx_free(skge, e, td->control);
00a6cae2 3010 }
7c442fa1 3011 skge->tx_ring.to_clean = e;
866b4f3e 3012
513f533e
SH		 3013 if (skge_avail(&skge->tx_ring) > TX_LOW_WATER)
3014 netif_wake_queue(dev);
00a6cae2 3015
513f533e 3016 netif_tx_unlock(dev);
00a6cae2 3017}
19a33d4e 3018
baef58b1
SH		 3019static int skge_poll(struct net_device *dev, int *budget)
3020{
3021 struct skge_port *skge = netdev_priv(dev);
3022 struct skge_hw *hw = skge->hw;
3023 struct skge_ring *ring = &skge->rx_ring;
3024 struct skge_element *e;
d15e9c4d 3025 unsigned long flags;
00a6cae2
SH		 3026 int to_do = min(dev->quota, *budget);
3027 int work_done = 0;
3028
513f533e
SH		 3029 skge_tx_done(dev);
3030
3031 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3032
1631aef1 3033 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 3034 struct skge_rx_desc *rd = e->desc;
19a33d4e 3035 struct sk_buff *skb;
383181ac 3036 u32 control;
baef58b1
SH		 3037
3038 rmb();
3039 control = rd->control;
3040 if (control & BMU_OWN)
3041 break;
3042
c54f9765 3043 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
19a33d4e 3044 if (likely(skb)) {
19a33d4e
SH		 3045 dev->last_rx = jiffies;
3046 netif_receive_skb(skb);
baef58b1 3047
19a33d4e 3048 ++work_done;
5a011447 3049 }
baef58b1
SH		 3050 }
3051 ring->to_clean = e;
3052
baef58b1
SH		 3053 /* restart receiver */
3054 wmb();
a9cdab86 3055 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
baef58b1 3056
19a33d4e
SH		 3057 *budget -= work_done;
3058 dev->quota -= work_done;
3059
3060 if (work_done >= to_do)
3061 return 1; /* not done */
baef58b1 3062
d15e9c4d 3063 spin_lock_irqsave(&hw->hw_lock, flags);
513f533e 3064 __netif_rx_complete(dev);
4ebabfcb 3065 hw->intr_mask |= napimask[skge->port];
80dd857d 3066 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3067 skge_read32(hw, B0_IMSK);
d15e9c4d 3068 spin_unlock_irqrestore(&hw->hw_lock, flags);
1631aef1 3069
19a33d4e 3070 return 0;
baef58b1
SH		 3071}
3072
f6620cab
SH		 3073/* Parity errors seem to happen when Genesis is connected to a switch
3074 * with no other ports present. Heartbeat error??
3075 */
baef58b1
SH		 3076static void skge_mac_parity(struct skge_hw *hw, int port)
3077{
f6620cab
SH		 3078 struct net_device *dev = hw->dev[port];
3079
3080 if (dev) {
3081 struct skge_port *skge = netdev_priv(dev);
3082 ++skge->net_stats.tx_heartbeat_errors;
3083 }
baef58b1
SH		 3084
3085 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 3086 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 3087 MFF_CLR_PERR);
3088 else
3089 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 3090 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 3091 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 3092 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3093}
3094
baef58b1
SH		 3095static void skge_mac_intr(struct skge_hw *hw, int port)
3096{
95566065 3097 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 3098 genesis_mac_intr(hw, port);
3099 else
3100 yukon_mac_intr(hw, port);
3101}
3102
3103/* Handle device specific framing and timeout interrupts */
3104static void skge_error_irq(struct skge_hw *hw)
3105{
1479d13c 3106 struct pci_dev *pdev = hw->pdev;
baef58b1
SH		 3107 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3108
3109 if (hw->chip_id == CHIP_ID_GENESIS) {
3110 /* clear xmac errors */
3111 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 3112 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 3113 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 3114 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 3115 } else {
3116 /* Timestamp (unused) overflow */
3117 if (hwstatus & IS_IRQ_TIST_OV)
3118 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 3119 }
3120
3121 if (hwstatus & IS_RAM_RD_PAR) {
1479d13c 3122 dev_err(&pdev->dev, "Ram read data parity error\n");
baef58b1
SH		 3123 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3124 }
3125
3126 if (hwstatus & IS_RAM_WR_PAR) {
1479d13c 3127 dev_err(&pdev->dev, "Ram write data parity error\n");
baef58b1
SH		 3128 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3129 }
3130
3131 if (hwstatus & IS_M1_PAR_ERR)
3132 skge_mac_parity(hw, 0);
3133
3134 if (hwstatus & IS_M2_PAR_ERR)
3135 skge_mac_parity(hw, 1);
3136
b9d64acc 3137 if (hwstatus & IS_R1_PAR_ERR) {
1479d13c
SH		 3138 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3139 hw->dev[0]->name);
baef58b1 3140 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
b9d64acc 3141 }
baef58b1 3142
b9d64acc 3143 if (hwstatus & IS_R2_PAR_ERR) {
1479d13c
SH		 3144 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3145 hw->dev[1]->name);
baef58b1 3146 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
b9d64acc 3147 }
baef58b1
SH		 3148
3149 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
b9d64acc
SH		 3150 u16 pci_status, pci_cmd;
3151
1479d13c
SH		 3152 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3153 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
baef58b1 3154
1479d13c
SH		 3155 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3156 pci_cmd, pci_status);
b9d64acc
SH		 3157
3158 /* Write the error bits back to clear them. */
3159 pci_status &= PCI_STATUS_ERROR_BITS;
3160 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1479d13c 3161 pci_write_config_word(pdev, PCI_COMMAND,
b9d64acc 3162 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
1479d13c 3163 pci_write_config_word(pdev, PCI_STATUS, pci_status);
b9d64acc 3164 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1 3165
050ec18a 3166 /* if error still set then just ignore it */
baef58b1
SH		 3167 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3168 if (hwstatus & IS_IRQ_STAT) {
1479d13c 3169 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
baef58b1
SH		 3170 hw->intr_mask &= ~IS_HW_ERR;
3171 }
3172 }
3173}
3174
3175/*
9cbe330f 3176 * Interrupt from PHY are handled in tasklet (softirq)
baef58b1
SH		 3177 * because accessing phy registers requires spin wait which might
3178 * cause excess interrupt latency.
3179 */
9cbe330f 3180static void skge_extirq(unsigned long arg)
baef58b1 3181{
9cbe330f 3182 struct skge_hw *hw = (struct skge_hw *) arg;
baef58b1
SH		 3183 int port;
3184
cfc3ed79 3185 for (port = 0; port < hw->ports; port++) {
baef58b1
SH		 3186 struct net_device *dev = hw->dev[port];
3187
cfc3ed79 3188 if (netif_running(dev)) {
9cbe330f
SH		 3189 struct skge_port *skge = netdev_priv(dev);
3190
3191 spin_lock(&hw->phy_lock);
baef58b1
SH		 3192 if (hw->chip_id != CHIP_ID_GENESIS)
3193 yukon_phy_intr(skge);
64f6b64d 3194 else if (hw->phy_type == SK_PHY_BCOM)
45bada65 3195 bcom_phy_intr(skge);
9cbe330f 3196 spin_unlock(&hw->phy_lock);
baef58b1
SH		 3197 }
3198 }
baef58b1 3199
7c442fa1 3200 spin_lock_irq(&hw->hw_lock);
baef58b1
SH		 3201 hw->intr_mask |= IS_EXT_REG;
3202 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3203 skge_read32(hw, B0_IMSK);
7c442fa1 3204 spin_unlock_irq(&hw->hw_lock);
baef58b1
SH		 3205}
3206
7d12e780 3207static irqreturn_t skge_intr(int irq, void *dev_id)
baef58b1
SH		 3208{
3209 struct skge_hw *hw = dev_id;
cfc3ed79 3210 u32 status;
29365c90 3211 int handled = 0;
baef58b1 3212
29365c90 3213 spin_lock(&hw->hw_lock);
cfc3ed79
SH		 3214 /* Reading this register masks IRQ */
3215 status = skge_read32(hw, B0_SP_ISRC);
0486a8c8 3216 if (status == 0 || status == ~0)
29365c90 3217 goto out;
baef58b1 3218
29365c90 3219 handled = 1;
7c442fa1 3220 status &= hw->intr_mask;
cfc3ed79
SH		 3221 if (status & IS_EXT_REG) {
3222 hw->intr_mask &= ~IS_EXT_REG;
9cbe330f 3223 tasklet_schedule(&hw->phy_task);
cfc3ed79
SH		 3224 }
3225
513f533e
SH		 3226 if (status & (IS_XA1_F|IS_R1_F)) {
3227 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
7c442fa1 3228 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 3229 }
3230
7c442fa1
SH		 3231 if (status & IS_PA_TO_TX1)
3232 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
cfc3ed79 3233
d25f5a67
SH		 3234 if (status & IS_PA_TO_RX1) {
3235 struct skge_port *skge = netdev_priv(hw->dev[0]);
d25f5a67 3236
d25f5a67 3237 ++skge->net_stats.rx_over_errors;
7c442fa1 3238 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
d25f5a67
SH		 3239 }
3240
d25f5a67 3241
baef58b1
SH		 3242 if (status & IS_MAC1)
3243 skge_mac_intr(hw, 0);
95566065 3244
7c442fa1 3245 if (hw->dev[1]) {
513f533e
SH		 3246 if (status & (IS_XA2_F|IS_R2_F)) {
3247 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
7c442fa1
SH		 3248 netif_rx_schedule(hw->dev[1]);
3249 }
3250
3251 if (status & IS_PA_TO_RX2) {
3252 struct skge_port *skge = netdev_priv(hw->dev[1]);
3253 ++skge->net_stats.rx_over_errors;
3254 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3255 }
3256
3257 if (status & IS_PA_TO_TX2)
3258 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3259
3260 if (status & IS_MAC2)
3261 skge_mac_intr(hw, 1);
3262 }
baef58b1
SH		 3263
3264 if (status & IS_HW_ERR)
3265 skge_error_irq(hw);
3266
7e676d91 3267 skge_write32(hw, B0_IMSK, hw->intr_mask);
78bc2186 3268 skge_read32(hw, B0_IMSK);
29365c90 3269out:
7c442fa1 3270 spin_unlock(&hw->hw_lock);
baef58b1 3271
29365c90 3272 return IRQ_RETVAL(handled);
baef58b1
SH		 3273}
3274
3275#ifdef CONFIG_NET_POLL_CONTROLLER
3276static void skge_netpoll(struct net_device *dev)
3277{
3278 struct skge_port *skge = netdev_priv(dev);
3279
3280 disable_irq(dev->irq);
7d12e780 3281 skge_intr(dev->irq, skge->hw);
baef58b1
SH		 3282 enable_irq(dev->irq);
3283}
3284#endif
3285
3286static int skge_set_mac_address(struct net_device *dev, void *p)
3287{
3288 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 3289 struct skge_hw *hw = skge->hw;
3290 unsigned port = skge->port;
3291 const struct sockaddr *addr = p;
2eb3e621 3292 u16 ctrl;
baef58b1
SH		 3293
3294 if (!is_valid_ether_addr(addr->sa_data))
3295 return -EADDRNOTAVAIL;
3296
baef58b1 3297 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 3298
9cbe330f
SH		 3299 if (!netif_running(dev)) {
3300 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3301 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3302 } else {
3303 /* disable Rx */
3304 spin_lock_bh(&hw->phy_lock);
3305 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3306 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
2eb3e621 3307
9cbe330f
SH		 3308 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3309 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
2eb3e621 3310
2eb3e621
SH		 3311 if (hw->chip_id == CHIP_ID_GENESIS)
3312 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3313 else {
3314 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3315 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3316 }
2eb3e621 3317
9cbe330f
SH		 3318 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3319 spin_unlock_bh(&hw->phy_lock);
3320 }
c2681dd8
SH		 3321
3322 return 0;
baef58b1
SH		 3323}
3324
3325static const struct {
3326 u8 id;
3327 const char *name;
3328} skge_chips[] = {
3329 { CHIP_ID_GENESIS, "Genesis" },
3330 { CHIP_ID_YUKON, "Yukon" },
3331 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3332 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 3333};
3334
3335static const char *skge_board_name(const struct skge_hw *hw)
3336{
3337 int i;
3338 static char buf[16];
3339
3340 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3341 if (skge_chips[i].id == hw->chip_id)
3342 return skge_chips[i].name;
3343
3344 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3345 return buf;
3346}
3347
3348
3349/*
3350 * Setup the board data structure, but don't bring up
3351 * the port(s)
3352 */
3353static int skge_reset(struct skge_hw *hw)
3354{
adba9e23 3355 u32 reg;
b9d64acc 3356 u16 ctst, pci_status;
64f6b64d 3357 u8 t8, mac_cfg, pmd_type;
981d0377 3358 int i;
baef58b1
SH		 3359
3360 ctst = skge_read16(hw, B0_CTST);
3361
3362 /* do a SW reset */
3363 skge_write8(hw, B0_CTST, CS_RST_SET);
3364 skge_write8(hw, B0_CTST, CS_RST_CLR);
3365
3366 /* clear PCI errors, if any */
b9d64acc
SH		 3367 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3368 skge_write8(hw, B2_TST_CTRL2, 0);
baef58b1 3369
b9d64acc
SH		 3370 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3371 pci_write_config_word(hw->pdev, PCI_STATUS,
3372 pci_status | PCI_STATUS_ERROR_BITS);
3373 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
baef58b1
SH		 3374 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3375
3376 /* restore CLK_RUN bits (for Yukon-Lite) */
3377 skge_write16(hw, B0_CTST,
3378 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3379
3380 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
64f6b64d 3381 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
5e1705dd
SH		 3382 pmd_type = skge_read8(hw, B2_PMD_TYP);
3383 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3384
95566065 3385 switch (hw->chip_id) {
baef58b1 3386 case CHIP_ID_GENESIS:
64f6b64d
SH		 3387 switch (hw->phy_type) {
3388 case SK_PHY_XMAC:
3389 hw->phy_addr = PHY_ADDR_XMAC;
3390 break;
baef58b1
SH		 3391 case SK_PHY_BCOM:
3392 hw->phy_addr = PHY_ADDR_BCOM;
3393 break;
3394 default:
1479d13c
SH		 3395 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3396 hw->phy_type);
baef58b1
SH		 3397 return -EOPNOTSUPP;
3398 }
3399 break;
3400
3401 case CHIP_ID_YUKON:
3402 case CHIP_ID_YUKON_LITE:
3403 case CHIP_ID_YUKON_LP:
64f6b64d 3404 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
5e1705dd 3405 hw->copper = 1;
baef58b1
SH		 3406
3407 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3408 break;
3409
3410 default:
1479d13c
SH		 3411 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3412 hw->chip_id);
baef58b1
SH		 3413 return -EOPNOTSUPP;
3414 }
3415
981d0377
SH		 3416 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3417 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3418 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3419
3420 /* read the adapters RAM size */
3421 t8 = skge_read8(hw, B2_E_0);
3422 if (hw->chip_id == CHIP_ID_GENESIS) {
3423 if (t8 == 3) {
3424 /* special case: 4 x 64k x 36, offset = 0x80000 */
3425 hw->ram_size = 0x100000;
3426 hw->ram_offset = 0x80000;
3427 } else
3428 hw->ram_size = t8 * 512;
3429 }
3430 else if (t8 == 0)
3431 hw->ram_size = 0x20000;
3432 else
3433 hw->ram_size = t8 * 4096;
3434
4ebabfcb 3435 hw->intr_mask = IS_HW_ERR;
cfc3ed79 3436
4ebabfcb 3437 /* Use PHY IRQ for all but fiber based Genesis board */
64f6b64d
SH		 3438 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3439 hw->intr_mask |= IS_EXT_REG;
3440
baef58b1
SH		 3441 if (hw->chip_id == CHIP_ID_GENESIS)
3442 genesis_init(hw);
3443 else {
3444 /* switch power to VCC (WA for VAUX problem) */
3445 skge_write8(hw, B0_POWER_CTRL,
3446 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3447
050ec18a
SH		 3448 /* avoid boards with stuck Hardware error bits */
3449 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3450 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
1479d13c 3451 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
050ec18a
SH		 3452 hw->intr_mask &= ~IS_HW_ERR;
3453 }
3454
adba9e23
SH		 3455 /* Clear PHY COMA */
3456 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3457 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3458 reg &= ~PCI_PHY_COMA;
3459 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3460 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3461
3462
981d0377 3463 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3464 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3465 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3466 }
3467 }
3468
3469 /* turn off hardware timer (unused) */
3470 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3471 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3472 skge_write8(hw, B0_LED, LED_STAT_ON);
3473
3474 /* enable the Tx Arbiters */
981d0377 3475 for (i = 0; i < hw->ports; i++)
6b0c1480 3476 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3477
3478 /* Initialize ram interface */
3479 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3480
3481 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3482 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3483 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3484 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3485 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3486 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3487 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3488 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3489 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3490 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3491 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3492 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3493
3494 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3495
3496 /* Set interrupt moderation for Transmit only
3497 * Receive interrupts avoided by NAPI
3498 */
3499 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3500 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3501 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3502
baef58b1
SH		 3503 skge_write32(hw, B0_IMSK, hw->intr_mask);
3504
981d0377 3505 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3506 if (hw->chip_id == CHIP_ID_GENESIS)
3507 genesis_reset(hw, i);
3508 else
3509 yukon_reset(hw, i);
3510 }
baef58b1
SH		 3511
3512 return 0;
3513}
3514
3515/* Initialize network device */
981d0377
SH		 3516static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3517 int highmem)
baef58b1
SH		 3518{
3519 struct skge_port *skge;
3520 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3521
3522 if (!dev) {
1479d13c 3523 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
baef58b1
SH		 3524 return NULL;
3525 }
3526
3527 SET_MODULE_OWNER(dev);
3528 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3529 dev->open = skge_up;
3530 dev->stop = skge_down;
2cd8e5d3 3531 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3532 dev->hard_start_xmit = skge_xmit_frame;
3533 dev->get_stats = skge_get_stats;
3534 if (hw->chip_id == CHIP_ID_GENESIS)
3535 dev->set_multicast_list = genesis_set_multicast;
3536 else
3537 dev->set_multicast_list = yukon_set_multicast;
3538
3539 dev->set_mac_address = skge_set_mac_address;
3540 dev->change_mtu = skge_change_mtu;
3541 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3542 dev->tx_timeout = skge_tx_timeout;
3543 dev->watchdog_timeo = TX_WATCHDOG;
3544 dev->poll = skge_poll;
3545 dev->weight = NAPI_WEIGHT;
3546#ifdef CONFIG_NET_POLL_CONTROLLER
3547 dev->poll_controller = skge_netpoll;
3548#endif
3549 dev->irq = hw->pdev->irq;
513f533e 3550
981d0377
SH		 3551 if (highmem)
3552 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3553
3554 skge = netdev_priv(dev);
3555 skge->netdev = dev;
3556 skge->hw = hw;
3557 skge->msg_enable = netif_msg_init(debug, default_msg);
9cbe330f 3558
baef58b1
SH		 3559 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3560 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3561
3562 /* Auto speed and flow control */
3563 skge->autoneg = AUTONEG_ENABLE;
5d5c8e03 3564 skge->flow_control = FLOW_MODE_SYM_OR_REM;
baef58b1
SH		 3565 skge->duplex = -1;
3566 skge->speed = -1;
31b619c5 3567 skge->advertising = skge_supported_modes(hw);
a504e64a 3568 skge->wol = pci_wake_enabled(hw->pdev) ? wol_supported(hw) : 0;
baef58b1
SH		 3569
3570 hw->dev[port] = dev;
3571
3572 skge->port = port;
3573
64f6b64d 3574 /* Only used for Genesis XMAC */
9cbe330f 3575 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
64f6b64d 3576
baef58b1
SH		 3577 if (hw->chip_id != CHIP_ID_GENESIS) {
3578 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3579 skge->rx_csum = 1;
3580 }
3581
3582 /* read the mac address */
3583 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3584 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3585
3586 /* device is off until link detection */
3587 netif_carrier_off(dev);
3588 netif_stop_queue(dev);
3589
3590 return dev;
3591}
3592
3593static void __devinit skge_show_addr(struct net_device *dev)
3594{
3595 const struct skge_port *skge = netdev_priv(dev);
3596
3597 if (netif_msg_probe(skge))
3598 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3599 dev->name,
3600 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3601 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3602}
3603
3604static int __devinit skge_probe(struct pci_dev *pdev,
3605 const struct pci_device_id *ent)
3606{
3607 struct net_device *dev, *dev1;
3608 struct skge_hw *hw;
3609 int err, using_dac = 0;
3610
203babb6
SH		 3611 err = pci_enable_device(pdev);
3612 if (err) {
1479d13c 3613 dev_err(&pdev->dev, "cannot enable PCI device\n");
baef58b1
SH		 3614 goto err_out;
3615 }
3616
203babb6
SH		 3617 err = pci_request_regions(pdev, DRV_NAME);
3618 if (err) {
1479d13c 3619 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
baef58b1
SH		 3620 goto err_out_disable_pdev;
3621 }
3622
3623 pci_set_master(pdev);
3624
93aea718 3625 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
baef58b1 3626 using_dac = 1;
77783a78 3627 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
93aea718
SH		 3628 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3629 using_dac = 0;
3630 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3631 }
3632
3633 if (err) {
1479d13c 3634 dev_err(&pdev->dev, "no usable DMA configuration\n");
93aea718 3635 goto err_out_free_regions;
baef58b1
SH		 3636 }
3637
3638#ifdef __BIG_ENDIAN
8f3f8193 3639 /* byte swap descriptors in hardware */
baef58b1
SH		 3640 {
3641 u32 reg;
3642
3643 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3644 reg |= PCI_REV_DESC;
3645 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3646 }
3647#endif
3648
3649 err = -ENOMEM;
7e863061 3650 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1 3651 if (!hw) {
1479d13c 3652 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
baef58b1
SH		 3653 goto err_out_free_regions;
3654 }
3655
baef58b1 3656 hw->pdev = pdev;
d38efdd6 3657 spin_lock_init(&hw->hw_lock);
9cbe330f
SH		 3658 spin_lock_init(&hw->phy_lock);
3659 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
baef58b1
SH		 3660
3661 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3662 if (!hw->regs) {
1479d13c 3663 dev_err(&pdev->dev, "cannot map device registers\n");
baef58b1
SH		 3664 goto err_out_free_hw;
3665 }
3666
baef58b1
SH		 3667 err = skge_reset(hw);
3668 if (err)
ccdaa2a9 3669 goto err_out_iounmap;
baef58b1 3670
7c7459d1
GKH		 3671 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3672 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
981d0377 3673 skge_board_name(hw), hw->chip_rev);
baef58b1 3674
ccdaa2a9
SH		 3675 dev = skge_devinit(hw, 0, using_dac);
3676 if (!dev)
baef58b1
SH		 3677 goto err_out_led_off;
3678
fae87592 3679 /* Some motherboards are broken and has zero in ROM. */
1479d13c
SH		 3680 if (!is_valid_ether_addr(dev->dev_addr))
3681 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
631ae320 3682
203babb6
SH		 3683 err = register_netdev(dev);
3684 if (err) {
1479d13c 3685 dev_err(&pdev->dev, "cannot register net device\n");
baef58b1
SH		 3686 goto err_out_free_netdev;
3687 }
3688
ccdaa2a9
SH		 3689 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3690 if (err) {
1479d13c 3691 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
ccdaa2a9
SH		 3692 dev->name, pdev->irq);
3693 goto err_out_unregister;
3694 }
baef58b1
SH		 3695 skge_show_addr(dev);
3696
981d0377 3697 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3698 if (register_netdev(dev1) == 0)
3699 skge_show_addr(dev1);
3700 else {
3701 /* Failure to register second port need not be fatal */
1479d13c 3702 dev_warn(&pdev->dev, "register of second port failed\n");
baef58b1
SH		 3703 hw->dev[1] = NULL;
3704 free_netdev(dev1);
3705 }
3706 }
ccdaa2a9 3707 pci_set_drvdata(pdev, hw);
baef58b1
SH		 3708
3709 return 0;
3710
ccdaa2a9
SH		 3711err_out_unregister:
3712 unregister_netdev(dev);
baef58b1
SH		 3713err_out_free_netdev:
3714 free_netdev(dev);
3715err_out_led_off:
3716 skge_write16(hw, B0_LED, LED_STAT_OFF);
baef58b1
SH		 3717err_out_iounmap:
3718 iounmap(hw->regs);
3719err_out_free_hw:
3720 kfree(hw);
3721err_out_free_regions:
3722 pci_release_regions(pdev);
3723err_out_disable_pdev:
3724 pci_disable_device(pdev);
3725 pci_set_drvdata(pdev, NULL);
3726err_out:
3727 return err;
3728}
3729
3730static void __devexit skge_remove(struct pci_dev *pdev)
3731{
3732 struct skge_hw *hw = pci_get_drvdata(pdev);
3733 struct net_device *dev0, *dev1;
3734
95566065 3735 if (!hw)
baef58b1
SH		 3736 return;
3737
208491d8
SH		 3738 flush_scheduled_work();
3739
baef58b1
SH		 3740 if ((dev1 = hw->dev[1]))
3741 unregister_netdev(dev1);
3742 dev0 = hw->dev[0];
3743 unregister_netdev(dev0);
3744
9cbe330f
SH		 3745 tasklet_disable(&hw->phy_task);
3746
7c442fa1
SH		 3747 spin_lock_irq(&hw->hw_lock);
3748 hw->intr_mask = 0;
46a60f2d 3749 skge_write32(hw, B0_IMSK, 0);
78bc2186 3750 skge_read32(hw, B0_IMSK);
7c442fa1
SH		 3751 spin_unlock_irq(&hw->hw_lock);
3752
46a60f2d 3753 skge_write16(hw, B0_LED, LED_STAT_OFF);
46a60f2d
SH		 3754 skge_write8(hw, B0_CTST, CS_RST_SET);
3755
baef58b1
SH		 3756 free_irq(pdev->irq, hw);
3757 pci_release_regions(pdev);
3758 pci_disable_device(pdev);
3759 if (dev1)
3760 free_netdev(dev1);
3761 free_netdev(dev0);
46a60f2d 3762
baef58b1
SH		 3763 iounmap(hw->regs);
3764 kfree(hw);
3765 pci_set_drvdata(pdev, NULL);
3766}
3767
3768#ifdef CONFIG_PM
a504e64a
SH		 3769static int vaux_avail(struct pci_dev *pdev)
3770{
3771 int pm_cap;
3772
3773 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3774 if (pm_cap) {
3775 u16 ctl;
3776 pci_read_config_word(pdev, pm_cap + PCI_PM_PMC, &ctl);
3777 if (ctl & PCI_PM_CAP_AUX_POWER)
3778 return 1;
3779 }
3780 return 0;
3781}
3782
3783
2a569579 3784static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3785{
3786 struct skge_hw *hw = pci_get_drvdata(pdev);
a504e64a
SH		 3787 int i, err, wol = 0;
3788
3789 err = pci_save_state(pdev);
3790 if (err)
3791 return err;
baef58b1 3792
d38efdd6 3793 for (i = 0; i < hw->ports; i++) {
baef58b1 3794 struct net_device *dev = hw->dev[i];
a504e64a 3795 struct skge_port *skge = netdev_priv(dev);
baef58b1 3796
a504e64a
SH		 3797 if (netif_running(dev))
3798 skge_down(dev);
3799 if (skge->wol)
3800 skge_wol_init(skge);
d38efdd6 3801
a504e64a 3802 wol |= skge->wol;
baef58b1
SH		 3803 }
3804
a504e64a
SH		 3805 if (wol && vaux_avail(pdev))
3806 skge_write8(hw, B0_POWER_CTRL,
3807 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
3808
d38efdd6 3809 skge_write32(hw, B0_IMSK, 0);
2a569579 3810 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3811 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3812
3813 return 0;
3814}
3815
3816static int skge_resume(struct pci_dev *pdev)
3817{
3818 struct skge_hw *hw = pci_get_drvdata(pdev);
d38efdd6 3819 int i, err;
baef58b1 3820
a504e64a
SH		 3821 err = pci_set_power_state(pdev, PCI_D0);
3822 if (err)
3823 goto out;
3824
3825 err = pci_restore_state(pdev);
3826 if (err)
3827 goto out;
3828
baef58b1
SH		 3829 pci_enable_wake(pdev, PCI_D0, 0);
3830
d38efdd6
SH		 3831 err = skge_reset(hw);
3832 if (err)
3833 goto out;
baef58b1 3834
d38efdd6 3835 for (i = 0; i < hw->ports; i++) {
baef58b1 3836 struct net_device *dev = hw->dev[i];
d38efdd6 3837
d38efdd6
SH		 3838 if (netif_running(dev)) {
3839 err = skge_up(dev);
3840
3841 if (err) {
3842 printk(KERN_ERR PFX "%s: could not up: %d\n",
3843 dev->name, err);
edd702e8 3844 dev_close(dev);
d38efdd6
SH		 3845 goto out;
3846 }
baef58b1
SH		 3847 }
3848 }
d38efdd6
SH		 3849out:
3850 return err;
baef58b1
SH		 3851}
3852#endif
3853
3854static struct pci_driver skge_driver = {
3855 .name = DRV_NAME,
3856 .id_table = skge_id_table,
3857 .probe = skge_probe,
3858 .remove = __devexit_p(skge_remove),
3859#ifdef CONFIG_PM
3860 .suspend = skge_suspend,
3861 .resume = skge_resume,
3862#endif
3863};
3864
3865static int __init skge_init_module(void)
3866{
29917620 3867 return pci_register_driver(&skge_driver);
baef58b1
SH		 3868}
3869
3870static void __exit skge_cleanup_module(void)
3871{
3872 pci_unregister_driver(&skge_driver);
3873}
3874
3875module_init(skge_init_module);
3876module_exit(skge_cleanup_module);
Ubuntu Artful kernel mirror