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[PATCH] skge: handle Tx/Rx arbiter timeout
[mirror_ubuntu-artful-kernel.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
4075400b 39#include <linux/dma-mapping.h>
baef58b1
SH		 40#include <asm/irq.h>
41
42#include "skge.h"
43
44#define DRV_NAME "skge"
45#define DRV_VERSION "0.6"
46#define PFX DRV_NAME " "
47
48#define DEFAULT_TX_RING_SIZE 128
49#define DEFAULT_RX_RING_SIZE 512
50#define MAX_TX_RING_SIZE 1024
51#define MAX_RX_RING_SIZE 4096
52#define PHY_RETRIES 1000
53#define ETH_JUMBO_MTU 9000
54#define TX_WATCHDOG (5 * HZ)
55#define NAPI_WEIGHT 64
56#define BLINK_HZ (HZ/4)
baef58b1
SH		 57
58MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
59MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
60MODULE_LICENSE("GPL");
61MODULE_VERSION(DRV_VERSION);
62
63static const u32 default_msg
64 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
65 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
66
67static int debug = -1; /* defaults above */
68module_param(debug, int, 0);
69MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 72 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
73 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
74 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
75 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
76 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
77 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
78 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
79 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
80 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
81 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1032) },
82 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
baef58b1
SH		 83 { 0 }
84};
85MODULE_DEVICE_TABLE(pci, skge_id_table);
86
87static int skge_up(struct net_device *dev);
88static int skge_down(struct net_device *dev);
89static void skge_tx_clean(struct skge_port *skge);
6b0c1480
SH		 90static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
91static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 92static void genesis_get_stats(struct skge_port *skge, u64 *data);
93static void yukon_get_stats(struct skge_port *skge, u64 *data);
94static void yukon_init(struct skge_hw *hw, int port);
95static void yukon_reset(struct skge_hw *hw, int port);
96static void genesis_mac_init(struct skge_hw *hw, int port);
97static void genesis_reset(struct skge_hw *hw, int port);
45bada65 98static void genesis_link_up(struct skge_port *skge);
baef58b1 99
7e676d91 100/* Avoid conditionals by using array */
baef58b1
SH		 101static const int txqaddr[] = { Q_XA1, Q_XA2 };
102static const int rxqaddr[] = { Q_R1, Q_R2 };
103static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
104static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
7e676d91 105static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1
SH		 106
107/* Don't need to look at whole 16K.
108 * last interesting register is descriptor poll timer.
109 */
110#define SKGE_REGS_LEN (29*128)
111
112static int skge_get_regs_len(struct net_device *dev)
113{
114 return SKGE_REGS_LEN;
115}
116
117/*
118 * Returns copy of control register region
119 * I/O region is divided into banks and certain regions are unreadable
120 */
121static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
122 void *p)
123{
124 const struct skge_port *skge = netdev_priv(dev);
125 unsigned long offs;
126 const void __iomem *io = skge->hw->regs;
127 static const unsigned long bankmap
128 = (1<<0) | (1<<2) | (1<<8) | (1<<9)
129 | (1<<12) | (1<<13) | (1<<14) | (1<<15) | (1<<16)
130 | (1<<17) | (1<<20) | (1<<21) | (1<<22) | (1<<23)
131 | (1<<24) | (1<<25) | (1<<26) | (1<<27) | (1<<28);
132
133 regs->version = 1;
134 for (offs = 0; offs < regs->len; offs += 128) {
135 u32 len = min_t(u32, 128, regs->len - offs);
136
137 if (bankmap & (1<<(offs/128)))
138 memcpy_fromio(p + offs, io + offs, len);
139 else
140 memset(p + offs, 0, len);
141 }
142}
143
144/* Wake on Lan only supported on Yukon chps with rev 1 or above */
145static int wol_supported(const struct skge_hw *hw)
146{
147 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 148 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 149}
150
151static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
152{
153 struct skge_port *skge = netdev_priv(dev);
154
155 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
156 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
157}
158
159static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
160{
161 struct skge_port *skge = netdev_priv(dev);
162 struct skge_hw *hw = skge->hw;
163
95566065 164 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 165 return -EOPNOTSUPP;
166
167 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
168 return -EOPNOTSUPP;
169
170 skge->wol = wol->wolopts == WAKE_MAGIC;
171
172 if (skge->wol) {
173 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
174
175 skge_write16(hw, WOL_CTRL_STAT,
176 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
177 WOL_CTL_ENA_MAGIC_PKT_UNIT);
178 } else
179 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
180
181 return 0;
182}
183
31b619c5
SH		 184/* Determine supported/adverised modes based on hardware.
185 * Note: ethtoool ADVERTISED_xxx == SUPPORTED_xxx
186 */
187static u32 skge_supported_modes(const struct skge_hw *hw)
188{
189 u32 supported;
190
191 if (iscopper(hw)) {
192 supported = SUPPORTED_10baseT_Half
193 | SUPPORTED_10baseT_Full
194 | SUPPORTED_100baseT_Half
195 | SUPPORTED_100baseT_Full
196 | SUPPORTED_1000baseT_Half
197 | SUPPORTED_1000baseT_Full
198 | SUPPORTED_Autoneg| SUPPORTED_TP;
199
200 if (hw->chip_id == CHIP_ID_GENESIS)
201 supported &= ~(SUPPORTED_10baseT_Half
202 | SUPPORTED_10baseT_Full
203 | SUPPORTED_100baseT_Half
204 | SUPPORTED_100baseT_Full);
205
206 else if (hw->chip_id == CHIP_ID_YUKON)
207 supported &= ~SUPPORTED_1000baseT_Half;
208 } else
209 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
210 | SUPPORTED_Autoneg;
211
212 return supported;
213}
baef58b1
SH		 214
215static int skge_get_settings(struct net_device *dev,
216 struct ethtool_cmd *ecmd)
217{
218 struct skge_port *skge = netdev_priv(dev);
219 struct skge_hw *hw = skge->hw;
220
221 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 222 ecmd->supported = skge_supported_modes(hw);
baef58b1
SH		 223
224 if (iscopper(hw)) {
baef58b1
SH		 225 ecmd->port = PORT_TP;
226 ecmd->phy_address = hw->phy_addr;
31b619c5 227 } else
baef58b1 228 ecmd->port = PORT_FIBRE;
baef58b1
SH		 229
230 ecmd->advertising = skge->advertising;
231 ecmd->autoneg = skge->autoneg;
232 ecmd->speed = skge->speed;
233 ecmd->duplex = skge->duplex;
234 return 0;
235}
236
baef58b1
SH		 237static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
238{
239 struct skge_port *skge = netdev_priv(dev);
240 const struct skge_hw *hw = skge->hw;
31b619c5 241 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 242
243 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 244 ecmd->advertising = supported;
245 skge->duplex = -1;
246 skge->speed = -1;
baef58b1 247 } else {
31b619c5
SH		 248 u32 setting;
249
250 switch(ecmd->speed) {
baef58b1 251 case SPEED_1000:
31b619c5
SH		 252 if (ecmd->duplex == DUPLEX_FULL)
253 setting = SUPPORTED_1000baseT_Full;
254 else if (ecmd->duplex == DUPLEX_HALF)
255 setting = SUPPORTED_1000baseT_Half;
256 else
257 return -EINVAL;
baef58b1
SH		 258 break;
259 case SPEED_100:
31b619c5
SH		 260 if (ecmd->duplex == DUPLEX_FULL)
261 setting = SUPPORTED_100baseT_Full;
262 else if (ecmd->duplex == DUPLEX_HALF)
263 setting = SUPPORTED_100baseT_Half;
264 else
265 return -EINVAL;
266 break;
267
baef58b1 268 case SPEED_10:
31b619c5
SH		 269 if (ecmd->duplex == DUPLEX_FULL)
270 setting = SUPPORTED_10baseT_Full;
271 else if (ecmd->duplex == DUPLEX_HALF)
272 setting = SUPPORTED_10baseT_Half;
273 else
baef58b1
SH		 274 return -EINVAL;
275 break;
276 default:
277 return -EINVAL;
278 }
31b619c5
SH		 279
280 if ((setting & supported) == 0)
281 return -EINVAL;
282
283 skge->speed = ecmd->speed;
284 skge->duplex = ecmd->duplex;
baef58b1
SH		 285 }
286
287 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 288 skge->advertising = ecmd->advertising;
289
290 if (netif_running(dev)) {
291 skge_down(dev);
292 skge_up(dev);
293 }
294 return (0);
295}
296
297static void skge_get_drvinfo(struct net_device *dev,
298 struct ethtool_drvinfo *info)
299{
300 struct skge_port *skge = netdev_priv(dev);
301
302 strcpy(info->driver, DRV_NAME);
303 strcpy(info->version, DRV_VERSION);
304 strcpy(info->fw_version, "N/A");
305 strcpy(info->bus_info, pci_name(skge->hw->pdev));
306}
307
308static const struct skge_stat {
309 char name[ETH_GSTRING_LEN];
310 u16 xmac_offset;
311 u16 gma_offset;
312} skge_stats[] = {
313 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
314 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
315
316 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
317 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
318 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
319 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
320 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
321 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
322 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
323 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
324
325 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
326 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
327 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
328 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
329 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
330 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
331
332 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
333 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
334 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
335 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
336 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
337};
338
339static int skge_get_stats_count(struct net_device *dev)
340{
341 return ARRAY_SIZE(skge_stats);
342}
343
344static void skge_get_ethtool_stats(struct net_device *dev,
345 struct ethtool_stats *stats, u64 *data)
346{
347 struct skge_port *skge = netdev_priv(dev);
348
349 if (skge->hw->chip_id == CHIP_ID_GENESIS)
350 genesis_get_stats(skge, data);
351 else
352 yukon_get_stats(skge, data);
353}
354
355/* Use hardware MIB variables for critical path statistics and
356 * transmit feedback not reported at interrupt.
357 * Other errors are accounted for in interrupt handler.
358 */
359static struct net_device_stats *skge_get_stats(struct net_device *dev)
360{
361 struct skge_port *skge = netdev_priv(dev);
362 u64 data[ARRAY_SIZE(skge_stats)];
363
364 if (skge->hw->chip_id == CHIP_ID_GENESIS)
365 genesis_get_stats(skge, data);
366 else
367 yukon_get_stats(skge, data);
368
369 skge->net_stats.tx_bytes = data[0];
370 skge->net_stats.rx_bytes = data[1];
371 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
372 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
373 skge->net_stats.multicast = data[5] + data[7];
374 skge->net_stats.collisions = data[10];
375 skge->net_stats.tx_aborted_errors = data[12];
376
377 return &skge->net_stats;
378}
379
380static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
381{
382 int i;
383
95566065 384 switch (stringset) {
baef58b1
SH		 385 case ETH_SS_STATS:
386 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
387 memcpy(data + i * ETH_GSTRING_LEN,
388 skge_stats[i].name, ETH_GSTRING_LEN);
389 break;
390 }
391}
392
393static void skge_get_ring_param(struct net_device *dev,
394 struct ethtool_ringparam *p)
395{
396 struct skge_port *skge = netdev_priv(dev);
397
398 p->rx_max_pending = MAX_RX_RING_SIZE;
399 p->tx_max_pending = MAX_TX_RING_SIZE;
400 p->rx_mini_max_pending = 0;
401 p->rx_jumbo_max_pending = 0;
402
403 p->rx_pending = skge->rx_ring.count;
404 p->tx_pending = skge->tx_ring.count;
405 p->rx_mini_pending = 0;
406 p->rx_jumbo_pending = 0;
407}
408
409static int skge_set_ring_param(struct net_device *dev,
410 struct ethtool_ringparam *p)
411{
412 struct skge_port *skge = netdev_priv(dev);
413
414 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
415 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
416 return -EINVAL;
417
418 skge->rx_ring.count = p->rx_pending;
419 skge->tx_ring.count = p->tx_pending;
420
421 if (netif_running(dev)) {
422 skge_down(dev);
423 skge_up(dev);
424 }
425
426 return 0;
427}
428
429static u32 skge_get_msglevel(struct net_device *netdev)
430{
431 struct skge_port *skge = netdev_priv(netdev);
432 return skge->msg_enable;
433}
434
435static void skge_set_msglevel(struct net_device *netdev, u32 value)
436{
437 struct skge_port *skge = netdev_priv(netdev);
438 skge->msg_enable = value;
439}
440
441static int skge_nway_reset(struct net_device *dev)
442{
443 struct skge_port *skge = netdev_priv(dev);
444 struct skge_hw *hw = skge->hw;
445 int port = skge->port;
446
447 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
448 return -EINVAL;
449
450 spin_lock_bh(&hw->phy_lock);
451 if (hw->chip_id == CHIP_ID_GENESIS) {
452 genesis_reset(hw, port);
453 genesis_mac_init(hw, port);
454 } else {
455 yukon_reset(hw, port);
456 yukon_init(hw, port);
457 }
458 spin_unlock_bh(&hw->phy_lock);
459 return 0;
460}
461
462static int skge_set_sg(struct net_device *dev, u32 data)
463{
464 struct skge_port *skge = netdev_priv(dev);
465 struct skge_hw *hw = skge->hw;
466
467 if (hw->chip_id == CHIP_ID_GENESIS && data)
468 return -EOPNOTSUPP;
469 return ethtool_op_set_sg(dev, data);
470}
471
472static int skge_set_tx_csum(struct net_device *dev, u32 data)
473{
474 struct skge_port *skge = netdev_priv(dev);
475 struct skge_hw *hw = skge->hw;
476
477 if (hw->chip_id == CHIP_ID_GENESIS && data)
478 return -EOPNOTSUPP;
479
480 return ethtool_op_set_tx_csum(dev, data);
481}
482
483static u32 skge_get_rx_csum(struct net_device *dev)
484{
485 struct skge_port *skge = netdev_priv(dev);
486
487 return skge->rx_csum;
488}
489
490/* Only Yukon supports checksum offload. */
491static int skge_set_rx_csum(struct net_device *dev, u32 data)
492{
493 struct skge_port *skge = netdev_priv(dev);
494
495 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
496 return -EOPNOTSUPP;
497
498 skge->rx_csum = data;
499 return 0;
500}
501
baef58b1
SH		 502static void skge_get_pauseparam(struct net_device *dev,
503 struct ethtool_pauseparam *ecmd)
504{
505 struct skge_port *skge = netdev_priv(dev);
506
507 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
508 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
509 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
510 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
511
512 ecmd->autoneg = skge->autoneg;
513}
514
515static int skge_set_pauseparam(struct net_device *dev,
516 struct ethtool_pauseparam *ecmd)
517{
518 struct skge_port *skge = netdev_priv(dev);
519
520 skge->autoneg = ecmd->autoneg;
521 if (ecmd->rx_pause && ecmd->tx_pause)
522 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 523 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 524 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 525 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 526 skge->flow_control = FLOW_MODE_LOC_SEND;
527 else
528 skge->flow_control = FLOW_MODE_NONE;
529
530 if (netif_running(dev)) {
531 skge_down(dev);
532 skge_up(dev);
533 }
534 return 0;
535}
536
537/* Chip internal frequency for clock calculations */
538static inline u32 hwkhz(const struct skge_hw *hw)
539{
540 if (hw->chip_id == CHIP_ID_GENESIS)
541 return 53215; /* or: 53.125 MHz */
baef58b1
SH		 542 else
543 return 78215; /* or: 78.125 MHz */
544}
545
546/* Chip hz to microseconds */
547static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
548{
549 return (ticks * 1000) / hwkhz(hw);
550}
551
552/* Microseconds to chip hz */
553static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
554{
555 return hwkhz(hw) * usec / 1000;
556}
557
558static int skge_get_coalesce(struct net_device *dev,
559 struct ethtool_coalesce *ecmd)
560{
561 struct skge_port *skge = netdev_priv(dev);
562 struct skge_hw *hw = skge->hw;
563 int port = skge->port;
564
565 ecmd->rx_coalesce_usecs = 0;
566 ecmd->tx_coalesce_usecs = 0;
567
568 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
569 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
570 u32 msk = skge_read32(hw, B2_IRQM_MSK);
571
572 if (msk & rxirqmask[port])
573 ecmd->rx_coalesce_usecs = delay;
574 if (msk & txirqmask[port])
575 ecmd->tx_coalesce_usecs = delay;
576 }
577
578 return 0;
579}
580
581/* Note: interrupt timer is per board, but can turn on/off per port */
582static int skge_set_coalesce(struct net_device *dev,
583 struct ethtool_coalesce *ecmd)
584{
585 struct skge_port *skge = netdev_priv(dev);
586 struct skge_hw *hw = skge->hw;
587 int port = skge->port;
588 u32 msk = skge_read32(hw, B2_IRQM_MSK);
589 u32 delay = 25;
590
591 if (ecmd->rx_coalesce_usecs == 0)
592 msk &= ~rxirqmask[port];
593 else if (ecmd->rx_coalesce_usecs < 25 ||
594 ecmd->rx_coalesce_usecs > 33333)
595 return -EINVAL;
596 else {
597 msk |= rxirqmask[port];
598 delay = ecmd->rx_coalesce_usecs;
599 }
600
601 if (ecmd->tx_coalesce_usecs == 0)
602 msk &= ~txirqmask[port];
603 else if (ecmd->tx_coalesce_usecs < 25 ||
604 ecmd->tx_coalesce_usecs > 33333)
605 return -EINVAL;
606 else {
607 msk |= txirqmask[port];
608 delay = min(delay, ecmd->rx_coalesce_usecs);
609 }
610
611 skge_write32(hw, B2_IRQM_MSK, msk);
612 if (msk == 0)
613 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
614 else {
615 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
616 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
617 }
618 return 0;
619}
620
621static void skge_led_on(struct skge_hw *hw, int port)
622{
623 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 624 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
baef58b1
SH		 625 skge_write8(hw, B0_LED, LED_STAT_ON);
626
6b0c1480
SH		 627 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
628 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
629 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 630
89bf5f23
SH		 631 /* For Broadcom Phy only */
632 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
baef58b1 633 } else {
6b0c1480
SH		 634 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
635 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 636 PHY_M_LED_MO_DUP(MO_LED_ON) |
637 PHY_M_LED_MO_10(MO_LED_ON) |
638 PHY_M_LED_MO_100(MO_LED_ON) |
639 PHY_M_LED_MO_1000(MO_LED_ON) |
640 PHY_M_LED_MO_RX(MO_LED_ON));
641 }
642}
643
644static void skge_led_off(struct skge_hw *hw, int port)
645{
646 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480 647 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
baef58b1
SH		 648 skge_write8(hw, B0_LED, LED_STAT_OFF);
649
6b0c1480
SH		 650 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
651 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
baef58b1 652
89bf5f23
SH		 653 /* Broadcom only */
654 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
baef58b1 655 } else {
6b0c1480
SH		 656 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
657 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
baef58b1
SH		 658 PHY_M_LED_MO_DUP(MO_LED_OFF) |
659 PHY_M_LED_MO_10(MO_LED_OFF) |
660 PHY_M_LED_MO_100(MO_LED_OFF) |
661 PHY_M_LED_MO_1000(MO_LED_OFF) |
662 PHY_M_LED_MO_RX(MO_LED_OFF));
663 }
664}
665
666static void skge_blink_timer(unsigned long data)
667{
668 struct skge_port *skge = (struct skge_port *) data;
669 struct skge_hw *hw = skge->hw;
670 unsigned long flags;
671
672 spin_lock_irqsave(&hw->phy_lock, flags);
673 if (skge->blink_on)
674 skge_led_on(hw, skge->port);
675 else
676 skge_led_off(hw, skge->port);
677 spin_unlock_irqrestore(&hw->phy_lock, flags);
678
679 skge->blink_on = !skge->blink_on;
680 mod_timer(&skge->led_blink, jiffies + BLINK_HZ);
681}
682
683/* blink LED's for finding board */
684static int skge_phys_id(struct net_device *dev, u32 data)
685{
686 struct skge_port *skge = netdev_priv(dev);
687
95566065 688 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
baef58b1
SH		 689 data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
690
691 /* start blinking */
692 skge->blink_on = 1;
693 mod_timer(&skge->led_blink, jiffies+1);
694
695 msleep_interruptible(data * 1000);
696 del_timer_sync(&skge->led_blink);
697
698 skge_led_off(skge->hw, skge->port);
699
700 return 0;
701}
702
703static struct ethtool_ops skge_ethtool_ops = {
704 .get_settings = skge_get_settings,
705 .set_settings = skge_set_settings,
706 .get_drvinfo = skge_get_drvinfo,
707 .get_regs_len = skge_get_regs_len,
708 .get_regs = skge_get_regs,
709 .get_wol = skge_get_wol,
710 .set_wol = skge_set_wol,
711 .get_msglevel = skge_get_msglevel,
712 .set_msglevel = skge_set_msglevel,
713 .nway_reset = skge_nway_reset,
714 .get_link = ethtool_op_get_link,
715 .get_ringparam = skge_get_ring_param,
716 .set_ringparam = skge_set_ring_param,
717 .get_pauseparam = skge_get_pauseparam,
718 .set_pauseparam = skge_set_pauseparam,
719 .get_coalesce = skge_get_coalesce,
720 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 721 .get_sg = ethtool_op_get_sg,
722 .set_sg = skge_set_sg,
723 .get_tx_csum = ethtool_op_get_tx_csum,
724 .set_tx_csum = skge_set_tx_csum,
725 .get_rx_csum = skge_get_rx_csum,
726 .set_rx_csum = skge_set_rx_csum,
727 .get_strings = skge_get_strings,
728 .phys_id = skge_phys_id,
729 .get_stats_count = skge_get_stats_count,
730 .get_ethtool_stats = skge_get_ethtool_stats,
731};
732
733/*
734 * Allocate ring elements and chain them together
735 * One-to-one association of board descriptors with ring elements
736 */
737static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
738{
739 struct skge_tx_desc *d;
740 struct skge_element *e;
741 int i;
742
743 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
744 if (!ring->start)
745 return -ENOMEM;
746
747 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
748 e->desc = d;
749 if (i == ring->count - 1) {
750 e->next = ring->start;
751 d->next_offset = base;
752 } else {
753 e->next = e + 1;
754 d->next_offset = base + (i+1) * sizeof(*d);
755 }
756 }
757 ring->to_use = ring->to_clean = ring->start;
758
759 return 0;
760}
761
762/* Setup buffer for receiving */
763static inline int skge_rx_alloc(struct skge_port *skge,
764 struct skge_element *e)
765{
766 unsigned long bufsize = skge->netdev->mtu + ETH_HLEN; /* VLAN? */
767 struct skge_rx_desc *rd = e->desc;
768 struct sk_buff *skb;
769 u64 map;
770
771 skb = dev_alloc_skb(bufsize + NET_IP_ALIGN);
772 if (unlikely(!skb)) {
773 printk(KERN_DEBUG PFX "%s: out of memory for receive\n",
774 skge->netdev->name);
775 return -ENOMEM;
776 }
777
778 skb->dev = skge->netdev;
779 skb_reserve(skb, NET_IP_ALIGN);
780
781 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
782 PCI_DMA_FROMDEVICE);
783
784 rd->dma_lo = map;
785 rd->dma_hi = map >> 32;
786 e->skb = skb;
787 rd->csum1_start = ETH_HLEN;
788 rd->csum2_start = ETH_HLEN;
789 rd->csum1 = 0;
790 rd->csum2 = 0;
791
792 wmb();
793
794 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
795 pci_unmap_addr_set(e, mapaddr, map);
796 pci_unmap_len_set(e, maplen, bufsize);
797 return 0;
798}
799
800/* Free all unused buffers in receive ring, assumes receiver stopped */
801static void skge_rx_clean(struct skge_port *skge)
802{
803 struct skge_hw *hw = skge->hw;
804 struct skge_ring *ring = &skge->rx_ring;
805 struct skge_element *e;
806
807 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
808 struct skge_rx_desc *rd = e->desc;
809 rd->control = 0;
810
811 pci_unmap_single(hw->pdev,
812 pci_unmap_addr(e, mapaddr),
813 pci_unmap_len(e, maplen),
814 PCI_DMA_FROMDEVICE);
815 dev_kfree_skb(e->skb);
816 e->skb = NULL;
817 }
818 ring->to_clean = e;
819}
820
821/* Allocate buffers for receive ring
822 * For receive: to_use is refill location
823 * to_clean is next received frame.
824 *
825 * if (to_use == to_clean)
826 * then ring all frames in ring need buffers
827 * if (to_use->next == to_clean)
828 * then ring all frames in ring have buffers
829 */
830static int skge_rx_fill(struct skge_port *skge)
831{
832 struct skge_ring *ring = &skge->rx_ring;
833 struct skge_element *e;
834 int ret = 0;
835
836 for (e = ring->to_use; e->next != ring->to_clean; e = e->next) {
837 if (skge_rx_alloc(skge, e)) {
838 ret = 1;
839 break;
840 }
841
842 }
843 ring->to_use = e;
844
845 return ret;
846}
847
848static void skge_link_up(struct skge_port *skge)
849{
850 netif_carrier_on(skge->netdev);
851 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
852 netif_wake_queue(skge->netdev);
853
854 if (netif_msg_link(skge))
855 printk(KERN_INFO PFX
856 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
857 skge->netdev->name, skge->speed,
858 skge->duplex == DUPLEX_FULL ? "full" : "half",
859 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
860 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
861 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
862 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
863 "unknown");
864}
865
866static void skge_link_down(struct skge_port *skge)
867{
868 netif_carrier_off(skge->netdev);
869 netif_stop_queue(skge->netdev);
870
871 if (netif_msg_link(skge))
872 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
873}
874
6b0c1480 875static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 876{
877 int i;
878 u16 v;
879
6b0c1480
SH		 880 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
881 v = xm_read16(hw, port, XM_PHY_DATA);
baef58b1 882
89bf5f23
SH		 883 /* Need to wait for external PHY */
884 for (i = 0; i < PHY_RETRIES; i++) {
885 udelay(1);
886 if (xm_read16(hw, port, XM_MMU_CMD)
887 & XM_MMU_PHY_RDY)
888 goto ready;
baef58b1
SH		 889 }
890
89bf5f23
SH		 891 printk(KERN_WARNING PFX "%s: phy read timed out\n",
892 hw->dev[port]->name);
893 return 0;
894 ready:
895 v = xm_read16(hw, port, XM_PHY_DATA);
896
baef58b1
SH		 897 return v;
898}
899
6b0c1480 900static void xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 901{
902 int i;
903
6b0c1480 904 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 905 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 906 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 907 goto ready;
89bf5f23 908 udelay(1);
baef58b1
SH		 909 }
910 printk(KERN_WARNING PFX "%s: phy write failed to come ready\n",
911 hw->dev[port]->name);
912
913
914 ready:
6b0c1480 915 xm_write16(hw, port, XM_PHY_DATA, val);
baef58b1
SH		 916 for (i = 0; i < PHY_RETRIES; i++) {
917 udelay(1);
6b0c1480 918 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1
SH		 919 return;
920 }
921 printk(KERN_WARNING PFX "%s: phy write timed out\n",
922 hw->dev[port]->name);
923}
924
925static void genesis_init(struct skge_hw *hw)
926{
927 /* set blink source counter */
928 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
929 skge_write8(hw, B2_BSC_CTRL, BSC_START);
930
931 /* configure mac arbiter */
932 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
933
934 /* configure mac arbiter timeout values */
935 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
936 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
937 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
938 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
939
940 skge_write8(hw, B3_MA_RCINI_RX1, 0);
941 skge_write8(hw, B3_MA_RCINI_RX2, 0);
942 skge_write8(hw, B3_MA_RCINI_TX1, 0);
943 skge_write8(hw, B3_MA_RCINI_TX2, 0);
944
945 /* configure packet arbiter timeout */
946 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
947 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
948 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
949 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
950 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
951}
952
953static void genesis_reset(struct skge_hw *hw, int port)
954{
45bada65 955 const u8 zero[8] = { 0 };
baef58b1
SH		 956
957 /* reset the statistics module */
6b0c1480
SH		 958 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
959 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
960 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
961 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
962 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 963
89bf5f23
SH		 964 /* disable Broadcom PHY IRQ */
965 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 966
45bada65 967 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 968}
969
970
45bada65
SH		 971/* Convert mode to MII values */
972static const u16 phy_pause_map[] = {
973 [FLOW_MODE_NONE] = 0,
974 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
975 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
976 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
977};
978
979
980/* Check status of Broadcom phy link */
981static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 982{
45bada65
SH		 983 struct net_device *dev = hw->dev[port];
984 struct skge_port *skge = netdev_priv(dev);
985 u16 status;
986
987 /* read twice because of latch */
988 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
989 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
990
991 pr_debug("bcom_check_link status=0x%x\n", status);
992
993 if ((status & PHY_ST_LSYNC) == 0) {
994 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
995 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
996 xm_write16(hw, port, XM_MMU_CMD, cmd);
997 /* dummy read to ensure writing */
998 (void) xm_read16(hw, port, XM_MMU_CMD);
999
1000 if (netif_carrier_ok(dev))
1001 skge_link_down(skge);
1002 } else {
1003 if (skge->autoneg == AUTONEG_ENABLE &&
1004 (status & PHY_ST_AN_OVER)) {
1005 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1006 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1007
1008 if (lpa & PHY_B_AN_RF) {
1009 printk(KERN_NOTICE PFX "%s: remote fault\n",
1010 dev->name);
1011 return;
1012 }
1013
1014 /* Check Duplex mismatch */
1015 switch(aux & PHY_B_AS_AN_RES_MSK) {
1016 case PHY_B_RES_1000FD:
1017 skge->duplex = DUPLEX_FULL;
1018 break;
1019 case PHY_B_RES_1000HD:
1020 skge->duplex = DUPLEX_HALF;
1021 break;
1022 default:
1023 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1024 dev->name);
1025 return;
1026 }
1027
1028
1029 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1030 switch (aux & PHY_B_AS_PAUSE_MSK) {
1031 case PHY_B_AS_PAUSE_MSK:
1032 skge->flow_control = FLOW_MODE_SYMMETRIC;
1033 break;
1034 case PHY_B_AS_PRR:
1035 skge->flow_control = FLOW_MODE_REM_SEND;
1036 break;
1037 case PHY_B_AS_PRT:
1038 skge->flow_control = FLOW_MODE_LOC_SEND;
1039 break;
1040 default:
1041 skge->flow_control = FLOW_MODE_NONE;
1042 }
1043
1044 skge->speed = SPEED_1000;
1045 }
1046
1047 if (!netif_carrier_ok(dev))
1048 genesis_link_up(skge);
1049 }
1050}
1051
1052/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1053 * Phy on for 100 or 10Mbit operation
1054 */
1055static void bcom_phy_init(struct skge_port *skge, int jumbo)
1056{
1057 struct skge_hw *hw = skge->hw;
1058 int port = skge->port;
baef58b1 1059 int i;
45bada65 1060 u16 id1, r, ext, ctl;
baef58b1
SH		 1061
1062 /* magic workaround patterns for Broadcom */
1063 static const struct {
1064 u16 reg;
1065 u16 val;
1066 } A1hack[] = {
1067 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1068 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1069 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1070 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1071 }, C0hack[] = {
1072 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1073 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1074 };
1075
45bada65
SH		 1076 pr_debug("bcom_phy_init\n");
1077
1078 /* read Id from external PHY (all have the same address) */
1079 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1080
1081 /* Optimize MDIO transfer by suppressing preamble. */
1082 r = xm_read16(hw, port, XM_MMU_CMD);
1083 r |= XM_MMU_NO_PRE;
1084 xm_write16(hw, port, XM_MMU_CMD,r);
1085
1086 switch(id1) {
1087 case PHY_BCOM_ID1_C0:
1088 /*
1089 * Workaround BCOM Errata for the C0 type.
1090 * Write magic patterns to reserved registers.
1091 */
1092 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1093 xm_phy_write(hw, port,
1094 C0hack[i].reg, C0hack[i].val);
1095
1096 break;
1097 case PHY_BCOM_ID1_A1:
1098 /*
1099 * Workaround BCOM Errata for the A1 type.
1100 * Write magic patterns to reserved registers.
1101 */
1102 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1103 xm_phy_write(hw, port,
1104 A1hack[i].reg, A1hack[i].val);
1105 break;
1106 }
1107
1108 /*
1109 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1110 * Disable Power Management after reset.
1111 */
1112 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1113 r |= PHY_B_AC_DIS_PM;
1114 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1115
1116 /* Dummy read */
1117 xm_read16(hw, port, XM_ISRC);
1118
1119 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1120 ctl = PHY_CT_SP1000; /* always 1000mbit */
1121
1122 if (skge->autoneg == AUTONEG_ENABLE) {
1123 /*
1124 * Workaround BCOM Errata #1 for the C5 type.
1125 * 1000Base-T Link Acquisition Failure in Slave Mode
1126 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1127 */
1128 u16 adv = PHY_B_1000C_RD;
1129 if (skge->advertising & ADVERTISED_1000baseT_Half)
1130 adv |= PHY_B_1000C_AHD;
1131 if (skge->advertising & ADVERTISED_1000baseT_Full)
1132 adv |= PHY_B_1000C_AFD;
1133 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1134
1135 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1136 } else {
1137 if (skge->duplex == DUPLEX_FULL)
1138 ctl |= PHY_CT_DUP_MD;
1139 /* Force to slave */
1140 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1141 }
1142
1143 /* Set autonegotiation pause parameters */
1144 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1145 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1146
1147 /* Handle Jumbo frames */
1148 if (jumbo) {
1149 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1150 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1151
1152 ext |= PHY_B_PEC_HIGH_LA;
1153
1154 }
1155
1156 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1157 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1158
1159 /* Use link status change interrrupt */
1160 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1161
1162 bcom_check_link(hw, port);
1163}
1164
1165static void genesis_mac_init(struct skge_hw *hw, int port)
1166{
1167 struct net_device *dev = hw->dev[port];
1168 struct skge_port *skge = netdev_priv(dev);
1169 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1170 int i;
1171 u32 r;
1172 const u8 zero[6] = { 0 };
1173
1174 /* Clear MIB counters */
1175 xm_write16(hw, port, XM_STAT_CMD,
1176 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1177 /* Clear two times according to Errata #3 */
1178 xm_write16(hw, port, XM_STAT_CMD,
1179 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
baef58b1
SH		 1180
1181 /* initialize Rx, Tx and Link LED */
6b0c1480
SH		 1182 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
1183 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 1184
6b0c1480
SH		 1185 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
1186 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1
SH		 1187
1188 /* Unreset the XMAC. */
6b0c1480 1189 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1190
1191 /*
1192 * Perform additional initialization for external PHYs,
1193 * namely for the 1000baseTX cards that use the XMAC's
1194 * GMII mode.
1195 */
1196 spin_lock_bh(&hw->phy_lock);
45bada65 1197 /* Take external Phy out of reset */
89bf5f23
SH		 1198 r = skge_read32(hw, B2_GP_IO);
1199 if (port == 0)
1200 r |= GP_DIR_0|GP_IO_0;
1201 else
1202 r |= GP_DIR_2|GP_IO_2;
1203
1204 skge_write32(hw, B2_GP_IO, r);
1205 skge_read32(hw, B2_GP_IO);
45bada65 1206 spin_unlock_bh(&hw->phy_lock);
89bf5f23 1207
45bada65 1208 /* Enable GMII interfac */
89bf5f23
SH		 1209 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1210
45bada65 1211 bcom_phy_init(skge, jumbo);
89bf5f23 1212
45bada65
SH		 1213 /* Set Station Address */
1214 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1215
45bada65
SH		 1216 /* We don't use match addresses so clear */
1217 for (i = 1; i < 16; i++)
1218 xm_outaddr(hw, port, XM_EXM(i), zero);
1219
1220 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1221 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1222
1223 /* We don't need the FCS appended to the packet. */
1224 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1225 if (jumbo)
1226 r |= XM_RX_BIG_PK_OK;
89bf5f23 1227
45bada65 1228 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1229 /*
45bada65
SH		 1230 * If in manual half duplex mode the other side might be in
1231 * full duplex mode, so ignore if a carrier extension is not seen
1232 * on frames received
89bf5f23 1233 */
45bada65 1234 r |= XM_RX_DIS_CEXT;
baef58b1 1235 }
45bada65 1236 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1237
baef58b1
SH		 1238
1239 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1240 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1241
1242 /*
1243 * Bump up the transmit threshold. This helps hold off transmit
1244 * underruns when we're blasting traffic from both ports at once.
1245 */
1246 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1247
1248 /*
1249 * Enable the reception of all error frames. This is is
1250 * a necessary evil due to the design of the XMAC. The
1251 * XMAC's receive FIFO is only 8K in size, however jumbo
1252 * frames can be up to 9000 bytes in length. When bad
1253 * frame filtering is enabled, the XMAC's RX FIFO operates
1254 * in 'store and forward' mode. For this to work, the
1255 * entire frame has to fit into the FIFO, but that means
1256 * that jumbo frames larger than 8192 bytes will be
1257 * truncated. Disabling all bad frame filtering causes
1258 * the RX FIFO to operate in streaming mode, in which
1259 * case the XMAC will start transfering frames out of the
1260 * RX FIFO as soon as the FIFO threshold is reached.
1261 */
45bada65 1262 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1263
baef58b1
SH		 1264
1265 /*
45bada65
SH		 1266 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1267 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1268 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1269 */
45bada65
SH		 1270 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1271
1272 /*
1273 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1274 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1275 * and 'Octets Tx OK Hi Cnt Ov'.
1276 */
1277 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1278
1279 /* Configure MAC arbiter */
1280 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1281
1282 /* configure timeout values */
1283 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1284 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1285 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1286 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1287
1288 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1289 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1290 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1291 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1292
1293 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1294 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1295 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1296 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1297
1298 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1299 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1300 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1301 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1302
45bada65 1303 if (jumbo) {
baef58b1 1304 /* Enable frame flushing if jumbo frames used */
6b0c1480 1305 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1306 } else {
1307 /* enable timeout timers if normal frames */
1308 skge_write16(hw, B3_PA_CTRL,
45bada65 1309 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1310 }
baef58b1
SH		 1311}
1312
1313static void genesis_stop(struct skge_port *skge)
1314{
1315 struct skge_hw *hw = skge->hw;
1316 int port = skge->port;
89bf5f23 1317 u32 reg;
baef58b1
SH		 1318
1319 /* Clear Tx packet arbiter timeout IRQ */
1320 skge_write16(hw, B3_PA_CTRL,
1321 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1322
1323 /*
1324 * If the transfer stucks at the MAC the STOP command will not
1325 * terminate if we don't flush the XMAC's transmit FIFO !
1326 */
6b0c1480
SH		 1327 xm_write32(hw, port, XM_MODE,
1328 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1329
1330
1331 /* Reset the MAC */
6b0c1480 1332 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1333
1334 /* For external PHYs there must be special handling */
89bf5f23
SH		 1335 reg = skge_read32(hw, B2_GP_IO);
1336 if (port == 0) {
1337 reg |= GP_DIR_0;
1338 reg &= ~GP_IO_0;
1339 } else {
1340 reg |= GP_DIR_2;
1341 reg &= ~GP_IO_2;
baef58b1 1342 }
89bf5f23
SH		 1343 skge_write32(hw, B2_GP_IO, reg);
1344 skge_read32(hw, B2_GP_IO);
baef58b1 1345
6b0c1480
SH		 1346 xm_write16(hw, port, XM_MMU_CMD,
1347 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1348 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1349
6b0c1480 1350 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1351}
1352
1353
1354static void genesis_get_stats(struct skge_port *skge, u64 *data)
1355{
1356 struct skge_hw *hw = skge->hw;
1357 int port = skge->port;
1358 int i;
1359 unsigned long timeout = jiffies + HZ;
1360
6b0c1480 1361 xm_write16(hw, port,
baef58b1
SH		 1362 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1363
1364 /* wait for update to complete */
6b0c1480 1365 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1366 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1367 if (time_after(jiffies, timeout))
1368 break;
1369 udelay(10);
1370 }
1371
1372 /* special case for 64 bit octet counter */
6b0c1480
SH		 1373 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1374 | xm_read32(hw, port, XM_TXO_OK_LO);
1375 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1376 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1377
1378 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1379 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1380}
1381
1382static void genesis_mac_intr(struct skge_hw *hw, int port)
1383{
1384 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1385 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1386
7e676d91
SH		 1387 if (netif_msg_intr(skge))
1388 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1389 skge->netdev->name, status);
baef58b1
SH		 1390
1391 if (status & XM_IS_TXF_UR) {
6b0c1480 1392 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1393 ++skge->net_stats.tx_fifo_errors;
1394 }
1395 if (status & XM_IS_RXF_OV) {
6b0c1480 1396 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1397 ++skge->net_stats.rx_fifo_errors;
1398 }
1399}
1400
6b0c1480 1401static void gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 1402{
1403 int i;
1404
6b0c1480
SH		 1405 gma_write16(hw, port, GM_SMI_DATA, val);
1406 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1407 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1408 for (i = 0; i < PHY_RETRIES; i++) {
1409 udelay(1);
1410
6b0c1480 1411 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
baef58b1
SH		 1412 break;
1413 }
1414}
1415
6b0c1480 1416static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
baef58b1
SH		 1417{
1418 int i;
1419
6b0c1480 1420 gma_write16(hw, port, GM_SMI_CTRL,
baef58b1
SH		 1421 GM_SMI_CT_PHY_AD(hw->phy_addr)
1422 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1423
1424 for (i = 0; i < PHY_RETRIES; i++) {
1425 udelay(1);
6b0c1480 1426 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
baef58b1
SH		 1427 goto ready;
1428 }
1429
1430 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1431 hw->dev[port]->name);
1432 return 0;
1433 ready:
6b0c1480 1434 return gma_read16(hw, port, GM_SMI_DATA);
baef58b1
SH		 1435}
1436
baef58b1
SH		 1437static void genesis_link_up(struct skge_port *skge)
1438{
1439 struct skge_hw *hw = skge->hw;
1440 int port = skge->port;
1441 u16 cmd;
1442 u32 mode, msk;
1443
1444 pr_debug("genesis_link_up\n");
6b0c1480 1445 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1446
1447 /*
1448 * enabling pause frame reception is required for 1000BT
1449 * because the XMAC is not reset if the link is going down
1450 */
1451 if (skge->flow_control == FLOW_MODE_NONE ||
1452 skge->flow_control == FLOW_MODE_LOC_SEND)
7e676d91 1453 /* Disable Pause Frame Reception */
baef58b1
SH		 1454 cmd |= XM_MMU_IGN_PF;
1455 else
1456 /* Enable Pause Frame Reception */
1457 cmd &= ~XM_MMU_IGN_PF;
1458
6b0c1480 1459 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1460
6b0c1480 1461 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1462 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1463 skge->flow_control == FLOW_MODE_LOC_SEND) {
1464 /*
1465 * Configure Pause Frame Generation
1466 * Use internal and external Pause Frame Generation.
1467 * Sending pause frames is edge triggered.
1468 * Send a Pause frame with the maximum pause time if
1469 * internal oder external FIFO full condition occurs.
1470 * Send a zero pause time frame to re-start transmission.
1471 */
1472 /* XM_PAUSE_DA = '010000C28001' (default) */
1473 /* XM_MAC_PTIME = 0xffff (maximum) */
1474 /* remember this value is defined in big endian (!) */
6b0c1480 1475 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1476
1477 mode |= XM_PAUSE_MODE;
6b0c1480 1478 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1479 } else {
1480 /*
1481 * disable pause frame generation is required for 1000BT
1482 * because the XMAC is not reset if the link is going down
1483 */
1484 /* Disable Pause Mode in Mode Register */
1485 mode &= ~XM_PAUSE_MODE;
1486
6b0c1480 1487 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1488 }
1489
6b0c1480 1490 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1491
1492 msk = XM_DEF_MSK;
89bf5f23
SH		 1493 /* disable GP0 interrupt bit for external Phy */
1494 msk |= XM_IS_INP_ASS;
baef58b1 1495
6b0c1480
SH		 1496 xm_write16(hw, port, XM_IMSK, msk);
1497 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1498
1499 /* get MMU Command Reg. */
6b0c1480 1500 cmd = xm_read16(hw, port, XM_MMU_CMD);
89bf5f23 1501 if (skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1502 cmd |= XM_MMU_GMII_FD;
1503
89bf5f23
SH		 1504 /*
1505 * Workaround BCOM Errata (#10523) for all BCom Phys
1506 * Enable Power Management after link up
1507 */
1508 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1509 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1510 & ~PHY_B_AC_DIS_PM);
1511 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
baef58b1
SH		 1512
1513 /* enable Rx/Tx */
6b0c1480 1514 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1515 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1516 skge_link_up(skge);
1517}
1518
1519
45bada65 1520static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1521{
1522 struct skge_hw *hw = skge->hw;
1523 int port = skge->port;
45bada65
SH		 1524 u16 isrc;
1525
1526 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1527 if (netif_msg_intr(skge))
1528 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1529 skge->netdev->name, isrc);
baef58b1 1530
45bada65
SH		 1531 if (isrc & PHY_B_IS_PSE)
1532 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1533 hw->dev[port]->name);
baef58b1
SH		 1534
1535 /* Workaround BCom Errata:
1536 * enable and disable loopback mode if "NO HCD" occurs.
1537 */
45bada65 1538 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1539 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1540 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1541 ctrl | PHY_CT_LOOP);
6b0c1480 1542 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1543 ctrl & ~PHY_CT_LOOP);
1544 }
1545
45bada65
SH		 1546 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1547 bcom_check_link(hw, port);
baef58b1 1548
baef58b1
SH		 1549}
1550
1551/* Marvell Phy Initailization */
1552static void yukon_init(struct skge_hw *hw, int port)
1553{
1554 struct skge_port *skge = netdev_priv(hw->dev[port]);
1555 u16 ctrl, ct1000, adv;
1556 u16 ledctrl, ledover;
1557
1558 pr_debug("yukon_init\n");
1559 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1560 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1561
1562 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1563 PHY_M_EC_MAC_S_MSK);
1564 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1565
c506a509 1566 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1567
6b0c1480 1568 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1569 }
1570
6b0c1480 1571 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1572 if (skge->autoneg == AUTONEG_DISABLE)
1573 ctrl &= ~PHY_CT_ANE;
1574
1575 ctrl |= PHY_CT_RESET;
6b0c1480 1576 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1577
1578 ctrl = 0;
1579 ct1000 = 0;
b18f2091 1580 adv = PHY_AN_CSMA;
baef58b1
SH		 1581
1582 if (skge->autoneg == AUTONEG_ENABLE) {
1583 if (iscopper(hw)) {
1584 if (skge->advertising & ADVERTISED_1000baseT_Full)
1585 ct1000 |= PHY_M_1000C_AFD;
1586 if (skge->advertising & ADVERTISED_1000baseT_Half)
1587 ct1000 |= PHY_M_1000C_AHD;
1588 if (skge->advertising & ADVERTISED_100baseT_Full)
1589 adv |= PHY_M_AN_100_FD;
1590 if (skge->advertising & ADVERTISED_100baseT_Half)
1591 adv |= PHY_M_AN_100_HD;
1592 if (skge->advertising & ADVERTISED_10baseT_Full)
1593 adv |= PHY_M_AN_10_FD;
1594 if (skge->advertising & ADVERTISED_10baseT_Half)
1595 adv |= PHY_M_AN_10_HD;
45bada65 1596 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1597 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1598
45bada65
SH		 1599 /* Set Flow-control capabilities */
1600 adv |= phy_pause_map[skge->flow_control];
1601
baef58b1
SH		 1602 /* Restart Auto-negotiation */
1603 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1604 } else {
1605 /* forced speed/duplex settings */
1606 ct1000 = PHY_M_1000C_MSE;
1607
1608 if (skge->duplex == DUPLEX_FULL)
1609 ctrl |= PHY_CT_DUP_MD;
1610
1611 switch (skge->speed) {
1612 case SPEED_1000:
1613 ctrl |= PHY_CT_SP1000;
1614 break;
1615 case SPEED_100:
1616 ctrl |= PHY_CT_SP100;
1617 break;
1618 }
1619
1620 ctrl |= PHY_CT_RESET;
1621 }
1622
c506a509 1623 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1624
6b0c1480
SH		 1625 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1626 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1627
1628 /* Setup Phy LED's */
1629 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
1630 ledover = 0;
1631
c506a509 1632 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
baef58b1 1633
c506a509
SH		 1634 /* turn off the Rx LED (LED_RX) */
1635 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
baef58b1
SH		 1636
1637 /* disable blink mode (LED_DUPLEX) on collisions */
1638 ctrl |= PHY_M_LEDC_DP_CTRL;
6b0c1480 1639 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
baef58b1
SH		 1640
1641 if (skge->autoneg == AUTONEG_DISABLE || skge->speed == SPEED_100) {
1642 /* turn on 100 Mbps LED (LED_LINK100) */
1643 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
1644 }
1645
1646 if (ledover)
6b0c1480 1647 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
baef58b1
SH		 1648
1649 /* Enable phy interrupt on autonegotiation complete (or link up) */
1650 if (skge->autoneg == AUTONEG_ENABLE)
6b0c1480 1651 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
baef58b1 1652 else
6b0c1480 1653 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1654}
1655
1656static void yukon_reset(struct skge_hw *hw, int port)
1657{
6b0c1480
SH		 1658 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1659 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1660 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1661 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1662 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1663
6b0c1480
SH		 1664 gma_write16(hw, port, GM_RX_CTRL,
1665 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1666 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1667}
1668
1669static void yukon_mac_init(struct skge_hw *hw, int port)
1670{
1671 struct skge_port *skge = netdev_priv(hw->dev[port]);
1672 int i;
1673 u32 reg;
1674 const u8 *addr = hw->dev[port]->dev_addr;
1675
1676 /* WA code for COMA mode -- set PHY reset */
1677 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1678 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1
SH		 1679 skge_write32(hw, B2_GP_IO,
1680 (skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9));
1681
1682 /* hard reset */
6b0c1480
SH		 1683 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1684 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1685
1686 /* WA code for COMA mode -- clear PHY reset */
1687 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1688 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1
SH		 1689 skge_write32(hw, B2_GP_IO,
1690 (skge_read32(hw, B2_GP_IO) | GP_DIR_9)
1691 & ~GP_IO_9);
1692
1693 /* Set hardware config mode */
1694 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1695 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
1696 reg |= iscopper(hw) ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
1697
1698 /* Clear GMC reset */
6b0c1480
SH		 1699 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1700 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1701 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
baef58b1
SH		 1702 if (skge->autoneg == AUTONEG_DISABLE) {
1703 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1704 gma_write16(hw, port, GM_GP_CTRL,
1705 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1706
1707 switch (skge->speed) {
1708 case SPEED_1000:
1709 reg |= GM_GPCR_SPEED_1000;
1710 /* fallthru */
1711 case SPEED_100:
1712 reg |= GM_GPCR_SPEED_100;
1713 }
1714
1715 if (skge->duplex == DUPLEX_FULL)
1716 reg |= GM_GPCR_DUP_FULL;
1717 } else
1718 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1719 switch (skge->flow_control) {
1720 case FLOW_MODE_NONE:
6b0c1480 1721 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1722 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1723 break;
1724 case FLOW_MODE_LOC_SEND:
1725 /* disable Rx flow-control */
1726 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1727 }
1728
6b0c1480 1729 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1
SH		 1730 skge_read16(hw, GMAC_IRQ_SRC);
1731
1732 spin_lock_bh(&hw->phy_lock);
1733 yukon_init(hw, port);
1734 spin_unlock_bh(&hw->phy_lock);
1735
1736 /* MIB clear */
6b0c1480
SH		 1737 reg = gma_read16(hw, port, GM_PHY_ADDR);
1738 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1739
1740 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1741 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1742 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1743
1744 /* transmit control */
6b0c1480 1745 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1746
1747 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1748 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1749 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1750
1751 /* transmit flow control */
6b0c1480 1752 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1753
1754 /* transmit parameter */
6b0c1480 1755 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1756 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1757 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1758 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1759
1760 /* serial mode register */
1761 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1762 if (hw->dev[port]->mtu > 1500)
1763 reg |= GM_SMOD_JUMBO_ENA;
1764
6b0c1480 1765 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1766
1767 /* physical address: used for pause frames */
6b0c1480 1768 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1769 /* virtual address for data */
6b0c1480 1770 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1771
1772 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1773 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1774 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1775 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1776
1777 /* Initialize Mac Fifo */
1778
1779 /* Configure Rx MAC FIFO */
6b0c1480 1780 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1
SH		 1781 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
1782 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1783 hw->chip_rev == CHIP_REV_YU_LITE_A3)
baef58b1 1784 reg &= ~GMF_RX_F_FL_ON;
6b0c1480
SH		 1785 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1786 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
1787 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
baef58b1
SH		 1788
1789 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1790 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1791 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1792}
1793
1794static void yukon_stop(struct skge_port *skge)
1795{
1796 struct skge_hw *hw = skge->hw;
1797 int port = skge->port;
1798
1799 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
981d0377 1800 hw->chip_rev == CHIP_REV_YU_LITE_A3) {
baef58b1
SH		 1801 skge_write32(hw, B2_GP_IO,
1802 skge_read32(hw, B2_GP_IO) | GP_DIR_9 | GP_IO_9);
1803 }
1804
6b0c1480
SH		 1805 gma_write16(hw, port, GM_GP_CTRL,
1806 gma_read16(hw, port, GM_GP_CTRL)
baef58b1 1807 & ~(GM_GPCR_RX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1808 gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1809
1810 /* set GPHY Control reset */
6b0c1480
SH		 1811 gma_write32(hw, port, GPHY_CTRL, GPC_RST_SET);
1812 gma_write32(hw, port, GMAC_CTRL, GMC_RST_SET);
baef58b1
SH		 1813}
1814
1815static void yukon_get_stats(struct skge_port *skge, u64 *data)
1816{
1817 struct skge_hw *hw = skge->hw;
1818 int port = skge->port;
1819 int i;
1820
6b0c1480
SH		 1821 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1822 | gma_read32(hw, port, GM_TXO_OK_LO);
1823 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1824 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1825
1826 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1827 data[i] = gma_read32(hw, port,
baef58b1
SH		 1828 skge_stats[i].gma_offset);
1829}
1830
1831static void yukon_mac_intr(struct skge_hw *hw, int port)
1832{
7e676d91
SH		 1833 struct net_device *dev = hw->dev[port];
1834 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1835 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1836
7e676d91
SH		 1837 if (netif_msg_intr(skge))
1838 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1839 dev->name, status);
1840
baef58b1
SH		 1841 if (status & GM_IS_RX_FF_OR) {
1842 ++skge->net_stats.rx_fifo_errors;
6b0c1480 1843 gma_write8(hw, port, RX_GMF_CTRL_T, GMF_CLI_RX_FO);
baef58b1
SH		 1844 }
1845 if (status & GM_IS_TX_FF_UR) {
1846 ++skge->net_stats.tx_fifo_errors;
6b0c1480 1847 gma_write8(hw, port, TX_GMF_CTRL_T, GMF_CLI_TX_FU);
baef58b1
SH		 1848 }
1849
1850}
1851
1852static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1853{
95566065 1854 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1855 case PHY_M_PS_SPEED_1000:
1856 return SPEED_1000;
1857 case PHY_M_PS_SPEED_100:
1858 return SPEED_100;
1859 default:
1860 return SPEED_10;
1861 }
1862}
1863
1864static void yukon_link_up(struct skge_port *skge)
1865{
1866 struct skge_hw *hw = skge->hw;
1867 int port = skge->port;
1868 u16 reg;
1869
1870 pr_debug("yukon_link_up\n");
1871
1872 /* Enable Transmit FIFO Underrun */
1873 skge_write8(hw, GMAC_IRQ_MSK, GMAC_DEF_MSK);
1874
6b0c1480 1875 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1876 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1877 reg |= GM_GPCR_DUP_FULL;
1878
1879 /* enable Rx/Tx */
1880 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1881 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1882
6b0c1480 1883 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
baef58b1
SH		 1884 skge_link_up(skge);
1885}
1886
1887static void yukon_link_down(struct skge_port *skge)
1888{
1889 struct skge_hw *hw = skge->hw;
1890 int port = skge->port;
1891
1892 pr_debug("yukon_link_down\n");
6b0c1480
SH		 1893 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1894 gm_phy_write(hw, port, GM_GP_CTRL,
1895 gm_phy_read(hw, port, GM_GP_CTRL)
baef58b1
SH		 1896 & ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA));
1897
c506a509 1898 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 1899 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1900 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1901 gm_phy_read(hw, port,
baef58b1
SH		 1902 PHY_MARV_AUNE_ADV)
1903 | PHY_M_AN_ASP);
1904
1905 }
1906
1907 yukon_reset(hw, port);
1908 skge_link_down(skge);
1909
1910 yukon_init(hw, port);
1911}
1912
1913static void yukon_phy_intr(struct skge_port *skge)
1914{
1915 struct skge_hw *hw = skge->hw;
1916 int port = skge->port;
1917 const char *reason = NULL;
1918 u16 istatus, phystat;
1919
6b0c1480
SH		 1920 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1921 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 1922
1923 if (netif_msg_intr(skge))
1924 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1925 skge->netdev->name, istatus, phystat);
baef58b1
SH		 1926
1927 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 1928 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 1929 & PHY_M_AN_RF) {
1930 reason = "remote fault";
1931 goto failed;
1932 }
1933
c506a509 1934 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 1935 reason = "master/slave fault";
1936 goto failed;
1937 }
1938
1939 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1940 reason = "speed/duplex";
1941 goto failed;
1942 }
1943
1944 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1945 ? DUPLEX_FULL : DUPLEX_HALF;
1946 skge->speed = yukon_speed(hw, phystat);
1947
baef58b1
SH		 1948 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1949 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1950 case PHY_M_PS_PAUSE_MSK:
1951 skge->flow_control = FLOW_MODE_SYMMETRIC;
1952 break;
1953 case PHY_M_PS_RX_P_EN:
1954 skge->flow_control = FLOW_MODE_REM_SEND;
1955 break;
1956 case PHY_M_PS_TX_P_EN:
1957 skge->flow_control = FLOW_MODE_LOC_SEND;
1958 break;
1959 default:
1960 skge->flow_control = FLOW_MODE_NONE;
1961 }
1962
1963 if (skge->flow_control == FLOW_MODE_NONE ||
1964 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 1965 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 1966 else
6b0c1480 1967 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 1968 yukon_link_up(skge);
1969 return;
1970 }
1971
1972 if (istatus & PHY_M_IS_LSP_CHANGE)
1973 skge->speed = yukon_speed(hw, phystat);
1974
1975 if (istatus & PHY_M_IS_DUP_CHANGE)
1976 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1977 if (istatus & PHY_M_IS_LST_CHANGE) {
1978 if (phystat & PHY_M_PS_LINK_UP)
1979 yukon_link_up(skge);
1980 else
1981 yukon_link_down(skge);
1982 }
1983 return;
1984 failed:
1985 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
1986 skge->netdev->name, reason);
1987
1988 /* XXX restart autonegotiation? */
1989}
1990
1991static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
1992{
1993 u32 end;
1994
1995 start /= 8;
1996 len /= 8;
1997 end = start + len - 1;
1998
1999 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2000 skge_write32(hw, RB_ADDR(q, RB_START), start);
2001 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2002 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2003 skge_write32(hw, RB_ADDR(q, RB_END), end);
2004
2005 if (q == Q_R1 || q == Q_R2) {
2006 /* Set thresholds on receive queue's */
2007 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2008 start + (2*len)/3);
2009 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2010 start + (len/3));
2011 } else {
2012 /* Enable store & forward on Tx queue's because
2013 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2014 */
2015 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2016 }
2017
2018 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2019}
2020
2021/* Setup Bus Memory Interface */
2022static void skge_qset(struct skge_port *skge, u16 q,
2023 const struct skge_element *e)
2024{
2025 struct skge_hw *hw = skge->hw;
2026 u32 watermark = 0x600;
2027 u64 base = skge->dma + (e->desc - skge->mem);
2028
2029 /* optimization to reduce window on 32bit/33mhz */
2030 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2031 watermark /= 2;
2032
2033 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2034 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2035 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2036 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2037}
2038
2039static int skge_up(struct net_device *dev)
2040{
2041 struct skge_port *skge = netdev_priv(dev);
2042 struct skge_hw *hw = skge->hw;
2043 int port = skge->port;
2044 u32 chunk, ram_addr;
2045 size_t rx_size, tx_size;
2046 int err;
2047
2048 if (netif_msg_ifup(skge))
2049 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2050
2051 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2052 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2053 skge->mem_size = tx_size + rx_size;
2054 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2055 if (!skge->mem)
2056 return -ENOMEM;
2057
2058 memset(skge->mem, 0, skge->mem_size);
2059
2060 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2061 goto free_pci_mem;
2062
2063 if (skge_rx_fill(skge))
2064 goto free_rx_ring;
2065
2066 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2067 skge->dma + rx_size)))
2068 goto free_rx_ring;
2069
2070 skge->tx_avail = skge->tx_ring.count - 1;
2071
7e676d91
SH		 2072 /* Enable IRQ from port */
2073 hw->intr_mask |= portirqmask[port];
2074 skge_write32(hw, B0_IMSK, hw->intr_mask);
2075
baef58b1
SH		 2076 /* Initialze MAC */
2077 if (hw->chip_id == CHIP_ID_GENESIS)
2078 genesis_mac_init(hw, port);
2079 else
2080 yukon_mac_init(hw, port);
2081
2082 /* Configure RAMbuffers */
981d0377 2083 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2084 ram_addr = hw->ram_offset + 2 * chunk * port;
2085
2086 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2087 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2088
2089 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2090 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2091 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2092
2093 /* Start receiver BMU */
2094 wmb();
2095 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2096
2097 pr_debug("skge_up completed\n");
2098 return 0;
2099
2100 free_rx_ring:
2101 skge_rx_clean(skge);
2102 kfree(skge->rx_ring.start);
2103 free_pci_mem:
2104 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2105
2106 return err;
2107}
2108
2109static int skge_down(struct net_device *dev)
2110{
2111 struct skge_port *skge = netdev_priv(dev);
2112 struct skge_hw *hw = skge->hw;
2113 int port = skge->port;
2114
2115 if (netif_msg_ifdown(skge))
2116 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2117
2118 netif_stop_queue(dev);
2119
2120 del_timer_sync(&skge->led_blink);
baef58b1
SH		 2121
2122 /* Stop transmitter */
2123 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2124 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2125 RB_RST_SET|RB_DIS_OP_MD);
2126
2127 if (hw->chip_id == CHIP_ID_GENESIS)
2128 genesis_stop(skge);
2129 else
2130 yukon_stop(skge);
2131
2132 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2133 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2134 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2135
2136 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2137 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2138 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2139
2140 /* Reset PCI FIFO */
2141 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2142 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2143
2144 /* Reset the RAM Buffer async Tx queue */
2145 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2146 /* stop receiver */
2147 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2148 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2149 RB_RST_SET|RB_DIS_OP_MD);
2150 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2151
2152 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2153 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2154 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2155 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_STOP);
2156 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_STOP);
baef58b1 2157 } else {
6b0c1480
SH		 2158 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2159 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2160 }
2161
2162 /* turn off led's */
2163 skge_write16(hw, B0_LED, LED_STAT_OFF);
2164
2165 skge_tx_clean(skge);
2166 skge_rx_clean(skge);
2167
2168 kfree(skge->rx_ring.start);
2169 kfree(skge->tx_ring.start);
2170 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2171 return 0;
2172}
2173
2174static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2175{
2176 struct skge_port *skge = netdev_priv(dev);
2177 struct skge_hw *hw = skge->hw;
2178 struct skge_ring *ring = &skge->tx_ring;
2179 struct skge_element *e;
2180 struct skge_tx_desc *td;
2181 int i;
2182 u32 control, len;
2183 u64 map;
2184 unsigned long flags;
2185
2186 skb = skb_padto(skb, ETH_ZLEN);
2187 if (!skb)
2188 return NETDEV_TX_OK;
2189
2190 local_irq_save(flags);
2191 if (!spin_trylock(&skge->tx_lock)) {
95566065
SH		 2192 /* Collision - tell upper layer to requeue */
2193 local_irq_restore(flags);
2194 return NETDEV_TX_LOCKED;
2195 }
baef58b1
SH		 2196
2197 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
2198 netif_stop_queue(dev);
2199 spin_unlock_irqrestore(&skge->tx_lock, flags);
2200
2201 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2202 dev->name);
2203 return NETDEV_TX_BUSY;
2204 }
2205
2206 e = ring->to_use;
2207 td = e->desc;
2208 e->skb = skb;
2209 len = skb_headlen(skb);
2210 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2211 pci_unmap_addr_set(e, mapaddr, map);
2212 pci_unmap_len_set(e, maplen, len);
2213
2214 td->dma_lo = map;
2215 td->dma_hi = map >> 32;
2216
2217 if (skb->ip_summed == CHECKSUM_HW) {
2218 const struct iphdr *ip
2219 = (const struct iphdr *) (skb->data + ETH_HLEN);
2220 int offset = skb->h.raw - skb->data;
2221
2222 /* This seems backwards, but it is what the sk98lin
2223 * does. Looks like hardware is wrong?
2224 */
2225 if (ip->protocol == IPPROTO_UDP
981d0377 2226 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2227 control = BMU_TCP_CHECK;
2228 else
2229 control = BMU_UDP_CHECK;
2230
2231 td->csum_offs = 0;
2232 td->csum_start = offset;
2233 td->csum_write = offset + skb->csum;
2234 } else
2235 control = BMU_CHECK;
2236
2237 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2238 control |= BMU_EOF| BMU_IRQ_EOF;
2239 else {
2240 struct skge_tx_desc *tf = td;
2241
2242 control |= BMU_STFWD;
2243 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2244 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2245
2246 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2247 frag->size, PCI_DMA_TODEVICE);
2248
2249 e = e->next;
2250 e->skb = NULL;
2251 tf = e->desc;
2252 tf->dma_lo = map;
2253 tf->dma_hi = (u64) map >> 32;
2254 pci_unmap_addr_set(e, mapaddr, map);
2255 pci_unmap_len_set(e, maplen, frag->size);
2256
2257 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2258 }
2259 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2260 }
2261 /* Make sure all the descriptors written */
2262 wmb();
2263 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2264 wmb();
2265
2266 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2267
2268 if (netif_msg_tx_queued(skge))
0b2d7fea 2269 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2270 dev->name, e - ring->start, skb->len);
2271
2272 ring->to_use = e->next;
2273 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2274 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2275 pr_debug("%s: transmit queue full\n", dev->name);
2276 netif_stop_queue(dev);
2277 }
2278
2279 dev->trans_start = jiffies;
2280 spin_unlock_irqrestore(&skge->tx_lock, flags);
2281
2282 return NETDEV_TX_OK;
2283}
2284
2285static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2286{
2287 if (e->skb) {
2288 pci_unmap_single(hw->pdev,
2289 pci_unmap_addr(e, mapaddr),
2290 pci_unmap_len(e, maplen),
2291 PCI_DMA_TODEVICE);
2292 dev_kfree_skb_any(e->skb);
2293 e->skb = NULL;
2294 } else {
2295 pci_unmap_page(hw->pdev,
2296 pci_unmap_addr(e, mapaddr),
2297 pci_unmap_len(e, maplen),
2298 PCI_DMA_TODEVICE);
2299 }
2300}
2301
2302static void skge_tx_clean(struct skge_port *skge)
2303{
2304 struct skge_ring *ring = &skge->tx_ring;
2305 struct skge_element *e;
2306 unsigned long flags;
2307
2308 spin_lock_irqsave(&skge->tx_lock, flags);
2309 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2310 ++skge->tx_avail;
2311 skge_tx_free(skge->hw, e);
2312 }
2313 ring->to_clean = e;
2314 spin_unlock_irqrestore(&skge->tx_lock, flags);
2315}
2316
2317static void skge_tx_timeout(struct net_device *dev)
2318{
2319 struct skge_port *skge = netdev_priv(dev);
2320
2321 if (netif_msg_timer(skge))
2322 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2323
2324 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2325 skge_tx_clean(skge);
2326}
2327
2328static int skge_change_mtu(struct net_device *dev, int new_mtu)
2329{
2330 int err = 0;
2331
95566065 2332 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2333 return -EINVAL;
2334
2335 dev->mtu = new_mtu;
2336
2337 if (netif_running(dev)) {
2338 skge_down(dev);
2339 skge_up(dev);
2340 }
2341
2342 return err;
2343}
2344
2345static void genesis_set_multicast(struct net_device *dev)
2346{
2347 struct skge_port *skge = netdev_priv(dev);
2348 struct skge_hw *hw = skge->hw;
2349 int port = skge->port;
2350 int i, count = dev->mc_count;
2351 struct dev_mc_list *list = dev->mc_list;
2352 u32 mode;
2353 u8 filter[8];
2354
45bada65
SH		 2355 pr_debug("genesis_set_multicast flags=%x count=%d\n", dev->flags, dev->mc_count);
2356
6b0c1480 2357 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2358 mode |= XM_MD_ENA_HASH;
2359 if (dev->flags & IFF_PROMISC)
2360 mode |= XM_MD_ENA_PROM;
2361 else
2362 mode &= ~XM_MD_ENA_PROM;
2363
2364 if (dev->flags & IFF_ALLMULTI)
2365 memset(filter, 0xff, sizeof(filter));
2366 else {
2367 memset(filter, 0, sizeof(filter));
95566065 2368 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2369 u32 crc, bit;
2370 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2371 bit = ~crc & 0x3f;
baef58b1
SH		 2372 filter[bit/8] |= 1 << (bit%8);
2373 }
2374 }
2375
6b0c1480 2376 xm_write32(hw, port, XM_MODE, mode);
45bada65 2377 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2378}
2379
2380static void yukon_set_multicast(struct net_device *dev)
2381{
2382 struct skge_port *skge = netdev_priv(dev);
2383 struct skge_hw *hw = skge->hw;
2384 int port = skge->port;
2385 struct dev_mc_list *list = dev->mc_list;
2386 u16 reg;
2387 u8 filter[8];
2388
2389 memset(filter, 0, sizeof(filter));
2390
6b0c1480 2391 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2392 reg |= GM_RXCR_UCF_ENA;
2393
2394 if (dev->flags & IFF_PROMISC) /* promiscious */
2395 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2396 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2397 memset(filter, 0xff, sizeof(filter));
2398 else if (dev->mc_count == 0) /* no multicast */
2399 reg &= ~GM_RXCR_MCF_ENA;
2400 else {
2401 int i;
2402 reg |= GM_RXCR_MCF_ENA;
2403
95566065 2404 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2405 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2406 filter[bit/8] |= 1 << (bit%8);
2407 }
2408 }
2409
2410
6b0c1480 2411 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2412 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2413 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2414 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2415 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2416 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2417 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2418 (u16)filter[6] | ((u16)filter[7] << 8));
2419
6b0c1480 2420 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2421}
2422
2423static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2424{
2425 if (hw->chip_id == CHIP_ID_GENESIS)
2426 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2427 else
2428 return (status & GMR_FS_ANY_ERR) ||
2429 (status & GMR_FS_RX_OK) == 0;
2430}
2431
2432static void skge_rx_error(struct skge_port *skge, int slot,
2433 u32 control, u32 status)
2434{
2435 if (netif_msg_rx_err(skge))
2436 printk(KERN_DEBUG PFX "%s: rx err, slot %d control 0x%x status 0x%x\n",
2437 skge->netdev->name, slot, control, status);
2438
2439 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2440 || (control & BMU_BBC) > skge->netdev->mtu + VLAN_ETH_HLEN)
2441 skge->net_stats.rx_length_errors++;
2442 else {
2443 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2444 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2445 skge->net_stats.rx_length_errors++;
2446 if (status & XMR_FS_FRA_ERR)
2447 skge->net_stats.rx_frame_errors++;
2448 if (status & XMR_FS_FCS_ERR)
2449 skge->net_stats.rx_crc_errors++;
2450 } else {
2451 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2452 skge->net_stats.rx_length_errors++;
2453 if (status & GMR_FS_FRAGMENT)
2454 skge->net_stats.rx_frame_errors++;
2455 if (status & GMR_FS_CRC_ERR)
2456 skge->net_stats.rx_crc_errors++;
2457 }
2458 }
2459}
2460
2461static int skge_poll(struct net_device *dev, int *budget)
2462{
2463 struct skge_port *skge = netdev_priv(dev);
2464 struct skge_hw *hw = skge->hw;
2465 struct skge_ring *ring = &skge->rx_ring;
2466 struct skge_element *e;
2467 unsigned int to_do = min(dev->quota, *budget);
2468 unsigned int work_done = 0;
2469 int done;
7e676d91
SH		 2470
2471 pr_debug("skge_poll\n");
baef58b1
SH		 2472
2473 for (e = ring->to_clean; e != ring->to_use && work_done < to_do;
2474 e = e->next) {
2475 struct skge_rx_desc *rd = e->desc;
2476 struct sk_buff *skb = e->skb;
2477 u32 control, len, status;
2478
2479 rmb();
2480 control = rd->control;
2481 if (control & BMU_OWN)
2482 break;
2483
2484 len = control & BMU_BBC;
2485 e->skb = NULL;
2486
2487 pci_unmap_single(hw->pdev,
2488 pci_unmap_addr(e, mapaddr),
2489 pci_unmap_len(e, maplen),
2490 PCI_DMA_FROMDEVICE);
2491
2492 status = rd->status;
2493 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF)
2494 || len > dev->mtu + VLAN_ETH_HLEN
2495 || bad_phy_status(hw, status)) {
2496 skge_rx_error(skge, e - ring->start, control, status);
2497 dev_kfree_skb(skb);
2498 continue;
2499 }
2500
2501 if (netif_msg_rx_status(skge))
0b2d7fea 2502 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
baef58b1
SH		 2503 dev->name, e - ring->start, rd->status, len);
2504
2505 skb_put(skb, len);
2506 skb->protocol = eth_type_trans(skb, dev);
2507
2508 if (skge->rx_csum) {
2509 skb->csum = le16_to_cpu(rd->csum2);
2510 skb->ip_summed = CHECKSUM_HW;
2511 }
2512
2513 dev->last_rx = jiffies;
2514 netif_receive_skb(skb);
2515
2516 ++work_done;
2517 }
2518 ring->to_clean = e;
2519
2520 *budget -= work_done;
2521 dev->quota -= work_done;
2522 done = work_done < to_do;
2523
2524 if (skge_rx_fill(skge))
2525 done = 0;
2526
2527 /* restart receiver */
2528 wmb();
2529 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2530 CSR_START | CSR_IRQ_CL_F);
2531
2532 if (done) {
2533 local_irq_disable();
baef58b1 2534 __netif_rx_complete(dev);
7e676d91
SH		 2535 hw->intr_mask |= portirqmask[skge->port];
2536 skge_write32(hw, B0_IMSK, hw->intr_mask);
baef58b1
SH		 2537 local_irq_enable();
2538 }
2539
2540 return !done;
2541}
2542
2543static inline void skge_tx_intr(struct net_device *dev)
2544{
2545 struct skge_port *skge = netdev_priv(dev);
2546 struct skge_hw *hw = skge->hw;
2547 struct skge_ring *ring = &skge->tx_ring;
2548 struct skge_element *e;
2549
2550 spin_lock(&skge->tx_lock);
95566065 2551 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
baef58b1
SH		 2552 struct skge_tx_desc *td = e->desc;
2553 u32 control;
2554
2555 rmb();
2556 control = td->control;
2557 if (control & BMU_OWN)
2558 break;
2559
2560 if (unlikely(netif_msg_tx_done(skge)))
0b2d7fea 2561 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
baef58b1
SH		 2562 dev->name, e - ring->start, td->status);
2563
2564 skge_tx_free(hw, e);
2565 e->skb = NULL;
2566 ++skge->tx_avail;
2567 }
2568 ring->to_clean = e;
2569 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2570
2571 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2572 netif_wake_queue(dev);
2573
2574 spin_unlock(&skge->tx_lock);
2575}
2576
2577static void skge_mac_parity(struct skge_hw *hw, int port)
2578{
2579 printk(KERN_ERR PFX "%s: mac data parity error\n",
2580 hw->dev[port] ? hw->dev[port]->name
2581 : (port == 0 ? "(port A)": "(port B"));
2582
2583 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2584 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2585 MFF_CLR_PERR);
2586 else
2587 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2588 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2589 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2590 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2591}
2592
2593static void skge_pci_clear(struct skge_hw *hw)
2594{
2595 u16 status;
2596
467b3417 2597 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
baef58b1 2598 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
467b3417
SH		 2599 pci_write_config_word(hw->pdev, PCI_STATUS,
2600 status | PCI_STATUS_ERROR_BITS);
baef58b1
SH		 2601 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2602}
2603
2604static void skge_mac_intr(struct skge_hw *hw, int port)
2605{
95566065 2606 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2607 genesis_mac_intr(hw, port);
2608 else
2609 yukon_mac_intr(hw, port);
2610}
2611
2612/* Handle device specific framing and timeout interrupts */
2613static void skge_error_irq(struct skge_hw *hw)
2614{
2615 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2616
2617 if (hw->chip_id == CHIP_ID_GENESIS) {
2618 /* clear xmac errors */
2619 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
6b0c1480 2620 skge_write16(hw, SK_REG(0, RX_MFF_CTRL1), MFF_CLR_INSTAT);
baef58b1 2621 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
6b0c1480 2622 skge_write16(hw, SK_REG(0, RX_MFF_CTRL2), MFF_CLR_INSTAT);
baef58b1
SH		 2623 } else {
2624 /* Timestamp (unused) overflow */
2625 if (hwstatus & IS_IRQ_TIST_OV)
2626 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2627
2628 if (hwstatus & IS_IRQ_SENSOR) {
2629 /* no sensors on 32-bit Yukon */
2630 if (!(skge_read16(hw, B0_CTST) & CS_BUS_SLOT_SZ)) {
2631 printk(KERN_ERR PFX "ignoring bogus sensor interrups\n");
2632 skge_write32(hw, B0_HWE_IMSK,
2633 IS_ERR_MSK & ~IS_IRQ_SENSOR);
2634 } else
2635 printk(KERN_WARNING PFX "sensor interrupt\n");
2636 }
2637
2638
2639 }
2640
2641 if (hwstatus & IS_RAM_RD_PAR) {
2642 printk(KERN_ERR PFX "Ram read data parity error\n");
2643 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2644 }
2645
2646 if (hwstatus & IS_RAM_WR_PAR) {
2647 printk(KERN_ERR PFX "Ram write data parity error\n");
2648 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2649 }
2650
2651 if (hwstatus & IS_M1_PAR_ERR)
2652 skge_mac_parity(hw, 0);
2653
2654 if (hwstatus & IS_M2_PAR_ERR)
2655 skge_mac_parity(hw, 1);
2656
2657 if (hwstatus & IS_R1_PAR_ERR)
2658 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2659
2660 if (hwstatus & IS_R2_PAR_ERR)
2661 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2662
2663 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2664 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2665 hwstatus);
2666
2667 skge_pci_clear(hw);
2668
2669 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2670 if (hwstatus & IS_IRQ_STAT) {
2671 printk(KERN_WARNING PFX "IRQ status %x: still set ignoring hardware errors\n",
2672 hwstatus);
2673 hw->intr_mask &= ~IS_HW_ERR;
2674 }
2675 }
2676}
2677
2678/*
2679 * Interrrupt from PHY are handled in tasklet (soft irq)
2680 * because accessing phy registers requires spin wait which might
2681 * cause excess interrupt latency.
2682 */
2683static void skge_extirq(unsigned long data)
2684{
2685 struct skge_hw *hw = (struct skge_hw *) data;
2686 int port;
2687
2688 spin_lock(&hw->phy_lock);
2689 for (port = 0; port < 2; port++) {
2690 struct net_device *dev = hw->dev[port];
2691
2692 if (dev && netif_running(dev)) {
2693 struct skge_port *skge = netdev_priv(dev);
2694
2695 if (hw->chip_id != CHIP_ID_GENESIS)
2696 yukon_phy_intr(skge);
89bf5f23 2697 else
45bada65 2698 bcom_phy_intr(skge);
baef58b1
SH		 2699 }
2700 }
2701 spin_unlock(&hw->phy_lock);
2702
2703 local_irq_disable();
2704 hw->intr_mask |= IS_EXT_REG;
2705 skge_write32(hw, B0_IMSK, hw->intr_mask);
2706 local_irq_enable();
2707}
2708
2709static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2710{
2711 struct skge_hw *hw = dev_id;
2712 u32 status = skge_read32(hw, B0_SP_ISRC);
2713
2714 if (status == 0 || status == ~0) /* hotplug or shared irq */
2715 return IRQ_NONE;
2716
2717 status &= hw->intr_mask;
7e676d91 2718 if (status & IS_R1_F) {
baef58b1 2719 hw->intr_mask &= ~IS_R1_F;
7e676d91 2720 netif_rx_schedule(hw->dev[0]);
baef58b1
SH		 2721 }
2722
7e676d91 2723 if (status & IS_R2_F) {
baef58b1 2724 hw->intr_mask &= ~IS_R2_F;
7e676d91 2725 netif_rx_schedule(hw->dev[1]);
baef58b1
SH		 2726 }
2727
2728 if (status & IS_XA1_F)
2729 skge_tx_intr(hw->dev[0]);
2730
2731 if (status & IS_XA2_F)
2732 skge_tx_intr(hw->dev[1]);
2733
d25f5a67
SH		 2734 if (status & IS_PA_TO_RX1) {
2735 struct skge_port *skge = netdev_priv(hw->dev[0]);
2736 ++skge->net_stats.rx_over_errors;
2737 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2738 }
2739
2740 if (status & IS_PA_TO_RX2) {
2741 struct skge_port *skge = netdev_priv(hw->dev[1]);
2742 ++skge->net_stats.rx_over_errors;
2743 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2744 }
2745
2746 if (status & IS_PA_TO_TX1)
2747 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2748
2749 if (status & IS_PA_TO_TX2)
2750 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2751
baef58b1
SH		 2752 if (status & IS_MAC1)
2753 skge_mac_intr(hw, 0);
95566065 2754
baef58b1
SH		 2755 if (status & IS_MAC2)
2756 skge_mac_intr(hw, 1);
2757
2758 if (status & IS_HW_ERR)
2759 skge_error_irq(hw);
2760
2761 if (status & IS_EXT_REG) {
2762 hw->intr_mask &= ~IS_EXT_REG;
2763 tasklet_schedule(&hw->ext_tasklet);
2764 }
2765
7e676d91 2766 skge_write32(hw, B0_IMSK, hw->intr_mask);
baef58b1
SH		 2767
2768 return IRQ_HANDLED;
2769}
2770
2771#ifdef CONFIG_NET_POLL_CONTROLLER
2772static void skge_netpoll(struct net_device *dev)
2773{
2774 struct skge_port *skge = netdev_priv(dev);
2775
2776 disable_irq(dev->irq);
2777 skge_intr(dev->irq, skge->hw, NULL);
2778 enable_irq(dev->irq);
2779}
2780#endif
2781
2782static int skge_set_mac_address(struct net_device *dev, void *p)
2783{
2784 struct skge_port *skge = netdev_priv(dev);
2785 struct sockaddr *addr = p;
2786 int err = 0;
2787
2788 if (!is_valid_ether_addr(addr->sa_data))
2789 return -EADDRNOTAVAIL;
2790
2791 skge_down(dev);
2792 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2793 memcpy_toio(skge->hw->regs + B2_MAC_1 + skge->port*8,
2794 dev->dev_addr, ETH_ALEN);
2795 memcpy_toio(skge->hw->regs + B2_MAC_2 + skge->port*8,
2796 dev->dev_addr, ETH_ALEN);
2797 if (dev->flags & IFF_UP)
2798 err = skge_up(dev);
2799 return err;
2800}
2801
2802static const struct {
2803 u8 id;
2804 const char *name;
2805} skge_chips[] = {
2806 { CHIP_ID_GENESIS, "Genesis" },
2807 { CHIP_ID_YUKON, "Yukon" },
2808 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2809 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 2810};
2811
2812static const char *skge_board_name(const struct skge_hw *hw)
2813{
2814 int i;
2815 static char buf[16];
2816
2817 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2818 if (skge_chips[i].id == hw->chip_id)
2819 return skge_chips[i].name;
2820
2821 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2822 return buf;
2823}
2824
2825
2826/*
2827 * Setup the board data structure, but don't bring up
2828 * the port(s)
2829 */
2830static int skge_reset(struct skge_hw *hw)
2831{
2832 u16 ctst;
981d0377
SH		 2833 u8 t8, mac_cfg;
2834 int i;
baef58b1
SH		 2835
2836 ctst = skge_read16(hw, B0_CTST);
2837
2838 /* do a SW reset */
2839 skge_write8(hw, B0_CTST, CS_RST_SET);
2840 skge_write8(hw, B0_CTST, CS_RST_CLR);
2841
2842 /* clear PCI errors, if any */
2843 skge_pci_clear(hw);
2844
2845 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2846
2847 /* restore CLK_RUN bits (for Yukon-Lite) */
2848 skge_write16(hw, B0_CTST,
2849 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2850
2851 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
2852 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
2853 hw->pmd_type = skge_read8(hw, B2_PMD_TYP);
2854
95566065 2855 switch (hw->chip_id) {
baef58b1
SH		 2856 case CHIP_ID_GENESIS:
2857 switch (hw->phy_type) {
baef58b1
SH		 2858 case SK_PHY_BCOM:
2859 hw->phy_addr = PHY_ADDR_BCOM;
2860 break;
2861 default:
2862 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
2863 pci_name(hw->pdev), hw->phy_type);
2864 return -EOPNOTSUPP;
2865 }
2866 break;
2867
2868 case CHIP_ID_YUKON:
2869 case CHIP_ID_YUKON_LITE:
2870 case CHIP_ID_YUKON_LP:
2871 if (hw->phy_type < SK_PHY_MARV_COPPER && hw->pmd_type != 'S')
2872 hw->phy_type = SK_PHY_MARV_COPPER;
2873
2874 hw->phy_addr = PHY_ADDR_MARV;
2875 if (!iscopper(hw))
2876 hw->phy_type = SK_PHY_MARV_FIBER;
2877
2878 break;
2879
2880 default:
2881 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2882 pci_name(hw->pdev), hw->chip_id);
2883 return -EOPNOTSUPP;
2884 }
2885
981d0377
SH		 2886 mac_cfg = skge_read8(hw, B2_MAC_CFG);
2887 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
2888 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 2889
2890 /* read the adapters RAM size */
2891 t8 = skge_read8(hw, B2_E_0);
2892 if (hw->chip_id == CHIP_ID_GENESIS) {
2893 if (t8 == 3) {
2894 /* special case: 4 x 64k x 36, offset = 0x80000 */
2895 hw->ram_size = 0x100000;
2896 hw->ram_offset = 0x80000;
2897 } else
2898 hw->ram_size = t8 * 512;
2899 }
2900 else if (t8 == 0)
2901 hw->ram_size = 0x20000;
2902 else
2903 hw->ram_size = t8 * 4096;
2904
2905 if (hw->chip_id == CHIP_ID_GENESIS)
2906 genesis_init(hw);
2907 else {
2908 /* switch power to VCC (WA for VAUX problem) */
2909 skge_write8(hw, B0_POWER_CTRL,
2910 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
981d0377 2911 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 2912 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2913 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 2914 }
2915 }
2916
2917 /* turn off hardware timer (unused) */
2918 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
2919 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2920 skge_write8(hw, B0_LED, LED_STAT_ON);
2921
2922 /* enable the Tx Arbiters */
981d0377 2923 for (i = 0; i < hw->ports; i++)
6b0c1480 2924 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 2925
2926 /* Initialize ram interface */
2927 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
2928
2929 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
2930 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
2931 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
2932 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
2933 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
2934 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
2935 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
2936 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
2937 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
2938 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
2939 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
2940 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
2941
2942 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
2943
2944 /* Set interrupt moderation for Transmit only
2945 * Receive interrupts avoided by NAPI
2946 */
2947 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
2948 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
2949 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
2950
7e676d91 2951 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
baef58b1
SH		 2952 skge_write32(hw, B0_IMSK, hw->intr_mask);
2953
2954 if (hw->chip_id != CHIP_ID_GENESIS)
2955 skge_write8(hw, GMAC_IRQ_MSK, 0);
2956
2957 spin_lock_bh(&hw->phy_lock);
981d0377 2958 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 2959 if (hw->chip_id == CHIP_ID_GENESIS)
2960 genesis_reset(hw, i);
2961 else
2962 yukon_reset(hw, i);
2963 }
2964 spin_unlock_bh(&hw->phy_lock);
2965
2966 return 0;
2967}
2968
2969/* Initialize network device */
981d0377
SH		 2970static struct net_device *skge_devinit(struct skge_hw *hw, int port,
2971 int highmem)
baef58b1
SH		 2972{
2973 struct skge_port *skge;
2974 struct net_device *dev = alloc_etherdev(sizeof(*skge));
2975
2976 if (!dev) {
2977 printk(KERN_ERR "skge etherdev alloc failed");
2978 return NULL;
2979 }
2980
2981 SET_MODULE_OWNER(dev);
2982 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2983 dev->open = skge_up;
2984 dev->stop = skge_down;
2985 dev->hard_start_xmit = skge_xmit_frame;
2986 dev->get_stats = skge_get_stats;
2987 if (hw->chip_id == CHIP_ID_GENESIS)
2988 dev->set_multicast_list = genesis_set_multicast;
2989 else
2990 dev->set_multicast_list = yukon_set_multicast;
2991
2992 dev->set_mac_address = skge_set_mac_address;
2993 dev->change_mtu = skge_change_mtu;
2994 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
2995 dev->tx_timeout = skge_tx_timeout;
2996 dev->watchdog_timeo = TX_WATCHDOG;
2997 dev->poll = skge_poll;
2998 dev->weight = NAPI_WEIGHT;
2999#ifdef CONFIG_NET_POLL_CONTROLLER
3000 dev->poll_controller = skge_netpoll;
3001#endif
3002 dev->irq = hw->pdev->irq;
3003 dev->features = NETIF_F_LLTX;
981d0377
SH		 3004 if (highmem)
3005 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3006
3007 skge = netdev_priv(dev);
3008 skge->netdev = dev;
3009 skge->hw = hw;
3010 skge->msg_enable = netif_msg_init(debug, default_msg);
3011 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3012 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3013
3014 /* Auto speed and flow control */
3015 skge->autoneg = AUTONEG_ENABLE;
3016 skge->flow_control = FLOW_MODE_SYMMETRIC;
3017 skge->duplex = -1;
3018 skge->speed = -1;
31b619c5 3019 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3020
3021 hw->dev[port] = dev;
3022
3023 skge->port = port;
3024
3025 spin_lock_init(&skge->tx_lock);
3026
baef58b1
SH		 3027 init_timer(&skge->led_blink);
3028 skge->led_blink.function = skge_blink_timer;
3029 skge->led_blink.data = (unsigned long) skge;
3030
3031 if (hw->chip_id != CHIP_ID_GENESIS) {
3032 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3033 skge->rx_csum = 1;
3034 }
3035
3036 /* read the mac address */
3037 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3038
3039 /* device is off until link detection */
3040 netif_carrier_off(dev);
3041 netif_stop_queue(dev);
3042
3043 return dev;
3044}
3045
3046static void __devinit skge_show_addr(struct net_device *dev)
3047{
3048 const struct skge_port *skge = netdev_priv(dev);
3049
3050 if (netif_msg_probe(skge))
3051 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3052 dev->name,
3053 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3054 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3055}
3056
3057static int __devinit skge_probe(struct pci_dev *pdev,
3058 const struct pci_device_id *ent)
3059{
3060 struct net_device *dev, *dev1;
3061 struct skge_hw *hw;
3062 int err, using_dac = 0;
3063
3064 if ((err = pci_enable_device(pdev))) {
3065 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3066 pci_name(pdev));
3067 goto err_out;
3068 }
3069
3070 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3071 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3072 pci_name(pdev));
3073 goto err_out_disable_pdev;
3074 }
3075
3076 pci_set_master(pdev);
3077
3078 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3079 using_dac = 1;
3080 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3081 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3082 pci_name(pdev));
3083 goto err_out_free_regions;
3084 }
3085
3086#ifdef __BIG_ENDIAN
3087 /* byte swap decriptors in hardware */
3088 {
3089 u32 reg;
3090
3091 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3092 reg |= PCI_REV_DESC;
3093 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3094 }
3095#endif
3096
3097 err = -ENOMEM;
3098 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3099 if (!hw) {
3100 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3101 pci_name(pdev));
3102 goto err_out_free_regions;
3103 }
3104
3105 memset(hw, 0, sizeof(*hw));
3106 hw->pdev = pdev;
3107 spin_lock_init(&hw->phy_lock);
3108 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3109
3110 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3111 if (!hw->regs) {
3112 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3113 pci_name(pdev));
3114 goto err_out_free_hw;
3115 }
3116
3117 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3118 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3119 pci_name(pdev), pdev->irq);
3120 goto err_out_iounmap;
3121 }
3122 pci_set_drvdata(pdev, hw);
3123
3124 err = skge_reset(hw);
3125 if (err)
3126 goto err_out_free_irq;
3127
3128 printk(KERN_INFO PFX "addr 0x%lx irq %d chip %s rev %d\n",
3129 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3130 skge_board_name(hw), hw->chip_rev);
baef58b1 3131
981d0377 3132 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3133 goto err_out_led_off;
3134
baef58b1
SH		 3135 if ((err = register_netdev(dev))) {
3136 printk(KERN_ERR PFX "%s: cannot register net device\n",
3137 pci_name(pdev));
3138 goto err_out_free_netdev;
3139 }
3140
3141 skge_show_addr(dev);
3142
981d0377 3143 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3144 if (register_netdev(dev1) == 0)
3145 skge_show_addr(dev1);
3146 else {
3147 /* Failure to register second port need not be fatal */
3148 printk(KERN_WARNING PFX "register of second port failed\n");
3149 hw->dev[1] = NULL;
3150 free_netdev(dev1);
3151 }
3152 }
3153
3154 return 0;
3155
3156err_out_free_netdev:
3157 free_netdev(dev);
3158err_out_led_off:
3159 skge_write16(hw, B0_LED, LED_STAT_OFF);
3160err_out_free_irq:
3161 free_irq(pdev->irq, hw);
3162err_out_iounmap:
3163 iounmap(hw->regs);
3164err_out_free_hw:
3165 kfree(hw);
3166err_out_free_regions:
3167 pci_release_regions(pdev);
3168err_out_disable_pdev:
3169 pci_disable_device(pdev);
3170 pci_set_drvdata(pdev, NULL);
3171err_out:
3172 return err;
3173}
3174
3175static void __devexit skge_remove(struct pci_dev *pdev)
3176{
3177 struct skge_hw *hw = pci_get_drvdata(pdev);
3178 struct net_device *dev0, *dev1;
3179
95566065 3180 if (!hw)
baef58b1
SH		 3181 return;
3182
3183 if ((dev1 = hw->dev[1]))
3184 unregister_netdev(dev1);
3185 dev0 = hw->dev[0];
3186 unregister_netdev(dev0);
3187
3188 tasklet_kill(&hw->ext_tasklet);
3189
3190 free_irq(pdev->irq, hw);
3191 pci_release_regions(pdev);
3192 pci_disable_device(pdev);
3193 if (dev1)
3194 free_netdev(dev1);
3195 free_netdev(dev0);
3196 skge_write16(hw, B0_LED, LED_STAT_OFF);
3197 iounmap(hw->regs);
3198 kfree(hw);
3199 pci_set_drvdata(pdev, NULL);
3200}
3201
3202#ifdef CONFIG_PM
3203static int skge_suspend(struct pci_dev *pdev, u32 state)
3204{
3205 struct skge_hw *hw = pci_get_drvdata(pdev);
3206 int i, wol = 0;
3207
95566065 3208 for (i = 0; i < 2; i++) {
baef58b1
SH		 3209 struct net_device *dev = hw->dev[i];
3210
3211 if (dev) {
3212 struct skge_port *skge = netdev_priv(dev);
3213 if (netif_running(dev)) {
3214 netif_carrier_off(dev);
3215 skge_down(dev);
3216 }
3217 netif_device_detach(dev);
3218 wol |= skge->wol;
3219 }
3220 }
3221
3222 pci_save_state(pdev);
3223 pci_enable_wake(pdev, state, wol);
3224 pci_disable_device(pdev);
3225 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3226
3227 return 0;
3228}
3229
3230static int skge_resume(struct pci_dev *pdev)
3231{
3232 struct skge_hw *hw = pci_get_drvdata(pdev);
3233 int i;
3234
3235 pci_set_power_state(pdev, PCI_D0);
3236 pci_restore_state(pdev);
3237 pci_enable_wake(pdev, PCI_D0, 0);
3238
3239 skge_reset(hw);
3240
95566065 3241 for (i = 0; i < 2; i++) {
baef58b1
SH		 3242 struct net_device *dev = hw->dev[i];
3243 if (dev) {
3244 netif_device_attach(dev);
95566065 3245 if (netif_running(dev))
baef58b1
SH		 3246 skge_up(dev);
3247 }
3248 }
3249 return 0;
3250}
3251#endif
3252
3253static struct pci_driver skge_driver = {
3254 .name = DRV_NAME,
3255 .id_table = skge_id_table,
3256 .probe = skge_probe,
3257 .remove = __devexit_p(skge_remove),
3258#ifdef CONFIG_PM
3259 .suspend = skge_suspend,
3260 .resume = skge_resume,
3261#endif
3262};
3263
3264static int __init skge_init_module(void)
3265{
3266 return pci_module_init(&skge_driver);
3267}
3268
3269static void __exit skge_cleanup_module(void)
3270{
3271 pci_unregister_driver(&skge_driver);
3272}
3273
3274module_init(skge_init_module);
3275module_exit(skge_cleanup_module);
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