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[PATCH] skge: avoid up/down on speed changes
[mirror_ubuntu-zesty-kernel.git] / drivers / net / skge.c
CommitLineData
baef58b1
SH		 1/*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
747802ab 10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
baef58b1
SH		 11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/config.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/moduleparam.h>
31#include <linux/netdevice.h>
32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/if_vlan.h>
36#include <linux/ip.h>
37#include <linux/delay.h>
38#include <linux/crc32.h>
4075400b 39#include <linux/dma-mapping.h>
2cd8e5d3 40#include <linux/mii.h>
baef58b1
SH		 41#include <asm/irq.h>
42
43#include "skge.h"
44
45#define DRV_NAME "skge"
d7eaee08 46#define DRV_VERSION "1.2"
baef58b1
SH		 47#define PFX DRV_NAME " "
48
49#define DEFAULT_TX_RING_SIZE 128
50#define DEFAULT_RX_RING_SIZE 512
51#define MAX_TX_RING_SIZE 1024
52#define MAX_RX_RING_SIZE 4096
19a33d4e
SH		 53#define RX_COPY_THRESHOLD 128
54#define RX_BUF_SIZE 1536
baef58b1
SH		 55#define PHY_RETRIES 1000
56#define ETH_JUMBO_MTU 9000
57#define TX_WATCHDOG (5 * HZ)
58#define NAPI_WEIGHT 64
6abebb53 59#define BLINK_MS 250
baef58b1
SH		 60
61MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
62MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
63MODULE_LICENSE("GPL");
64MODULE_VERSION(DRV_VERSION);
65
66static const u32 default_msg
67 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
68 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
69
70static int debug = -1; /* defaults above */
71module_param(debug, int, 0);
72MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
73
74static const struct pci_device_id skge_id_table[] = {
275834d1
SH		 75 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
77 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
275834d1
SH		 79 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T), },
80 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
81 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
82 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
275834d1 83 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86f0cd50 84 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015, },
baef58b1
SH		 85 { 0 }
86};
87MODULE_DEVICE_TABLE(pci, skge_id_table);
88
89static int skge_up(struct net_device *dev);
90static int skge_down(struct net_device *dev);
ee294dcd 91static void skge_phy_reset(struct skge_port *skge);
baef58b1 92static void skge_tx_clean(struct skge_port *skge);
2cd8e5d3
SH		 93static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
94static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
baef58b1
SH		 95static void genesis_get_stats(struct skge_port *skge, u64 *data);
96static void yukon_get_stats(struct skge_port *skge, u64 *data);
97static void yukon_init(struct skge_hw *hw, int port);
baef58b1 98static void genesis_mac_init(struct skge_hw *hw, int port);
45bada65 99static void genesis_link_up(struct skge_port *skge);
baef58b1 100
7e676d91 101/* Avoid conditionals by using array */
baef58b1
SH		 102static const int txqaddr[] = { Q_XA1, Q_XA2 };
103static const int rxqaddr[] = { Q_R1, Q_R2 };
104static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
105static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
7e676d91 106static const u32 portirqmask[] = { IS_PORT_1, IS_PORT_2 };
baef58b1 107
baef58b1
SH		 108static int skge_get_regs_len(struct net_device *dev)
109{
c3f8be96 110 return 0x4000;
baef58b1
SH		 111}
112
113/*
c3f8be96
SH		 114 * Returns copy of whole control register region
115 * Note: skip RAM address register because accessing it will
116 * cause bus hangs!
baef58b1
SH		 117 */
118static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
119 void *p)
120{
121 const struct skge_port *skge = netdev_priv(dev);
baef58b1 122 const void __iomem *io = skge->hw->regs;
baef58b1
SH		 123
124 regs->version = 1;
c3f8be96
SH		 125 memset(p, 0, regs->len);
126 memcpy_fromio(p, io, B3_RAM_ADDR);
baef58b1 127
c3f8be96
SH		 128 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
129 regs->len - B3_RI_WTO_R1);
baef58b1
SH		 130}
131
8f3f8193 132/* Wake on Lan only supported on Yukon chips with rev 1 or above */
baef58b1
SH		 133static int wol_supported(const struct skge_hw *hw)
134{
135 return !((hw->chip_id == CHIP_ID_GENESIS ||
981d0377 136 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)));
baef58b1
SH		 137}
138
139static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
140{
141 struct skge_port *skge = netdev_priv(dev);
142
143 wol->supported = wol_supported(skge->hw) ? WAKE_MAGIC : 0;
144 wol->wolopts = skge->wol ? WAKE_MAGIC : 0;
145}
146
147static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
148{
149 struct skge_port *skge = netdev_priv(dev);
150 struct skge_hw *hw = skge->hw;
151
95566065 152 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
baef58b1
SH		 153 return -EOPNOTSUPP;
154
155 if (wol->wolopts == WAKE_MAGIC && !wol_supported(hw))
156 return -EOPNOTSUPP;
157
158 skge->wol = wol->wolopts == WAKE_MAGIC;
159
160 if (skge->wol) {
161 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
162
163 skge_write16(hw, WOL_CTRL_STAT,
164 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
165 WOL_CTL_ENA_MAGIC_PKT_UNIT);
166 } else
167 skge_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
168
169 return 0;
170}
171
8f3f8193
SH		 172/* Determine supported/advertised modes based on hardware.
173 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
31b619c5
SH		 174 */
175static u32 skge_supported_modes(const struct skge_hw *hw)
176{
177 u32 supported;
178
5e1705dd 179 if (hw->copper) {
31b619c5
SH		 180 supported = SUPPORTED_10baseT_Half
181 | SUPPORTED_10baseT_Full
182 | SUPPORTED_100baseT_Half
183 | SUPPORTED_100baseT_Full
184 | SUPPORTED_1000baseT_Half
185 | SUPPORTED_1000baseT_Full
186 | SUPPORTED_Autoneg| SUPPORTED_TP;
187
188 if (hw->chip_id == CHIP_ID_GENESIS)
189 supported &= ~(SUPPORTED_10baseT_Half
190 | SUPPORTED_10baseT_Full
191 | SUPPORTED_100baseT_Half
192 | SUPPORTED_100baseT_Full);
193
194 else if (hw->chip_id == CHIP_ID_YUKON)
195 supported &= ~SUPPORTED_1000baseT_Half;
196 } else
197 supported = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
198 | SUPPORTED_Autoneg;
199
200 return supported;
201}
baef58b1
SH		 202
203static int skge_get_settings(struct net_device *dev,
204 struct ethtool_cmd *ecmd)
205{
206 struct skge_port *skge = netdev_priv(dev);
207 struct skge_hw *hw = skge->hw;
208
209 ecmd->transceiver = XCVR_INTERNAL;
31b619c5 210 ecmd->supported = skge_supported_modes(hw);
baef58b1 211
5e1705dd 212 if (hw->copper) {
baef58b1
SH		 213 ecmd->port = PORT_TP;
214 ecmd->phy_address = hw->phy_addr;
31b619c5 215 } else
baef58b1 216 ecmd->port = PORT_FIBRE;
baef58b1
SH		 217
218 ecmd->advertising = skge->advertising;
219 ecmd->autoneg = skge->autoneg;
220 ecmd->speed = skge->speed;
221 ecmd->duplex = skge->duplex;
222 return 0;
223}
224
baef58b1
SH		 225static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
226{
227 struct skge_port *skge = netdev_priv(dev);
228 const struct skge_hw *hw = skge->hw;
31b619c5 229 u32 supported = skge_supported_modes(hw);
baef58b1
SH		 230
231 if (ecmd->autoneg == AUTONEG_ENABLE) {
31b619c5
SH		 232 ecmd->advertising = supported;
233 skge->duplex = -1;
234 skge->speed = -1;
baef58b1 235 } else {
31b619c5
SH		 236 u32 setting;
237
2c668514 238 switch (ecmd->speed) {
baef58b1 239 case SPEED_1000:
31b619c5
SH		 240 if (ecmd->duplex == DUPLEX_FULL)
241 setting = SUPPORTED_1000baseT_Full;
242 else if (ecmd->duplex == DUPLEX_HALF)
243 setting = SUPPORTED_1000baseT_Half;
244 else
245 return -EINVAL;
baef58b1
SH		 246 break;
247 case SPEED_100:
31b619c5
SH		 248 if (ecmd->duplex == DUPLEX_FULL)
249 setting = SUPPORTED_100baseT_Full;
250 else if (ecmd->duplex == DUPLEX_HALF)
251 setting = SUPPORTED_100baseT_Half;
252 else
253 return -EINVAL;
254 break;
255
baef58b1 256 case SPEED_10:
31b619c5
SH		 257 if (ecmd->duplex == DUPLEX_FULL)
258 setting = SUPPORTED_10baseT_Full;
259 else if (ecmd->duplex == DUPLEX_HALF)
260 setting = SUPPORTED_10baseT_Half;
261 else
baef58b1
SH		 262 return -EINVAL;
263 break;
264 default:
265 return -EINVAL;
266 }
31b619c5
SH		 267
268 if ((setting & supported) == 0)
269 return -EINVAL;
270
271 skge->speed = ecmd->speed;
272 skge->duplex = ecmd->duplex;
baef58b1
SH		 273 }
274
275 skge->autoneg = ecmd->autoneg;
baef58b1
SH		 276 skge->advertising = ecmd->advertising;
277
ee294dcd
SH		 278 if (netif_running(dev))
279 skge_phy_reset(skge);
280
baef58b1
SH		 281 return (0);
282}
283
284static void skge_get_drvinfo(struct net_device *dev,
285 struct ethtool_drvinfo *info)
286{
287 struct skge_port *skge = netdev_priv(dev);
288
289 strcpy(info->driver, DRV_NAME);
290 strcpy(info->version, DRV_VERSION);
291 strcpy(info->fw_version, "N/A");
292 strcpy(info->bus_info, pci_name(skge->hw->pdev));
293}
294
295static const struct skge_stat {
296 char name[ETH_GSTRING_LEN];
297 u16 xmac_offset;
298 u16 gma_offset;
299} skge_stats[] = {
300 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
301 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
302
303 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
304 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
305 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
306 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
307 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
308 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
309 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
310 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
311
312 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
313 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
314 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
315 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
316 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
317 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
318
319 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
320 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
321 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
322 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
323 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
324};
325
326static int skge_get_stats_count(struct net_device *dev)
327{
328 return ARRAY_SIZE(skge_stats);
329}
330
331static void skge_get_ethtool_stats(struct net_device *dev,
332 struct ethtool_stats *stats, u64 *data)
333{
334 struct skge_port *skge = netdev_priv(dev);
335
336 if (skge->hw->chip_id == CHIP_ID_GENESIS)
337 genesis_get_stats(skge, data);
338 else
339 yukon_get_stats(skge, data);
340}
341
342/* Use hardware MIB variables for critical path statistics and
343 * transmit feedback not reported at interrupt.
344 * Other errors are accounted for in interrupt handler.
345 */
346static struct net_device_stats *skge_get_stats(struct net_device *dev)
347{
348 struct skge_port *skge = netdev_priv(dev);
349 u64 data[ARRAY_SIZE(skge_stats)];
350
351 if (skge->hw->chip_id == CHIP_ID_GENESIS)
352 genesis_get_stats(skge, data);
353 else
354 yukon_get_stats(skge, data);
355
356 skge->net_stats.tx_bytes = data[0];
357 skge->net_stats.rx_bytes = data[1];
358 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
359 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
360 skge->net_stats.multicast = data[5] + data[7];
361 skge->net_stats.collisions = data[10];
362 skge->net_stats.tx_aborted_errors = data[12];
363
364 return &skge->net_stats;
365}
366
367static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
368{
369 int i;
370
95566065 371 switch (stringset) {
baef58b1
SH		 372 case ETH_SS_STATS:
373 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
374 memcpy(data + i * ETH_GSTRING_LEN,
375 skge_stats[i].name, ETH_GSTRING_LEN);
376 break;
377 }
378}
379
380static void skge_get_ring_param(struct net_device *dev,
381 struct ethtool_ringparam *p)
382{
383 struct skge_port *skge = netdev_priv(dev);
384
385 p->rx_max_pending = MAX_RX_RING_SIZE;
386 p->tx_max_pending = MAX_TX_RING_SIZE;
387 p->rx_mini_max_pending = 0;
388 p->rx_jumbo_max_pending = 0;
389
390 p->rx_pending = skge->rx_ring.count;
391 p->tx_pending = skge->tx_ring.count;
392 p->rx_mini_pending = 0;
393 p->rx_jumbo_pending = 0;
394}
395
396static int skge_set_ring_param(struct net_device *dev,
397 struct ethtool_ringparam *p)
398{
399 struct skge_port *skge = netdev_priv(dev);
400
401 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
402 p->tx_pending == 0 || p->tx_pending > MAX_TX_RING_SIZE)
403 return -EINVAL;
404
405 skge->rx_ring.count = p->rx_pending;
406 skge->tx_ring.count = p->tx_pending;
407
408 if (netif_running(dev)) {
409 skge_down(dev);
410 skge_up(dev);
411 }
412
413 return 0;
414}
415
416static u32 skge_get_msglevel(struct net_device *netdev)
417{
418 struct skge_port *skge = netdev_priv(netdev);
419 return skge->msg_enable;
420}
421
422static void skge_set_msglevel(struct net_device *netdev, u32 value)
423{
424 struct skge_port *skge = netdev_priv(netdev);
425 skge->msg_enable = value;
426}
427
428static int skge_nway_reset(struct net_device *dev)
429{
430 struct skge_port *skge = netdev_priv(dev);
baef58b1
SH		 431
432 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
433 return -EINVAL;
434
ee294dcd 435 skge_phy_reset(skge);
baef58b1
SH		 436 return 0;
437}
438
439static int skge_set_sg(struct net_device *dev, u32 data)
440{
441 struct skge_port *skge = netdev_priv(dev);
442 struct skge_hw *hw = skge->hw;
443
444 if (hw->chip_id == CHIP_ID_GENESIS && data)
445 return -EOPNOTSUPP;
446 return ethtool_op_set_sg(dev, data);
447}
448
449static int skge_set_tx_csum(struct net_device *dev, u32 data)
450{
451 struct skge_port *skge = netdev_priv(dev);
452 struct skge_hw *hw = skge->hw;
453
454 if (hw->chip_id == CHIP_ID_GENESIS && data)
455 return -EOPNOTSUPP;
456
457 return ethtool_op_set_tx_csum(dev, data);
458}
459
460static u32 skge_get_rx_csum(struct net_device *dev)
461{
462 struct skge_port *skge = netdev_priv(dev);
463
464 return skge->rx_csum;
465}
466
467/* Only Yukon supports checksum offload. */
468static int skge_set_rx_csum(struct net_device *dev, u32 data)
469{
470 struct skge_port *skge = netdev_priv(dev);
471
472 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
473 return -EOPNOTSUPP;
474
475 skge->rx_csum = data;
476 return 0;
477}
478
baef58b1
SH		 479static void skge_get_pauseparam(struct net_device *dev,
480 struct ethtool_pauseparam *ecmd)
481{
482 struct skge_port *skge = netdev_priv(dev);
483
484 ecmd->tx_pause = (skge->flow_control == FLOW_MODE_LOC_SEND)
485 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
486 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_REM_SEND)
487 || (skge->flow_control == FLOW_MODE_SYMMETRIC);
488
489 ecmd->autoneg = skge->autoneg;
490}
491
492static int skge_set_pauseparam(struct net_device *dev,
493 struct ethtool_pauseparam *ecmd)
494{
495 struct skge_port *skge = netdev_priv(dev);
496
497 skge->autoneg = ecmd->autoneg;
498 if (ecmd->rx_pause && ecmd->tx_pause)
499 skge->flow_control = FLOW_MODE_SYMMETRIC;
95566065 500 else if (ecmd->rx_pause && !ecmd->tx_pause)
baef58b1 501 skge->flow_control = FLOW_MODE_REM_SEND;
95566065 502 else if (!ecmd->rx_pause && ecmd->tx_pause)
baef58b1
SH		 503 skge->flow_control = FLOW_MODE_LOC_SEND;
504 else
505 skge->flow_control = FLOW_MODE_NONE;
506
507 if (netif_running(dev)) {
508 skge_down(dev);
509 skge_up(dev);
510 }
511 return 0;
512}
513
514/* Chip internal frequency for clock calculations */
515static inline u32 hwkhz(const struct skge_hw *hw)
516{
517 if (hw->chip_id == CHIP_ID_GENESIS)
518 return 53215; /* or: 53.125 MHz */
baef58b1
SH		 519 else
520 return 78215; /* or: 78.125 MHz */
521}
522
8f3f8193 523/* Chip HZ to microseconds */
baef58b1
SH		 524static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
525{
526 return (ticks * 1000) / hwkhz(hw);
527}
528
8f3f8193 529/* Microseconds to chip HZ */
baef58b1
SH		 530static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
531{
532 return hwkhz(hw) * usec / 1000;
533}
534
535static int skge_get_coalesce(struct net_device *dev,
536 struct ethtool_coalesce *ecmd)
537{
538 struct skge_port *skge = netdev_priv(dev);
539 struct skge_hw *hw = skge->hw;
540 int port = skge->port;
541
542 ecmd->rx_coalesce_usecs = 0;
543 ecmd->tx_coalesce_usecs = 0;
544
545 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
546 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
547 u32 msk = skge_read32(hw, B2_IRQM_MSK);
548
549 if (msk & rxirqmask[port])
550 ecmd->rx_coalesce_usecs = delay;
551 if (msk & txirqmask[port])
552 ecmd->tx_coalesce_usecs = delay;
553 }
554
555 return 0;
556}
557
558/* Note: interrupt timer is per board, but can turn on/off per port */
559static int skge_set_coalesce(struct net_device *dev,
560 struct ethtool_coalesce *ecmd)
561{
562 struct skge_port *skge = netdev_priv(dev);
563 struct skge_hw *hw = skge->hw;
564 int port = skge->port;
565 u32 msk = skge_read32(hw, B2_IRQM_MSK);
566 u32 delay = 25;
567
568 if (ecmd->rx_coalesce_usecs == 0)
569 msk &= ~rxirqmask[port];
570 else if (ecmd->rx_coalesce_usecs < 25 ||
571 ecmd->rx_coalesce_usecs > 33333)
572 return -EINVAL;
573 else {
574 msk |= rxirqmask[port];
575 delay = ecmd->rx_coalesce_usecs;
576 }
577
578 if (ecmd->tx_coalesce_usecs == 0)
579 msk &= ~txirqmask[port];
580 else if (ecmd->tx_coalesce_usecs < 25 ||
581 ecmd->tx_coalesce_usecs > 33333)
582 return -EINVAL;
583 else {
584 msk |= txirqmask[port];
585 delay = min(delay, ecmd->rx_coalesce_usecs);
586 }
587
588 skge_write32(hw, B2_IRQM_MSK, msk);
589 if (msk == 0)
590 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
591 else {
592 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
593 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
594 }
595 return 0;
596}
597
6abebb53
SH		 598enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
599static void skge_led(struct skge_port *skge, enum led_mode mode)
baef58b1 600{
6abebb53
SH		 601 struct skge_hw *hw = skge->hw;
602 int port = skge->port;
603
604 spin_lock_bh(&hw->phy_lock);
baef58b1 605 if (hw->chip_id == CHIP_ID_GENESIS) {
6abebb53
SH		 606 switch (mode) {
607 case LED_MODE_OFF:
608 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
609 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
610 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
611 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
612 break;
baef58b1 613
6abebb53
SH		 614 case LED_MODE_ON:
615 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
616 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
baef58b1 617
6abebb53
SH		 618 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
619 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
baef58b1 620
6abebb53 621 break;
baef58b1 622
6abebb53
SH		 623 case LED_MODE_TST:
624 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
625 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
626 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
baef58b1 627
6abebb53
SH		 628 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
629 break;
630 }
baef58b1 631 } else {
6abebb53
SH		 632 switch (mode) {
633 case LED_MODE_OFF:
634 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
635 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
636 PHY_M_LED_MO_DUP(MO_LED_OFF) |
637 PHY_M_LED_MO_10(MO_LED_OFF) |
638 PHY_M_LED_MO_100(MO_LED_OFF) |
639 PHY_M_LED_MO_1000(MO_LED_OFF) |
640 PHY_M_LED_MO_RX(MO_LED_OFF));
641 break;
642 case LED_MODE_ON:
643 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
644 PHY_M_LED_PULS_DUR(PULS_170MS) |
645 PHY_M_LED_BLINK_RT(BLINK_84MS) |
646 PHY_M_LEDC_TX_CTRL |
647 PHY_M_LEDC_DP_CTRL);
46a60f2d 648
6abebb53
SH		 649 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
650 PHY_M_LED_MO_RX(MO_LED_OFF) |
651 (skge->speed == SPEED_100 ?
652 PHY_M_LED_MO_100(MO_LED_ON) : 0));
653 break;
654 case LED_MODE_TST:
655 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
656 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
657 PHY_M_LED_MO_DUP(MO_LED_ON) |
658 PHY_M_LED_MO_10(MO_LED_ON) |
659 PHY_M_LED_MO_100(MO_LED_ON) |
660 PHY_M_LED_MO_1000(MO_LED_ON) |
661 PHY_M_LED_MO_RX(MO_LED_ON));
662 }
baef58b1 663 }
4ff6ac05 664 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 665}
666
667/* blink LED's for finding board */
668static int skge_phys_id(struct net_device *dev, u32 data)
669{
670 struct skge_port *skge = netdev_priv(dev);
6abebb53
SH		 671 unsigned long ms;
672 enum led_mode mode = LED_MODE_TST;
baef58b1 673
95566065 674 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
6abebb53
SH		 675 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
676 else
677 ms = data * 1000;
baef58b1 678
6abebb53
SH		 679 while (ms > 0) {
680 skge_led(skge, mode);
681 mode ^= LED_MODE_TST;
baef58b1 682
6abebb53
SH		 683 if (msleep_interruptible(BLINK_MS))
684 break;
685 ms -= BLINK_MS;
686 }
baef58b1 687
6abebb53
SH		 688 /* back to regular LED state */
689 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
baef58b1
SH		 690
691 return 0;
692}
693
694static struct ethtool_ops skge_ethtool_ops = {
695 .get_settings = skge_get_settings,
696 .set_settings = skge_set_settings,
697 .get_drvinfo = skge_get_drvinfo,
698 .get_regs_len = skge_get_regs_len,
699 .get_regs = skge_get_regs,
700 .get_wol = skge_get_wol,
701 .set_wol = skge_set_wol,
702 .get_msglevel = skge_get_msglevel,
703 .set_msglevel = skge_set_msglevel,
704 .nway_reset = skge_nway_reset,
705 .get_link = ethtool_op_get_link,
706 .get_ringparam = skge_get_ring_param,
707 .set_ringparam = skge_set_ring_param,
708 .get_pauseparam = skge_get_pauseparam,
709 .set_pauseparam = skge_set_pauseparam,
710 .get_coalesce = skge_get_coalesce,
711 .set_coalesce = skge_set_coalesce,
baef58b1
SH		 712 .get_sg = ethtool_op_get_sg,
713 .set_sg = skge_set_sg,
714 .get_tx_csum = ethtool_op_get_tx_csum,
715 .set_tx_csum = skge_set_tx_csum,
716 .get_rx_csum = skge_get_rx_csum,
717 .set_rx_csum = skge_set_rx_csum,
718 .get_strings = skge_get_strings,
719 .phys_id = skge_phys_id,
720 .get_stats_count = skge_get_stats_count,
721 .get_ethtool_stats = skge_get_ethtool_stats,
56230d53 722 .get_perm_addr = ethtool_op_get_perm_addr,
baef58b1
SH		 723};
724
725/*
726 * Allocate ring elements and chain them together
727 * One-to-one association of board descriptors with ring elements
728 */
729static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u64 base)
730{
731 struct skge_tx_desc *d;
732 struct skge_element *e;
733 int i;
734
735 ring->start = kmalloc(sizeof(*e)*ring->count, GFP_KERNEL);
736 if (!ring->start)
737 return -ENOMEM;
738
739 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
740 e->desc = d;
19a33d4e 741 e->skb = NULL;
baef58b1
SH		 742 if (i == ring->count - 1) {
743 e->next = ring->start;
744 d->next_offset = base;
745 } else {
746 e->next = e + 1;
747 d->next_offset = base + (i+1) * sizeof(*d);
748 }
749 }
750 ring->to_use = ring->to_clean = ring->start;
751
752 return 0;
753}
754
19a33d4e
SH		 755/* Allocate and setup a new buffer for receiving */
756static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
757 struct sk_buff *skb, unsigned int bufsize)
758{
759 struct skge_rx_desc *rd = e->desc;
760 u64 map;
baef58b1
SH		 761
762 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
763 PCI_DMA_FROMDEVICE);
764
765 rd->dma_lo = map;
766 rd->dma_hi = map >> 32;
767 e->skb = skb;
768 rd->csum1_start = ETH_HLEN;
769 rd->csum2_start = ETH_HLEN;
770 rd->csum1 = 0;
771 rd->csum2 = 0;
772
773 wmb();
774
775 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
776 pci_unmap_addr_set(e, mapaddr, map);
777 pci_unmap_len_set(e, maplen, bufsize);
baef58b1
SH		 778}
779
19a33d4e
SH		 780/* Resume receiving using existing skb,
781 * Note: DMA address is not changed by chip.
782 * MTU not changed while receiver active.
783 */
784static void skge_rx_reuse(struct skge_element *e, unsigned int size)
785{
786 struct skge_rx_desc *rd = e->desc;
787
788 rd->csum2 = 0;
789 rd->csum2_start = ETH_HLEN;
790
791 wmb();
792
793 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
794}
795
796
797/* Free all buffers in receive ring, assumes receiver stopped */
baef58b1
SH		 798static void skge_rx_clean(struct skge_port *skge)
799{
800 struct skge_hw *hw = skge->hw;
801 struct skge_ring *ring = &skge->rx_ring;
802 struct skge_element *e;
803
19a33d4e
SH		 804 e = ring->start;
805 do {
baef58b1
SH		 806 struct skge_rx_desc *rd = e->desc;
807 rd->control = 0;
19a33d4e
SH		 808 if (e->skb) {
809 pci_unmap_single(hw->pdev,
810 pci_unmap_addr(e, mapaddr),
811 pci_unmap_len(e, maplen),
812 PCI_DMA_FROMDEVICE);
813 dev_kfree_skb(e->skb);
814 e->skb = NULL;
815 }
816 } while ((e = e->next) != ring->start);
baef58b1
SH		 817}
818
19a33d4e 819
baef58b1 820/* Allocate buffers for receive ring
19a33d4e 821 * For receive: to_clean is next received frame.
baef58b1
SH		 822 */
823static int skge_rx_fill(struct skge_port *skge)
824{
825 struct skge_ring *ring = &skge->rx_ring;
826 struct skge_element *e;
baef58b1 827
19a33d4e
SH		 828 e = ring->start;
829 do {
383181ac 830 struct sk_buff *skb;
baef58b1 831
383181ac 832 skb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
19a33d4e
SH		 833 if (!skb)
834 return -ENOMEM;
835
383181ac
SH		 836 skb_reserve(skb, NET_IP_ALIGN);
837 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
19a33d4e 838 } while ( (e = e->next) != ring->start);
baef58b1 839
19a33d4e
SH		 840 ring->to_clean = ring->start;
841 return 0;
baef58b1
SH		 842}
843
844static void skge_link_up(struct skge_port *skge)
845{
46a60f2d 846 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
54cfb5aa
SH		 847 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
848
baef58b1
SH		 849 netif_carrier_on(skge->netdev);
850 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
851 netif_wake_queue(skge->netdev);
852
853 if (netif_msg_link(skge))
854 printk(KERN_INFO PFX
855 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
856 skge->netdev->name, skge->speed,
857 skge->duplex == DUPLEX_FULL ? "full" : "half",
858 (skge->flow_control == FLOW_MODE_NONE) ? "none" :
859 (skge->flow_control == FLOW_MODE_LOC_SEND) ? "tx only" :
860 (skge->flow_control == FLOW_MODE_REM_SEND) ? "rx only" :
861 (skge->flow_control == FLOW_MODE_SYMMETRIC) ? "tx and rx" :
862 "unknown");
863}
864
865static void skge_link_down(struct skge_port *skge)
866{
54cfb5aa 867 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
baef58b1
SH		 868 netif_carrier_off(skge->netdev);
869 netif_stop_queue(skge->netdev);
870
871 if (netif_msg_link(skge))
872 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
873}
874
2cd8e5d3 875static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
baef58b1
SH		 876{
877 int i;
baef58b1 878
6b0c1480 879 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
2cd8e5d3 880 xm_read16(hw, port, XM_PHY_DATA);
baef58b1 881
89bf5f23
SH		 882 /* Need to wait for external PHY */
883 for (i = 0; i < PHY_RETRIES; i++) {
884 udelay(1);
2cd8e5d3 885 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
89bf5f23 886 goto ready;
baef58b1
SH		 887 }
888
2cd8e5d3 889 return -ETIMEDOUT;
89bf5f23 890 ready:
2cd8e5d3 891 *val = xm_read16(hw, port, XM_PHY_DATA);
89bf5f23 892
2cd8e5d3
SH		 893 return 0;
894}
895
896static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
897{
898 u16 v = 0;
899 if (__xm_phy_read(hw, port, reg, &v))
900 printk(KERN_WARNING PFX "%s: phy read timed out\n",
901 hw->dev[port]->name);
baef58b1
SH		 902 return v;
903}
904
2cd8e5d3 905static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
baef58b1
SH		 906{
907 int i;
908
6b0c1480 909 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
baef58b1 910 for (i = 0; i < PHY_RETRIES; i++) {
6b0c1480 911 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
baef58b1 912 goto ready;
89bf5f23 913 udelay(1);
baef58b1 914 }
2cd8e5d3 915 return -EIO;
baef58b1
SH		 916
917 ready:
6b0c1480 918 xm_write16(hw, port, XM_PHY_DATA, val);
2cd8e5d3 919 return 0;
baef58b1
SH		 920}
921
922static void genesis_init(struct skge_hw *hw)
923{
924 /* set blink source counter */
925 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
926 skge_write8(hw, B2_BSC_CTRL, BSC_START);
927
928 /* configure mac arbiter */
929 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
930
931 /* configure mac arbiter timeout values */
932 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
933 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
934 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
935 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
936
937 skge_write8(hw, B3_MA_RCINI_RX1, 0);
938 skge_write8(hw, B3_MA_RCINI_RX2, 0);
939 skge_write8(hw, B3_MA_RCINI_TX1, 0);
940 skge_write8(hw, B3_MA_RCINI_TX2, 0);
941
942 /* configure packet arbiter timeout */
943 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
944 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
945 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
946 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
947 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
948}
949
950static void genesis_reset(struct skge_hw *hw, int port)
951{
45bada65 952 const u8 zero[8] = { 0 };
baef58b1 953
46a60f2d
SH		 954 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
955
baef58b1 956 /* reset the statistics module */
6b0c1480
SH		 957 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
958 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
959 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
960 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
961 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
baef58b1 962
89bf5f23
SH		 963 /* disable Broadcom PHY IRQ */
964 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
baef58b1 965
45bada65 966 xm_outhash(hw, port, XM_HSM, zero);
baef58b1
SH		 967}
968
969
45bada65
SH		 970/* Convert mode to MII values */
971static const u16 phy_pause_map[] = {
972 [FLOW_MODE_NONE] = 0,
973 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
974 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
975 [FLOW_MODE_REM_SEND] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
976};
977
978
979/* Check status of Broadcom phy link */
980static void bcom_check_link(struct skge_hw *hw, int port)
baef58b1 981{
45bada65
SH		 982 struct net_device *dev = hw->dev[port];
983 struct skge_port *skge = netdev_priv(dev);
984 u16 status;
985
986 /* read twice because of latch */
987 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
988 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
989
45bada65
SH		 990 if ((status & PHY_ST_LSYNC) == 0) {
991 u16 cmd = xm_read16(hw, port, XM_MMU_CMD);
992 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
993 xm_write16(hw, port, XM_MMU_CMD, cmd);
994 /* dummy read to ensure writing */
995 (void) xm_read16(hw, port, XM_MMU_CMD);
996
997 if (netif_carrier_ok(dev))
998 skge_link_down(skge);
999 } else {
1000 if (skge->autoneg == AUTONEG_ENABLE &&
1001 (status & PHY_ST_AN_OVER)) {
1002 u16 lpa = xm_phy_read(hw, port, PHY_BCOM_AUNE_LP);
1003 u16 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1004
1005 if (lpa & PHY_B_AN_RF) {
1006 printk(KERN_NOTICE PFX "%s: remote fault\n",
1007 dev->name);
1008 return;
1009 }
1010
1011 /* Check Duplex mismatch */
2c668514 1012 switch (aux & PHY_B_AS_AN_RES_MSK) {
45bada65
SH		 1013 case PHY_B_RES_1000FD:
1014 skge->duplex = DUPLEX_FULL;
1015 break;
1016 case PHY_B_RES_1000HD:
1017 skge->duplex = DUPLEX_HALF;
1018 break;
1019 default:
1020 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1021 dev->name);
1022 return;
1023 }
1024
1025
1026 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1027 switch (aux & PHY_B_AS_PAUSE_MSK) {
1028 case PHY_B_AS_PAUSE_MSK:
1029 skge->flow_control = FLOW_MODE_SYMMETRIC;
1030 break;
1031 case PHY_B_AS_PRR:
1032 skge->flow_control = FLOW_MODE_REM_SEND;
1033 break;
1034 case PHY_B_AS_PRT:
1035 skge->flow_control = FLOW_MODE_LOC_SEND;
1036 break;
1037 default:
1038 skge->flow_control = FLOW_MODE_NONE;
1039 }
1040
1041 skge->speed = SPEED_1000;
1042 }
1043
1044 if (!netif_carrier_ok(dev))
1045 genesis_link_up(skge);
1046 }
1047}
1048
1049/* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1050 * Phy on for 100 or 10Mbit operation
1051 */
1052static void bcom_phy_init(struct skge_port *skge, int jumbo)
1053{
1054 struct skge_hw *hw = skge->hw;
1055 int port = skge->port;
baef58b1 1056 int i;
45bada65 1057 u16 id1, r, ext, ctl;
baef58b1
SH		 1058
1059 /* magic workaround patterns for Broadcom */
1060 static const struct {
1061 u16 reg;
1062 u16 val;
1063 } A1hack[] = {
1064 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1065 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1066 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1067 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1068 }, C0hack[] = {
1069 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1070 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1071 };
1072
45bada65
SH		 1073 /* read Id from external PHY (all have the same address) */
1074 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1075
1076 /* Optimize MDIO transfer by suppressing preamble. */
1077 r = xm_read16(hw, port, XM_MMU_CMD);
1078 r |= XM_MMU_NO_PRE;
1079 xm_write16(hw, port, XM_MMU_CMD,r);
1080
2c668514 1081 switch (id1) {
45bada65
SH		 1082 case PHY_BCOM_ID1_C0:
1083 /*
1084 * Workaround BCOM Errata for the C0 type.
1085 * Write magic patterns to reserved registers.
1086 */
1087 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1088 xm_phy_write(hw, port,
1089 C0hack[i].reg, C0hack[i].val);
1090
1091 break;
1092 case PHY_BCOM_ID1_A1:
1093 /*
1094 * Workaround BCOM Errata for the A1 type.
1095 * Write magic patterns to reserved registers.
1096 */
1097 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1098 xm_phy_write(hw, port,
1099 A1hack[i].reg, A1hack[i].val);
1100 break;
1101 }
1102
1103 /*
1104 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1105 * Disable Power Management after reset.
1106 */
1107 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1108 r |= PHY_B_AC_DIS_PM;
1109 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1110
1111 /* Dummy read */
1112 xm_read16(hw, port, XM_ISRC);
1113
1114 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1115 ctl = PHY_CT_SP1000; /* always 1000mbit */
1116
1117 if (skge->autoneg == AUTONEG_ENABLE) {
1118 /*
1119 * Workaround BCOM Errata #1 for the C5 type.
1120 * 1000Base-T Link Acquisition Failure in Slave Mode
1121 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1122 */
1123 u16 adv = PHY_B_1000C_RD;
1124 if (skge->advertising & ADVERTISED_1000baseT_Half)
1125 adv |= PHY_B_1000C_AHD;
1126 if (skge->advertising & ADVERTISED_1000baseT_Full)
1127 adv |= PHY_B_1000C_AFD;
1128 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1129
1130 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1131 } else {
1132 if (skge->duplex == DUPLEX_FULL)
1133 ctl |= PHY_CT_DUP_MD;
1134 /* Force to slave */
1135 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1136 }
1137
1138 /* Set autonegotiation pause parameters */
1139 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1140 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1141
1142 /* Handle Jumbo frames */
1143 if (jumbo) {
1144 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1145 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1146
1147 ext |= PHY_B_PEC_HIGH_LA;
1148
1149 }
1150
1151 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1152 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1153
8f3f8193 1154 /* Use link status change interrupt */
45bada65
SH		 1155 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1156
1157 bcom_check_link(hw, port);
1158}
1159
1160static void genesis_mac_init(struct skge_hw *hw, int port)
1161{
1162 struct net_device *dev = hw->dev[port];
1163 struct skge_port *skge = netdev_priv(dev);
1164 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1165 int i;
1166 u32 r;
1167 const u8 zero[6] = { 0 };
1168
1169 /* Clear MIB counters */
1170 xm_write16(hw, port, XM_STAT_CMD,
1171 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1172 /* Clear two times according to Errata #3 */
1173 xm_write16(hw, port, XM_STAT_CMD,
1174 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
baef58b1 1175
baef58b1 1176 /* Unreset the XMAC. */
6b0c1480 1177 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
baef58b1
SH		 1178
1179 /*
1180 * Perform additional initialization for external PHYs,
1181 * namely for the 1000baseTX cards that use the XMAC's
1182 * GMII mode.
1183 */
45bada65 1184 /* Take external Phy out of reset */
89bf5f23
SH		 1185 r = skge_read32(hw, B2_GP_IO);
1186 if (port == 0)
1187 r |= GP_DIR_0|GP_IO_0;
1188 else
1189 r |= GP_DIR_2|GP_IO_2;
1190
1191 skge_write32(hw, B2_GP_IO, r);
1192 skge_read32(hw, B2_GP_IO);
1193
8f3f8193 1194 /* Enable GMII interface */
89bf5f23
SH		 1195 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1196
45bada65 1197 bcom_phy_init(skge, jumbo);
89bf5f23 1198
45bada65
SH		 1199 /* Set Station Address */
1200 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
89bf5f23 1201
45bada65
SH		 1202 /* We don't use match addresses so clear */
1203 for (i = 1; i < 16; i++)
1204 xm_outaddr(hw, port, XM_EXM(i), zero);
1205
1206 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1207 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1208
1209 /* We don't need the FCS appended to the packet. */
1210 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1211 if (jumbo)
1212 r |= XM_RX_BIG_PK_OK;
89bf5f23 1213
45bada65 1214 if (skge->duplex == DUPLEX_HALF) {
89bf5f23 1215 /*
45bada65
SH		 1216 * If in manual half duplex mode the other side might be in
1217 * full duplex mode, so ignore if a carrier extension is not seen
1218 * on frames received
89bf5f23 1219 */
45bada65 1220 r |= XM_RX_DIS_CEXT;
baef58b1 1221 }
45bada65 1222 xm_write16(hw, port, XM_RX_CMD, r);
baef58b1 1223
baef58b1
SH		 1224
1225 /* We want short frames padded to 60 bytes. */
45bada65
SH		 1226 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1227
1228 /*
1229 * Bump up the transmit threshold. This helps hold off transmit
1230 * underruns when we're blasting traffic from both ports at once.
1231 */
1232 xm_write16(hw, port, XM_TX_THR, 512);
baef58b1
SH		 1233
1234 /*
1235 * Enable the reception of all error frames. This is is
1236 * a necessary evil due to the design of the XMAC. The
1237 * XMAC's receive FIFO is only 8K in size, however jumbo
1238 * frames can be up to 9000 bytes in length. When bad
1239 * frame filtering is enabled, the XMAC's RX FIFO operates
1240 * in 'store and forward' mode. For this to work, the
1241 * entire frame has to fit into the FIFO, but that means
1242 * that jumbo frames larger than 8192 bytes will be
1243 * truncated. Disabling all bad frame filtering causes
1244 * the RX FIFO to operate in streaming mode, in which
8f3f8193 1245 * case the XMAC will start transferring frames out of the
baef58b1
SH		 1246 * RX FIFO as soon as the FIFO threshold is reached.
1247 */
45bada65 1248 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
baef58b1 1249
baef58b1
SH		 1250
1251 /*
45bada65
SH		 1252 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1253 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1254 * and 'Octets Rx OK Hi Cnt Ov'.
baef58b1 1255 */
45bada65
SH		 1256 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1257
1258 /*
1259 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1260 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1261 * and 'Octets Tx OK Hi Cnt Ov'.
1262 */
1263 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
baef58b1
SH		 1264
1265 /* Configure MAC arbiter */
1266 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1267
1268 /* configure timeout values */
1269 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1270 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1271 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1272 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1273
1274 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1275 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1276 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1277 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1278
1279 /* Configure Rx MAC FIFO */
6b0c1480
SH		 1280 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1281 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1282 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1
SH		 1283
1284 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1285 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1286 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1287 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
baef58b1 1288
45bada65 1289 if (jumbo) {
baef58b1 1290 /* Enable frame flushing if jumbo frames used */
6b0c1480 1291 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
baef58b1
SH		 1292 } else {
1293 /* enable timeout timers if normal frames */
1294 skge_write16(hw, B3_PA_CTRL,
45bada65 1295 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
baef58b1 1296 }
baef58b1
SH		 1297}
1298
1299static void genesis_stop(struct skge_port *skge)
1300{
1301 struct skge_hw *hw = skge->hw;
1302 int port = skge->port;
89bf5f23 1303 u32 reg;
baef58b1 1304
46a60f2d
SH		 1305 genesis_reset(hw, port);
1306
baef58b1
SH		 1307 /* Clear Tx packet arbiter timeout IRQ */
1308 skge_write16(hw, B3_PA_CTRL,
1309 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1310
1311 /*
8f3f8193 1312 * If the transfer sticks at the MAC the STOP command will not
baef58b1
SH		 1313 * terminate if we don't flush the XMAC's transmit FIFO !
1314 */
6b0c1480
SH		 1315 xm_write32(hw, port, XM_MODE,
1316 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
baef58b1
SH		 1317
1318
1319 /* Reset the MAC */
6b0c1480 1320 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
baef58b1
SH		 1321
1322 /* For external PHYs there must be special handling */
89bf5f23
SH		 1323 reg = skge_read32(hw, B2_GP_IO);
1324 if (port == 0) {
1325 reg |= GP_DIR_0;
1326 reg &= ~GP_IO_0;
1327 } else {
1328 reg |= GP_DIR_2;
1329 reg &= ~GP_IO_2;
baef58b1 1330 }
89bf5f23
SH		 1331 skge_write32(hw, B2_GP_IO, reg);
1332 skge_read32(hw, B2_GP_IO);
baef58b1 1333
6b0c1480
SH		 1334 xm_write16(hw, port, XM_MMU_CMD,
1335 xm_read16(hw, port, XM_MMU_CMD)
baef58b1
SH		 1336 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1337
6b0c1480 1338 xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1339}
1340
1341
1342static void genesis_get_stats(struct skge_port *skge, u64 *data)
1343{
1344 struct skge_hw *hw = skge->hw;
1345 int port = skge->port;
1346 int i;
1347 unsigned long timeout = jiffies + HZ;
1348
6b0c1480 1349 xm_write16(hw, port,
baef58b1
SH		 1350 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1351
1352 /* wait for update to complete */
6b0c1480 1353 while (xm_read16(hw, port, XM_STAT_CMD)
baef58b1
SH		 1354 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1355 if (time_after(jiffies, timeout))
1356 break;
1357 udelay(10);
1358 }
1359
1360 /* special case for 64 bit octet counter */
6b0c1480
SH		 1361 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1362 | xm_read32(hw, port, XM_TXO_OK_LO);
1363 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1364 | xm_read32(hw, port, XM_RXO_OK_LO);
baef58b1
SH		 1365
1366 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1367 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
baef58b1
SH		 1368}
1369
1370static void genesis_mac_intr(struct skge_hw *hw, int port)
1371{
1372 struct skge_port *skge = netdev_priv(hw->dev[port]);
6b0c1480 1373 u16 status = xm_read16(hw, port, XM_ISRC);
baef58b1 1374
7e676d91
SH		 1375 if (netif_msg_intr(skge))
1376 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1377 skge->netdev->name, status);
baef58b1
SH		 1378
1379 if (status & XM_IS_TXF_UR) {
6b0c1480 1380 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
baef58b1
SH		 1381 ++skge->net_stats.tx_fifo_errors;
1382 }
1383 if (status & XM_IS_RXF_OV) {
6b0c1480 1384 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
baef58b1
SH		 1385 ++skge->net_stats.rx_fifo_errors;
1386 }
1387}
1388
baef58b1
SH		 1389static void genesis_link_up(struct skge_port *skge)
1390{
1391 struct skge_hw *hw = skge->hw;
1392 int port = skge->port;
1393 u16 cmd;
1394 u32 mode, msk;
1395
6b0c1480 1396 cmd = xm_read16(hw, port, XM_MMU_CMD);
baef58b1
SH		 1397
1398 /*
1399 * enabling pause frame reception is required for 1000BT
1400 * because the XMAC is not reset if the link is going down
1401 */
1402 if (skge->flow_control == FLOW_MODE_NONE ||
1403 skge->flow_control == FLOW_MODE_LOC_SEND)
7e676d91 1404 /* Disable Pause Frame Reception */
baef58b1
SH		 1405 cmd |= XM_MMU_IGN_PF;
1406 else
1407 /* Enable Pause Frame Reception */
1408 cmd &= ~XM_MMU_IGN_PF;
1409
6b0c1480 1410 xm_write16(hw, port, XM_MMU_CMD, cmd);
baef58b1 1411
6b0c1480 1412 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 1413 if (skge->flow_control == FLOW_MODE_SYMMETRIC ||
1414 skge->flow_control == FLOW_MODE_LOC_SEND) {
1415 /*
1416 * Configure Pause Frame Generation
1417 * Use internal and external Pause Frame Generation.
1418 * Sending pause frames is edge triggered.
1419 * Send a Pause frame with the maximum pause time if
1420 * internal oder external FIFO full condition occurs.
1421 * Send a zero pause time frame to re-start transmission.
1422 */
1423 /* XM_PAUSE_DA = '010000C28001' (default) */
1424 /* XM_MAC_PTIME = 0xffff (maximum) */
1425 /* remember this value is defined in big endian (!) */
6b0c1480 1426 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
baef58b1
SH		 1427
1428 mode |= XM_PAUSE_MODE;
6b0c1480 1429 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
baef58b1
SH		 1430 } else {
1431 /*
1432 * disable pause frame generation is required for 1000BT
1433 * because the XMAC is not reset if the link is going down
1434 */
1435 /* Disable Pause Mode in Mode Register */
1436 mode &= ~XM_PAUSE_MODE;
1437
6b0c1480 1438 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
baef58b1
SH		 1439 }
1440
6b0c1480 1441 xm_write32(hw, port, XM_MODE, mode);
baef58b1
SH		 1442
1443 msk = XM_DEF_MSK;
89bf5f23
SH		 1444 /* disable GP0 interrupt bit for external Phy */
1445 msk |= XM_IS_INP_ASS;
baef58b1 1446
6b0c1480
SH		 1447 xm_write16(hw, port, XM_IMSK, msk);
1448 xm_read16(hw, port, XM_ISRC);
baef58b1
SH		 1449
1450 /* get MMU Command Reg. */
6b0c1480 1451 cmd = xm_read16(hw, port, XM_MMU_CMD);
89bf5f23 1452 if (skge->duplex == DUPLEX_FULL)
baef58b1
SH		 1453 cmd |= XM_MMU_GMII_FD;
1454
89bf5f23
SH		 1455 /*
1456 * Workaround BCOM Errata (#10523) for all BCom Phys
1457 * Enable Power Management after link up
1458 */
1459 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1460 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1461 & ~PHY_B_AC_DIS_PM);
1462 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
baef58b1
SH		 1463
1464 /* enable Rx/Tx */
6b0c1480 1465 xm_write16(hw, port, XM_MMU_CMD,
baef58b1
SH		 1466 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1467 skge_link_up(skge);
1468}
1469
1470
45bada65 1471static inline void bcom_phy_intr(struct skge_port *skge)
baef58b1
SH		 1472{
1473 struct skge_hw *hw = skge->hw;
1474 int port = skge->port;
45bada65
SH		 1475 u16 isrc;
1476
1477 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
7e676d91
SH		 1478 if (netif_msg_intr(skge))
1479 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1480 skge->netdev->name, isrc);
baef58b1 1481
45bada65
SH		 1482 if (isrc & PHY_B_IS_PSE)
1483 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1484 hw->dev[port]->name);
baef58b1
SH		 1485
1486 /* Workaround BCom Errata:
1487 * enable and disable loopback mode if "NO HCD" occurs.
1488 */
45bada65 1489 if (isrc & PHY_B_IS_NO_HDCL) {
6b0c1480
SH		 1490 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1491 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1 1492 ctrl | PHY_CT_LOOP);
6b0c1480 1493 xm_phy_write(hw, port, PHY_BCOM_CTRL,
baef58b1
SH		 1494 ctrl & ~PHY_CT_LOOP);
1495 }
1496
45bada65
SH		 1497 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1498 bcom_check_link(hw, port);
baef58b1 1499
baef58b1
SH		 1500}
1501
2cd8e5d3
SH		 1502static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1503{
1504 int i;
1505
1506 gma_write16(hw, port, GM_SMI_DATA, val);
1507 gma_write16(hw, port, GM_SMI_CTRL,
1508 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1509 for (i = 0; i < PHY_RETRIES; i++) {
1510 udelay(1);
1511
1512 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1513 return 0;
1514 }
1515
1516 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1517 hw->dev[port]->name);
1518 return -EIO;
1519}
1520
1521static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1522{
1523 int i;
1524
1525 gma_write16(hw, port, GM_SMI_CTRL,
1526 GM_SMI_CT_PHY_AD(hw->phy_addr)
1527 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1528
1529 for (i = 0; i < PHY_RETRIES; i++) {
1530 udelay(1);
1531 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1532 goto ready;
1533 }
1534
1535 return -ETIMEDOUT;
1536 ready:
1537 *val = gma_read16(hw, port, GM_SMI_DATA);
1538 return 0;
1539}
1540
1541static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1542{
1543 u16 v = 0;
1544 if (__gm_phy_read(hw, port, reg, &v))
1545 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1546 hw->dev[port]->name);
1547 return v;
1548}
1549
8f3f8193 1550/* Marvell Phy Initialization */
baef58b1
SH		 1551static void yukon_init(struct skge_hw *hw, int port)
1552{
1553 struct skge_port *skge = netdev_priv(hw->dev[port]);
1554 u16 ctrl, ct1000, adv;
baef58b1 1555
baef58b1 1556 if (skge->autoneg == AUTONEG_ENABLE) {
6b0c1480 1557 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
baef58b1
SH		 1558
1559 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1560 PHY_M_EC_MAC_S_MSK);
1561 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1562
c506a509 1563 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
baef58b1 1564
6b0c1480 1565 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
baef58b1
SH		 1566 }
1567
6b0c1480 1568 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
baef58b1
SH		 1569 if (skge->autoneg == AUTONEG_DISABLE)
1570 ctrl &= ~PHY_CT_ANE;
1571
1572 ctrl |= PHY_CT_RESET;
6b0c1480 1573 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1
SH		 1574
1575 ctrl = 0;
1576 ct1000 = 0;
b18f2091 1577 adv = PHY_AN_CSMA;
baef58b1
SH		 1578
1579 if (skge->autoneg == AUTONEG_ENABLE) {
5e1705dd 1580 if (hw->copper) {
baef58b1
SH		 1581 if (skge->advertising & ADVERTISED_1000baseT_Full)
1582 ct1000 |= PHY_M_1000C_AFD;
1583 if (skge->advertising & ADVERTISED_1000baseT_Half)
1584 ct1000 |= PHY_M_1000C_AHD;
1585 if (skge->advertising & ADVERTISED_100baseT_Full)
1586 adv |= PHY_M_AN_100_FD;
1587 if (skge->advertising & ADVERTISED_100baseT_Half)
1588 adv |= PHY_M_AN_100_HD;
1589 if (skge->advertising & ADVERTISED_10baseT_Full)
1590 adv |= PHY_M_AN_10_FD;
1591 if (skge->advertising & ADVERTISED_10baseT_Half)
1592 adv |= PHY_M_AN_10_HD;
45bada65 1593 } else /* special defines for FIBER (88E1011S only) */
baef58b1
SH		 1594 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
1595
45bada65
SH		 1596 /* Set Flow-control capabilities */
1597 adv |= phy_pause_map[skge->flow_control];
1598
baef58b1
SH		 1599 /* Restart Auto-negotiation */
1600 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1601 } else {
1602 /* forced speed/duplex settings */
1603 ct1000 = PHY_M_1000C_MSE;
1604
1605 if (skge->duplex == DUPLEX_FULL)
1606 ctrl |= PHY_CT_DUP_MD;
1607
1608 switch (skge->speed) {
1609 case SPEED_1000:
1610 ctrl |= PHY_CT_SP1000;
1611 break;
1612 case SPEED_100:
1613 ctrl |= PHY_CT_SP100;
1614 break;
1615 }
1616
1617 ctrl |= PHY_CT_RESET;
1618 }
1619
c506a509 1620 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
baef58b1 1621
6b0c1480
SH		 1622 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1623 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
baef58b1 1624
baef58b1
SH		 1625 /* Enable phy interrupt on autonegotiation complete (or link up) */
1626 if (skge->autoneg == AUTONEG_ENABLE)
4cde06ed 1627 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
baef58b1 1628 else
4cde06ed 1629 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1630}
1631
1632static void yukon_reset(struct skge_hw *hw, int port)
1633{
6b0c1480
SH		 1634 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1635 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1636 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1637 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1638 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
baef58b1 1639
6b0c1480
SH		 1640 gma_write16(hw, port, GM_RX_CTRL,
1641 gma_read16(hw, port, GM_RX_CTRL)
baef58b1
SH		 1642 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1643}
1644
c8868611
SH		 1645/* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1646static int is_yukon_lite_a0(struct skge_hw *hw)
1647{
1648 u32 reg;
1649 int ret;
1650
1651 if (hw->chip_id != CHIP_ID_YUKON)
1652 return 0;
1653
1654 reg = skge_read32(hw, B2_FAR);
1655 skge_write8(hw, B2_FAR + 3, 0xff);
1656 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1657 skge_write32(hw, B2_FAR, reg);
1658 return ret;
1659}
1660
baef58b1
SH		 1661static void yukon_mac_init(struct skge_hw *hw, int port)
1662{
1663 struct skge_port *skge = netdev_priv(hw->dev[port]);
1664 int i;
1665 u32 reg;
1666 const u8 *addr = hw->dev[port]->dev_addr;
1667
1668 /* WA code for COMA mode -- set PHY reset */
1669 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1670 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1671 reg = skge_read32(hw, B2_GP_IO);
1672 reg |= GP_DIR_9 | GP_IO_9;
1673 skge_write32(hw, B2_GP_IO, reg);
1674 }
baef58b1
SH		 1675
1676 /* hard reset */
6b0c1480
SH		 1677 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1678 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1679
1680 /* WA code for COMA mode -- clear PHY reset */
1681 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
46a60f2d
SH		 1682 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1683 reg = skge_read32(hw, B2_GP_IO);
1684 reg |= GP_DIR_9;
1685 reg &= ~GP_IO_9;
1686 skge_write32(hw, B2_GP_IO, reg);
1687 }
baef58b1
SH		 1688
1689 /* Set hardware config mode */
1690 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
1691 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
5e1705dd 1692 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
baef58b1
SH		 1693
1694 /* Clear GMC reset */
6b0c1480
SH		 1695 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
1696 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
1697 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
baef58b1
SH		 1698 if (skge->autoneg == AUTONEG_DISABLE) {
1699 reg = GM_GPCR_AU_ALL_DIS;
6b0c1480
SH		 1700 gma_write16(hw, port, GM_GP_CTRL,
1701 gma_read16(hw, port, GM_GP_CTRL) | reg);
baef58b1
SH		 1702
1703 switch (skge->speed) {
1704 case SPEED_1000:
1705 reg |= GM_GPCR_SPEED_1000;
1706 /* fallthru */
1707 case SPEED_100:
1708 reg |= GM_GPCR_SPEED_100;
1709 }
1710
1711 if (skge->duplex == DUPLEX_FULL)
1712 reg |= GM_GPCR_DUP_FULL;
1713 } else
1714 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
1715 switch (skge->flow_control) {
1716 case FLOW_MODE_NONE:
6b0c1480 1717 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1
SH		 1718 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1719 break;
1720 case FLOW_MODE_LOC_SEND:
1721 /* disable Rx flow-control */
1722 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
1723 }
1724
6b0c1480 1725 gma_write16(hw, port, GM_GP_CTRL, reg);
46a60f2d 1726 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1727
baef58b1 1728 yukon_init(hw, port);
baef58b1
SH		 1729
1730 /* MIB clear */
6b0c1480
SH		 1731 reg = gma_read16(hw, port, GM_PHY_ADDR);
1732 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
baef58b1
SH		 1733
1734 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
6b0c1480
SH		 1735 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
1736 gma_write16(hw, port, GM_PHY_ADDR, reg);
baef58b1
SH		 1737
1738 /* transmit control */
6b0c1480 1739 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
baef58b1
SH		 1740
1741 /* receive control reg: unicast + multicast + no FCS */
6b0c1480 1742 gma_write16(hw, port, GM_RX_CTRL,
baef58b1
SH		 1743 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
1744
1745 /* transmit flow control */
6b0c1480 1746 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
baef58b1
SH		 1747
1748 /* transmit parameter */
6b0c1480 1749 gma_write16(hw, port, GM_TX_PARAM,
baef58b1
SH		 1750 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
1751 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
1752 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
1753
1754 /* serial mode register */
1755 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1756 if (hw->dev[port]->mtu > 1500)
1757 reg |= GM_SMOD_JUMBO_ENA;
1758
6b0c1480 1759 gma_write16(hw, port, GM_SERIAL_MODE, reg);
baef58b1
SH		 1760
1761 /* physical address: used for pause frames */
6b0c1480 1762 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
baef58b1 1763 /* virtual address for data */
6b0c1480 1764 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
baef58b1
SH		 1765
1766 /* enable interrupt mask for counter overflows */
6b0c1480
SH		 1767 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
1768 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
1769 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
baef58b1
SH		 1770
1771 /* Initialize Mac Fifo */
1772
1773 /* Configure Rx MAC FIFO */
6b0c1480 1774 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
baef58b1 1775 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
c8868611
SH		 1776
1777 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
1778 if (is_yukon_lite_a0(hw))
baef58b1 1779 reg &= ~GMF_RX_F_FL_ON;
c8868611 1780
6b0c1480
SH		 1781 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
1782 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
c5923081
SH		 1783 /*
1784 * because Pause Packet Truncation in GMAC is not working
1785 * we have to increase the Flush Threshold to 64 bytes
1786 * in order to flush pause packets in Rx FIFO on Yukon-1
1787 */
1788 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
baef58b1
SH		 1789
1790 /* Configure Tx MAC FIFO */
6b0c1480
SH		 1791 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
1792 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
baef58b1
SH		 1793}
1794
355ec572
SH		 1795/* Go into power down mode */
1796static void yukon_suspend(struct skge_hw *hw, int port)
1797{
1798 u16 ctrl;
1799
1800 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
1801 ctrl |= PHY_M_PC_POL_R_DIS;
1802 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
1803
1804 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1805 ctrl |= PHY_CT_RESET;
1806 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1807
1808 /* switch IEEE compatible power down mode on */
1809 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1810 ctrl |= PHY_CT_PDOWN;
1811 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1812}
1813
baef58b1
SH		 1814static void yukon_stop(struct skge_port *skge)
1815{
1816 struct skge_hw *hw = skge->hw;
1817 int port = skge->port;
1818
46a60f2d
SH		 1819 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1820 yukon_reset(hw, port);
baef58b1 1821
6b0c1480
SH		 1822 gma_write16(hw, port, GM_GP_CTRL,
1823 gma_read16(hw, port, GM_GP_CTRL)
0eedf4ac 1824 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
6b0c1480 1825 gma_read16(hw, port, GM_GP_CTRL);
baef58b1 1826
355ec572 1827 yukon_suspend(hw, port);
46a60f2d 1828
baef58b1 1829 /* set GPHY Control reset */
46a60f2d
SH		 1830 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1831 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
baef58b1
SH		 1832}
1833
1834static void yukon_get_stats(struct skge_port *skge, u64 *data)
1835{
1836 struct skge_hw *hw = skge->hw;
1837 int port = skge->port;
1838 int i;
1839
6b0c1480
SH		 1840 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
1841 | gma_read32(hw, port, GM_TXO_OK_LO);
1842 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
1843 | gma_read32(hw, port, GM_RXO_OK_LO);
baef58b1
SH		 1844
1845 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
6b0c1480 1846 data[i] = gma_read32(hw, port,
baef58b1
SH		 1847 skge_stats[i].gma_offset);
1848}
1849
1850static void yukon_mac_intr(struct skge_hw *hw, int port)
1851{
7e676d91
SH		 1852 struct net_device *dev = hw->dev[port];
1853 struct skge_port *skge = netdev_priv(dev);
6b0c1480 1854 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
baef58b1 1855
7e676d91
SH		 1856 if (netif_msg_intr(skge))
1857 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1858 dev->name, status);
1859
baef58b1
SH		 1860 if (status & GM_IS_RX_FF_OR) {
1861 ++skge->net_stats.rx_fifo_errors;
d8a09943 1862 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
baef58b1 1863 }
d8a09943 1864
baef58b1
SH		 1865 if (status & GM_IS_TX_FF_UR) {
1866 ++skge->net_stats.tx_fifo_errors;
d8a09943 1867 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
baef58b1
SH		 1868 }
1869
1870}
1871
1872static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
1873{
95566065 1874 switch (aux & PHY_M_PS_SPEED_MSK) {
baef58b1
SH		 1875 case PHY_M_PS_SPEED_1000:
1876 return SPEED_1000;
1877 case PHY_M_PS_SPEED_100:
1878 return SPEED_100;
1879 default:
1880 return SPEED_10;
1881 }
1882}
1883
1884static void yukon_link_up(struct skge_port *skge)
1885{
1886 struct skge_hw *hw = skge->hw;
1887 int port = skge->port;
1888 u16 reg;
1889
baef58b1 1890 /* Enable Transmit FIFO Underrun */
46a60f2d 1891 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
baef58b1 1892
6b0c1480 1893 reg = gma_read16(hw, port, GM_GP_CTRL);
baef58b1
SH		 1894 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
1895 reg |= GM_GPCR_DUP_FULL;
1896
1897 /* enable Rx/Tx */
1898 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
6b0c1480 1899 gma_write16(hw, port, GM_GP_CTRL, reg);
baef58b1 1900
4cde06ed 1901 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
baef58b1
SH		 1902 skge_link_up(skge);
1903}
1904
1905static void yukon_link_down(struct skge_port *skge)
1906{
1907 struct skge_hw *hw = skge->hw;
1908 int port = skge->port;
d8a09943 1909 u16 ctrl;
baef58b1 1910
6b0c1480 1911 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
d8a09943
SH		 1912
1913 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1914 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1915 gma_write16(hw, port, GM_GP_CTRL, ctrl);
baef58b1 1916
c506a509 1917 if (skge->flow_control == FLOW_MODE_REM_SEND) {
baef58b1 1918 /* restore Asymmetric Pause bit */
6b0c1480
SH		 1919 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1920 gm_phy_read(hw, port,
baef58b1
SH		 1921 PHY_MARV_AUNE_ADV)
1922 | PHY_M_AN_ASP);
1923
1924 }
1925
1926 yukon_reset(hw, port);
1927 skge_link_down(skge);
1928
1929 yukon_init(hw, port);
1930}
1931
1932static void yukon_phy_intr(struct skge_port *skge)
1933{
1934 struct skge_hw *hw = skge->hw;
1935 int port = skge->port;
1936 const char *reason = NULL;
1937 u16 istatus, phystat;
1938
6b0c1480
SH		 1939 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1940 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
7e676d91
SH		 1941
1942 if (netif_msg_intr(skge))
1943 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
1944 skge->netdev->name, istatus, phystat);
baef58b1
SH		 1945
1946 if (istatus & PHY_M_IS_AN_COMPL) {
6b0c1480 1947 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
baef58b1
SH		 1948 & PHY_M_AN_RF) {
1949 reason = "remote fault";
1950 goto failed;
1951 }
1952
c506a509 1953 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
baef58b1
SH		 1954 reason = "master/slave fault";
1955 goto failed;
1956 }
1957
1958 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
1959 reason = "speed/duplex";
1960 goto failed;
1961 }
1962
1963 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
1964 ? DUPLEX_FULL : DUPLEX_HALF;
1965 skge->speed = yukon_speed(hw, phystat);
1966
baef58b1
SH		 1967 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1968 switch (phystat & PHY_M_PS_PAUSE_MSK) {
1969 case PHY_M_PS_PAUSE_MSK:
1970 skge->flow_control = FLOW_MODE_SYMMETRIC;
1971 break;
1972 case PHY_M_PS_RX_P_EN:
1973 skge->flow_control = FLOW_MODE_REM_SEND;
1974 break;
1975 case PHY_M_PS_TX_P_EN:
1976 skge->flow_control = FLOW_MODE_LOC_SEND;
1977 break;
1978 default:
1979 skge->flow_control = FLOW_MODE_NONE;
1980 }
1981
1982 if (skge->flow_control == FLOW_MODE_NONE ||
1983 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
6b0c1480 1984 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
baef58b1 1985 else
6b0c1480 1986 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
baef58b1
SH		 1987 yukon_link_up(skge);
1988 return;
1989 }
1990
1991 if (istatus & PHY_M_IS_LSP_CHANGE)
1992 skge->speed = yukon_speed(hw, phystat);
1993
1994 if (istatus & PHY_M_IS_DUP_CHANGE)
1995 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1996 if (istatus & PHY_M_IS_LST_CHANGE) {
1997 if (phystat & PHY_M_PS_LINK_UP)
1998 yukon_link_up(skge);
1999 else
2000 yukon_link_down(skge);
2001 }
2002 return;
2003 failed:
2004 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2005 skge->netdev->name, reason);
2006
2007 /* XXX restart autonegotiation? */
2008}
2009
ee294dcd
SH		 2010static void skge_phy_reset(struct skge_port *skge)
2011{
2012 struct skge_hw *hw = skge->hw;
2013 int port = skge->port;
2014
2015 netif_stop_queue(skge->netdev);
2016 netif_carrier_off(skge->netdev);
2017
2018 spin_lock_bh(&hw->phy_lock);
2019 if (hw->chip_id == CHIP_ID_GENESIS) {
2020 genesis_reset(hw, port);
2021 genesis_mac_init(hw, port);
2022 } else {
2023 yukon_reset(hw, port);
2024 yukon_init(hw, port);
2025 }
2026 spin_unlock_bh(&hw->phy_lock);
2027}
2028
2cd8e5d3
SH		 2029/* Basic MII support */
2030static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2031{
2032 struct mii_ioctl_data *data = if_mii(ifr);
2033 struct skge_port *skge = netdev_priv(dev);
2034 struct skge_hw *hw = skge->hw;
2035 int err = -EOPNOTSUPP;
2036
2037 if (!netif_running(dev))
2038 return -ENODEV; /* Phy still in reset */
2039
2040 switch(cmd) {
2041 case SIOCGMIIPHY:
2042 data->phy_id = hw->phy_addr;
2043
2044 /* fallthru */
2045 case SIOCGMIIREG: {
2046 u16 val = 0;
2047 spin_lock_bh(&hw->phy_lock);
2048 if (hw->chip_id == CHIP_ID_GENESIS)
2049 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2050 else
2051 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2052 spin_unlock_bh(&hw->phy_lock);
2053 data->val_out = val;
2054 break;
2055 }
2056
2057 case SIOCSMIIREG:
2058 if (!capable(CAP_NET_ADMIN))
2059 return -EPERM;
2060
2061 spin_lock_bh(&hw->phy_lock);
2062 if (hw->chip_id == CHIP_ID_GENESIS)
2063 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2064 data->val_in);
2065 else
2066 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2067 data->val_in);
2068 spin_unlock_bh(&hw->phy_lock);
2069 break;
2070 }
2071 return err;
2072}
2073
baef58b1
SH		 2074static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2075{
2076 u32 end;
2077
2078 start /= 8;
2079 len /= 8;
2080 end = start + len - 1;
2081
2082 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2083 skge_write32(hw, RB_ADDR(q, RB_START), start);
2084 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2085 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2086 skge_write32(hw, RB_ADDR(q, RB_END), end);
2087
2088 if (q == Q_R1 || q == Q_R2) {
2089 /* Set thresholds on receive queue's */
2090 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2091 start + (2*len)/3);
2092 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2093 start + (len/3));
2094 } else {
2095 /* Enable store & forward on Tx queue's because
2096 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2097 */
2098 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2099 }
2100
2101 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2102}
2103
2104/* Setup Bus Memory Interface */
2105static void skge_qset(struct skge_port *skge, u16 q,
2106 const struct skge_element *e)
2107{
2108 struct skge_hw *hw = skge->hw;
2109 u32 watermark = 0x600;
2110 u64 base = skge->dma + (e->desc - skge->mem);
2111
2112 /* optimization to reduce window on 32bit/33mhz */
2113 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2114 watermark /= 2;
2115
2116 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2117 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2118 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2119 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2120}
2121
2122static int skge_up(struct net_device *dev)
2123{
2124 struct skge_port *skge = netdev_priv(dev);
2125 struct skge_hw *hw = skge->hw;
2126 int port = skge->port;
2127 u32 chunk, ram_addr;
2128 size_t rx_size, tx_size;
2129 int err;
2130
2131 if (netif_msg_ifup(skge))
2132 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2133
19a33d4e
SH		 2134 if (dev->mtu > RX_BUF_SIZE)
2135 skge->rx_buf_size = dev->mtu + ETH_HLEN + NET_IP_ALIGN;
2136 else
2137 skge->rx_buf_size = RX_BUF_SIZE;
2138
2139
baef58b1
SH		 2140 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2141 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2142 skge->mem_size = tx_size + rx_size;
2143 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2144 if (!skge->mem)
2145 return -ENOMEM;
2146
2147 memset(skge->mem, 0, skge->mem_size);
2148
2149 if ((err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma)))
2150 goto free_pci_mem;
2151
19a33d4e
SH		 2152 err = skge_rx_fill(skge);
2153 if (err)
baef58b1
SH		 2154 goto free_rx_ring;
2155
2156 if ((err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2157 skge->dma + rx_size)))
2158 goto free_rx_ring;
2159
2160 skge->tx_avail = skge->tx_ring.count - 1;
2161
7e676d91
SH		 2162 /* Enable IRQ from port */
2163 hw->intr_mask |= portirqmask[port];
2164 skge_write32(hw, B0_IMSK, hw->intr_mask);
2165
8f3f8193 2166 /* Initialize MAC */
4ff6ac05 2167 spin_lock_bh(&hw->phy_lock);
baef58b1
SH		 2168 if (hw->chip_id == CHIP_ID_GENESIS)
2169 genesis_mac_init(hw, port);
2170 else
2171 yukon_mac_init(hw, port);
4ff6ac05 2172 spin_unlock_bh(&hw->phy_lock);
baef58b1
SH		 2173
2174 /* Configure RAMbuffers */
981d0377 2175 chunk = hw->ram_size / ((hw->ports + 1)*2);
baef58b1
SH		 2176 ram_addr = hw->ram_offset + 2 * chunk * port;
2177
2178 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2179 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2180
2181 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2182 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2183 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2184
2185 /* Start receiver BMU */
2186 wmb();
2187 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
6abebb53 2188 skge_led(skge, LED_MODE_ON);
baef58b1 2189
baef58b1
SH		 2190 return 0;
2191
2192 free_rx_ring:
2193 skge_rx_clean(skge);
2194 kfree(skge->rx_ring.start);
2195 free_pci_mem:
2196 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2197
2198 return err;
2199}
2200
2201static int skge_down(struct net_device *dev)
2202{
2203 struct skge_port *skge = netdev_priv(dev);
2204 struct skge_hw *hw = skge->hw;
2205 int port = skge->port;
2206
2207 if (netif_msg_ifdown(skge))
2208 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2209
2210 netif_stop_queue(dev);
2211
46a60f2d
SH		 2212 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2213 if (hw->chip_id == CHIP_ID_GENESIS)
2214 genesis_stop(skge);
2215 else
2216 yukon_stop(skge);
2217
2218 hw->intr_mask &= ~portirqmask[skge->port];
2219 skge_write32(hw, B0_IMSK, hw->intr_mask);
2220
baef58b1
SH		 2221 /* Stop transmitter */
2222 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2223 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2224 RB_RST_SET|RB_DIS_OP_MD);
2225
baef58b1
SH		 2226
2227 /* Disable Force Sync bit and Enable Alloc bit */
6b0c1480 2228 skge_write8(hw, SK_REG(port, TXA_CTRL),
baef58b1
SH		 2229 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2230
2231 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
6b0c1480
SH		 2232 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2233 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
baef58b1
SH		 2234
2235 /* Reset PCI FIFO */
2236 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2237 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2238
2239 /* Reset the RAM Buffer async Tx queue */
2240 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2241 /* stop receiver */
2242 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2243 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2244 RB_RST_SET|RB_DIS_OP_MD);
2245 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2246
2247 if (hw->chip_id == CHIP_ID_GENESIS) {
6b0c1480
SH		 2248 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2249 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
baef58b1 2250 } else {
6b0c1480
SH		 2251 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2252 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
baef58b1
SH		 2253 }
2254
6abebb53 2255 skge_led(skge, LED_MODE_OFF);
baef58b1
SH		 2256
2257 skge_tx_clean(skge);
2258 skge_rx_clean(skge);
2259
2260 kfree(skge->rx_ring.start);
2261 kfree(skge->tx_ring.start);
2262 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2263 return 0;
2264}
2265
2266static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2267{
2268 struct skge_port *skge = netdev_priv(dev);
2269 struct skge_hw *hw = skge->hw;
2270 struct skge_ring *ring = &skge->tx_ring;
2271 struct skge_element *e;
2272 struct skge_tx_desc *td;
2273 int i;
2274 u32 control, len;
2275 u64 map;
2276 unsigned long flags;
2277
2278 skb = skb_padto(skb, ETH_ZLEN);
2279 if (!skb)
2280 return NETDEV_TX_OK;
2281
2282 local_irq_save(flags);
2283 if (!spin_trylock(&skge->tx_lock)) {
95566065
SH		 2284 /* Collision - tell upper layer to requeue */
2285 local_irq_restore(flags);
2286 return NETDEV_TX_LOCKED;
2287 }
baef58b1
SH		 2288
2289 if (unlikely(skge->tx_avail < skb_shinfo(skb)->nr_frags +1)) {
98684a9d 2290 if (!netif_queue_stopped(dev)) {
ee1c8191 2291 netif_stop_queue(dev);
baef58b1 2292
ee1c8191
SH		 2293 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
2294 dev->name);
2295 }
2296 spin_unlock_irqrestore(&skge->tx_lock, flags);
baef58b1
SH		 2297 return NETDEV_TX_BUSY;
2298 }
2299
2300 e = ring->to_use;
2301 td = e->desc;
2302 e->skb = skb;
2303 len = skb_headlen(skb);
2304 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2305 pci_unmap_addr_set(e, mapaddr, map);
2306 pci_unmap_len_set(e, maplen, len);
2307
2308 td->dma_lo = map;
2309 td->dma_hi = map >> 32;
2310
2311 if (skb->ip_summed == CHECKSUM_HW) {
baef58b1
SH		 2312 int offset = skb->h.raw - skb->data;
2313
2314 /* This seems backwards, but it is what the sk98lin
2315 * does. Looks like hardware is wrong?
2316 */
ea182d4a 2317 if (skb->h.ipiph->protocol == IPPROTO_UDP
981d0377 2318 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
baef58b1
SH		 2319 control = BMU_TCP_CHECK;
2320 else
2321 control = BMU_UDP_CHECK;
2322
2323 td->csum_offs = 0;
2324 td->csum_start = offset;
2325 td->csum_write = offset + skb->csum;
2326 } else
2327 control = BMU_CHECK;
2328
2329 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2330 control |= BMU_EOF| BMU_IRQ_EOF;
2331 else {
2332 struct skge_tx_desc *tf = td;
2333
2334 control |= BMU_STFWD;
2335 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2336 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2337
2338 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2339 frag->size, PCI_DMA_TODEVICE);
2340
2341 e = e->next;
2342 e->skb = NULL;
2343 tf = e->desc;
2344 tf->dma_lo = map;
2345 tf->dma_hi = (u64) map >> 32;
2346 pci_unmap_addr_set(e, mapaddr, map);
2347 pci_unmap_len_set(e, maplen, frag->size);
2348
2349 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2350 }
2351 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2352 }
2353 /* Make sure all the descriptors written */
2354 wmb();
2355 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2356 wmb();
2357
2358 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2359
2360 if (netif_msg_tx_queued(skge))
0b2d7fea 2361 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
baef58b1
SH		 2362 dev->name, e - ring->start, skb->len);
2363
2364 ring->to_use = e->next;
2365 skge->tx_avail -= skb_shinfo(skb)->nr_frags + 1;
2366 if (skge->tx_avail <= MAX_SKB_FRAGS + 1) {
2367 pr_debug("%s: transmit queue full\n", dev->name);
2368 netif_stop_queue(dev);
2369 }
2370
2371 dev->trans_start = jiffies;
2372 spin_unlock_irqrestore(&skge->tx_lock, flags);
2373
2374 return NETDEV_TX_OK;
2375}
2376
2377static inline void skge_tx_free(struct skge_hw *hw, struct skge_element *e)
2378{
19a33d4e 2379 /* This ring element can be skb or fragment */
baef58b1
SH		 2380 if (e->skb) {
2381 pci_unmap_single(hw->pdev,
2382 pci_unmap_addr(e, mapaddr),
2383 pci_unmap_len(e, maplen),
2384 PCI_DMA_TODEVICE);
2385 dev_kfree_skb_any(e->skb);
2386 e->skb = NULL;
2387 } else {
2388 pci_unmap_page(hw->pdev,
2389 pci_unmap_addr(e, mapaddr),
2390 pci_unmap_len(e, maplen),
2391 PCI_DMA_TODEVICE);
2392 }
2393}
2394
2395static void skge_tx_clean(struct skge_port *skge)
2396{
2397 struct skge_ring *ring = &skge->tx_ring;
2398 struct skge_element *e;
2399 unsigned long flags;
2400
2401 spin_lock_irqsave(&skge->tx_lock, flags);
2402 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
2403 ++skge->tx_avail;
2404 skge_tx_free(skge->hw, e);
2405 }
2406 ring->to_clean = e;
2407 spin_unlock_irqrestore(&skge->tx_lock, flags);
2408}
2409
2410static void skge_tx_timeout(struct net_device *dev)
2411{
2412 struct skge_port *skge = netdev_priv(dev);
2413
2414 if (netif_msg_timer(skge))
2415 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2416
2417 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2418 skge_tx_clean(skge);
2419}
2420
2421static int skge_change_mtu(struct net_device *dev, int new_mtu)
2422{
2423 int err = 0;
19a33d4e 2424 int running = netif_running(dev);
baef58b1 2425
95566065 2426 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
baef58b1
SH		 2427 return -EINVAL;
2428
baef58b1 2429
19a33d4e 2430 if (running)
baef58b1 2431 skge_down(dev);
19a33d4e
SH		 2432 dev->mtu = new_mtu;
2433 if (running)
baef58b1 2434 skge_up(dev);
baef58b1
SH		 2435
2436 return err;
2437}
2438
2439static void genesis_set_multicast(struct net_device *dev)
2440{
2441 struct skge_port *skge = netdev_priv(dev);
2442 struct skge_hw *hw = skge->hw;
2443 int port = skge->port;
2444 int i, count = dev->mc_count;
2445 struct dev_mc_list *list = dev->mc_list;
2446 u32 mode;
2447 u8 filter[8];
2448
6b0c1480 2449 mode = xm_read32(hw, port, XM_MODE);
baef58b1
SH		 2450 mode |= XM_MD_ENA_HASH;
2451 if (dev->flags & IFF_PROMISC)
2452 mode |= XM_MD_ENA_PROM;
2453 else
2454 mode &= ~XM_MD_ENA_PROM;
2455
2456 if (dev->flags & IFF_ALLMULTI)
2457 memset(filter, 0xff, sizeof(filter));
2458 else {
2459 memset(filter, 0, sizeof(filter));
95566065 2460 for (i = 0; list && i < count; i++, list = list->next) {
45bada65
SH		 2461 u32 crc, bit;
2462 crc = ether_crc_le(ETH_ALEN, list->dmi_addr);
2463 bit = ~crc & 0x3f;
baef58b1
SH		 2464 filter[bit/8] |= 1 << (bit%8);
2465 }
2466 }
2467
6b0c1480 2468 xm_write32(hw, port, XM_MODE, mode);
45bada65 2469 xm_outhash(hw, port, XM_HSM, filter);
baef58b1
SH		 2470}
2471
2472static void yukon_set_multicast(struct net_device *dev)
2473{
2474 struct skge_port *skge = netdev_priv(dev);
2475 struct skge_hw *hw = skge->hw;
2476 int port = skge->port;
2477 struct dev_mc_list *list = dev->mc_list;
2478 u16 reg;
2479 u8 filter[8];
2480
2481 memset(filter, 0, sizeof(filter));
2482
6b0c1480 2483 reg = gma_read16(hw, port, GM_RX_CTRL);
baef58b1
SH		 2484 reg |= GM_RXCR_UCF_ENA;
2485
8f3f8193 2486 if (dev->flags & IFF_PROMISC) /* promiscuous */
baef58b1
SH		 2487 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2488 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2489 memset(filter, 0xff, sizeof(filter));
2490 else if (dev->mc_count == 0) /* no multicast */
2491 reg &= ~GM_RXCR_MCF_ENA;
2492 else {
2493 int i;
2494 reg |= GM_RXCR_MCF_ENA;
2495
95566065 2496 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
baef58b1
SH		 2497 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2498 filter[bit/8] |= 1 << (bit%8);
2499 }
2500 }
2501
2502
6b0c1480 2503 gma_write16(hw, port, GM_MC_ADDR_H1,
baef58b1 2504 (u16)filter[0] | ((u16)filter[1] << 8));
6b0c1480 2505 gma_write16(hw, port, GM_MC_ADDR_H2,
baef58b1 2506 (u16)filter[2] | ((u16)filter[3] << 8));
6b0c1480 2507 gma_write16(hw, port, GM_MC_ADDR_H3,
baef58b1 2508 (u16)filter[4] | ((u16)filter[5] << 8));
6b0c1480 2509 gma_write16(hw, port, GM_MC_ADDR_H4,
baef58b1
SH		 2510 (u16)filter[6] | ((u16)filter[7] << 8));
2511
6b0c1480 2512 gma_write16(hw, port, GM_RX_CTRL, reg);
baef58b1
SH		 2513}
2514
383181ac
SH		 2515static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2516{
2517 if (hw->chip_id == CHIP_ID_GENESIS)
2518 return status >> XMR_FS_LEN_SHIFT;
2519 else
2520 return status >> GMR_FS_LEN_SHIFT;
2521}
2522
baef58b1
SH		 2523static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2524{
2525 if (hw->chip_id == CHIP_ID_GENESIS)
2526 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2527 else
2528 return (status & GMR_FS_ANY_ERR) ||
2529 (status & GMR_FS_RX_OK) == 0;
2530}
2531
19a33d4e
SH		 2532
2533/* Get receive buffer from descriptor.
2534 * Handles copy of small buffers and reallocation failures
2535 */
2536static inline struct sk_buff *skge_rx_get(struct skge_port *skge,
2537 struct skge_element *e,
383181ac 2538 u32 control, u32 status, u16 csum)
19a33d4e 2539{
383181ac
SH		 2540 struct sk_buff *skb;
2541 u16 len = control & BMU_BBC;
2542
2543 if (unlikely(netif_msg_rx_status(skge)))
2544 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2545 skge->netdev->name, e - skge->rx_ring.start,
2546 status, len);
2547
2548 if (len > skge->rx_buf_size)
2549 goto error;
2550
2551 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2552 goto error;
2553
2554 if (bad_phy_status(skge->hw, status))
2555 goto error;
2556
2557 if (phy_length(skge->hw, status) != len)
2558 goto error;
19a33d4e
SH		 2559
2560 if (len < RX_COPY_THRESHOLD) {
383181ac
SH		 2561 skb = dev_alloc_skb(len + 2);
2562 if (!skb)
2563 goto resubmit;
19a33d4e 2564
383181ac 2565 skb_reserve(skb, 2);
19a33d4e
SH		 2566 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2567 pci_unmap_addr(e, mapaddr),
2568 len, PCI_DMA_FROMDEVICE);
383181ac 2569 memcpy(skb->data, e->skb->data, len);
19a33d4e
SH		 2570 pci_dma_sync_single_for_device(skge->hw->pdev,
2571 pci_unmap_addr(e, mapaddr),
2572 len, PCI_DMA_FROMDEVICE);
19a33d4e 2573 skge_rx_reuse(e, skge->rx_buf_size);
19a33d4e 2574 } else {
383181ac
SH		 2575 struct sk_buff *nskb;
2576 nskb = dev_alloc_skb(skge->rx_buf_size + NET_IP_ALIGN);
2577 if (!nskb)
2578 goto resubmit;
19a33d4e
SH		 2579
2580 pci_unmap_single(skge->hw->pdev,
2581 pci_unmap_addr(e, mapaddr),
2582 pci_unmap_len(e, maplen),
2583 PCI_DMA_FROMDEVICE);
2584 skb = e->skb;
383181ac 2585 prefetch(skb->data);
19a33d4e 2586 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
baef58b1 2587 }
383181ac
SH		 2588
2589 skb_put(skb, len);
2590 skb->dev = skge->netdev;
2591 if (skge->rx_csum) {
2592 skb->csum = csum;
2593 skb->ip_summed = CHECKSUM_HW;
2594 }
2595
2596 skb->protocol = eth_type_trans(skb, skge->netdev);
2597
2598 return skb;
2599error:
2600
2601 if (netif_msg_rx_err(skge))
2602 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2603 skge->netdev->name, e - skge->rx_ring.start,
2604 control, status);
2605
2606 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2607 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2608 skge->net_stats.rx_length_errors++;
2609 if (status & XMR_FS_FRA_ERR)
2610 skge->net_stats.rx_frame_errors++;
2611 if (status & XMR_FS_FCS_ERR)
2612 skge->net_stats.rx_crc_errors++;
2613 } else {
2614 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
2615 skge->net_stats.rx_length_errors++;
2616 if (status & GMR_FS_FRAGMENT)
2617 skge->net_stats.rx_frame_errors++;
2618 if (status & GMR_FS_CRC_ERR)
2619 skge->net_stats.rx_crc_errors++;
2620 }
2621
2622resubmit:
2623 skge_rx_reuse(e, skge->rx_buf_size);
2624 return NULL;
baef58b1
SH		 2625}
2626
19a33d4e 2627
baef58b1
SH		 2628static int skge_poll(struct net_device *dev, int *budget)
2629{
2630 struct skge_port *skge = netdev_priv(dev);
2631 struct skge_hw *hw = skge->hw;
2632 struct skge_ring *ring = &skge->rx_ring;
2633 struct skge_element *e;
2634 unsigned int to_do = min(dev->quota, *budget);
2635 unsigned int work_done = 0;
7e676d91 2636
1631aef1 2637 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
baef58b1 2638 struct skge_rx_desc *rd = e->desc;
19a33d4e 2639 struct sk_buff *skb;
383181ac 2640 u32 control;
baef58b1
SH		 2641
2642 rmb();
2643 control = rd->control;
2644 if (control & BMU_OWN)
2645 break;
2646
383181ac
SH		 2647 skb = skge_rx_get(skge, e, control, rd->status,
2648 le16_to_cpu(rd->csum2));
19a33d4e 2649 if (likely(skb)) {
19a33d4e
SH		 2650 dev->last_rx = jiffies;
2651 netif_receive_skb(skb);
baef58b1 2652
19a33d4e
SH		 2653 ++work_done;
2654 } else
2655 skge_rx_reuse(e, skge->rx_buf_size);
baef58b1
SH		 2656 }
2657 ring->to_clean = e;
2658
baef58b1
SH		 2659 /* restart receiver */
2660 wmb();
2661 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR),
2662 CSR_START | CSR_IRQ_CL_F);
2663
19a33d4e
SH		 2664 *budget -= work_done;
2665 dev->quota -= work_done;
2666
2667 if (work_done >= to_do)
2668 return 1; /* not done */
baef58b1 2669
1631aef1 2670 netif_rx_complete(dev);
19a33d4e
SH		 2671 hw->intr_mask |= portirqmask[skge->port];
2672 skge_write32(hw, B0_IMSK, hw->intr_mask);
1631aef1
SH		 2673 skge_read32(hw, B0_IMSK);
2674
19a33d4e 2675 return 0;
baef58b1
SH		 2676}
2677
2678static inline void skge_tx_intr(struct net_device *dev)
2679{
2680 struct skge_port *skge = netdev_priv(dev);
2681 struct skge_hw *hw = skge->hw;
2682 struct skge_ring *ring = &skge->tx_ring;
2683 struct skge_element *e;
2684
2685 spin_lock(&skge->tx_lock);
1631aef1 2686 for (e = ring->to_clean; prefetch(e->next), e != ring->to_use; e = e->next) {
baef58b1
SH		 2687 struct skge_tx_desc *td = e->desc;
2688 u32 control;
2689
2690 rmb();
2691 control = td->control;
2692 if (control & BMU_OWN)
2693 break;
2694
2695 if (unlikely(netif_msg_tx_done(skge)))
0b2d7fea 2696 printk(KERN_DEBUG PFX "%s: tx done slot %td status 0x%x\n",
baef58b1
SH		 2697 dev->name, e - ring->start, td->status);
2698
2699 skge_tx_free(hw, e);
2700 e->skb = NULL;
2701 ++skge->tx_avail;
2702 }
2703 ring->to_clean = e;
2704 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
2705
2706 if (skge->tx_avail > MAX_SKB_FRAGS + 1)
2707 netif_wake_queue(dev);
2708
2709 spin_unlock(&skge->tx_lock);
2710}
2711
f6620cab
SH		 2712/* Parity errors seem to happen when Genesis is connected to a switch
2713 * with no other ports present. Heartbeat error??
2714 */
baef58b1
SH		 2715static void skge_mac_parity(struct skge_hw *hw, int port)
2716{
f6620cab
SH		 2717 struct net_device *dev = hw->dev[port];
2718
2719 if (dev) {
2720 struct skge_port *skge = netdev_priv(dev);
2721 ++skge->net_stats.tx_heartbeat_errors;
2722 }
baef58b1
SH		 2723
2724 if (hw->chip_id == CHIP_ID_GENESIS)
6b0c1480 2725 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
baef58b1
SH		 2726 MFF_CLR_PERR);
2727 else
2728 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
6b0c1480 2729 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
981d0377 2730 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
baef58b1
SH		 2731 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
2732}
2733
2734static void skge_pci_clear(struct skge_hw *hw)
2735{
2736 u16 status;
2737
467b3417 2738 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
baef58b1 2739 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
467b3417
SH		 2740 pci_write_config_word(hw->pdev, PCI_STATUS,
2741 status | PCI_STATUS_ERROR_BITS);
baef58b1
SH		 2742 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2743}
2744
2745static void skge_mac_intr(struct skge_hw *hw, int port)
2746{
95566065 2747 if (hw->chip_id == CHIP_ID_GENESIS)
baef58b1
SH		 2748 genesis_mac_intr(hw, port);
2749 else
2750 yukon_mac_intr(hw, port);
2751}
2752
2753/* Handle device specific framing and timeout interrupts */
2754static void skge_error_irq(struct skge_hw *hw)
2755{
2756 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2757
2758 if (hw->chip_id == CHIP_ID_GENESIS) {
2759 /* clear xmac errors */
2760 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
46a60f2d 2761 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
baef58b1 2762 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
46a60f2d 2763 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
baef58b1
SH		 2764 } else {
2765 /* Timestamp (unused) overflow */
2766 if (hwstatus & IS_IRQ_TIST_OV)
2767 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
baef58b1
SH		 2768 }
2769
2770 if (hwstatus & IS_RAM_RD_PAR) {
2771 printk(KERN_ERR PFX "Ram read data parity error\n");
2772 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
2773 }
2774
2775 if (hwstatus & IS_RAM_WR_PAR) {
2776 printk(KERN_ERR PFX "Ram write data parity error\n");
2777 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
2778 }
2779
2780 if (hwstatus & IS_M1_PAR_ERR)
2781 skge_mac_parity(hw, 0);
2782
2783 if (hwstatus & IS_M2_PAR_ERR)
2784 skge_mac_parity(hw, 1);
2785
2786 if (hwstatus & IS_R1_PAR_ERR)
2787 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
2788
2789 if (hwstatus & IS_R2_PAR_ERR)
2790 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
2791
2792 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
2793 printk(KERN_ERR PFX "hardware error detected (status 0x%x)\n",
2794 hwstatus);
2795
2796 skge_pci_clear(hw);
2797
050ec18a 2798 /* if error still set then just ignore it */
baef58b1
SH		 2799 hwstatus = skge_read32(hw, B0_HWE_ISRC);
2800 if (hwstatus & IS_IRQ_STAT) {
050ec18a 2801 pr_debug("IRQ status %x: still set ignoring hardware errors\n",
baef58b1
SH		 2802 hwstatus);
2803 hw->intr_mask &= ~IS_HW_ERR;
2804 }
2805 }
2806}
2807
2808/*
8f3f8193 2809 * Interrupt from PHY are handled in tasklet (soft irq)
baef58b1
SH		 2810 * because accessing phy registers requires spin wait which might
2811 * cause excess interrupt latency.
2812 */
2813static void skge_extirq(unsigned long data)
2814{
2815 struct skge_hw *hw = (struct skge_hw *) data;
2816 int port;
2817
2818 spin_lock(&hw->phy_lock);
2819 for (port = 0; port < 2; port++) {
2820 struct net_device *dev = hw->dev[port];
2821
2822 if (dev && netif_running(dev)) {
2823 struct skge_port *skge = netdev_priv(dev);
2824
2825 if (hw->chip_id != CHIP_ID_GENESIS)
2826 yukon_phy_intr(skge);
89bf5f23 2827 else
45bada65 2828 bcom_phy_intr(skge);
baef58b1
SH		 2829 }
2830 }
2831 spin_unlock(&hw->phy_lock);
2832
2833 local_irq_disable();
2834 hw->intr_mask |= IS_EXT_REG;
2835 skge_write32(hw, B0_IMSK, hw->intr_mask);
2836 local_irq_enable();
2837}
2838
1631aef1
SH		 2839static inline void skge_wakeup(struct net_device *dev)
2840{
2841 struct skge_port *skge = netdev_priv(dev);
2842
2843 prefetch(skge->rx_ring.to_clean);
2844 netif_rx_schedule(dev);
2845}
2846
baef58b1
SH		 2847static irqreturn_t skge_intr(int irq, void *dev_id, struct pt_regs *regs)
2848{
2849 struct skge_hw *hw = dev_id;
2850 u32 status = skge_read32(hw, B0_SP_ISRC);
2851
2852 if (status == 0 || status == ~0) /* hotplug or shared irq */
2853 return IRQ_NONE;
2854
2855 status &= hw->intr_mask;
7e676d91 2856 if (status & IS_R1_F) {
baef58b1 2857 hw->intr_mask &= ~IS_R1_F;
1631aef1 2858 skge_wakeup(hw->dev[0]);
baef58b1
SH		 2859 }
2860
7e676d91 2861 if (status & IS_R2_F) {
baef58b1 2862 hw->intr_mask &= ~IS_R2_F;
1631aef1 2863 skge_wakeup(hw->dev[1]);
baef58b1
SH		 2864 }
2865
2866 if (status & IS_XA1_F)
2867 skge_tx_intr(hw->dev[0]);
2868
2869 if (status & IS_XA2_F)
2870 skge_tx_intr(hw->dev[1]);
2871
d25f5a67
SH		 2872 if (status & IS_PA_TO_RX1) {
2873 struct skge_port *skge = netdev_priv(hw->dev[0]);
2874 ++skge->net_stats.rx_over_errors;
2875 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
2876 }
2877
2878 if (status & IS_PA_TO_RX2) {
2879 struct skge_port *skge = netdev_priv(hw->dev[1]);
2880 ++skge->net_stats.rx_over_errors;
2881 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
2882 }
2883
2884 if (status & IS_PA_TO_TX1)
2885 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
2886
2887 if (status & IS_PA_TO_TX2)
2888 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
2889
baef58b1
SH		 2890 if (status & IS_MAC1)
2891 skge_mac_intr(hw, 0);
95566065 2892
baef58b1
SH		 2893 if (status & IS_MAC2)
2894 skge_mac_intr(hw, 1);
2895
2896 if (status & IS_HW_ERR)
2897 skge_error_irq(hw);
2898
2899 if (status & IS_EXT_REG) {
2900 hw->intr_mask &= ~IS_EXT_REG;
2901 tasklet_schedule(&hw->ext_tasklet);
2902 }
2903
7e676d91 2904 skge_write32(hw, B0_IMSK, hw->intr_mask);
baef58b1
SH		 2905
2906 return IRQ_HANDLED;
2907}
2908
2909#ifdef CONFIG_NET_POLL_CONTROLLER
2910static void skge_netpoll(struct net_device *dev)
2911{
2912 struct skge_port *skge = netdev_priv(dev);
2913
2914 disable_irq(dev->irq);
2915 skge_intr(dev->irq, skge->hw, NULL);
2916 enable_irq(dev->irq);
2917}
2918#endif
2919
2920static int skge_set_mac_address(struct net_device *dev, void *p)
2921{
2922 struct skge_port *skge = netdev_priv(dev);
c2681dd8
SH		 2923 struct skge_hw *hw = skge->hw;
2924 unsigned port = skge->port;
2925 const struct sockaddr *addr = p;
baef58b1
SH		 2926
2927 if (!is_valid_ether_addr(addr->sa_data))
2928 return -EADDRNOTAVAIL;
2929
c2681dd8 2930 spin_lock_bh(&hw->phy_lock);
baef58b1 2931 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
c2681dd8 2932 memcpy_toio(hw->regs + B2_MAC_1 + port*8,
baef58b1 2933 dev->dev_addr, ETH_ALEN);
c2681dd8 2934 memcpy_toio(hw->regs + B2_MAC_2 + port*8,
baef58b1 2935 dev->dev_addr, ETH_ALEN);
c2681dd8
SH		 2936
2937 if (hw->chip_id == CHIP_ID_GENESIS)
2938 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
2939 else {
2940 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2941 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2942 }
2943 spin_unlock_bh(&hw->phy_lock);
2944
2945 return 0;
baef58b1
SH		 2946}
2947
2948static const struct {
2949 u8 id;
2950 const char *name;
2951} skge_chips[] = {
2952 { CHIP_ID_GENESIS, "Genesis" },
2953 { CHIP_ID_YUKON, "Yukon" },
2954 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
2955 { CHIP_ID_YUKON_LP, "Yukon-LP"},
baef58b1
SH		 2956};
2957
2958static const char *skge_board_name(const struct skge_hw *hw)
2959{
2960 int i;
2961 static char buf[16];
2962
2963 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
2964 if (skge_chips[i].id == hw->chip_id)
2965 return skge_chips[i].name;
2966
2967 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
2968 return buf;
2969}
2970
2971
2972/*
2973 * Setup the board data structure, but don't bring up
2974 * the port(s)
2975 */
2976static int skge_reset(struct skge_hw *hw)
2977{
adba9e23 2978 u32 reg;
baef58b1 2979 u16 ctst;
5e1705dd 2980 u8 t8, mac_cfg, pmd_type, phy_type;
981d0377 2981 int i;
baef58b1
SH		 2982
2983 ctst = skge_read16(hw, B0_CTST);
2984
2985 /* do a SW reset */
2986 skge_write8(hw, B0_CTST, CS_RST_SET);
2987 skge_write8(hw, B0_CTST, CS_RST_CLR);
2988
2989 /* clear PCI errors, if any */
2990 skge_pci_clear(hw);
2991
2992 skge_write8(hw, B0_CTST, CS_MRST_CLR);
2993
2994 /* restore CLK_RUN bits (for Yukon-Lite) */
2995 skge_write16(hw, B0_CTST,
2996 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
2997
2998 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
5e1705dd
SH		 2999 phy_type = skge_read8(hw, B2_E_1) & 0xf;
3000 pmd_type = skge_read8(hw, B2_PMD_TYP);
3001 hw->copper = (pmd_type == 'T' || pmd_type == '1');
baef58b1 3002
95566065 3003 switch (hw->chip_id) {
baef58b1 3004 case CHIP_ID_GENESIS:
5e1705dd 3005 switch (phy_type) {
baef58b1
SH		 3006 case SK_PHY_BCOM:
3007 hw->phy_addr = PHY_ADDR_BCOM;
3008 break;
3009 default:
3010 printk(KERN_ERR PFX "%s: unsupported phy type 0x%x\n",
5e1705dd 3011 pci_name(hw->pdev), phy_type);
baef58b1
SH		 3012 return -EOPNOTSUPP;
3013 }
3014 break;
3015
3016 case CHIP_ID_YUKON:
3017 case CHIP_ID_YUKON_LITE:
3018 case CHIP_ID_YUKON_LP:
5e1705dd
SH		 3019 if (phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3020 hw->copper = 1;
baef58b1
SH		 3021
3022 hw->phy_addr = PHY_ADDR_MARV;
baef58b1
SH		 3023 break;
3024
3025 default:
3026 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
3027 pci_name(hw->pdev), hw->chip_id);
3028 return -EOPNOTSUPP;
3029 }
3030
981d0377
SH		 3031 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3032 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3033 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
baef58b1
SH		 3034
3035 /* read the adapters RAM size */
3036 t8 = skge_read8(hw, B2_E_0);
3037 if (hw->chip_id == CHIP_ID_GENESIS) {
3038 if (t8 == 3) {
3039 /* special case: 4 x 64k x 36, offset = 0x80000 */
3040 hw->ram_size = 0x100000;
3041 hw->ram_offset = 0x80000;
3042 } else
3043 hw->ram_size = t8 * 512;
3044 }
3045 else if (t8 == 0)
3046 hw->ram_size = 0x20000;
3047 else
3048 hw->ram_size = t8 * 4096;
3049
050ec18a 3050 hw->intr_mask = IS_HW_ERR | IS_EXT_REG;
baef58b1
SH		 3051 if (hw->chip_id == CHIP_ID_GENESIS)
3052 genesis_init(hw);
3053 else {
3054 /* switch power to VCC (WA for VAUX problem) */
3055 skge_write8(hw, B0_POWER_CTRL,
3056 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
adba9e23 3057
050ec18a
SH		 3058 /* avoid boards with stuck Hardware error bits */
3059 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3060 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3061 printk(KERN_WARNING PFX "stuck hardware sensor bit\n");
3062 hw->intr_mask &= ~IS_HW_ERR;
3063 }
3064
adba9e23
SH		 3065 /* Clear PHY COMA */
3066 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3067 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3068 reg &= ~PCI_PHY_COMA;
3069 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3070 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3071
3072
981d0377 3073 for (i = 0; i < hw->ports; i++) {
6b0c1480
SH		 3074 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3075 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
baef58b1
SH		 3076 }
3077 }
3078
3079 /* turn off hardware timer (unused) */
3080 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3081 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3082 skge_write8(hw, B0_LED, LED_STAT_ON);
3083
3084 /* enable the Tx Arbiters */
981d0377 3085 for (i = 0; i < hw->ports; i++)
6b0c1480 3086 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
baef58b1
SH		 3087
3088 /* Initialize ram interface */
3089 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3090
3091 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3092 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3093 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3094 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3095 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3096 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3097 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3098 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3099 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3100 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3101 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3102 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3103
3104 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3105
3106 /* Set interrupt moderation for Transmit only
3107 * Receive interrupts avoided by NAPI
3108 */
3109 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3110 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3111 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3112
baef58b1
SH		 3113 skge_write32(hw, B0_IMSK, hw->intr_mask);
3114
baef58b1 3115 spin_lock_bh(&hw->phy_lock);
981d0377 3116 for (i = 0; i < hw->ports; i++) {
baef58b1
SH		 3117 if (hw->chip_id == CHIP_ID_GENESIS)
3118 genesis_reset(hw, i);
3119 else
3120 yukon_reset(hw, i);
3121 }
3122 spin_unlock_bh(&hw->phy_lock);
3123
3124 return 0;
3125}
3126
3127/* Initialize network device */
981d0377
SH		 3128static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3129 int highmem)
baef58b1
SH		 3130{
3131 struct skge_port *skge;
3132 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3133
3134 if (!dev) {
3135 printk(KERN_ERR "skge etherdev alloc failed");
3136 return NULL;
3137 }
3138
3139 SET_MODULE_OWNER(dev);
3140 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3141 dev->open = skge_up;
3142 dev->stop = skge_down;
2cd8e5d3 3143 dev->do_ioctl = skge_ioctl;
baef58b1
SH		 3144 dev->hard_start_xmit = skge_xmit_frame;
3145 dev->get_stats = skge_get_stats;
3146 if (hw->chip_id == CHIP_ID_GENESIS)
3147 dev->set_multicast_list = genesis_set_multicast;
3148 else
3149 dev->set_multicast_list = yukon_set_multicast;
3150
3151 dev->set_mac_address = skge_set_mac_address;
3152 dev->change_mtu = skge_change_mtu;
3153 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3154 dev->tx_timeout = skge_tx_timeout;
3155 dev->watchdog_timeo = TX_WATCHDOG;
3156 dev->poll = skge_poll;
3157 dev->weight = NAPI_WEIGHT;
3158#ifdef CONFIG_NET_POLL_CONTROLLER
3159 dev->poll_controller = skge_netpoll;
3160#endif
3161 dev->irq = hw->pdev->irq;
3162 dev->features = NETIF_F_LLTX;
981d0377
SH		 3163 if (highmem)
3164 dev->features |= NETIF_F_HIGHDMA;
baef58b1
SH		 3165
3166 skge = netdev_priv(dev);
3167 skge->netdev = dev;
3168 skge->hw = hw;
3169 skge->msg_enable = netif_msg_init(debug, default_msg);
3170 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3171 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3172
3173 /* Auto speed and flow control */
3174 skge->autoneg = AUTONEG_ENABLE;
3175 skge->flow_control = FLOW_MODE_SYMMETRIC;
3176 skge->duplex = -1;
3177 skge->speed = -1;
31b619c5 3178 skge->advertising = skge_supported_modes(hw);
baef58b1
SH		 3179
3180 hw->dev[port] = dev;
3181
3182 skge->port = port;
3183
3184 spin_lock_init(&skge->tx_lock);
3185
baef58b1
SH		 3186 if (hw->chip_id != CHIP_ID_GENESIS) {
3187 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3188 skge->rx_csum = 1;
3189 }
3190
3191 /* read the mac address */
3192 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
56230d53 3193 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
baef58b1
SH		 3194
3195 /* device is off until link detection */
3196 netif_carrier_off(dev);
3197 netif_stop_queue(dev);
3198
3199 return dev;
3200}
3201
3202static void __devinit skge_show_addr(struct net_device *dev)
3203{
3204 const struct skge_port *skge = netdev_priv(dev);
3205
3206 if (netif_msg_probe(skge))
3207 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3208 dev->name,
3209 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3210 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3211}
3212
3213static int __devinit skge_probe(struct pci_dev *pdev,
3214 const struct pci_device_id *ent)
3215{
3216 struct net_device *dev, *dev1;
3217 struct skge_hw *hw;
3218 int err, using_dac = 0;
3219
3220 if ((err = pci_enable_device(pdev))) {
3221 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3222 pci_name(pdev));
3223 goto err_out;
3224 }
3225
3226 if ((err = pci_request_regions(pdev, DRV_NAME))) {
3227 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3228 pci_name(pdev));
3229 goto err_out_disable_pdev;
3230 }
3231
3232 pci_set_master(pdev);
3233
3234 if (!(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK)))
3235 using_dac = 1;
3236 else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3237 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3238 pci_name(pdev));
3239 goto err_out_free_regions;
3240 }
3241
3242#ifdef __BIG_ENDIAN
8f3f8193 3243 /* byte swap descriptors in hardware */
baef58b1
SH		 3244 {
3245 u32 reg;
3246
3247 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3248 reg |= PCI_REV_DESC;
3249 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3250 }
3251#endif
3252
3253 err = -ENOMEM;
7e863061 3254 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
baef58b1
SH		 3255 if (!hw) {
3256 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3257 pci_name(pdev));
3258 goto err_out_free_regions;
3259 }
3260
baef58b1
SH		 3261 hw->pdev = pdev;
3262 spin_lock_init(&hw->phy_lock);
3263 tasklet_init(&hw->ext_tasklet, skge_extirq, (unsigned long) hw);
3264
3265 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3266 if (!hw->regs) {
3267 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3268 pci_name(pdev));
3269 goto err_out_free_hw;
3270 }
3271
3272 if ((err = request_irq(pdev->irq, skge_intr, SA_SHIRQ, DRV_NAME, hw))) {
3273 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3274 pci_name(pdev), pdev->irq);
3275 goto err_out_iounmap;
3276 }
3277 pci_set_drvdata(pdev, hw);
3278
3279 err = skge_reset(hw);
3280 if (err)
3281 goto err_out_free_irq;
3282
d7eaee08 3283 printk(KERN_INFO PFX DRV_VERSION " addr 0x%lx irq %d chip %s rev %d\n",
baef58b1 3284 pci_resource_start(pdev, 0), pdev->irq,
981d0377 3285 skge_board_name(hw), hw->chip_rev);
baef58b1 3286
981d0377 3287 if ((dev = skge_devinit(hw, 0, using_dac)) == NULL)
baef58b1
SH		 3288 goto err_out_led_off;
3289
baef58b1
SH		 3290 if ((err = register_netdev(dev))) {
3291 printk(KERN_ERR PFX "%s: cannot register net device\n",
3292 pci_name(pdev));
3293 goto err_out_free_netdev;
3294 }
3295
3296 skge_show_addr(dev);
3297
981d0377 3298 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
baef58b1
SH		 3299 if (register_netdev(dev1) == 0)
3300 skge_show_addr(dev1);
3301 else {
3302 /* Failure to register second port need not be fatal */
3303 printk(KERN_WARNING PFX "register of second port failed\n");
3304 hw->dev[1] = NULL;
3305 free_netdev(dev1);
3306 }
3307 }
3308
3309 return 0;
3310
3311err_out_free_netdev:
3312 free_netdev(dev);
3313err_out_led_off:
3314 skge_write16(hw, B0_LED, LED_STAT_OFF);
3315err_out_free_irq:
3316 free_irq(pdev->irq, hw);
3317err_out_iounmap:
3318 iounmap(hw->regs);
3319err_out_free_hw:
3320 kfree(hw);
3321err_out_free_regions:
3322 pci_release_regions(pdev);
3323err_out_disable_pdev:
3324 pci_disable_device(pdev);
3325 pci_set_drvdata(pdev, NULL);
3326err_out:
3327 return err;
3328}
3329
3330static void __devexit skge_remove(struct pci_dev *pdev)
3331{
3332 struct skge_hw *hw = pci_get_drvdata(pdev);
3333 struct net_device *dev0, *dev1;
3334
95566065 3335 if (!hw)
baef58b1
SH		 3336 return;
3337
3338 if ((dev1 = hw->dev[1]))
3339 unregister_netdev(dev1);
3340 dev0 = hw->dev[0];
3341 unregister_netdev(dev0);
3342
46a60f2d
SH		 3343 skge_write32(hw, B0_IMSK, 0);
3344 skge_write16(hw, B0_LED, LED_STAT_OFF);
3345 skge_pci_clear(hw);
3346 skge_write8(hw, B0_CTST, CS_RST_SET);
3347
baef58b1
SH		 3348 tasklet_kill(&hw->ext_tasklet);
3349
3350 free_irq(pdev->irq, hw);
3351 pci_release_regions(pdev);
3352 pci_disable_device(pdev);
3353 if (dev1)
3354 free_netdev(dev1);
3355 free_netdev(dev0);
46a60f2d 3356
baef58b1
SH		 3357 iounmap(hw->regs);
3358 kfree(hw);
3359 pci_set_drvdata(pdev, NULL);
3360}
3361
3362#ifdef CONFIG_PM
2a569579 3363static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
baef58b1
SH		 3364{
3365 struct skge_hw *hw = pci_get_drvdata(pdev);
3366 int i, wol = 0;
3367
95566065 3368 for (i = 0; i < 2; i++) {
baef58b1
SH		 3369 struct net_device *dev = hw->dev[i];
3370
3371 if (dev) {
3372 struct skge_port *skge = netdev_priv(dev);
3373 if (netif_running(dev)) {
3374 netif_carrier_off(dev);
46a60f2d
SH		 3375 if (skge->wol)
3376 netif_stop_queue(dev);
3377 else
3378 skge_down(dev);
baef58b1
SH		 3379 }
3380 netif_device_detach(dev);
3381 wol |= skge->wol;
3382 }
3383 }
3384
3385 pci_save_state(pdev);
2a569579 3386 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
baef58b1
SH		 3387 pci_disable_device(pdev);
3388 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3389
3390 return 0;
3391}
3392
3393static int skge_resume(struct pci_dev *pdev)
3394{
3395 struct skge_hw *hw = pci_get_drvdata(pdev);
3396 int i;
3397
3398 pci_set_power_state(pdev, PCI_D0);
3399 pci_restore_state(pdev);
3400 pci_enable_wake(pdev, PCI_D0, 0);
3401
3402 skge_reset(hw);
3403
95566065 3404 for (i = 0; i < 2; i++) {
baef58b1
SH		 3405 struct net_device *dev = hw->dev[i];
3406 if (dev) {
3407 netif_device_attach(dev);
95566065 3408 if (netif_running(dev))
baef58b1
SH		 3409 skge_up(dev);
3410 }
3411 }
3412 return 0;
3413}
3414#endif
3415
3416static struct pci_driver skge_driver = {
3417 .name = DRV_NAME,
3418 .id_table = skge_id_table,
3419 .probe = skge_probe,
3420 .remove = __devexit_p(skge_remove),
3421#ifdef CONFIG_PM
3422 .suspend = skge_suspend,
3423 .resume = skge_resume,
3424#endif
3425};
3426
3427static int __init skge_init_module(void)
3428{
3429 return pci_module_init(&skge_driver);
3430}
3431
3432static void __exit skge_cleanup_module(void)
3433{
3434 pci_unregister_driver(&skge_driver);
3435}
3436
3437module_init(skge_init_module);
3438module_exit(skge_cleanup_module);
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