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sky2: disable support for 88E8056
[mirror_ubuntu-artful-kernel.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
798b6b19 13 * the Free Software Foundation; either version 2 of the License.
cd28ab6a
SH		 14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
793b883e 25#include <linux/crc32.h>
cd28ab6a
SH		 26#include <linux/kernel.h>
27#include <linux/version.h>
28#include <linux/module.h>
29#include <linux/netdevice.h>
d0bbccfa 30#include <linux/dma-mapping.h>
cd28ab6a
SH		 31#include <linux/etherdevice.h>
32#include <linux/ethtool.h>
33#include <linux/pci.h>
34#include <linux/ip.h>
35#include <linux/tcp.h>
36#include <linux/in.h>
37#include <linux/delay.h>
91c86df5 38#include <linux/workqueue.h>
d1f13708 39#include <linux/if_vlan.h>
d70cd51a 40#include <linux/prefetch.h>
ef743d33 41#include <linux/mii.h>
cd28ab6a
SH		 42
43#include <asm/irq.h>
44
d1f13708
SH		 45#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
46#define SKY2_VLAN_TAG_USED 1
47#endif
48
cd28ab6a
SH		 49#include "sky2.h"
50
51#define DRV_NAME "sky2"
62ba7e6c 52#define DRV_VERSION "1.13"
cd28ab6a
SH		 53#define PFX DRV_NAME " "
54
55/*
56 * The Yukon II chipset takes 64 bit command blocks (called list elements)
57 * that are organized into three (receive, transmit, status) different rings
14d0263f 58 * similar to Tigon3.
cd28ab6a
SH		 59 */
60
14d0263f 61#define RX_LE_SIZE 1024
cd28ab6a 62#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 63#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 64#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 65#define RX_SKB_ALIGN 8
22e11703 66#define RX_BUF_WRITE 16
793b883e
SH		 67
68#define TX_RING_SIZE 512
69#define TX_DEF_PENDING (TX_RING_SIZE - 1)
70#define TX_MIN_PENDING 64
b19666d9 71#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 72
793b883e 73#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 74#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 75#define TX_WATCHDOG (5 * HZ)
76#define NAPI_WEIGHT 64
77#define PHY_RETRIES 1000
78
cb5d9547
SH		 79#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
80
cd28ab6a 81static const u32 default_msg =
793b883e
SH		 82 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
83 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 84 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 85
793b883e 86static int debug = -1; /* defaults above */
cd28ab6a
SH		 87module_param(debug, int, 0);
88MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
89
14d0263f 90static int copybreak __read_mostly = 128;
bdb5c58e
SH		 91module_param(copybreak, int, 0);
92MODULE_PARM_DESC(copybreak, "Receive copy threshold");
93
fb2690a9
SH		 94static int disable_msi = 0;
95module_param(disable_msi, int, 0);
96MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
97
e561a83b 98static int idle_timeout = 0;
01bd7564 99module_param(idle_timeout, int, 0);
e561a83b 100MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 101
cd28ab6a 102static const struct pci_device_id sky2_id_table[] = {
e5b74c7d
SH		 103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
2d2a3871 105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
508f89e7 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
f1a0b6f5 108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
e5b74c7d
SH		 109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
0a17e4c2
SH		 126#ifdef broken
127 /* This device causes data corruption problems that are not resolved */
e5b74c7d 128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
0a17e4c2 129#endif
e5b74c7d
SH		 130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
f1a0b6f5
SH		 133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
cd28ab6a
SH		 136 { 0 }
137};
793b883e 138
cd28ab6a
SH		 139MODULE_DEVICE_TABLE(pci, sky2_id_table);
140
141/* Avoid conditionals by using array */
142static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
143static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 144static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 145
92f965e8
SH		 146/* This driver supports yukon2 chipset only */
147static const char *yukon2_name[] = {
148 "XL", /* 0xb3 */
149 "EC Ultra", /* 0xb4 */
93745494 150 "Extreme", /* 0xb5 */
92f965e8
SH		 151 "EC", /* 0xb6 */
152 "FE", /* 0xb7 */
793b883e
SH		 153};
154
793b883e 155/* Access to external PHY */
ef743d33 156static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 157{
158 int i;
159
160 gma_write16(hw, port, GM_SMI_DATA, val);
161 gma_write16(hw, port, GM_SMI_CTRL,
162 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
163
164 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 165 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 166 return 0;
793b883e 167 udelay(1);
cd28ab6a 168 }
ef743d33 169
793b883e 170 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 171 return -ETIMEDOUT;
cd28ab6a
SH		 172}
173
ef743d33 174static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 175{
176 int i;
177
793b883e 178 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 179 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
180
181 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 182 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
183 *val = gma_read16(hw, port, GM_SMI_DATA);
184 return 0;
185 }
186
793b883e 187 udelay(1);
cd28ab6a
SH		 188 }
189
ef743d33
SH		 190 return -ETIMEDOUT;
191}
192
193static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
194{
195 u16 v;
196
197 if (__gm_phy_read(hw, port, reg, &v) != 0)
198 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
199 return v;
cd28ab6a
SH		 200}
201
5afa0a9c 202
ae306cca
SH		 203static void sky2_power_on(struct sky2_hw *hw)
204{
205 /* switch power to VCC (WA for VAUX problem) */
206 sky2_write8(hw, B0_POWER_CTRL,
207 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
5afa0a9c 208
ae306cca
SH		 209 /* disable Core Clock Division, */
210 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
d3bcfbeb 211
ae306cca
SH		 212 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
213 /* enable bits are inverted */
214 sky2_write8(hw, B2_Y2_CLK_GATE,
215 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
216 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
217 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
218 else
219 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
977bdf06 220
93745494 221 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
ae306cca 222 u32 reg1;
5afa0a9c 223
ae306cca
SH		 224 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
225 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
226 reg1 &= P_ASPM_CONTROL_MSK;
227 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
228 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
5afa0a9c 229 }
ae306cca 230}
5afa0a9c 231
ae306cca
SH		 232static void sky2_power_aux(struct sky2_hw *hw)
233{
234 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
236 else
237 /* enable bits are inverted */
238 sky2_write8(hw, B2_Y2_CLK_GATE,
239 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
240 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
241 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
242
243 /* switch power to VAUX */
244 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
245 sky2_write8(hw, B0_POWER_CTRL,
246 (PC_VAUX_ENA | PC_VCC_ENA |
247 PC_VAUX_ON | PC_VCC_OFF));
5afa0a9c
SH		 248}
249
d3bcfbeb 250static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 251{
252 u16 reg;
253
254 /* disable all GMAC IRQ's */
255 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
256 /* disable PHY IRQs */
257 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 258
cd28ab6a
SH		 259 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
260 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
261 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
262 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
263
264 reg = gma_read16(hw, port, GM_RX_CTRL);
265 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
266 gma_write16(hw, port, GM_RX_CTRL, reg);
267}
268
16ad91e1
SH		 269/* flow control to advertise bits */
270static const u16 copper_fc_adv[] = {
271 [FC_NONE] = 0,
272 [FC_TX] = PHY_M_AN_ASP,
273 [FC_RX] = PHY_M_AN_PC,
274 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
275};
276
277/* flow control to advertise bits when using 1000BaseX */
278static const u16 fiber_fc_adv[] = {
279 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
280 [FC_TX] = PHY_M_P_ASYM_MD_X,
281 [FC_RX] = PHY_M_P_SYM_MD_X,
282 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
283};
284
285/* flow control to GMA disable bits */
286static const u16 gm_fc_disable[] = {
287 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
288 [FC_TX] = GM_GPCR_FC_RX_DIS,
289 [FC_RX] = GM_GPCR_FC_TX_DIS,
290 [FC_BOTH] = 0,
291};
292
293
cd28ab6a
SH		 294static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
295{
296 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 297 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 298
93745494
SH		 299 if (sky2->autoneg == AUTONEG_ENABLE
300 && !(hw->chip_id == CHIP_ID_YUKON_XL
301 || hw->chip_id == CHIP_ID_YUKON_EC_U
302 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 303 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
304
305 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 306 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 307 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
308
309 if (hw->chip_id == CHIP_ID_YUKON_EC)
310 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
311 else
312 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
313
314 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
315 }
316
317 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 318 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 319 if (hw->chip_id == CHIP_ID_YUKON_FE) {
320 /* enable automatic crossover */
321 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
322 } else {
323 /* disable energy detect */
324 ctrl &= ~PHY_M_PC_EN_DET_MSK;
325
326 /* enable automatic crossover */
327 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
328
93745494
SH		 329 if (sky2->autoneg == AUTONEG_ENABLE
330 && (hw->chip_id == CHIP_ID_YUKON_XL
331 || hw->chip_id == CHIP_ID_YUKON_EC_U
332 || hw->chip_id == CHIP_ID_YUKON_EX)) {
cd28ab6a
SH		 333 ctrl &= ~PHY_M_PC_DSC_MSK;
334 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
335 }
336 }
cd28ab6a
SH		 337 } else {
338 /* workaround for deviation #4.88 (CRC errors) */
339 /* disable Automatic Crossover */
340
341 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 342 }
cd28ab6a 343
b89165f2
SH		 344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345
346 /* special setup for PHY 88E1112 Fiber */
347 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
348 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 349
b89165f2
SH		 350 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
351 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
352 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 ctrl &= ~PHY_M_MAC_MD_MSK;
354 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
355 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
356
357 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 358 /* select page 1 to access Fiber registers */
359 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 360
361 /* for SFP-module set SIGDET polarity to low */
362 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
363 ctrl |= PHY_M_FIB_SIGD_POL;
364 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 365 }
b89165f2
SH		 366
367 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 368 }
369
7800fddc 370 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 371 ct1000 = 0;
372 adv = PHY_AN_CSMA;
2eaba1a2 373 reg = 0;
cd28ab6a
SH		 374
375 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 376 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 377 if (sky2->advertising & ADVERTISED_1000baseT_Full)
378 ct1000 |= PHY_M_1000C_AFD;
379 if (sky2->advertising & ADVERTISED_1000baseT_Half)
380 ct1000 |= PHY_M_1000C_AHD;
381 if (sky2->advertising & ADVERTISED_100baseT_Full)
382 adv |= PHY_M_AN_100_FD;
383 if (sky2->advertising & ADVERTISED_100baseT_Half)
384 adv |= PHY_M_AN_100_HD;
385 if (sky2->advertising & ADVERTISED_10baseT_Full)
386 adv |= PHY_M_AN_10_FD;
387 if (sky2->advertising & ADVERTISED_10baseT_Half)
388 adv |= PHY_M_AN_10_HD;
709c6e7b 389
16ad91e1 390 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 391 } else { /* special defines for FIBER (88E1040S only) */
392 if (sky2->advertising & ADVERTISED_1000baseT_Full)
393 adv |= PHY_M_AN_1000X_AFD;
394 if (sky2->advertising & ADVERTISED_1000baseT_Half)
395 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 396
16ad91e1 397 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 398 }
cd28ab6a
SH		 399
400 /* Restart Auto-negotiation */
401 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
402 } else {
403 /* forced speed/duplex settings */
404 ct1000 = PHY_M_1000C_MSE;
405
2eaba1a2
SH		 406 /* Disable auto update for duplex flow control and speed */
407 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 408
409 switch (sky2->speed) {
410 case SPEED_1000:
411 ctrl |= PHY_CT_SP1000;
2eaba1a2 412 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 413 break;
414 case SPEED_100:
415 ctrl |= PHY_CT_SP100;
2eaba1a2 416 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 417 break;
418 }
419
2eaba1a2
SH		 420 if (sky2->duplex == DUPLEX_FULL) {
421 reg |= GM_GPCR_DUP_FULL;
422 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 423 } else if (sky2->speed < SPEED_1000)
424 sky2->flow_mode = FC_NONE;
2eaba1a2 425
2eaba1a2 426
16ad91e1 427 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 428
429 /* Forward pause packets to GMAC? */
16ad91e1 430 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 431 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
432 else
433 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 434 }
435
2eaba1a2
SH		 436 gma_write16(hw, port, GM_GP_CTRL, reg);
437
cd28ab6a
SH		 438 if (hw->chip_id != CHIP_ID_YUKON_FE)
439 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
440
441 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
442 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
443
444 /* Setup Phy LED's */
445 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
446 ledover = 0;
447
448 switch (hw->chip_id) {
449 case CHIP_ID_YUKON_FE:
450 /* on 88E3082 these bits are at 11..9 (shifted left) */
451 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
452
453 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
454
455 /* delete ACT LED control bits */
456 ctrl &= ~PHY_M_FELP_LED1_MSK;
457 /* change ACT LED control to blink mode */
458 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
459 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
460 break;
461
462 case CHIP_ID_YUKON_XL:
793b883e 463 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 464
465 /* select page 3 to access LED control register */
466 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
467
468 /* set LED Function Control register */
ed6d32c7
SH		 469 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
470 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
471 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
472 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
473 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 474
475 /* set Polarity Control register */
476 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 477 (PHY_M_POLC_LS1_P_MIX(4) |
478 PHY_M_POLC_IS0_P_MIX(4) |
479 PHY_M_POLC_LOS_CTRL(2) |
480 PHY_M_POLC_INIT_CTRL(2) |
481 PHY_M_POLC_STA1_CTRL(2) |
482 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 483
484 /* restore page register */
793b883e 485 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 486 break;
93745494 487
ed6d32c7 488 case CHIP_ID_YUKON_EC_U:
93745494 489 case CHIP_ID_YUKON_EX:
ed6d32c7
SH		 490 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
491
492 /* select page 3 to access LED control register */
493 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
494
495 /* set LED Function Control register */
496 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
497 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
498 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
499 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
500 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
501
502 /* set Blink Rate in LED Timer Control Register */
503 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
504 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
505 /* restore page register */
506 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
507 break;
cd28ab6a
SH		 508
509 default:
510 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
511 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
512 /* turn off the Rx LED (LED_RX) */
0efdf262 513 ledover &= ~PHY_M_LED_MO_RX;
cd28ab6a
SH		 514 }
515
9467a8fc
SH		 516 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
517 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
977bdf06 518 /* apply fixes in PHY AFE */
ed6d32c7
SH		 519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
520
977bdf06 521 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 522 gm_phy_write(hw, port, 0x18, 0xaa99);
523 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 524
977bdf06 525 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 526 gm_phy_write(hw, port, 0x18, 0xa204);
527 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 528
529 /* set page register to 0 */
9467a8fc 530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
93745494 531 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
977bdf06 532 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 533
977bdf06
SH		 534 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
535 /* turn on 100 Mbps LED (LED_LINK100) */
0efdf262 536 ledover |= PHY_M_LED_MO_100;
977bdf06 537 }
cd28ab6a 538
977bdf06
SH		 539 if (ledover)
540 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
541
542 }
2eaba1a2 543
d571b694 544 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 545 if (sky2->autoneg == AUTONEG_ENABLE)
546 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
547 else
548 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
549}
550
d3bcfbeb
SH		 551static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
552{
553 u32 reg1;
554 static const u32 phy_power[]
555 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
556
557 /* looks like this XL is back asswards .. */
558 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
559 onoff = !onoff;
560
aed2cec4 561 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
d3bcfbeb 562 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 563 if (onoff)
564 /* Turn off phy power saving */
565 reg1 &= ~phy_power[port];
566 else
567 reg1 |= phy_power[port];
568
569 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 570 sky2_pci_read32(hw, PCI_DEV_REG1);
aed2cec4 571 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
d3bcfbeb
SH		 572 udelay(100);
573}
574
1b537565
SH		 575/* Force a renegotiation */
576static void sky2_phy_reinit(struct sky2_port *sky2)
577{
e07b1aa8 578 spin_lock_bh(&sky2->phy_lock);
1b537565 579 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 580 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 581}
582
e3173832
SH		 583/* Put device in state to listen for Wake On Lan */
584static void sky2_wol_init(struct sky2_port *sky2)
585{
586 struct sky2_hw *hw = sky2->hw;
587 unsigned port = sky2->port;
588 enum flow_control save_mode;
589 u16 ctrl;
590 u32 reg1;
591
592 /* Bring hardware out of reset */
593 sky2_write16(hw, B0_CTST, CS_RST_CLR);
594 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
595
596 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
597 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
598
599 /* Force to 10/100
600 * sky2_reset will re-enable on resume
601 */
602 save_mode = sky2->flow_mode;
603 ctrl = sky2->advertising;
604
605 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
606 sky2->flow_mode = FC_NONE;
607 sky2_phy_power(hw, port, 1);
608 sky2_phy_reinit(sky2);
609
610 sky2->flow_mode = save_mode;
611 sky2->advertising = ctrl;
612
613 /* Set GMAC to no flow control and auto update for speed/duplex */
614 gma_write16(hw, port, GM_GP_CTRL,
615 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
616 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
617
618 /* Set WOL address */
619 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
620 sky2->netdev->dev_addr, ETH_ALEN);
621
622 /* Turn on appropriate WOL control bits */
623 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
624 ctrl = 0;
625 if (sky2->wol & WAKE_PHY)
626 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
627 else
628 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
629
630 if (sky2->wol & WAKE_MAGIC)
631 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
632 else
633 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
634
635 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
636 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
637
638 /* Turn on legacy PCI-Express PME mode */
639 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
640 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
641 reg1 |= PCI_Y2_PME_LEGACY;
642 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
643 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
644
645 /* block receiver */
646 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
647
648}
649
cd28ab6a
SH		 650static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
651{
652 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
653 u16 reg;
654 int i;
655 const u8 *addr = hw->dev[port]->dev_addr;
656
42eeea01
SH		 657 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
658 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 659
660 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
661
793b883e 662 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 663 /* WA DEV_472 -- looks like crossed wires on port 2 */
664 /* clear GMAC 1 Control reset */
665 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
666 do {
667 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
668 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
669 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
670 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
671 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
672 }
673
793b883e 674 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 675
2eaba1a2
SH		 676 /* Enable Transmit FIFO Underrun */
677 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
678
e07b1aa8 679 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 680 sky2_phy_init(hw, port);
e07b1aa8 681 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 682
683 /* MIB clear */
684 reg = gma_read16(hw, port, GM_PHY_ADDR);
685 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
686
43f2f104
SH		 687 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
688 gma_read16(hw, port, i);
cd28ab6a
SH		 689 gma_write16(hw, port, GM_PHY_ADDR, reg);
690
691 /* transmit control */
692 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
693
694 /* receive control reg: unicast + multicast + no FCS */
695 gma_write16(hw, port, GM_RX_CTRL,
793b883e 696 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 697
698 /* transmit flow control */
699 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
700
701 /* transmit parameter */
702 gma_write16(hw, port, GM_TX_PARAM,
703 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
704 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
705 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
706 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
707
708 /* serial mode register */
709 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 710 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 711
6b1a3aef 712 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 713 reg |= GM_SMOD_JUMBO_ENA;
714
715 gma_write16(hw, port, GM_SERIAL_MODE, reg);
716
cd28ab6a
SH		 717 /* virtual address for data */
718 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
719
793b883e
SH		 720 /* physical address: used for pause frames */
721 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
722
723 /* ignore counter overflows */
cd28ab6a
SH		 724 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
725 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
726 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
727
728 /* Configure Rx MAC FIFO */
729 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 730 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
731 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 732
d571b694 733 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 734 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 735
8df9a876
SH		 736 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
737 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
cd28ab6a
SH		 738
739 /* Configure Tx MAC FIFO */
740 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
741 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0 742
93745494 743 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
8df9a876 744 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
5a5b1ea0
SH		 745 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
746 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
747 /* set Tx GMAC FIFO Almost Empty Threshold */
748 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
749 /* Disable Store & Forward mode for TX */
750 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
751 }
752 }
753
cd28ab6a
SH		 754}
755
67712901
SH		 756/* Assign Ram Buffer allocation to queue */
757static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
cd28ab6a 758{
67712901
SH		 759 u32 end;
760
761 /* convert from K bytes to qwords used for hw register */
762 start *= 1024/8;
763 space *= 1024/8;
764 end = start + space - 1;
793b883e 765
cd28ab6a
SH		 766 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
767 sky2_write32(hw, RB_ADDR(q, RB_START), start);
768 sky2_write32(hw, RB_ADDR(q, RB_END), end);
769 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
770 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
771
772 if (q == Q_R1 || q == Q_R2) {
1c28f6ba 773 u32 tp = space - space/4;
793b883e 774
1c28f6ba
SH		 775 /* On receive queue's set the thresholds
776 * give receiver priority when > 3/4 full
777 * send pause when down to 2K
778 */
779 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
780 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 781
1c28f6ba
SH		 782 tp = space - 2048/8;
783 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
784 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 785 } else {
786 /* Enable store & forward on Tx queue's because
787 * Tx FIFO is only 1K on Yukon
788 */
789 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
790 }
791
792 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 793 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 794}
795
cd28ab6a 796/* Setup Bus Memory Interface */
af4ed7e6 797static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 798{
799 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
800 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
801 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 802 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 803}
804
cd28ab6a
SH		 805/* Setup prefetch unit registers. This is the interface between
806 * hardware and driver list elements
807 */
8cc048e3 808static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 809 u64 addr, u32 last)
810{
cd28ab6a
SH		 811 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
812 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
813 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
814 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
815 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
816 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 817
818 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 819}
820
793b883e
SH		 821static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
822{
823 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
824
cb5d9547 825 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 826 le->ctrl = 0;
793b883e
SH		 827 return le;
828}
cd28ab6a 829
291ea614
SH		 830static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
831 struct sky2_tx_le *le)
832{
833 return sky2->tx_ring + (le - sky2->tx_le);
834}
835
290d4de5
SH		 836/* Update chip's next pointer */
837static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 838{
98232f85 839 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 840 wmb();
98232f85
SH		 841 sky2_write16(hw, q, idx);
842 sky2_read16(hw, q);
cd28ab6a
SH		 843}
844
793b883e 845
cd28ab6a
SH		 846static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
847{
848 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 849 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 850 le->ctrl = 0;
cd28ab6a
SH		 851 return le;
852}
853
a018e330
SH		 854/* Return high part of DMA address (could be 32 or 64 bit) */
855static inline u32 high32(dma_addr_t a)
856{
a036119f 857 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 858}
859
14d0263f
SH		 860/* Build description to hardware for one receive segment */
861static void sky2_rx_add(struct sky2_port *sky2, u8 op,
862 dma_addr_t map, unsigned len)
cd28ab6a
SH		 863{
864 struct sky2_rx_le *le;
734d1868 865 u32 hi = high32(map);
cd28ab6a 866
793b883e 867 if (sky2->rx_addr64 != hi) {
cd28ab6a 868 le = sky2_next_rx(sky2);
793b883e 869 le->addr = cpu_to_le32(hi);
cd28ab6a 870 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 871 sky2->rx_addr64 = high32(map + len);
cd28ab6a 872 }
793b883e 873
cd28ab6a 874 le = sky2_next_rx(sky2);
734d1868
SH		 875 le->addr = cpu_to_le32((u32) map);
876 le->length = cpu_to_le16(len);
14d0263f 877 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 878}
879
14d0263f
SH		 880/* Build description to hardware for one possibly fragmented skb */
881static void sky2_rx_submit(struct sky2_port *sky2,
882 const struct rx_ring_info *re)
883{
884 int i;
885
886 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
887
888 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
889 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
890}
891
892
893static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
894 unsigned size)
895{
896 struct sk_buff *skb = re->skb;
897 int i;
898
899 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
900 pci_unmap_len_set(re, data_size, size);
901
902 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
903 re->frag_addr[i] = pci_map_page(pdev,
904 skb_shinfo(skb)->frags[i].page,
905 skb_shinfo(skb)->frags[i].page_offset,
906 skb_shinfo(skb)->frags[i].size,
907 PCI_DMA_FROMDEVICE);
908}
909
910static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
911{
912 struct sk_buff *skb = re->skb;
913 int i;
914
915 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
916 PCI_DMA_FROMDEVICE);
917
918 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
919 pci_unmap_page(pdev, re->frag_addr[i],
920 skb_shinfo(skb)->frags[i].size,
921 PCI_DMA_FROMDEVICE);
922}
793b883e 923
cd28ab6a
SH		 924/* Tell chip where to start receive checksum.
925 * Actually has two checksums, but set both same to avoid possible byte
926 * order problems.
927 */
793b883e 928static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 929{
930 struct sky2_rx_le *le;
931
cd28ab6a 932 le = sky2_next_rx(sky2);
f65b138c 933 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 934 le->ctrl = 0;
935 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 936
793b883e
SH		 937 sky2_write32(sky2->hw,
938 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
939 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 940
941}
942
6b1a3aef
SH		 943/*
944 * The RX Stop command will not work for Yukon-2 if the BMU does not
945 * reach the end of packet and since we can't make sure that we have
946 * incoming data, we must reset the BMU while it is not doing a DMA
947 * transfer. Since it is possible that the RX path is still active,
948 * the RX RAM buffer will be stopped first, so any possible incoming
949 * data will not trigger a DMA. After the RAM buffer is stopped, the
950 * BMU is polled until any DMA in progress is ended and only then it
951 * will be reset.
952 */
953static void sky2_rx_stop(struct sky2_port *sky2)
954{
955 struct sky2_hw *hw = sky2->hw;
956 unsigned rxq = rxqaddr[sky2->port];
957 int i;
958
959 /* disable the RAM Buffer receive queue */
960 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
961
962 for (i = 0; i < 0xffff; i++)
963 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
964 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
965 goto stopped;
966
967 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
968 sky2->netdev->name);
969stopped:
970 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
971
972 /* reset the Rx prefetch unit */
973 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
974}
793b883e 975
d571b694 976/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 977static void sky2_rx_clean(struct sky2_port *sky2)
978{
979 unsigned i;
980
981 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 982 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 983 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 984
985 if (re->skb) {
14d0263f 986 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 987 kfree_skb(re->skb);
988 re->skb = NULL;
989 }
990 }
991}
992
ef743d33
SH		 993/* Basic MII support */
994static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
995{
996 struct mii_ioctl_data *data = if_mii(ifr);
997 struct sky2_port *sky2 = netdev_priv(dev);
998 struct sky2_hw *hw = sky2->hw;
999 int err = -EOPNOTSUPP;
1000
1001 if (!netif_running(dev))
1002 return -ENODEV; /* Phy still in reset */
1003
d89e1343 1004 switch (cmd) {
ef743d33
SH		 1005 case SIOCGMIIPHY:
1006 data->phy_id = PHY_ADDR_MARV;
1007
1008 /* fallthru */
1009 case SIOCGMIIREG: {
1010 u16 val = 0;
91c86df5 1011
e07b1aa8 1012 spin_lock_bh(&sky2->phy_lock);
ef743d33 1013 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 1014 spin_unlock_bh(&sky2->phy_lock);
91c86df5 1015
ef743d33
SH		 1016 data->val_out = val;
1017 break;
1018 }
1019
1020 case SIOCSMIIREG:
1021 if (!capable(CAP_NET_ADMIN))
1022 return -EPERM;
1023
e07b1aa8 1024 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 1025 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1026 data->val_in);
e07b1aa8 1027 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 1028 break;
1029 }
1030 return err;
1031}
1032
d1f13708
SH		 1033#ifdef SKY2_VLAN_TAG_USED
1034static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1035{
1036 struct sky2_port *sky2 = netdev_priv(dev);
1037 struct sky2_hw *hw = sky2->hw;
1038 u16 port = sky2->port;
d1f13708 1039
2bb8c262 1040 netif_tx_lock_bh(dev);
d1f13708
SH		 1041
1042 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1043 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1044 sky2->vlgrp = grp;
1045
2bb8c262 1046 netif_tx_unlock_bh(dev);
d1f13708
SH		 1047}
1048
1049static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1050{
1051 struct sky2_port *sky2 = netdev_priv(dev);
1052 struct sky2_hw *hw = sky2->hw;
1053 u16 port = sky2->port;
d1f13708 1054
2bb8c262 1055 netif_tx_lock_bh(dev);
d1f13708
SH		 1056
1057 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1058 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
5c15bdec 1059 vlan_group_set_device(sky2->vlgrp, vid, NULL);
d1f13708 1060
2bb8c262 1061 netif_tx_unlock_bh(dev);
d1f13708
SH		 1062}
1063#endif
1064
82788c7a 1065/*
14d0263f
SH		 1066 * Allocate an skb for receiving. If the MTU is large enough
1067 * make the skb non-linear with a fragment list of pages.
1068 *
82788c7a
SH		 1069 * It appears the hardware has a bug in the FIFO logic that
1070 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1071 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1072 * aligned except if slab debugging is enabled.
82788c7a 1073 */
14d0263f 1074static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1075{
1076 struct sk_buff *skb;
14d0263f
SH		 1077 unsigned long p;
1078 int i;
82788c7a 1079
14d0263f
SH		 1080 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1081 if (!skb)
1082 goto nomem;
1083
1084 p = (unsigned long) skb->data;
1085 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1086
1087 for (i = 0; i < sky2->rx_nfrags; i++) {
1088 struct page *page = alloc_page(GFP_ATOMIC);
1089
1090 if (!page)
1091 goto free_partial;
1092 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1093 }
1094
1095 return skb;
14d0263f
SH		 1096free_partial:
1097 kfree_skb(skb);
1098nomem:
1099 return NULL;
82788c7a
SH		 1100}
1101
cd28ab6a
SH		 1102/*
1103 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1104 * Normal case this ends up creating one list element for skb
1105 * in the receive ring. Worst case if using large MTU and each
1106 * allocation falls on a different 64 bit region, that results
1107 * in 6 list elements per ring entry.
1108 * One element is used for checksum enable/disable, and one
1109 * extra to avoid wrap.
cd28ab6a 1110 */
6b1a3aef 1111static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1112{
6b1a3aef 1113 struct sky2_hw *hw = sky2->hw;
14d0263f 1114 struct rx_ring_info *re;
6b1a3aef 1115 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1116 unsigned i, size, space, thresh;
cd28ab6a 1117
6b1a3aef 1118 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1119 sky2_qset(hw, rxq);
977bdf06 1120
c3905bc4
SH		 1121 /* On PCI express lowering the watermark gives better performance */
1122 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1123 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1124
1125 /* These chips have no ram buffer?
1126 * MAC Rx RAM Read is controlled by hardware */
8df9a876 1127 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
c3905bc4
SH		 1128 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1129 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
977bdf06 1130 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
977bdf06 1131
6b1a3aef
SH		 1132 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1133
1134 rx_set_checksum(sky2);
14d0263f
SH		 1135
1136 /* Space needed for frame data + headers rounded up */
1137 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1138 + 8;
1139
1140 /* Stopping point for hardware truncation */
1141 thresh = (size - 8) / sizeof(u32);
1142
1143 /* Account for overhead of skb - to avoid order > 0 allocation */
1144 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1145 + sizeof(struct skb_shared_info);
1146
1147 sky2->rx_nfrags = space >> PAGE_SHIFT;
1148 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1149
1150 if (sky2->rx_nfrags != 0) {
1151 /* Compute residue after pages */
1152 space = sky2->rx_nfrags << PAGE_SHIFT;
1153
1154 if (space < size)
1155 size -= space;
1156 else
1157 size = 0;
1158
1159 /* Optimize to handle small packets and headers */
1160 if (size < copybreak)
1161 size = copybreak;
1162 if (size < ETH_HLEN)
1163 size = ETH_HLEN;
1164 }
1165 sky2->rx_data_size = size;
1166
1167 /* Fill Rx ring */
793b883e 1168 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1169 re = sky2->rx_ring + i;
cd28ab6a 1170
14d0263f 1171 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1172 if (!re->skb)
1173 goto nomem;
1174
14d0263f
SH		 1175 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1176 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1177 }
1178
a1433ac4
SH		 1179 /*
1180 * The receiver hangs if it receives frames larger than the
1181 * packet buffer. As a workaround, truncate oversize frames, but
1182 * the register is limited to 9 bits, so if you do frames > 2052
1183 * you better get the MTU right!
1184 */
a1433ac4
SH		 1185 if (thresh > 0x1ff)
1186 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1187 else {
1188 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1189 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1190 }
1191
6b1a3aef
SH		 1192 /* Tell chip about available buffers */
1193 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1194 return 0;
1195nomem:
1196 sky2_rx_clean(sky2);
1197 return -ENOMEM;
1198}
1199
1200/* Bring up network interface. */
1201static int sky2_up(struct net_device *dev)
1202{
1203 struct sky2_port *sky2 = netdev_priv(dev);
1204 struct sky2_hw *hw = sky2->hw;
1205 unsigned port = sky2->port;
67712901 1206 u32 ramsize, imask;
ee7abb04 1207 int cap, err = -ENOMEM;
843a46f4 1208 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1209
ee7abb04
SH		 1210 /*
1211 * On dual port PCI-X card, there is an problem where status
1212 * can be received out of order due to split transactions
843a46f4 1213 */
ee7abb04
SH		 1214 if (otherdev && netif_running(otherdev) &&
1215 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1216 struct sky2_port *osky2 = netdev_priv(otherdev);
1217 u16 cmd;
1218
1219 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1220 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1221 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1222
1223 sky2->rx_csum = 0;
1224 osky2->rx_csum = 0;
1225 }
843a46f4 1226
cd28ab6a
SH		 1227 if (netif_msg_ifup(sky2))
1228 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1229
1230 /* must be power of 2 */
1231 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1232 TX_RING_SIZE *
1233 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1234 &sky2->tx_le_map);
1235 if (!sky2->tx_le)
1236 goto err_out;
1237
6cdbbdf3 1238 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1239 GFP_KERNEL);
1240 if (!sky2->tx_ring)
1241 goto err_out;
1242 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1243
1244 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1245 &sky2->rx_le_map);
1246 if (!sky2->rx_le)
1247 goto err_out;
1248 memset(sky2->rx_le, 0, RX_LE_BYTES);
1249
291ea614 1250 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1251 GFP_KERNEL);
1252 if (!sky2->rx_ring)
1253 goto err_out;
1254
d3bcfbeb
SH		 1255 sky2_phy_power(hw, port, 1);
1256
cd28ab6a
SH		 1257 sky2_mac_init(hw, port);
1258
67712901
SH		 1259 /* Register is number of 4K blocks on internal RAM buffer. */
1260 ramsize = sky2_read8(hw, B2_E_0) * 4;
1261 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1c28f6ba 1262
67712901
SH		 1263 if (ramsize > 0) {
1264 u32 rxspace;
cd28ab6a 1265
67712901
SH		 1266 if (ramsize < 16)
1267 rxspace = ramsize / 2;
1268 else
1269 rxspace = 8 + (2*(ramsize - 16))/3;
cd28ab6a 1270
67712901
SH		 1271 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1272 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1273
1274 /* Make sure SyncQ is disabled */
1275 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1276 RB_RST_SET);
1277 }
793b883e 1278
af4ed7e6 1279 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1280
977bdf06 1281 /* Set almost empty threshold */
c2716fb4
SH		 1282 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1283 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1284 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1285
6b1a3aef
SH		 1286 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1287 TX_RING_SIZE - 1);
cd28ab6a 1288
6b1a3aef 1289 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1290 if (err)
1291 goto err_out;
1292
cd28ab6a 1293 /* Enable interrupts from phy/mac for port */
e07b1aa8 1294 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1295 imask |= portirq_msk[port];
e07b1aa8
SH		 1296 sky2_write32(hw, B0_IMSK, imask);
1297
cd28ab6a
SH		 1298 return 0;
1299
1300err_out:
1b537565 1301 if (sky2->rx_le) {
cd28ab6a
SH		 1302 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1303 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1304 sky2->rx_le = NULL;
1305 }
1306 if (sky2->tx_le) {
cd28ab6a
SH		 1307 pci_free_consistent(hw->pdev,
1308 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1309 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1310 sky2->tx_le = NULL;
1311 }
1312 kfree(sky2->tx_ring);
1313 kfree(sky2->rx_ring);
cd28ab6a 1314
1b537565
SH		 1315 sky2->tx_ring = NULL;
1316 sky2->rx_ring = NULL;
cd28ab6a
SH		 1317 return err;
1318}
1319
793b883e
SH		 1320/* Modular subtraction in ring */
1321static inline int tx_dist(unsigned tail, unsigned head)
1322{
cb5d9547 1323 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1324}
cd28ab6a 1325
793b883e
SH		 1326/* Number of list elements available for next tx */
1327static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1328{
793b883e 1329 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1330}
1331
793b883e 1332/* Estimate of number of transmit list elements required */
28bd181a 1333static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1334{
793b883e
SH		 1335 unsigned count;
1336
1337 count = sizeof(dma_addr_t) / sizeof(u32);
1338 count += skb_shinfo(skb)->nr_frags * count;
1339
89114afd 1340 if (skb_is_gso(skb))
793b883e
SH		 1341 ++count;
1342
84fa7933 1343 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1344 ++count;
1345
1346 return count;
cd28ab6a
SH		 1347}
1348
793b883e
SH		 1349/*
1350 * Put one packet in ring for transmit.
1351 * A single packet can generate multiple list elements, and
1352 * the number of ring elements will probably be less than the number
1353 * of list elements used.
1354 */
cd28ab6a
SH		 1355static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1356{
1357 struct sky2_port *sky2 = netdev_priv(dev);
1358 struct sky2_hw *hw = sky2->hw;
d1f13708 1359 struct sky2_tx_le *le = NULL;
6cdbbdf3 1360 struct tx_ring_info *re;
cd28ab6a
SH		 1361 unsigned i, len;
1362 dma_addr_t mapping;
1363 u32 addr64;
1364 u16 mss;
1365 u8 ctrl;
1366
2bb8c262
SH		 1367 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1368 return NETDEV_TX_BUSY;
cd28ab6a 1369
793b883e 1370 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1371 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1372 dev->name, sky2->tx_prod, skb->len);
1373
cd28ab6a
SH		 1374 len = skb_headlen(skb);
1375 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1376 addr64 = high32(mapping);
793b883e 1377
a018e330
SH		 1378 /* Send high bits if changed or crosses boundary */
1379 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1380 le = get_tx_le(sky2);
f65b138c 1381 le->addr = cpu_to_le32(addr64);
793b883e 1382 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1383 sky2->tx_addr64 = high32(mapping + len);
793b883e 1384 }
cd28ab6a
SH		 1385
1386 /* Check for TCP Segmentation Offload */
7967168c 1387 mss = skb_shinfo(skb)->gso_size;
793b883e 1388 if (mss != 0) {
cd28ab6a
SH		 1389 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1390 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1391 mss += ETH_HLEN;
1392
e07560cd
SH		 1393 if (mss != sky2->tx_last_mss) {
1394 le = get_tx_le(sky2);
f65b138c 1395 le->addr = cpu_to_le32(mss);
e07560cd 1396 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1397 sky2->tx_last_mss = mss;
1398 }
cd28ab6a
SH		 1399 }
1400
cd28ab6a 1401 ctrl = 0;
d1f13708
SH		 1402#ifdef SKY2_VLAN_TAG_USED
1403 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1404 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1405 if (!le) {
1406 le = get_tx_le(sky2);
f65b138c 1407 le->addr = 0;
d1f13708 1408 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1409 } else
1410 le->opcode |= OP_VLAN;
1411 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1412 ctrl |= INS_VLAN;
1413 }
1414#endif
1415
1416 /* Handle TCP checksum offload */
84fa7933 1417 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1418 unsigned offset = skb->h.raw - skb->data;
1419 u32 tcpsum;
1420
1421 tcpsum = offset << 16; /* sum start */
ff1dcadb 1422 tcpsum |= offset + skb->csum_offset; /* sum write */
cd28ab6a
SH		 1423
1424 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1425 if (skb->nh.iph->protocol == IPPROTO_UDP)
1426 ctrl |= UDPTCP;
1427
f65b138c
SH		 1428 if (tcpsum != sky2->tx_tcpsum) {
1429 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1430
1431 le = get_tx_le(sky2);
f65b138c 1432 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1433 le->length = 0; /* initial checksum value */
1434 le->ctrl = 1; /* one packet */
1435 le->opcode = OP_TCPLISW | HW_OWNER;
1436 }
cd28ab6a
SH		 1437 }
1438
1439 le = get_tx_le(sky2);
f65b138c 1440 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1441 le->length = cpu_to_le16(len);
1442 le->ctrl = ctrl;
793b883e 1443 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1444
291ea614 1445 re = tx_le_re(sky2, le);
cd28ab6a 1446 re->skb = skb;
6cdbbdf3 1447 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1448 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1449
1450 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1451 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1452
1453 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1454 frag->size, PCI_DMA_TODEVICE);
a036119f 1455 addr64 = high32(mapping);
793b883e
SH		 1456 if (addr64 != sky2->tx_addr64) {
1457 le = get_tx_le(sky2);
f65b138c 1458 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1459 le->ctrl = 0;
1460 le->opcode = OP_ADDR64 | HW_OWNER;
1461 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1462 }
1463
1464 le = get_tx_le(sky2);
f65b138c 1465 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1466 le->length = cpu_to_le16(frag->size);
1467 le->ctrl = ctrl;
793b883e 1468 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1469
291ea614
SH		 1470 re = tx_le_re(sky2, le);
1471 re->skb = skb;
1472 pci_unmap_addr_set(re, mapaddr, mapping);
1473 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1474 }
6cdbbdf3 1475
cd28ab6a
SH		 1476 le->ctrl |= EOP;
1477
97bda706
SH		 1478 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1479 netif_stop_queue(dev);
b19666d9 1480
290d4de5 1481 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1482
cd28ab6a
SH		 1483 dev->trans_start = jiffies;
1484 return NETDEV_TX_OK;
1485}
1486
cd28ab6a 1487/*
793b883e
SH		 1488 * Free ring elements from starting at tx_cons until "done"
1489 *
1490 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1491 * buffers so make sure not to free skb to early.
cd28ab6a 1492 */
d11c13e7 1493static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1494{
d11c13e7 1495 struct net_device *dev = sky2->netdev;
af2a58ac 1496 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1497 unsigned idx;
cd28ab6a 1498
0e3ff6aa 1499 BUG_ON(done >= TX_RING_SIZE);
2224795d 1500
291ea614
SH		 1501 for (idx = sky2->tx_cons; idx != done;
1502 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1503 struct sky2_tx_le *le = sky2->tx_le + idx;
1504 struct tx_ring_info *re = sky2->tx_ring + idx;
1505
1506 switch(le->opcode & ~HW_OWNER) {
1507 case OP_LARGESEND:
1508 case OP_PACKET:
1509 pci_unmap_single(pdev,
1510 pci_unmap_addr(re, mapaddr),
1511 pci_unmap_len(re, maplen),
1512 PCI_DMA_TODEVICE);
af2a58ac 1513 break;
291ea614
SH		 1514 case OP_BUFFER:
1515 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1516 pci_unmap_len(re, maplen),
734d1868 1517 PCI_DMA_TODEVICE);
291ea614
SH		 1518 break;
1519 }
1520
1521 if (le->ctrl & EOP) {
1522 if (unlikely(netif_msg_tx_done(sky2)))
1523 printk(KERN_DEBUG "%s: tx done %u\n",
1524 dev->name, idx);
2bf56fe2 1525 sky2->net_stats.tx_packets++;
1526 sky2->net_stats.tx_bytes += re->skb->len;
1527
794b2bd2 1528 dev_kfree_skb_any(re->skb);
cd28ab6a
SH		 1529 }
1530
291ea614 1531 le->opcode = 0; /* paranoia */
793b883e 1532 }
793b883e 1533
291ea614 1534 sky2->tx_cons = idx;
22e11703 1535 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1536 netif_wake_queue(dev);
cd28ab6a
SH		 1537}
1538
1539/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1540static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1541{
2bb8c262
SH		 1542 struct sky2_port *sky2 = netdev_priv(dev);
1543
1544 netif_tx_lock_bh(dev);
d11c13e7 1545 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1546 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1547}
1548
1549/* Network shutdown */
1550static int sky2_down(struct net_device *dev)
1551{
1552 struct sky2_port *sky2 = netdev_priv(dev);
1553 struct sky2_hw *hw = sky2->hw;
1554 unsigned port = sky2->port;
1555 u16 ctrl;
e07b1aa8 1556 u32 imask;
cd28ab6a 1557
1b537565
SH		 1558 /* Never really got started! */
1559 if (!sky2->tx_le)
1560 return 0;
1561
cd28ab6a
SH		 1562 if (netif_msg_ifdown(sky2))
1563 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1564
018d1c66 1565 /* Stop more packets from being queued */
cd28ab6a 1566 netif_stop_queue(dev);
9a87240c 1567 netif_carrier_off(dev);
cd28ab6a 1568
ebc646f6
SH		 1569 /* Disable port IRQ */
1570 imask = sky2_read32(hw, B0_IMSK);
1571 imask &= ~portirq_msk[port];
1572 sky2_write32(hw, B0_IMSK, imask);
1573
25d82d7a
SH		 1574 /*
1575 * Both ports share the NAPI poll on port 0, so if necessary undo the
1576 * the disable that is done in dev_close.
1577 */
1578 if (sky2->port == 0 && hw->ports > 1)
1579 netif_poll_enable(dev);
1580
d3bcfbeb 1581 sky2_gmac_reset(hw, port);
793b883e 1582
cd28ab6a
SH		 1583 /* Stop transmitter */
1584 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1585 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1586
1587 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1588 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1589
c2716fb4
SH		 1590 /* WA for dev. #4.209 */
1591 if (hw->chip_id == CHIP_ID_YUKON_EC_U
8df9a876 1592 && (hw->chip_rev == CHIP_REV_YU_EC_U_A1 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
c2716fb4
SH		 1593 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1594 sky2->speed != SPEED_1000 ?
1595 TX_STFW_ENA : TX_STFW_DIS);
1596
cd28ab6a 1597 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1598 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1599 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1600
1601 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1602
1603 /* Workaround shared GMAC reset */
793b883e
SH		 1604 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1605 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1606 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1607
1608 /* Disable Force Sync bit and Enable Alloc bit */
1609 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1610 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1611
1612 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1613 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1614 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1615
1616 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1617 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1618 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1619
1620 /* Reset the Tx prefetch units */
1621 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1622 PREF_UNIT_RST_SET);
1623
1624 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1625
6b1a3aef 1626 sky2_rx_stop(sky2);
cd28ab6a
SH		 1627
1628 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1629 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1630
d3bcfbeb
SH		 1631 sky2_phy_power(hw, port, 0);
1632
d571b694 1633 /* turn off LED's */
cd28ab6a
SH		 1634 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1635
018d1c66
SH		 1636 synchronize_irq(hw->pdev->irq);
1637
2bb8c262 1638 sky2_tx_clean(dev);
cd28ab6a
SH		 1639 sky2_rx_clean(sky2);
1640
1641 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1642 sky2->rx_le, sky2->rx_le_map);
1643 kfree(sky2->rx_ring);
1644
1645 pci_free_consistent(hw->pdev,
1646 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1647 sky2->tx_le, sky2->tx_le_map);
1648 kfree(sky2->tx_ring);
1649
1b537565
SH		 1650 sky2->tx_le = NULL;
1651 sky2->rx_le = NULL;
1652
1653 sky2->rx_ring = NULL;
1654 sky2->tx_ring = NULL;
1655
cd28ab6a
SH		 1656 return 0;
1657}
1658
1659static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1660{
b89165f2 1661 if (!sky2_is_copper(hw))
793b883e
SH		 1662 return SPEED_1000;
1663
cd28ab6a
SH		 1664 if (hw->chip_id == CHIP_ID_YUKON_FE)
1665 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1666
1667 switch (aux & PHY_M_PS_SPEED_MSK) {
1668 case PHY_M_PS_SPEED_1000:
1669 return SPEED_1000;
1670 case PHY_M_PS_SPEED_100:
1671 return SPEED_100;
1672 default:
1673 return SPEED_10;
1674 }
1675}
1676
1677static void sky2_link_up(struct sky2_port *sky2)
1678{
1679 struct sky2_hw *hw = sky2->hw;
1680 unsigned port = sky2->port;
1681 u16 reg;
16ad91e1
SH		 1682 static const char *fc_name[] = {
1683 [FC_NONE] = "none",
1684 [FC_TX] = "tx",
1685 [FC_RX] = "rx",
1686 [FC_BOTH] = "both",
1687 };
cd28ab6a 1688
cd28ab6a 1689 /* enable Rx/Tx */
2eaba1a2 1690 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1691 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1692 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1693
1694 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1695
1696 netif_carrier_on(sky2->netdev);
1697 netif_wake_queue(sky2->netdev);
1698
1699 /* Turn on link LED */
793b883e 1700 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1701 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1702
93745494
SH		 1703 if (hw->chip_id == CHIP_ID_YUKON_XL
1704 || hw->chip_id == CHIP_ID_YUKON_EC_U
1705 || hw->chip_id == CHIP_ID_YUKON_EX) {
793b883e 1706 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1707 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1708
1709 switch(sky2->speed) {
1710 case SPEED_10:
1711 led |= PHY_M_LEDC_INIT_CTRL(7);
1712 break;
1713
1714 case SPEED_100:
1715 led |= PHY_M_LEDC_STA1_CTRL(7);
1716 break;
1717
1718 case SPEED_1000:
1719 led |= PHY_M_LEDC_STA0_CTRL(7);
1720 break;
1721 }
793b883e
SH		 1722
1723 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1724 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1725 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1726 }
1727
cd28ab6a
SH		 1728 if (netif_msg_link(sky2))
1729 printk(KERN_INFO PFX
d571b694 1730 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1731 sky2->netdev->name, sky2->speed,
1732 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1733 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1734}
1735
1736static void sky2_link_down(struct sky2_port *sky2)
1737{
1738 struct sky2_hw *hw = sky2->hw;
1739 unsigned port = sky2->port;
1740 u16 reg;
1741
1742 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1743
1744 reg = gma_read16(hw, port, GM_GP_CTRL);
1745 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1746 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1747
cd28ab6a
SH		 1748 netif_carrier_off(sky2->netdev);
1749 netif_stop_queue(sky2->netdev);
1750
1751 /* Turn on link LED */
1752 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1753
1754 if (netif_msg_link(sky2))
1755 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1756
cd28ab6a
SH		 1757 sky2_phy_init(hw, port);
1758}
1759
16ad91e1
SH		 1760static enum flow_control sky2_flow(int rx, int tx)
1761{
1762 if (rx)
1763 return tx ? FC_BOTH : FC_RX;
1764 else
1765 return tx ? FC_TX : FC_NONE;
1766}
1767
793b883e
SH		 1768static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1769{
1770 struct sky2_hw *hw = sky2->hw;
1771 unsigned port = sky2->port;
da4c1ff4 1772 u16 advert, lpa;
793b883e 1773
da4c1ff4 1774 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
793b883e 1775 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
793b883e
SH		 1776 if (lpa & PHY_M_AN_RF) {
1777 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1778 return -1;
1779 }
1780
793b883e
SH		 1781 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1782 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1783 sky2->netdev->name);
1784 return -1;
1785 }
1786
793b883e 1787 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1788 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e 1789
da4c1ff4
SH		 1790 /* Since the pause result bits seem to in different positions on
1791 * different chips. look at registers.
1792 */
1793 if (!sky2_is_copper(hw)) {
1794 /* Shift for bits in fiber PHY */
1795 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1796 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1797
1798 if (advert & ADVERTISE_1000XPAUSE)
1799 advert |= ADVERTISE_PAUSE_CAP;
1800 if (advert & ADVERTISE_1000XPSE_ASYM)
1801 advert |= ADVERTISE_PAUSE_ASYM;
1802 if (lpa & LPA_1000XPAUSE)
1803 lpa |= LPA_PAUSE_CAP;
1804 if (lpa & LPA_1000XPAUSE_ASYM)
1805 lpa |= LPA_PAUSE_ASYM;
1806 }
793b883e 1807
da4c1ff4
SH		 1808 sky2->flow_status = FC_NONE;
1809 if (advert & ADVERTISE_PAUSE_CAP) {
1810 if (lpa & LPA_PAUSE_CAP)
1811 sky2->flow_status = FC_BOTH;
1812 else if (advert & ADVERTISE_PAUSE_ASYM)
1813 sky2->flow_status = FC_RX;
1814 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1815 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1816 sky2->flow_status = FC_TX;
1817 }
793b883e 1818
16ad91e1 1819 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
93745494 1820 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
16ad91e1 1821 sky2->flow_status = FC_NONE;
2eaba1a2 1822
da4c1ff4 1823 if (sky2->flow_status & FC_TX)
793b883e
SH		 1824 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1825 else
1826 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1827
1828 return 0;
1829}
cd28ab6a 1830
e07b1aa8
SH		 1831/* Interrupt from PHY */
1832static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1833{
e07b1aa8
SH		 1834 struct net_device *dev = hw->dev[port];
1835 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1836 u16 istatus, phystat;
1837
ebc646f6
SH		 1838 if (!netif_running(dev))
1839 return;
1840
e07b1aa8
SH		 1841 spin_lock(&sky2->phy_lock);
1842 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1843 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1844
cd28ab6a
SH		 1845 if (netif_msg_intr(sky2))
1846 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1847 sky2->netdev->name, istatus, phystat);
1848
2eaba1a2 1849 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1850 if (sky2_autoneg_done(sky2, phystat) == 0)
1851 sky2_link_up(sky2);
1852 goto out;
1853 }
cd28ab6a 1854
793b883e
SH		 1855 if (istatus & PHY_M_IS_LSP_CHANGE)
1856 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1857
793b883e
SH		 1858 if (istatus & PHY_M_IS_DUP_CHANGE)
1859 sky2->duplex =
1860 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1861
793b883e
SH		 1862 if (istatus & PHY_M_IS_LST_CHANGE) {
1863 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1864 sky2_link_up(sky2);
793b883e
SH		 1865 else
1866 sky2_link_down(sky2);
cd28ab6a 1867 }
793b883e 1868out:
e07b1aa8 1869 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1870}
1871
62335ab0 1872/* Transmit timeout is only called if we are running, carrier is up
302d1252
SH		 1873 * and tx queue is full (stopped).
1874 */
cd28ab6a
SH		 1875static void sky2_tx_timeout(struct net_device *dev)
1876{
1877 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3 1878 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1879
1880 if (netif_msg_timer(sky2))
1881 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1882
8f24664d 1883 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
62335ab0
SH		 1884 dev->name, sky2->tx_cons, sky2->tx_prod,
1885 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1886 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
8f24664d 1887
81906791
SH		 1888 /* can't restart safely under softirq */
1889 schedule_work(&hw->restart_work);
cd28ab6a
SH		 1890}
1891
1892static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1893{
6b1a3aef
SH		 1894 struct sky2_port *sky2 = netdev_priv(dev);
1895 struct sky2_hw *hw = sky2->hw;
1896 int err;
1897 u16 ctl, mode;
e07b1aa8 1898 u32 imask;
cd28ab6a
SH		 1899
1900 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1901 return -EINVAL;
1902
4a50a876 1903 /* TSO on Yukon Ultra and MTU > 1500 not supported */
5a5b1ea0 1904 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
4a50a876 1905 dev->features &= ~NETIF_F_TSO;
5a5b1ea0 1906
6b1a3aef
SH		 1907 if (!netif_running(dev)) {
1908 dev->mtu = new_mtu;
1909 return 0;
1910 }
1911
e07b1aa8 1912 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1913 sky2_write32(hw, B0_IMSK, 0);
1914
018d1c66
SH		 1915 dev->trans_start = jiffies; /* prevent tx timeout */
1916 netif_stop_queue(dev);
1917 netif_poll_disable(hw->dev[0]);
1918
e07b1aa8
SH		 1919 synchronize_irq(hw->pdev->irq);
1920
6b1a3aef
SH		 1921 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1922 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1923 sky2_rx_stop(sky2);
1924 sky2_rx_clean(sky2);
cd28ab6a
SH		 1925
1926 dev->mtu = new_mtu;
14d0263f 1927
6b1a3aef
SH		 1928 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1929 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1930
1931 if (dev->mtu > ETH_DATA_LEN)
1932 mode |= GM_SMOD_JUMBO_ENA;
1933
1934 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1935
6b1a3aef 1936 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1937
6b1a3aef 1938 err = sky2_rx_start(sky2);
e07b1aa8 1939 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1940
1b537565
SH		 1941 if (err)
1942 dev_close(dev);
1943 else {
1944 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1945
1946 netif_poll_enable(hw->dev[0]);
1947 netif_wake_queue(dev);
1948 }
1949
cd28ab6a
SH		 1950 return err;
1951}
1952
14d0263f
SH		 1953/* For small just reuse existing skb for next receive */
1954static struct sk_buff *receive_copy(struct sky2_port *sky2,
1955 const struct rx_ring_info *re,
1956 unsigned length)
1957{
1958 struct sk_buff *skb;
1959
1960 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1961 if (likely(skb)) {
1962 skb_reserve(skb, 2);
1963 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1964 length, PCI_DMA_FROMDEVICE);
1965 memcpy(skb->data, re->skb->data, length);
1966 skb->ip_summed = re->skb->ip_summed;
1967 skb->csum = re->skb->csum;
1968 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1969 length, PCI_DMA_FROMDEVICE);
1970 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1971 skb_put(skb, length);
14d0263f
SH		 1972 }
1973 return skb;
1974}
1975
1976/* Adjust length of skb with fragments to match received data */
1977static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1978 unsigned int length)
1979{
1980 int i, num_frags;
1981 unsigned int size;
1982
1983 /* put header into skb */
1984 size = min(length, hdr_space);
1985 skb->tail += size;
1986 skb->len += size;
1987 length -= size;
1988
1989 num_frags = skb_shinfo(skb)->nr_frags;
1990 for (i = 0; i < num_frags; i++) {
1991 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1992
1993 if (length == 0) {
1994 /* don't need this page */
1995 __free_page(frag->page);
1996 --skb_shinfo(skb)->nr_frags;
1997 } else {
1998 size = min(length, (unsigned) PAGE_SIZE);
1999
2000 frag->size = size;
2001 skb->data_len += size;
2002 skb->truesize += size;
2003 skb->len += size;
2004 length -= size;
2005 }
2006 }
2007}
2008
2009/* Normal packet - take skb from ring element and put in a new one */
2010static struct sk_buff *receive_new(struct sky2_port *sky2,
2011 struct rx_ring_info *re,
2012 unsigned int length)
2013{
2014 struct sk_buff *skb, *nskb;
2015 unsigned hdr_space = sky2->rx_data_size;
2016
2017 pr_debug(PFX "receive new length=%d\n", length);
2018
2019 /* Don't be tricky about reusing pages (yet) */
2020 nskb = sky2_rx_alloc(sky2);
2021 if (unlikely(!nskb))
2022 return NULL;
2023
2024 skb = re->skb;
2025 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2026
2027 prefetch(skb->data);
2028 re->skb = nskb;
2029 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2030
2031 if (skb_shinfo(skb)->nr_frags)
2032 skb_put_frags(skb, hdr_space, length);
2033 else
489b10c1 2034 skb_put(skb, length);
14d0263f
SH		 2035 return skb;
2036}
2037
cd28ab6a
SH		 2038/*
2039 * Receive one packet.
d571b694 2040 * For larger packets, get new buffer.
cd28ab6a 2041 */
497d7c86 2042static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 2043 u16 length, u32 status)
2044{
497d7c86 2045 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 2046 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 2047 struct sk_buff *skb = NULL;
cd28ab6a
SH		 2048
2049 if (unlikely(netif_msg_rx_status(sky2)))
2050 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2051 dev->name, sky2->rx_next, status, length);
cd28ab6a 2052
793b883e 2053 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2054 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2055
42eeea01 2056 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2057 goto error;
2058
42eeea01
SH		 2059 if (!(status & GMR_FS_RX_OK))
2060 goto resubmit;
2061
14d0263f
SH		 2062 if (length < copybreak)
2063 skb = receive_copy(sky2, re, length);
2064 else
2065 skb = receive_new(sky2, re, length);
793b883e 2066resubmit:
14d0263f 2067 sky2_rx_submit(sky2, re);
79e57d32 2068
cd28ab6a
SH		 2069 return skb;
2070
2071error:
6e15b712 2072 ++sky2->net_stats.rx_errors;
b6d77734 2073 if (status & GMR_FS_RX_FF_OV) {
a79abdc6 2074 sky2->net_stats.rx_over_errors++;
b6d77734
SH		 2075 goto resubmit;
2076 }
6e15b712 2077
3be92a70 2078 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2079 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2080 dev->name, status, length);
793b883e
SH		 2081
2082 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2083 sky2->net_stats.rx_length_errors++;
2084 if (status & GMR_FS_FRAGMENT)
2085 sky2->net_stats.rx_frame_errors++;
2086 if (status & GMR_FS_CRC_ERR)
2087 sky2->net_stats.rx_crc_errors++;
79e57d32 2088
793b883e 2089 goto resubmit;
cd28ab6a
SH		 2090}
2091
e07b1aa8
SH		 2092/* Transmit complete */
2093static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2094{
e07b1aa8 2095 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2096
e07b1aa8 2097 if (netif_running(dev)) {
2bb8c262 2098 netif_tx_lock(dev);
e07b1aa8 2099 sky2_tx_complete(sky2, last);
2bb8c262 2100 netif_tx_unlock(dev);
2224795d 2101 }
cd28ab6a
SH		 2102}
2103
e07b1aa8
SH		 2104/* Process status response ring */
2105static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2106{
22e11703 2107 struct sky2_port *sky2;
e07b1aa8 2108 int work_done = 0;
22e11703 2109 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2110 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2111
af2a58ac 2112 rmb();
bea86103 2113
e71ebd73 2114 while (hw->st_idx != hwidx) {
13210ce5
SH		 2115 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2116 struct net_device *dev;
cd28ab6a 2117 struct sk_buff *skb;
cd28ab6a
SH		 2118 u32 status;
2119 u16 length;
2120
cb5d9547 2121 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2122
e71ebd73
SH		 2123 BUG_ON(le->link >= 2);
2124 dev = hw->dev[le->link];
13210ce5
SH		 2125
2126 sky2 = netdev_priv(dev);
f65b138c
SH		 2127 length = le16_to_cpu(le->length);
2128 status = le32_to_cpu(le->status);
cd28ab6a 2129
e71ebd73 2130 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2131 case OP_RXSTAT:
497d7c86 2132 skb = sky2_receive(dev, length, status);
d1f13708 2133 if (!skb)
5df79111 2134 goto force_update;
13210ce5 2135
13210ce5 2136 skb->protocol = eth_type_trans(skb, dev);
2bf56fe2 2137 sky2->net_stats.rx_packets++;
2138 sky2->net_stats.rx_bytes += skb->len;
13210ce5
SH		 2139 dev->last_rx = jiffies;
2140
d1f13708
SH		 2141#ifdef SKY2_VLAN_TAG_USED
2142 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2143 vlan_hwaccel_receive_skb(skb,
2144 sky2->vlgrp,
2145 be16_to_cpu(sky2->rx_tag));
2146 } else
2147#endif
cd28ab6a 2148 netif_receive_skb(skb);
13210ce5 2149
22e11703
SH		 2150 /* Update receiver after 16 frames */
2151 if (++buf_write[le->link] == RX_BUF_WRITE) {
5df79111
SH		 2152force_update:
2153 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
22e11703
SH		 2154 buf_write[le->link] = 0;
2155 }
2156
2157 /* Stop after net poll weight */
13210ce5
SH		 2158 if (++work_done >= to_do)
2159 goto exit_loop;
cd28ab6a
SH		 2160 break;
2161
d1f13708
SH		 2162#ifdef SKY2_VLAN_TAG_USED
2163 case OP_RXVLAN:
2164 sky2->rx_tag = length;
2165 break;
2166
2167 case OP_RXCHKSVLAN:
2168 sky2->rx_tag = length;
2169 /* fall through */
2170#endif
cd28ab6a 2171 case OP_RXCHKS:
87418307
SH		 2172 if (!sky2->rx_csum)
2173 break;
2174
2175 /* Both checksum counters are programmed to start at
2176 * the same offset, so unless there is a problem they
2177 * should match. This failure is an early indication that
2178 * hardware receive checksumming won't work.
2179 */
2180 if (likely(status >> 16 == (status & 0xffff))) {
2181 skb = sky2->rx_ring[sky2->rx_next].skb;
2182 skb->ip_summed = CHECKSUM_COMPLETE;
2183 skb->csum = status & 0xffff;
2184 } else {
2185 printk(KERN_NOTICE PFX "%s: hardware receive "
2186 "checksum problem (status = %#x)\n",
2187 dev->name, status);
2188 sky2->rx_csum = 0;
2189 sky2_write32(sky2->hw,
2190 Q_ADDR(rxqaddr[le->link], Q_CSR),
2191 BMU_DIS_RX_CHKSUM);
2192 }
cd28ab6a
SH		 2193 break;
2194
2195 case OP_TXINDEXLE:
13b97b74 2196 /* TX index reports status for both ports */
f55925d7
SH		 2197 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2198 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2199 if (hw->dev[1])
2200 sky2_tx_done(hw->dev[1],
2201 ((status >> 24) & 0xff)
2202 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2203 break;
2204
cd28ab6a
SH		 2205 default:
2206 if (net_ratelimit())
793b883e 2207 printk(KERN_WARNING PFX
e71ebd73
SH		 2208 "unknown status opcode 0x%x\n", le->opcode);
2209 goto exit_loop;
cd28ab6a 2210 }
13210ce5 2211 }
cd28ab6a 2212
fe2a24df
SH		 2213 /* Fully processed status ring so clear irq */
2214 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2215
13210ce5 2216exit_loop:
22e11703
SH		 2217 if (buf_write[0]) {
2218 sky2 = netdev_priv(hw->dev[0]);
2219 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2220 }
2221
2222 if (buf_write[1]) {
2223 sky2 = netdev_priv(hw->dev[1]);
2224 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2225 }
2226
e07b1aa8 2227 return work_done;
cd28ab6a
SH		 2228}
2229
2230static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2231{
2232 struct net_device *dev = hw->dev[port];
2233
3be92a70
SH		 2234 if (net_ratelimit())
2235 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2236 dev->name, status);
cd28ab6a
SH		 2237
2238 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2239 if (net_ratelimit())
2240 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2241 dev->name);
cd28ab6a
SH		 2242 /* Clear IRQ */
2243 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2244 }
2245
2246 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2247 if (net_ratelimit())
2248 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2249 dev->name);
cd28ab6a
SH		 2250
2251 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2252 }
2253
2254 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2255 if (net_ratelimit())
2256 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2257 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2258 }
2259
2260 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2261 if (net_ratelimit())
2262 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2263 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2264 }
2265
2266 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2267 if (net_ratelimit())
2268 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2269 dev->name);
cd28ab6a
SH		 2270 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2271 }
2272}
2273
2274static void sky2_hw_intr(struct sky2_hw *hw)
2275{
2276 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2277
793b883e 2278 if (status & Y2_IS_TIST_OV)
cd28ab6a 2279 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2280
2281 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2282 u16 pci_err;
2283
56a645cc 2284 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70 2285 if (net_ratelimit())
b02a9258
SH		 2286 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2287 pci_err);
cd28ab6a
SH		 2288
2289 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2290 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2291 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2292 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2293 }
2294
2295 if (status & Y2_IS_PCI_EXP) {
d571b694 2296 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2297 u32 pex_err;
2298
7bd656d1 2299 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2300
3be92a70 2301 if (net_ratelimit())
b02a9258
SH		 2302 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2303 pex_err);
cd28ab6a
SH		 2304
2305 /* clear the interrupt */
2306 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2307 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2308 0xffffffffUL);
cd28ab6a
SH		 2309 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2310
7bd656d1 2311 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2312 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2313 hwmsk &= ~Y2_IS_PCI_EXP;
2314 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2315 }
2316 }
2317
2318 if (status & Y2_HWE_L1_MASK)
2319 sky2_hw_error(hw, 0, status);
2320 status >>= 8;
2321 if (status & Y2_HWE_L1_MASK)
2322 sky2_hw_error(hw, 1, status);
2323}
2324
2325static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2326{
2327 struct net_device *dev = hw->dev[port];
2328 struct sky2_port *sky2 = netdev_priv(dev);
2329 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2330
2331 if (netif_msg_intr(sky2))
2332 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2333 dev->name, status);
2334
2335 if (status & GM_IS_RX_FF_OR) {
2336 ++sky2->net_stats.rx_fifo_errors;
2337 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2338 }
2339
2340 if (status & GM_IS_TX_FF_UR) {
2341 ++sky2->net_stats.tx_fifo_errors;
2342 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2343 }
cd28ab6a
SH		 2344}
2345
d257924e
SH		 2346/* This should never happen it is a fatal situation */
2347static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2348 const char *rxtx, u32 mask)
2349{
2350 struct net_device *dev = hw->dev[port];
2351 struct sky2_port *sky2 = netdev_priv(dev);
2352 u32 imask;
2353
2354 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2355 dev ? dev->name : "<not registered>", rxtx);
2356
2357 imask = sky2_read32(hw, B0_IMSK);
2358 imask &= ~mask;
2359 sky2_write32(hw, B0_IMSK, imask);
2360
2361 if (dev) {
2362 spin_lock(&sky2->phy_lock);
2363 sky2_link_down(sky2);
2364 spin_unlock(&sky2->phy_lock);
2365 }
2366}
cd28ab6a 2367
d27ed387
SH		 2368/* If idle then force a fake soft NAPI poll once a second
2369 * to work around cases where sharing an edge triggered interrupt.
2370 */
eb35cf60
SH		 2371static inline void sky2_idle_start(struct sky2_hw *hw)
2372{
2373 if (idle_timeout > 0)
2374 mod_timer(&hw->idle_timer,
2375 jiffies + msecs_to_jiffies(idle_timeout));
2376}
2377
d27ed387
SH		 2378static void sky2_idle(unsigned long arg)
2379{
01bd7564
SH		 2380 struct sky2_hw *hw = (struct sky2_hw *) arg;
2381 struct net_device *dev = hw->dev[0];
d27ed387 2382
d27ed387
SH		 2383 if (__netif_rx_schedule_prep(dev))
2384 __netif_rx_schedule(dev);
01bd7564
SH		 2385
2386 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2387}
2388
2389
e07b1aa8 2390static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2391{
e07b1aa8
SH		 2392 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2393 int work_limit = min(dev0->quota, *budget);
2394 int work_done = 0;
fb2690a9 2395 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2396
1e5f1283
SH		 2397 if (status & Y2_IS_HW_ERR)
2398 sky2_hw_intr(hw);
d257924e 2399
1e5f1283
SH		 2400 if (status & Y2_IS_IRQ_PHY1)
2401 sky2_phy_intr(hw, 0);
cd28ab6a 2402
1e5f1283
SH		 2403 if (status & Y2_IS_IRQ_PHY2)
2404 sky2_phy_intr(hw, 1);
cd28ab6a 2405
1e5f1283
SH		 2406 if (status & Y2_IS_IRQ_MAC1)
2407 sky2_mac_intr(hw, 0);
cd28ab6a 2408
1e5f1283
SH		 2409 if (status & Y2_IS_IRQ_MAC2)
2410 sky2_mac_intr(hw, 1);
cd28ab6a 2411
1e5f1283
SH		 2412 if (status & Y2_IS_CHK_RX1)
2413 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2414
1e5f1283
SH		 2415 if (status & Y2_IS_CHK_RX2)
2416 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2417
1e5f1283
SH		 2418 if (status & Y2_IS_CHK_TXA1)
2419 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2420
1e5f1283
SH		 2421 if (status & Y2_IS_CHK_TXA2)
2422 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2423
1e5f1283 2424 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2425 if (work_done < work_limit) {
2426 netif_rx_complete(dev0);
86fba634 2427
fe2a24df
SH		 2428 sky2_read32(hw, B0_Y2_SP_LISR);
2429 return 0;
2430 } else {
2431 *budget -= work_done;
2432 dev0->quota -= work_done;
1e5f1283 2433 return 1;
fe2a24df 2434 }
e07b1aa8
SH		 2435}
2436
7d12e780 2437static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2438{
2439 struct sky2_hw *hw = dev_id;
2440 struct net_device *dev0 = hw->dev[0];
2441 u32 status;
2442
2443 /* Reading this mask interrupts as side effect */
2444 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2445 if (status == 0 || status == ~0)
2446 return IRQ_NONE;
793b883e 2447
e07b1aa8
SH		 2448 prefetch(&hw->st_le[hw->st_idx]);
2449 if (likely(__netif_rx_schedule_prep(dev0)))
2450 __netif_rx_schedule(dev0);
793b883e 2451
cd28ab6a
SH		 2452 return IRQ_HANDLED;
2453}
2454
2455#ifdef CONFIG_NET_POLL_CONTROLLER
2456static void sky2_netpoll(struct net_device *dev)
2457{
2458 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2459 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2460
88d11360
SH		 2461 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2462 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2463}
2464#endif
2465
2466/* Chip internal frequency for clock calculations */
fb17358f 2467static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2468{
793b883e 2469 switch (hw->chip_id) {
cd28ab6a 2470 case CHIP_ID_YUKON_EC:
5a5b1ea0 2471 case CHIP_ID_YUKON_EC_U:
93745494 2472 case CHIP_ID_YUKON_EX:
fb17358f 2473 return 125; /* 125 Mhz */
cd28ab6a 2474 case CHIP_ID_YUKON_FE:
fb17358f 2475 return 100; /* 100 Mhz */
793b883e 2476 default: /* YUKON_XL */
fb17358f 2477 return 156; /* 156 Mhz */
cd28ab6a
SH		 2478 }
2479}
2480
fb17358f 2481static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2482{
fb17358f 2483 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2484}
2485
fb17358f 2486static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2487{
fb17358f 2488 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2489}
2490
fb17358f 2491
e3173832 2492static int __devinit sky2_init(struct sky2_hw *hw)
cd28ab6a 2493{
b89165f2 2494 u8 t8;
cd28ab6a 2495
cd28ab6a 2496 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2497
cd28ab6a
SH		 2498 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2499 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
b02a9258
SH		 2500 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2501 hw->chip_id);
cd28ab6a
SH		 2502 return -EOPNOTSUPP;
2503 }
2504
93745494
SH		 2505 if (hw->chip_id == CHIP_ID_YUKON_EX)
2506 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2507 "Please report success or failure to <netdev@vger.kernel.org>\n");
2508
2509 /* Make sure and enable all clocks */
2510 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2511 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2512
290d4de5
SH		 2513 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2514
2515 /* This rev is really old, and requires untested workarounds */
2516 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
b02a9258
SH		 2517 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2518 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2519 hw->chip_id, hw->chip_rev);
290d4de5
SH		 2520 return -EOPNOTSUPP;
2521 }
2522
e3173832
SH		 2523 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2524 hw->ports = 1;
2525 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2526 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2527 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2528 ++hw->ports;
2529 }
2530
2531 return 0;
2532}
2533
2534static void sky2_reset(struct sky2_hw *hw)
2535{
2536 u16 status;
2537 int i;
2538
cd28ab6a
SH		 2539 /* disable ASF */
2540 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
93745494
SH		 2541 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2542 status = sky2_read16(hw, HCU_CCSR);
2543 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2544 HCU_CCSR_UC_STATE_MSK);
2545 sky2_write16(hw, HCU_CCSR, status);
2546 } else
2547 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
cd28ab6a
SH		 2548 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2549 }
2550
2551 /* do a SW reset */
2552 sky2_write8(hw, B0_CTST, CS_RST_SET);
2553 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2554
2555 /* clear PCI errors, if any */
56a645cc 2556 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2557
cd28ab6a 2558 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2559 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2560
cd28ab6a
SH		 2561
2562 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2563
2564 /* clear any PEX errors */
7bd656d1
SH		 2565 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2566 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2567
cd28ab6a 2568
ae306cca 2569 sky2_power_on(hw);
cd28ab6a
SH		 2570
2571 for (i = 0; i < hw->ports; i++) {
2572 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2573 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2574 }
2575
2576 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2577
793b883e
SH		 2578 /* Clear I2C IRQ noise */
2579 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2580
2581 /* turn off hardware timer (unused) */
2582 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2583 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2584
cd28ab6a
SH		 2585 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2586
69634ee7
SH		 2587 /* Turn off descriptor polling */
2588 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2589
2590 /* Turn off receive timestamp */
2591 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2592 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2593
2594 /* enable the Tx Arbiters */
2595 for (i = 0; i < hw->ports; i++)
2596 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2597
2598 /* Initialize ram interface */
2599 for (i = 0; i < hw->ports; i++) {
793b883e 2600 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2601
2602 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2603 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2604 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2605 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2606 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2607 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2608 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2609 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2610 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2611 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2612 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2613 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2614 }
2615
7bd656d1 2616 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2617
cd28ab6a 2618 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2619 sky2_gmac_reset(hw, i);
cd28ab6a 2620
cd28ab6a
SH		 2621 memset(hw->st_le, 0, STATUS_LE_BYTES);
2622 hw->st_idx = 0;
2623
2624 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2625 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2626
2627 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2628 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2629
2630 /* Set the list last index */
793b883e 2631 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2632
290d4de5
SH		 2633 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2634 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2635
290d4de5
SH		 2636 /* set Status-FIFO ISR watermark */
2637 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2638 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2639 else
2640 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2641
290d4de5 2642 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2643 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2644 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2645
793b883e 2646 /* enable status unit */
cd28ab6a
SH		 2647 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2648
2649 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2650 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2651 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
e3173832
SH		 2652}
2653
81906791
SH		 2654static void sky2_restart(struct work_struct *work)
2655{
2656 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2657 struct net_device *dev;
2658 int i, err;
2659
2660 dev_dbg(&hw->pdev->dev, "restarting\n");
2661
2662 del_timer_sync(&hw->idle_timer);
2663
2664 rtnl_lock();
2665 sky2_write32(hw, B0_IMSK, 0);
2666 sky2_read32(hw, B0_IMSK);
2667
2668 netif_poll_disable(hw->dev[0]);
2669
2670 for (i = 0; i < hw->ports; i++) {
2671 dev = hw->dev[i];
2672 if (netif_running(dev))
2673 sky2_down(dev);
2674 }
2675
2676 sky2_reset(hw);
2677 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2678 netif_poll_enable(hw->dev[0]);
2679
2680 for (i = 0; i < hw->ports; i++) {
2681 dev = hw->dev[i];
2682 if (netif_running(dev)) {
2683 err = sky2_up(dev);
2684 if (err) {
2685 printk(KERN_INFO PFX "%s: could not restart %d\n",
2686 dev->name, err);
2687 dev_close(dev);
2688 }
2689 }
2690 }
2691
2692 sky2_idle_start(hw);
2693
2694 rtnl_unlock();
2695}
2696
e3173832
SH		 2697static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2698{
2699 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2700}
2701
2702static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2703{
2704 const struct sky2_port *sky2 = netdev_priv(dev);
2705
2706 wol->supported = sky2_wol_supported(sky2->hw);
2707 wol->wolopts = sky2->wol;
2708}
2709
2710static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2711{
2712 struct sky2_port *sky2 = netdev_priv(dev);
2713 struct sky2_hw *hw = sky2->hw;
cd28ab6a 2714
e3173832
SH		 2715 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2716 return -EOPNOTSUPP;
2717
2718 sky2->wol = wol->wolopts;
2719
2720 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2721 sky2_write32(hw, B0_CTST, sky2->wol
2722 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2723
2724 if (!netif_running(dev))
2725 sky2_wol_init(sky2);
cd28ab6a
SH		 2726 return 0;
2727}
2728
28bd181a 2729static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2730{
b89165f2
SH		 2731 if (sky2_is_copper(hw)) {
2732 u32 modes = SUPPORTED_10baseT_Half
2733 | SUPPORTED_10baseT_Full
2734 | SUPPORTED_100baseT_Half
2735 | SUPPORTED_100baseT_Full
2736 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2737
2738 if (hw->chip_id != CHIP_ID_YUKON_FE)
2739 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2740 | SUPPORTED_1000baseT_Full;
2741 return modes;
cd28ab6a 2742 } else
b89165f2
SH		 2743 return SUPPORTED_1000baseT_Half
2744 | SUPPORTED_1000baseT_Full
2745 | SUPPORTED_Autoneg
2746 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2747}
2748
793b883e 2749static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2750{
2751 struct sky2_port *sky2 = netdev_priv(dev);
2752 struct sky2_hw *hw = sky2->hw;
2753
2754 ecmd->transceiver = XCVR_INTERNAL;
2755 ecmd->supported = sky2_supported_modes(hw);
2756 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2757 if (sky2_is_copper(hw)) {
cd28ab6a 2758 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2759 | SUPPORTED_10baseT_Full
2760 | SUPPORTED_100baseT_Half
2761 | SUPPORTED_100baseT_Full
2762 | SUPPORTED_1000baseT_Half
2763 | SUPPORTED_1000baseT_Full
2764 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2765 ecmd->port = PORT_TP;
b89165f2
SH		 2766 ecmd->speed = sky2->speed;
2767 } else {
2768 ecmd->speed = SPEED_1000;
cd28ab6a 2769 ecmd->port = PORT_FIBRE;
b89165f2 2770 }
cd28ab6a
SH		 2771
2772 ecmd->advertising = sky2->advertising;
2773 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2774 ecmd->duplex = sky2->duplex;
2775 return 0;
2776}
2777
2778static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2779{
2780 struct sky2_port *sky2 = netdev_priv(dev);
2781 const struct sky2_hw *hw = sky2->hw;
2782 u32 supported = sky2_supported_modes(hw);
2783
2784 if (ecmd->autoneg == AUTONEG_ENABLE) {
2785 ecmd->advertising = supported;
2786 sky2->duplex = -1;
2787 sky2->speed = -1;
2788 } else {
2789 u32 setting;
2790
793b883e 2791 switch (ecmd->speed) {
cd28ab6a
SH		 2792 case SPEED_1000:
2793 if (ecmd->duplex == DUPLEX_FULL)
2794 setting = SUPPORTED_1000baseT_Full;
2795 else if (ecmd->duplex == DUPLEX_HALF)
2796 setting = SUPPORTED_1000baseT_Half;
2797 else
2798 return -EINVAL;
2799 break;
2800 case SPEED_100:
2801 if (ecmd->duplex == DUPLEX_FULL)
2802 setting = SUPPORTED_100baseT_Full;
2803 else if (ecmd->duplex == DUPLEX_HALF)
2804 setting = SUPPORTED_100baseT_Half;
2805 else
2806 return -EINVAL;
2807 break;
2808
2809 case SPEED_10:
2810 if (ecmd->duplex == DUPLEX_FULL)
2811 setting = SUPPORTED_10baseT_Full;
2812 else if (ecmd->duplex == DUPLEX_HALF)
2813 setting = SUPPORTED_10baseT_Half;
2814 else
2815 return -EINVAL;
2816 break;
2817 default:
2818 return -EINVAL;
2819 }
2820
2821 if ((setting & supported) == 0)
2822 return -EINVAL;
2823
2824 sky2->speed = ecmd->speed;
2825 sky2->duplex = ecmd->duplex;
2826 }
2827
2828 sky2->autoneg = ecmd->autoneg;
2829 sky2->advertising = ecmd->advertising;
2830
1b537565
SH		 2831 if (netif_running(dev))
2832 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2833
2834 return 0;
2835}
2836
2837static void sky2_get_drvinfo(struct net_device *dev,
2838 struct ethtool_drvinfo *info)
2839{
2840 struct sky2_port *sky2 = netdev_priv(dev);
2841
2842 strcpy(info->driver, DRV_NAME);
2843 strcpy(info->version, DRV_VERSION);
2844 strcpy(info->fw_version, "N/A");
2845 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2846}
2847
2848static const struct sky2_stat {
793b883e
SH		 2849 char name[ETH_GSTRING_LEN];
2850 u16 offset;
cd28ab6a
SH		 2851} sky2_stats[] = {
2852 { "tx_bytes", GM_TXO_OK_HI },
2853 { "rx_bytes", GM_RXO_OK_HI },
2854 { "tx_broadcast", GM_TXF_BC_OK },
2855 { "rx_broadcast", GM_RXF_BC_OK },
2856 { "tx_multicast", GM_TXF_MC_OK },
2857 { "rx_multicast", GM_RXF_MC_OK },
2858 { "tx_unicast", GM_TXF_UC_OK },
2859 { "rx_unicast", GM_RXF_UC_OK },
2860 { "tx_mac_pause", GM_TXF_MPAUSE },
2861 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2862 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2863 { "late_collision",GM_TXF_LAT_COL },
2864 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2865 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2866 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2867
d2604540 2868 { "rx_short", GM_RXF_SHT },
cd28ab6a 2869 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2870 { "rx_64_byte_packets", GM_RXF_64B },
2871 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2872 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2873 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2874 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2875 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2876 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2877 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2878 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2879 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2880 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2881
2882 { "tx_64_byte_packets", GM_TXF_64B },
2883 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2884 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2885 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2886 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2887 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2888 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2889 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2890};
2891
cd28ab6a
SH		 2892static u32 sky2_get_rx_csum(struct net_device *dev)
2893{
2894 struct sky2_port *sky2 = netdev_priv(dev);
2895
2896 return sky2->rx_csum;
2897}
2898
2899static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2900{
2901 struct sky2_port *sky2 = netdev_priv(dev);
2902
2903 sky2->rx_csum = data;
793b883e 2904
cd28ab6a
SH		 2905 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2906 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2907
2908 return 0;
2909}
2910
2911static u32 sky2_get_msglevel(struct net_device *netdev)
2912{
2913 struct sky2_port *sky2 = netdev_priv(netdev);
2914 return sky2->msg_enable;
2915}
2916
9a7ae0a9
SH		 2917static int sky2_nway_reset(struct net_device *dev)
2918{
2919 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2920
16ad91e1 2921 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2922 return -EINVAL;
2923
1b537565 2924 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2925
2926 return 0;
2927}
2928
793b883e 2929static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2930{
2931 struct sky2_hw *hw = sky2->hw;
2932 unsigned port = sky2->port;
2933 int i;
2934
2935 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2936 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2937 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2938 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2939
793b883e 2940 for (i = 2; i < count; i++)
cd28ab6a
SH		 2941 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2942}
2943
cd28ab6a
SH		 2944static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2945{
2946 struct sky2_port *sky2 = netdev_priv(netdev);
2947 sky2->msg_enable = value;
2948}
2949
2950static int sky2_get_stats_count(struct net_device *dev)
2951{
2952 return ARRAY_SIZE(sky2_stats);
2953}
2954
2955static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2956 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2957{
2958 struct sky2_port *sky2 = netdev_priv(dev);
2959
793b883e 2960 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2961}
2962
793b883e 2963static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2964{
2965 int i;
2966
2967 switch (stringset) {
2968 case ETH_SS_STATS:
2969 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2970 memcpy(data + i * ETH_GSTRING_LEN,
2971 sky2_stats[i].name, ETH_GSTRING_LEN);
2972 break;
2973 }
2974}
2975
cd28ab6a
SH		 2976static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2977{
2978 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 2979 return &sky2->net_stats;
2980}
2981
2982static int sky2_set_mac_address(struct net_device *dev, void *p)
2983{
2984 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2985 struct sky2_hw *hw = sky2->hw;
2986 unsigned port = sky2->port;
2987 const struct sockaddr *addr = p;
cd28ab6a
SH		 2988
2989 if (!is_valid_ether_addr(addr->sa_data))
2990 return -EADDRNOTAVAIL;
2991
cd28ab6a 2992 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2993 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2994 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2995 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2996 dev->dev_addr, ETH_ALEN);
1b537565 2997
a8ab1ec0
SH		 2998 /* virtual address for data */
2999 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3000
3001 /* physical address: used for pause frames */
3002 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 3003
3004 return 0;
cd28ab6a
SH		 3005}
3006
a052b52f
SH		 3007static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3008{
3009 u32 bit;
3010
3011 bit = ether_crc(ETH_ALEN, addr) & 63;
3012 filter[bit >> 3] |= 1 << (bit & 7);
3013}
3014
cd28ab6a
SH		 3015static void sky2_set_multicast(struct net_device *dev)
3016{
3017 struct sky2_port *sky2 = netdev_priv(dev);
3018 struct sky2_hw *hw = sky2->hw;
3019 unsigned port = sky2->port;
3020 struct dev_mc_list *list = dev->mc_list;
3021 u16 reg;
3022 u8 filter[8];
a052b52f
SH		 3023 int rx_pause;
3024 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
cd28ab6a 3025
a052b52f 3026 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
cd28ab6a
SH		 3027 memset(filter, 0, sizeof(filter));
3028
3029 reg = gma_read16(hw, port, GM_RX_CTRL);
3030 reg |= GM_RXCR_UCF_ENA;
3031
d571b694 3032 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 3033 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
a052b52f 3034 else if (dev->flags & IFF_ALLMULTI)
cd28ab6a 3035 memset(filter, 0xff, sizeof(filter));
a052b52f 3036 else if (dev->mc_count == 0 && !rx_pause)
cd28ab6a
SH		 3037 reg &= ~GM_RXCR_MCF_ENA;
3038 else {
3039 int i;
3040 reg |= GM_RXCR_MCF_ENA;
3041
a052b52f
SH		 3042 if (rx_pause)
3043 sky2_add_filter(filter, pause_mc_addr);
3044
3045 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3046 sky2_add_filter(filter, list->dmi_addr);
cd28ab6a
SH		 3047 }
3048
cd28ab6a 3049 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 3050 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 3051 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 3052 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 3053 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 3054 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 3055 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 3056 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 3057
3058 gma_write16(hw, port, GM_RX_CTRL, reg);
3059}
3060
3061/* Can have one global because blinking is controlled by
3062 * ethtool and that is always under RTNL mutex
3063 */
91c86df5 3064static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 3065{
793b883e
SH		 3066 u16 pg;
3067
793b883e
SH		 3068 switch (hw->chip_id) {
3069 case CHIP_ID_YUKON_XL:
3070 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3071 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3072 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3073 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3074 PHY_M_LEDC_INIT_CTRL(7) |
3075 PHY_M_LEDC_STA1_CTRL(7) |
3076 PHY_M_LEDC_STA0_CTRL(7))
3077 : 0);
3078
3079 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3080 break;
3081
3082 default:
3083 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
0efdf262
SH		 3084 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3085 on ? PHY_M_LED_ALL : 0);
793b883e 3086 }
cd28ab6a
SH		 3087}
3088
3089/* blink LED's for finding board */
3090static int sky2_phys_id(struct net_device *dev, u32 data)
3091{
3092 struct sky2_port *sky2 = netdev_priv(dev);
3093 struct sky2_hw *hw = sky2->hw;
3094 unsigned port = sky2->port;
793b883e 3095 u16 ledctrl, ledover = 0;
cd28ab6a 3096 long ms;
91c86df5 3097 int interrupted;
cd28ab6a
SH		 3098 int onoff = 1;
3099
793b883e 3100 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 3101 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3102 else
3103 ms = data * 1000;
3104
3105 /* save initial values */
e07b1aa8 3106 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 3107 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3108 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3109 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3110 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3111 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3112 } else {
3113 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3114 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3115 }
cd28ab6a 3116
91c86df5
SH		 3117 interrupted = 0;
3118 while (!interrupted && ms > 0) {
cd28ab6a
SH		 3119 sky2_led(hw, port, onoff);
3120 onoff = !onoff;
3121
e07b1aa8 3122 spin_unlock_bh(&sky2->phy_lock);
91c86df5 3123 interrupted = msleep_interruptible(250);
e07b1aa8 3124 spin_lock_bh(&sky2->phy_lock);
91c86df5 3125
cd28ab6a
SH		 3126 ms -= 250;
3127 }
3128
3129 /* resume regularly scheduled programming */
793b883e
SH		 3130 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3131 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3132 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3133 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3134 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3135 } else {
3136 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3137 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3138 }
e07b1aa8 3139 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 3140
3141 return 0;
3142}
3143
3144static void sky2_get_pauseparam(struct net_device *dev,
3145 struct ethtool_pauseparam *ecmd)
3146{
3147 struct sky2_port *sky2 = netdev_priv(dev);
3148
16ad91e1
SH		 3149 switch (sky2->flow_mode) {
3150 case FC_NONE:
3151 ecmd->tx_pause = ecmd->rx_pause = 0;
3152 break;
3153 case FC_TX:
3154 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3155 break;
3156 case FC_RX:
3157 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3158 break;
3159 case FC_BOTH:
3160 ecmd->tx_pause = ecmd->rx_pause = 1;
3161 }
3162
cd28ab6a
SH		 3163 ecmd->autoneg = sky2->autoneg;
3164}
3165
3166static int sky2_set_pauseparam(struct net_device *dev,
3167 struct ethtool_pauseparam *ecmd)
3168{
3169 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3170
3171 sky2->autoneg = ecmd->autoneg;
16ad91e1 3172 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3173
16ad91e1
SH		 3174 if (netif_running(dev))
3175 sky2_phy_reinit(sky2);
cd28ab6a 3176
2eaba1a2 3177 return 0;
cd28ab6a
SH		 3178}
3179
fb17358f
SH		 3180static int sky2_get_coalesce(struct net_device *dev,
3181 struct ethtool_coalesce *ecmd)
3182{
3183 struct sky2_port *sky2 = netdev_priv(dev);
3184 struct sky2_hw *hw = sky2->hw;
3185
3186 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3187 ecmd->tx_coalesce_usecs = 0;
3188 else {
3189 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3190 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3191 }
3192 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3193
3194 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3195 ecmd->rx_coalesce_usecs = 0;
3196 else {
3197 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3198 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3199 }
3200 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3201
3202 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3203 ecmd->rx_coalesce_usecs_irq = 0;
3204 else {
3205 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3206 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3207 }
3208
3209 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3210
3211 return 0;
3212}
3213
3214/* Note: this affect both ports */
3215static int sky2_set_coalesce(struct net_device *dev,
3216 struct ethtool_coalesce *ecmd)
3217{
3218 struct sky2_port *sky2 = netdev_priv(dev);
3219 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3220 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3221
77b3d6a2
SH		 3222 if (ecmd->tx_coalesce_usecs > tmax ||
3223 ecmd->rx_coalesce_usecs > tmax ||
3224 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3225 return -EINVAL;
3226
ff81fbbe 3227 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3228 return -EINVAL;
ff81fbbe 3229 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3230 return -EINVAL;
ff81fbbe 3231 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3232 return -EINVAL;
3233
3234 if (ecmd->tx_coalesce_usecs == 0)
3235 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3236 else {
3237 sky2_write32(hw, STAT_TX_TIMER_INI,
3238 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3239 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3240 }
3241 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3242
3243 if (ecmd->rx_coalesce_usecs == 0)
3244 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3245 else {
3246 sky2_write32(hw, STAT_LEV_TIMER_INI,
3247 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3248 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3249 }
3250 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3251
3252 if (ecmd->rx_coalesce_usecs_irq == 0)
3253 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3254 else {
d28d4870 3255 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3256 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3257 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3258 }
3259 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3260 return 0;
3261}
3262
793b883e
SH		 3263static void sky2_get_ringparam(struct net_device *dev,
3264 struct ethtool_ringparam *ering)
3265{
3266 struct sky2_port *sky2 = netdev_priv(dev);
3267
3268 ering->rx_max_pending = RX_MAX_PENDING;
3269 ering->rx_mini_max_pending = 0;
3270 ering->rx_jumbo_max_pending = 0;
3271 ering->tx_max_pending = TX_RING_SIZE - 1;
3272
3273 ering->rx_pending = sky2->rx_pending;
3274 ering->rx_mini_pending = 0;
3275 ering->rx_jumbo_pending = 0;
3276 ering->tx_pending = sky2->tx_pending;
3277}
3278
3279static int sky2_set_ringparam(struct net_device *dev,
3280 struct ethtool_ringparam *ering)
3281{
3282 struct sky2_port *sky2 = netdev_priv(dev);
3283 int err = 0;
3284
3285 if (ering->rx_pending > RX_MAX_PENDING ||
3286 ering->rx_pending < 8 ||
3287 ering->tx_pending < MAX_SKB_TX_LE ||
3288 ering->tx_pending > TX_RING_SIZE - 1)
3289 return -EINVAL;
3290
3291 if (netif_running(dev))
3292 sky2_down(dev);
3293
3294 sky2->rx_pending = ering->rx_pending;
3295 sky2->tx_pending = ering->tx_pending;
3296
1b537565 3297 if (netif_running(dev)) {
793b883e 3298 err = sky2_up(dev);
1b537565
SH		 3299 if (err)
3300 dev_close(dev);
6ed995bb
SH		 3301 else
3302 sky2_set_multicast(dev);
1b537565 3303 }
793b883e
SH		 3304
3305 return err;
3306}
3307
793b883e
SH		 3308static int sky2_get_regs_len(struct net_device *dev)
3309{
6e4cbb34 3310 return 0x4000;
793b883e
SH		 3311}
3312
3313/*
3314 * Returns copy of control register region
6e4cbb34 3315 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3316 */
3317static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3318 void *p)
3319{
3320 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3321 const void __iomem *io = sky2->hw->regs;
793b883e 3322
6e4cbb34 3323 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3324 regs->version = 1;
6e4cbb34 3325 memset(p, 0, regs->len);
793b883e 3326
6e4cbb34
SH		 3327 memcpy_fromio(p, io, B3_RAM_ADDR);
3328
3329 memcpy_fromio(p + B3_RI_WTO_R1,
3330 io + B3_RI_WTO_R1,
3331 regs->len - B3_RI_WTO_R1);
793b883e 3332}
cd28ab6a 3333
7282d491 3334static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3335 .get_settings = sky2_get_settings,
3336 .set_settings = sky2_set_settings,
e3173832
SH		 3337 .get_drvinfo = sky2_get_drvinfo,
3338 .get_wol = sky2_get_wol,
3339 .set_wol = sky2_set_wol,
793b883e
SH		 3340 .get_msglevel = sky2_get_msglevel,
3341 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3342 .nway_reset = sky2_nway_reset,
793b883e
SH		 3343 .get_regs_len = sky2_get_regs_len,
3344 .get_regs = sky2_get_regs,
3345 .get_link = ethtool_op_get_link,
3346 .get_sg = ethtool_op_get_sg,
3347 .set_sg = ethtool_op_set_sg,
3348 .get_tx_csum = ethtool_op_get_tx_csum,
3349 .set_tx_csum = ethtool_op_set_tx_csum,
3350 .get_tso = ethtool_op_get_tso,
3351 .set_tso = ethtool_op_set_tso,
3352 .get_rx_csum = sky2_get_rx_csum,
3353 .set_rx_csum = sky2_set_rx_csum,
3354 .get_strings = sky2_get_strings,
fb17358f
SH		 3355 .get_coalesce = sky2_get_coalesce,
3356 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3357 .get_ringparam = sky2_get_ringparam,
3358 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3359 .get_pauseparam = sky2_get_pauseparam,
3360 .set_pauseparam = sky2_set_pauseparam,
793b883e 3361 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3362 .get_stats_count = sky2_get_stats_count,
3363 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3364 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3365};
3366
3367/* Initialize network device */
3368static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
e3173832
SH		 3369 unsigned port,
3370 int highmem, int wol)
cd28ab6a
SH		 3371{
3372 struct sky2_port *sky2;
3373 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3374
3375 if (!dev) {
b02a9258 3376 dev_err(&hw->pdev->dev, "etherdev alloc failed");
cd28ab6a
SH		 3377 return NULL;
3378 }
3379
3380 SET_MODULE_OWNER(dev);
3381 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3382 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3383 dev->open = sky2_up;
3384 dev->stop = sky2_down;
ef743d33 3385 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3386 dev->hard_start_xmit = sky2_xmit_frame;
3387 dev->get_stats = sky2_get_stats;
3388 dev->set_multicast_list = sky2_set_multicast;
3389 dev->set_mac_address = sky2_set_mac_address;
3390 dev->change_mtu = sky2_change_mtu;
3391 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3392 dev->tx_timeout = sky2_tx_timeout;
3393 dev->watchdog_timeo = TX_WATCHDOG;
3394 if (port == 0)
3395 dev->poll = sky2_poll;
3396 dev->weight = NAPI_WEIGHT;
3397#ifdef CONFIG_NET_POLL_CONTROLLER
0ca43235
SH		 3398 /* Network console (only works on port 0)
3399 * because netpoll makes assumptions about NAPI
3400 */
3401 if (port == 0)
3402 dev->poll_controller = sky2_netpoll;
cd28ab6a 3403#endif
cd28ab6a
SH		 3404
3405 sky2 = netdev_priv(dev);
3406 sky2->netdev = dev;
3407 sky2->hw = hw;
3408 sky2->msg_enable = netif_msg_init(debug, default_msg);
3409
cd28ab6a
SH		 3410 /* Auto speed and flow control */
3411 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3412 sky2->flow_mode = FC_BOTH;
3413
cd28ab6a
SH		 3414 sky2->duplex = -1;
3415 sky2->speed = -1;
3416 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3417 sky2->rx_csum = 1;
e3173832 3418 sky2->wol = wol;
75d070c5 3419
e07b1aa8 3420 spin_lock_init(&sky2->phy_lock);
793b883e 3421 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3422 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3423
3424 hw->dev[port] = dev;
3425
3426 sky2->port = port;
3427
4a50a876 3428 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a
SH		 3429 if (highmem)
3430 dev->features |= NETIF_F_HIGHDMA;
cd28ab6a 3431
d1f13708
SH		 3432#ifdef SKY2_VLAN_TAG_USED
3433 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3434 dev->vlan_rx_register = sky2_vlan_rx_register;
3435 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3436#endif
3437
cd28ab6a 3438 /* read the mac address */
793b883e 3439 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3440 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3441
3442 /* device is off until link detection */
3443 netif_carrier_off(dev);
3444 netif_stop_queue(dev);
3445
3446 return dev;
3447}
3448
28bd181a 3449static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3450{
3451 const struct sky2_port *sky2 = netdev_priv(dev);
3452
3453 if (netif_msg_probe(sky2))
3454 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3455 dev->name,
3456 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3457 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3458}
3459
fb2690a9 3460/* Handle software interrupt used during MSI test */
7d12e780 3461static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3462{
3463 struct sky2_hw *hw = dev_id;
3464 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3465
3466 if (status == 0)
3467 return IRQ_NONE;
3468
3469 if (status & Y2_IS_IRQ_SW) {
b0a20ded 3470 hw->msi = 1;
fb2690a9
SH		 3471 wake_up(&hw->msi_wait);
3472 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3473 }
3474 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3475
3476 return IRQ_HANDLED;
3477}
3478
3479/* Test interrupt path by forcing a a software IRQ */
3480static int __devinit sky2_test_msi(struct sky2_hw *hw)
3481{
3482 struct pci_dev *pdev = hw->pdev;
3483 int err;
3484
bb507fe1
SH		 3485 init_waitqueue_head (&hw->msi_wait);
3486
fb2690a9
SH		 3487 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3488
b0a20ded 3489 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
fb2690a9 3490 if (err) {
b02a9258 3491 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
fb2690a9
SH		 3492 return err;
3493 }
3494
fb2690a9 3495 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3496 sky2_read8(hw, B0_CTST);
fb2690a9 3497
b0a20ded 3498 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
fb2690a9 3499
b0a20ded 3500 if (!hw->msi) {
fb2690a9 3501 /* MSI test failed, go back to INTx mode */
b02a9258
SH		 3502 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3503 "switching to INTx mode.\n");
fb2690a9
SH		 3504
3505 err = -EOPNOTSUPP;
3506 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3507 }
3508
3509 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3510 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3511
3512 free_irq(pdev->irq, hw);
3513
3514 return err;
3515}
3516
e3173832
SH		 3517static int __devinit pci_wake_enabled(struct pci_dev *dev)
3518{
3519 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3520 u16 value;
3521
3522 if (!pm)
3523 return 0;
3524 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3525 return 0;
3526 return value & PCI_PM_CTRL_PME_ENABLE;
3527}
3528
cd28ab6a
SH		 3529static int __devinit sky2_probe(struct pci_dev *pdev,
3530 const struct pci_device_id *ent)
3531{
7f60c64b 3532 struct net_device *dev;
cd28ab6a 3533 struct sky2_hw *hw;
e3173832 3534 int err, using_dac = 0, wol_default;
cd28ab6a 3535
793b883e
SH		 3536 err = pci_enable_device(pdev);
3537 if (err) {
b02a9258 3538 dev_err(&pdev->dev, "cannot enable PCI device\n");
cd28ab6a
SH		 3539 goto err_out;
3540 }
3541
793b883e
SH		 3542 err = pci_request_regions(pdev, DRV_NAME);
3543 if (err) {
b02a9258 3544 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
793b883e 3545 goto err_out;
cd28ab6a
SH		 3546 }
3547
3548 pci_set_master(pdev);
3549
d1f3d4dd
SH		 3550 if (sizeof(dma_addr_t) > sizeof(u32) &&
3551 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3552 using_dac = 1;
3553 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3554 if (err < 0) {
b02a9258
SH		 3555 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3556 "for consistent allocations\n");
d1f3d4dd
SH		 3557 goto err_out_free_regions;
3558 }
d1f3d4dd 3559 } else {
cd28ab6a
SH		 3560 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3561 if (err) {
b02a9258 3562 dev_err(&pdev->dev, "no usable DMA configuration\n");
cd28ab6a
SH		 3563 goto err_out_free_regions;
3564 }
3565 }
d1f3d4dd 3566
e3173832
SH		 3567 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3568
cd28ab6a 3569 err = -ENOMEM;
6aad85d6 3570 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a 3571 if (!hw) {
b02a9258 3572 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
cd28ab6a
SH		 3573 goto err_out_free_regions;
3574 }
3575
cd28ab6a 3576 hw->pdev = pdev;
cd28ab6a
SH		 3577
3578 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3579 if (!hw->regs) {
b02a9258 3580 dev_err(&pdev->dev, "cannot map device registers\n");
cd28ab6a
SH		 3581 goto err_out_free_hw;
3582 }
3583
56a645cc 3584#ifdef __BIG_ENDIAN
f65b138c
SH		 3585 /* The sk98lin vendor driver uses hardware byte swapping but
3586 * this driver uses software swapping.
3587 */
56a645cc
SH		 3588 {
3589 u32 reg;
56a645cc 3590 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3591 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3592 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3593 }
3594#endif
3595
08c06d8a
SH		 3596 /* ring for status responses */
3597 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3598 &hw->st_dma);
3599 if (!hw->st_le)
3600 goto err_out_iounmap;
3601
e3173832 3602 err = sky2_init(hw);
cd28ab6a 3603 if (err)
793b883e 3604 goto err_out_iounmap;
cd28ab6a 3605
b02a9258 3606 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
7c7459d1
GKH		 3607 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3608 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3609 hw->chip_id, hw->chip_rev);
cd28ab6a 3610
e3173832
SH		 3611 sky2_reset(hw);
3612
3613 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
7f60c64b 3614 if (!dev) {
3615 err = -ENOMEM;
cd28ab6a 3616 goto err_out_free_pci;
7f60c64b 3617 }
cd28ab6a 3618
9fa1b1f3
SH		 3619 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3620 err = sky2_test_msi(hw);
3621 if (err == -EOPNOTSUPP)
3622 pci_disable_msi(pdev);
3623 else if (err)
3624 goto err_out_free_netdev;
3625 }
3626
793b883e
SH		 3627 err = register_netdev(dev);
3628 if (err) {
b02a9258 3629 dev_err(&pdev->dev, "cannot register net device\n");
cd28ab6a
SH		 3630 goto err_out_free_netdev;
3631 }
3632
b0a20ded
SH		 3633 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3634 dev->name, hw);
9fa1b1f3 3635 if (err) {
b02a9258 3636 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
9fa1b1f3
SH		 3637 goto err_out_unregister;
3638 }
3639 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3640
cd28ab6a
SH		 3641 sky2_show_addr(dev);
3642
7f60c64b 3643 if (hw->ports > 1) {
3644 struct net_device *dev1;
3645
e3173832 3646 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
b02a9258
SH		 3647 if (!dev1)
3648 dev_warn(&pdev->dev, "allocation for second device failed\n");
3649 else if ((err = register_netdev(dev1))) {
3650 dev_warn(&pdev->dev,
3651 "register of second port failed (%d)\n", err);
cd28ab6a
SH		 3652 hw->dev[1] = NULL;
3653 free_netdev(dev1);
b02a9258
SH		 3654 } else
3655 sky2_show_addr(dev1);
cd28ab6a
SH		 3656 }
3657
01bd7564 3658 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
81906791
SH		 3659 INIT_WORK(&hw->restart_work, sky2_restart);
3660
eb35cf60 3661 sky2_idle_start(hw);
d27ed387 3662
793b883e
SH		 3663 pci_set_drvdata(pdev, hw);
3664
cd28ab6a
SH		 3665 return 0;
3666
793b883e 3667err_out_unregister:
b0a20ded
SH		 3668 if (hw->msi)
3669 pci_disable_msi(pdev);
793b883e 3670 unregister_netdev(dev);
cd28ab6a
SH		 3671err_out_free_netdev:
3672 free_netdev(dev);
cd28ab6a 3673err_out_free_pci:
793b883e 3674 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3675 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3676err_out_iounmap:
3677 iounmap(hw->regs);
3678err_out_free_hw:
3679 kfree(hw);
3680err_out_free_regions:
3681 pci_release_regions(pdev);
cd28ab6a 3682 pci_disable_device(pdev);
cd28ab6a
SH		 3683err_out:
3684 return err;
3685}
3686
3687static void __devexit sky2_remove(struct pci_dev *pdev)
3688{
793b883e 3689 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3690 struct net_device *dev0, *dev1;
3691
793b883e 3692 if (!hw)
cd28ab6a
SH		 3693 return;
3694
d27ed387
SH		 3695 del_timer_sync(&hw->idle_timer);
3696
81906791
SH		 3697 flush_scheduled_work();
3698
d27ed387 3699 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3700 synchronize_irq(hw->pdev->irq);
3701
cd28ab6a 3702 dev0 = hw->dev[0];
793b883e
SH		 3703 dev1 = hw->dev[1];
3704 if (dev1)
3705 unregister_netdev(dev1);
cd28ab6a
SH		 3706 unregister_netdev(dev0);
3707
ae306cca
SH		 3708 sky2_power_aux(hw);
3709
cd28ab6a 3710 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3711 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3712 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3713
3714 free_irq(pdev->irq, hw);
b0a20ded
SH		 3715 if (hw->msi)
3716 pci_disable_msi(pdev);
793b883e 3717 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3718 pci_release_regions(pdev);
3719 pci_disable_device(pdev);
793b883e 3720
cd28ab6a
SH		 3721 if (dev1)
3722 free_netdev(dev1);
3723 free_netdev(dev0);
3724 iounmap(hw->regs);
3725 kfree(hw);
5afa0a9c 3726
cd28ab6a
SH		 3727 pci_set_drvdata(pdev, NULL);
3728}
3729
3730#ifdef CONFIG_PM
3731static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3732{
793b883e 3733 struct sky2_hw *hw = pci_get_drvdata(pdev);
e3173832 3734 int i, wol = 0;
cd28ab6a 3735
eb35cf60 3736 del_timer_sync(&hw->idle_timer);
6a5706b9 3737 netif_poll_disable(hw->dev[0]);
eb35cf60 3738
f05267e7 3739 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3740 struct net_device *dev = hw->dev[i];
e3173832 3741 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a 3742
e3173832 3743 if (netif_running(dev))
5afa0a9c 3744 sky2_down(dev);
e3173832
SH		 3745
3746 if (sky2->wol)
3747 sky2_wol_init(sky2);
3748
3749 wol |= sky2->wol;
cd28ab6a
SH		 3750 }
3751
8ab8fca2 3752 sky2_write32(hw, B0_IMSK, 0);
ae306cca 3753 sky2_power_aux(hw);
e3173832 3754
d374c1c1 3755 pci_save_state(pdev);
e3173832 3756 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
ae306cca
SH		 3757 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3758
2ccc99b7 3759 return 0;
cd28ab6a
SH		 3760}
3761
3762static int sky2_resume(struct pci_dev *pdev)
3763{
793b883e 3764 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3765 int i, err;
cd28ab6a 3766
ae306cca
SH		 3767 err = pci_set_power_state(pdev, PCI_D0);
3768 if (err)
3769 goto out;
3770
3771 err = pci_restore_state(pdev);
3772 if (err)
3773 goto out;
3774
cd28ab6a 3775 pci_enable_wake(pdev, PCI_D0, 0);
1ad5b4a5
SH		 3776
3777 /* Re-enable all clocks */
3778 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3779 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3780
e3173832 3781 sky2_reset(hw);
cd28ab6a 3782
8ab8fca2
SH		 3783 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3784
f05267e7 3785 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3786 struct net_device *dev = hw->dev[i];
6a5706b9 3787 if (netif_running(dev)) {
08c06d8a
SH		 3788 err = sky2_up(dev);
3789 if (err) {
3790 printk(KERN_ERR PFX "%s: could not up: %d\n",
3791 dev->name, err);
3792 dev_close(dev);
eb35cf60 3793 goto out;
5afa0a9c 3794 }
cd28ab6a
SH		 3795 }
3796 }
eb35cf60 3797
6a5706b9 3798 netif_poll_enable(hw->dev[0]);
eb35cf60 3799 sky2_idle_start(hw);
ae306cca 3800 return 0;
08c06d8a 3801out:
b02a9258 3802 dev_err(&pdev->dev, "resume failed (%d)\n", err);
ae306cca 3803 pci_disable_device(pdev);
08c06d8a 3804 return err;
cd28ab6a
SH		 3805}
3806#endif
3807
e3173832
SH		 3808static void sky2_shutdown(struct pci_dev *pdev)
3809{
3810 struct sky2_hw *hw = pci_get_drvdata(pdev);
3811 int i, wol = 0;
3812
3813 del_timer_sync(&hw->idle_timer);
3814 netif_poll_disable(hw->dev[0]);
3815
3816 for (i = 0; i < hw->ports; i++) {
3817 struct net_device *dev = hw->dev[i];
3818 struct sky2_port *sky2 = netdev_priv(dev);
3819
3820 if (sky2->wol) {
3821 wol = 1;
3822 sky2_wol_init(sky2);
3823 }
3824 }
3825
3826 if (wol)
3827 sky2_power_aux(hw);
3828
3829 pci_enable_wake(pdev, PCI_D3hot, wol);
3830 pci_enable_wake(pdev, PCI_D3cold, wol);
3831
3832 pci_disable_device(pdev);
3833 pci_set_power_state(pdev, PCI_D3hot);
3834
3835}
3836
cd28ab6a 3837static struct pci_driver sky2_driver = {
793b883e
SH		 3838 .name = DRV_NAME,
3839 .id_table = sky2_id_table,
3840 .probe = sky2_probe,
3841 .remove = __devexit_p(sky2_remove),
cd28ab6a 3842#ifdef CONFIG_PM
793b883e
SH		 3843 .suspend = sky2_suspend,
3844 .resume = sky2_resume,
cd28ab6a 3845#endif
e3173832 3846 .shutdown = sky2_shutdown,
cd28ab6a
SH		 3847};
3848
3849static int __init sky2_init_module(void)
3850{
50241c4c 3851 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3852}
3853
3854static void __exit sky2_cleanup_module(void)
3855{
3856 pci_unregister_driver(&sky2_driver);
3857}
3858
3859module_init(sky2_init_module);
3860module_exit(sky2_cleanup_module);
3861
3862MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
65ebe634 3863MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
cd28ab6a 3864MODULE_LICENSE("GPL");
5f4f9dc1 3865MODULE_VERSION(DRV_VERSION);
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