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sky2: advertising register 16 bits
[mirror_ubuntu-bionic-kernel.git] / drivers / net / sky2.c
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cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
793b883e 26#include <linux/crc32.h>
cd28ab6a
SH		 27#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
c73a29da 53#define DRV_VERSION "1.9"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 66#define RX_SKB_ALIGN 8
22e11703 67#define RX_BUF_WRITE 16
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
cb5d9547
SH		 80#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
cd28ab6a 82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
14d0263f 91static int copybreak __read_mostly = 128;
bdb5c58e
SH		 92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
e561a83b 99static int idle_timeout = 0;
01bd7564 100module_param(idle_timeout, int, 0);
e561a83b 101MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
793b883e 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
cd28ab6a
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
2f4a66ad 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
cd28ab6a
SH		 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
5f5d83fd 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
57fa442c
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
2f4a66ad 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
cd28ab6a
SH		 130 { 0 }
131};
793b883e 132
cd28ab6a
SH		 133MODULE_DEVICE_TABLE(pci, sky2_id_table);
134
135/* Avoid conditionals by using array */
136static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
137static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 138static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 139
92f965e8
SH		 140/* This driver supports yukon2 chipset only */
141static const char *yukon2_name[] = {
142 "XL", /* 0xb3 */
143 "EC Ultra", /* 0xb4 */
144 "UNKNOWN", /* 0xb5 */
145 "EC", /* 0xb6 */
146 "FE", /* 0xb7 */
793b883e
SH		 147};
148
793b883e 149/* Access to external PHY */
ef743d33 150static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 151{
152 int i;
153
154 gma_write16(hw, port, GM_SMI_DATA, val);
155 gma_write16(hw, port, GM_SMI_CTRL,
156 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
157
158 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 159 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 160 return 0;
793b883e 161 udelay(1);
cd28ab6a 162 }
ef743d33 163
793b883e 164 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 165 return -ETIMEDOUT;
cd28ab6a
SH		 166}
167
ef743d33 168static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 169{
170 int i;
171
793b883e 172 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 173 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
174
175 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 176 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
177 *val = gma_read16(hw, port, GM_SMI_DATA);
178 return 0;
179 }
180
793b883e 181 udelay(1);
cd28ab6a
SH		 182 }
183
ef743d33
SH		 184 return -ETIMEDOUT;
185}
186
187static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
188{
189 u16 v;
190
191 if (__gm_phy_read(hw, port, reg, &v) != 0)
192 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
193 return v;
cd28ab6a
SH		 194}
195
2ccc99b7 196static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c
SH		 197{
198 u16 power_control;
5afa0a9c 199 int vaux;
5afa0a9c
SH		 200
201 pr_debug("sky2_set_power_state %d\n", state);
202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
203
56a645cc 204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 205 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 206 (power_control & PCI_PM_CAP_PME_D3cold);
207
56a645cc 208 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 209
210 power_control |= PCI_PM_CTRL_PME_STATUS;
211 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
212
213 switch (state) {
214 case PCI_D0:
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw, B0_POWER_CTRL,
217 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
218
219 /* disable Core Clock Division, */
220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
221
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
223 /* enable bits are inverted */
224 sky2_write8(hw, B2_Y2_CLK_GATE,
225 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
228 else
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
230
977bdf06 231 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb
SH		 232 u32 reg1;
233
56a645cc
SH		 234 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
235 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 236 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 237 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
238 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 239 }
240
5afa0a9c
SH		 241 break;
242
243 case PCI_D3hot:
244 case PCI_D3cold:
5afa0a9c
SH		 245 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
246 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
247 else
248 /* enable bits are inverted */
249 sky2_write8(hw, B2_Y2_CLK_GATE,
250 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
251 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
252 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
253
254 /* switch power to VAUX */
255 if (vaux && state != PCI_D3cold)
256 sky2_write8(hw, B0_POWER_CTRL,
257 (PC_VAUX_ENA | PC_VCC_ENA |
258 PC_VAUX_ON | PC_VCC_OFF));
259 break;
260 default:
261 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c
SH		 262 }
263
56a645cc 264 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 265 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c
SH		 266}
267
d3bcfbeb 268static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 269{
270 u16 reg;
271
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 276
cd28ab6a
SH		 277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
281
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
285}
286
287static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
288{
289 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 290 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 291
ed6d32c7 292 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 293 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 294 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
295
296 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 297 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 298 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
299
300 if (hw->chip_id == CHIP_ID_YUKON_EC)
301 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
302 else
303 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
304
305 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
306 }
307
308 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 309 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 310 if (hw->chip_id == CHIP_ID_YUKON_FE) {
311 /* enable automatic crossover */
312 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
313 } else {
314 /* disable energy detect */
315 ctrl &= ~PHY_M_PC_EN_DET_MSK;
316
317 /* enable automatic crossover */
318 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
319
320 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 321 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 322 ctrl &= ~PHY_M_PC_DSC_MSK;
323 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
324 }
325 }
cd28ab6a
SH		 326 } else {
327 /* workaround for deviation #4.88 (CRC errors) */
328 /* disable Automatic Crossover */
329
330 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 331 }
cd28ab6a 332
b89165f2
SH		 333 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
334
335 /* special setup for PHY 88E1112 Fiber */
336 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
337 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 338
b89165f2
SH		 339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
341 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
342 ctrl &= ~PHY_M_MAC_MD_MSK;
343 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345
346 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 349
350 /* for SFP-module set SIGDET polarity to low */
351 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
352 ctrl |= PHY_M_FIB_SIGD_POL;
353 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 354 }
b89165f2
SH		 355
356 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 357 }
358
359 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
360 if (sky2->autoneg == AUTONEG_DISABLE)
361 ctrl &= ~PHY_CT_ANE;
362 else
363 ctrl |= PHY_CT_ANE;
364
365 ctrl |= PHY_CT_RESET;
366 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
367
368 ctrl = 0;
369 ct1000 = 0;
370 adv = PHY_AN_CSMA;
2eaba1a2 371 reg = 0;
cd28ab6a
SH		 372
373 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 374 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 375 if (sky2->advertising & ADVERTISED_1000baseT_Full)
376 ct1000 |= PHY_M_1000C_AFD;
377 if (sky2->advertising & ADVERTISED_1000baseT_Half)
378 ct1000 |= PHY_M_1000C_AHD;
379 if (sky2->advertising & ADVERTISED_100baseT_Full)
380 adv |= PHY_M_AN_100_FD;
381 if (sky2->advertising & ADVERTISED_100baseT_Half)
382 adv |= PHY_M_AN_100_HD;
383 if (sky2->advertising & ADVERTISED_10baseT_Full)
384 adv |= PHY_M_AN_10_FD;
385 if (sky2->advertising & ADVERTISED_10baseT_Half)
386 adv |= PHY_M_AN_10_HD;
709c6e7b
SH		 387
388 /* desired flow control */
389 if (sky2->tx_pause && sky2->rx_pause) /* both */
390 adv |= PHY_M_AN_PC | PHY_M_AN_ASP;
391 else if (sky2->tx_pause)
392 adv |= PHY_M_AN_ASP;
393 else if (sky2->rx_pause)
394 adv |= PHY_M_AN_PC;
395
396
b89165f2
SH		 397 } else { /* special defines for FIBER (88E1040S only) */
398 if (sky2->advertising & ADVERTISED_1000baseT_Full)
399 adv |= PHY_M_AN_1000X_AFD;
400 if (sky2->advertising & ADVERTISED_1000baseT_Half)
401 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 402
709c6e7b
SH		 403 if (sky2->tx_pause && sky2->rx_pause) /* both */
404 adv |= PHY_M_P_BOTH_MD_X;
405 else if (sky2->tx_pause)
406 adv |= PHY_M_P_ASYM_MD_X;
407 else if (sky2->rx_pause)
408 adv |= PHY_M_P_SYM_MD_X;
409 else
410 adv |= PHY_M_P_NO_PAUSE_X;
411 }
cd28ab6a
SH		 412
413 /* Restart Auto-negotiation */
414 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
415 } else {
416 /* forced speed/duplex settings */
417 ct1000 = PHY_M_1000C_MSE;
418
2eaba1a2
SH		 419 /* Disable auto update for duplex flow control and speed */
420 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 421
422 switch (sky2->speed) {
423 case SPEED_1000:
424 ctrl |= PHY_CT_SP1000;
2eaba1a2 425 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 426 break;
427 case SPEED_100:
428 ctrl |= PHY_CT_SP100;
2eaba1a2 429 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 430 break;
431 }
432
2eaba1a2
SH		 433 if (sky2->duplex == DUPLEX_FULL) {
434 reg |= GM_GPCR_DUP_FULL;
435 ctrl |= PHY_CT_DUP_MD;
436 } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) {
437 /* Turn off flow control for 10/100mbps */
438 sky2->rx_pause = 0;
439 sky2->tx_pause = 0;
440 }
441
442 if (!sky2->rx_pause)
443 reg |= GM_GPCR_FC_RX_DIS;
444
445 if (!sky2->tx_pause)
446 reg |= GM_GPCR_FC_TX_DIS;
447
448 /* Forward pause packets to GMAC? */
449 if (sky2->tx_pause || sky2->rx_pause)
450 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
451 else
452 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
453
cd28ab6a
SH		 454 ctrl |= PHY_CT_RESET;
455 }
456
2eaba1a2
SH		 457 gma_write16(hw, port, GM_GP_CTRL, reg);
458
cd28ab6a
SH		 459 if (hw->chip_id != CHIP_ID_YUKON_FE)
460 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
461
462 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
463 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
464
465 /* Setup Phy LED's */
466 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
467 ledover = 0;
468
469 switch (hw->chip_id) {
470 case CHIP_ID_YUKON_FE:
471 /* on 88E3082 these bits are at 11..9 (shifted left) */
472 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
473
474 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
475
476 /* delete ACT LED control bits */
477 ctrl &= ~PHY_M_FELP_LED1_MSK;
478 /* change ACT LED control to blink mode */
479 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
480 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
481 break;
482
483 case CHIP_ID_YUKON_XL:
793b883e 484 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 485
486 /* select page 3 to access LED control register */
487 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
488
489 /* set LED Function Control register */
ed6d32c7
SH		 490 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
491 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
492 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
493 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
494 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 495
496 /* set Polarity Control register */
497 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 498 (PHY_M_POLC_LS1_P_MIX(4) |
499 PHY_M_POLC_IS0_P_MIX(4) |
500 PHY_M_POLC_LOS_CTRL(2) |
501 PHY_M_POLC_INIT_CTRL(2) |
502 PHY_M_POLC_STA1_CTRL(2) |
503 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 504
505 /* restore page register */
793b883e 506 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 507 break;
ed6d32c7
SH		 508 case CHIP_ID_YUKON_EC_U:
509 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
510
511 /* select page 3 to access LED control register */
512 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
513
514 /* set LED Function Control register */
515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
516 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
517 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
518 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
519 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
520
521 /* set Blink Rate in LED Timer Control Register */
522 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
523 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
524 /* restore page register */
525 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
526 break;
cd28ab6a
SH		 527
528 default:
529 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
530 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
531 /* turn off the Rx LED (LED_RX) */
532 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
533 }
534
ed6d32c7 535 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 536 /* apply fixes in PHY AFE */
ed6d32c7
SH		 537 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
538 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
539
977bdf06 540 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 541 gm_phy_write(hw, port, 0x18, 0xaa99);
542 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 543
977bdf06 544 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 545 gm_phy_write(hw, port, 0x18, 0xa204);
546 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 547
548 /* set page register to 0 */
ed6d32c7 549 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 550 } else {
551 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 552
977bdf06
SH		 553 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
554 /* turn on 100 Mbps LED (LED_LINK100) */
555 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
556 }
cd28ab6a 557
977bdf06
SH		 558 if (ledover)
559 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
560
561 }
2eaba1a2 562
d571b694 563 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 564 if (sky2->autoneg == AUTONEG_ENABLE)
565 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
566 else
567 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
568}
569
d3bcfbeb
SH		 570static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
571{
572 u32 reg1;
573 static const u32 phy_power[]
574 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
575
576 /* looks like this XL is back asswards .. */
577 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
578 onoff = !onoff;
579
580 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
581
582 if (onoff)
583 /* Turn off phy power saving */
584 reg1 &= ~phy_power[port];
585 else
586 reg1 |= phy_power[port];
587
588 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 589 sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 590 udelay(100);
591}
592
1b537565
SH		 593/* Force a renegotiation */
594static void sky2_phy_reinit(struct sky2_port *sky2)
595{
e07b1aa8 596 spin_lock_bh(&sky2->phy_lock);
1b537565 597 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 598 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 599}
600
cd28ab6a
SH		 601static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
602{
603 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
604 u16 reg;
605 int i;
606 const u8 *addr = hw->dev[port]->dev_addr;
607
42eeea01
SH		 608 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
609 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 610
611 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
612
793b883e 613 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 614 /* WA DEV_472 -- looks like crossed wires on port 2 */
615 /* clear GMAC 1 Control reset */
616 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
617 do {
618 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
619 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
620 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
621 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
622 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
623 }
624
793b883e 625 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 626
2eaba1a2
SH		 627 /* Enable Transmit FIFO Underrun */
628 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
629
e07b1aa8 630 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 631 sky2_phy_init(hw, port);
e07b1aa8 632 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 633
634 /* MIB clear */
635 reg = gma_read16(hw, port, GM_PHY_ADDR);
636 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
637
43f2f104
SH		 638 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
639 gma_read16(hw, port, i);
cd28ab6a
SH		 640 gma_write16(hw, port, GM_PHY_ADDR, reg);
641
642 /* transmit control */
643 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
644
645 /* receive control reg: unicast + multicast + no FCS */
646 gma_write16(hw, port, GM_RX_CTRL,
793b883e 647 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 648
649 /* transmit flow control */
650 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
651
652 /* transmit parameter */
653 gma_write16(hw, port, GM_TX_PARAM,
654 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
655 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
656 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
657 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
658
659 /* serial mode register */
660 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 661 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 662
6b1a3aef 663 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 664 reg |= GM_SMOD_JUMBO_ENA;
665
666 gma_write16(hw, port, GM_SERIAL_MODE, reg);
667
cd28ab6a
SH		 668 /* virtual address for data */
669 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
670
793b883e
SH		 671 /* physical address: used for pause frames */
672 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
673
674 /* ignore counter overflows */
cd28ab6a
SH		 675 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
676 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
677 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
678
679 /* Configure Rx MAC FIFO */
680 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 681 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
682 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 683
d571b694 684 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 685 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 686
793b883e
SH		 687 /* Set threshold to 0xa (64 bytes)
688 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 689 */
690 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
691
692 /* Configure Tx MAC FIFO */
693 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
694 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 695
696 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
6e532cfe 697 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8);
5a5b1ea0
SH		 698 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
699 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
700 /* set Tx GMAC FIFO Almost Empty Threshold */
701 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
702 /* Disable Store & Forward mode for TX */
703 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
704 }
705 }
706
cd28ab6a
SH		 707}
708
1c28f6ba
SH		 709/* Assign Ram Buffer allocation.
710 * start and end are in units of 4k bytes
711 * ram registers are in units of 64bit words
712 */
713static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 714{
1c28f6ba 715 u32 start, end;
cd28ab6a 716
1c28f6ba
SH		 717 start = startk * 4096/8;
718 end = (endk * 4096/8) - 1;
793b883e 719
cd28ab6a
SH		 720 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
721 sky2_write32(hw, RB_ADDR(q, RB_START), start);
722 sky2_write32(hw, RB_ADDR(q, RB_END), end);
723 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
724 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
725
726 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 727 u32 space = (endk - startk) * 4096/8;
728 u32 tp = space - space/4;
793b883e 729
1c28f6ba
SH		 730 /* On receive queue's set the thresholds
731 * give receiver priority when > 3/4 full
732 * send pause when down to 2K
733 */
734 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
735 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 736
1c28f6ba
SH		 737 tp = space - 2048/8;
738 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
739 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 740 } else {
741 /* Enable store & forward on Tx queue's because
742 * Tx FIFO is only 1K on Yukon
743 */
744 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
745 }
746
747 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 748 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 749}
750
cd28ab6a 751/* Setup Bus Memory Interface */
af4ed7e6 752static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 753{
754 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
755 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
756 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 757 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 758}
759
cd28ab6a
SH		 760/* Setup prefetch unit registers. This is the interface between
761 * hardware and driver list elements
762 */
8cc048e3 763static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 764 u64 addr, u32 last)
765{
cd28ab6a
SH		 766 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
767 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
768 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
769 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
770 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
771 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 772
773 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 774}
775
793b883e
SH		 776static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
777{
778 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
779
cb5d9547 780 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 781 le->ctrl = 0;
793b883e
SH		 782 return le;
783}
cd28ab6a 784
291ea614
SH		 785static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
786 struct sky2_tx_le *le)
787{
788 return sky2->tx_ring + (le - sky2->tx_le);
789}
790
290d4de5
SH		 791/* Update chip's next pointer */
792static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 793{
98232f85 794 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 795 wmb();
98232f85
SH		 796 sky2_write16(hw, q, idx);
797 sky2_read16(hw, q);
cd28ab6a
SH		 798}
799
793b883e 800
cd28ab6a
SH		 801static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
802{
803 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 804 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 805 le->ctrl = 0;
cd28ab6a
SH		 806 return le;
807}
808
a018e330
SH		 809/* Return high part of DMA address (could be 32 or 64 bit) */
810static inline u32 high32(dma_addr_t a)
811{
a036119f 812 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 813}
814
14d0263f
SH		 815/* Build description to hardware for one receive segment */
816static void sky2_rx_add(struct sky2_port *sky2, u8 op,
817 dma_addr_t map, unsigned len)
cd28ab6a
SH		 818{
819 struct sky2_rx_le *le;
734d1868 820 u32 hi = high32(map);
cd28ab6a 821
793b883e 822 if (sky2->rx_addr64 != hi) {
cd28ab6a 823 le = sky2_next_rx(sky2);
793b883e 824 le->addr = cpu_to_le32(hi);
cd28ab6a 825 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 826 sky2->rx_addr64 = high32(map + len);
cd28ab6a 827 }
793b883e 828
cd28ab6a 829 le = sky2_next_rx(sky2);
734d1868
SH		 830 le->addr = cpu_to_le32((u32) map);
831 le->length = cpu_to_le16(len);
14d0263f 832 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 833}
834
14d0263f
SH		 835/* Build description to hardware for one possibly fragmented skb */
836static void sky2_rx_submit(struct sky2_port *sky2,
837 const struct rx_ring_info *re)
838{
839 int i;
840
841 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
842
843 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
844 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
845}
846
847
848static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
849 unsigned size)
850{
851 struct sk_buff *skb = re->skb;
852 int i;
853
854 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
855 pci_unmap_len_set(re, data_size, size);
856
857 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
858 re->frag_addr[i] = pci_map_page(pdev,
859 skb_shinfo(skb)->frags[i].page,
860 skb_shinfo(skb)->frags[i].page_offset,
861 skb_shinfo(skb)->frags[i].size,
862 PCI_DMA_FROMDEVICE);
863}
864
865static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
866{
867 struct sk_buff *skb = re->skb;
868 int i;
869
870 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
871 PCI_DMA_FROMDEVICE);
872
873 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
874 pci_unmap_page(pdev, re->frag_addr[i],
875 skb_shinfo(skb)->frags[i].size,
876 PCI_DMA_FROMDEVICE);
877}
793b883e 878
cd28ab6a
SH		 879/* Tell chip where to start receive checksum.
880 * Actually has two checksums, but set both same to avoid possible byte
881 * order problems.
882 */
793b883e 883static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 884{
885 struct sky2_rx_le *le;
886
cd28ab6a 887 le = sky2_next_rx(sky2);
f65b138c 888 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 889 le->ctrl = 0;
890 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 891
793b883e
SH		 892 sky2_write32(sky2->hw,
893 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
894 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 895
896}
897
6b1a3aef
SH		 898/*
899 * The RX Stop command will not work for Yukon-2 if the BMU does not
900 * reach the end of packet and since we can't make sure that we have
901 * incoming data, we must reset the BMU while it is not doing a DMA
902 * transfer. Since it is possible that the RX path is still active,
903 * the RX RAM buffer will be stopped first, so any possible incoming
904 * data will not trigger a DMA. After the RAM buffer is stopped, the
905 * BMU is polled until any DMA in progress is ended and only then it
906 * will be reset.
907 */
908static void sky2_rx_stop(struct sky2_port *sky2)
909{
910 struct sky2_hw *hw = sky2->hw;
911 unsigned rxq = rxqaddr[sky2->port];
912 int i;
913
914 /* disable the RAM Buffer receive queue */
915 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
916
917 for (i = 0; i < 0xffff; i++)
918 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
919 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
920 goto stopped;
921
922 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
923 sky2->netdev->name);
924stopped:
925 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
926
927 /* reset the Rx prefetch unit */
928 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
929}
793b883e 930
d571b694 931/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 932static void sky2_rx_clean(struct sky2_port *sky2)
933{
934 unsigned i;
935
936 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 937 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 938 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 939
940 if (re->skb) {
14d0263f 941 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 942 kfree_skb(re->skb);
943 re->skb = NULL;
944 }
945 }
946}
947
ef743d33
SH		 948/* Basic MII support */
949static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
950{
951 struct mii_ioctl_data *data = if_mii(ifr);
952 struct sky2_port *sky2 = netdev_priv(dev);
953 struct sky2_hw *hw = sky2->hw;
954 int err = -EOPNOTSUPP;
955
956 if (!netif_running(dev))
957 return -ENODEV; /* Phy still in reset */
958
d89e1343 959 switch (cmd) {
ef743d33
SH		 960 case SIOCGMIIPHY:
961 data->phy_id = PHY_ADDR_MARV;
962
963 /* fallthru */
964 case SIOCGMIIREG: {
965 u16 val = 0;
91c86df5 966
e07b1aa8 967 spin_lock_bh(&sky2->phy_lock);
ef743d33 968 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 969 spin_unlock_bh(&sky2->phy_lock);
91c86df5 970
ef743d33
SH		 971 data->val_out = val;
972 break;
973 }
974
975 case SIOCSMIIREG:
976 if (!capable(CAP_NET_ADMIN))
977 return -EPERM;
978
e07b1aa8 979 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 980 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
981 data->val_in);
e07b1aa8 982 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 983 break;
984 }
985 return err;
986}
987
d1f13708
SH		 988#ifdef SKY2_VLAN_TAG_USED
989static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
990{
991 struct sky2_port *sky2 = netdev_priv(dev);
992 struct sky2_hw *hw = sky2->hw;
993 u16 port = sky2->port;
d1f13708 994
2bb8c262 995 netif_tx_lock_bh(dev);
d1f13708
SH		 996
997 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
998 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
999 sky2->vlgrp = grp;
1000
2bb8c262 1001 netif_tx_unlock_bh(dev);
d1f13708
SH		 1002}
1003
1004static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1005{
1006 struct sky2_port *sky2 = netdev_priv(dev);
1007 struct sky2_hw *hw = sky2->hw;
1008 u16 port = sky2->port;
d1f13708 1009
2bb8c262 1010 netif_tx_lock_bh(dev);
d1f13708
SH		 1011
1012 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1013 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1014 if (sky2->vlgrp)
1015 sky2->vlgrp->vlan_devices[vid] = NULL;
1016
2bb8c262 1017 netif_tx_unlock_bh(dev);
d1f13708
SH		 1018}
1019#endif
1020
82788c7a 1021/*
14d0263f
SH		 1022 * Allocate an skb for receiving. If the MTU is large enough
1023 * make the skb non-linear with a fragment list of pages.
1024 *
82788c7a
SH		 1025 * It appears the hardware has a bug in the FIFO logic that
1026 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1027 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1028 * aligned except if slab debugging is enabled.
82788c7a 1029 */
14d0263f 1030static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1031{
1032 struct sk_buff *skb;
14d0263f
SH		 1033 unsigned long p;
1034 int i;
82788c7a 1035
14d0263f
SH		 1036 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1037 if (!skb)
1038 goto nomem;
1039
1040 p = (unsigned long) skb->data;
1041 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1042
1043 for (i = 0; i < sky2->rx_nfrags; i++) {
1044 struct page *page = alloc_page(GFP_ATOMIC);
1045
1046 if (!page)
1047 goto free_partial;
1048 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1049 }
1050
1051 return skb;
14d0263f
SH		 1052free_partial:
1053 kfree_skb(skb);
1054nomem:
1055 return NULL;
82788c7a
SH		 1056}
1057
cd28ab6a
SH		 1058/*
1059 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1060 * Normal case this ends up creating one list element for skb
1061 * in the receive ring. Worst case if using large MTU and each
1062 * allocation falls on a different 64 bit region, that results
1063 * in 6 list elements per ring entry.
1064 * One element is used for checksum enable/disable, and one
1065 * extra to avoid wrap.
cd28ab6a 1066 */
6b1a3aef 1067static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1068{
6b1a3aef 1069 struct sky2_hw *hw = sky2->hw;
14d0263f 1070 struct rx_ring_info *re;
6b1a3aef 1071 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1072 unsigned i, size, space, thresh;
cd28ab6a 1073
6b1a3aef 1074 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1075 sky2_qset(hw, rxq);
977bdf06
SH		 1076
1077 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
1078 /* MAC Rx RAM Read is controlled by hardware */
1079 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1080 }
1081
6b1a3aef
SH		 1082 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1083
1084 rx_set_checksum(sky2);
14d0263f
SH		 1085
1086 /* Space needed for frame data + headers rounded up */
1087 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1088 + 8;
1089
1090 /* Stopping point for hardware truncation */
1091 thresh = (size - 8) / sizeof(u32);
1092
1093 /* Account for overhead of skb - to avoid order > 0 allocation */
1094 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1095 + sizeof(struct skb_shared_info);
1096
1097 sky2->rx_nfrags = space >> PAGE_SHIFT;
1098 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1099
1100 if (sky2->rx_nfrags != 0) {
1101 /* Compute residue after pages */
1102 space = sky2->rx_nfrags << PAGE_SHIFT;
1103
1104 if (space < size)
1105 size -= space;
1106 else
1107 size = 0;
1108
1109 /* Optimize to handle small packets and headers */
1110 if (size < copybreak)
1111 size = copybreak;
1112 if (size < ETH_HLEN)
1113 size = ETH_HLEN;
1114 }
1115 sky2->rx_data_size = size;
1116
1117 /* Fill Rx ring */
793b883e 1118 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1119 re = sky2->rx_ring + i;
cd28ab6a 1120
14d0263f 1121 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1122 if (!re->skb)
1123 goto nomem;
1124
14d0263f
SH		 1125 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1126 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1127 }
1128
a1433ac4
SH		 1129 /*
1130 * The receiver hangs if it receives frames larger than the
1131 * packet buffer. As a workaround, truncate oversize frames, but
1132 * the register is limited to 9 bits, so if you do frames > 2052
1133 * you better get the MTU right!
1134 */
a1433ac4
SH		 1135 if (thresh > 0x1ff)
1136 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1137 else {
1138 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1139 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1140 }
1141
6b1a3aef
SH		 1142 /* Tell chip about available buffers */
1143 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1144 return 0;
1145nomem:
1146 sky2_rx_clean(sky2);
1147 return -ENOMEM;
1148}
1149
1150/* Bring up network interface. */
1151static int sky2_up(struct net_device *dev)
1152{
1153 struct sky2_port *sky2 = netdev_priv(dev);
1154 struct sky2_hw *hw = sky2->hw;
1155 unsigned port = sky2->port;
e07b1aa8 1156 u32 ramsize, rxspace, imask;
ee7abb04 1157 int cap, err = -ENOMEM;
843a46f4 1158 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1159
ee7abb04
SH		 1160 /*
1161 * On dual port PCI-X card, there is an problem where status
1162 * can be received out of order due to split transactions
843a46f4 1163 */
ee7abb04
SH		 1164 if (otherdev && netif_running(otherdev) &&
1165 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1166 struct sky2_port *osky2 = netdev_priv(otherdev);
1167 u16 cmd;
1168
1169 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1170 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1171 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1172
1173 sky2->rx_csum = 0;
1174 osky2->rx_csum = 0;
1175 }
843a46f4 1176
cd28ab6a
SH		 1177 if (netif_msg_ifup(sky2))
1178 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1179
1180 /* must be power of 2 */
1181 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1182 TX_RING_SIZE *
1183 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1184 &sky2->tx_le_map);
1185 if (!sky2->tx_le)
1186 goto err_out;
1187
6cdbbdf3 1188 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1189 GFP_KERNEL);
1190 if (!sky2->tx_ring)
1191 goto err_out;
1192 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1193
1194 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1195 &sky2->rx_le_map);
1196 if (!sky2->rx_le)
1197 goto err_out;
1198 memset(sky2->rx_le, 0, RX_LE_BYTES);
1199
291ea614 1200 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1201 GFP_KERNEL);
1202 if (!sky2->rx_ring)
1203 goto err_out;
1204
d3bcfbeb
SH		 1205 sky2_phy_power(hw, port, 1);
1206
cd28ab6a
SH		 1207 sky2_mac_init(hw, port);
1208
1c28f6ba
SH		 1209 /* Determine available ram buffer space (in 4K blocks).
1210 * Note: not sure about the FE setting below yet
1211 */
1212 if (hw->chip_id == CHIP_ID_YUKON_FE)
1213 ramsize = 4;
1214 else
1215 ramsize = sky2_read8(hw, B2_E_0);
1216
1217 /* Give transmitter one third (rounded up) */
1218 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1219
cd28ab6a 1220 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1221 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1222
793b883e
SH		 1223 /* Make sure SyncQ is disabled */
1224 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1225 RB_RST_SET);
1226
af4ed7e6 1227 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1228
977bdf06 1229 /* Set almost empty threshold */
c2716fb4
SH		 1230 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1231 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1232 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1233
6b1a3aef
SH		 1234 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1235 TX_RING_SIZE - 1);
cd28ab6a 1236
6b1a3aef 1237 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1238 if (err)
1239 goto err_out;
1240
cd28ab6a 1241 /* Enable interrupts from phy/mac for port */
e07b1aa8 1242 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1243 imask |= portirq_msk[port];
e07b1aa8
SH		 1244 sky2_write32(hw, B0_IMSK, imask);
1245
cd28ab6a
SH		 1246 return 0;
1247
1248err_out:
1b537565 1249 if (sky2->rx_le) {
cd28ab6a
SH		 1250 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1251 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1252 sky2->rx_le = NULL;
1253 }
1254 if (sky2->tx_le) {
cd28ab6a
SH		 1255 pci_free_consistent(hw->pdev,
1256 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1257 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1258 sky2->tx_le = NULL;
1259 }
1260 kfree(sky2->tx_ring);
1261 kfree(sky2->rx_ring);
cd28ab6a 1262
1b537565
SH		 1263 sky2->tx_ring = NULL;
1264 sky2->rx_ring = NULL;
cd28ab6a
SH		 1265 return err;
1266}
1267
793b883e
SH		 1268/* Modular subtraction in ring */
1269static inline int tx_dist(unsigned tail, unsigned head)
1270{
cb5d9547 1271 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1272}
cd28ab6a 1273
793b883e
SH		 1274/* Number of list elements available for next tx */
1275static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1276{
793b883e 1277 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1278}
1279
793b883e 1280/* Estimate of number of transmit list elements required */
28bd181a 1281static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1282{
793b883e
SH		 1283 unsigned count;
1284
1285 count = sizeof(dma_addr_t) / sizeof(u32);
1286 count += skb_shinfo(skb)->nr_frags * count;
1287
89114afd 1288 if (skb_is_gso(skb))
793b883e
SH		 1289 ++count;
1290
84fa7933 1291 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1292 ++count;
1293
1294 return count;
cd28ab6a
SH		 1295}
1296
793b883e
SH		 1297/*
1298 * Put one packet in ring for transmit.
1299 * A single packet can generate multiple list elements, and
1300 * the number of ring elements will probably be less than the number
1301 * of list elements used.
1302 */
cd28ab6a
SH		 1303static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1304{
1305 struct sky2_port *sky2 = netdev_priv(dev);
1306 struct sky2_hw *hw = sky2->hw;
d1f13708 1307 struct sky2_tx_le *le = NULL;
6cdbbdf3 1308 struct tx_ring_info *re;
cd28ab6a
SH		 1309 unsigned i, len;
1310 dma_addr_t mapping;
1311 u32 addr64;
1312 u16 mss;
1313 u8 ctrl;
1314
2bb8c262
SH		 1315 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1316 return NETDEV_TX_BUSY;
cd28ab6a 1317
793b883e 1318 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1319 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1320 dev->name, sky2->tx_prod, skb->len);
1321
cd28ab6a
SH		 1322 len = skb_headlen(skb);
1323 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1324 addr64 = high32(mapping);
793b883e 1325
a018e330
SH		 1326 /* Send high bits if changed or crosses boundary */
1327 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1328 le = get_tx_le(sky2);
f65b138c 1329 le->addr = cpu_to_le32(addr64);
793b883e 1330 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1331 sky2->tx_addr64 = high32(mapping + len);
793b883e 1332 }
cd28ab6a
SH		 1333
1334 /* Check for TCP Segmentation Offload */
7967168c 1335 mss = skb_shinfo(skb)->gso_size;
793b883e 1336 if (mss != 0) {
cd28ab6a
SH		 1337 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1338 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1339 mss += ETH_HLEN;
1340
e07560cd
SH		 1341 if (mss != sky2->tx_last_mss) {
1342 le = get_tx_le(sky2);
f65b138c 1343 le->addr = cpu_to_le32(mss);
e07560cd 1344 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1345 sky2->tx_last_mss = mss;
1346 }
cd28ab6a
SH		 1347 }
1348
cd28ab6a 1349 ctrl = 0;
d1f13708
SH		 1350#ifdef SKY2_VLAN_TAG_USED
1351 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1352 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1353 if (!le) {
1354 le = get_tx_le(sky2);
f65b138c 1355 le->addr = 0;
d1f13708 1356 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1357 } else
1358 le->opcode |= OP_VLAN;
1359 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1360 ctrl |= INS_VLAN;
1361 }
1362#endif
1363
1364 /* Handle TCP checksum offload */
84fa7933 1365 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1366 unsigned offset = skb->h.raw - skb->data;
1367 u32 tcpsum;
1368
1369 tcpsum = offset << 16; /* sum start */
1370 tcpsum |= offset + skb->csum; /* sum write */
cd28ab6a
SH		 1371
1372 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1373 if (skb->nh.iph->protocol == IPPROTO_UDP)
1374 ctrl |= UDPTCP;
1375
f65b138c
SH		 1376 if (tcpsum != sky2->tx_tcpsum) {
1377 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1378
1379 le = get_tx_le(sky2);
f65b138c 1380 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1381 le->length = 0; /* initial checksum value */
1382 le->ctrl = 1; /* one packet */
1383 le->opcode = OP_TCPLISW | HW_OWNER;
1384 }
cd28ab6a
SH		 1385 }
1386
1387 le = get_tx_le(sky2);
f65b138c 1388 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1389 le->length = cpu_to_le16(len);
1390 le->ctrl = ctrl;
793b883e 1391 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1392
291ea614 1393 re = tx_le_re(sky2, le);
cd28ab6a 1394 re->skb = skb;
6cdbbdf3 1395 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1396 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1397
1398 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1399 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1400
1401 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1402 frag->size, PCI_DMA_TODEVICE);
a036119f 1403 addr64 = high32(mapping);
793b883e
SH		 1404 if (addr64 != sky2->tx_addr64) {
1405 le = get_tx_le(sky2);
f65b138c 1406 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1407 le->ctrl = 0;
1408 le->opcode = OP_ADDR64 | HW_OWNER;
1409 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1410 }
1411
1412 le = get_tx_le(sky2);
f65b138c 1413 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1414 le->length = cpu_to_le16(frag->size);
1415 le->ctrl = ctrl;
793b883e 1416 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1417
291ea614
SH		 1418 re = tx_le_re(sky2, le);
1419 re->skb = skb;
1420 pci_unmap_addr_set(re, mapaddr, mapping);
1421 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1422 }
6cdbbdf3 1423
cd28ab6a
SH		 1424 le->ctrl |= EOP;
1425
97bda706
SH		 1426 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1427 netif_stop_queue(dev);
b19666d9 1428
290d4de5 1429 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1430
cd28ab6a
SH		 1431 dev->trans_start = jiffies;
1432 return NETDEV_TX_OK;
1433}
1434
cd28ab6a 1435/*
793b883e
SH		 1436 * Free ring elements from starting at tx_cons until "done"
1437 *
1438 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1439 * buffers so make sure not to free skb to early.
cd28ab6a 1440 */
d11c13e7 1441static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1442{
d11c13e7 1443 struct net_device *dev = sky2->netdev;
af2a58ac 1444 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1445 unsigned idx;
cd28ab6a 1446
0e3ff6aa 1447 BUG_ON(done >= TX_RING_SIZE);
2224795d 1448
291ea614
SH		 1449 for (idx = sky2->tx_cons; idx != done;
1450 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1451 struct sky2_tx_le *le = sky2->tx_le + idx;
1452 struct tx_ring_info *re = sky2->tx_ring + idx;
1453
1454 switch(le->opcode & ~HW_OWNER) {
1455 case OP_LARGESEND:
1456 case OP_PACKET:
1457 pci_unmap_single(pdev,
1458 pci_unmap_addr(re, mapaddr),
1459 pci_unmap_len(re, maplen),
1460 PCI_DMA_TODEVICE);
af2a58ac 1461 break;
291ea614
SH		 1462 case OP_BUFFER:
1463 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1464 pci_unmap_len(re, maplen),
734d1868 1465 PCI_DMA_TODEVICE);
291ea614
SH		 1466 break;
1467 }
1468
1469 if (le->ctrl & EOP) {
1470 if (unlikely(netif_msg_tx_done(sky2)))
1471 printk(KERN_DEBUG "%s: tx done %u\n",
1472 dev->name, idx);
1473 dev_kfree_skb(re->skb);
cd28ab6a
SH		 1474 }
1475
291ea614 1476 le->opcode = 0; /* paranoia */
793b883e 1477 }
793b883e 1478
291ea614 1479 sky2->tx_cons = idx;
22e11703 1480 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1481 netif_wake_queue(dev);
cd28ab6a
SH		 1482}
1483
1484/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1485static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1486{
2bb8c262
SH		 1487 struct sky2_port *sky2 = netdev_priv(dev);
1488
1489 netif_tx_lock_bh(dev);
d11c13e7 1490 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1491 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1492}
1493
1494/* Network shutdown */
1495static int sky2_down(struct net_device *dev)
1496{
1497 struct sky2_port *sky2 = netdev_priv(dev);
1498 struct sky2_hw *hw = sky2->hw;
1499 unsigned port = sky2->port;
1500 u16 ctrl;
e07b1aa8 1501 u32 imask;
cd28ab6a 1502
1b537565
SH		 1503 /* Never really got started! */
1504 if (!sky2->tx_le)
1505 return 0;
1506
cd28ab6a
SH		 1507 if (netif_msg_ifdown(sky2))
1508 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1509
018d1c66 1510 /* Stop more packets from being queued */
cd28ab6a
SH		 1511 netif_stop_queue(dev);
1512
ebc646f6
SH		 1513 /* Disable port IRQ */
1514 imask = sky2_read32(hw, B0_IMSK);
1515 imask &= ~portirq_msk[port];
1516 sky2_write32(hw, B0_IMSK, imask);
1517
d3bcfbeb 1518 sky2_gmac_reset(hw, port);
793b883e 1519
cd28ab6a
SH		 1520 /* Stop transmitter */
1521 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1522 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1523
1524 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1525 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1526
c2716fb4
SH		 1527 /* WA for dev. #4.209 */
1528 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1529 && hw->chip_rev == CHIP_REV_YU_EC_U_A1)
1530 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1531 sky2->speed != SPEED_1000 ?
1532 TX_STFW_ENA : TX_STFW_DIS);
1533
cd28ab6a 1534 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1535 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1536 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1537
1538 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1539
1540 /* Workaround shared GMAC reset */
793b883e
SH		 1541 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1542 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1543 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1544
1545 /* Disable Force Sync bit and Enable Alloc bit */
1546 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1547 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1548
1549 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1550 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1551 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1552
1553 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1554 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1555 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1556
1557 /* Reset the Tx prefetch units */
1558 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1559 PREF_UNIT_RST_SET);
1560
1561 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1562
6b1a3aef 1563 sky2_rx_stop(sky2);
cd28ab6a
SH		 1564
1565 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1566 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1567
d3bcfbeb
SH		 1568 sky2_phy_power(hw, port, 0);
1569
d571b694 1570 /* turn off LED's */
cd28ab6a
SH		 1571 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1572
018d1c66
SH		 1573 synchronize_irq(hw->pdev->irq);
1574
2bb8c262 1575 sky2_tx_clean(dev);
cd28ab6a
SH		 1576 sky2_rx_clean(sky2);
1577
1578 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1579 sky2->rx_le, sky2->rx_le_map);
1580 kfree(sky2->rx_ring);
1581
1582 pci_free_consistent(hw->pdev,
1583 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1584 sky2->tx_le, sky2->tx_le_map);
1585 kfree(sky2->tx_ring);
1586
1b537565
SH		 1587 sky2->tx_le = NULL;
1588 sky2->rx_le = NULL;
1589
1590 sky2->rx_ring = NULL;
1591 sky2->tx_ring = NULL;
1592
cd28ab6a
SH		 1593 return 0;
1594}
1595
1596static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1597{
b89165f2 1598 if (!sky2_is_copper(hw))
793b883e
SH		 1599 return SPEED_1000;
1600
cd28ab6a
SH		 1601 if (hw->chip_id == CHIP_ID_YUKON_FE)
1602 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1603
1604 switch (aux & PHY_M_PS_SPEED_MSK) {
1605 case PHY_M_PS_SPEED_1000:
1606 return SPEED_1000;
1607 case PHY_M_PS_SPEED_100:
1608 return SPEED_100;
1609 default:
1610 return SPEED_10;
1611 }
1612}
1613
1614static void sky2_link_up(struct sky2_port *sky2)
1615{
1616 struct sky2_hw *hw = sky2->hw;
1617 unsigned port = sky2->port;
1618 u16 reg;
1619
cd28ab6a 1620 /* enable Rx/Tx */
2eaba1a2 1621 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1622 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1623 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1624
1625 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1626
1627 netif_carrier_on(sky2->netdev);
1628 netif_wake_queue(sky2->netdev);
1629
1630 /* Turn on link LED */
793b883e 1631 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1632 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1633
ed6d32c7 1634 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1635 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1636 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1637
1638 switch(sky2->speed) {
1639 case SPEED_10:
1640 led |= PHY_M_LEDC_INIT_CTRL(7);
1641 break;
1642
1643 case SPEED_100:
1644 led |= PHY_M_LEDC_STA1_CTRL(7);
1645 break;
1646
1647 case SPEED_1000:
1648 led |= PHY_M_LEDC_STA0_CTRL(7);
1649 break;
1650 }
793b883e
SH		 1651
1652 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1653 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1654 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1655 }
1656
cd28ab6a
SH		 1657 if (netif_msg_link(sky2))
1658 printk(KERN_INFO PFX
d571b694 1659 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1660 sky2->netdev->name, sky2->speed,
1661 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1662 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1663 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1664}
1665
1666static void sky2_link_down(struct sky2_port *sky2)
1667{
1668 struct sky2_hw *hw = sky2->hw;
1669 unsigned port = sky2->port;
1670 u16 reg;
1671
1672 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1673
1674 reg = gma_read16(hw, port, GM_GP_CTRL);
1675 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1676 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1677
1678 if (sky2->rx_pause && !sky2->tx_pause) {
1679 /* restore Asymmetric Pause bit */
1680 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1681 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1682 | PHY_M_AN_ASP);
cd28ab6a
SH		 1683 }
1684
cd28ab6a
SH		 1685 netif_carrier_off(sky2->netdev);
1686 netif_stop_queue(sky2->netdev);
1687
1688 /* Turn on link LED */
1689 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1690
1691 if (netif_msg_link(sky2))
1692 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1693
cd28ab6a
SH		 1694 sky2_phy_init(hw, port);
1695}
1696
793b883e
SH		 1697static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1698{
1699 struct sky2_hw *hw = sky2->hw;
1700 unsigned port = sky2->port;
1701 u16 lpa;
1702
1703 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1704
1705 if (lpa & PHY_M_AN_RF) {
1706 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1707 return -1;
1708 }
1709
793b883e
SH		 1710 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1711 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1712 sky2->netdev->name);
1713 return -1;
1714 }
1715
793b883e 1716 sky2->speed = sky2_phy_speed(hw, aux);
e0ed5459
SH		 1717 if (sky2->speed == SPEED_1000) {
1718 u16 ctl2 = gm_phy_read(hw, port, PHY_MARV_1000T_CTRL);
1719 u16 lpa2 = gm_phy_read(hw, port, PHY_MARV_1000T_STAT);
1720 if (lpa2 & PHY_B_1000S_MSF) {
1721 printk(KERN_ERR PFX "%s: master/slave fault",
1722 sky2->netdev->name);
1723 return -1;
1724 }
1725
1726 if ((ctl2 & PHY_M_1000C_AFD) && (lpa2 & PHY_B_1000S_LP_FD))
1727 sky2->duplex = DUPLEX_FULL;
1728 else
1729 sky2->duplex = DUPLEX_HALF;
1730 } else {
1731 u16 adv = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1732 if ((aux & adv) & PHY_AN_FULL)
1733 sky2->duplex = DUPLEX_FULL;
1734 else
1735 sky2->duplex = DUPLEX_HALF;
1736 }
793b883e
SH		 1737
1738 /* Pause bits are offset (9..8) */
ed6d32c7 1739 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1740 aux >>= 6;
1741
1742 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1743 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1744
2eaba1a2
SH		 1745 if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000
1746 && hw->chip_id != CHIP_ID_YUKON_EC_U)
1747 sky2->rx_pause = sky2->tx_pause = 0;
1748
1749 if (sky2->rx_pause || sky2->tx_pause)
793b883e
SH		 1750 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1751 else
1752 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1753
1754 return 0;
1755}
cd28ab6a 1756
e07b1aa8
SH		 1757/* Interrupt from PHY */
1758static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1759{
e07b1aa8
SH		 1760 struct net_device *dev = hw->dev[port];
1761 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1762 u16 istatus, phystat;
1763
ebc646f6
SH		 1764 if (!netif_running(dev))
1765 return;
1766
e07b1aa8
SH		 1767 spin_lock(&sky2->phy_lock);
1768 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1769 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1770
cd28ab6a
SH		 1771 if (netif_msg_intr(sky2))
1772 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1773 sky2->netdev->name, istatus, phystat);
1774
2eaba1a2 1775 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1776 if (sky2_autoneg_done(sky2, phystat) == 0)
1777 sky2_link_up(sky2);
1778 goto out;
1779 }
cd28ab6a 1780
793b883e
SH		 1781 if (istatus & PHY_M_IS_LSP_CHANGE)
1782 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1783
793b883e
SH		 1784 if (istatus & PHY_M_IS_DUP_CHANGE)
1785 sky2->duplex =
1786 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1787
793b883e
SH		 1788 if (istatus & PHY_M_IS_LST_CHANGE) {
1789 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1790 sky2_link_up(sky2);
793b883e
SH		 1791 else
1792 sky2_link_down(sky2);
cd28ab6a 1793 }
793b883e 1794out:
e07b1aa8 1795 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1796}
1797
302d1252
SH		 1798
1799/* Transmit timeout is only called if we are running, carries is up
1800 * and tx queue is full (stopped).
1801 */
cd28ab6a
SH		 1802static void sky2_tx_timeout(struct net_device *dev)
1803{
1804 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1805 struct sky2_hw *hw = sky2->hw;
1806 unsigned txq = txqaddr[sky2->port];
8f24664d 1807 u16 report, done;
cd28ab6a
SH		 1808
1809 if (netif_msg_timer(sky2))
1810 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1811
8f24664d
SH		 1812 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1813 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1814
8f24664d
SH		 1815 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1816 dev->name,
1817 sky2->tx_cons, sky2->tx_prod, report, done);
1818
1819 if (report != done) {
1820 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1821
1822 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1823 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1824 } else if (report != sky2->tx_cons) {
1825 printk(KERN_INFO PFX "status report lost?\n");
1826
2bb8c262 1827 netif_tx_lock_bh(dev);
8f24664d 1828 sky2_tx_complete(sky2, report);
2bb8c262 1829 netif_tx_unlock_bh(dev);
8f24664d
SH		 1830 } else {
1831 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1832
8f24664d
SH		 1833 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1834 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1835
2bb8c262 1836 sky2_tx_clean(dev);
8f24664d
SH		 1837
1838 sky2_qset(hw, txq);
1839 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1840 }
cd28ab6a
SH		 1841}
1842
1843static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1844{
6b1a3aef
SH		 1845 struct sky2_port *sky2 = netdev_priv(dev);
1846 struct sky2_hw *hw = sky2->hw;
1847 int err;
1848 u16 ctl, mode;
e07b1aa8 1849 u32 imask;
cd28ab6a
SH		 1850
1851 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1852 return -EINVAL;
1853
5a5b1ea0
SH		 1854 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1855 return -EINVAL;
1856
6b1a3aef
SH		 1857 if (!netif_running(dev)) {
1858 dev->mtu = new_mtu;
1859 return 0;
1860 }
1861
e07b1aa8 1862 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1863 sky2_write32(hw, B0_IMSK, 0);
1864
018d1c66
SH		 1865 dev->trans_start = jiffies; /* prevent tx timeout */
1866 netif_stop_queue(dev);
1867 netif_poll_disable(hw->dev[0]);
1868
e07b1aa8
SH		 1869 synchronize_irq(hw->pdev->irq);
1870
6b1a3aef
SH		 1871 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1872 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1873 sky2_rx_stop(sky2);
1874 sky2_rx_clean(sky2);
cd28ab6a
SH		 1875
1876 dev->mtu = new_mtu;
14d0263f 1877
6b1a3aef
SH		 1878 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1879 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1880
1881 if (dev->mtu > ETH_DATA_LEN)
1882 mode |= GM_SMOD_JUMBO_ENA;
1883
1884 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1885
6b1a3aef 1886 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1887
6b1a3aef 1888 err = sky2_rx_start(sky2);
e07b1aa8 1889 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1890
1b537565
SH		 1891 if (err)
1892 dev_close(dev);
1893 else {
1894 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1895
1896 netif_poll_enable(hw->dev[0]);
1897 netif_wake_queue(dev);
1898 }
1899
cd28ab6a
SH		 1900 return err;
1901}
1902
14d0263f
SH		 1903/* For small just reuse existing skb for next receive */
1904static struct sk_buff *receive_copy(struct sky2_port *sky2,
1905 const struct rx_ring_info *re,
1906 unsigned length)
1907{
1908 struct sk_buff *skb;
1909
1910 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1911 if (likely(skb)) {
1912 skb_reserve(skb, 2);
1913 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1914 length, PCI_DMA_FROMDEVICE);
1915 memcpy(skb->data, re->skb->data, length);
1916 skb->ip_summed = re->skb->ip_summed;
1917 skb->csum = re->skb->csum;
1918 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1919 length, PCI_DMA_FROMDEVICE);
1920 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1921 skb_put(skb, length);
14d0263f
SH		 1922 }
1923 return skb;
1924}
1925
1926/* Adjust length of skb with fragments to match received data */
1927static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1928 unsigned int length)
1929{
1930 int i, num_frags;
1931 unsigned int size;
1932
1933 /* put header into skb */
1934 size = min(length, hdr_space);
1935 skb->tail += size;
1936 skb->len += size;
1937 length -= size;
1938
1939 num_frags = skb_shinfo(skb)->nr_frags;
1940 for (i = 0; i < num_frags; i++) {
1941 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1942
1943 if (length == 0) {
1944 /* don't need this page */
1945 __free_page(frag->page);
1946 --skb_shinfo(skb)->nr_frags;
1947 } else {
1948 size = min(length, (unsigned) PAGE_SIZE);
1949
1950 frag->size = size;
1951 skb->data_len += size;
1952 skb->truesize += size;
1953 skb->len += size;
1954 length -= size;
1955 }
1956 }
1957}
1958
1959/* Normal packet - take skb from ring element and put in a new one */
1960static struct sk_buff *receive_new(struct sky2_port *sky2,
1961 struct rx_ring_info *re,
1962 unsigned int length)
1963{
1964 struct sk_buff *skb, *nskb;
1965 unsigned hdr_space = sky2->rx_data_size;
1966
1967 pr_debug(PFX "receive new length=%d\n", length);
1968
1969 /* Don't be tricky about reusing pages (yet) */
1970 nskb = sky2_rx_alloc(sky2);
1971 if (unlikely(!nskb))
1972 return NULL;
1973
1974 skb = re->skb;
1975 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1976
1977 prefetch(skb->data);
1978 re->skb = nskb;
1979 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1980
1981 if (skb_shinfo(skb)->nr_frags)
1982 skb_put_frags(skb, hdr_space, length);
1983 else
489b10c1 1984 skb_put(skb, length);
14d0263f
SH		 1985 return skb;
1986}
1987
cd28ab6a
SH		 1988/*
1989 * Receive one packet.
d571b694 1990 * For larger packets, get new buffer.
cd28ab6a 1991 */
497d7c86 1992static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1993 u16 length, u32 status)
1994{
497d7c86 1995 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 1996 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1997 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1998
1999 if (unlikely(netif_msg_rx_status(sky2)))
2000 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 2001 dev->name, sky2->rx_next, status, length);
cd28ab6a 2002
793b883e 2003 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 2004 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 2005
42eeea01 2006 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 2007 goto error;
2008
42eeea01
SH		 2009 if (!(status & GMR_FS_RX_OK))
2010 goto resubmit;
2011
497d7c86 2012 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 2013 goto oversize;
2014
14d0263f
SH		 2015 if (length < copybreak)
2016 skb = receive_copy(sky2, re, length);
2017 else
2018 skb = receive_new(sky2, re, length);
793b883e 2019resubmit:
14d0263f 2020 sky2_rx_submit(sky2, re);
79e57d32 2021
cd28ab6a
SH		 2022 return skb;
2023
6e15b712
SH		 2024oversize:
2025 ++sky2->net_stats.rx_over_errors;
2026 goto resubmit;
2027
cd28ab6a 2028error:
6e15b712
SH		 2029 ++sky2->net_stats.rx_errors;
2030
3be92a70 2031 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2032 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2033 dev->name, status, length);
793b883e
SH		 2034
2035 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2036 sky2->net_stats.rx_length_errors++;
2037 if (status & GMR_FS_FRAGMENT)
2038 sky2->net_stats.rx_frame_errors++;
2039 if (status & GMR_FS_CRC_ERR)
2040 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 2041 if (status & GMR_FS_RX_FF_OV)
2042 sky2->net_stats.rx_fifo_errors++;
79e57d32 2043
793b883e 2044 goto resubmit;
cd28ab6a
SH		 2045}
2046
e07b1aa8
SH		 2047/* Transmit complete */
2048static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2049{
e07b1aa8 2050 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2051
e07b1aa8 2052 if (netif_running(dev)) {
2bb8c262 2053 netif_tx_lock(dev);
e07b1aa8 2054 sky2_tx_complete(sky2, last);
2bb8c262 2055 netif_tx_unlock(dev);
2224795d 2056 }
cd28ab6a
SH		 2057}
2058
e07b1aa8
SH		 2059/* Process status response ring */
2060static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2061{
22e11703 2062 struct sky2_port *sky2;
e07b1aa8 2063 int work_done = 0;
22e11703 2064 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2065 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2066
af2a58ac 2067 rmb();
bea86103 2068
e71ebd73 2069 while (hw->st_idx != hwidx) {
13210ce5
SH		 2070 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2071 struct net_device *dev;
cd28ab6a 2072 struct sk_buff *skb;
cd28ab6a
SH		 2073 u32 status;
2074 u16 length;
2075
cb5d9547 2076 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2077
e71ebd73
SH		 2078 BUG_ON(le->link >= 2);
2079 dev = hw->dev[le->link];
13210ce5
SH		 2080
2081 sky2 = netdev_priv(dev);
f65b138c
SH		 2082 length = le16_to_cpu(le->length);
2083 status = le32_to_cpu(le->status);
cd28ab6a 2084
e71ebd73 2085 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2086 case OP_RXSTAT:
497d7c86 2087 skb = sky2_receive(dev, length, status);
d1f13708
SH		 2088 if (!skb)
2089 break;
13210ce5 2090
13210ce5
SH		 2091 skb->protocol = eth_type_trans(skb, dev);
2092 dev->last_rx = jiffies;
2093
d1f13708
SH		 2094#ifdef SKY2_VLAN_TAG_USED
2095 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2096 vlan_hwaccel_receive_skb(skb,
2097 sky2->vlgrp,
2098 be16_to_cpu(sky2->rx_tag));
2099 } else
2100#endif
cd28ab6a 2101 netif_receive_skb(skb);
13210ce5 2102
22e11703
SH		 2103 /* Update receiver after 16 frames */
2104 if (++buf_write[le->link] == RX_BUF_WRITE) {
2105 sky2_put_idx(hw, rxqaddr[le->link],
2106 sky2->rx_put);
2107 buf_write[le->link] = 0;
2108 }
2109
2110 /* Stop after net poll weight */
13210ce5
SH		 2111 if (++work_done >= to_do)
2112 goto exit_loop;
cd28ab6a
SH		 2113 break;
2114
d1f13708
SH		 2115#ifdef SKY2_VLAN_TAG_USED
2116 case OP_RXVLAN:
2117 sky2->rx_tag = length;
2118 break;
2119
2120 case OP_RXCHKSVLAN:
2121 sky2->rx_tag = length;
2122 /* fall through */
2123#endif
cd28ab6a 2124 case OP_RXCHKS:
d11c13e7 2125 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2126 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2127 skb->csum = status & 0xffff;
cd28ab6a
SH		 2128 break;
2129
2130 case OP_TXINDEXLE:
13b97b74 2131 /* TX index reports status for both ports */
f55925d7
SH		 2132 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2133 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2134 if (hw->dev[1])
2135 sky2_tx_done(hw->dev[1],
2136 ((status >> 24) & 0xff)
2137 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2138 break;
2139
cd28ab6a
SH		 2140 default:
2141 if (net_ratelimit())
793b883e 2142 printk(KERN_WARNING PFX
e71ebd73
SH		 2143 "unknown status opcode 0x%x\n", le->opcode);
2144 goto exit_loop;
cd28ab6a 2145 }
13210ce5 2146 }
cd28ab6a 2147
fe2a24df
SH		 2148 /* Fully processed status ring so clear irq */
2149 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2150
13210ce5 2151exit_loop:
22e11703
SH		 2152 if (buf_write[0]) {
2153 sky2 = netdev_priv(hw->dev[0]);
2154 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2155 }
2156
2157 if (buf_write[1]) {
2158 sky2 = netdev_priv(hw->dev[1]);
2159 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2160 }
2161
e07b1aa8 2162 return work_done;
cd28ab6a
SH		 2163}
2164
2165static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2166{
2167 struct net_device *dev = hw->dev[port];
2168
3be92a70
SH		 2169 if (net_ratelimit())
2170 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2171 dev->name, status);
cd28ab6a
SH		 2172
2173 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2174 if (net_ratelimit())
2175 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2176 dev->name);
cd28ab6a
SH		 2177 /* Clear IRQ */
2178 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2179 }
2180
2181 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2182 if (net_ratelimit())
2183 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2184 dev->name);
cd28ab6a
SH		 2185
2186 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2187 }
2188
2189 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2190 if (net_ratelimit())
2191 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2192 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2193 }
2194
2195 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2196 if (net_ratelimit())
2197 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2198 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2199 }
2200
2201 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2202 if (net_ratelimit())
2203 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2204 dev->name);
cd28ab6a
SH		 2205 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2206 }
2207}
2208
2209static void sky2_hw_intr(struct sky2_hw *hw)
2210{
2211 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2212
793b883e 2213 if (status & Y2_IS_TIST_OV)
cd28ab6a 2214 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2215
2216 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2217 u16 pci_err;
2218
56a645cc 2219 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2220 if (net_ratelimit())
2221 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2222 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2223
2224 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2225 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2226 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2227 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2228 }
2229
2230 if (status & Y2_IS_PCI_EXP) {
d571b694 2231 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2232 u32 pex_err;
2233
7bd656d1 2234 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2235
3be92a70
SH		 2236 if (net_ratelimit())
2237 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2238 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2239
2240 /* clear the interrupt */
2241 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2242 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2243 0xffffffffUL);
cd28ab6a
SH		 2244 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2245
7bd656d1 2246 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2247 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2248 hwmsk &= ~Y2_IS_PCI_EXP;
2249 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2250 }
2251 }
2252
2253 if (status & Y2_HWE_L1_MASK)
2254 sky2_hw_error(hw, 0, status);
2255 status >>= 8;
2256 if (status & Y2_HWE_L1_MASK)
2257 sky2_hw_error(hw, 1, status);
2258}
2259
2260static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2261{
2262 struct net_device *dev = hw->dev[port];
2263 struct sky2_port *sky2 = netdev_priv(dev);
2264 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2265
2266 if (netif_msg_intr(sky2))
2267 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2268 dev->name, status);
2269
2270 if (status & GM_IS_RX_FF_OR) {
2271 ++sky2->net_stats.rx_fifo_errors;
2272 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2273 }
2274
2275 if (status & GM_IS_TX_FF_UR) {
2276 ++sky2->net_stats.tx_fifo_errors;
2277 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2278 }
cd28ab6a
SH		 2279}
2280
d257924e
SH		 2281/* This should never happen it is a fatal situation */
2282static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2283 const char *rxtx, u32 mask)
2284{
2285 struct net_device *dev = hw->dev[port];
2286 struct sky2_port *sky2 = netdev_priv(dev);
2287 u32 imask;
2288
2289 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2290 dev ? dev->name : "<not registered>", rxtx);
2291
2292 imask = sky2_read32(hw, B0_IMSK);
2293 imask &= ~mask;
2294 sky2_write32(hw, B0_IMSK, imask);
2295
2296 if (dev) {
2297 spin_lock(&sky2->phy_lock);
2298 sky2_link_down(sky2);
2299 spin_unlock(&sky2->phy_lock);
2300 }
2301}
cd28ab6a 2302
d27ed387
SH		 2303/* If idle then force a fake soft NAPI poll once a second
2304 * to work around cases where sharing an edge triggered interrupt.
2305 */
eb35cf60
SH		 2306static inline void sky2_idle_start(struct sky2_hw *hw)
2307{
2308 if (idle_timeout > 0)
2309 mod_timer(&hw->idle_timer,
2310 jiffies + msecs_to_jiffies(idle_timeout));
2311}
2312
d27ed387
SH		 2313static void sky2_idle(unsigned long arg)
2314{
01bd7564
SH		 2315 struct sky2_hw *hw = (struct sky2_hw *) arg;
2316 struct net_device *dev = hw->dev[0];
d27ed387 2317
d27ed387
SH		 2318 if (__netif_rx_schedule_prep(dev))
2319 __netif_rx_schedule(dev);
01bd7564
SH		 2320
2321 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2322}
2323
2324
e07b1aa8 2325static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2326{
e07b1aa8
SH		 2327 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2328 int work_limit = min(dev0->quota, *budget);
2329 int work_done = 0;
fb2690a9 2330 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2331
1e5f1283
SH		 2332 if (status & Y2_IS_HW_ERR)
2333 sky2_hw_intr(hw);
d257924e 2334
1e5f1283
SH		 2335 if (status & Y2_IS_IRQ_PHY1)
2336 sky2_phy_intr(hw, 0);
cd28ab6a 2337
1e5f1283
SH		 2338 if (status & Y2_IS_IRQ_PHY2)
2339 sky2_phy_intr(hw, 1);
cd28ab6a 2340
1e5f1283
SH		 2341 if (status & Y2_IS_IRQ_MAC1)
2342 sky2_mac_intr(hw, 0);
cd28ab6a 2343
1e5f1283
SH		 2344 if (status & Y2_IS_IRQ_MAC2)
2345 sky2_mac_intr(hw, 1);
cd28ab6a 2346
1e5f1283
SH		 2347 if (status & Y2_IS_CHK_RX1)
2348 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2349
1e5f1283
SH		 2350 if (status & Y2_IS_CHK_RX2)
2351 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2352
1e5f1283
SH		 2353 if (status & Y2_IS_CHK_TXA1)
2354 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2355
1e5f1283
SH		 2356 if (status & Y2_IS_CHK_TXA2)
2357 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2358
1e5f1283 2359 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2360 if (work_done < work_limit) {
2361 netif_rx_complete(dev0);
86fba634 2362
fe2a24df
SH		 2363 sky2_read32(hw, B0_Y2_SP_LISR);
2364 return 0;
2365 } else {
2366 *budget -= work_done;
2367 dev0->quota -= work_done;
1e5f1283 2368 return 1;
fe2a24df 2369 }
e07b1aa8
SH		 2370}
2371
7d12e780 2372static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2373{
2374 struct sky2_hw *hw = dev_id;
2375 struct net_device *dev0 = hw->dev[0];
2376 u32 status;
2377
2378 /* Reading this mask interrupts as side effect */
2379 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2380 if (status == 0 || status == ~0)
2381 return IRQ_NONE;
793b883e 2382
e07b1aa8
SH		 2383 prefetch(&hw->st_le[hw->st_idx]);
2384 if (likely(__netif_rx_schedule_prep(dev0)))
2385 __netif_rx_schedule(dev0);
793b883e 2386
cd28ab6a
SH		 2387 return IRQ_HANDLED;
2388}
2389
2390#ifdef CONFIG_NET_POLL_CONTROLLER
2391static void sky2_netpoll(struct net_device *dev)
2392{
2393 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2394 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2395
88d11360
SH		 2396 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2397 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2398}
2399#endif
2400
2401/* Chip internal frequency for clock calculations */
fb17358f 2402static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2403{
793b883e 2404 switch (hw->chip_id) {
cd28ab6a 2405 case CHIP_ID_YUKON_EC:
5a5b1ea0 2406 case CHIP_ID_YUKON_EC_U:
fb17358f 2407 return 125; /* 125 Mhz */
cd28ab6a 2408 case CHIP_ID_YUKON_FE:
fb17358f 2409 return 100; /* 100 Mhz */
793b883e 2410 default: /* YUKON_XL */
fb17358f 2411 return 156; /* 156 Mhz */
cd28ab6a
SH		 2412 }
2413}
2414
fb17358f 2415static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2416{
fb17358f 2417 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2418}
2419
fb17358f 2420static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2421{
fb17358f 2422 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2423}
2424
fb17358f 2425
59139528 2426static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2427{
cd28ab6a 2428 u16 status;
b89165f2 2429 u8 t8;
56a645cc 2430 int i;
cd28ab6a 2431
cd28ab6a 2432 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2433
cd28ab6a
SH		 2434 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2435 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2436 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2437 pci_name(hw->pdev), hw->chip_id);
2438 return -EOPNOTSUPP;
2439 }
2440
290d4de5
SH		 2441 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2442
2443 /* This rev is really old, and requires untested workarounds */
2444 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2445 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2446 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2447 hw->chip_id, hw->chip_rev);
2448 return -EOPNOTSUPP;
2449 }
2450
cd28ab6a
SH		 2451 /* disable ASF */
2452 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2453 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2454 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2455 }
2456
2457 /* do a SW reset */
2458 sky2_write8(hw, B0_CTST, CS_RST_SET);
2459 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2460
2461 /* clear PCI errors, if any */
56a645cc 2462 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2463
cd28ab6a 2464 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2465 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2466
cd28ab6a
SH		 2467
2468 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2469
2470 /* clear any PEX errors */
7bd656d1
SH		 2471 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2472 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2473
cd28ab6a 2474
b89165f2 2475 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
cd28ab6a
SH		 2476 hw->ports = 1;
2477 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2478 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2479 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2480 ++hw->ports;
2481 }
cd28ab6a 2482
5afa0a9c 2483 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2484
2485 for (i = 0; i < hw->ports; i++) {
2486 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2487 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2488 }
2489
2490 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2491
793b883e
SH		 2492 /* Clear I2C IRQ noise */
2493 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2494
2495 /* turn off hardware timer (unused) */
2496 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2497 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2498
cd28ab6a
SH		 2499 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2500
69634ee7
SH		 2501 /* Turn off descriptor polling */
2502 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2503
2504 /* Turn off receive timestamp */
2505 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2506 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2507
2508 /* enable the Tx Arbiters */
2509 for (i = 0; i < hw->ports; i++)
2510 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2511
2512 /* Initialize ram interface */
2513 for (i = 0; i < hw->ports; i++) {
793b883e 2514 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2515
2516 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2517 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2518 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2519 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2520 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2521 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2522 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2523 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2524 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2525 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2526 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2527 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2528 }
2529
7bd656d1 2530 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2531
cd28ab6a 2532 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2533 sky2_gmac_reset(hw, i);
cd28ab6a 2534
cd28ab6a
SH		 2535 memset(hw->st_le, 0, STATUS_LE_BYTES);
2536 hw->st_idx = 0;
2537
2538 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2539 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2540
2541 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2542 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2543
2544 /* Set the list last index */
793b883e 2545 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2546
290d4de5
SH		 2547 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2548 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2549
290d4de5
SH		 2550 /* set Status-FIFO ISR watermark */
2551 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2552 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2553 else
2554 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2555
290d4de5 2556 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2557 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2558 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2559
793b883e 2560 /* enable status unit */
cd28ab6a
SH		 2561 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2562
2563 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2564 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2565 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2566
2567 return 0;
2568}
2569
28bd181a 2570static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2571{
b89165f2
SH		 2572 if (sky2_is_copper(hw)) {
2573 u32 modes = SUPPORTED_10baseT_Half
2574 | SUPPORTED_10baseT_Full
2575 | SUPPORTED_100baseT_Half
2576 | SUPPORTED_100baseT_Full
2577 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2578
2579 if (hw->chip_id != CHIP_ID_YUKON_FE)
2580 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2581 | SUPPORTED_1000baseT_Full;
2582 return modes;
cd28ab6a 2583 } else
b89165f2
SH		 2584 return SUPPORTED_1000baseT_Half
2585 | SUPPORTED_1000baseT_Full
2586 | SUPPORTED_Autoneg
2587 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2588}
2589
793b883e 2590static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2591{
2592 struct sky2_port *sky2 = netdev_priv(dev);
2593 struct sky2_hw *hw = sky2->hw;
2594
2595 ecmd->transceiver = XCVR_INTERNAL;
2596 ecmd->supported = sky2_supported_modes(hw);
2597 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2598 if (sky2_is_copper(hw)) {
cd28ab6a 2599 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2600 | SUPPORTED_10baseT_Full
2601 | SUPPORTED_100baseT_Half
2602 | SUPPORTED_100baseT_Full
2603 | SUPPORTED_1000baseT_Half
2604 | SUPPORTED_1000baseT_Full
2605 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2606 ecmd->port = PORT_TP;
b89165f2
SH		 2607 ecmd->speed = sky2->speed;
2608 } else {
2609 ecmd->speed = SPEED_1000;
cd28ab6a 2610 ecmd->port = PORT_FIBRE;
b89165f2 2611 }
cd28ab6a
SH		 2612
2613 ecmd->advertising = sky2->advertising;
2614 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2615 ecmd->duplex = sky2->duplex;
2616 return 0;
2617}
2618
2619static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2620{
2621 struct sky2_port *sky2 = netdev_priv(dev);
2622 const struct sky2_hw *hw = sky2->hw;
2623 u32 supported = sky2_supported_modes(hw);
2624
2625 if (ecmd->autoneg == AUTONEG_ENABLE) {
2626 ecmd->advertising = supported;
2627 sky2->duplex = -1;
2628 sky2->speed = -1;
2629 } else {
2630 u32 setting;
2631
793b883e 2632 switch (ecmd->speed) {
cd28ab6a
SH		 2633 case SPEED_1000:
2634 if (ecmd->duplex == DUPLEX_FULL)
2635 setting = SUPPORTED_1000baseT_Full;
2636 else if (ecmd->duplex == DUPLEX_HALF)
2637 setting = SUPPORTED_1000baseT_Half;
2638 else
2639 return -EINVAL;
2640 break;
2641 case SPEED_100:
2642 if (ecmd->duplex == DUPLEX_FULL)
2643 setting = SUPPORTED_100baseT_Full;
2644 else if (ecmd->duplex == DUPLEX_HALF)
2645 setting = SUPPORTED_100baseT_Half;
2646 else
2647 return -EINVAL;
2648 break;
2649
2650 case SPEED_10:
2651 if (ecmd->duplex == DUPLEX_FULL)
2652 setting = SUPPORTED_10baseT_Full;
2653 else if (ecmd->duplex == DUPLEX_HALF)
2654 setting = SUPPORTED_10baseT_Half;
2655 else
2656 return -EINVAL;
2657 break;
2658 default:
2659 return -EINVAL;
2660 }
2661
2662 if ((setting & supported) == 0)
2663 return -EINVAL;
2664
2665 sky2->speed = ecmd->speed;
2666 sky2->duplex = ecmd->duplex;
2667 }
2668
2669 sky2->autoneg = ecmd->autoneg;
2670 sky2->advertising = ecmd->advertising;
2671
1b537565
SH		 2672 if (netif_running(dev))
2673 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2674
2675 return 0;
2676}
2677
2678static void sky2_get_drvinfo(struct net_device *dev,
2679 struct ethtool_drvinfo *info)
2680{
2681 struct sky2_port *sky2 = netdev_priv(dev);
2682
2683 strcpy(info->driver, DRV_NAME);
2684 strcpy(info->version, DRV_VERSION);
2685 strcpy(info->fw_version, "N/A");
2686 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2687}
2688
2689static const struct sky2_stat {
793b883e
SH		 2690 char name[ETH_GSTRING_LEN];
2691 u16 offset;
cd28ab6a
SH		 2692} sky2_stats[] = {
2693 { "tx_bytes", GM_TXO_OK_HI },
2694 { "rx_bytes", GM_RXO_OK_HI },
2695 { "tx_broadcast", GM_TXF_BC_OK },
2696 { "rx_broadcast", GM_RXF_BC_OK },
2697 { "tx_multicast", GM_TXF_MC_OK },
2698 { "rx_multicast", GM_RXF_MC_OK },
2699 { "tx_unicast", GM_TXF_UC_OK },
2700 { "rx_unicast", GM_RXF_UC_OK },
2701 { "tx_mac_pause", GM_TXF_MPAUSE },
2702 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2703 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2704 { "late_collision",GM_TXF_LAT_COL },
2705 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2706 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2707 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2708
d2604540 2709 { "rx_short", GM_RXF_SHT },
cd28ab6a 2710 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2711 { "rx_64_byte_packets", GM_RXF_64B },
2712 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2713 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2714 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2715 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2716 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2717 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2718 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2719 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2720 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2721 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2722
2723 { "tx_64_byte_packets", GM_TXF_64B },
2724 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2725 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2726 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2727 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2728 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2729 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2730 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2731};
2732
cd28ab6a
SH		 2733static u32 sky2_get_rx_csum(struct net_device *dev)
2734{
2735 struct sky2_port *sky2 = netdev_priv(dev);
2736
2737 return sky2->rx_csum;
2738}
2739
2740static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2741{
2742 struct sky2_port *sky2 = netdev_priv(dev);
2743
2744 sky2->rx_csum = data;
793b883e 2745
cd28ab6a
SH		 2746 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2747 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2748
2749 return 0;
2750}
2751
2752static u32 sky2_get_msglevel(struct net_device *netdev)
2753{
2754 struct sky2_port *sky2 = netdev_priv(netdev);
2755 return sky2->msg_enable;
2756}
2757
9a7ae0a9
SH		 2758static int sky2_nway_reset(struct net_device *dev)
2759{
2760 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9
SH		 2761
2762 if (sky2->autoneg != AUTONEG_ENABLE)
2763 return -EINVAL;
2764
1b537565 2765 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2766
2767 return 0;
2768}
2769
793b883e 2770static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2771{
2772 struct sky2_hw *hw = sky2->hw;
2773 unsigned port = sky2->port;
2774 int i;
2775
2776 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2777 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2778 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2779 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2780
793b883e 2781 for (i = 2; i < count; i++)
cd28ab6a
SH		 2782 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2783}
2784
cd28ab6a
SH		 2785static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2786{
2787 struct sky2_port *sky2 = netdev_priv(netdev);
2788 sky2->msg_enable = value;
2789}
2790
2791static int sky2_get_stats_count(struct net_device *dev)
2792{
2793 return ARRAY_SIZE(sky2_stats);
2794}
2795
2796static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2797 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2798{
2799 struct sky2_port *sky2 = netdev_priv(dev);
2800
793b883e 2801 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2802}
2803
793b883e 2804static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2805{
2806 int i;
2807
2808 switch (stringset) {
2809 case ETH_SS_STATS:
2810 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2811 memcpy(data + i * ETH_GSTRING_LEN,
2812 sky2_stats[i].name, ETH_GSTRING_LEN);
2813 break;
2814 }
2815}
2816
2817/* Use hardware MIB variables for critical path statistics and
2818 * transmit feedback not reported at interrupt.
2819 * Other errors are accounted for in interrupt handler.
2820 */
2821static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2822{
2823 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2824 u64 data[13];
cd28ab6a 2825
793b883e 2826 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2827
2828 sky2->net_stats.tx_bytes = data[0];
2829 sky2->net_stats.rx_bytes = data[1];
2830 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2831 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2832 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2833 sky2->net_stats.collisions = data[10];
2834 sky2->net_stats.tx_aborted_errors = data[12];
2835
2836 return &sky2->net_stats;
2837}
2838
2839static int sky2_set_mac_address(struct net_device *dev, void *p)
2840{
2841 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2842 struct sky2_hw *hw = sky2->hw;
2843 unsigned port = sky2->port;
2844 const struct sockaddr *addr = p;
cd28ab6a
SH		 2845
2846 if (!is_valid_ether_addr(addr->sa_data))
2847 return -EADDRNOTAVAIL;
2848
cd28ab6a 2849 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2850 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2851 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2852 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2853 dev->dev_addr, ETH_ALEN);
1b537565 2854
a8ab1ec0
SH		 2855 /* virtual address for data */
2856 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2857
2858 /* physical address: used for pause frames */
2859 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2860
2861 return 0;
cd28ab6a
SH		 2862}
2863
2864static void sky2_set_multicast(struct net_device *dev)
2865{
2866 struct sky2_port *sky2 = netdev_priv(dev);
2867 struct sky2_hw *hw = sky2->hw;
2868 unsigned port = sky2->port;
2869 struct dev_mc_list *list = dev->mc_list;
2870 u16 reg;
2871 u8 filter[8];
2872
2873 memset(filter, 0, sizeof(filter));
2874
2875 reg = gma_read16(hw, port, GM_RX_CTRL);
2876 reg |= GM_RXCR_UCF_ENA;
2877
d571b694 2878 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2879 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2880 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2881 memset(filter, 0xff, sizeof(filter));
793b883e 2882 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2883 reg &= ~GM_RXCR_MCF_ENA;
2884 else {
2885 int i;
2886 reg |= GM_RXCR_MCF_ENA;
2887
2888 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2889 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2890 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2891 }
2892 }
2893
cd28ab6a 2894 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2895 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2896 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2897 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2898 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2899 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2900 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2901 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2902
2903 gma_write16(hw, port, GM_RX_CTRL, reg);
2904}
2905
2906/* Can have one global because blinking is controlled by
2907 * ethtool and that is always under RTNL mutex
2908 */
91c86df5 2909static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2910{
793b883e
SH		 2911 u16 pg;
2912
793b883e
SH		 2913 switch (hw->chip_id) {
2914 case CHIP_ID_YUKON_XL:
2915 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2916 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2917 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2918 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2919 PHY_M_LEDC_INIT_CTRL(7) |
2920 PHY_M_LEDC_STA1_CTRL(7) |
2921 PHY_M_LEDC_STA0_CTRL(7))
2922 : 0);
2923
2924 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2925 break;
2926
2927 default:
2928 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2929 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2930 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2931 PHY_M_LED_MO_10(MO_LED_ON) |
2932 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2933 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2934 PHY_M_LED_MO_RX(MO_LED_ON)
2935 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2936 PHY_M_LED_MO_10(MO_LED_OFF) |
2937 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2938 PHY_M_LED_MO_1000(MO_LED_OFF) |
2939 PHY_M_LED_MO_RX(MO_LED_OFF));
2940
793b883e 2941 }
cd28ab6a
SH		 2942}
2943
2944/* blink LED's for finding board */
2945static int sky2_phys_id(struct net_device *dev, u32 data)
2946{
2947 struct sky2_port *sky2 = netdev_priv(dev);
2948 struct sky2_hw *hw = sky2->hw;
2949 unsigned port = sky2->port;
793b883e 2950 u16 ledctrl, ledover = 0;
cd28ab6a 2951 long ms;
91c86df5 2952 int interrupted;
cd28ab6a
SH		 2953 int onoff = 1;
2954
793b883e 2955 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2956 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2957 else
2958 ms = data * 1000;
2959
2960 /* save initial values */
e07b1aa8 2961 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2962 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2963 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2964 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2965 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2966 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2967 } else {
2968 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2969 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2970 }
cd28ab6a 2971
91c86df5
SH		 2972 interrupted = 0;
2973 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2974 sky2_led(hw, port, onoff);
2975 onoff = !onoff;
2976
e07b1aa8 2977 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2978 interrupted = msleep_interruptible(250);
e07b1aa8 2979 spin_lock_bh(&sky2->phy_lock);
91c86df5 2980
cd28ab6a
SH		 2981 ms -= 250;
2982 }
2983
2984 /* resume regularly scheduled programming */
793b883e
SH		 2985 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2986 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2987 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2988 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2989 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2990 } else {
2991 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2992 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2993 }
e07b1aa8 2994 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2995
2996 return 0;
2997}
2998
2999static void sky2_get_pauseparam(struct net_device *dev,
3000 struct ethtool_pauseparam *ecmd)
3001{
3002 struct sky2_port *sky2 = netdev_priv(dev);
3003
3004 ecmd->tx_pause = sky2->tx_pause;
3005 ecmd->rx_pause = sky2->rx_pause;
3006 ecmd->autoneg = sky2->autoneg;
3007}
3008
3009static int sky2_set_pauseparam(struct net_device *dev,
3010 struct ethtool_pauseparam *ecmd)
3011{
3012 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3013
3014 sky2->autoneg = ecmd->autoneg;
3015 sky2->tx_pause = ecmd->tx_pause != 0;
3016 sky2->rx_pause = ecmd->rx_pause != 0;
3017
1b537565 3018 sky2_phy_reinit(sky2);
cd28ab6a 3019
2eaba1a2 3020 return 0;
cd28ab6a
SH		 3021}
3022
fb17358f
SH		 3023static int sky2_get_coalesce(struct net_device *dev,
3024 struct ethtool_coalesce *ecmd)
3025{
3026 struct sky2_port *sky2 = netdev_priv(dev);
3027 struct sky2_hw *hw = sky2->hw;
3028
3029 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3030 ecmd->tx_coalesce_usecs = 0;
3031 else {
3032 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3033 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3034 }
3035 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3036
3037 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3038 ecmd->rx_coalesce_usecs = 0;
3039 else {
3040 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3041 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3042 }
3043 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3044
3045 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3046 ecmd->rx_coalesce_usecs_irq = 0;
3047 else {
3048 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3049 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3050 }
3051
3052 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3053
3054 return 0;
3055}
3056
3057/* Note: this affect both ports */
3058static int sky2_set_coalesce(struct net_device *dev,
3059 struct ethtool_coalesce *ecmd)
3060{
3061 struct sky2_port *sky2 = netdev_priv(dev);
3062 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3063 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3064
77b3d6a2
SH		 3065 if (ecmd->tx_coalesce_usecs > tmax ||
3066 ecmd->rx_coalesce_usecs > tmax ||
3067 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3068 return -EINVAL;
3069
ff81fbbe 3070 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3071 return -EINVAL;
ff81fbbe 3072 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3073 return -EINVAL;
ff81fbbe 3074 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3075 return -EINVAL;
3076
3077 if (ecmd->tx_coalesce_usecs == 0)
3078 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3079 else {
3080 sky2_write32(hw, STAT_TX_TIMER_INI,
3081 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3082 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3083 }
3084 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3085
3086 if (ecmd->rx_coalesce_usecs == 0)
3087 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3088 else {
3089 sky2_write32(hw, STAT_LEV_TIMER_INI,
3090 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3091 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3092 }
3093 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3094
3095 if (ecmd->rx_coalesce_usecs_irq == 0)
3096 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3097 else {
d28d4870 3098 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3099 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3100 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3101 }
3102 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3103 return 0;
3104}
3105
793b883e
SH		 3106static void sky2_get_ringparam(struct net_device *dev,
3107 struct ethtool_ringparam *ering)
3108{
3109 struct sky2_port *sky2 = netdev_priv(dev);
3110
3111 ering->rx_max_pending = RX_MAX_PENDING;
3112 ering->rx_mini_max_pending = 0;
3113 ering->rx_jumbo_max_pending = 0;
3114 ering->tx_max_pending = TX_RING_SIZE - 1;
3115
3116 ering->rx_pending = sky2->rx_pending;
3117 ering->rx_mini_pending = 0;
3118 ering->rx_jumbo_pending = 0;
3119 ering->tx_pending = sky2->tx_pending;
3120}
3121
3122static int sky2_set_ringparam(struct net_device *dev,
3123 struct ethtool_ringparam *ering)
3124{
3125 struct sky2_port *sky2 = netdev_priv(dev);
3126 int err = 0;
3127
3128 if (ering->rx_pending > RX_MAX_PENDING ||
3129 ering->rx_pending < 8 ||
3130 ering->tx_pending < MAX_SKB_TX_LE ||
3131 ering->tx_pending > TX_RING_SIZE - 1)
3132 return -EINVAL;
3133
3134 if (netif_running(dev))
3135 sky2_down(dev);
3136
3137 sky2->rx_pending = ering->rx_pending;
3138 sky2->tx_pending = ering->tx_pending;
3139
1b537565 3140 if (netif_running(dev)) {
793b883e 3141 err = sky2_up(dev);
1b537565
SH		 3142 if (err)
3143 dev_close(dev);
6ed995bb
SH		 3144 else
3145 sky2_set_multicast(dev);
1b537565 3146 }
793b883e
SH		 3147
3148 return err;
3149}
3150
793b883e
SH		 3151static int sky2_get_regs_len(struct net_device *dev)
3152{
6e4cbb34 3153 return 0x4000;
793b883e
SH		 3154}
3155
3156/*
3157 * Returns copy of control register region
6e4cbb34 3158 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3159 */
3160static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3161 void *p)
3162{
3163 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3164 const void __iomem *io = sky2->hw->regs;
793b883e 3165
6e4cbb34 3166 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3167 regs->version = 1;
6e4cbb34 3168 memset(p, 0, regs->len);
793b883e 3169
6e4cbb34
SH		 3170 memcpy_fromio(p, io, B3_RAM_ADDR);
3171
3172 memcpy_fromio(p + B3_RI_WTO_R1,
3173 io + B3_RI_WTO_R1,
3174 regs->len - B3_RI_WTO_R1);
793b883e 3175}
cd28ab6a 3176
7282d491 3177static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3178 .get_settings = sky2_get_settings,
3179 .set_settings = sky2_set_settings,
3180 .get_drvinfo = sky2_get_drvinfo,
3181 .get_msglevel = sky2_get_msglevel,
3182 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3183 .nway_reset = sky2_nway_reset,
793b883e
SH		 3184 .get_regs_len = sky2_get_regs_len,
3185 .get_regs = sky2_get_regs,
3186 .get_link = ethtool_op_get_link,
3187 .get_sg = ethtool_op_get_sg,
3188 .set_sg = ethtool_op_set_sg,
3189 .get_tx_csum = ethtool_op_get_tx_csum,
3190 .set_tx_csum = ethtool_op_set_tx_csum,
3191 .get_tso = ethtool_op_get_tso,
3192 .set_tso = ethtool_op_set_tso,
3193 .get_rx_csum = sky2_get_rx_csum,
3194 .set_rx_csum = sky2_set_rx_csum,
3195 .get_strings = sky2_get_strings,
fb17358f
SH		 3196 .get_coalesce = sky2_get_coalesce,
3197 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3198 .get_ringparam = sky2_get_ringparam,
3199 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3200 .get_pauseparam = sky2_get_pauseparam,
3201 .set_pauseparam = sky2_set_pauseparam,
793b883e 3202 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3203 .get_stats_count = sky2_get_stats_count,
3204 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3205 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3206};
3207
3208/* Initialize network device */
3209static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3210 unsigned port, int highmem)
3211{
3212 struct sky2_port *sky2;
3213 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3214
3215 if (!dev) {
3216 printk(KERN_ERR "sky2 etherdev alloc failed");
3217 return NULL;
3218 }
3219
3220 SET_MODULE_OWNER(dev);
3221 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3222 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3223 dev->open = sky2_up;
3224 dev->stop = sky2_down;
ef743d33 3225 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3226 dev->hard_start_xmit = sky2_xmit_frame;
3227 dev->get_stats = sky2_get_stats;
3228 dev->set_multicast_list = sky2_set_multicast;
3229 dev->set_mac_address = sky2_set_mac_address;
3230 dev->change_mtu = sky2_change_mtu;
3231 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3232 dev->tx_timeout = sky2_tx_timeout;
3233 dev->watchdog_timeo = TX_WATCHDOG;
3234 if (port == 0)
3235 dev->poll = sky2_poll;
3236 dev->weight = NAPI_WEIGHT;
3237#ifdef CONFIG_NET_POLL_CONTROLLER
3238 dev->poll_controller = sky2_netpoll;
3239#endif
cd28ab6a
SH		 3240
3241 sky2 = netdev_priv(dev);
3242 sky2->netdev = dev;
3243 sky2->hw = hw;
3244 sky2->msg_enable = netif_msg_init(debug, default_msg);
3245
cd28ab6a
SH		 3246 /* Auto speed and flow control */
3247 sky2->autoneg = AUTONEG_ENABLE;
585b5601 3248 sky2->tx_pause = 1;
cd28ab6a
SH		 3249 sky2->rx_pause = 1;
3250 sky2->duplex = -1;
3251 sky2->speed = -1;
3252 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3253 sky2->rx_csum = 1;
75d070c5 3254
e07b1aa8 3255 spin_lock_init(&sky2->phy_lock);
793b883e 3256 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3257 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3258
3259 hw->dev[port] = dev;
3260
3261 sky2->port = port;
3262
5a5b1ea0
SH		 3263 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3264 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3265 if (highmem)
3266 dev->features |= NETIF_F_HIGHDMA;
793b883e 3267 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3268
d1f13708
SH		 3269#ifdef SKY2_VLAN_TAG_USED
3270 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3271 dev->vlan_rx_register = sky2_vlan_rx_register;
3272 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3273#endif
3274
cd28ab6a 3275 /* read the mac address */
793b883e 3276 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3277 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3278
3279 /* device is off until link detection */
3280 netif_carrier_off(dev);
3281 netif_stop_queue(dev);
3282
3283 return dev;
3284}
3285
28bd181a 3286static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3287{
3288 const struct sky2_port *sky2 = netdev_priv(dev);
3289
3290 if (netif_msg_probe(sky2))
3291 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3292 dev->name,
3293 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3294 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3295}
3296
fb2690a9 3297/* Handle software interrupt used during MSI test */
7d12e780 3298static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3299{
3300 struct sky2_hw *hw = dev_id;
3301 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3302
3303 if (status == 0)
3304 return IRQ_NONE;
3305
3306 if (status & Y2_IS_IRQ_SW) {
3307 hw->msi_detected = 1;
3308 wake_up(&hw->msi_wait);
3309 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3310 }
3311 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3312
3313 return IRQ_HANDLED;
3314}
3315
3316/* Test interrupt path by forcing a a software IRQ */
3317static int __devinit sky2_test_msi(struct sky2_hw *hw)
3318{
3319 struct pci_dev *pdev = hw->pdev;
3320 int err;
3321
bb507fe1
SH		 3322 init_waitqueue_head (&hw->msi_wait);
3323
fb2690a9
SH		 3324 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3325
1fb9df5d 3326 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
fb2690a9
SH		 3327 if (err) {
3328 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3329 pci_name(pdev), pdev->irq);
3330 return err;
3331 }
3332
fb2690a9 3333 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3334 sky2_read8(hw, B0_CTST);
fb2690a9
SH		 3335
3336 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3337
3338 if (!hw->msi_detected) {
3339 /* MSI test failed, go back to INTx mode */
2bffc23a
SH		 3340 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3341 "switching to INTx mode.\n",
fb2690a9
SH		 3342 pci_name(pdev));
3343
3344 err = -EOPNOTSUPP;
3345 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3346 }
3347
3348 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3349 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3350
3351 free_irq(pdev->irq, hw);
3352
3353 return err;
3354}
3355
cd28ab6a
SH		 3356static int __devinit sky2_probe(struct pci_dev *pdev,
3357 const struct pci_device_id *ent)
3358{
793b883e 3359 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3360 struct sky2_hw *hw;
5afa0a9c 3361 int err, pm_cap, using_dac = 0;
cd28ab6a 3362
793b883e
SH		 3363 err = pci_enable_device(pdev);
3364 if (err) {
cd28ab6a
SH		 3365 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3366 pci_name(pdev));
3367 goto err_out;
3368 }
3369
793b883e
SH		 3370 err = pci_request_regions(pdev, DRV_NAME);
3371 if (err) {
cd28ab6a
SH		 3372 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3373 pci_name(pdev));
793b883e 3374 goto err_out;
cd28ab6a
SH		 3375 }
3376
3377 pci_set_master(pdev);
3378
5afa0a9c
SH		 3379 /* Find power-management capability. */
3380 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3381 if (pm_cap == 0) {
3382 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3383 "aborting.\n");
3384 err = -EIO;
3385 goto err_out_free_regions;
3386 }
3387
d1f3d4dd
SH		 3388 if (sizeof(dma_addr_t) > sizeof(u32) &&
3389 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3390 using_dac = 1;
3391 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3392 if (err < 0) {
3393 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3394 "for consistent allocations\n", pci_name(pdev));
3395 goto err_out_free_regions;
3396 }
cd28ab6a 3397
d1f3d4dd 3398 } else {
cd28ab6a
SH		 3399 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3400 if (err) {
3401 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3402 pci_name(pdev));
3403 goto err_out_free_regions;
3404 }
3405 }
d1f3d4dd 3406
cd28ab6a 3407 err = -ENOMEM;
6aad85d6 3408 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3409 if (!hw) {
3410 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3411 pci_name(pdev));
3412 goto err_out_free_regions;
3413 }
3414
cd28ab6a 3415 hw->pdev = pdev;
cd28ab6a
SH		 3416
3417 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3418 if (!hw->regs) {
3419 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3420 pci_name(pdev));
3421 goto err_out_free_hw;
3422 }
5afa0a9c 3423 hw->pm_cap = pm_cap;
cd28ab6a 3424
56a645cc 3425#ifdef __BIG_ENDIAN
f65b138c
SH		 3426 /* The sk98lin vendor driver uses hardware byte swapping but
3427 * this driver uses software swapping.
3428 */
56a645cc
SH		 3429 {
3430 u32 reg;
56a645cc 3431 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3432 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3433 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3434 }
3435#endif
3436
08c06d8a
SH		 3437 /* ring for status responses */
3438 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3439 &hw->st_dma);
3440 if (!hw->st_le)
3441 goto err_out_iounmap;
3442
cd28ab6a
SH		 3443 err = sky2_reset(hw);
3444 if (err)
793b883e 3445 goto err_out_iounmap;
cd28ab6a 3446
7c7459d1
GKH		 3447 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3448 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3449 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3450 hw->chip_id, hw->chip_rev);
cd28ab6a 3451
793b883e
SH		 3452 dev = sky2_init_netdev(hw, 0, using_dac);
3453 if (!dev)
cd28ab6a
SH		 3454 goto err_out_free_pci;
3455
9fa1b1f3
SH		 3456 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3457 err = sky2_test_msi(hw);
3458 if (err == -EOPNOTSUPP)
3459 pci_disable_msi(pdev);
3460 else if (err)
3461 goto err_out_free_netdev;
3462 }
3463
793b883e
SH		 3464 err = register_netdev(dev);
3465 if (err) {
cd28ab6a
SH		 3466 printk(KERN_ERR PFX "%s: cannot register net device\n",
3467 pci_name(pdev));
3468 goto err_out_free_netdev;
3469 }
3470
9fa1b1f3
SH		 3471 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, dev->name, hw);
3472 if (err) {
3473 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3474 pci_name(pdev), pdev->irq);
3475 goto err_out_unregister;
3476 }
3477 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3478
cd28ab6a
SH		 3479 sky2_show_addr(dev);
3480
3481 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3482 if (register_netdev(dev1) == 0)
3483 sky2_show_addr(dev1);
3484 else {
3485 /* Failure to register second port need not be fatal */
793b883e
SH		 3486 printk(KERN_WARNING PFX
3487 "register of second port failed\n");
cd28ab6a
SH		 3488 hw->dev[1] = NULL;
3489 free_netdev(dev1);
3490 }
3491 }
3492
01bd7564 3493 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3494 sky2_idle_start(hw);
d27ed387 3495
793b883e
SH		 3496 pci_set_drvdata(pdev, hw);
3497
cd28ab6a
SH		 3498 return 0;
3499
793b883e 3500err_out_unregister:
fb2690a9 3501 pci_disable_msi(pdev);
793b883e 3502 unregister_netdev(dev);
cd28ab6a
SH		 3503err_out_free_netdev:
3504 free_netdev(dev);
cd28ab6a 3505err_out_free_pci:
793b883e 3506 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3507 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3508err_out_iounmap:
3509 iounmap(hw->regs);
3510err_out_free_hw:
3511 kfree(hw);
3512err_out_free_regions:
3513 pci_release_regions(pdev);
cd28ab6a 3514 pci_disable_device(pdev);
cd28ab6a
SH		 3515err_out:
3516 return err;
3517}
3518
3519static void __devexit sky2_remove(struct pci_dev *pdev)
3520{
793b883e 3521 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3522 struct net_device *dev0, *dev1;
3523
793b883e 3524 if (!hw)
cd28ab6a
SH		 3525 return;
3526
d27ed387
SH		 3527 del_timer_sync(&hw->idle_timer);
3528
3529 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3530 synchronize_irq(hw->pdev->irq);
3531
cd28ab6a 3532 dev0 = hw->dev[0];
793b883e
SH		 3533 dev1 = hw->dev[1];
3534 if (dev1)
3535 unregister_netdev(dev1);
cd28ab6a
SH		 3536 unregister_netdev(dev0);
3537
5afa0a9c 3538 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3539 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3540 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3541 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3542
3543 free_irq(pdev->irq, hw);
fb2690a9 3544 pci_disable_msi(pdev);
793b883e 3545 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3546 pci_release_regions(pdev);
3547 pci_disable_device(pdev);
793b883e 3548
cd28ab6a
SH		 3549 if (dev1)
3550 free_netdev(dev1);
3551 free_netdev(dev0);
3552 iounmap(hw->regs);
3553 kfree(hw);
5afa0a9c 3554
cd28ab6a
SH		 3555 pci_set_drvdata(pdev, NULL);
3556}
3557
3558#ifdef CONFIG_PM
3559static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3560{
793b883e 3561 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3562 int i;
2ccc99b7
SH		 3563 pci_power_t pstate = pci_choose_state(pdev, state);
3564
3565 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3566 return -EINVAL;
cd28ab6a 3567
eb35cf60 3568 del_timer_sync(&hw->idle_timer);
6a5706b9 3569 netif_poll_disable(hw->dev[0]);
eb35cf60 3570
f05267e7 3571 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3572 struct net_device *dev = hw->dev[i];
3573
6a5706b9 3574 if (netif_running(dev)) {
5afa0a9c 3575 sky2_down(dev);
cd28ab6a 3576 netif_device_detach(dev);
cd28ab6a
SH		 3577 }
3578 }
3579
8ab8fca2 3580 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3581 pci_save_state(pdev);
2ccc99b7
SH		 3582 sky2_set_power_state(hw, pstate);
3583 return 0;
cd28ab6a
SH		 3584}
3585
3586static int sky2_resume(struct pci_dev *pdev)
3587{
793b883e 3588 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3589 int i, err;
cd28ab6a 3590
cd28ab6a
SH		 3591 pci_restore_state(pdev);
3592 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3593 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3594
08c06d8a
SH		 3595 err = sky2_reset(hw);
3596 if (err)
3597 goto out;
cd28ab6a 3598
8ab8fca2
SH		 3599 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3600
f05267e7 3601 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3602 struct net_device *dev = hw->dev[i];
6a5706b9 3603 if (netif_running(dev)) {
08c06d8a 3604 netif_device_attach(dev);
88d11360 3605
08c06d8a
SH		 3606 err = sky2_up(dev);
3607 if (err) {
3608 printk(KERN_ERR PFX "%s: could not up: %d\n",
3609 dev->name, err);
3610 dev_close(dev);
eb35cf60 3611 goto out;
5afa0a9c 3612 }
cd28ab6a
SH		 3613 }
3614 }
eb35cf60 3615
6a5706b9 3616 netif_poll_enable(hw->dev[0]);
eb35cf60 3617 sky2_idle_start(hw);
08c06d8a
SH		 3618out:
3619 return err;
cd28ab6a
SH		 3620}
3621#endif
3622
3623static struct pci_driver sky2_driver = {
793b883e
SH		 3624 .name = DRV_NAME,
3625 .id_table = sky2_id_table,
3626 .probe = sky2_probe,
3627 .remove = __devexit_p(sky2_remove),
cd28ab6a 3628#ifdef CONFIG_PM
793b883e
SH		 3629 .suspend = sky2_suspend,
3630 .resume = sky2_resume,
cd28ab6a
SH		 3631#endif
3632};
3633
3634static int __init sky2_init_module(void)
3635{
50241c4c 3636 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3637}
3638
3639static void __exit sky2_cleanup_module(void)
3640{
3641 pci_unregister_driver(&sky2_driver);
3642}
3643
3644module_init(sky2_init_module);
3645module_exit(sky2_cleanup_module);
3646
3647MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3648MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3649MODULE_LICENSE("GPL");
5f4f9dc1 3650MODULE_VERSION(DRV_VERSION);
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