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[PATCH] sky2: ring distance optimization
[mirror_ubuntu-zesty-kernel.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
cd28ab6a
SH		 27 * TOTEST
28 * - speed setting
724bca3c 29 * - suspend/resume
cd28ab6a
SH		 30 */
31
32#include <linux/config.h>
793b883e 33#include <linux/crc32.h>
cd28ab6a
SH		 34#include <linux/kernel.h>
35#include <linux/version.h>
36#include <linux/module.h>
37#include <linux/netdevice.h>
d0bbccfa 38#include <linux/dma-mapping.h>
cd28ab6a
SH		 39#include <linux/etherdevice.h>
40#include <linux/ethtool.h>
41#include <linux/pci.h>
42#include <linux/ip.h>
43#include <linux/tcp.h>
44#include <linux/in.h>
45#include <linux/delay.h>
91c86df5 46#include <linux/workqueue.h>
d1f13708 47#include <linux/if_vlan.h>
ef743d33 48#include <linux/mii.h>
cd28ab6a
SH		 49
50#include <asm/irq.h>
51
d1f13708
SH		 52#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
53#define SKY2_VLAN_TAG_USED 1
54#endif
55
cd28ab6a
SH		 56#include "sky2.h"
57
58#define DRV_NAME "sky2"
5f4f9dc1 59#define DRV_VERSION "0.9"
cd28ab6a
SH		 60#define PFX DRV_NAME " "
61
62/*
63 * The Yukon II chipset takes 64 bit command blocks (called list elements)
64 * that are organized into three (receive, transmit, status) different rings
65 * similar to Tigon3. A transmit can require several elements;
66 * a receive requires one (or two if using 64 bit dma).
67 */
68
cd28ab6a 69#define is_ec_a1(hw) \
21437643
SH		 70 unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
71 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
cd28ab6a 72
13210ce5 73#define RX_LE_SIZE 512
cd28ab6a 74#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
bea86103 75#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
13210ce5 76#define RX_DEF_PENDING RX_MAX_PENDING
793b883e
SH		 77
78#define TX_RING_SIZE 512
79#define TX_DEF_PENDING (TX_RING_SIZE - 1)
80#define TX_MIN_PENDING 64
81#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
cd28ab6a 82
793b883e 83#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a
SH		 84#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
85#define ETH_JUMBO_MTU 9000
86#define TX_WATCHDOG (5 * HZ)
87#define NAPI_WEIGHT 64
88#define PHY_RETRIES 1000
89
90static const u32 default_msg =
793b883e
SH		 91 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
92 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
93 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
cd28ab6a 94
793b883e 95static int debug = -1; /* defaults above */
cd28ab6a
SH		 96module_param(debug, int, 0);
97MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
98
bdb5c58e
SH		 99static int copybreak __read_mostly = 256;
100module_param(copybreak, int, 0);
101MODULE_PARM_DESC(copybreak, "Receive copy threshold");
102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
793b883e 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a
SH		 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
cd28ab6a
SH		 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
cd28ab6a
SH		 123 { 0 }
124};
793b883e 125
cd28ab6a
SH		 126MODULE_DEVICE_TABLE(pci, sky2_id_table);
127
128/* Avoid conditionals by using array */
129static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
131
92f965e8
SH		 132/* This driver supports yukon2 chipset only */
133static const char *yukon2_name[] = {
134 "XL", /* 0xb3 */
135 "EC Ultra", /* 0xb4 */
136 "UNKNOWN", /* 0xb5 */
137 "EC", /* 0xb6 */
138 "FE", /* 0xb7 */
793b883e
SH		 139};
140
793b883e 141/* Access to external PHY */
ef743d33 142static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 143{
144 int i;
145
146 gma_write16(hw, port, GM_SMI_DATA, val);
147 gma_write16(hw, port, GM_SMI_CTRL,
148 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
149
150 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 151 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 152 return 0;
793b883e 153 udelay(1);
cd28ab6a 154 }
ef743d33 155
793b883e 156 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 157 return -ETIMEDOUT;
cd28ab6a
SH		 158}
159
ef743d33 160static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 161{
162 int i;
163
793b883e 164 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 165 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
166
167 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 168 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
169 *val = gma_read16(hw, port, GM_SMI_DATA);
170 return 0;
171 }
172
793b883e 173 udelay(1);
cd28ab6a
SH		 174 }
175
ef743d33
SH		 176 return -ETIMEDOUT;
177}
178
179static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
180{
181 u16 v;
182
183 if (__gm_phy_read(hw, port, reg, &v) != 0)
184 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
185 return v;
cd28ab6a
SH		 186}
187
5afa0a9c
SH		 188static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
189{
190 u16 power_control;
191 u32 reg1;
192 int vaux;
193 int ret = 0;
194
195 pr_debug("sky2_set_power_state %d\n", state);
196 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
197
198 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
199 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
200 (power_control & PCI_PM_CAP_PME_D3cold);
201
202 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
203
204 power_control |= PCI_PM_CTRL_PME_STATUS;
205 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
206
207 switch (state) {
208 case PCI_D0:
209 /* switch power to VCC (WA for VAUX problem) */
210 sky2_write8(hw, B0_POWER_CTRL,
211 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
212
213 /* disable Core Clock Division, */
214 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
215
216 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
217 /* enable bits are inverted */
218 sky2_write8(hw, B2_Y2_CLK_GATE,
219 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
220 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
221 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
222 else
223 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
224
225 /* Turn off phy power saving */
226 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
227 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
228
d571b694 229 /* looks like this XL is back asswards .. */
5afa0a9c
SH		 230 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
231 reg1 |= PCI_Y2_PHY1_COMA;
232 if (hw->ports > 1)
233 reg1 |= PCI_Y2_PHY2_COMA;
234 }
235 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
236 break;
237
238 case PCI_D3hot:
239 case PCI_D3cold:
240 /* Turn on phy power saving */
241 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
242 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
243 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
244 else
245 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
246 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
247
248 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
249 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
250 else
251 /* enable bits are inverted */
252 sky2_write8(hw, B2_Y2_CLK_GATE,
253 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
254 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
255 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
256
257 /* switch power to VAUX */
258 if (vaux && state != PCI_D3cold)
259 sky2_write8(hw, B0_POWER_CTRL,
260 (PC_VAUX_ENA | PC_VCC_ENA |
261 PC_VAUX_ON | PC_VCC_OFF));
262 break;
263 default:
264 printk(KERN_ERR PFX "Unknown power state %d\n", state);
265 ret = -1;
266 }
267
268 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
269 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
270 return ret;
271}
272
cd28ab6a
SH		 273static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
274{
275 u16 reg;
276
277 /* disable all GMAC IRQ's */
278 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
279 /* disable PHY IRQs */
280 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 281
cd28ab6a
SH		 282 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
283 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
284 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
285 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
286
287 reg = gma_read16(hw, port, GM_RX_CTRL);
288 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
289 gma_write16(hw, port, GM_RX_CTRL, reg);
290}
291
292static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
293{
294 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
793b883e 295 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
cd28ab6a 296
793b883e 297 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
cd28ab6a
SH		 298 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
299
300 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 301 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 302 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
303
304 if (hw->chip_id == CHIP_ID_YUKON_EC)
305 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
306 else
307 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
308
309 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
310 }
311
312 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
313 if (hw->copper) {
314 if (hw->chip_id == CHIP_ID_YUKON_FE) {
315 /* enable automatic crossover */
316 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
317 } else {
318 /* disable energy detect */
319 ctrl &= ~PHY_M_PC_EN_DET_MSK;
320
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
323
324 if (sky2->autoneg == AUTONEG_ENABLE &&
325 hw->chip_id == CHIP_ID_YUKON_XL) {
326 ctrl &= ~PHY_M_PC_DSC_MSK;
327 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
328 }
329 }
330 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
331 } else {
332 /* workaround for deviation #4.88 (CRC errors) */
333 /* disable Automatic Crossover */
334
335 ctrl &= ~PHY_M_PC_MDIX_MSK;
336 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
337
338 if (hw->chip_id == CHIP_ID_YUKON_XL) {
339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
341 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
342 ctrl &= ~PHY_M_MAC_MD_MSK;
343 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
344 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
345
346 /* select page 1 to access Fiber registers */
347 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
348 }
cd28ab6a
SH		 349 }
350
351 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
352 if (sky2->autoneg == AUTONEG_DISABLE)
353 ctrl &= ~PHY_CT_ANE;
354 else
355 ctrl |= PHY_CT_ANE;
356
357 ctrl |= PHY_CT_RESET;
358 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
359
360 ctrl = 0;
361 ct1000 = 0;
362 adv = PHY_AN_CSMA;
363
364 if (sky2->autoneg == AUTONEG_ENABLE) {
365 if (hw->copper) {
366 if (sky2->advertising & ADVERTISED_1000baseT_Full)
367 ct1000 |= PHY_M_1000C_AFD;
368 if (sky2->advertising & ADVERTISED_1000baseT_Half)
369 ct1000 |= PHY_M_1000C_AHD;
370 if (sky2->advertising & ADVERTISED_100baseT_Full)
371 adv |= PHY_M_AN_100_FD;
372 if (sky2->advertising & ADVERTISED_100baseT_Half)
373 adv |= PHY_M_AN_100_HD;
374 if (sky2->advertising & ADVERTISED_10baseT_Full)
375 adv |= PHY_M_AN_10_FD;
376 if (sky2->advertising & ADVERTISED_10baseT_Half)
377 adv |= PHY_M_AN_10_HD;
793b883e 378 } else /* special defines for FIBER (88E1011S only) */
cd28ab6a
SH		 379 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
380
381 /* Set Flow-control capabilities */
382 if (sky2->tx_pause && sky2->rx_pause)
793b883e 383 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
cd28ab6a 384 else if (sky2->rx_pause && !sky2->tx_pause)
793b883e 385 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
cd28ab6a
SH		 386 else if (!sky2->rx_pause && sky2->tx_pause)
387 adv |= PHY_AN_PAUSE_ASYM; /* local */
388
389 /* Restart Auto-negotiation */
390 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
391 } else {
392 /* forced speed/duplex settings */
393 ct1000 = PHY_M_1000C_MSE;
394
395 if (sky2->duplex == DUPLEX_FULL)
396 ctrl |= PHY_CT_DUP_MD;
397
398 switch (sky2->speed) {
399 case SPEED_1000:
400 ctrl |= PHY_CT_SP1000;
401 break;
402 case SPEED_100:
403 ctrl |= PHY_CT_SP100;
404 break;
405 }
406
407 ctrl |= PHY_CT_RESET;
408 }
409
410 if (hw->chip_id != CHIP_ID_YUKON_FE)
411 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
412
413 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
414 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
415
416 /* Setup Phy LED's */
417 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
418 ledover = 0;
419
420 switch (hw->chip_id) {
421 case CHIP_ID_YUKON_FE:
422 /* on 88E3082 these bits are at 11..9 (shifted left) */
423 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
424
425 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
426
427 /* delete ACT LED control bits */
428 ctrl &= ~PHY_M_FELP_LED1_MSK;
429 /* change ACT LED control to blink mode */
430 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
431 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
432 break;
433
434 case CHIP_ID_YUKON_XL:
793b883e 435 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 436
437 /* select page 3 to access LED control register */
438 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
439
440 /* set LED Function Control register */
793b883e
SH		 441 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
442 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
443 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
444 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 445
446 /* set Polarity Control register */
447 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 448 (PHY_M_POLC_LS1_P_MIX(4) |
449 PHY_M_POLC_IS0_P_MIX(4) |
450 PHY_M_POLC_LOS_CTRL(2) |
451 PHY_M_POLC_INIT_CTRL(2) |
452 PHY_M_POLC_STA1_CTRL(2) |
453 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 454
455 /* restore page register */
793b883e 456 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 457 break;
458
459 default:
460 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
461 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
462 /* turn off the Rx LED (LED_RX) */
463 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
464 }
465
466 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
467
468 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
469 /* turn on 100 Mbps LED (LED_LINK100) */
470 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
471 }
472
473 if (ledover)
474 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
475
d571b694 476 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 477 if (sky2->autoneg == AUTONEG_ENABLE)
478 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
479 else
480 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
481}
482
483static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
484{
485 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
486 u16 reg;
487 int i;
488 const u8 *addr = hw->dev[port]->dev_addr;
489
42eeea01
SH		 490 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
491 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 492
493 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
494
793b883e 495 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 496 /* WA DEV_472 -- looks like crossed wires on port 2 */
497 /* clear GMAC 1 Control reset */
498 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
499 do {
500 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
501 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
502 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
503 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
504 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
505 }
506
cd28ab6a
SH		 507 if (sky2->autoneg == AUTONEG_DISABLE) {
508 reg = gma_read16(hw, port, GM_GP_CTRL);
509 reg |= GM_GPCR_AU_ALL_DIS;
510 gma_write16(hw, port, GM_GP_CTRL, reg);
511 gma_read16(hw, port, GM_GP_CTRL);
512
cd28ab6a
SH		 513 switch (sky2->speed) {
514 case SPEED_1000:
515 reg |= GM_GPCR_SPEED_1000;
516 /* fallthru */
517 case SPEED_100:
518 reg |= GM_GPCR_SPEED_100;
519 }
520
521 if (sky2->duplex == DUPLEX_FULL)
522 reg |= GM_GPCR_DUP_FULL;
523 } else
524 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
525
526 if (!sky2->tx_pause && !sky2->rx_pause) {
527 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
793b883e
SH		 528 reg |=
529 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
530 } else if (sky2->tx_pause && !sky2->rx_pause) {
cd28ab6a
SH		 531 /* disable Rx flow-control */
532 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
533 }
534
535 gma_write16(hw, port, GM_GP_CTRL, reg);
536
793b883e 537 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 538
91c86df5 539 down(&sky2->phy_sema);
cd28ab6a 540 sky2_phy_init(hw, port);
91c86df5 541 up(&sky2->phy_sema);
cd28ab6a
SH		 542
543 /* MIB clear */
544 reg = gma_read16(hw, port, GM_PHY_ADDR);
545 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
546
547 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
793b883e 548 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
cd28ab6a
SH		 549 gma_write16(hw, port, GM_PHY_ADDR, reg);
550
551 /* transmit control */
552 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
553
554 /* receive control reg: unicast + multicast + no FCS */
555 gma_write16(hw, port, GM_RX_CTRL,
793b883e 556 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 557
558 /* transmit flow control */
559 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
560
561 /* transmit parameter */
562 gma_write16(hw, port, GM_TX_PARAM,
563 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
564 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
565 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
566 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
567
568 /* serial mode register */
569 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 570 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 571
6b1a3aef 572 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 573 reg |= GM_SMOD_JUMBO_ENA;
574
575 gma_write16(hw, port, GM_SERIAL_MODE, reg);
576
cd28ab6a
SH		 577 /* virtual address for data */
578 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
579
793b883e
SH		 580 /* physical address: used for pause frames */
581 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
582
583 /* ignore counter overflows */
cd28ab6a
SH		 584 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
585 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
586 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
587
588 /* Configure Rx MAC FIFO */
589 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
793b883e 590 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
d1f13708 591 GMF_RX_CTRL_DEF);
cd28ab6a 592
d571b694 593 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 594 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 595
793b883e
SH		 596 /* Set threshold to 0xa (64 bytes)
597 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 598 */
599 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
600
601 /* Configure Tx MAC FIFO */
602 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
603 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 604
605 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
606 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
607 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
608 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
609 /* set Tx GMAC FIFO Almost Empty Threshold */
610 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
611 /* Disable Store & Forward mode for TX */
612 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
613 }
614 }
615
cd28ab6a
SH		 616}
617
618static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
619{
620 u32 end;
621
622 start /= 8;
623 len /= 8;
624 end = start + len - 1;
793b883e 625
cd28ab6a
SH		 626 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
627 sky2_write32(hw, RB_ADDR(q, RB_START), start);
628 sky2_write32(hw, RB_ADDR(q, RB_END), end);
629 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
630 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
631
632 if (q == Q_R1 || q == Q_R2) {
793b883e
SH		 633 u32 rxup, rxlo;
634
635 rxlo = len/2;
636 rxup = rxlo + len/4;
793b883e 637
cd28ab6a 638 /* Set thresholds on receive queue's */
793b883e
SH		 639 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
640 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
cd28ab6a
SH		 641 } else {
642 /* Enable store & forward on Tx queue's because
643 * Tx FIFO is only 1K on Yukon
644 */
645 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
646 }
647
648 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 649 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 650}
651
cd28ab6a 652/* Setup Bus Memory Interface */
af4ed7e6 653static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 654{
655 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
656 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
657 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 658 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 659}
660
cd28ab6a
SH		 661/* Setup prefetch unit registers. This is the interface between
662 * hardware and driver list elements
663 */
664static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
665 u64 addr, u32 last)
666{
cd28ab6a
SH		 667 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
668 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
669 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
670 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
671 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
672 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 673
674 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 675}
676
793b883e
SH		 677static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
678{
679 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
680
681 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
682 return le;
683}
cd28ab6a
SH		 684
685/*
d571b694 686 * This is a workaround code taken from SysKonnect sk98lin driver
793b883e 687 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
cd28ab6a
SH		 688 */
689static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
690 u16 idx, u16 *last, u16 size)
cd28ab6a 691{
cd28ab6a
SH		 692 if (is_ec_a1(hw) && idx < *last) {
693 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
694
695 if (hwget == 0) {
696 /* Start prefetching again */
793b883e 697 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
cd28ab6a
SH		 698 goto setnew;
699 }
700
793b883e 701 if (hwget == size - 1) {
cd28ab6a
SH		 702 /* set watermark to one list element */
703 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
704
705 /* set put index to first list element */
706 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
793b883e
SH		 707 } else /* have hardware go to end of list */
708 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
709 size - 1);
cd28ab6a 710 } else {
793b883e 711setnew:
cd28ab6a 712 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
cd28ab6a 713 }
bea86103 714 *last = idx;
cd28ab6a
SH		 715}
716
793b883e 717
cd28ab6a
SH		 718static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
719{
720 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
721 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
722 return le;
723}
724
a018e330
SH		 725/* Return high part of DMA address (could be 32 or 64 bit) */
726static inline u32 high32(dma_addr_t a)
727{
728 return (a >> 16) >> 16;
729}
730
793b883e
SH		 731/* Build description to hardware about buffer */
732static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
cd28ab6a
SH		 733{
734 struct sky2_rx_le *le;
a018e330 735 u32 hi = high32(re->mapaddr);
cd28ab6a 736
793b883e
SH		 737 re->idx = sky2->rx_put;
738 if (sky2->rx_addr64 != hi) {
cd28ab6a 739 le = sky2_next_rx(sky2);
793b883e 740 le->addr = cpu_to_le32(hi);
cd28ab6a
SH		 741 le->ctrl = 0;
742 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 743 sky2->rx_addr64 = high32(re->mapaddr + re->maplen);
cd28ab6a 744 }
793b883e 745
cd28ab6a 746 le = sky2_next_rx(sky2);
793b883e
SH		 747 le->addr = cpu_to_le32((u32) re->mapaddr);
748 le->length = cpu_to_le16(re->maplen);
cd28ab6a
SH		 749 le->ctrl = 0;
750 le->opcode = OP_PACKET | HW_OWNER;
751}
752
793b883e 753
cd28ab6a
SH		 754/* Tell chip where to start receive checksum.
755 * Actually has two checksums, but set both same to avoid possible byte
756 * order problems.
757 */
793b883e 758static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 759{
760 struct sky2_rx_le *le;
761
cd28ab6a 762 le = sky2_next_rx(sky2);
793b883e 763 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
cd28ab6a
SH		 764 le->ctrl = 0;
765 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 766
793b883e
SH		 767 sky2_write32(sky2->hw,
768 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
769 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 770
771}
772
6b1a3aef
SH		 773/*
774 * The RX Stop command will not work for Yukon-2 if the BMU does not
775 * reach the end of packet and since we can't make sure that we have
776 * incoming data, we must reset the BMU while it is not doing a DMA
777 * transfer. Since it is possible that the RX path is still active,
778 * the RX RAM buffer will be stopped first, so any possible incoming
779 * data will not trigger a DMA. After the RAM buffer is stopped, the
780 * BMU is polled until any DMA in progress is ended and only then it
781 * will be reset.
782 */
783static void sky2_rx_stop(struct sky2_port *sky2)
784{
785 struct sky2_hw *hw = sky2->hw;
786 unsigned rxq = rxqaddr[sky2->port];
787 int i;
788
789 /* disable the RAM Buffer receive queue */
790 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
791
792 for (i = 0; i < 0xffff; i++)
793 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
794 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
795 goto stopped;
796
797 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
798 sky2->netdev->name);
799stopped:
800 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
801
802 /* reset the Rx prefetch unit */
803 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
804}
793b883e 805
d571b694 806/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 807static void sky2_rx_clean(struct sky2_port *sky2)
808{
809 unsigned i;
810
811 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 812 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a
SH		 813 struct ring_info *re = sky2->rx_ring + i;
814
815 if (re->skb) {
793b883e
SH		 816 pci_unmap_single(sky2->hw->pdev,
817 re->mapaddr, re->maplen,
cd28ab6a
SH		 818 PCI_DMA_FROMDEVICE);
819 kfree_skb(re->skb);
820 re->skb = NULL;
821 }
822 }
823}
824
ef743d33
SH		 825/* Basic MII support */
826static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
827{
828 struct mii_ioctl_data *data = if_mii(ifr);
829 struct sky2_port *sky2 = netdev_priv(dev);
830 struct sky2_hw *hw = sky2->hw;
831 int err = -EOPNOTSUPP;
832
833 if (!netif_running(dev))
834 return -ENODEV; /* Phy still in reset */
835
836 switch(cmd) {
837 case SIOCGMIIPHY:
838 data->phy_id = PHY_ADDR_MARV;
839
840 /* fallthru */
841 case SIOCGMIIREG: {
842 u16 val = 0;
91c86df5
SH		 843
844 down(&sky2->phy_sema);
ef743d33 845 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
91c86df5
SH		 846 up(&sky2->phy_sema);
847
ef743d33
SH		 848 data->val_out = val;
849 break;
850 }
851
852 case SIOCSMIIREG:
853 if (!capable(CAP_NET_ADMIN))
854 return -EPERM;
855
91c86df5 856 down(&sky2->phy_sema);
ef743d33
SH		 857 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
858 data->val_in);
91c86df5 859 up(&sky2->phy_sema);
ef743d33
SH		 860 break;
861 }
862 return err;
863}
864
d1f13708
SH		 865#ifdef SKY2_VLAN_TAG_USED
866static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
867{
868 struct sky2_port *sky2 = netdev_priv(dev);
869 struct sky2_hw *hw = sky2->hw;
870 u16 port = sky2->port;
d1f13708 871
f2e46561 872 spin_lock(&sky2->tx_lock);
d1f13708
SH		 873
874 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
875 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
876 sky2->vlgrp = grp;
877
f2e46561 878 spin_unlock(&sky2->tx_lock);
d1f13708
SH		 879}
880
881static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
882{
883 struct sky2_port *sky2 = netdev_priv(dev);
884 struct sky2_hw *hw = sky2->hw;
885 u16 port = sky2->port;
d1f13708 886
f2e46561 887 spin_lock(&sky2->tx_lock);
d1f13708
SH		 888
889 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
890 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
891 if (sky2->vlgrp)
892 sky2->vlgrp->vlan_devices[vid] = NULL;
893
f2e46561 894 spin_unlock(&sky2->tx_lock);
d1f13708
SH		 895}
896#endif
897
79e57d32 898#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
6b1a3aef 899static inline unsigned rx_size(const struct sky2_port *sky2)
cd28ab6a 900{
79e57d32 901 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
cd28ab6a
SH		 902}
903
904/*
905 * Allocate and setup receiver buffer pool.
906 * In case of 64 bit dma, there are 2X as many list elements
907 * available as ring entries
908 * and need to reserve one list element so we don't wrap around.
79e57d32
SH		 909 *
910 * It appears the hardware has a bug in the FIFO logic that
911 * cause it to hang if the FIFO gets overrun and the receive buffer
912 * is not aligned. This means we can't use skb_reserve to align
913 * the IP header.
cd28ab6a 914 */
6b1a3aef 915static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 916{
6b1a3aef
SH		 917 struct sky2_hw *hw = sky2->hw;
918 unsigned size = rx_size(sky2);
919 unsigned rxq = rxqaddr[sky2->port];
920 int i;
cd28ab6a 921
6b1a3aef 922 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 923 sky2_qset(hw, rxq);
6b1a3aef
SH		 924 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
925
926 rx_set_checksum(sky2);
793b883e 927 for (i = 0; i < sky2->rx_pending; i++) {
cd28ab6a 928 struct ring_info *re = sky2->rx_ring + i;
cd28ab6a 929
79e57d32 930 re->skb = dev_alloc_skb(size);
cd28ab6a
SH		 931 if (!re->skb)
932 goto nomem;
933
6b1a3aef 934 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
79e57d32
SH		 935 size, PCI_DMA_FROMDEVICE);
936 re->maplen = size;
793b883e 937 sky2_rx_add(sky2, re);
cd28ab6a
SH		 938 }
939
6b1a3aef
SH		 940 /* Tell chip about available buffers */
941 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
942 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
cd28ab6a
SH		 943 return 0;
944nomem:
945 sky2_rx_clean(sky2);
946 return -ENOMEM;
947}
948
949/* Bring up network interface. */
950static int sky2_up(struct net_device *dev)
951{
952 struct sky2_port *sky2 = netdev_priv(dev);
953 struct sky2_hw *hw = sky2->hw;
954 unsigned port = sky2->port;
955 u32 ramsize, rxspace;
956 int err = -ENOMEM;
957
958 if (netif_msg_ifup(sky2))
959 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
960
961 /* must be power of 2 */
962 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 963 TX_RING_SIZE *
964 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 965 &sky2->tx_le_map);
966 if (!sky2->tx_le)
967 goto err_out;
968
b2f5ad4f 969 sky2->tx_ring = kzalloc(TX_RING_SIZE * sizeof(struct ring_info),
cd28ab6a
SH		 970 GFP_KERNEL);
971 if (!sky2->tx_ring)
972 goto err_out;
973 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 974
975 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
976 &sky2->rx_le_map);
977 if (!sky2->rx_le)
978 goto err_out;
979 memset(sky2->rx_le, 0, RX_LE_BYTES);
980
b2f5ad4f 981 sky2->rx_ring = kzalloc(sky2->rx_pending * sizeof(struct ring_info),
cd28ab6a
SH		 982 GFP_KERNEL);
983 if (!sky2->rx_ring)
984 goto err_out;
985
986 sky2_mac_init(hw, port);
987
988 /* Configure RAM buffers */
989 if (hw->chip_id == CHIP_ID_YUKON_FE ||
990 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
991 ramsize = 4096;
992 else {
793b883e
SH		 993 u8 e0 = sky2_read8(hw, B2_E_0);
994 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
cd28ab6a
SH		 995 }
996
997 /* 2/3 for Rx */
998 rxspace = (2 * ramsize) / 3;
999 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1000 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1001
793b883e
SH		 1002 /* Make sure SyncQ is disabled */
1003 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1004 RB_RST_SET);
1005
af4ed7e6 1006 sky2_qset(hw, txqaddr[port]);
5a5b1ea0
SH		 1007 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
1008 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1009
1010
6b1a3aef
SH		 1011 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1012 TX_RING_SIZE - 1);
cd28ab6a 1013
6b1a3aef 1014 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1015 if (err)
1016 goto err_out;
1017
cd28ab6a
SH		 1018 /* Enable interrupts from phy/mac for port */
1019 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
1020 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1021 return 0;
1022
1023err_out:
1024 if (sky2->rx_le)
1025 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1026 sky2->rx_le, sky2->rx_le_map);
1027 if (sky2->tx_le)
1028 pci_free_consistent(hw->pdev,
1029 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1030 sky2->tx_le, sky2->tx_le_map);
1031 if (sky2->tx_ring)
1032 kfree(sky2->tx_ring);
1033 if (sky2->rx_ring)
1034 kfree(sky2->rx_ring);
1035
1036 return err;
1037}
1038
793b883e
SH		 1039/* Modular subtraction in ring */
1040static inline int tx_dist(unsigned tail, unsigned head)
1041{
129372d0 1042 return (head - tail) % TX_RING_SIZE;
793b883e 1043}
cd28ab6a 1044
793b883e
SH		 1045/* Number of list elements available for next tx */
1046static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1047{
793b883e 1048 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1049}
1050
793b883e
SH		 1051/* Estimate of number of transmit list elements required */
1052static inline unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1053{
793b883e
SH		 1054 unsigned count;
1055
1056 count = sizeof(dma_addr_t) / sizeof(u32);
1057 count += skb_shinfo(skb)->nr_frags * count;
1058
1059 if (skb_shinfo(skb)->tso_size)
1060 ++count;
1061
1062 if (skb->ip_summed)
1063 ++count;
1064
1065 return count;
cd28ab6a
SH		 1066}
1067
793b883e
SH		 1068/*
1069 * Put one packet in ring for transmit.
1070 * A single packet can generate multiple list elements, and
1071 * the number of ring elements will probably be less than the number
1072 * of list elements used.
f2e46561
SH		 1073 *
1074 * No BH disabling for tx_lock here (like tg3)
793b883e 1075 */
cd28ab6a
SH		 1076static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1077{
1078 struct sky2_port *sky2 = netdev_priv(dev);
1079 struct sky2_hw *hw = sky2->hw;
d1f13708 1080 struct sky2_tx_le *le = NULL;
cd28ab6a
SH		 1081 struct ring_info *re;
1082 unsigned i, len;
1083 dma_addr_t mapping;
1084 u32 addr64;
1085 u16 mss;
1086 u8 ctrl;
1087
f2e46561 1088 if (!spin_trylock(&sky2->tx_lock))
cd28ab6a
SH		 1089 return NETDEV_TX_LOCKED;
1090
793b883e 1091 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
cd28ab6a 1092 netif_stop_queue(dev);
f2e46561 1093 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1094
1095 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1096 dev->name);
1097 return NETDEV_TX_BUSY;
1098 }
1099
793b883e 1100 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1101 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1102 dev->name, sky2->tx_prod, skb->len);
1103
cd28ab6a
SH		 1104 len = skb_headlen(skb);
1105 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1106 addr64 = high32(mapping);
793b883e
SH		 1107
1108 re = sky2->tx_ring + sky2->tx_prod;
1109
a018e330
SH		 1110 /* Send high bits if changed or crosses boundary */
1111 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e
SH		 1112 le = get_tx_le(sky2);
1113 le->tx.addr = cpu_to_le32(addr64);
1114 le->ctrl = 0;
1115 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1116 sky2->tx_addr64 = high32(mapping + len);
793b883e 1117 }
cd28ab6a
SH		 1118
1119 /* Check for TCP Segmentation Offload */
1120 mss = skb_shinfo(skb)->tso_size;
793b883e 1121 if (mss != 0) {
cd28ab6a
SH		 1122 /* just drop the packet if non-linear expansion fails */
1123 if (skb_header_cloned(skb) &&
1124 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
793b883e
SH		 1125 dev_kfree_skb_any(skb);
1126 goto out_unlock;
cd28ab6a
SH		 1127 }
1128
1129 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1130 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1131 mss += ETH_HLEN;
793b883e 1132 }
cd28ab6a 1133
793b883e 1134 if (mss != sky2->tx_last_mss) {
cd28ab6a
SH		 1135 le = get_tx_le(sky2);
1136 le->tx.tso.size = cpu_to_le16(mss);
793b883e 1137 le->tx.tso.rsvd = 0;
cd28ab6a 1138 le->opcode = OP_LRGLEN | HW_OWNER;
cd28ab6a 1139 le->ctrl = 0;
793b883e 1140 sky2->tx_last_mss = mss;
cd28ab6a
SH		 1141 }
1142
cd28ab6a 1143 ctrl = 0;
d1f13708
SH		 1144#ifdef SKY2_VLAN_TAG_USED
1145 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1146 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1147 if (!le) {
1148 le = get_tx_le(sky2);
1149 le->tx.addr = 0;
1150 le->opcode = OP_VLAN|HW_OWNER;
1151 le->ctrl = 0;
1152 } else
1153 le->opcode |= OP_VLAN;
1154 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1155 ctrl |= INS_VLAN;
1156 }
1157#endif
1158
1159 /* Handle TCP checksum offload */
cd28ab6a 1160 if (skb->ip_summed == CHECKSUM_HW) {
793b883e
SH		 1161 u16 hdr = skb->h.raw - skb->data;
1162 u16 offset = hdr + skb->csum;
cd28ab6a
SH		 1163
1164 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1165 if (skb->nh.iph->protocol == IPPROTO_UDP)
1166 ctrl |= UDPTCP;
1167
1168 le = get_tx_le(sky2);
1169 le->tx.csum.start = cpu_to_le16(hdr);
793b883e
SH		 1170 le->tx.csum.offset = cpu_to_le16(offset);
1171 le->length = 0; /* initial checksum value */
cd28ab6a 1172 le->ctrl = 1; /* one packet */
793b883e 1173 le->opcode = OP_TCPLISW | HW_OWNER;
cd28ab6a
SH		 1174 }
1175
1176 le = get_tx_le(sky2);
1177 le->tx.addr = cpu_to_le32((u32) mapping);
1178 le->length = cpu_to_le16(len);
1179 le->ctrl = ctrl;
793b883e 1180 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1181
793b883e 1182 /* Record the transmit mapping info */
cd28ab6a 1183 re->skb = skb;
793b883e
SH		 1184 re->mapaddr = mapping;
1185 re->maplen = len;
cd28ab6a
SH		 1186
1187 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1188 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
793b883e 1189 struct ring_info *fre;
cd28ab6a
SH		 1190
1191 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1192 frag->size, PCI_DMA_TODEVICE);
793b883e
SH		 1193 addr64 = (mapping >> 16) >> 16;
1194 if (addr64 != sky2->tx_addr64) {
1195 le = get_tx_le(sky2);
1196 le->tx.addr = cpu_to_le32(addr64);
1197 le->ctrl = 0;
1198 le->opcode = OP_ADDR64 | HW_OWNER;
1199 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1200 }
1201
1202 le = get_tx_le(sky2);
1203 le->tx.addr = cpu_to_le32((u32) mapping);
1204 le->length = cpu_to_le16(frag->size);
1205 le->ctrl = ctrl;
793b883e 1206 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1207
793b883e
SH		 1208 fre = sky2->tx_ring
1209 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1210 fre->skb = NULL;
1211 fre->mapaddr = mapping;
1212 fre->maplen = frag->size;
cd28ab6a 1213 }
793b883e 1214 re->idx = sky2->tx_prod;
cd28ab6a
SH		 1215 le->ctrl |= EOP;
1216
724bca3c 1217 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
cd28ab6a
SH		 1218 &sky2->tx_last_put, TX_RING_SIZE);
1219
793b883e 1220 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
cd28ab6a 1221 netif_stop_queue(dev);
793b883e
SH		 1222
1223out_unlock:
1224 mmiowb();
f2e46561 1225 spin_unlock(&sky2->tx_lock);
cd28ab6a
SH		 1226
1227 dev->trans_start = jiffies;
1228 return NETDEV_TX_OK;
1229}
1230
cd28ab6a 1231/*
793b883e
SH		 1232 * Free ring elements from starting at tx_cons until "done"
1233 *
1234 * NB: the hardware will tell us about partial completion of multi-part
d571b694 1235 * buffers; these are deferred until completion.
cd28ab6a 1236 */
d11c13e7 1237static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1238{
d11c13e7 1239 struct net_device *dev = sky2->netdev;
793b883e 1240 unsigned i;
cd28ab6a 1241
2224795d
SH		 1242 if (done == sky2->tx_cons)
1243 return;
1244
d11c13e7 1245 if (unlikely(netif_msg_tx_done(sky2)))
d571b694 1246 printk(KERN_DEBUG "%s: tx done, up to %u\n",
d11c13e7 1247 dev->name, done);
cd28ab6a
SH		 1248
1249 spin_lock(&sky2->tx_lock);
cd28ab6a 1250
793b883e
SH		 1251 while (sky2->tx_cons != done) {
1252 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1253 struct sk_buff *skb;
cd28ab6a 1254
793b883e
SH		 1255 /* Check for partial status */
1256 if (tx_dist(sky2->tx_cons, done)
1257 < tx_dist(sky2->tx_cons, re->idx))
1258 goto out;
1259
1260 skb = re->skb;
1261 pci_unmap_single(sky2->hw->pdev,
1262 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1263
1264 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1265 struct ring_info *fre;
1266 fre =
1267 sky2->tx_ring + (sky2->tx_cons + i +
1268 1) % TX_RING_SIZE;
1269 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1270 fre->maplen, PCI_DMA_TODEVICE);
cd28ab6a
SH		 1271 }
1272
cd28ab6a 1273 dev_kfree_skb_any(skb);
cd28ab6a 1274
793b883e
SH		 1275 sky2->tx_cons = re->idx;
1276 }
1277out:
1278
1279 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
cd28ab6a
SH		 1280 netif_wake_queue(dev);
1281 spin_unlock(&sky2->tx_lock);
1282}
1283
1284/* Cleanup all untransmitted buffers, assume transmitter not running */
1285static inline void sky2_tx_clean(struct sky2_port *sky2)
1286{
d11c13e7 1287 sky2_tx_complete(sky2, sky2->tx_prod);
cd28ab6a
SH		 1288}
1289
1290/* Network shutdown */
1291static int sky2_down(struct net_device *dev)
1292{
1293 struct sky2_port *sky2 = netdev_priv(dev);
1294 struct sky2_hw *hw = sky2->hw;
1295 unsigned port = sky2->port;
1296 u16 ctrl;
cd28ab6a
SH		 1297
1298 if (netif_msg_ifdown(sky2))
1299 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1300
018d1c66 1301 /* Stop more packets from being queued */
cd28ab6a
SH		 1302 netif_stop_queue(dev);
1303
018d1c66
SH		 1304 /* Disable port IRQ */
1305 local_irq_disable();
1306 hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1307 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1308 local_irq_enable();
1309
91c86df5 1310 flush_scheduled_work();
018d1c66 1311
793b883e
SH		 1312 sky2_phy_reset(hw, port);
1313
cd28ab6a
SH		 1314 /* Stop transmitter */
1315 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1316 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1317
1318 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1319 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a
SH		 1320
1321 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1322 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1323 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1324
1325 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1326
1327 /* Workaround shared GMAC reset */
793b883e
SH		 1328 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1329 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1330 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1331
1332 /* Disable Force Sync bit and Enable Alloc bit */
1333 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1334 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1335
1336 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1337 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1338 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1339
1340 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1341 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1342 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1343
1344 /* Reset the Tx prefetch units */
1345 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1346 PREF_UNIT_RST_SET);
1347
1348 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1349
6b1a3aef 1350 sky2_rx_stop(sky2);
cd28ab6a
SH		 1351
1352 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1353 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1354
d571b694 1355 /* turn off LED's */
cd28ab6a
SH		 1356 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1357
018d1c66
SH		 1358 synchronize_irq(hw->pdev->irq);
1359
cd28ab6a
SH		 1360 sky2_tx_clean(sky2);
1361 sky2_rx_clean(sky2);
1362
1363 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1364 sky2->rx_le, sky2->rx_le_map);
1365 kfree(sky2->rx_ring);
1366
1367 pci_free_consistent(hw->pdev,
1368 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1369 sky2->tx_le, sky2->tx_le_map);
1370 kfree(sky2->tx_ring);
1371
1372 return 0;
1373}
1374
1375static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1376{
793b883e
SH		 1377 if (!hw->copper)
1378 return SPEED_1000;
1379
cd28ab6a
SH		 1380 if (hw->chip_id == CHIP_ID_YUKON_FE)
1381 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1382
1383 switch (aux & PHY_M_PS_SPEED_MSK) {
1384 case PHY_M_PS_SPEED_1000:
1385 return SPEED_1000;
1386 case PHY_M_PS_SPEED_100:
1387 return SPEED_100;
1388 default:
1389 return SPEED_10;
1390 }
1391}
1392
1393static void sky2_link_up(struct sky2_port *sky2)
1394{
1395 struct sky2_hw *hw = sky2->hw;
1396 unsigned port = sky2->port;
1397 u16 reg;
1398
1399 /* Enable Transmit FIFO Underrun */
793b883e 1400 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
cd28ab6a
SH		 1401
1402 reg = gma_read16(hw, port, GM_GP_CTRL);
1403 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1404 reg |= GM_GPCR_DUP_FULL;
1405
cd28ab6a
SH		 1406 /* enable Rx/Tx */
1407 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1408 gma_write16(hw, port, GM_GP_CTRL, reg);
1409 gma_read16(hw, port, GM_GP_CTRL);
1410
1411 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1412
1413 netif_carrier_on(sky2->netdev);
1414 netif_wake_queue(sky2->netdev);
1415
1416 /* Turn on link LED */
793b883e 1417 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1418 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1419
793b883e
SH		 1420 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1421 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1422
1423 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1424 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1425 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1426 SPEED_10 ? 7 : 0) |
1427 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1428 SPEED_100 ? 7 : 0) |
1429 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1430 SPEED_1000 ? 7 : 0));
1431 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1432 }
1433
cd28ab6a
SH		 1434 if (netif_msg_link(sky2))
1435 printk(KERN_INFO PFX
d571b694 1436 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1437 sky2->netdev->name, sky2->speed,
1438 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1439 (sky2->tx_pause && sky2->rx_pause) ? "both" :
793b883e 1440 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
cd28ab6a
SH		 1441}
1442
1443static void sky2_link_down(struct sky2_port *sky2)
1444{
1445 struct sky2_hw *hw = sky2->hw;
1446 unsigned port = sky2->port;
1447 u16 reg;
1448
1449 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1450
1451 reg = gma_read16(hw, port, GM_GP_CTRL);
1452 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1453 gma_write16(hw, port, GM_GP_CTRL, reg);
1454 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1455
1456 if (sky2->rx_pause && !sky2->tx_pause) {
1457 /* restore Asymmetric Pause bit */
1458 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1459 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1460 | PHY_M_AN_ASP);
cd28ab6a
SH		 1461 }
1462
1463 sky2_phy_reset(hw, port);
1464
1465 netif_carrier_off(sky2->netdev);
1466 netif_stop_queue(sky2->netdev);
1467
1468 /* Turn on link LED */
1469 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1470
1471 if (netif_msg_link(sky2))
1472 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1473 sky2_phy_init(hw, port);
1474}
1475
793b883e
SH		 1476static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1477{
1478 struct sky2_hw *hw = sky2->hw;
1479 unsigned port = sky2->port;
1480 u16 lpa;
1481
1482 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1483
1484 if (lpa & PHY_M_AN_RF) {
1485 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1486 return -1;
1487 }
1488
1489 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1490 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1491 printk(KERN_ERR PFX "%s: master/slave fault",
1492 sky2->netdev->name);
1493 return -1;
1494 }
1495
1496 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1497 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1498 sky2->netdev->name);
1499 return -1;
1500 }
1501
1502 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1503
1504 sky2->speed = sky2_phy_speed(hw, aux);
1505
1506 /* Pause bits are offset (9..8) */
1507 if (hw->chip_id == CHIP_ID_YUKON_XL)
1508 aux >>= 6;
1509
1510 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1511 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1512
1513 if ((sky2->tx_pause || sky2->rx_pause)
1514 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1515 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1516 else
1517 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1518
1519 return 0;
1520}
cd28ab6a
SH		 1521
1522/*
91c86df5 1523 * Interrupt from PHY are handled outside of interrupt context
cd28ab6a
SH		 1524 * because accessing phy registers requires spin wait which might
1525 * cause excess interrupt latency.
1526 */
91c86df5 1527static void sky2_phy_task(void *arg)
cd28ab6a 1528{
91c86df5 1529 struct sky2_port *sky2 = arg;
cd28ab6a 1530 struct sky2_hw *hw = sky2->hw;
cd28ab6a
SH		 1531 u16 istatus, phystat;
1532
91c86df5 1533 down(&sky2->phy_sema);
793b883e
SH		 1534 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1535 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
cd28ab6a
SH		 1536
1537 if (netif_msg_intr(sky2))
1538 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1539 sky2->netdev->name, istatus, phystat);
1540
1541 if (istatus & PHY_M_IS_AN_COMPL) {
793b883e
SH		 1542 if (sky2_autoneg_done(sky2, phystat) == 0)
1543 sky2_link_up(sky2);
1544 goto out;
1545 }
cd28ab6a 1546
793b883e
SH		 1547 if (istatus & PHY_M_IS_LSP_CHANGE)
1548 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1549
793b883e
SH		 1550 if (istatus & PHY_M_IS_DUP_CHANGE)
1551 sky2->duplex =
1552 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1553
793b883e
SH		 1554 if (istatus & PHY_M_IS_LST_CHANGE) {
1555 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1556 sky2_link_up(sky2);
793b883e
SH		 1557 else
1558 sky2_link_down(sky2);
cd28ab6a 1559 }
793b883e 1560out:
91c86df5 1561 up(&sky2->phy_sema);
cd28ab6a
SH		 1562
1563 local_irq_disable();
793b883e 1564 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
cd28ab6a
SH		 1565 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1566 local_irq_enable();
1567}
1568
1569static void sky2_tx_timeout(struct net_device *dev)
1570{
1571 struct sky2_port *sky2 = netdev_priv(dev);
1572
1573 if (netif_msg_timer(sky2))
1574 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1575
1576 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1577 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1578
1579 sky2_tx_clean(sky2);
1580}
1581
1582static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1583{
6b1a3aef
SH		 1584 struct sky2_port *sky2 = netdev_priv(dev);
1585 struct sky2_hw *hw = sky2->hw;
1586 int err;
1587 u16 ctl, mode;
cd28ab6a
SH		 1588
1589 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1590 return -EINVAL;
1591
5a5b1ea0
SH		 1592 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1593 return -EINVAL;
1594
6b1a3aef
SH		 1595 if (!netif_running(dev)) {
1596 dev->mtu = new_mtu;
1597 return 0;
1598 }
1599
6b1a3aef
SH		 1600 sky2_write32(hw, B0_IMSK, 0);
1601
018d1c66
SH		 1602 dev->trans_start = jiffies; /* prevent tx timeout */
1603 netif_stop_queue(dev);
1604 netif_poll_disable(hw->dev[0]);
1605
6b1a3aef
SH		 1606 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1607 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1608 sky2_rx_stop(sky2);
1609 sky2_rx_clean(sky2);
cd28ab6a
SH		 1610
1611 dev->mtu = new_mtu;
6b1a3aef
SH		 1612 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1613 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1614
1615 if (dev->mtu > ETH_DATA_LEN)
1616 mode |= GM_SMOD_JUMBO_ENA;
1617
1618 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1619
6b1a3aef 1620 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1621
6b1a3aef
SH		 1622 err = sky2_rx_start(sky2);
1623 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1624
018d1c66
SH		 1625 netif_poll_disable(hw->dev[0]);
1626 netif_wake_queue(dev);
6b1a3aef 1627 sky2_write32(hw, B0_IMSK, hw->intr_mask);
018d1c66 1628
cd28ab6a
SH		 1629 return err;
1630}
1631
1632/*
1633 * Receive one packet.
1634 * For small packets or errors, just reuse existing skb.
d571b694 1635 * For larger packets, get new buffer.
cd28ab6a 1636 */
d11c13e7 1637static struct sk_buff *sky2_receive(struct sky2_port *sky2,
cd28ab6a
SH		 1638 u16 length, u32 status)
1639{
cd28ab6a 1640 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1641 struct sk_buff *skb = NULL;
6b1a3aef 1642 const unsigned int bufsize = rx_size(sky2);
cd28ab6a
SH		 1643
1644 if (unlikely(netif_msg_rx_status(sky2)))
1645 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
d11c13e7 1646 sky2->netdev->name, sky2->rx_next, status, length);
cd28ab6a 1647
793b883e 1648 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
cd28ab6a 1649
42eeea01 1650 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1651 goto error;
1652
42eeea01
SH		 1653 if (!(status & GMR_FS_RX_OK))
1654 goto resubmit;
1655
bdb5c58e 1656 if (length < copybreak) {
79e57d32
SH		 1657 skb = alloc_skb(length + 2, GFP_ATOMIC);
1658 if (!skb)
793b883e
SH		 1659 goto resubmit;
1660
79e57d32 1661 skb_reserve(skb, 2);
793b883e
SH		 1662 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1663 length, PCI_DMA_FROMDEVICE);
79e57d32 1664 memcpy(skb->data, re->skb->data, length);
d11c13e7
SH		 1665 skb->ip_summed = re->skb->ip_summed;
1666 skb->csum = re->skb->csum;
793b883e
SH		 1667 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1668 length, PCI_DMA_FROMDEVICE);
793b883e 1669 } else {
79e57d32
SH		 1670 struct sk_buff *nskb;
1671
1672 nskb = dev_alloc_skb(bufsize);
793b883e
SH		 1673 if (!nskb)
1674 goto resubmit;
cd28ab6a 1675
793b883e 1676 skb = re->skb;
79e57d32 1677 re->skb = nskb;
793b883e
SH		 1678 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1679 re->maplen, PCI_DMA_FROMDEVICE);
1680 prefetch(skb->data);
cd28ab6a 1681
793b883e 1682 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
79e57d32
SH		 1683 bufsize, PCI_DMA_FROMDEVICE);
1684 re->maplen = bufsize;
793b883e 1685 }
cd28ab6a 1686
79e57d32 1687 skb_put(skb, length);
793b883e 1688resubmit:
d11c13e7 1689 re->skb->ip_summed = CHECKSUM_NONE;
793b883e 1690 sky2_rx_add(sky2, re);
79e57d32 1691
bea86103
SH		 1692 /* Tell receiver about new buffers. */
1693 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1694 &sky2->rx_last_put, RX_LE_SIZE);
1695
cd28ab6a
SH		 1696 return skb;
1697
1698error:
1699 if (netif_msg_rx_err(sky2))
1700 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1701 sky2->netdev->name, status, length);
793b883e
SH		 1702
1703 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 1704 sky2->net_stats.rx_length_errors++;
1705 if (status & GMR_FS_FRAGMENT)
1706 sky2->net_stats.rx_frame_errors++;
1707 if (status & GMR_FS_CRC_ERR)
1708 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 1709 if (status & GMR_FS_RX_FF_OV)
1710 sky2->net_stats.rx_fifo_errors++;
79e57d32 1711
793b883e 1712 goto resubmit;
cd28ab6a
SH		 1713}
1714
2224795d
SH		 1715/*
1716 * Check for transmit complete
793b883e 1717 */
2224795d 1718static inline void sky2_tx_check(struct sky2_hw *hw, int port)
cd28ab6a 1719{
2224795d
SH		 1720 struct net_device *dev = hw->dev[port];
1721
1722 if (dev && netif_running(dev)) {
1723 sky2_tx_complete(netdev_priv(dev),
1724 sky2_read16(hw, port == 0
1725 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX));
1726 }
cd28ab6a
SH		 1727}
1728
1729/*
cd28ab6a
SH		 1730 * Both ports share the same status interrupt, therefore there is only
1731 * one poll routine.
cd28ab6a 1732 */
d11c13e7 1733static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 1734{
d11c13e7
SH		 1735 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1736 unsigned int to_do = min(dev0->quota, *budget);
cd28ab6a 1737 unsigned int work_done = 0;
793b883e 1738 u16 hwidx;
cd28ab6a 1739
f89c2b46 1740 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
793b883e 1741 hwidx = sky2_read16(hw, STAT_PUT_IDX);
79e57d32 1742 BUG_ON(hwidx >= STATUS_RING_SIZE);
793b883e 1743 rmb();
bea86103 1744
13210ce5
SH		 1745 while (hwidx != hw->st_idx) {
1746 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1747 struct net_device *dev;
d11c13e7 1748 struct sky2_port *sky2;
cd28ab6a 1749 struct sk_buff *skb;
cd28ab6a
SH		 1750 u32 status;
1751 u16 length;
13210ce5 1752 u8 op;
cd28ab6a 1753
13210ce5 1754 le = hw->st_le + hw->st_idx;
bea86103 1755 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
13210ce5 1756 prefetch(hw->st_le + hw->st_idx);
bea86103
SH		 1757
1758 BUG_ON(le->link >= hw->ports || !hw->dev[le->link]);
d1f13708 1759
13210ce5
SH		 1760 BUG_ON(le->link >= 2);
1761 dev = hw->dev[le->link];
1762 if (dev == NULL || !netif_running(dev))
1763 continue;
1764
1765 sky2 = netdev_priv(dev);
cd28ab6a
SH		 1766 status = le32_to_cpu(le->status);
1767 length = le16_to_cpu(le->length);
13210ce5
SH		 1768 op = le->opcode & ~HW_OWNER;
1769 le->opcode = 0;
cd28ab6a 1770
13210ce5 1771 switch (op) {
cd28ab6a 1772 case OP_RXSTAT:
d11c13e7 1773 skb = sky2_receive(sky2, length, status);
d1f13708
SH		 1774 if (!skb)
1775 break;
13210ce5
SH		 1776
1777 skb->dev = dev;
1778 skb->protocol = eth_type_trans(skb, dev);
1779 dev->last_rx = jiffies;
1780
d1f13708
SH		 1781#ifdef SKY2_VLAN_TAG_USED
1782 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1783 vlan_hwaccel_receive_skb(skb,
1784 sky2->vlgrp,
1785 be16_to_cpu(sky2->rx_tag));
1786 } else
1787#endif
cd28ab6a 1788 netif_receive_skb(skb);
13210ce5
SH		 1789
1790 if (++work_done >= to_do)
1791 goto exit_loop;
cd28ab6a
SH		 1792 break;
1793
d1f13708
SH		 1794#ifdef SKY2_VLAN_TAG_USED
1795 case OP_RXVLAN:
1796 sky2->rx_tag = length;
1797 break;
1798
1799 case OP_RXCHKSVLAN:
1800 sky2->rx_tag = length;
1801 /* fall through */
1802#endif
cd28ab6a 1803 case OP_RXCHKS:
d11c13e7
SH		 1804 skb = sky2->rx_ring[sky2->rx_next].skb;
1805 skb->ip_summed = CHECKSUM_HW;
1806 skb->csum = le16_to_cpu(status);
cd28ab6a
SH		 1807 break;
1808
1809 case OP_TXINDEXLE:
2224795d 1810 /* pick up transmit status later */
cd28ab6a
SH		 1811 break;
1812
cd28ab6a
SH		 1813 default:
1814 if (net_ratelimit())
793b883e 1815 printk(KERN_WARNING PFX
13210ce5 1816 "unknown status opcode 0x%x\n", op);
cd28ab6a
SH		 1817 break;
1818 }
13210ce5 1819 }
cd28ab6a 1820
13210ce5 1821exit_loop:
2224795d
SH		 1822 sky2_tx_check(hw, 0);
1823 sky2_tx_check(hw, 1);
cd28ab6a 1824
793b883e
SH		 1825 mmiowb();
1826
cd28ab6a
SH		 1827 if (work_done < to_do) {
1828 /*
1829 * Another chip workaround, need to restart TX timer if status
1830 * LE was handled. WA_DEV_43_418
1831 */
1832 if (is_ec_a1(hw)) {
1833 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1834 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1835 }
1836
bea86103 1837 netif_rx_complete(dev0);
cd28ab6a
SH		 1838 hw->intr_mask |= Y2_IS_STAT_BMU;
1839 sky2_write32(hw, B0_IMSK, hw->intr_mask);
13210ce5
SH		 1840 mmiowb();
1841 return 0;
1842 } else {
1843 *budget -= work_done;
1844 dev0->quota -= work_done;
1845 return 1;
cd28ab6a 1846 }
cd28ab6a
SH		 1847}
1848
1849static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1850{
1851 struct net_device *dev = hw->dev[port];
1852
1853 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1854 dev->name, status);
1855
1856 if (status & Y2_IS_PAR_RD1) {
1857 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1858 dev->name);
1859 /* Clear IRQ */
1860 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1861 }
1862
1863 if (status & Y2_IS_PAR_WR1) {
1864 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1865 dev->name);
1866
1867 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1868 }
1869
1870 if (status & Y2_IS_PAR_MAC1) {
1871 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1872 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1873 }
1874
1875 if (status & Y2_IS_PAR_RX1) {
1876 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1877 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1878 }
1879
1880 if (status & Y2_IS_TCP_TXA1) {
1881 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1882 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1883 }
1884}
1885
1886static void sky2_hw_intr(struct sky2_hw *hw)
1887{
1888 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1889
793b883e 1890 if (status & Y2_IS_TIST_OV)
cd28ab6a 1891 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 1892
1893 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 1894 u16 pci_err;
1895
1896 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
cd28ab6a
SH		 1897 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1898 pci_name(hw->pdev), pci_err);
1899
1900 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1901 pci_write_config_word(hw->pdev, PCI_STATUS,
1902 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 1903 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1904 }
1905
1906 if (status & Y2_IS_PCI_EXP) {
d571b694 1907 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 1908 u32 pex_err;
1909
1910 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
cd28ab6a 1911
cd28ab6a
SH		 1912 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1913 pci_name(hw->pdev), pex_err);
1914
1915 /* clear the interrupt */
1916 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 1917 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1918 0xffffffffUL);
cd28ab6a
SH		 1919 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1920
1921 if (pex_err & PEX_FATAL_ERRORS) {
1922 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1923 hwmsk &= ~Y2_IS_PCI_EXP;
1924 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1925 }
1926 }
1927
1928 if (status & Y2_HWE_L1_MASK)
1929 sky2_hw_error(hw, 0, status);
1930 status >>= 8;
1931 if (status & Y2_HWE_L1_MASK)
1932 sky2_hw_error(hw, 1, status);
1933}
1934
1935static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1936{
1937 struct net_device *dev = hw->dev[port];
1938 struct sky2_port *sky2 = netdev_priv(dev);
1939 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1940
1941 if (netif_msg_intr(sky2))
1942 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1943 dev->name, status);
1944
1945 if (status & GM_IS_RX_FF_OR) {
1946 ++sky2->net_stats.rx_fifo_errors;
1947 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1948 }
1949
1950 if (status & GM_IS_TX_FF_UR) {
1951 ++sky2->net_stats.tx_fifo_errors;
1952 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1953 }
cd28ab6a
SH		 1954}
1955
1956static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1957{
1958 struct net_device *dev = hw->dev[port];
1959 struct sky2_port *sky2 = netdev_priv(dev);
1960
1961 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1962 sky2_write32(hw, B0_IMSK, hw->intr_mask);
91c86df5 1963 schedule_work(&sky2->phy_task);
cd28ab6a
SH		 1964}
1965
1966static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1967{
1968 struct sky2_hw *hw = dev_id;
bea86103 1969 struct net_device *dev0 = hw->dev[0];
cd28ab6a
SH		 1970 u32 status;
1971
1972 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
793b883e 1973 if (status == 0 || status == ~0)
cd28ab6a
SH		 1974 return IRQ_NONE;
1975
1976 if (status & Y2_IS_HW_ERR)
1977 sky2_hw_intr(hw);
1978
793b883e 1979 /* Do NAPI for Rx and Tx status */
bea86103 1980 if (status & Y2_IS_STAT_BMU) {
cd28ab6a
SH		 1981 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1982 sky2_write32(hw, B0_IMSK, hw->intr_mask);
bea86103 1983
0a122576
SH		 1984 if (likely(__netif_rx_schedule_prep(dev0))) {
1985 prefetch(&hw->st_le[hw->st_idx]);
bea86103 1986 __netif_rx_schedule(dev0);
0a122576 1987 }
cd28ab6a
SH		 1988 }
1989
793b883e 1990 if (status & Y2_IS_IRQ_PHY1)
cd28ab6a
SH		 1991 sky2_phy_intr(hw, 0);
1992
1993 if (status & Y2_IS_IRQ_PHY2)
1994 sky2_phy_intr(hw, 1);
1995
1996 if (status & Y2_IS_IRQ_MAC1)
1997 sky2_mac_intr(hw, 0);
1998
1999 if (status & Y2_IS_IRQ_MAC2)
2000 sky2_mac_intr(hw, 1);
2001
cd28ab6a 2002 sky2_write32(hw, B0_Y2_SP_ICR, 2);
793b883e
SH		 2003
2004 sky2_read32(hw, B0_IMSK);
2005
cd28ab6a
SH		 2006 return IRQ_HANDLED;
2007}
2008
2009#ifdef CONFIG_NET_POLL_CONTROLLER
2010static void sky2_netpoll(struct net_device *dev)
2011{
2012 struct sky2_port *sky2 = netdev_priv(dev);
2013
793b883e 2014 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
cd28ab6a
SH		 2015}
2016#endif
2017
2018/* Chip internal frequency for clock calculations */
fb17358f 2019static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2020{
793b883e 2021 switch (hw->chip_id) {
cd28ab6a 2022 case CHIP_ID_YUKON_EC:
5a5b1ea0 2023 case CHIP_ID_YUKON_EC_U:
fb17358f 2024 return 125; /* 125 Mhz */
cd28ab6a 2025 case CHIP_ID_YUKON_FE:
fb17358f 2026 return 100; /* 100 Mhz */
793b883e 2027 default: /* YUKON_XL */
fb17358f 2028 return 156; /* 156 Mhz */
cd28ab6a
SH		 2029 }
2030}
2031
fb17358f 2032static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2033{
fb17358f 2034 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2035}
2036
fb17358f 2037static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2038{
fb17358f 2039 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2040}
2041
fb17358f 2042
cd28ab6a
SH		 2043static int sky2_reset(struct sky2_hw *hw)
2044{
5afa0a9c 2045 u32 ctst;
cd28ab6a
SH		 2046 u16 status;
2047 u8 t8, pmd_type;
2048 int i;
2049
2050 ctst = sky2_read32(hw, B0_CTST);
2051
2052 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2053 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2054 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2055 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2056 pci_name(hw->pdev), hw->chip_id);
2057 return -EOPNOTSUPP;
2058 }
2059
793b883e
SH		 2060 /* ring for status responses */
2061 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
2062 &hw->st_dma);
2063 if (!hw->st_le)
2064 return -ENOMEM;
2065
cd28ab6a
SH		 2066 /* disable ASF */
2067 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2068 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2069 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2070 }
2071
2072 /* do a SW reset */
2073 sky2_write8(hw, B0_CTST, CS_RST_SET);
2074 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2075
2076 /* clear PCI errors, if any */
793b883e 2077 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
cd28ab6a 2078 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
793b883e
SH		 2079 pci_write_config_word(hw->pdev, PCI_STATUS,
2080 status | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2081
2082 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2083
2084 /* clear any PEX errors */
2085 if (is_pciex(hw)) {
793b883e
SH		 2086 u16 lstat;
2087 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
2088 0xffffffffUL);
2089 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
cd28ab6a
SH		 2090 }
2091
2092 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2093 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2094
2095 hw->ports = 1;
2096 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2097 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2098 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2099 ++hw->ports;
2100 }
2101 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2102
5afa0a9c 2103 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2104
2105 for (i = 0; i < hw->ports; i++) {
2106 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2107 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2108 }
2109
2110 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2111
793b883e
SH		 2112 /* Clear I2C IRQ noise */
2113 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2114
2115 /* turn off hardware timer (unused) */
2116 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2117 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2118
cd28ab6a
SH		 2119 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2120
793b883e 2121 /* Turn on descriptor polling (every 75us) */
cd28ab6a
SH		 2122 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
2123 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
2124
2125 /* Turn off receive timestamp */
2126 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2127 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2128
2129 /* enable the Tx Arbiters */
2130 for (i = 0; i < hw->ports; i++)
2131 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2132
2133 /* Initialize ram interface */
2134 for (i = 0; i < hw->ports; i++) {
793b883e 2135 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2136
2137 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2138 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2139 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2140 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2141 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2142 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2143 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2144 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2145 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2146 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2147 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2148 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2149 }
2150
cd28ab6a
SH		 2151 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2152
cd28ab6a
SH		 2153 for (i = 0; i < hw->ports; i++)
2154 sky2_phy_reset(hw, i);
cd28ab6a 2155
cd28ab6a
SH		 2156 memset(hw->st_le, 0, STATUS_LE_BYTES);
2157 hw->st_idx = 0;
2158
2159 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2160 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2161
2162 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2163 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2164
2165 /* Set the list last index */
793b883e 2166 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2167
fb17358f 2168 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
793b883e
SH		 2169
2170 /* These status setup values are copied from SysKonnect's driver */
cd28ab6a
SH		 2171 if (is_ec_a1(hw)) {
2172 /* WA for dev. #4.3 */
793b883e 2173 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
cd28ab6a
SH		 2174
2175 /* set Status-FIFO watermark */
2176 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2177
2178 /* set Status-FIFO ISR watermark */
793b883e 2179 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
cd28ab6a 2180
cd28ab6a 2181 } else {
cd28ab6a
SH		 2182 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2183
2184 /* set Status-FIFO watermark */
2185 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2186
2187 /* set Status-FIFO ISR watermark */
2188 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2189 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2190
d571b694 2191 else /* WA dev 4.109 */
cd28ab6a
SH		 2192 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2193
2194 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2195 }
2196
793b883e 2197 /* enable status unit */
cd28ab6a
SH		 2198 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2199
2200 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2201 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2202 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2203
2204 return 0;
2205}
2206
2207static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2208{
2209 u32 modes;
2210 if (hw->copper) {
793b883e
SH		 2211 modes = SUPPORTED_10baseT_Half
2212 | SUPPORTED_10baseT_Full
2213 | SUPPORTED_100baseT_Half
2214 | SUPPORTED_100baseT_Full
2215 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2216
2217 if (hw->chip_id != CHIP_ID_YUKON_FE)
2218 modes |= SUPPORTED_1000baseT_Half
793b883e 2219 | SUPPORTED_1000baseT_Full;
cd28ab6a
SH		 2220 } else
2221 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
793b883e 2222 | SUPPORTED_Autoneg;
cd28ab6a
SH		 2223 return modes;
2224}
2225
793b883e 2226static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2227{
2228 struct sky2_port *sky2 = netdev_priv(dev);
2229 struct sky2_hw *hw = sky2->hw;
2230
2231 ecmd->transceiver = XCVR_INTERNAL;
2232 ecmd->supported = sky2_supported_modes(hw);
2233 ecmd->phy_address = PHY_ADDR_MARV;
2234 if (hw->copper) {
2235 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2236 | SUPPORTED_10baseT_Full
2237 | SUPPORTED_100baseT_Half
2238 | SUPPORTED_100baseT_Full
2239 | SUPPORTED_1000baseT_Half
2240 | SUPPORTED_1000baseT_Full
2241 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2242 ecmd->port = PORT_TP;
2243 } else
2244 ecmd->port = PORT_FIBRE;
2245
2246 ecmd->advertising = sky2->advertising;
2247 ecmd->autoneg = sky2->autoneg;
2248 ecmd->speed = sky2->speed;
2249 ecmd->duplex = sky2->duplex;
2250 return 0;
2251}
2252
2253static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2254{
2255 struct sky2_port *sky2 = netdev_priv(dev);
2256 const struct sky2_hw *hw = sky2->hw;
2257 u32 supported = sky2_supported_modes(hw);
2258
2259 if (ecmd->autoneg == AUTONEG_ENABLE) {
2260 ecmd->advertising = supported;
2261 sky2->duplex = -1;
2262 sky2->speed = -1;
2263 } else {
2264 u32 setting;
2265
793b883e 2266 switch (ecmd->speed) {
cd28ab6a
SH		 2267 case SPEED_1000:
2268 if (ecmd->duplex == DUPLEX_FULL)
2269 setting = SUPPORTED_1000baseT_Full;
2270 else if (ecmd->duplex == DUPLEX_HALF)
2271 setting = SUPPORTED_1000baseT_Half;
2272 else
2273 return -EINVAL;
2274 break;
2275 case SPEED_100:
2276 if (ecmd->duplex == DUPLEX_FULL)
2277 setting = SUPPORTED_100baseT_Full;
2278 else if (ecmd->duplex == DUPLEX_HALF)
2279 setting = SUPPORTED_100baseT_Half;
2280 else
2281 return -EINVAL;
2282 break;
2283
2284 case SPEED_10:
2285 if (ecmd->duplex == DUPLEX_FULL)
2286 setting = SUPPORTED_10baseT_Full;
2287 else if (ecmd->duplex == DUPLEX_HALF)
2288 setting = SUPPORTED_10baseT_Half;
2289 else
2290 return -EINVAL;
2291 break;
2292 default:
2293 return -EINVAL;
2294 }
2295
2296 if ((setting & supported) == 0)
2297 return -EINVAL;
2298
2299 sky2->speed = ecmd->speed;
2300 sky2->duplex = ecmd->duplex;
2301 }
2302
2303 sky2->autoneg = ecmd->autoneg;
2304 sky2->advertising = ecmd->advertising;
2305
2306 if (netif_running(dev)) {
2307 sky2_down(dev);
2308 sky2_up(dev);
2309 }
2310
2311 return 0;
2312}
2313
2314static void sky2_get_drvinfo(struct net_device *dev,
2315 struct ethtool_drvinfo *info)
2316{
2317 struct sky2_port *sky2 = netdev_priv(dev);
2318
2319 strcpy(info->driver, DRV_NAME);
2320 strcpy(info->version, DRV_VERSION);
2321 strcpy(info->fw_version, "N/A");
2322 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2323}
2324
2325static const struct sky2_stat {
793b883e
SH		 2326 char name[ETH_GSTRING_LEN];
2327 u16 offset;
cd28ab6a
SH		 2328} sky2_stats[] = {
2329 { "tx_bytes", GM_TXO_OK_HI },
2330 { "rx_bytes", GM_RXO_OK_HI },
2331 { "tx_broadcast", GM_TXF_BC_OK },
2332 { "rx_broadcast", GM_RXF_BC_OK },
2333 { "tx_multicast", GM_TXF_MC_OK },
2334 { "rx_multicast", GM_RXF_MC_OK },
2335 { "tx_unicast", GM_TXF_UC_OK },
2336 { "rx_unicast", GM_RXF_UC_OK },
2337 { "tx_mac_pause", GM_TXF_MPAUSE },
2338 { "rx_mac_pause", GM_RXF_MPAUSE },
2339 { "collisions", GM_TXF_SNG_COL },
2340 { "late_collision",GM_TXF_LAT_COL },
2341 { "aborted", GM_TXF_ABO_COL },
2342 { "multi_collisions", GM_TXF_MUL_COL },
2343 { "fifo_underrun", GM_TXE_FIFO_UR },
2344 { "fifo_overflow", GM_RXE_FIFO_OV },
2345 { "rx_toolong", GM_RXF_LNG_ERR },
2346 { "rx_jabber", GM_RXF_JAB_PKT },
2347 { "rx_runt", GM_RXE_FRAG },
2348 { "rx_too_long", GM_RXF_LNG_ERR },
2349 { "rx_fcs_error", GM_RXF_FCS_ERR },
2350};
2351
cd28ab6a
SH		 2352static u32 sky2_get_rx_csum(struct net_device *dev)
2353{
2354 struct sky2_port *sky2 = netdev_priv(dev);
2355
2356 return sky2->rx_csum;
2357}
2358
2359static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2360{
2361 struct sky2_port *sky2 = netdev_priv(dev);
2362
2363 sky2->rx_csum = data;
793b883e 2364
cd28ab6a
SH		 2365 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2366 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2367
2368 return 0;
2369}
2370
2371static u32 sky2_get_msglevel(struct net_device *netdev)
2372{
2373 struct sky2_port *sky2 = netdev_priv(netdev);
2374 return sky2->msg_enable;
2375}
2376
9a7ae0a9
SH		 2377static int sky2_nway_reset(struct net_device *dev)
2378{
2379 struct sky2_port *sky2 = netdev_priv(dev);
2380 struct sky2_hw *hw = sky2->hw;
2381
2382 if (sky2->autoneg != AUTONEG_ENABLE)
2383 return -EINVAL;
2384
2385 netif_stop_queue(dev);
2386
91c86df5 2387 down(&sky2->phy_sema);
9a7ae0a9
SH		 2388 sky2_phy_reset(hw, sky2->port);
2389 sky2_phy_init(hw, sky2->port);
91c86df5 2390 up(&sky2->phy_sema);
9a7ae0a9
SH		 2391
2392 return 0;
2393}
2394
793b883e 2395static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2396{
2397 struct sky2_hw *hw = sky2->hw;
2398 unsigned port = sky2->port;
2399 int i;
2400
2401 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2402 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2403 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2404 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2405
793b883e 2406 for (i = 2; i < count; i++)
cd28ab6a
SH		 2407 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2408}
2409
cd28ab6a
SH		 2410static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2411{
2412 struct sky2_port *sky2 = netdev_priv(netdev);
2413 sky2->msg_enable = value;
2414}
2415
2416static int sky2_get_stats_count(struct net_device *dev)
2417{
2418 return ARRAY_SIZE(sky2_stats);
2419}
2420
2421static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2422 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2423{
2424 struct sky2_port *sky2 = netdev_priv(dev);
2425
793b883e 2426 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2427}
2428
793b883e 2429static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2430{
2431 int i;
2432
2433 switch (stringset) {
2434 case ETH_SS_STATS:
2435 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2436 memcpy(data + i * ETH_GSTRING_LEN,
2437 sky2_stats[i].name, ETH_GSTRING_LEN);
2438 break;
2439 }
2440}
2441
2442/* Use hardware MIB variables for critical path statistics and
2443 * transmit feedback not reported at interrupt.
2444 * Other errors are accounted for in interrupt handler.
2445 */
2446static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2447{
2448 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2449 u64 data[13];
cd28ab6a 2450
793b883e 2451 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2452
2453 sky2->net_stats.tx_bytes = data[0];
2454 sky2->net_stats.rx_bytes = data[1];
2455 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2456 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2457 sky2->net_stats.multicast = data[5] + data[7];
2458 sky2->net_stats.collisions = data[10];
2459 sky2->net_stats.tx_aborted_errors = data[12];
2460
2461 return &sky2->net_stats;
2462}
2463
2464static int sky2_set_mac_address(struct net_device *dev, void *p)
2465{
2466 struct sky2_port *sky2 = netdev_priv(dev);
2467 struct sockaddr *addr = p;
2468 int err = 0;
2469
2470 if (!is_valid_ether_addr(addr->sa_data))
2471 return -EADDRNOTAVAIL;
2472
2473 sky2_down(dev);
2474 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
793b883e 2475 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
cd28ab6a 2476 dev->dev_addr, ETH_ALEN);
793b883e 2477 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
cd28ab6a
SH		 2478 dev->dev_addr, ETH_ALEN);
2479 if (dev->flags & IFF_UP)
2480 err = sky2_up(dev);
2481 return err;
2482}
2483
2484static void sky2_set_multicast(struct net_device *dev)
2485{
2486 struct sky2_port *sky2 = netdev_priv(dev);
2487 struct sky2_hw *hw = sky2->hw;
2488 unsigned port = sky2->port;
2489 struct dev_mc_list *list = dev->mc_list;
2490 u16 reg;
2491 u8 filter[8];
2492
2493 memset(filter, 0, sizeof(filter));
2494
2495 reg = gma_read16(hw, port, GM_RX_CTRL);
2496 reg |= GM_RXCR_UCF_ENA;
2497
d571b694 2498 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2499 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2500 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2501 memset(filter, 0xff, sizeof(filter));
793b883e 2502 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2503 reg &= ~GM_RXCR_MCF_ENA;
2504 else {
2505 int i;
2506 reg |= GM_RXCR_MCF_ENA;
2507
2508 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2509 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2510 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2511 }
2512 }
2513
cd28ab6a 2514 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2515 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2516 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2517 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2518 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2519 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2520 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2521 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2522
2523 gma_write16(hw, port, GM_RX_CTRL, reg);
2524}
2525
2526/* Can have one global because blinking is controlled by
2527 * ethtool and that is always under RTNL mutex
2528 */
91c86df5 2529static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2530{
793b883e
SH		 2531 u16 pg;
2532
793b883e
SH		 2533 switch (hw->chip_id) {
2534 case CHIP_ID_YUKON_XL:
2535 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2536 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2537 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2538 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2539 PHY_M_LEDC_INIT_CTRL(7) |
2540 PHY_M_LEDC_STA1_CTRL(7) |
2541 PHY_M_LEDC_STA0_CTRL(7))
2542 : 0);
2543
2544 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2545 break;
2546
2547 default:
2548 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2549 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2550 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2551 PHY_M_LED_MO_10(MO_LED_ON) |
2552 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2553 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2554 PHY_M_LED_MO_RX(MO_LED_ON)
2555 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2556 PHY_M_LED_MO_10(MO_LED_OFF) |
2557 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2558 PHY_M_LED_MO_1000(MO_LED_OFF) |
2559 PHY_M_LED_MO_RX(MO_LED_OFF));
2560
793b883e 2561 }
cd28ab6a
SH		 2562}
2563
2564/* blink LED's for finding board */
2565static int sky2_phys_id(struct net_device *dev, u32 data)
2566{
2567 struct sky2_port *sky2 = netdev_priv(dev);
2568 struct sky2_hw *hw = sky2->hw;
2569 unsigned port = sky2->port;
793b883e 2570 u16 ledctrl, ledover = 0;
cd28ab6a 2571 long ms;
91c86df5 2572 int interrupted;
cd28ab6a
SH		 2573 int onoff = 1;
2574
793b883e 2575 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2576 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2577 else
2578 ms = data * 1000;
2579
2580 /* save initial values */
91c86df5 2581 down(&sky2->phy_sema);
793b883e
SH		 2582 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2583 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2584 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2585 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2586 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2587 } else {
2588 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2589 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2590 }
cd28ab6a 2591
91c86df5
SH		 2592 interrupted = 0;
2593 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2594 sky2_led(hw, port, onoff);
2595 onoff = !onoff;
2596
91c86df5
SH		 2597 up(&sky2->phy_sema);
2598 interrupted = msleep_interruptible(250);
2599 down(&sky2->phy_sema);
2600
cd28ab6a
SH		 2601 ms -= 250;
2602 }
2603
2604 /* resume regularly scheduled programming */
793b883e
SH		 2605 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2606 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2607 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2608 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2609 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2610 } else {
2611 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2612 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2613 }
91c86df5 2614 up(&sky2->phy_sema);
cd28ab6a
SH		 2615
2616 return 0;
2617}
2618
2619static void sky2_get_pauseparam(struct net_device *dev,
2620 struct ethtool_pauseparam *ecmd)
2621{
2622 struct sky2_port *sky2 = netdev_priv(dev);
2623
2624 ecmd->tx_pause = sky2->tx_pause;
2625 ecmd->rx_pause = sky2->rx_pause;
2626 ecmd->autoneg = sky2->autoneg;
2627}
2628
2629static int sky2_set_pauseparam(struct net_device *dev,
2630 struct ethtool_pauseparam *ecmd)
2631{
2632 struct sky2_port *sky2 = netdev_priv(dev);
2633 int err = 0;
2634
2635 sky2->autoneg = ecmd->autoneg;
2636 sky2->tx_pause = ecmd->tx_pause != 0;
2637 sky2->rx_pause = ecmd->rx_pause != 0;
2638
2639 if (netif_running(dev)) {
2640 sky2_down(dev);
2641 err = sky2_up(dev);
2642 }
2643
2644 return err;
2645}
2646
2647#ifdef CONFIG_PM
2648static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2649{
2650 struct sky2_port *sky2 = netdev_priv(dev);
2651
2652 wol->supported = WAKE_MAGIC;
2653 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2654}
2655
2656static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2657{
2658 struct sky2_port *sky2 = netdev_priv(dev);
2659 struct sky2_hw *hw = sky2->hw;
2660
2661 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2662 return -EOPNOTSUPP;
2663
2664 sky2->wol = wol->wolopts == WAKE_MAGIC;
2665
2666 if (sky2->wol) {
2667 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2668
2669 sky2_write16(hw, WOL_CTRL_STAT,
2670 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2671 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2672 } else
2673 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2674
2675 return 0;
2676}
2677#endif
2678
fb17358f
SH		 2679static int sky2_get_coalesce(struct net_device *dev,
2680 struct ethtool_coalesce *ecmd)
2681{
2682 struct sky2_port *sky2 = netdev_priv(dev);
2683 struct sky2_hw *hw = sky2->hw;
2684
2685 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2686 ecmd->tx_coalesce_usecs = 0;
2687 else {
2688 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2689 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2690 }
2691 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2692
2693 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2694 ecmd->rx_coalesce_usecs = 0;
2695 else {
2696 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2697 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2698 }
2699 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2700
2701 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2702 ecmd->rx_coalesce_usecs_irq = 0;
2703 else {
2704 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2705 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2706 }
2707
2708 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2709
2710 return 0;
2711}
2712
2713/* Note: this affect both ports */
2714static int sky2_set_coalesce(struct net_device *dev,
2715 struct ethtool_coalesce *ecmd)
2716{
2717 struct sky2_port *sky2 = netdev_priv(dev);
2718 struct sky2_hw *hw = sky2->hw;
2719 const u32 tmin = sky2_clk2us(hw, 1);
2720 const u32 tmax = 5000;
2721
2722 if (ecmd->tx_coalesce_usecs != 0 &&
2723 (ecmd->tx_coalesce_usecs < tmin || ecmd->tx_coalesce_usecs > tmax))
2724 return -EINVAL;
2725
2726 if (ecmd->rx_coalesce_usecs != 0 &&
2727 (ecmd->rx_coalesce_usecs < tmin || ecmd->rx_coalesce_usecs > tmax))
2728 return -EINVAL;
2729
2730 if (ecmd->rx_coalesce_usecs_irq != 0 &&
2731 (ecmd->rx_coalesce_usecs_irq < tmin || ecmd->rx_coalesce_usecs_irq > tmax))
2732 return -EINVAL;
2733
2734 if (ecmd->tx_max_coalesced_frames > 0xffff)
2735 return -EINVAL;
2736 if (ecmd->rx_max_coalesced_frames > 0xff)
2737 return -EINVAL;
2738 if (ecmd->rx_max_coalesced_frames_irq > 0xff)
2739 return -EINVAL;
2740
2741 if (ecmd->tx_coalesce_usecs == 0)
2742 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2743 else {
2744 sky2_write32(hw, STAT_TX_TIMER_INI,
2745 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2746 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2747 }
2748 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2749
2750 if (ecmd->rx_coalesce_usecs == 0)
2751 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2752 else {
2753 sky2_write32(hw, STAT_LEV_TIMER_INI,
2754 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2755 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2756 }
2757 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2758
2759 if (ecmd->rx_coalesce_usecs_irq == 0)
2760 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2761 else {
2762 sky2_write32(hw, STAT_TX_TIMER_INI,
2763 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2764 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2765 }
2766 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2767 return 0;
2768}
2769
793b883e
SH		 2770static void sky2_get_ringparam(struct net_device *dev,
2771 struct ethtool_ringparam *ering)
2772{
2773 struct sky2_port *sky2 = netdev_priv(dev);
2774
2775 ering->rx_max_pending = RX_MAX_PENDING;
2776 ering->rx_mini_max_pending = 0;
2777 ering->rx_jumbo_max_pending = 0;
2778 ering->tx_max_pending = TX_RING_SIZE - 1;
2779
2780 ering->rx_pending = sky2->rx_pending;
2781 ering->rx_mini_pending = 0;
2782 ering->rx_jumbo_pending = 0;
2783 ering->tx_pending = sky2->tx_pending;
2784}
2785
2786static int sky2_set_ringparam(struct net_device *dev,
2787 struct ethtool_ringparam *ering)
2788{
2789 struct sky2_port *sky2 = netdev_priv(dev);
2790 int err = 0;
2791
2792 if (ering->rx_pending > RX_MAX_PENDING ||
2793 ering->rx_pending < 8 ||
2794 ering->tx_pending < MAX_SKB_TX_LE ||
2795 ering->tx_pending > TX_RING_SIZE - 1)
2796 return -EINVAL;
2797
2798 if (netif_running(dev))
2799 sky2_down(dev);
2800
2801 sky2->rx_pending = ering->rx_pending;
2802 sky2->tx_pending = ering->tx_pending;
2803
2804 if (netif_running(dev))
2805 err = sky2_up(dev);
2806
2807 return err;
2808}
2809
793b883e
SH		 2810static int sky2_get_regs_len(struct net_device *dev)
2811{
6e4cbb34 2812 return 0x4000;
793b883e
SH		 2813}
2814
2815/*
2816 * Returns copy of control register region
6e4cbb34 2817 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 2818 */
2819static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2820 void *p)
2821{
2822 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2823 const void __iomem *io = sky2->hw->regs;
793b883e 2824
6e4cbb34 2825 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 2826 regs->version = 1;
6e4cbb34 2827 memset(p, 0, regs->len);
793b883e 2828
6e4cbb34
SH		 2829 memcpy_fromio(p, io, B3_RAM_ADDR);
2830
2831 memcpy_fromio(p + B3_RI_WTO_R1,
2832 io + B3_RI_WTO_R1,
2833 regs->len - B3_RI_WTO_R1);
793b883e 2834}
cd28ab6a
SH		 2835
2836static struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 2837 .get_settings = sky2_get_settings,
2838 .set_settings = sky2_set_settings,
2839 .get_drvinfo = sky2_get_drvinfo,
2840 .get_msglevel = sky2_get_msglevel,
2841 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 2842 .nway_reset = sky2_nway_reset,
793b883e
SH		 2843 .get_regs_len = sky2_get_regs_len,
2844 .get_regs = sky2_get_regs,
2845 .get_link = ethtool_op_get_link,
2846 .get_sg = ethtool_op_get_sg,
2847 .set_sg = ethtool_op_set_sg,
2848 .get_tx_csum = ethtool_op_get_tx_csum,
2849 .set_tx_csum = ethtool_op_set_tx_csum,
2850 .get_tso = ethtool_op_get_tso,
2851 .set_tso = ethtool_op_set_tso,
2852 .get_rx_csum = sky2_get_rx_csum,
2853 .set_rx_csum = sky2_set_rx_csum,
2854 .get_strings = sky2_get_strings,
fb17358f
SH		 2855 .get_coalesce = sky2_get_coalesce,
2856 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 2857 .get_ringparam = sky2_get_ringparam,
2858 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 2859 .get_pauseparam = sky2_get_pauseparam,
2860 .set_pauseparam = sky2_set_pauseparam,
2861#ifdef CONFIG_PM
793b883e
SH		 2862 .get_wol = sky2_get_wol,
2863 .set_wol = sky2_set_wol,
cd28ab6a 2864#endif
793b883e 2865 .phys_id = sky2_phys_id,
cd28ab6a
SH		 2866 .get_stats_count = sky2_get_stats_count,
2867 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 2868 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 2869};
2870
2871/* Initialize network device */
2872static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2873 unsigned port, int highmem)
2874{
2875 struct sky2_port *sky2;
2876 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2877
2878 if (!dev) {
2879 printk(KERN_ERR "sky2 etherdev alloc failed");
2880 return NULL;
2881 }
2882
2883 SET_MODULE_OWNER(dev);
2884 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 2885 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 2886 dev->open = sky2_up;
2887 dev->stop = sky2_down;
ef743d33 2888 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 2889 dev->hard_start_xmit = sky2_xmit_frame;
2890 dev->get_stats = sky2_get_stats;
2891 dev->set_multicast_list = sky2_set_multicast;
2892 dev->set_mac_address = sky2_set_mac_address;
2893 dev->change_mtu = sky2_change_mtu;
2894 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2895 dev->tx_timeout = sky2_tx_timeout;
2896 dev->watchdog_timeo = TX_WATCHDOG;
2897 if (port == 0)
2898 dev->poll = sky2_poll;
2899 dev->weight = NAPI_WEIGHT;
2900#ifdef CONFIG_NET_POLL_CONTROLLER
2901 dev->poll_controller = sky2_netpoll;
2902#endif
cd28ab6a
SH		 2903
2904 sky2 = netdev_priv(dev);
2905 sky2->netdev = dev;
2906 sky2->hw = hw;
2907 sky2->msg_enable = netif_msg_init(debug, default_msg);
2908
2909 spin_lock_init(&sky2->tx_lock);
2910 /* Auto speed and flow control */
2911 sky2->autoneg = AUTONEG_ENABLE;
2912 sky2->tx_pause = 0;
2913 sky2->rx_pause = 1;
2914 sky2->duplex = -1;
2915 sky2->speed = -1;
2916 sky2->advertising = sky2_supported_modes(hw);
2917 sky2->rx_csum = 1;
91c86df5
SH		 2918 INIT_WORK(&sky2->phy_task, sky2_phy_task, sky2);
2919 init_MUTEX(&sky2->phy_sema);
793b883e
SH		 2920 sky2->tx_pending = TX_DEF_PENDING;
2921 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
cd28ab6a
SH		 2922
2923 hw->dev[port] = dev;
2924
2925 sky2->port = port;
2926
5a5b1ea0
SH		 2927 dev->features |= NETIF_F_LLTX;
2928 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
2929 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 2930 if (highmem)
2931 dev->features |= NETIF_F_HIGHDMA;
793b883e 2932 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 2933
d1f13708
SH		 2934#ifdef SKY2_VLAN_TAG_USED
2935 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2936 dev->vlan_rx_register = sky2_vlan_rx_register;
2937 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2938#endif
2939
cd28ab6a 2940 /* read the mac address */
793b883e 2941 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 2942 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 2943
2944 /* device is off until link detection */
2945 netif_carrier_off(dev);
2946 netif_stop_queue(dev);
2947
2948 return dev;
2949}
2950
2951static inline void sky2_show_addr(struct net_device *dev)
2952{
2953 const struct sky2_port *sky2 = netdev_priv(dev);
2954
2955 if (netif_msg_probe(sky2))
2956 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2957 dev->name,
2958 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2959 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2960}
2961
2962static int __devinit sky2_probe(struct pci_dev *pdev,
2963 const struct pci_device_id *ent)
2964{
793b883e 2965 struct net_device *dev, *dev1 = NULL;
cd28ab6a 2966 struct sky2_hw *hw;
5afa0a9c 2967 int err, pm_cap, using_dac = 0;
cd28ab6a 2968
793b883e
SH		 2969 err = pci_enable_device(pdev);
2970 if (err) {
cd28ab6a
SH		 2971 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2972 pci_name(pdev));
2973 goto err_out;
2974 }
2975
793b883e
SH		 2976 err = pci_request_regions(pdev, DRV_NAME);
2977 if (err) {
cd28ab6a
SH		 2978 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2979 pci_name(pdev));
793b883e 2980 goto err_out;
cd28ab6a
SH		 2981 }
2982
2983 pci_set_master(pdev);
2984
5afa0a9c
SH		 2985 /* Find power-management capability. */
2986 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2987 if (pm_cap == 0) {
2988 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
2989 "aborting.\n");
2990 err = -EIO;
2991 goto err_out_free_regions;
2992 }
2993
cd28ab6a
SH		 2994 if (sizeof(dma_addr_t) > sizeof(u32)) {
2995 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2996 if (!err)
2997 using_dac = 1;
2998 }
2999
3000 if (!using_dac) {
3001 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3002 if (err) {
3003 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3004 pci_name(pdev));
3005 goto err_out_free_regions;
3006 }
3007 }
cd28ab6a 3008#ifdef __BIG_ENDIAN
d571b694 3009 /* byte swap descriptors in hardware */
cd28ab6a
SH		 3010 {
3011 u32 reg;
3012
3013 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3014 reg |= PCI_REV_DESC;
3015 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3016 }
3017#endif
3018
3019 err = -ENOMEM;
3020 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
3021 if (!hw) {
3022 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3023 pci_name(pdev));
3024 goto err_out_free_regions;
3025 }
3026
3027 memset(hw, 0, sizeof(*hw));
3028 hw->pdev = pdev;
cd28ab6a
SH		 3029
3030 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3031 if (!hw->regs) {
3032 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3033 pci_name(pdev));
3034 goto err_out_free_hw;
3035 }
5afa0a9c 3036 hw->pm_cap = pm_cap;
cd28ab6a 3037
cd28ab6a
SH		 3038 err = sky2_reset(hw);
3039 if (err)
793b883e 3040 goto err_out_iounmap;
cd28ab6a 3041
5f4f9dc1
SH		 3042 printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
3043 DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq,
92f965e8 3044 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3045 hw->chip_id, hw->chip_rev);
cd28ab6a 3046
793b883e
SH		 3047 dev = sky2_init_netdev(hw, 0, using_dac);
3048 if (!dev)
cd28ab6a
SH		 3049 goto err_out_free_pci;
3050
793b883e
SH		 3051 err = register_netdev(dev);
3052 if (err) {
cd28ab6a
SH		 3053 printk(KERN_ERR PFX "%s: cannot register net device\n",
3054 pci_name(pdev));
3055 goto err_out_free_netdev;
3056 }
3057
3058 sky2_show_addr(dev);
3059
3060 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3061 if (register_netdev(dev1) == 0)
3062 sky2_show_addr(dev1);
3063 else {
3064 /* Failure to register second port need not be fatal */
793b883e
SH		 3065 printk(KERN_WARNING PFX
3066 "register of second port failed\n");
cd28ab6a
SH		 3067 hw->dev[1] = NULL;
3068 free_netdev(dev1);
3069 }
3070 }
3071
793b883e
SH		 3072 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
3073 if (err) {
3074 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3075 pci_name(pdev), pdev->irq);
3076 goto err_out_unregister;
3077 }
3078
3079 hw->intr_mask = Y2_IS_BASE;
3080 sky2_write32(hw, B0_IMSK, hw->intr_mask);
3081
3082 pci_set_drvdata(pdev, hw);
3083
cd28ab6a
SH		 3084 return 0;
3085
793b883e
SH		 3086err_out_unregister:
3087 if (dev1) {
3088 unregister_netdev(dev1);
3089 free_netdev(dev1);
3090 }
3091 unregister_netdev(dev);
cd28ab6a
SH		 3092err_out_free_netdev:
3093 free_netdev(dev);
cd28ab6a 3094err_out_free_pci:
793b883e 3095 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3096 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3097err_out_iounmap:
3098 iounmap(hw->regs);
3099err_out_free_hw:
3100 kfree(hw);
3101err_out_free_regions:
3102 pci_release_regions(pdev);
cd28ab6a 3103 pci_disable_device(pdev);
cd28ab6a
SH		 3104err_out:
3105 return err;
3106}
3107
3108static void __devexit sky2_remove(struct pci_dev *pdev)
3109{
793b883e 3110 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3111 struct net_device *dev0, *dev1;
3112
793b883e 3113 if (!hw)
cd28ab6a
SH		 3114 return;
3115
cd28ab6a 3116 dev0 = hw->dev[0];
793b883e
SH		 3117 dev1 = hw->dev[1];
3118 if (dev1)
3119 unregister_netdev(dev1);
cd28ab6a
SH		 3120 unregister_netdev(dev0);
3121
793b883e 3122 sky2_write32(hw, B0_IMSK, 0);
5afa0a9c 3123 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3124 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3125 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3126 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3127
3128 free_irq(pdev->irq, hw);
793b883e 3129 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3130 pci_release_regions(pdev);
3131 pci_disable_device(pdev);
793b883e 3132
cd28ab6a
SH		 3133 if (dev1)
3134 free_netdev(dev1);
3135 free_netdev(dev0);
3136 iounmap(hw->regs);
3137 kfree(hw);
5afa0a9c 3138
cd28ab6a
SH		 3139 pci_set_drvdata(pdev, NULL);
3140}
3141
3142#ifdef CONFIG_PM
3143static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3144{
793b883e 3145 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3146 int i;
cd28ab6a
SH		 3147
3148 for (i = 0; i < 2; i++) {
3149 struct net_device *dev = hw->dev[i];
3150
3151 if (dev) {
5afa0a9c
SH		 3152 if (!netif_running(dev))
3153 continue;
3154
3155 sky2_down(dev);
cd28ab6a 3156 netif_device_detach(dev);
cd28ab6a
SH		 3157 }
3158 }
3159
5afa0a9c 3160 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
cd28ab6a
SH		 3161}
3162
3163static int sky2_resume(struct pci_dev *pdev)
3164{
793b883e 3165 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3166 int i;
3167
cd28ab6a
SH		 3168 pci_restore_state(pdev);
3169 pci_enable_wake(pdev, PCI_D0, 0);
5afa0a9c 3170 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 3171
3172 sky2_reset(hw);
3173
3174 for (i = 0; i < 2; i++) {
3175 struct net_device *dev = hw->dev[i];
3176 if (dev) {
5afa0a9c
SH		 3177 if (netif_running(dev)) {
3178 netif_device_attach(dev);
cd28ab6a 3179 sky2_up(dev);
5afa0a9c 3180 }
cd28ab6a
SH		 3181 }
3182 }
3183 return 0;
3184}
3185#endif
3186
3187static struct pci_driver sky2_driver = {
793b883e
SH		 3188 .name = DRV_NAME,
3189 .id_table = sky2_id_table,
3190 .probe = sky2_probe,
3191 .remove = __devexit_p(sky2_remove),
cd28ab6a 3192#ifdef CONFIG_PM
793b883e
SH		 3193 .suspend = sky2_suspend,
3194 .resume = sky2_resume,
cd28ab6a
SH		 3195#endif
3196};
3197
3198static int __init sky2_init_module(void)
3199{
50241c4c 3200 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3201}
3202
3203static void __exit sky2_cleanup_module(void)
3204{
3205 pci_unregister_driver(&sky2_driver);
3206}
3207
3208module_init(sky2_init_module);
3209module_exit(sky2_cleanup_module);
3210
3211MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3212MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3213MODULE_LICENSE("GPL");
5f4f9dc1 3214MODULE_VERSION(DRV_VERSION);
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