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sky2: flow control setting fixes
[mirror_ubuntu-bionic-kernel.git] / drivers / net / sky2.c
CommitLineData
cd28ab6a
SH		 1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
793b883e 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
cd28ab6a
SH		 19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
793b883e 26#include <linux/crc32.h>
cd28ab6a
SH		 27#include <linux/kernel.h>
28#include <linux/version.h>
29#include <linux/module.h>
30#include <linux/netdevice.h>
d0bbccfa 31#include <linux/dma-mapping.h>
cd28ab6a
SH		 32#include <linux/etherdevice.h>
33#include <linux/ethtool.h>
34#include <linux/pci.h>
35#include <linux/ip.h>
36#include <linux/tcp.h>
37#include <linux/in.h>
38#include <linux/delay.h>
91c86df5 39#include <linux/workqueue.h>
d1f13708 40#include <linux/if_vlan.h>
d70cd51a 41#include <linux/prefetch.h>
ef743d33 42#include <linux/mii.h>
cd28ab6a
SH		 43
44#include <asm/irq.h>
45
d1f13708
SH		 46#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47#define SKY2_VLAN_TAG_USED 1
48#endif
49
cd28ab6a
SH		 50#include "sky2.h"
51
52#define DRV_NAME "sky2"
c73a29da 53#define DRV_VERSION "1.9"
cd28ab6a
SH		 54#define PFX DRV_NAME " "
55
56/*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
14d0263f 59 * similar to Tigon3.
cd28ab6a
SH		 60 */
61
14d0263f 62#define RX_LE_SIZE 1024
cd28ab6a 63#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
14d0263f 64#define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
13210ce5 65#define RX_DEF_PENDING RX_MAX_PENDING
82788c7a 66#define RX_SKB_ALIGN 8
22e11703 67#define RX_BUF_WRITE 16
793b883e
SH		 68
69#define TX_RING_SIZE 512
70#define TX_DEF_PENDING (TX_RING_SIZE - 1)
71#define TX_MIN_PENDING 64
b19666d9 72#define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
cd28ab6a 73
793b883e 74#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
cd28ab6a 75#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
cd28ab6a
SH		 76#define TX_WATCHDOG (5 * HZ)
77#define NAPI_WEIGHT 64
78#define PHY_RETRIES 1000
79
cb5d9547
SH		 80#define RING_NEXT(x,s) (((x)+1) & ((s)-1))
81
cd28ab6a 82static const u32 default_msg =
793b883e
SH		 83 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
84 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
3be92a70 85 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
cd28ab6a 86
793b883e 87static int debug = -1; /* defaults above */
cd28ab6a
SH		 88module_param(debug, int, 0);
89MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
90
14d0263f 91static int copybreak __read_mostly = 128;
bdb5c58e
SH		 92module_param(copybreak, int, 0);
93MODULE_PARM_DESC(copybreak, "Receive copy threshold");
94
fb2690a9
SH		 95static int disable_msi = 0;
96module_param(disable_msi, int, 0);
97MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
98
e561a83b 99static int idle_timeout = 0;
01bd7564 100module_param(idle_timeout, int, 0);
e561a83b 101MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
01bd7564 102
cd28ab6a 103static const struct pci_device_id sky2_id_table[] = {
793b883e 104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
cd28ab6a 105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
2d2a3871 106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
2f4a66ad 107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
cd28ab6a
SH		 108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
5a5b1ea0 118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
2f4a66ad 119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
cd28ab6a
SH		 120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
5a5b1ea0 123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
5f5d83fd 124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
57fa442c
SH		 125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
2f4a66ad 129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
cd28ab6a
SH		 130 { 0 }
131};
793b883e 132
cd28ab6a
SH		 133MODULE_DEVICE_TABLE(pci, sky2_id_table);
134
135/* Avoid conditionals by using array */
136static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
137static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
f4ea431b 138static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
cd28ab6a 139
92f965e8
SH		 140/* This driver supports yukon2 chipset only */
141static const char *yukon2_name[] = {
142 "XL", /* 0xb3 */
143 "EC Ultra", /* 0xb4 */
144 "UNKNOWN", /* 0xb5 */
145 "EC", /* 0xb6 */
146 "FE", /* 0xb7 */
793b883e
SH		 147};
148
793b883e 149/* Access to external PHY */
ef743d33 150static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
cd28ab6a
SH		 151{
152 int i;
153
154 gma_write16(hw, port, GM_SMI_DATA, val);
155 gma_write16(hw, port, GM_SMI_CTRL,
156 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
157
158 for (i = 0; i < PHY_RETRIES; i++) {
cd28ab6a 159 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
ef743d33 160 return 0;
793b883e 161 udelay(1);
cd28ab6a 162 }
ef743d33 163
793b883e 164 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
ef743d33 165 return -ETIMEDOUT;
cd28ab6a
SH		 166}
167
ef743d33 168static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
cd28ab6a
SH		 169{
170 int i;
171
793b883e 172 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
cd28ab6a
SH		 173 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
174
175 for (i = 0; i < PHY_RETRIES; i++) {
ef743d33
SH		 176 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
177 *val = gma_read16(hw, port, GM_SMI_DATA);
178 return 0;
179 }
180
793b883e 181 udelay(1);
cd28ab6a
SH		 182 }
183
ef743d33
SH		 184 return -ETIMEDOUT;
185}
186
187static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
188{
189 u16 v;
190
191 if (__gm_phy_read(hw, port, reg, &v) != 0)
192 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
193 return v;
cd28ab6a
SH		 194}
195
2ccc99b7 196static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
5afa0a9c
SH		 197{
198 u16 power_control;
5afa0a9c 199 int vaux;
5afa0a9c
SH		 200
201 pr_debug("sky2_set_power_state %d\n", state);
202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
203
56a645cc 204 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
08c06d8a 205 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
5afa0a9c
SH		 206 (power_control & PCI_PM_CAP_PME_D3cold);
207
56a645cc 208 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
5afa0a9c
SH		 209
210 power_control |= PCI_PM_CTRL_PME_STATUS;
211 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
212
213 switch (state) {
214 case PCI_D0:
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw, B0_POWER_CTRL,
217 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
218
219 /* disable Core Clock Division, */
220 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
221
222 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
223 /* enable bits are inverted */
224 sky2_write8(hw, B2_Y2_CLK_GATE,
225 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
226 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
227 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
228 else
229 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
230
977bdf06 231 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
d3bcfbeb
SH		 232 u32 reg1;
233
56a645cc
SH		 234 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
235 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
977bdf06 236 reg1 &= P_ASPM_CONTROL_MSK;
56a645cc
SH		 237 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
238 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
977bdf06
SH		 239 }
240
5afa0a9c
SH		 241 break;
242
243 case PCI_D3hot:
244 case PCI_D3cold:
5afa0a9c
SH		 245 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
246 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
247 else
248 /* enable bits are inverted */
249 sky2_write8(hw, B2_Y2_CLK_GATE,
250 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
251 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
252 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
253
254 /* switch power to VAUX */
255 if (vaux && state != PCI_D3cold)
256 sky2_write8(hw, B0_POWER_CTRL,
257 (PC_VAUX_ENA | PC_VCC_ENA |
258 PC_VAUX_ON | PC_VCC_OFF));
259 break;
260 default:
261 printk(KERN_ERR PFX "Unknown power state %d\n", state);
5afa0a9c
SH		 262 }
263
56a645cc 264 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
5afa0a9c 265 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
5afa0a9c
SH		 266}
267
d3bcfbeb 268static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
cd28ab6a
SH		 269{
270 u16 reg;
271
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
793b883e 276
cd28ab6a
SH		 277 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
278 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
279 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
280 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
281
282 reg = gma_read16(hw, port, GM_RX_CTRL);
283 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
284 gma_write16(hw, port, GM_RX_CTRL, reg);
285}
286
16ad91e1
SH		 287/* flow control to advertise bits */
288static const u16 copper_fc_adv[] = {
289 [FC_NONE] = 0,
290 [FC_TX] = PHY_M_AN_ASP,
291 [FC_RX] = PHY_M_AN_PC,
292 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
293};
294
295/* flow control to advertise bits when using 1000BaseX */
296static const u16 fiber_fc_adv[] = {
297 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
298 [FC_TX] = PHY_M_P_ASYM_MD_X,
299 [FC_RX] = PHY_M_P_SYM_MD_X,
300 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
301};
302
303/* flow control to GMA disable bits */
304static const u16 gm_fc_disable[] = {
305 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
306 [FC_TX] = GM_GPCR_FC_RX_DIS,
307 [FC_RX] = GM_GPCR_FC_TX_DIS,
308 [FC_BOTH] = 0,
309};
310
311
cd28ab6a
SH		 312static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
313{
314 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
2eaba1a2 315 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
cd28ab6a 316
ed6d32c7 317 if (sky2->autoneg == AUTONEG_ENABLE &&
86a31a75 318 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 319 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
320
321 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
793b883e 322 PHY_M_EC_MAC_S_MSK);
cd28ab6a
SH		 323 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
324
325 if (hw->chip_id == CHIP_ID_YUKON_EC)
326 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
327 else
328 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
329
330 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
331 }
332
333 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
b89165f2 334 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 335 if (hw->chip_id == CHIP_ID_YUKON_FE) {
336 /* enable automatic crossover */
337 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
338 } else {
339 /* disable energy detect */
340 ctrl &= ~PHY_M_PC_EN_DET_MSK;
341
342 /* enable automatic crossover */
343 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
344
345 if (sky2->autoneg == AUTONEG_ENABLE &&
ed6d32c7 346 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
cd28ab6a
SH		 347 ctrl &= ~PHY_M_PC_DSC_MSK;
348 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
349 }
350 }
cd28ab6a
SH		 351 } else {
352 /* workaround for deviation #4.88 (CRC errors) */
353 /* disable Automatic Crossover */
354
355 ctrl &= ~PHY_M_PC_MDIX_MSK;
b89165f2 356 }
cd28ab6a 357
b89165f2
SH		 358 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
359
360 /* special setup for PHY 88E1112 Fiber */
361 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
362 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a 363
b89165f2
SH		 364 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
365 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
366 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
367 ctrl &= ~PHY_M_MAC_MD_MSK;
368 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
369 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
370
371 if (hw->pmd_type == 'P') {
cd28ab6a
SH		 372 /* select page 1 to access Fiber registers */
373 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
b89165f2
SH		 374
375 /* for SFP-module set SIGDET polarity to low */
376 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
377 ctrl |= PHY_M_FIB_SIGD_POL;
378 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
cd28ab6a 379 }
b89165f2
SH		 380
381 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a
SH		 382 }
383
7800fddc 384 ctrl = PHY_CT_RESET;
cd28ab6a
SH		 385 ct1000 = 0;
386 adv = PHY_AN_CSMA;
2eaba1a2 387 reg = 0;
cd28ab6a
SH		 388
389 if (sky2->autoneg == AUTONEG_ENABLE) {
b89165f2 390 if (sky2_is_copper(hw)) {
cd28ab6a
SH		 391 if (sky2->advertising & ADVERTISED_1000baseT_Full)
392 ct1000 |= PHY_M_1000C_AFD;
393 if (sky2->advertising & ADVERTISED_1000baseT_Half)
394 ct1000 |= PHY_M_1000C_AHD;
395 if (sky2->advertising & ADVERTISED_100baseT_Full)
396 adv |= PHY_M_AN_100_FD;
397 if (sky2->advertising & ADVERTISED_100baseT_Half)
398 adv |= PHY_M_AN_100_HD;
399 if (sky2->advertising & ADVERTISED_10baseT_Full)
400 adv |= PHY_M_AN_10_FD;
401 if (sky2->advertising & ADVERTISED_10baseT_Half)
402 adv |= PHY_M_AN_10_HD;
709c6e7b 403
16ad91e1 404 adv |= copper_fc_adv[sky2->flow_mode];
b89165f2
SH		 405 } else { /* special defines for FIBER (88E1040S only) */
406 if (sky2->advertising & ADVERTISED_1000baseT_Full)
407 adv |= PHY_M_AN_1000X_AFD;
408 if (sky2->advertising & ADVERTISED_1000baseT_Half)
409 adv |= PHY_M_AN_1000X_AHD;
cd28ab6a 410
16ad91e1 411 adv |= fiber_fc_adv[sky2->flow_mode];
709c6e7b 412 }
cd28ab6a
SH		 413
414 /* Restart Auto-negotiation */
415 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
416 } else {
417 /* forced speed/duplex settings */
418 ct1000 = PHY_M_1000C_MSE;
419
2eaba1a2
SH		 420 /* Disable auto update for duplex flow control and speed */
421 reg |= GM_GPCR_AU_ALL_DIS;
cd28ab6a
SH		 422
423 switch (sky2->speed) {
424 case SPEED_1000:
425 ctrl |= PHY_CT_SP1000;
2eaba1a2 426 reg |= GM_GPCR_SPEED_1000;
cd28ab6a
SH		 427 break;
428 case SPEED_100:
429 ctrl |= PHY_CT_SP100;
2eaba1a2 430 reg |= GM_GPCR_SPEED_100;
cd28ab6a
SH		 431 break;
432 }
433
2eaba1a2
SH		 434 if (sky2->duplex == DUPLEX_FULL) {
435 reg |= GM_GPCR_DUP_FULL;
436 ctrl |= PHY_CT_DUP_MD;
16ad91e1
SH		 437 } else if (sky2->speed < SPEED_1000)
438 sky2->flow_mode = FC_NONE;
2eaba1a2 439
2eaba1a2 440
16ad91e1 441 reg |= gm_fc_disable[sky2->flow_mode];
2eaba1a2
SH		 442
443 /* Forward pause packets to GMAC? */
16ad91e1 444 if (sky2->flow_mode & FC_RX)
2eaba1a2
SH		 445 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
446 else
447 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
cd28ab6a
SH		 448 }
449
2eaba1a2
SH		 450 gma_write16(hw, port, GM_GP_CTRL, reg);
451
cd28ab6a
SH		 452 if (hw->chip_id != CHIP_ID_YUKON_FE)
453 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
454
455 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
456 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
457
458 /* Setup Phy LED's */
459 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
460 ledover = 0;
461
462 switch (hw->chip_id) {
463 case CHIP_ID_YUKON_FE:
464 /* on 88E3082 these bits are at 11..9 (shifted left) */
465 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
466
467 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
468
469 /* delete ACT LED control bits */
470 ctrl &= ~PHY_M_FELP_LED1_MSK;
471 /* change ACT LED control to blink mode */
472 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
473 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
474 break;
475
476 case CHIP_ID_YUKON_XL:
793b883e 477 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
cd28ab6a
SH		 478
479 /* select page 3 to access LED control register */
480 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
481
482 /* set LED Function Control register */
ed6d32c7
SH		 483 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
484 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
485 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
486 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
487 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
cd28ab6a
SH		 488
489 /* set Polarity Control register */
490 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
793b883e
SH		 491 (PHY_M_POLC_LS1_P_MIX(4) |
492 PHY_M_POLC_IS0_P_MIX(4) |
493 PHY_M_POLC_LOS_CTRL(2) |
494 PHY_M_POLC_INIT_CTRL(2) |
495 PHY_M_POLC_STA1_CTRL(2) |
496 PHY_M_POLC_STA0_CTRL(2)));
cd28ab6a
SH		 497
498 /* restore page register */
793b883e 499 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
cd28ab6a 500 break;
ed6d32c7
SH		 501 case CHIP_ID_YUKON_EC_U:
502 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
503
504 /* select page 3 to access LED control register */
505 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
506
507 /* set LED Function Control register */
508 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
509 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
510 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
511 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
512 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
513
514 /* set Blink Rate in LED Timer Control Register */
515 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
516 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
517 /* restore page register */
518 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
519 break;
cd28ab6a
SH		 520
521 default:
522 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
523 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
524 /* turn off the Rx LED (LED_RX) */
525 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
526 }
527
ed6d32c7 528 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
977bdf06 529 /* apply fixes in PHY AFE */
ed6d32c7
SH		 530 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
532
977bdf06 533 /* increase differential signal amplitude in 10BASE-T */
ed6d32c7
SH		 534 gm_phy_write(hw, port, 0x18, 0xaa99);
535 gm_phy_write(hw, port, 0x17, 0x2011);
cd28ab6a 536
977bdf06 537 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
ed6d32c7
SH		 538 gm_phy_write(hw, port, 0x18, 0xa204);
539 gm_phy_write(hw, port, 0x17, 0x2002);
977bdf06
SH		 540
541 /* set page register to 0 */
ed6d32c7 542 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
977bdf06
SH		 543 } else {
544 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
cd28ab6a 545
977bdf06
SH		 546 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
547 /* turn on 100 Mbps LED (LED_LINK100) */
548 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
549 }
cd28ab6a 550
977bdf06
SH		 551 if (ledover)
552 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
553
554 }
2eaba1a2 555
d571b694 556 /* Enable phy interrupt on auto-negotiation complete (or link up) */
cd28ab6a
SH		 557 if (sky2->autoneg == AUTONEG_ENABLE)
558 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
559 else
560 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
561}
562
d3bcfbeb
SH		 563static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
564{
565 u32 reg1;
566 static const u32 phy_power[]
567 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
568
569 /* looks like this XL is back asswards .. */
570 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
571 onoff = !onoff;
572
573 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
574
575 if (onoff)
576 /* Turn off phy power saving */
577 reg1 &= ~phy_power[port];
578 else
579 reg1 |= phy_power[port];
580
581 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
98232f85 582 sky2_pci_read32(hw, PCI_DEV_REG1);
d3bcfbeb
SH		 583 udelay(100);
584}
585
1b537565
SH		 586/* Force a renegotiation */
587static void sky2_phy_reinit(struct sky2_port *sky2)
588{
e07b1aa8 589 spin_lock_bh(&sky2->phy_lock);
1b537565 590 sky2_phy_init(sky2->hw, sky2->port);
e07b1aa8 591 spin_unlock_bh(&sky2->phy_lock);
1b537565
SH		 592}
593
cd28ab6a
SH		 594static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
595{
596 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
597 u16 reg;
598 int i;
599 const u8 *addr = hw->dev[port]->dev_addr;
600
42eeea01
SH		 601 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
602 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
cd28ab6a
SH		 603
604 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
605
793b883e 606 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
cd28ab6a
SH		 607 /* WA DEV_472 -- looks like crossed wires on port 2 */
608 /* clear GMAC 1 Control reset */
609 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
610 do {
611 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
612 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
613 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
614 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
615 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
616 }
617
793b883e 618 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
cd28ab6a 619
2eaba1a2
SH		 620 /* Enable Transmit FIFO Underrun */
621 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
622
e07b1aa8 623 spin_lock_bh(&sky2->phy_lock);
cd28ab6a 624 sky2_phy_init(hw, port);
e07b1aa8 625 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 626
627 /* MIB clear */
628 reg = gma_read16(hw, port, GM_PHY_ADDR);
629 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
630
43f2f104
SH		 631 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
632 gma_read16(hw, port, i);
cd28ab6a
SH		 633 gma_write16(hw, port, GM_PHY_ADDR, reg);
634
635 /* transmit control */
636 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
637
638 /* receive control reg: unicast + multicast + no FCS */
639 gma_write16(hw, port, GM_RX_CTRL,
793b883e 640 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
cd28ab6a
SH		 641
642 /* transmit flow control */
643 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
644
645 /* transmit parameter */
646 gma_write16(hw, port, GM_TX_PARAM,
647 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
648 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
649 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
650 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
651
652 /* serial mode register */
653 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
6b1a3aef 654 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
cd28ab6a 655
6b1a3aef 656 if (hw->dev[port]->mtu > ETH_DATA_LEN)
cd28ab6a
SH		 657 reg |= GM_SMOD_JUMBO_ENA;
658
659 gma_write16(hw, port, GM_SERIAL_MODE, reg);
660
cd28ab6a
SH		 661 /* virtual address for data */
662 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
663
793b883e
SH		 664 /* physical address: used for pause frames */
665 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
666
667 /* ignore counter overflows */
cd28ab6a
SH		 668 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
669 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
670 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
671
672 /* Configure Rx MAC FIFO */
673 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
70f1be48
SH		 674 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
675 GMF_OPER_ON | GMF_RX_F_FL_ON);
cd28ab6a 676
d571b694 677 /* Flush Rx MAC FIFO on any flow control or error */
42eeea01 678 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
cd28ab6a 679
793b883e
SH		 680 /* Set threshold to 0xa (64 bytes)
681 * ASF disabled so no need to do WA dev #4.30
cd28ab6a
SH		 682 */
683 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
684
685 /* Configure Tx MAC FIFO */
686 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
687 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
5a5b1ea0
SH		 688
689 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
6e532cfe 690 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8);
5a5b1ea0
SH		 691 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
692 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
693 /* set Tx GMAC FIFO Almost Empty Threshold */
694 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
695 /* Disable Store & Forward mode for TX */
696 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
697 }
698 }
699
cd28ab6a
SH		 700}
701
1c28f6ba
SH		 702/* Assign Ram Buffer allocation.
703 * start and end are in units of 4k bytes
704 * ram registers are in units of 64bit words
705 */
706static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
cd28ab6a 707{
1c28f6ba 708 u32 start, end;
cd28ab6a 709
1c28f6ba
SH		 710 start = startk * 4096/8;
711 end = (endk * 4096/8) - 1;
793b883e 712
cd28ab6a
SH		 713 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
714 sky2_write32(hw, RB_ADDR(q, RB_START), start);
715 sky2_write32(hw, RB_ADDR(q, RB_END), end);
716 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
717 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
718
719 if (q == Q_R1 || q == Q_R2) {
1c28f6ba
SH		 720 u32 space = (endk - startk) * 4096/8;
721 u32 tp = space - space/4;
793b883e 722
1c28f6ba
SH		 723 /* On receive queue's set the thresholds
724 * give receiver priority when > 3/4 full
725 * send pause when down to 2K
726 */
727 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
728 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
793b883e 729
1c28f6ba
SH		 730 tp = space - 2048/8;
731 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
732 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
cd28ab6a
SH		 733 } else {
734 /* Enable store & forward on Tx queue's because
735 * Tx FIFO is only 1K on Yukon
736 */
737 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
738 }
739
740 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
793b883e 741 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
cd28ab6a
SH		 742}
743
cd28ab6a 744/* Setup Bus Memory Interface */
af4ed7e6 745static void sky2_qset(struct sky2_hw *hw, u16 q)
cd28ab6a
SH		 746{
747 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
748 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
749 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
af4ed7e6 750 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
cd28ab6a
SH		 751}
752
cd28ab6a
SH		 753/* Setup prefetch unit registers. This is the interface between
754 * hardware and driver list elements
755 */
8cc048e3 756static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
cd28ab6a
SH		 757 u64 addr, u32 last)
758{
cd28ab6a
SH		 759 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
760 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
761 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
762 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
763 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
764 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
793b883e
SH		 765
766 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
cd28ab6a
SH		 767}
768
793b883e
SH		 769static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
770{
771 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
772
cb5d9547 773 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
291ea614 774 le->ctrl = 0;
793b883e
SH		 775 return le;
776}
cd28ab6a 777
291ea614
SH		 778static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
779 struct sky2_tx_le *le)
780{
781 return sky2->tx_ring + (le - sky2->tx_le);
782}
783
290d4de5
SH		 784/* Update chip's next pointer */
785static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
cd28ab6a 786{
98232f85 787 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
762c2de2 788 wmb();
98232f85
SH		 789 sky2_write16(hw, q, idx);
790 sky2_read16(hw, q);
cd28ab6a
SH		 791}
792
793b883e 793
cd28ab6a
SH		 794static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
795{
796 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
cb5d9547 797 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
291ea614 798 le->ctrl = 0;
cd28ab6a
SH		 799 return le;
800}
801
a018e330
SH		 802/* Return high part of DMA address (could be 32 or 64 bit) */
803static inline u32 high32(dma_addr_t a)
804{
a036119f 805 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
a018e330
SH		 806}
807
14d0263f
SH		 808/* Build description to hardware for one receive segment */
809static void sky2_rx_add(struct sky2_port *sky2, u8 op,
810 dma_addr_t map, unsigned len)
cd28ab6a
SH		 811{
812 struct sky2_rx_le *le;
734d1868 813 u32 hi = high32(map);
cd28ab6a 814
793b883e 815 if (sky2->rx_addr64 != hi) {
cd28ab6a 816 le = sky2_next_rx(sky2);
793b883e 817 le->addr = cpu_to_le32(hi);
cd28ab6a 818 le->opcode = OP_ADDR64 | HW_OWNER;
734d1868 819 sky2->rx_addr64 = high32(map + len);
cd28ab6a 820 }
793b883e 821
cd28ab6a 822 le = sky2_next_rx(sky2);
734d1868
SH		 823 le->addr = cpu_to_le32((u32) map);
824 le->length = cpu_to_le16(len);
14d0263f 825 le->opcode = op | HW_OWNER;
cd28ab6a
SH		 826}
827
14d0263f
SH		 828/* Build description to hardware for one possibly fragmented skb */
829static void sky2_rx_submit(struct sky2_port *sky2,
830 const struct rx_ring_info *re)
831{
832 int i;
833
834 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
835
836 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
837 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
838}
839
840
841static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
842 unsigned size)
843{
844 struct sk_buff *skb = re->skb;
845 int i;
846
847 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
848 pci_unmap_len_set(re, data_size, size);
849
850 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
851 re->frag_addr[i] = pci_map_page(pdev,
852 skb_shinfo(skb)->frags[i].page,
853 skb_shinfo(skb)->frags[i].page_offset,
854 skb_shinfo(skb)->frags[i].size,
855 PCI_DMA_FROMDEVICE);
856}
857
858static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
859{
860 struct sk_buff *skb = re->skb;
861 int i;
862
863 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
864 PCI_DMA_FROMDEVICE);
865
866 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
867 pci_unmap_page(pdev, re->frag_addr[i],
868 skb_shinfo(skb)->frags[i].size,
869 PCI_DMA_FROMDEVICE);
870}
793b883e 871
cd28ab6a
SH		 872/* Tell chip where to start receive checksum.
873 * Actually has two checksums, but set both same to avoid possible byte
874 * order problems.
875 */
793b883e 876static void rx_set_checksum(struct sky2_port *sky2)
cd28ab6a
SH		 877{
878 struct sky2_rx_le *le;
879
cd28ab6a 880 le = sky2_next_rx(sky2);
f65b138c 881 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
cd28ab6a
SH		 882 le->ctrl = 0;
883 le->opcode = OP_TCPSTART | HW_OWNER;
793b883e 884
793b883e
SH		 885 sky2_write32(sky2->hw,
886 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
887 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
cd28ab6a
SH		 888
889}
890
6b1a3aef
SH		 891/*
892 * The RX Stop command will not work for Yukon-2 if the BMU does not
893 * reach the end of packet and since we can't make sure that we have
894 * incoming data, we must reset the BMU while it is not doing a DMA
895 * transfer. Since it is possible that the RX path is still active,
896 * the RX RAM buffer will be stopped first, so any possible incoming
897 * data will not trigger a DMA. After the RAM buffer is stopped, the
898 * BMU is polled until any DMA in progress is ended and only then it
899 * will be reset.
900 */
901static void sky2_rx_stop(struct sky2_port *sky2)
902{
903 struct sky2_hw *hw = sky2->hw;
904 unsigned rxq = rxqaddr[sky2->port];
905 int i;
906
907 /* disable the RAM Buffer receive queue */
908 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
909
910 for (i = 0; i < 0xffff; i++)
911 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
912 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
913 goto stopped;
914
915 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
916 sky2->netdev->name);
917stopped:
918 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
919
920 /* reset the Rx prefetch unit */
921 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
922}
793b883e 923
d571b694 924/* Clean out receive buffer area, assumes receiver hardware stopped */
cd28ab6a
SH		 925static void sky2_rx_clean(struct sky2_port *sky2)
926{
927 unsigned i;
928
929 memset(sky2->rx_le, 0, RX_LE_BYTES);
793b883e 930 for (i = 0; i < sky2->rx_pending; i++) {
291ea614 931 struct rx_ring_info *re = sky2->rx_ring + i;
cd28ab6a
SH		 932
933 if (re->skb) {
14d0263f 934 sky2_rx_unmap_skb(sky2->hw->pdev, re);
cd28ab6a
SH		 935 kfree_skb(re->skb);
936 re->skb = NULL;
937 }
938 }
939}
940
ef743d33
SH		 941/* Basic MII support */
942static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
943{
944 struct mii_ioctl_data *data = if_mii(ifr);
945 struct sky2_port *sky2 = netdev_priv(dev);
946 struct sky2_hw *hw = sky2->hw;
947 int err = -EOPNOTSUPP;
948
949 if (!netif_running(dev))
950 return -ENODEV; /* Phy still in reset */
951
d89e1343 952 switch (cmd) {
ef743d33
SH		 953 case SIOCGMIIPHY:
954 data->phy_id = PHY_ADDR_MARV;
955
956 /* fallthru */
957 case SIOCGMIIREG: {
958 u16 val = 0;
91c86df5 959
e07b1aa8 960 spin_lock_bh(&sky2->phy_lock);
ef743d33 961 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
e07b1aa8 962 spin_unlock_bh(&sky2->phy_lock);
91c86df5 963
ef743d33
SH		 964 data->val_out = val;
965 break;
966 }
967
968 case SIOCSMIIREG:
969 if (!capable(CAP_NET_ADMIN))
970 return -EPERM;
971
e07b1aa8 972 spin_lock_bh(&sky2->phy_lock);
ef743d33
SH		 973 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
974 data->val_in);
e07b1aa8 975 spin_unlock_bh(&sky2->phy_lock);
ef743d33
SH		 976 break;
977 }
978 return err;
979}
980
d1f13708
SH		 981#ifdef SKY2_VLAN_TAG_USED
982static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
983{
984 struct sky2_port *sky2 = netdev_priv(dev);
985 struct sky2_hw *hw = sky2->hw;
986 u16 port = sky2->port;
d1f13708 987
2bb8c262 988 netif_tx_lock_bh(dev);
d1f13708
SH		 989
990 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
991 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
992 sky2->vlgrp = grp;
993
2bb8c262 994 netif_tx_unlock_bh(dev);
d1f13708
SH		 995}
996
997static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
998{
999 struct sky2_port *sky2 = netdev_priv(dev);
1000 struct sky2_hw *hw = sky2->hw;
1001 u16 port = sky2->port;
d1f13708 1002
2bb8c262 1003 netif_tx_lock_bh(dev);
d1f13708
SH		 1004
1005 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1006 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1007 if (sky2->vlgrp)
1008 sky2->vlgrp->vlan_devices[vid] = NULL;
1009
2bb8c262 1010 netif_tx_unlock_bh(dev);
d1f13708
SH		 1011}
1012#endif
1013
82788c7a 1014/*
14d0263f
SH		 1015 * Allocate an skb for receiving. If the MTU is large enough
1016 * make the skb non-linear with a fragment list of pages.
1017 *
82788c7a
SH		 1018 * It appears the hardware has a bug in the FIFO logic that
1019 * cause it to hang if the FIFO gets overrun and the receive buffer
497d7c86
SH		 1020 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1021 * aligned except if slab debugging is enabled.
82788c7a 1022 */
14d0263f 1023static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
82788c7a
SH		 1024{
1025 struct sk_buff *skb;
14d0263f
SH		 1026 unsigned long p;
1027 int i;
82788c7a 1028
14d0263f
SH		 1029 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1030 if (!skb)
1031 goto nomem;
1032
1033 p = (unsigned long) skb->data;
1034 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1035
1036 for (i = 0; i < sky2->rx_nfrags; i++) {
1037 struct page *page = alloc_page(GFP_ATOMIC);
1038
1039 if (!page)
1040 goto free_partial;
1041 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
82788c7a
SH		 1042 }
1043
1044 return skb;
14d0263f
SH		 1045free_partial:
1046 kfree_skb(skb);
1047nomem:
1048 return NULL;
82788c7a
SH		 1049}
1050
cd28ab6a
SH		 1051/*
1052 * Allocate and setup receiver buffer pool.
14d0263f
SH		 1053 * Normal case this ends up creating one list element for skb
1054 * in the receive ring. Worst case if using large MTU and each
1055 * allocation falls on a different 64 bit region, that results
1056 * in 6 list elements per ring entry.
1057 * One element is used for checksum enable/disable, and one
1058 * extra to avoid wrap.
cd28ab6a 1059 */
6b1a3aef 1060static int sky2_rx_start(struct sky2_port *sky2)
cd28ab6a 1061{
6b1a3aef 1062 struct sky2_hw *hw = sky2->hw;
14d0263f 1063 struct rx_ring_info *re;
6b1a3aef 1064 unsigned rxq = rxqaddr[sky2->port];
14d0263f 1065 unsigned i, size, space, thresh;
cd28ab6a 1066
6b1a3aef 1067 sky2->rx_put = sky2->rx_next = 0;
af4ed7e6 1068 sky2_qset(hw, rxq);
977bdf06
SH		 1069
1070 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
1071 /* MAC Rx RAM Read is controlled by hardware */
1072 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1073 }
1074
6b1a3aef
SH		 1075 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1076
1077 rx_set_checksum(sky2);
14d0263f
SH		 1078
1079 /* Space needed for frame data + headers rounded up */
1080 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1081 + 8;
1082
1083 /* Stopping point for hardware truncation */
1084 thresh = (size - 8) / sizeof(u32);
1085
1086 /* Account for overhead of skb - to avoid order > 0 allocation */
1087 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1088 + sizeof(struct skb_shared_info);
1089
1090 sky2->rx_nfrags = space >> PAGE_SHIFT;
1091 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1092
1093 if (sky2->rx_nfrags != 0) {
1094 /* Compute residue after pages */
1095 space = sky2->rx_nfrags << PAGE_SHIFT;
1096
1097 if (space < size)
1098 size -= space;
1099 else
1100 size = 0;
1101
1102 /* Optimize to handle small packets and headers */
1103 if (size < copybreak)
1104 size = copybreak;
1105 if (size < ETH_HLEN)
1106 size = ETH_HLEN;
1107 }
1108 sky2->rx_data_size = size;
1109
1110 /* Fill Rx ring */
793b883e 1111 for (i = 0; i < sky2->rx_pending; i++) {
14d0263f 1112 re = sky2->rx_ring + i;
cd28ab6a 1113
14d0263f 1114 re->skb = sky2_rx_alloc(sky2);
cd28ab6a
SH		 1115 if (!re->skb)
1116 goto nomem;
1117
14d0263f
SH		 1118 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1119 sky2_rx_submit(sky2, re);
cd28ab6a
SH		 1120 }
1121
a1433ac4
SH		 1122 /*
1123 * The receiver hangs if it receives frames larger than the
1124 * packet buffer. As a workaround, truncate oversize frames, but
1125 * the register is limited to 9 bits, so if you do frames > 2052
1126 * you better get the MTU right!
1127 */
a1433ac4
SH		 1128 if (thresh > 0x1ff)
1129 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1130 else {
1131 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1132 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1133 }
1134
6b1a3aef
SH		 1135 /* Tell chip about available buffers */
1136 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
cd28ab6a
SH		 1137 return 0;
1138nomem:
1139 sky2_rx_clean(sky2);
1140 return -ENOMEM;
1141}
1142
1143/* Bring up network interface. */
1144static int sky2_up(struct net_device *dev)
1145{
1146 struct sky2_port *sky2 = netdev_priv(dev);
1147 struct sky2_hw *hw = sky2->hw;
1148 unsigned port = sky2->port;
e07b1aa8 1149 u32 ramsize, rxspace, imask;
ee7abb04 1150 int cap, err = -ENOMEM;
843a46f4 1151 struct net_device *otherdev = hw->dev[sky2->port^1];
cd28ab6a 1152
ee7abb04
SH		 1153 /*
1154 * On dual port PCI-X card, there is an problem where status
1155 * can be received out of order due to split transactions
843a46f4 1156 */
ee7abb04
SH		 1157 if (otherdev && netif_running(otherdev) &&
1158 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1159 struct sky2_port *osky2 = netdev_priv(otherdev);
1160 u16 cmd;
1161
1162 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1163 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1164 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1165
1166 sky2->rx_csum = 0;
1167 osky2->rx_csum = 0;
1168 }
843a46f4 1169
cd28ab6a
SH		 1170 if (netif_msg_ifup(sky2))
1171 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1172
1173 /* must be power of 2 */
1174 sky2->tx_le = pci_alloc_consistent(hw->pdev,
793b883e
SH		 1175 TX_RING_SIZE *
1176 sizeof(struct sky2_tx_le),
cd28ab6a
SH		 1177 &sky2->tx_le_map);
1178 if (!sky2->tx_le)
1179 goto err_out;
1180
6cdbbdf3 1181 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
cd28ab6a
SH		 1182 GFP_KERNEL);
1183 if (!sky2->tx_ring)
1184 goto err_out;
1185 sky2->tx_prod = sky2->tx_cons = 0;
cd28ab6a
SH		 1186
1187 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1188 &sky2->rx_le_map);
1189 if (!sky2->rx_le)
1190 goto err_out;
1191 memset(sky2->rx_le, 0, RX_LE_BYTES);
1192
291ea614 1193 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
cd28ab6a
SH		 1194 GFP_KERNEL);
1195 if (!sky2->rx_ring)
1196 goto err_out;
1197
d3bcfbeb
SH		 1198 sky2_phy_power(hw, port, 1);
1199
cd28ab6a
SH		 1200 sky2_mac_init(hw, port);
1201
1c28f6ba
SH		 1202 /* Determine available ram buffer space (in 4K blocks).
1203 * Note: not sure about the FE setting below yet
1204 */
1205 if (hw->chip_id == CHIP_ID_YUKON_FE)
1206 ramsize = 4;
1207 else
1208 ramsize = sky2_read8(hw, B2_E_0);
1209
1210 /* Give transmitter one third (rounded up) */
1211 rxspace = ramsize - (ramsize + 2) / 3;
cd28ab6a 1212
cd28ab6a 1213 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1c28f6ba 1214 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
cd28ab6a 1215
793b883e
SH		 1216 /* Make sure SyncQ is disabled */
1217 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1218 RB_RST_SET);
1219
af4ed7e6 1220 sky2_qset(hw, txqaddr[port]);
5a5b1ea0 1221
977bdf06 1222 /* Set almost empty threshold */
c2716fb4
SH		 1223 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1224 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
977bdf06 1225 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
5a5b1ea0 1226
6b1a3aef
SH		 1227 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1228 TX_RING_SIZE - 1);
cd28ab6a 1229
6b1a3aef 1230 err = sky2_rx_start(sky2);
cd28ab6a
SH		 1231 if (err)
1232 goto err_out;
1233
cd28ab6a 1234 /* Enable interrupts from phy/mac for port */
e07b1aa8 1235 imask = sky2_read32(hw, B0_IMSK);
f4ea431b 1236 imask |= portirq_msk[port];
e07b1aa8
SH		 1237 sky2_write32(hw, B0_IMSK, imask);
1238
cd28ab6a
SH		 1239 return 0;
1240
1241err_out:
1b537565 1242 if (sky2->rx_le) {
cd28ab6a
SH		 1243 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1244 sky2->rx_le, sky2->rx_le_map);
1b537565
SH		 1245 sky2->rx_le = NULL;
1246 }
1247 if (sky2->tx_le) {
cd28ab6a
SH		 1248 pci_free_consistent(hw->pdev,
1249 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1250 sky2->tx_le, sky2->tx_le_map);
1b537565
SH		 1251 sky2->tx_le = NULL;
1252 }
1253 kfree(sky2->tx_ring);
1254 kfree(sky2->rx_ring);
cd28ab6a 1255
1b537565
SH		 1256 sky2->tx_ring = NULL;
1257 sky2->rx_ring = NULL;
cd28ab6a
SH		 1258 return err;
1259}
1260
793b883e
SH		 1261/* Modular subtraction in ring */
1262static inline int tx_dist(unsigned tail, unsigned head)
1263{
cb5d9547 1264 return (head - tail) & (TX_RING_SIZE - 1);
793b883e 1265}
cd28ab6a 1266
793b883e
SH		 1267/* Number of list elements available for next tx */
1268static inline int tx_avail(const struct sky2_port *sky2)
cd28ab6a 1269{
793b883e 1270 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
cd28ab6a
SH		 1271}
1272
793b883e 1273/* Estimate of number of transmit list elements required */
28bd181a 1274static unsigned tx_le_req(const struct sk_buff *skb)
cd28ab6a 1275{
793b883e
SH		 1276 unsigned count;
1277
1278 count = sizeof(dma_addr_t) / sizeof(u32);
1279 count += skb_shinfo(skb)->nr_frags * count;
1280
89114afd 1281 if (skb_is_gso(skb))
793b883e
SH		 1282 ++count;
1283
84fa7933 1284 if (skb->ip_summed == CHECKSUM_PARTIAL)
793b883e
SH		 1285 ++count;
1286
1287 return count;
cd28ab6a
SH		 1288}
1289
793b883e
SH		 1290/*
1291 * Put one packet in ring for transmit.
1292 * A single packet can generate multiple list elements, and
1293 * the number of ring elements will probably be less than the number
1294 * of list elements used.
1295 */
cd28ab6a
SH		 1296static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1297{
1298 struct sky2_port *sky2 = netdev_priv(dev);
1299 struct sky2_hw *hw = sky2->hw;
d1f13708 1300 struct sky2_tx_le *le = NULL;
6cdbbdf3 1301 struct tx_ring_info *re;
cd28ab6a
SH		 1302 unsigned i, len;
1303 dma_addr_t mapping;
1304 u32 addr64;
1305 u16 mss;
1306 u8 ctrl;
1307
2bb8c262
SH		 1308 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1309 return NETDEV_TX_BUSY;
cd28ab6a 1310
793b883e 1311 if (unlikely(netif_msg_tx_queued(sky2)))
cd28ab6a
SH		 1312 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1313 dev->name, sky2->tx_prod, skb->len);
1314
cd28ab6a
SH		 1315 len = skb_headlen(skb);
1316 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
a018e330 1317 addr64 = high32(mapping);
793b883e 1318
a018e330
SH		 1319 /* Send high bits if changed or crosses boundary */
1320 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
793b883e 1321 le = get_tx_le(sky2);
f65b138c 1322 le->addr = cpu_to_le32(addr64);
793b883e 1323 le->opcode = OP_ADDR64 | HW_OWNER;
a018e330 1324 sky2->tx_addr64 = high32(mapping + len);
793b883e 1325 }
cd28ab6a
SH		 1326
1327 /* Check for TCP Segmentation Offload */
7967168c 1328 mss = skb_shinfo(skb)->gso_size;
793b883e 1329 if (mss != 0) {
cd28ab6a
SH		 1330 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1331 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1332 mss += ETH_HLEN;
1333
e07560cd
SH		 1334 if (mss != sky2->tx_last_mss) {
1335 le = get_tx_le(sky2);
f65b138c 1336 le->addr = cpu_to_le32(mss);
e07560cd 1337 le->opcode = OP_LRGLEN | HW_OWNER;
e07560cd
SH		 1338 sky2->tx_last_mss = mss;
1339 }
cd28ab6a
SH		 1340 }
1341
cd28ab6a 1342 ctrl = 0;
d1f13708
SH		 1343#ifdef SKY2_VLAN_TAG_USED
1344 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1345 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1346 if (!le) {
1347 le = get_tx_le(sky2);
f65b138c 1348 le->addr = 0;
d1f13708 1349 le->opcode = OP_VLAN|HW_OWNER;
d1f13708
SH		 1350 } else
1351 le->opcode |= OP_VLAN;
1352 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1353 ctrl |= INS_VLAN;
1354 }
1355#endif
1356
1357 /* Handle TCP checksum offload */
84fa7933 1358 if (skb->ip_summed == CHECKSUM_PARTIAL) {
f65b138c
SH		 1359 unsigned offset = skb->h.raw - skb->data;
1360 u32 tcpsum;
1361
1362 tcpsum = offset << 16; /* sum start */
1363 tcpsum |= offset + skb->csum; /* sum write */
cd28ab6a
SH		 1364
1365 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1366 if (skb->nh.iph->protocol == IPPROTO_UDP)
1367 ctrl |= UDPTCP;
1368
f65b138c
SH		 1369 if (tcpsum != sky2->tx_tcpsum) {
1370 sky2->tx_tcpsum = tcpsum;
1d179332
SH		 1371
1372 le = get_tx_le(sky2);
f65b138c 1373 le->addr = cpu_to_le32(tcpsum);
1d179332
SH		 1374 le->length = 0; /* initial checksum value */
1375 le->ctrl = 1; /* one packet */
1376 le->opcode = OP_TCPLISW | HW_OWNER;
1377 }
cd28ab6a
SH		 1378 }
1379
1380 le = get_tx_le(sky2);
f65b138c 1381 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1382 le->length = cpu_to_le16(len);
1383 le->ctrl = ctrl;
793b883e 1384 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
cd28ab6a 1385
291ea614 1386 re = tx_le_re(sky2, le);
cd28ab6a 1387 re->skb = skb;
6cdbbdf3 1388 pci_unmap_addr_set(re, mapaddr, mapping);
291ea614 1389 pci_unmap_len_set(re, maplen, len);
cd28ab6a
SH		 1390
1391 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
291ea614 1392 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
cd28ab6a
SH		 1393
1394 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1395 frag->size, PCI_DMA_TODEVICE);
a036119f 1396 addr64 = high32(mapping);
793b883e
SH		 1397 if (addr64 != sky2->tx_addr64) {
1398 le = get_tx_le(sky2);
f65b138c 1399 le->addr = cpu_to_le32(addr64);
793b883e
SH		 1400 le->ctrl = 0;
1401 le->opcode = OP_ADDR64 | HW_OWNER;
1402 sky2->tx_addr64 = addr64;
cd28ab6a
SH		 1403 }
1404
1405 le = get_tx_le(sky2);
f65b138c 1406 le->addr = cpu_to_le32((u32) mapping);
cd28ab6a
SH		 1407 le->length = cpu_to_le16(frag->size);
1408 le->ctrl = ctrl;
793b883e 1409 le->opcode = OP_BUFFER | HW_OWNER;
cd28ab6a 1410
291ea614
SH		 1411 re = tx_le_re(sky2, le);
1412 re->skb = skb;
1413 pci_unmap_addr_set(re, mapaddr, mapping);
1414 pci_unmap_len_set(re, maplen, frag->size);
cd28ab6a 1415 }
6cdbbdf3 1416
cd28ab6a
SH		 1417 le->ctrl |= EOP;
1418
97bda706
SH		 1419 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1420 netif_stop_queue(dev);
b19666d9 1421
290d4de5 1422 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
cd28ab6a 1423
cd28ab6a
SH		 1424 dev->trans_start = jiffies;
1425 return NETDEV_TX_OK;
1426}
1427
cd28ab6a 1428/*
793b883e
SH		 1429 * Free ring elements from starting at tx_cons until "done"
1430 *
1431 * NB: the hardware will tell us about partial completion of multi-part
291ea614 1432 * buffers so make sure not to free skb to early.
cd28ab6a 1433 */
d11c13e7 1434static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
cd28ab6a 1435{
d11c13e7 1436 struct net_device *dev = sky2->netdev;
af2a58ac 1437 struct pci_dev *pdev = sky2->hw->pdev;
291ea614 1438 unsigned idx;
cd28ab6a 1439
0e3ff6aa 1440 BUG_ON(done >= TX_RING_SIZE);
2224795d 1441
291ea614
SH		 1442 for (idx = sky2->tx_cons; idx != done;
1443 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1444 struct sky2_tx_le *le = sky2->tx_le + idx;
1445 struct tx_ring_info *re = sky2->tx_ring + idx;
1446
1447 switch(le->opcode & ~HW_OWNER) {
1448 case OP_LARGESEND:
1449 case OP_PACKET:
1450 pci_unmap_single(pdev,
1451 pci_unmap_addr(re, mapaddr),
1452 pci_unmap_len(re, maplen),
1453 PCI_DMA_TODEVICE);
af2a58ac 1454 break;
291ea614
SH		 1455 case OP_BUFFER:
1456 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1457 pci_unmap_len(re, maplen),
734d1868 1458 PCI_DMA_TODEVICE);
291ea614
SH		 1459 break;
1460 }
1461
1462 if (le->ctrl & EOP) {
1463 if (unlikely(netif_msg_tx_done(sky2)))
1464 printk(KERN_DEBUG "%s: tx done %u\n",
1465 dev->name, idx);
1466 dev_kfree_skb(re->skb);
cd28ab6a
SH		 1467 }
1468
291ea614 1469 le->opcode = 0; /* paranoia */
793b883e 1470 }
793b883e 1471
291ea614 1472 sky2->tx_cons = idx;
22e11703 1473 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
cd28ab6a 1474 netif_wake_queue(dev);
cd28ab6a
SH		 1475}
1476
1477/* Cleanup all untransmitted buffers, assume transmitter not running */
2bb8c262 1478static void sky2_tx_clean(struct net_device *dev)
cd28ab6a 1479{
2bb8c262
SH		 1480 struct sky2_port *sky2 = netdev_priv(dev);
1481
1482 netif_tx_lock_bh(dev);
d11c13e7 1483 sky2_tx_complete(sky2, sky2->tx_prod);
2bb8c262 1484 netif_tx_unlock_bh(dev);
cd28ab6a
SH		 1485}
1486
1487/* Network shutdown */
1488static int sky2_down(struct net_device *dev)
1489{
1490 struct sky2_port *sky2 = netdev_priv(dev);
1491 struct sky2_hw *hw = sky2->hw;
1492 unsigned port = sky2->port;
1493 u16 ctrl;
e07b1aa8 1494 u32 imask;
cd28ab6a 1495
1b537565
SH		 1496 /* Never really got started! */
1497 if (!sky2->tx_le)
1498 return 0;
1499
cd28ab6a
SH		 1500 if (netif_msg_ifdown(sky2))
1501 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1502
018d1c66 1503 /* Stop more packets from being queued */
cd28ab6a
SH		 1504 netif_stop_queue(dev);
1505
ebc646f6
SH		 1506 /* Disable port IRQ */
1507 imask = sky2_read32(hw, B0_IMSK);
1508 imask &= ~portirq_msk[port];
1509 sky2_write32(hw, B0_IMSK, imask);
1510
d3bcfbeb 1511 sky2_gmac_reset(hw, port);
793b883e 1512
cd28ab6a
SH		 1513 /* Stop transmitter */
1514 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1515 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1516
1517 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
793b883e 1518 RB_RST_SET | RB_DIS_OP_MD);
cd28ab6a 1519
c2716fb4
SH		 1520 /* WA for dev. #4.209 */
1521 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1522 && hw->chip_rev == CHIP_REV_YU_EC_U_A1)
1523 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1524 sky2->speed != SPEED_1000 ?
1525 TX_STFW_ENA : TX_STFW_DIS);
1526
cd28ab6a 1527 ctrl = gma_read16(hw, port, GM_GP_CTRL);
793b883e 1528 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
cd28ab6a
SH		 1529 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1530
1531 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1532
1533 /* Workaround shared GMAC reset */
793b883e
SH		 1534 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1535 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
cd28ab6a
SH		 1536 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1537
1538 /* Disable Force Sync bit and Enable Alloc bit */
1539 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1540 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1541
1542 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1543 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1544 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1545
1546 /* Reset the PCI FIFO of the async Tx queue */
793b883e
SH		 1547 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1548 BMU_RST_SET | BMU_FIFO_RST);
cd28ab6a
SH		 1549
1550 /* Reset the Tx prefetch units */
1551 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1552 PREF_UNIT_RST_SET);
1553
1554 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1555
6b1a3aef 1556 sky2_rx_stop(sky2);
cd28ab6a
SH		 1557
1558 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1559 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1560
d3bcfbeb
SH		 1561 sky2_phy_power(hw, port, 0);
1562
d571b694 1563 /* turn off LED's */
cd28ab6a
SH		 1564 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1565
018d1c66
SH		 1566 synchronize_irq(hw->pdev->irq);
1567
2bb8c262 1568 sky2_tx_clean(dev);
cd28ab6a
SH		 1569 sky2_rx_clean(sky2);
1570
1571 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1572 sky2->rx_le, sky2->rx_le_map);
1573 kfree(sky2->rx_ring);
1574
1575 pci_free_consistent(hw->pdev,
1576 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1577 sky2->tx_le, sky2->tx_le_map);
1578 kfree(sky2->tx_ring);
1579
1b537565
SH		 1580 sky2->tx_le = NULL;
1581 sky2->rx_le = NULL;
1582
1583 sky2->rx_ring = NULL;
1584 sky2->tx_ring = NULL;
1585
cd28ab6a
SH		 1586 return 0;
1587}
1588
1589static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1590{
b89165f2 1591 if (!sky2_is_copper(hw))
793b883e
SH		 1592 return SPEED_1000;
1593
cd28ab6a
SH		 1594 if (hw->chip_id == CHIP_ID_YUKON_FE)
1595 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1596
1597 switch (aux & PHY_M_PS_SPEED_MSK) {
1598 case PHY_M_PS_SPEED_1000:
1599 return SPEED_1000;
1600 case PHY_M_PS_SPEED_100:
1601 return SPEED_100;
1602 default:
1603 return SPEED_10;
1604 }
1605}
1606
1607static void sky2_link_up(struct sky2_port *sky2)
1608{
1609 struct sky2_hw *hw = sky2->hw;
1610 unsigned port = sky2->port;
1611 u16 reg;
16ad91e1
SH		 1612 static const char *fc_name[] = {
1613 [FC_NONE] = "none",
1614 [FC_TX] = "tx",
1615 [FC_RX] = "rx",
1616 [FC_BOTH] = "both",
1617 };
cd28ab6a 1618
cd28ab6a 1619 /* enable Rx/Tx */
2eaba1a2 1620 reg = gma_read16(hw, port, GM_GP_CTRL);
cd28ab6a
SH		 1621 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1622 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a
SH		 1623
1624 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1625
1626 netif_carrier_on(sky2->netdev);
1627 netif_wake_queue(sky2->netdev);
1628
1629 /* Turn on link LED */
793b883e 1630 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
cd28ab6a
SH		 1631 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1632
ed6d32c7 1633 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
793b883e 1634 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
ed6d32c7
SH		 1635 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1636
1637 switch(sky2->speed) {
1638 case SPEED_10:
1639 led |= PHY_M_LEDC_INIT_CTRL(7);
1640 break;
1641
1642 case SPEED_100:
1643 led |= PHY_M_LEDC_STA1_CTRL(7);
1644 break;
1645
1646 case SPEED_1000:
1647 led |= PHY_M_LEDC_STA0_CTRL(7);
1648 break;
1649 }
793b883e
SH		 1650
1651 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
ed6d32c7 1652 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
793b883e
SH		 1653 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1654 }
1655
cd28ab6a
SH		 1656 if (netif_msg_link(sky2))
1657 printk(KERN_INFO PFX
d571b694 1658 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
cd28ab6a
SH		 1659 sky2->netdev->name, sky2->speed,
1660 sky2->duplex == DUPLEX_FULL ? "full" : "half",
16ad91e1 1661 fc_name[sky2->flow_status]);
cd28ab6a
SH		 1662}
1663
1664static void sky2_link_down(struct sky2_port *sky2)
1665{
1666 struct sky2_hw *hw = sky2->hw;
1667 unsigned port = sky2->port;
1668 u16 reg;
1669
1670 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1671
1672 reg = gma_read16(hw, port, GM_GP_CTRL);
1673 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1674 gma_write16(hw, port, GM_GP_CTRL, reg);
cd28ab6a 1675
16ad91e1 1676 if (sky2->flow_status == FC_RX) {
cd28ab6a
SH		 1677 /* restore Asymmetric Pause bit */
1678 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
793b883e
SH		 1679 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1680 | PHY_M_AN_ASP);
cd28ab6a
SH		 1681 }
1682
cd28ab6a
SH		 1683 netif_carrier_off(sky2->netdev);
1684 netif_stop_queue(sky2->netdev);
1685
1686 /* Turn on link LED */
1687 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1688
1689 if (netif_msg_link(sky2))
1690 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2eaba1a2 1691
cd28ab6a
SH		 1692 sky2_phy_init(hw, port);
1693}
1694
16ad91e1
SH		 1695static enum flow_control sky2_flow(int rx, int tx)
1696{
1697 if (rx)
1698 return tx ? FC_BOTH : FC_RX;
1699 else
1700 return tx ? FC_TX : FC_NONE;
1701}
1702
793b883e
SH		 1703static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1704{
1705 struct sky2_hw *hw = sky2->hw;
1706 unsigned port = sky2->port;
1707 u16 lpa;
1708
1709 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1710
1711 if (lpa & PHY_M_AN_RF) {
1712 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1713 return -1;
1714 }
1715
793b883e
SH		 1716 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1717 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1718 sky2->netdev->name);
1719 return -1;
1720 }
1721
793b883e 1722 sky2->speed = sky2_phy_speed(hw, aux);
7c74ac1c 1723 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
793b883e
SH		 1724
1725 /* Pause bits are offset (9..8) */
ed6d32c7 1726 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
793b883e
SH		 1727 aux >>= 6;
1728
16ad91e1
SH		 1729 sky2->flow_status = sky2_flow(aux & PHY_M_PS_RX_P_EN,
1730 aux & PHY_M_PS_TX_P_EN);
793b883e 1731
16ad91e1 1732 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
2eaba1a2 1733 && hw->chip_id != CHIP_ID_YUKON_EC_U)
16ad91e1 1734 sky2->flow_status = FC_NONE;
2eaba1a2 1735
16ad91e1 1736 if (aux & PHY_M_PS_RX_P_EN)
793b883e
SH		 1737 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1738 else
1739 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1740
1741 return 0;
1742}
cd28ab6a 1743
e07b1aa8
SH		 1744/* Interrupt from PHY */
1745static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
cd28ab6a 1746{
e07b1aa8
SH		 1747 struct net_device *dev = hw->dev[port];
1748 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 1749 u16 istatus, phystat;
1750
ebc646f6
SH		 1751 if (!netif_running(dev))
1752 return;
1753
e07b1aa8
SH		 1754 spin_lock(&sky2->phy_lock);
1755 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1756 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1757
cd28ab6a
SH		 1758 if (netif_msg_intr(sky2))
1759 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1760 sky2->netdev->name, istatus, phystat);
1761
2eaba1a2 1762 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
793b883e
SH		 1763 if (sky2_autoneg_done(sky2, phystat) == 0)
1764 sky2_link_up(sky2);
1765 goto out;
1766 }
cd28ab6a 1767
793b883e
SH		 1768 if (istatus & PHY_M_IS_LSP_CHANGE)
1769 sky2->speed = sky2_phy_speed(hw, phystat);
cd28ab6a 1770
793b883e
SH		 1771 if (istatus & PHY_M_IS_DUP_CHANGE)
1772 sky2->duplex =
1773 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
cd28ab6a 1774
793b883e
SH		 1775 if (istatus & PHY_M_IS_LST_CHANGE) {
1776 if (phystat & PHY_M_PS_LINK_UP)
cd28ab6a 1777 sky2_link_up(sky2);
793b883e
SH		 1778 else
1779 sky2_link_down(sky2);
cd28ab6a 1780 }
793b883e 1781out:
e07b1aa8 1782 spin_unlock(&sky2->phy_lock);
cd28ab6a
SH		 1783}
1784
302d1252
SH		 1785
1786/* Transmit timeout is only called if we are running, carries is up
1787 * and tx queue is full (stopped).
1788 */
cd28ab6a
SH		 1789static void sky2_tx_timeout(struct net_device *dev)
1790{
1791 struct sky2_port *sky2 = netdev_priv(dev);
8cc048e3
SH		 1792 struct sky2_hw *hw = sky2->hw;
1793 unsigned txq = txqaddr[sky2->port];
8f24664d 1794 u16 report, done;
cd28ab6a
SH		 1795
1796 if (netif_msg_timer(sky2))
1797 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1798
8f24664d
SH		 1799 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1800 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
cd28ab6a 1801
8f24664d
SH		 1802 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1803 dev->name,
1804 sky2->tx_cons, sky2->tx_prod, report, done);
1805
1806 if (report != done) {
1807 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1808
1809 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1810 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1811 } else if (report != sky2->tx_cons) {
1812 printk(KERN_INFO PFX "status report lost?\n");
1813
2bb8c262 1814 netif_tx_lock_bh(dev);
8f24664d 1815 sky2_tx_complete(sky2, report);
2bb8c262 1816 netif_tx_unlock_bh(dev);
8f24664d
SH		 1817 } else {
1818 printk(KERN_INFO PFX "hardware hung? flushing\n");
8cc048e3 1819
8f24664d
SH		 1820 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1821 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1822
2bb8c262 1823 sky2_tx_clean(dev);
8f24664d
SH		 1824
1825 sky2_qset(hw, txq);
1826 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1827 }
cd28ab6a
SH		 1828}
1829
1830static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1831{
6b1a3aef
SH		 1832 struct sky2_port *sky2 = netdev_priv(dev);
1833 struct sky2_hw *hw = sky2->hw;
1834 int err;
1835 u16 ctl, mode;
e07b1aa8 1836 u32 imask;
cd28ab6a
SH		 1837
1838 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1839 return -EINVAL;
1840
5a5b1ea0
SH		 1841 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1842 return -EINVAL;
1843
6b1a3aef
SH		 1844 if (!netif_running(dev)) {
1845 dev->mtu = new_mtu;
1846 return 0;
1847 }
1848
e07b1aa8 1849 imask = sky2_read32(hw, B0_IMSK);
6b1a3aef
SH		 1850 sky2_write32(hw, B0_IMSK, 0);
1851
018d1c66
SH		 1852 dev->trans_start = jiffies; /* prevent tx timeout */
1853 netif_stop_queue(dev);
1854 netif_poll_disable(hw->dev[0]);
1855
e07b1aa8
SH		 1856 synchronize_irq(hw->pdev->irq);
1857
6b1a3aef
SH		 1858 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1859 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1860 sky2_rx_stop(sky2);
1861 sky2_rx_clean(sky2);
cd28ab6a
SH		 1862
1863 dev->mtu = new_mtu;
14d0263f 1864
6b1a3aef
SH		 1865 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1866 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1867
1868 if (dev->mtu > ETH_DATA_LEN)
1869 mode |= GM_SMOD_JUMBO_ENA;
1870
1871 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
cd28ab6a 1872
6b1a3aef 1873 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
cd28ab6a 1874
6b1a3aef 1875 err = sky2_rx_start(sky2);
e07b1aa8 1876 sky2_write32(hw, B0_IMSK, imask);
018d1c66 1877
1b537565
SH		 1878 if (err)
1879 dev_close(dev);
1880 else {
1881 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1882
1883 netif_poll_enable(hw->dev[0]);
1884 netif_wake_queue(dev);
1885 }
1886
cd28ab6a
SH		 1887 return err;
1888}
1889
14d0263f
SH		 1890/* For small just reuse existing skb for next receive */
1891static struct sk_buff *receive_copy(struct sky2_port *sky2,
1892 const struct rx_ring_info *re,
1893 unsigned length)
1894{
1895 struct sk_buff *skb;
1896
1897 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1898 if (likely(skb)) {
1899 skb_reserve(skb, 2);
1900 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1901 length, PCI_DMA_FROMDEVICE);
1902 memcpy(skb->data, re->skb->data, length);
1903 skb->ip_summed = re->skb->ip_summed;
1904 skb->csum = re->skb->csum;
1905 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1906 length, PCI_DMA_FROMDEVICE);
1907 re->skb->ip_summed = CHECKSUM_NONE;
489b10c1 1908 skb_put(skb, length);
14d0263f
SH		 1909 }
1910 return skb;
1911}
1912
1913/* Adjust length of skb with fragments to match received data */
1914static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1915 unsigned int length)
1916{
1917 int i, num_frags;
1918 unsigned int size;
1919
1920 /* put header into skb */
1921 size = min(length, hdr_space);
1922 skb->tail += size;
1923 skb->len += size;
1924 length -= size;
1925
1926 num_frags = skb_shinfo(skb)->nr_frags;
1927 for (i = 0; i < num_frags; i++) {
1928 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1929
1930 if (length == 0) {
1931 /* don't need this page */
1932 __free_page(frag->page);
1933 --skb_shinfo(skb)->nr_frags;
1934 } else {
1935 size = min(length, (unsigned) PAGE_SIZE);
1936
1937 frag->size = size;
1938 skb->data_len += size;
1939 skb->truesize += size;
1940 skb->len += size;
1941 length -= size;
1942 }
1943 }
1944}
1945
1946/* Normal packet - take skb from ring element and put in a new one */
1947static struct sk_buff *receive_new(struct sky2_port *sky2,
1948 struct rx_ring_info *re,
1949 unsigned int length)
1950{
1951 struct sk_buff *skb, *nskb;
1952 unsigned hdr_space = sky2->rx_data_size;
1953
1954 pr_debug(PFX "receive new length=%d\n", length);
1955
1956 /* Don't be tricky about reusing pages (yet) */
1957 nskb = sky2_rx_alloc(sky2);
1958 if (unlikely(!nskb))
1959 return NULL;
1960
1961 skb = re->skb;
1962 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1963
1964 prefetch(skb->data);
1965 re->skb = nskb;
1966 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
1967
1968 if (skb_shinfo(skb)->nr_frags)
1969 skb_put_frags(skb, hdr_space, length);
1970 else
489b10c1 1971 skb_put(skb, length);
14d0263f
SH		 1972 return skb;
1973}
1974
cd28ab6a
SH		 1975/*
1976 * Receive one packet.
d571b694 1977 * For larger packets, get new buffer.
cd28ab6a 1978 */
497d7c86 1979static struct sk_buff *sky2_receive(struct net_device *dev,
cd28ab6a
SH		 1980 u16 length, u32 status)
1981{
497d7c86 1982 struct sky2_port *sky2 = netdev_priv(dev);
291ea614 1983 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
79e57d32 1984 struct sk_buff *skb = NULL;
cd28ab6a
SH		 1985
1986 if (unlikely(netif_msg_rx_status(sky2)))
1987 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
497d7c86 1988 dev->name, sky2->rx_next, status, length);
cd28ab6a 1989
793b883e 1990 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
d70cd51a 1991 prefetch(sky2->rx_ring + sky2->rx_next);
cd28ab6a 1992
42eeea01 1993 if (status & GMR_FS_ANY_ERR)
cd28ab6a
SH		 1994 goto error;
1995
42eeea01
SH		 1996 if (!(status & GMR_FS_RX_OK))
1997 goto resubmit;
1998
497d7c86 1999 if (length > dev->mtu + ETH_HLEN)
6e15b712
SH		 2000 goto oversize;
2001
14d0263f
SH		 2002 if (length < copybreak)
2003 skb = receive_copy(sky2, re, length);
2004 else
2005 skb = receive_new(sky2, re, length);
793b883e 2006resubmit:
14d0263f 2007 sky2_rx_submit(sky2, re);
79e57d32 2008
cd28ab6a
SH		 2009 return skb;
2010
6e15b712
SH		 2011oversize:
2012 ++sky2->net_stats.rx_over_errors;
2013 goto resubmit;
2014
cd28ab6a 2015error:
6e15b712
SH		 2016 ++sky2->net_stats.rx_errors;
2017
3be92a70 2018 if (netif_msg_rx_err(sky2) && net_ratelimit())
cd28ab6a 2019 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
497d7c86 2020 dev->name, status, length);
793b883e
SH		 2021
2022 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
cd28ab6a
SH		 2023 sky2->net_stats.rx_length_errors++;
2024 if (status & GMR_FS_FRAGMENT)
2025 sky2->net_stats.rx_frame_errors++;
2026 if (status & GMR_FS_CRC_ERR)
2027 sky2->net_stats.rx_crc_errors++;
793b883e
SH		 2028 if (status & GMR_FS_RX_FF_OV)
2029 sky2->net_stats.rx_fifo_errors++;
79e57d32 2030
793b883e 2031 goto resubmit;
cd28ab6a
SH		 2032}
2033
e07b1aa8
SH		 2034/* Transmit complete */
2035static inline void sky2_tx_done(struct net_device *dev, u16 last)
13b97b74 2036{
e07b1aa8 2037 struct sky2_port *sky2 = netdev_priv(dev);
302d1252 2038
e07b1aa8 2039 if (netif_running(dev)) {
2bb8c262 2040 netif_tx_lock(dev);
e07b1aa8 2041 sky2_tx_complete(sky2, last);
2bb8c262 2042 netif_tx_unlock(dev);
2224795d 2043 }
cd28ab6a
SH		 2044}
2045
e07b1aa8
SH		 2046/* Process status response ring */
2047static int sky2_status_intr(struct sky2_hw *hw, int to_do)
cd28ab6a 2048{
22e11703 2049 struct sky2_port *sky2;
e07b1aa8 2050 int work_done = 0;
22e11703 2051 unsigned buf_write[2] = { 0, 0 };
e71ebd73 2052 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
a8fd6266 2053
af2a58ac 2054 rmb();
bea86103 2055
e71ebd73 2056 while (hw->st_idx != hwidx) {
13210ce5
SH		 2057 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2058 struct net_device *dev;
cd28ab6a 2059 struct sk_buff *skb;
cd28ab6a
SH		 2060 u32 status;
2061 u16 length;
2062
cb5d9547 2063 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
bea86103 2064
e71ebd73
SH		 2065 BUG_ON(le->link >= 2);
2066 dev = hw->dev[le->link];
13210ce5
SH		 2067
2068 sky2 = netdev_priv(dev);
f65b138c
SH		 2069 length = le16_to_cpu(le->length);
2070 status = le32_to_cpu(le->status);
cd28ab6a 2071
e71ebd73 2072 switch (le->opcode & ~HW_OWNER) {
cd28ab6a 2073 case OP_RXSTAT:
497d7c86 2074 skb = sky2_receive(dev, length, status);
d1f13708
SH		 2075 if (!skb)
2076 break;
13210ce5 2077
13210ce5
SH		 2078 skb->protocol = eth_type_trans(skb, dev);
2079 dev->last_rx = jiffies;
2080
d1f13708
SH		 2081#ifdef SKY2_VLAN_TAG_USED
2082 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2083 vlan_hwaccel_receive_skb(skb,
2084 sky2->vlgrp,
2085 be16_to_cpu(sky2->rx_tag));
2086 } else
2087#endif
cd28ab6a 2088 netif_receive_skb(skb);
13210ce5 2089
22e11703
SH		 2090 /* Update receiver after 16 frames */
2091 if (++buf_write[le->link] == RX_BUF_WRITE) {
2092 sky2_put_idx(hw, rxqaddr[le->link],
2093 sky2->rx_put);
2094 buf_write[le->link] = 0;
2095 }
2096
2097 /* Stop after net poll weight */
13210ce5
SH		 2098 if (++work_done >= to_do)
2099 goto exit_loop;
cd28ab6a
SH		 2100 break;
2101
d1f13708
SH		 2102#ifdef SKY2_VLAN_TAG_USED
2103 case OP_RXVLAN:
2104 sky2->rx_tag = length;
2105 break;
2106
2107 case OP_RXCHKSVLAN:
2108 sky2->rx_tag = length;
2109 /* fall through */
2110#endif
cd28ab6a 2111 case OP_RXCHKS:
d11c13e7 2112 skb = sky2->rx_ring[sky2->rx_next].skb;
84fa7933 2113 skb->ip_summed = CHECKSUM_COMPLETE;
f65b138c 2114 skb->csum = status & 0xffff;
cd28ab6a
SH		 2115 break;
2116
2117 case OP_TXINDEXLE:
13b97b74 2118 /* TX index reports status for both ports */
f55925d7
SH		 2119 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2120 sky2_tx_done(hw->dev[0], status & 0xfff);
e07b1aa8
SH		 2121 if (hw->dev[1])
2122 sky2_tx_done(hw->dev[1],
2123 ((status >> 24) & 0xff)
2124 | (u16)(length & 0xf) << 8);
cd28ab6a
SH		 2125 break;
2126
cd28ab6a
SH		 2127 default:
2128 if (net_ratelimit())
793b883e 2129 printk(KERN_WARNING PFX
e71ebd73
SH		 2130 "unknown status opcode 0x%x\n", le->opcode);
2131 goto exit_loop;
cd28ab6a 2132 }
13210ce5 2133 }
cd28ab6a 2134
fe2a24df
SH		 2135 /* Fully processed status ring so clear irq */
2136 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2137
13210ce5 2138exit_loop:
22e11703
SH		 2139 if (buf_write[0]) {
2140 sky2 = netdev_priv(hw->dev[0]);
2141 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2142 }
2143
2144 if (buf_write[1]) {
2145 sky2 = netdev_priv(hw->dev[1]);
2146 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2147 }
2148
e07b1aa8 2149 return work_done;
cd28ab6a
SH		 2150}
2151
2152static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2153{
2154 struct net_device *dev = hw->dev[port];
2155
3be92a70
SH		 2156 if (net_ratelimit())
2157 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2158 dev->name, status);
cd28ab6a
SH		 2159
2160 if (status & Y2_IS_PAR_RD1) {
3be92a70
SH		 2161 if (net_ratelimit())
2162 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2163 dev->name);
cd28ab6a
SH		 2164 /* Clear IRQ */
2165 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2166 }
2167
2168 if (status & Y2_IS_PAR_WR1) {
3be92a70
SH		 2169 if (net_ratelimit())
2170 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2171 dev->name);
cd28ab6a
SH		 2172
2173 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2174 }
2175
2176 if (status & Y2_IS_PAR_MAC1) {
3be92a70
SH		 2177 if (net_ratelimit())
2178 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
cd28ab6a
SH		 2179 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2180 }
2181
2182 if (status & Y2_IS_PAR_RX1) {
3be92a70
SH		 2183 if (net_ratelimit())
2184 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
cd28ab6a
SH		 2185 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2186 }
2187
2188 if (status & Y2_IS_TCP_TXA1) {
3be92a70
SH		 2189 if (net_ratelimit())
2190 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2191 dev->name);
cd28ab6a
SH		 2192 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2193 }
2194}
2195
2196static void sky2_hw_intr(struct sky2_hw *hw)
2197{
2198 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2199
793b883e 2200 if (status & Y2_IS_TIST_OV)
cd28ab6a 2201 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2202
2203 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
793b883e
SH		 2204 u16 pci_err;
2205
56a645cc 2206 pci_err = sky2_pci_read16(hw, PCI_STATUS);
3be92a70
SH		 2207 if (net_ratelimit())
2208 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2209 pci_name(hw->pdev), pci_err);
cd28ab6a
SH		 2210
2211 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc 2212 sky2_pci_write16(hw, PCI_STATUS,
91aeb3ed 2213 pci_err | PCI_STATUS_ERROR_BITS);
cd28ab6a
SH		 2214 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2215 }
2216
2217 if (status & Y2_IS_PCI_EXP) {
d571b694 2218 /* PCI-Express uncorrectable Error occurred */
793b883e
SH		 2219 u32 pex_err;
2220
7bd656d1 2221 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
cd28ab6a 2222
3be92a70
SH		 2223 if (net_ratelimit())
2224 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2225 pci_name(hw->pdev), pex_err);
cd28ab6a
SH		 2226
2227 /* clear the interrupt */
2228 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
7bd656d1
SH		 2229 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2230 0xffffffffUL);
cd28ab6a
SH		 2231 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2232
7bd656d1 2233 if (pex_err & PEX_FATAL_ERRORS) {
cd28ab6a
SH		 2234 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2235 hwmsk &= ~Y2_IS_PCI_EXP;
2236 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2237 }
2238 }
2239
2240 if (status & Y2_HWE_L1_MASK)
2241 sky2_hw_error(hw, 0, status);
2242 status >>= 8;
2243 if (status & Y2_HWE_L1_MASK)
2244 sky2_hw_error(hw, 1, status);
2245}
2246
2247static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2248{
2249 struct net_device *dev = hw->dev[port];
2250 struct sky2_port *sky2 = netdev_priv(dev);
2251 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2252
2253 if (netif_msg_intr(sky2))
2254 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2255 dev->name, status);
2256
2257 if (status & GM_IS_RX_FF_OR) {
2258 ++sky2->net_stats.rx_fifo_errors;
2259 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2260 }
2261
2262 if (status & GM_IS_TX_FF_UR) {
2263 ++sky2->net_stats.tx_fifo_errors;
2264 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2265 }
cd28ab6a
SH		 2266}
2267
d257924e
SH		 2268/* This should never happen it is a fatal situation */
2269static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2270 const char *rxtx, u32 mask)
2271{
2272 struct net_device *dev = hw->dev[port];
2273 struct sky2_port *sky2 = netdev_priv(dev);
2274 u32 imask;
2275
2276 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2277 dev ? dev->name : "<not registered>", rxtx);
2278
2279 imask = sky2_read32(hw, B0_IMSK);
2280 imask &= ~mask;
2281 sky2_write32(hw, B0_IMSK, imask);
2282
2283 if (dev) {
2284 spin_lock(&sky2->phy_lock);
2285 sky2_link_down(sky2);
2286 spin_unlock(&sky2->phy_lock);
2287 }
2288}
cd28ab6a 2289
d27ed387
SH		 2290/* If idle then force a fake soft NAPI poll once a second
2291 * to work around cases where sharing an edge triggered interrupt.
2292 */
eb35cf60
SH		 2293static inline void sky2_idle_start(struct sky2_hw *hw)
2294{
2295 if (idle_timeout > 0)
2296 mod_timer(&hw->idle_timer,
2297 jiffies + msecs_to_jiffies(idle_timeout));
2298}
2299
d27ed387
SH		 2300static void sky2_idle(unsigned long arg)
2301{
01bd7564
SH		 2302 struct sky2_hw *hw = (struct sky2_hw *) arg;
2303 struct net_device *dev = hw->dev[0];
d27ed387 2304
d27ed387
SH		 2305 if (__netif_rx_schedule_prep(dev))
2306 __netif_rx_schedule(dev);
01bd7564
SH		 2307
2308 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
d27ed387
SH		 2309}
2310
2311
e07b1aa8 2312static int sky2_poll(struct net_device *dev0, int *budget)
cd28ab6a 2313{
e07b1aa8
SH		 2314 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2315 int work_limit = min(dev0->quota, *budget);
2316 int work_done = 0;
fb2690a9 2317 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
cd28ab6a 2318
1e5f1283
SH		 2319 if (status & Y2_IS_HW_ERR)
2320 sky2_hw_intr(hw);
d257924e 2321
1e5f1283
SH		 2322 if (status & Y2_IS_IRQ_PHY1)
2323 sky2_phy_intr(hw, 0);
cd28ab6a 2324
1e5f1283
SH		 2325 if (status & Y2_IS_IRQ_PHY2)
2326 sky2_phy_intr(hw, 1);
cd28ab6a 2327
1e5f1283
SH		 2328 if (status & Y2_IS_IRQ_MAC1)
2329 sky2_mac_intr(hw, 0);
cd28ab6a 2330
1e5f1283
SH		 2331 if (status & Y2_IS_IRQ_MAC2)
2332 sky2_mac_intr(hw, 1);
cd28ab6a 2333
1e5f1283
SH		 2334 if (status & Y2_IS_CHK_RX1)
2335 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
d257924e 2336
1e5f1283
SH		 2337 if (status & Y2_IS_CHK_RX2)
2338 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
d257924e 2339
1e5f1283
SH		 2340 if (status & Y2_IS_CHK_TXA1)
2341 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
d257924e 2342
1e5f1283
SH		 2343 if (status & Y2_IS_CHK_TXA2)
2344 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
cd28ab6a 2345
1e5f1283 2346 work_done = sky2_status_intr(hw, work_limit);
fe2a24df
SH		 2347 if (work_done < work_limit) {
2348 netif_rx_complete(dev0);
86fba634 2349
fe2a24df
SH		 2350 sky2_read32(hw, B0_Y2_SP_LISR);
2351 return 0;
2352 } else {
2353 *budget -= work_done;
2354 dev0->quota -= work_done;
1e5f1283 2355 return 1;
fe2a24df 2356 }
e07b1aa8
SH		 2357}
2358
7d12e780 2359static irqreturn_t sky2_intr(int irq, void *dev_id)
e07b1aa8
SH		 2360{
2361 struct sky2_hw *hw = dev_id;
2362 struct net_device *dev0 = hw->dev[0];
2363 u32 status;
2364
2365 /* Reading this mask interrupts as side effect */
2366 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2367 if (status == 0 || status == ~0)
2368 return IRQ_NONE;
793b883e 2369
e07b1aa8
SH		 2370 prefetch(&hw->st_le[hw->st_idx]);
2371 if (likely(__netif_rx_schedule_prep(dev0)))
2372 __netif_rx_schedule(dev0);
793b883e 2373
cd28ab6a
SH		 2374 return IRQ_HANDLED;
2375}
2376
2377#ifdef CONFIG_NET_POLL_CONTROLLER
2378static void sky2_netpoll(struct net_device *dev)
2379{
2380 struct sky2_port *sky2 = netdev_priv(dev);
88d11360 2381 struct net_device *dev0 = sky2->hw->dev[0];
cd28ab6a 2382
88d11360
SH		 2383 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2384 __netif_rx_schedule(dev0);
cd28ab6a
SH		 2385}
2386#endif
2387
2388/* Chip internal frequency for clock calculations */
fb17358f 2389static inline u32 sky2_mhz(const struct sky2_hw *hw)
cd28ab6a 2390{
793b883e 2391 switch (hw->chip_id) {
cd28ab6a 2392 case CHIP_ID_YUKON_EC:
5a5b1ea0 2393 case CHIP_ID_YUKON_EC_U:
fb17358f 2394 return 125; /* 125 Mhz */
cd28ab6a 2395 case CHIP_ID_YUKON_FE:
fb17358f 2396 return 100; /* 100 Mhz */
793b883e 2397 default: /* YUKON_XL */
fb17358f 2398 return 156; /* 156 Mhz */
cd28ab6a
SH		 2399 }
2400}
2401
fb17358f 2402static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
cd28ab6a 2403{
fb17358f 2404 return sky2_mhz(hw) * us;
cd28ab6a
SH		 2405}
2406
fb17358f 2407static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
cd28ab6a 2408{
fb17358f 2409 return clk / sky2_mhz(hw);
cd28ab6a
SH		 2410}
2411
fb17358f 2412
59139528 2413static int sky2_reset(struct sky2_hw *hw)
cd28ab6a 2414{
cd28ab6a 2415 u16 status;
b89165f2 2416 u8 t8;
56a645cc 2417 int i;
cd28ab6a 2418
cd28ab6a 2419 sky2_write8(hw, B0_CTST, CS_RST_CLR);
08c06d8a 2420
cd28ab6a
SH		 2421 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2422 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2423 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2424 pci_name(hw->pdev), hw->chip_id);
2425 return -EOPNOTSUPP;
2426 }
2427
290d4de5
SH		 2428 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2429
2430 /* This rev is really old, and requires untested workarounds */
2431 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2432 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2433 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2434 hw->chip_id, hw->chip_rev);
2435 return -EOPNOTSUPP;
2436 }
2437
cd28ab6a
SH		 2438 /* disable ASF */
2439 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2440 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2441 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2442 }
2443
2444 /* do a SW reset */
2445 sky2_write8(hw, B0_CTST, CS_RST_SET);
2446 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2447
2448 /* clear PCI errors, if any */
56a645cc 2449 status = sky2_pci_read16(hw, PCI_STATUS);
2d42d21f 2450
cd28ab6a 2451 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
56a645cc
SH		 2452 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2453
cd28ab6a
SH		 2454
2455 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2456
2457 /* clear any PEX errors */
7bd656d1
SH		 2458 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2459 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2460
cd28ab6a 2461
b89165f2 2462 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
cd28ab6a
SH		 2463 hw->ports = 1;
2464 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2465 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2466 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2467 ++hw->ports;
2468 }
cd28ab6a 2469
5afa0a9c 2470 sky2_set_power_state(hw, PCI_D0);
cd28ab6a
SH		 2471
2472 for (i = 0; i < hw->ports; i++) {
2473 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2474 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2475 }
2476
2477 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2478
793b883e
SH		 2479 /* Clear I2C IRQ noise */
2480 sky2_write32(hw, B2_I2C_IRQ, 1);
cd28ab6a
SH		 2481
2482 /* turn off hardware timer (unused) */
2483 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2484 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
793b883e 2485
cd28ab6a
SH		 2486 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2487
69634ee7
SH		 2488 /* Turn off descriptor polling */
2489 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
cd28ab6a
SH		 2490
2491 /* Turn off receive timestamp */
2492 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
793b883e 2493 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
cd28ab6a
SH		 2494
2495 /* enable the Tx Arbiters */
2496 for (i = 0; i < hw->ports; i++)
2497 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2498
2499 /* Initialize ram interface */
2500 for (i = 0; i < hw->ports; i++) {
793b883e 2501 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
cd28ab6a
SH		 2502
2503 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2504 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2505 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2506 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2507 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2508 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2509 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2510 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2511 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2512 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2513 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2514 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2515 }
2516
7bd656d1 2517 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
cd28ab6a 2518
cd28ab6a 2519 for (i = 0; i < hw->ports; i++)
d3bcfbeb 2520 sky2_gmac_reset(hw, i);
cd28ab6a 2521
cd28ab6a
SH		 2522 memset(hw->st_le, 0, STATUS_LE_BYTES);
2523 hw->st_idx = 0;
2524
2525 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2526 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2527
2528 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
793b883e 2529 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
cd28ab6a
SH		 2530
2531 /* Set the list last index */
793b883e 2532 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
cd28ab6a 2533
290d4de5
SH		 2534 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2535 sky2_write8(hw, STAT_FIFO_WM, 16);
cd28ab6a 2536
290d4de5
SH		 2537 /* set Status-FIFO ISR watermark */
2538 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2539 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2540 else
2541 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
cd28ab6a 2542
290d4de5 2543 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
77b3d6a2
SH		 2544 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2545 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
cd28ab6a 2546
793b883e 2547 /* enable status unit */
cd28ab6a
SH		 2548 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2549
2550 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2551 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2552 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2553
2554 return 0;
2555}
2556
28bd181a 2557static u32 sky2_supported_modes(const struct sky2_hw *hw)
cd28ab6a 2558{
b89165f2
SH		 2559 if (sky2_is_copper(hw)) {
2560 u32 modes = SUPPORTED_10baseT_Half
2561 | SUPPORTED_10baseT_Full
2562 | SUPPORTED_100baseT_Half
2563 | SUPPORTED_100baseT_Full
2564 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a
SH		 2565
2566 if (hw->chip_id != CHIP_ID_YUKON_FE)
2567 modes |= SUPPORTED_1000baseT_Half
b89165f2
SH		 2568 | SUPPORTED_1000baseT_Full;
2569 return modes;
cd28ab6a 2570 } else
b89165f2
SH		 2571 return SUPPORTED_1000baseT_Half
2572 | SUPPORTED_1000baseT_Full
2573 | SUPPORTED_Autoneg
2574 | SUPPORTED_FIBRE;
cd28ab6a
SH		 2575}
2576
793b883e 2577static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
cd28ab6a
SH		 2578{
2579 struct sky2_port *sky2 = netdev_priv(dev);
2580 struct sky2_hw *hw = sky2->hw;
2581
2582 ecmd->transceiver = XCVR_INTERNAL;
2583 ecmd->supported = sky2_supported_modes(hw);
2584 ecmd->phy_address = PHY_ADDR_MARV;
b89165f2 2585 if (sky2_is_copper(hw)) {
cd28ab6a 2586 ecmd->supported = SUPPORTED_10baseT_Half
793b883e
SH		 2587 | SUPPORTED_10baseT_Full
2588 | SUPPORTED_100baseT_Half
2589 | SUPPORTED_100baseT_Full
2590 | SUPPORTED_1000baseT_Half
2591 | SUPPORTED_1000baseT_Full
2592 | SUPPORTED_Autoneg | SUPPORTED_TP;
cd28ab6a 2593 ecmd->port = PORT_TP;
b89165f2
SH		 2594 ecmd->speed = sky2->speed;
2595 } else {
2596 ecmd->speed = SPEED_1000;
cd28ab6a 2597 ecmd->port = PORT_FIBRE;
b89165f2 2598 }
cd28ab6a
SH		 2599
2600 ecmd->advertising = sky2->advertising;
2601 ecmd->autoneg = sky2->autoneg;
cd28ab6a
SH		 2602 ecmd->duplex = sky2->duplex;
2603 return 0;
2604}
2605
2606static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2607{
2608 struct sky2_port *sky2 = netdev_priv(dev);
2609 const struct sky2_hw *hw = sky2->hw;
2610 u32 supported = sky2_supported_modes(hw);
2611
2612 if (ecmd->autoneg == AUTONEG_ENABLE) {
2613 ecmd->advertising = supported;
2614 sky2->duplex = -1;
2615 sky2->speed = -1;
2616 } else {
2617 u32 setting;
2618
793b883e 2619 switch (ecmd->speed) {
cd28ab6a
SH		 2620 case SPEED_1000:
2621 if (ecmd->duplex == DUPLEX_FULL)
2622 setting = SUPPORTED_1000baseT_Full;
2623 else if (ecmd->duplex == DUPLEX_HALF)
2624 setting = SUPPORTED_1000baseT_Half;
2625 else
2626 return -EINVAL;
2627 break;
2628 case SPEED_100:
2629 if (ecmd->duplex == DUPLEX_FULL)
2630 setting = SUPPORTED_100baseT_Full;
2631 else if (ecmd->duplex == DUPLEX_HALF)
2632 setting = SUPPORTED_100baseT_Half;
2633 else
2634 return -EINVAL;
2635 break;
2636
2637 case SPEED_10:
2638 if (ecmd->duplex == DUPLEX_FULL)
2639 setting = SUPPORTED_10baseT_Full;
2640 else if (ecmd->duplex == DUPLEX_HALF)
2641 setting = SUPPORTED_10baseT_Half;
2642 else
2643 return -EINVAL;
2644 break;
2645 default:
2646 return -EINVAL;
2647 }
2648
2649 if ((setting & supported) == 0)
2650 return -EINVAL;
2651
2652 sky2->speed = ecmd->speed;
2653 sky2->duplex = ecmd->duplex;
2654 }
2655
2656 sky2->autoneg = ecmd->autoneg;
2657 sky2->advertising = ecmd->advertising;
2658
1b537565
SH		 2659 if (netif_running(dev))
2660 sky2_phy_reinit(sky2);
cd28ab6a
SH		 2661
2662 return 0;
2663}
2664
2665static void sky2_get_drvinfo(struct net_device *dev,
2666 struct ethtool_drvinfo *info)
2667{
2668 struct sky2_port *sky2 = netdev_priv(dev);
2669
2670 strcpy(info->driver, DRV_NAME);
2671 strcpy(info->version, DRV_VERSION);
2672 strcpy(info->fw_version, "N/A");
2673 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2674}
2675
2676static const struct sky2_stat {
793b883e
SH		 2677 char name[ETH_GSTRING_LEN];
2678 u16 offset;
cd28ab6a
SH		 2679} sky2_stats[] = {
2680 { "tx_bytes", GM_TXO_OK_HI },
2681 { "rx_bytes", GM_RXO_OK_HI },
2682 { "tx_broadcast", GM_TXF_BC_OK },
2683 { "rx_broadcast", GM_RXF_BC_OK },
2684 { "tx_multicast", GM_TXF_MC_OK },
2685 { "rx_multicast", GM_RXF_MC_OK },
2686 { "tx_unicast", GM_TXF_UC_OK },
2687 { "rx_unicast", GM_RXF_UC_OK },
2688 { "tx_mac_pause", GM_TXF_MPAUSE },
2689 { "rx_mac_pause", GM_RXF_MPAUSE },
eadfa7dd 2690 { "collisions", GM_TXF_COL },
cd28ab6a
SH		 2691 { "late_collision",GM_TXF_LAT_COL },
2692 { "aborted", GM_TXF_ABO_COL },
eadfa7dd 2693 { "single_collisions", GM_TXF_SNG_COL },
cd28ab6a 2694 { "multi_collisions", GM_TXF_MUL_COL },
eadfa7dd 2695
d2604540 2696 { "rx_short", GM_RXF_SHT },
cd28ab6a 2697 { "rx_runt", GM_RXE_FRAG },
eadfa7dd
SH		 2698 { "rx_64_byte_packets", GM_RXF_64B },
2699 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2700 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2701 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2702 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2703 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2704 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
cd28ab6a 2705 { "rx_too_long", GM_RXF_LNG_ERR },
eadfa7dd
SH		 2706 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2707 { "rx_jabber", GM_RXF_JAB_PKT },
cd28ab6a 2708 { "rx_fcs_error", GM_RXF_FCS_ERR },
eadfa7dd
SH		 2709
2710 { "tx_64_byte_packets", GM_TXF_64B },
2711 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2712 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2713 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2714 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2715 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2716 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2717 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
cd28ab6a
SH		 2718};
2719
cd28ab6a
SH		 2720static u32 sky2_get_rx_csum(struct net_device *dev)
2721{
2722 struct sky2_port *sky2 = netdev_priv(dev);
2723
2724 return sky2->rx_csum;
2725}
2726
2727static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2728{
2729 struct sky2_port *sky2 = netdev_priv(dev);
2730
2731 sky2->rx_csum = data;
793b883e 2732
cd28ab6a
SH		 2733 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2734 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2735
2736 return 0;
2737}
2738
2739static u32 sky2_get_msglevel(struct net_device *netdev)
2740{
2741 struct sky2_port *sky2 = netdev_priv(netdev);
2742 return sky2->msg_enable;
2743}
2744
9a7ae0a9
SH		 2745static int sky2_nway_reset(struct net_device *dev)
2746{
2747 struct sky2_port *sky2 = netdev_priv(dev);
9a7ae0a9 2748
16ad91e1 2749 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
9a7ae0a9
SH		 2750 return -EINVAL;
2751
1b537565 2752 sky2_phy_reinit(sky2);
9a7ae0a9
SH		 2753
2754 return 0;
2755}
2756
793b883e 2757static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
cd28ab6a
SH		 2758{
2759 struct sky2_hw *hw = sky2->hw;
2760 unsigned port = sky2->port;
2761 int i;
2762
2763 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
793b883e 2764 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
cd28ab6a 2765 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
793b883e 2766 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
cd28ab6a 2767
793b883e 2768 for (i = 2; i < count; i++)
cd28ab6a
SH		 2769 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2770}
2771
cd28ab6a
SH		 2772static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2773{
2774 struct sky2_port *sky2 = netdev_priv(netdev);
2775 sky2->msg_enable = value;
2776}
2777
2778static int sky2_get_stats_count(struct net_device *dev)
2779{
2780 return ARRAY_SIZE(sky2_stats);
2781}
2782
2783static void sky2_get_ethtool_stats(struct net_device *dev,
793b883e 2784 struct ethtool_stats *stats, u64 * data)
cd28ab6a
SH		 2785{
2786 struct sky2_port *sky2 = netdev_priv(dev);
2787
793b883e 2788 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
cd28ab6a
SH		 2789}
2790
793b883e 2791static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
cd28ab6a
SH		 2792{
2793 int i;
2794
2795 switch (stringset) {
2796 case ETH_SS_STATS:
2797 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2798 memcpy(data + i * ETH_GSTRING_LEN,
2799 sky2_stats[i].name, ETH_GSTRING_LEN);
2800 break;
2801 }
2802}
2803
2804/* Use hardware MIB variables for critical path statistics and
2805 * transmit feedback not reported at interrupt.
2806 * Other errors are accounted for in interrupt handler.
2807 */
2808static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2809{
2810 struct sky2_port *sky2 = netdev_priv(dev);
793b883e 2811 u64 data[13];
cd28ab6a 2812
793b883e 2813 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
cd28ab6a
SH		 2814
2815 sky2->net_stats.tx_bytes = data[0];
2816 sky2->net_stats.rx_bytes = data[1];
2817 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2818 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
050ff180 2819 sky2->net_stats.multicast = data[3] + data[5];
cd28ab6a
SH		 2820 sky2->net_stats.collisions = data[10];
2821 sky2->net_stats.tx_aborted_errors = data[12];
2822
2823 return &sky2->net_stats;
2824}
2825
2826static int sky2_set_mac_address(struct net_device *dev, void *p)
2827{
2828 struct sky2_port *sky2 = netdev_priv(dev);
a8ab1ec0
SH		 2829 struct sky2_hw *hw = sky2->hw;
2830 unsigned port = sky2->port;
2831 const struct sockaddr *addr = p;
cd28ab6a
SH		 2832
2833 if (!is_valid_ether_addr(addr->sa_data))
2834 return -EADDRNOTAVAIL;
2835
cd28ab6a 2836 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
a8ab1ec0 2837 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
cd28ab6a 2838 dev->dev_addr, ETH_ALEN);
a8ab1ec0 2839 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
cd28ab6a 2840 dev->dev_addr, ETH_ALEN);
1b537565 2841
a8ab1ec0
SH		 2842 /* virtual address for data */
2843 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2844
2845 /* physical address: used for pause frames */
2846 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
1b537565
SH		 2847
2848 return 0;
cd28ab6a
SH		 2849}
2850
2851static void sky2_set_multicast(struct net_device *dev)
2852{
2853 struct sky2_port *sky2 = netdev_priv(dev);
2854 struct sky2_hw *hw = sky2->hw;
2855 unsigned port = sky2->port;
2856 struct dev_mc_list *list = dev->mc_list;
2857 u16 reg;
2858 u8 filter[8];
2859
2860 memset(filter, 0, sizeof(filter));
2861
2862 reg = gma_read16(hw, port, GM_RX_CTRL);
2863 reg |= GM_RXCR_UCF_ENA;
2864
d571b694 2865 if (dev->flags & IFF_PROMISC) /* promiscuous */
cd28ab6a 2866 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
793b883e 2867 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
cd28ab6a 2868 memset(filter, 0xff, sizeof(filter));
793b883e 2869 else if (dev->mc_count == 0) /* no multicast */
cd28ab6a
SH		 2870 reg &= ~GM_RXCR_MCF_ENA;
2871 else {
2872 int i;
2873 reg |= GM_RXCR_MCF_ENA;
2874
2875 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2876 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
793b883e 2877 filter[bit / 8] |= 1 << (bit % 8);
cd28ab6a
SH		 2878 }
2879 }
2880
cd28ab6a 2881 gma_write16(hw, port, GM_MC_ADDR_H1,
793b883e 2882 (u16) filter[0] | ((u16) filter[1] << 8));
cd28ab6a 2883 gma_write16(hw, port, GM_MC_ADDR_H2,
793b883e 2884 (u16) filter[2] | ((u16) filter[3] << 8));
cd28ab6a 2885 gma_write16(hw, port, GM_MC_ADDR_H3,
793b883e 2886 (u16) filter[4] | ((u16) filter[5] << 8));
cd28ab6a 2887 gma_write16(hw, port, GM_MC_ADDR_H4,
793b883e 2888 (u16) filter[6] | ((u16) filter[7] << 8));
cd28ab6a
SH		 2889
2890 gma_write16(hw, port, GM_RX_CTRL, reg);
2891}
2892
2893/* Can have one global because blinking is controlled by
2894 * ethtool and that is always under RTNL mutex
2895 */
91c86df5 2896static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
cd28ab6a 2897{
793b883e
SH		 2898 u16 pg;
2899
793b883e
SH		 2900 switch (hw->chip_id) {
2901 case CHIP_ID_YUKON_XL:
2902 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2903 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2904 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2905 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2906 PHY_M_LEDC_INIT_CTRL(7) |
2907 PHY_M_LEDC_STA1_CTRL(7) |
2908 PHY_M_LEDC_STA0_CTRL(7))
2909 : 0);
2910
2911 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2912 break;
2913
2914 default:
2915 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
cd28ab6a 2916 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
793b883e
SH		 2917 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2918 PHY_M_LED_MO_10(MO_LED_ON) |
2919 PHY_M_LED_MO_100(MO_LED_ON) |
cd28ab6a 2920 PHY_M_LED_MO_1000(MO_LED_ON) |
793b883e
SH		 2921 PHY_M_LED_MO_RX(MO_LED_ON)
2922 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2923 PHY_M_LED_MO_10(MO_LED_OFF) |
2924 PHY_M_LED_MO_100(MO_LED_OFF) |
cd28ab6a
SH		 2925 PHY_M_LED_MO_1000(MO_LED_OFF) |
2926 PHY_M_LED_MO_RX(MO_LED_OFF));
2927
793b883e 2928 }
cd28ab6a
SH		 2929}
2930
2931/* blink LED's for finding board */
2932static int sky2_phys_id(struct net_device *dev, u32 data)
2933{
2934 struct sky2_port *sky2 = netdev_priv(dev);
2935 struct sky2_hw *hw = sky2->hw;
2936 unsigned port = sky2->port;
793b883e 2937 u16 ledctrl, ledover = 0;
cd28ab6a 2938 long ms;
91c86df5 2939 int interrupted;
cd28ab6a
SH		 2940 int onoff = 1;
2941
793b883e 2942 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
cd28ab6a
SH		 2943 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2944 else
2945 ms = data * 1000;
2946
2947 /* save initial values */
e07b1aa8 2948 spin_lock_bh(&sky2->phy_lock);
793b883e
SH		 2949 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2950 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2951 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2952 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2953 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2954 } else {
2955 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2956 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2957 }
cd28ab6a 2958
91c86df5
SH		 2959 interrupted = 0;
2960 while (!interrupted && ms > 0) {
cd28ab6a
SH		 2961 sky2_led(hw, port, onoff);
2962 onoff = !onoff;
2963
e07b1aa8 2964 spin_unlock_bh(&sky2->phy_lock);
91c86df5 2965 interrupted = msleep_interruptible(250);
e07b1aa8 2966 spin_lock_bh(&sky2->phy_lock);
91c86df5 2967
cd28ab6a
SH		 2968 ms -= 250;
2969 }
2970
2971 /* resume regularly scheduled programming */
793b883e
SH		 2972 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2973 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2974 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2975 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2976 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2977 } else {
2978 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2979 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2980 }
e07b1aa8 2981 spin_unlock_bh(&sky2->phy_lock);
cd28ab6a
SH		 2982
2983 return 0;
2984}
2985
2986static void sky2_get_pauseparam(struct net_device *dev,
2987 struct ethtool_pauseparam *ecmd)
2988{
2989 struct sky2_port *sky2 = netdev_priv(dev);
2990
16ad91e1
SH		 2991 switch (sky2->flow_mode) {
2992 case FC_NONE:
2993 ecmd->tx_pause = ecmd->rx_pause = 0;
2994 break;
2995 case FC_TX:
2996 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
2997 break;
2998 case FC_RX:
2999 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3000 break;
3001 case FC_BOTH:
3002 ecmd->tx_pause = ecmd->rx_pause = 1;
3003 }
3004
cd28ab6a
SH		 3005 ecmd->autoneg = sky2->autoneg;
3006}
3007
3008static int sky2_set_pauseparam(struct net_device *dev,
3009 struct ethtool_pauseparam *ecmd)
3010{
3011 struct sky2_port *sky2 = netdev_priv(dev);
cd28ab6a
SH		 3012
3013 sky2->autoneg = ecmd->autoneg;
16ad91e1 3014 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
cd28ab6a 3015
16ad91e1
SH		 3016 if (netif_running(dev))
3017 sky2_phy_reinit(sky2);
cd28ab6a 3018
2eaba1a2 3019 return 0;
cd28ab6a
SH		 3020}
3021
fb17358f
SH		 3022static int sky2_get_coalesce(struct net_device *dev,
3023 struct ethtool_coalesce *ecmd)
3024{
3025 struct sky2_port *sky2 = netdev_priv(dev);
3026 struct sky2_hw *hw = sky2->hw;
3027
3028 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3029 ecmd->tx_coalesce_usecs = 0;
3030 else {
3031 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3032 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3033 }
3034 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3035
3036 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3037 ecmd->rx_coalesce_usecs = 0;
3038 else {
3039 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3040 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3041 }
3042 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3043
3044 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3045 ecmd->rx_coalesce_usecs_irq = 0;
3046 else {
3047 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3048 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3049 }
3050
3051 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3052
3053 return 0;
3054}
3055
3056/* Note: this affect both ports */
3057static int sky2_set_coalesce(struct net_device *dev,
3058 struct ethtool_coalesce *ecmd)
3059{
3060 struct sky2_port *sky2 = netdev_priv(dev);
3061 struct sky2_hw *hw = sky2->hw;
77b3d6a2 3062 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
fb17358f 3063
77b3d6a2
SH		 3064 if (ecmd->tx_coalesce_usecs > tmax ||
3065 ecmd->rx_coalesce_usecs > tmax ||
3066 ecmd->rx_coalesce_usecs_irq > tmax)
fb17358f
SH		 3067 return -EINVAL;
3068
ff81fbbe 3069 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
fb17358f 3070 return -EINVAL;
ff81fbbe 3071 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
fb17358f 3072 return -EINVAL;
ff81fbbe 3073 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
fb17358f
SH		 3074 return -EINVAL;
3075
3076 if (ecmd->tx_coalesce_usecs == 0)
3077 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3078 else {
3079 sky2_write32(hw, STAT_TX_TIMER_INI,
3080 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3081 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3082 }
3083 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3084
3085 if (ecmd->rx_coalesce_usecs == 0)
3086 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3087 else {
3088 sky2_write32(hw, STAT_LEV_TIMER_INI,
3089 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3090 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3091 }
3092 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3093
3094 if (ecmd->rx_coalesce_usecs_irq == 0)
3095 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3096 else {
d28d4870 3097 sky2_write32(hw, STAT_ISR_TIMER_INI,
fb17358f
SH		 3098 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3099 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3100 }
3101 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3102 return 0;
3103}
3104
793b883e
SH		 3105static void sky2_get_ringparam(struct net_device *dev,
3106 struct ethtool_ringparam *ering)
3107{
3108 struct sky2_port *sky2 = netdev_priv(dev);
3109
3110 ering->rx_max_pending = RX_MAX_PENDING;
3111 ering->rx_mini_max_pending = 0;
3112 ering->rx_jumbo_max_pending = 0;
3113 ering->tx_max_pending = TX_RING_SIZE - 1;
3114
3115 ering->rx_pending = sky2->rx_pending;
3116 ering->rx_mini_pending = 0;
3117 ering->rx_jumbo_pending = 0;
3118 ering->tx_pending = sky2->tx_pending;
3119}
3120
3121static int sky2_set_ringparam(struct net_device *dev,
3122 struct ethtool_ringparam *ering)
3123{
3124 struct sky2_port *sky2 = netdev_priv(dev);
3125 int err = 0;
3126
3127 if (ering->rx_pending > RX_MAX_PENDING ||
3128 ering->rx_pending < 8 ||
3129 ering->tx_pending < MAX_SKB_TX_LE ||
3130 ering->tx_pending > TX_RING_SIZE - 1)
3131 return -EINVAL;
3132
3133 if (netif_running(dev))
3134 sky2_down(dev);
3135
3136 sky2->rx_pending = ering->rx_pending;
3137 sky2->tx_pending = ering->tx_pending;
3138
1b537565 3139 if (netif_running(dev)) {
793b883e 3140 err = sky2_up(dev);
1b537565
SH		 3141 if (err)
3142 dev_close(dev);
6ed995bb
SH		 3143 else
3144 sky2_set_multicast(dev);
1b537565 3145 }
793b883e
SH		 3146
3147 return err;
3148}
3149
793b883e
SH		 3150static int sky2_get_regs_len(struct net_device *dev)
3151{
6e4cbb34 3152 return 0x4000;
793b883e
SH		 3153}
3154
3155/*
3156 * Returns copy of control register region
6e4cbb34 3157 * Note: access to the RAM address register set will cause timeouts.
793b883e
SH		 3158 */
3159static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3160 void *p)
3161{
3162 const struct sky2_port *sky2 = netdev_priv(dev);
793b883e 3163 const void __iomem *io = sky2->hw->regs;
793b883e 3164
6e4cbb34 3165 BUG_ON(regs->len < B3_RI_WTO_R1);
793b883e 3166 regs->version = 1;
6e4cbb34 3167 memset(p, 0, regs->len);
793b883e 3168
6e4cbb34
SH		 3169 memcpy_fromio(p, io, B3_RAM_ADDR);
3170
3171 memcpy_fromio(p + B3_RI_WTO_R1,
3172 io + B3_RI_WTO_R1,
3173 regs->len - B3_RI_WTO_R1);
793b883e 3174}
cd28ab6a 3175
7282d491 3176static const struct ethtool_ops sky2_ethtool_ops = {
793b883e
SH		 3177 .get_settings = sky2_get_settings,
3178 .set_settings = sky2_set_settings,
3179 .get_drvinfo = sky2_get_drvinfo,
3180 .get_msglevel = sky2_get_msglevel,
3181 .set_msglevel = sky2_set_msglevel,
9a7ae0a9 3182 .nway_reset = sky2_nway_reset,
793b883e
SH		 3183 .get_regs_len = sky2_get_regs_len,
3184 .get_regs = sky2_get_regs,
3185 .get_link = ethtool_op_get_link,
3186 .get_sg = ethtool_op_get_sg,
3187 .set_sg = ethtool_op_set_sg,
3188 .get_tx_csum = ethtool_op_get_tx_csum,
3189 .set_tx_csum = ethtool_op_set_tx_csum,
3190 .get_tso = ethtool_op_get_tso,
3191 .set_tso = ethtool_op_set_tso,
3192 .get_rx_csum = sky2_get_rx_csum,
3193 .set_rx_csum = sky2_set_rx_csum,
3194 .get_strings = sky2_get_strings,
fb17358f
SH		 3195 .get_coalesce = sky2_get_coalesce,
3196 .set_coalesce = sky2_set_coalesce,
793b883e
SH		 3197 .get_ringparam = sky2_get_ringparam,
3198 .set_ringparam = sky2_set_ringparam,
cd28ab6a
SH		 3199 .get_pauseparam = sky2_get_pauseparam,
3200 .set_pauseparam = sky2_set_pauseparam,
793b883e 3201 .phys_id = sky2_phys_id,
cd28ab6a
SH		 3202 .get_stats_count = sky2_get_stats_count,
3203 .get_ethtool_stats = sky2_get_ethtool_stats,
2995bfb7 3204 .get_perm_addr = ethtool_op_get_perm_addr,
cd28ab6a
SH		 3205};
3206
3207/* Initialize network device */
3208static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3209 unsigned port, int highmem)
3210{
3211 struct sky2_port *sky2;
3212 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3213
3214 if (!dev) {
3215 printk(KERN_ERR "sky2 etherdev alloc failed");
3216 return NULL;
3217 }
3218
3219 SET_MODULE_OWNER(dev);
3220 SET_NETDEV_DEV(dev, &hw->pdev->dev);
ef743d33 3221 dev->irq = hw->pdev->irq;
cd28ab6a
SH		 3222 dev->open = sky2_up;
3223 dev->stop = sky2_down;
ef743d33 3224 dev->do_ioctl = sky2_ioctl;
cd28ab6a
SH		 3225 dev->hard_start_xmit = sky2_xmit_frame;
3226 dev->get_stats = sky2_get_stats;
3227 dev->set_multicast_list = sky2_set_multicast;
3228 dev->set_mac_address = sky2_set_mac_address;
3229 dev->change_mtu = sky2_change_mtu;
3230 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3231 dev->tx_timeout = sky2_tx_timeout;
3232 dev->watchdog_timeo = TX_WATCHDOG;
3233 if (port == 0)
3234 dev->poll = sky2_poll;
3235 dev->weight = NAPI_WEIGHT;
3236#ifdef CONFIG_NET_POLL_CONTROLLER
3237 dev->poll_controller = sky2_netpoll;
3238#endif
cd28ab6a
SH		 3239
3240 sky2 = netdev_priv(dev);
3241 sky2->netdev = dev;
3242 sky2->hw = hw;
3243 sky2->msg_enable = netif_msg_init(debug, default_msg);
3244
cd28ab6a
SH		 3245 /* Auto speed and flow control */
3246 sky2->autoneg = AUTONEG_ENABLE;
16ad91e1
SH		 3247 sky2->flow_mode = FC_BOTH;
3248
cd28ab6a
SH		 3249 sky2->duplex = -1;
3250 sky2->speed = -1;
3251 sky2->advertising = sky2_supported_modes(hw);
ee7abb04 3252 sky2->rx_csum = 1;
75d070c5 3253
e07b1aa8 3254 spin_lock_init(&sky2->phy_lock);
793b883e 3255 sky2->tx_pending = TX_DEF_PENDING;
290d4de5 3256 sky2->rx_pending = RX_DEF_PENDING;
cd28ab6a
SH		 3257
3258 hw->dev[port] = dev;
3259
3260 sky2->port = port;
3261
5a5b1ea0
SH		 3262 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3263 dev->features |= NETIF_F_TSO;
cd28ab6a
SH		 3264 if (highmem)
3265 dev->features |= NETIF_F_HIGHDMA;
793b883e 3266 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
cd28ab6a 3267
d1f13708
SH		 3268#ifdef SKY2_VLAN_TAG_USED
3269 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3270 dev->vlan_rx_register = sky2_vlan_rx_register;
3271 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3272#endif
3273
cd28ab6a 3274 /* read the mac address */
793b883e 3275 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2995bfb7 3276 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
cd28ab6a
SH		 3277
3278 /* device is off until link detection */
3279 netif_carrier_off(dev);
3280 netif_stop_queue(dev);
3281
3282 return dev;
3283}
3284
28bd181a 3285static void __devinit sky2_show_addr(struct net_device *dev)
cd28ab6a
SH		 3286{
3287 const struct sky2_port *sky2 = netdev_priv(dev);
3288
3289 if (netif_msg_probe(sky2))
3290 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3291 dev->name,
3292 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3293 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3294}
3295
fb2690a9 3296/* Handle software interrupt used during MSI test */
7d12e780 3297static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
fb2690a9
SH		 3298{
3299 struct sky2_hw *hw = dev_id;
3300 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3301
3302 if (status == 0)
3303 return IRQ_NONE;
3304
3305 if (status & Y2_IS_IRQ_SW) {
3306 hw->msi_detected = 1;
3307 wake_up(&hw->msi_wait);
3308 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3309 }
3310 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3311
3312 return IRQ_HANDLED;
3313}
3314
3315/* Test interrupt path by forcing a a software IRQ */
3316static int __devinit sky2_test_msi(struct sky2_hw *hw)
3317{
3318 struct pci_dev *pdev = hw->pdev;
3319 int err;
3320
bb507fe1
SH		 3321 init_waitqueue_head (&hw->msi_wait);
3322
fb2690a9
SH		 3323 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3324
1fb9df5d 3325 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
fb2690a9
SH		 3326 if (err) {
3327 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3328 pci_name(pdev), pdev->irq);
3329 return err;
3330 }
3331
fb2690a9 3332 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
bb507fe1 3333 sky2_read8(hw, B0_CTST);
fb2690a9
SH		 3334
3335 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3336
3337 if (!hw->msi_detected) {
3338 /* MSI test failed, go back to INTx mode */
2bffc23a
SH		 3339 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3340 "switching to INTx mode.\n",
fb2690a9
SH		 3341 pci_name(pdev));
3342
3343 err = -EOPNOTSUPP;
3344 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3345 }
3346
3347 sky2_write32(hw, B0_IMSK, 0);
2bffc23a 3348 sky2_read32(hw, B0_IMSK);
fb2690a9
SH		 3349
3350 free_irq(pdev->irq, hw);
3351
3352 return err;
3353}
3354
cd28ab6a
SH		 3355static int __devinit sky2_probe(struct pci_dev *pdev,
3356 const struct pci_device_id *ent)
3357{
793b883e 3358 struct net_device *dev, *dev1 = NULL;
cd28ab6a 3359 struct sky2_hw *hw;
5afa0a9c 3360 int err, pm_cap, using_dac = 0;
cd28ab6a 3361
793b883e
SH		 3362 err = pci_enable_device(pdev);
3363 if (err) {
cd28ab6a
SH		 3364 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3365 pci_name(pdev));
3366 goto err_out;
3367 }
3368
793b883e
SH		 3369 err = pci_request_regions(pdev, DRV_NAME);
3370 if (err) {
cd28ab6a
SH		 3371 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3372 pci_name(pdev));
793b883e 3373 goto err_out;
cd28ab6a
SH		 3374 }
3375
3376 pci_set_master(pdev);
3377
5afa0a9c
SH		 3378 /* Find power-management capability. */
3379 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3380 if (pm_cap == 0) {
3381 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3382 "aborting.\n");
3383 err = -EIO;
3384 goto err_out_free_regions;
3385 }
3386
d1f3d4dd
SH		 3387 if (sizeof(dma_addr_t) > sizeof(u32) &&
3388 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3389 using_dac = 1;
3390 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3391 if (err < 0) {
3392 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3393 "for consistent allocations\n", pci_name(pdev));
3394 goto err_out_free_regions;
3395 }
cd28ab6a 3396
d1f3d4dd 3397 } else {
cd28ab6a
SH		 3398 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3399 if (err) {
3400 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3401 pci_name(pdev));
3402 goto err_out_free_regions;
3403 }
3404 }
d1f3d4dd 3405
cd28ab6a 3406 err = -ENOMEM;
6aad85d6 3407 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
cd28ab6a
SH		 3408 if (!hw) {
3409 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3410 pci_name(pdev));
3411 goto err_out_free_regions;
3412 }
3413
cd28ab6a 3414 hw->pdev = pdev;
cd28ab6a
SH		 3415
3416 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3417 if (!hw->regs) {
3418 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3419 pci_name(pdev));
3420 goto err_out_free_hw;
3421 }
5afa0a9c 3422 hw->pm_cap = pm_cap;
cd28ab6a 3423
56a645cc 3424#ifdef __BIG_ENDIAN
f65b138c
SH		 3425 /* The sk98lin vendor driver uses hardware byte swapping but
3426 * this driver uses software swapping.
3427 */
56a645cc
SH		 3428 {
3429 u32 reg;
56a645cc 3430 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
f65b138c 3431 reg &= ~PCI_REV_DESC;
56a645cc
SH		 3432 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3433 }
3434#endif
3435
08c06d8a
SH		 3436 /* ring for status responses */
3437 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3438 &hw->st_dma);
3439 if (!hw->st_le)
3440 goto err_out_iounmap;
3441
cd28ab6a
SH		 3442 err = sky2_reset(hw);
3443 if (err)
793b883e 3444 goto err_out_iounmap;
cd28ab6a 3445
7c7459d1
GKH		 3446 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3447 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3448 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
793b883e 3449 hw->chip_id, hw->chip_rev);
cd28ab6a 3450
793b883e
SH		 3451 dev = sky2_init_netdev(hw, 0, using_dac);
3452 if (!dev)
cd28ab6a
SH		 3453 goto err_out_free_pci;
3454
9fa1b1f3
SH		 3455 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3456 err = sky2_test_msi(hw);
3457 if (err == -EOPNOTSUPP)
3458 pci_disable_msi(pdev);
3459 else if (err)
3460 goto err_out_free_netdev;
3461 }
3462
793b883e
SH		 3463 err = register_netdev(dev);
3464 if (err) {
cd28ab6a
SH		 3465 printk(KERN_ERR PFX "%s: cannot register net device\n",
3466 pci_name(pdev));
3467 goto err_out_free_netdev;
3468 }
3469
9fa1b1f3
SH		 3470 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, dev->name, hw);
3471 if (err) {
3472 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3473 pci_name(pdev), pdev->irq);
3474 goto err_out_unregister;
3475 }
3476 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3477
cd28ab6a
SH		 3478 sky2_show_addr(dev);
3479
3480 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3481 if (register_netdev(dev1) == 0)
3482 sky2_show_addr(dev1);
3483 else {
3484 /* Failure to register second port need not be fatal */
793b883e
SH		 3485 printk(KERN_WARNING PFX
3486 "register of second port failed\n");
cd28ab6a
SH		 3487 hw->dev[1] = NULL;
3488 free_netdev(dev1);
3489 }
3490 }
3491
01bd7564 3492 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
eb35cf60 3493 sky2_idle_start(hw);
d27ed387 3494
793b883e
SH		 3495 pci_set_drvdata(pdev, hw);
3496
cd28ab6a
SH		 3497 return 0;
3498
793b883e 3499err_out_unregister:
fb2690a9 3500 pci_disable_msi(pdev);
793b883e 3501 unregister_netdev(dev);
cd28ab6a
SH		 3502err_out_free_netdev:
3503 free_netdev(dev);
cd28ab6a 3504err_out_free_pci:
793b883e 3505 sky2_write8(hw, B0_CTST, CS_RST_SET);
cd28ab6a
SH		 3506 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3507err_out_iounmap:
3508 iounmap(hw->regs);
3509err_out_free_hw:
3510 kfree(hw);
3511err_out_free_regions:
3512 pci_release_regions(pdev);
cd28ab6a 3513 pci_disable_device(pdev);
cd28ab6a
SH		 3514err_out:
3515 return err;
3516}
3517
3518static void __devexit sky2_remove(struct pci_dev *pdev)
3519{
793b883e 3520 struct sky2_hw *hw = pci_get_drvdata(pdev);
cd28ab6a
SH		 3521 struct net_device *dev0, *dev1;
3522
793b883e 3523 if (!hw)
cd28ab6a
SH		 3524 return;
3525
d27ed387
SH		 3526 del_timer_sync(&hw->idle_timer);
3527
3528 sky2_write32(hw, B0_IMSK, 0);
72cb8529
SH		 3529 synchronize_irq(hw->pdev->irq);
3530
cd28ab6a 3531 dev0 = hw->dev[0];
793b883e
SH		 3532 dev1 = hw->dev[1];
3533 if (dev1)
3534 unregister_netdev(dev1);
cd28ab6a
SH		 3535 unregister_netdev(dev0);
3536
5afa0a9c 3537 sky2_set_power_state(hw, PCI_D3hot);
cd28ab6a 3538 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
793b883e 3539 sky2_write8(hw, B0_CTST, CS_RST_SET);
5afa0a9c 3540 sky2_read8(hw, B0_CTST);
cd28ab6a
SH		 3541
3542 free_irq(pdev->irq, hw);
fb2690a9 3543 pci_disable_msi(pdev);
793b883e 3544 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
cd28ab6a
SH		 3545 pci_release_regions(pdev);
3546 pci_disable_device(pdev);
793b883e 3547
cd28ab6a
SH		 3548 if (dev1)
3549 free_netdev(dev1);
3550 free_netdev(dev0);
3551 iounmap(hw->regs);
3552 kfree(hw);
5afa0a9c 3553
cd28ab6a
SH		 3554 pci_set_drvdata(pdev, NULL);
3555}
3556
3557#ifdef CONFIG_PM
3558static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3559{
793b883e 3560 struct sky2_hw *hw = pci_get_drvdata(pdev);
5afa0a9c 3561 int i;
2ccc99b7
SH		 3562 pci_power_t pstate = pci_choose_state(pdev, state);
3563
3564 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3565 return -EINVAL;
cd28ab6a 3566
eb35cf60 3567 del_timer_sync(&hw->idle_timer);
6a5706b9 3568 netif_poll_disable(hw->dev[0]);
eb35cf60 3569
f05267e7 3570 for (i = 0; i < hw->ports; i++) {
cd28ab6a
SH		 3571 struct net_device *dev = hw->dev[i];
3572
6a5706b9 3573 if (netif_running(dev)) {
5afa0a9c 3574 sky2_down(dev);
cd28ab6a 3575 netif_device_detach(dev);
cd28ab6a
SH		 3576 }
3577 }
3578
8ab8fca2 3579 sky2_write32(hw, B0_IMSK, 0);
d374c1c1 3580 pci_save_state(pdev);
2ccc99b7
SH		 3581 sky2_set_power_state(hw, pstate);
3582 return 0;
cd28ab6a
SH		 3583}
3584
3585static int sky2_resume(struct pci_dev *pdev)
3586{
793b883e 3587 struct sky2_hw *hw = pci_get_drvdata(pdev);
08c06d8a 3588 int i, err;
cd28ab6a 3589
cd28ab6a
SH		 3590 pci_restore_state(pdev);
3591 pci_enable_wake(pdev, PCI_D0, 0);
2ccc99b7 3592 sky2_set_power_state(hw, PCI_D0);
cd28ab6a 3593
08c06d8a
SH		 3594 err = sky2_reset(hw);
3595 if (err)
3596 goto out;
cd28ab6a 3597
8ab8fca2
SH		 3598 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3599
f05267e7 3600 for (i = 0; i < hw->ports; i++) {
cd28ab6a 3601 struct net_device *dev = hw->dev[i];
6a5706b9 3602 if (netif_running(dev)) {
08c06d8a 3603 netif_device_attach(dev);
88d11360 3604
08c06d8a
SH		 3605 err = sky2_up(dev);
3606 if (err) {
3607 printk(KERN_ERR PFX "%s: could not up: %d\n",
3608 dev->name, err);
3609 dev_close(dev);
eb35cf60 3610 goto out;
5afa0a9c 3611 }
cd28ab6a
SH		 3612 }
3613 }
eb35cf60 3614
6a5706b9 3615 netif_poll_enable(hw->dev[0]);
eb35cf60 3616 sky2_idle_start(hw);
08c06d8a
SH		 3617out:
3618 return err;
cd28ab6a
SH		 3619}
3620#endif
3621
3622static struct pci_driver sky2_driver = {
793b883e
SH		 3623 .name = DRV_NAME,
3624 .id_table = sky2_id_table,
3625 .probe = sky2_probe,
3626 .remove = __devexit_p(sky2_remove),
cd28ab6a 3627#ifdef CONFIG_PM
793b883e
SH		 3628 .suspend = sky2_suspend,
3629 .resume = sky2_resume,
cd28ab6a
SH		 3630#endif
3631};
3632
3633static int __init sky2_init_module(void)
3634{
50241c4c 3635 return pci_register_driver(&sky2_driver);
cd28ab6a
SH		 3636}
3637
3638static void __exit sky2_cleanup_module(void)
3639{
3640 pci_unregister_driver(&sky2_driver);
3641}
3642
3643module_init(sky2_init_module);
3644module_exit(sky2_cleanup_module);
3645
3646MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3647MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3648MODULE_LICENSE("GPL");
5f4f9dc1 3649MODULE_VERSION(DRV_VERSION);
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