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Commit | Line | Data |
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cd28ab6a SH |
1 | /* |
2 | * New driver for Marvell Yukon 2 chipset. | |
3 | * Based on earlier sk98lin, and skge driver. | |
4 | * | |
5 | * This driver intentionally does not support all the features | |
6 | * of the original driver such as link fail-over and link management because | |
7 | * those should be done at higher levels. | |
8 | * | |
9 | * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org> | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2 of the License, or | |
14 | * (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
793b883e | 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
cd28ab6a SH |
19 | * GNU General Public License for more details. |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | */ | |
25 | ||
cd28ab6a | 26 | #include <linux/config.h> |
793b883e | 27 | #include <linux/crc32.h> |
cd28ab6a SH |
28 | #include <linux/kernel.h> |
29 | #include <linux/version.h> | |
30 | #include <linux/module.h> | |
31 | #include <linux/netdevice.h> | |
d0bbccfa | 32 | #include <linux/dma-mapping.h> |
cd28ab6a SH |
33 | #include <linux/etherdevice.h> |
34 | #include <linux/ethtool.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/ip.h> | |
37 | #include <linux/tcp.h> | |
38 | #include <linux/in.h> | |
39 | #include <linux/delay.h> | |
91c86df5 | 40 | #include <linux/workqueue.h> |
d1f13708 | 41 | #include <linux/if_vlan.h> |
d70cd51a | 42 | #include <linux/prefetch.h> |
ef743d33 | 43 | #include <linux/mii.h> |
cd28ab6a SH |
44 | |
45 | #include <asm/irq.h> | |
46 | ||
d1f13708 SH |
47 | #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) |
48 | #define SKY2_VLAN_TAG_USED 1 | |
49 | #endif | |
50 | ||
cd28ab6a SH |
51 | #include "sky2.h" |
52 | ||
53 | #define DRV_NAME "sky2" | |
6d4b0f61 | 54 | #define DRV_VERSION "1.3" |
cd28ab6a SH |
55 | #define PFX DRV_NAME " " |
56 | ||
57 | /* | |
58 | * The Yukon II chipset takes 64 bit command blocks (called list elements) | |
59 | * that are organized into three (receive, transmit, status) different rings | |
60 | * similar to Tigon3. A transmit can require several elements; | |
61 | * a receive requires one (or two if using 64 bit dma). | |
62 | */ | |
63 | ||
13210ce5 | 64 | #define RX_LE_SIZE 512 |
cd28ab6a | 65 | #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le)) |
bea86103 | 66 | #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2) |
13210ce5 | 67 | #define RX_DEF_PENDING RX_MAX_PENDING |
82788c7a | 68 | #define RX_SKB_ALIGN 8 |
793b883e SH |
69 | |
70 | #define TX_RING_SIZE 512 | |
71 | #define TX_DEF_PENDING (TX_RING_SIZE - 1) | |
72 | #define TX_MIN_PENDING 64 | |
b19666d9 | 73 | #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS) |
cd28ab6a | 74 | |
793b883e | 75 | #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */ |
cd28ab6a SH |
76 | #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le)) |
77 | #define ETH_JUMBO_MTU 9000 | |
78 | #define TX_WATCHDOG (5 * HZ) | |
79 | #define NAPI_WEIGHT 64 | |
80 | #define PHY_RETRIES 1000 | |
81 | ||
cb5d9547 SH |
82 | #define RING_NEXT(x,s) (((x)+1) & ((s)-1)) |
83 | ||
cd28ab6a | 84 | static const u32 default_msg = |
793b883e SH |
85 | NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
86 | | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR | |
3be92a70 | 87 | | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN; |
cd28ab6a | 88 | |
793b883e | 89 | static int debug = -1; /* defaults above */ |
cd28ab6a SH |
90 | module_param(debug, int, 0); |
91 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); | |
92 | ||
bdb5c58e SH |
93 | static int copybreak __read_mostly = 256; |
94 | module_param(copybreak, int, 0); | |
95 | MODULE_PARM_DESC(copybreak, "Receive copy threshold"); | |
96 | ||
fb2690a9 SH |
97 | static int disable_msi = 0; |
98 | module_param(disable_msi, int, 0); | |
99 | MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)"); | |
100 | ||
01bd7564 SH |
101 | static int idle_timeout = 100; |
102 | module_param(idle_timeout, int, 0); | |
103 | MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)"); | |
104 | ||
cd28ab6a | 105 | static const struct pci_device_id sky2_id_table[] = { |
793b883e | 106 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, |
cd28ab6a | 107 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, |
cd28ab6a SH |
108 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, |
109 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, | |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, | |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, | |
112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, | |
113 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, | |
114 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, | |
115 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, | |
116 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, | |
117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, | |
5a5b1ea0 | 118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, |
cd28ab6a SH |
119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, |
120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, | |
121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, | |
5a5b1ea0 | 122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, |
cd28ab6a SH |
123 | { 0 } |
124 | }; | |
793b883e | 125 | |
cd28ab6a SH |
126 | MODULE_DEVICE_TABLE(pci, sky2_id_table); |
127 | ||
128 | /* Avoid conditionals by using array */ | |
129 | static const unsigned txqaddr[] = { Q_XA1, Q_XA2 }; | |
130 | static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; | |
f4ea431b | 131 | static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 }; |
cd28ab6a | 132 | |
92f965e8 SH |
133 | /* This driver supports yukon2 chipset only */ |
134 | static const char *yukon2_name[] = { | |
135 | "XL", /* 0xb3 */ | |
136 | "EC Ultra", /* 0xb4 */ | |
137 | "UNKNOWN", /* 0xb5 */ | |
138 | "EC", /* 0xb6 */ | |
139 | "FE", /* 0xb7 */ | |
793b883e SH |
140 | }; |
141 | ||
793b883e | 142 | /* Access to external PHY */ |
ef743d33 | 143 | static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val) |
cd28ab6a SH |
144 | { |
145 | int i; | |
146 | ||
147 | gma_write16(hw, port, GM_SMI_DATA, val); | |
148 | gma_write16(hw, port, GM_SMI_CTRL, | |
149 | GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg)); | |
150 | ||
151 | for (i = 0; i < PHY_RETRIES; i++) { | |
cd28ab6a | 152 | if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY)) |
ef743d33 | 153 | return 0; |
793b883e | 154 | udelay(1); |
cd28ab6a | 155 | } |
ef743d33 | 156 | |
793b883e | 157 | printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name); |
ef743d33 | 158 | return -ETIMEDOUT; |
cd28ab6a SH |
159 | } |
160 | ||
ef743d33 | 161 | static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val) |
cd28ab6a SH |
162 | { |
163 | int i; | |
164 | ||
793b883e | 165 | gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) |
cd28ab6a SH |
166 | | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); |
167 | ||
168 | for (i = 0; i < PHY_RETRIES; i++) { | |
ef743d33 SH |
169 | if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) { |
170 | *val = gma_read16(hw, port, GM_SMI_DATA); | |
171 | return 0; | |
172 | } | |
173 | ||
793b883e | 174 | udelay(1); |
cd28ab6a SH |
175 | } |
176 | ||
ef743d33 SH |
177 | return -ETIMEDOUT; |
178 | } | |
179 | ||
180 | static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) | |
181 | { | |
182 | u16 v; | |
183 | ||
184 | if (__gm_phy_read(hw, port, reg, &v) != 0) | |
185 | printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name); | |
186 | return v; | |
cd28ab6a SH |
187 | } |
188 | ||
5afa0a9c SH |
189 | static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) |
190 | { | |
191 | u16 power_control; | |
192 | u32 reg1; | |
193 | int vaux; | |
194 | int ret = 0; | |
195 | ||
196 | pr_debug("sky2_set_power_state %d\n", state); | |
197 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
198 | ||
56a645cc | 199 | power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC); |
08c06d8a | 200 | vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) && |
5afa0a9c SH |
201 | (power_control & PCI_PM_CAP_PME_D3cold); |
202 | ||
56a645cc | 203 | power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL); |
5afa0a9c SH |
204 | |
205 | power_control |= PCI_PM_CTRL_PME_STATUS; | |
206 | power_control &= ~(PCI_PM_CTRL_STATE_MASK); | |
207 | ||
208 | switch (state) { | |
209 | case PCI_D0: | |
210 | /* switch power to VCC (WA for VAUX problem) */ | |
211 | sky2_write8(hw, B0_POWER_CTRL, | |
212 | PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); | |
213 | ||
214 | /* disable Core Clock Division, */ | |
215 | sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); | |
216 | ||
217 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
218 | /* enable bits are inverted */ | |
219 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
220 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
221 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
222 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
223 | else | |
224 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
225 | ||
226 | /* Turn off phy power saving */ | |
56a645cc | 227 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
5afa0a9c SH |
228 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); |
229 | ||
d571b694 | 230 | /* looks like this XL is back asswards .. */ |
5afa0a9c SH |
231 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { |
232 | reg1 |= PCI_Y2_PHY1_COMA; | |
233 | if (hw->ports > 1) | |
234 | reg1 |= PCI_Y2_PHY2_COMA; | |
235 | } | |
977bdf06 SH |
236 | |
237 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
56a645cc SH |
238 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
239 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); | |
977bdf06 | 240 | reg1 &= P_ASPM_CONTROL_MSK; |
56a645cc SH |
241 | sky2_pci_write32(hw, PCI_DEV_REG4, reg1); |
242 | sky2_pci_write32(hw, PCI_DEV_REG5, 0); | |
977bdf06 SH |
243 | } |
244 | ||
56a645cc | 245 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
977bdf06 | 246 | |
5afa0a9c SH |
247 | break; |
248 | ||
249 | case PCI_D3hot: | |
250 | case PCI_D3cold: | |
251 | /* Turn on phy power saving */ | |
56a645cc | 252 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
5afa0a9c SH |
253 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
254 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
255 | else | |
256 | reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | |
56a645cc | 257 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
5afa0a9c SH |
258 | |
259 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | |
260 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | |
261 | else | |
262 | /* enable bits are inverted */ | |
263 | sky2_write8(hw, B2_Y2_CLK_GATE, | |
264 | Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | | |
265 | Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | | |
266 | Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS); | |
267 | ||
268 | /* switch power to VAUX */ | |
269 | if (vaux && state != PCI_D3cold) | |
270 | sky2_write8(hw, B0_POWER_CTRL, | |
271 | (PC_VAUX_ENA | PC_VCC_ENA | | |
272 | PC_VAUX_ON | PC_VCC_OFF)); | |
273 | break; | |
274 | default: | |
275 | printk(KERN_ERR PFX "Unknown power state %d\n", state); | |
276 | ret = -1; | |
277 | } | |
278 | ||
56a645cc | 279 | sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control); |
5afa0a9c SH |
280 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
281 | return ret; | |
282 | } | |
283 | ||
cd28ab6a SH |
284 | static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) |
285 | { | |
286 | u16 reg; | |
287 | ||
288 | /* disable all GMAC IRQ's */ | |
289 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0); | |
290 | /* disable PHY IRQs */ | |
291 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
793b883e | 292 | |
cd28ab6a SH |
293 | gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */ |
294 | gma_write16(hw, port, GM_MC_ADDR_H2, 0); | |
295 | gma_write16(hw, port, GM_MC_ADDR_H3, 0); | |
296 | gma_write16(hw, port, GM_MC_ADDR_H4, 0); | |
297 | ||
298 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
299 | reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; | |
300 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
301 | } | |
302 | ||
303 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |
304 | { | |
305 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
793b883e | 306 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover; |
cd28ab6a | 307 | |
ed6d32c7 SH |
308 | if (sky2->autoneg == AUTONEG_ENABLE && |
309 | (hw->chip_id != CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) { | |
cd28ab6a SH |
310 | u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL); |
311 | ||
312 | ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK | | |
793b883e | 313 | PHY_M_EC_MAC_S_MSK); |
cd28ab6a SH |
314 | ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ); |
315 | ||
316 | if (hw->chip_id == CHIP_ID_YUKON_EC) | |
317 | ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA; | |
318 | else | |
319 | ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3); | |
320 | ||
321 | gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl); | |
322 | } | |
323 | ||
324 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
325 | if (hw->copper) { | |
326 | if (hw->chip_id == CHIP_ID_YUKON_FE) { | |
327 | /* enable automatic crossover */ | |
328 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | |
329 | } else { | |
330 | /* disable energy detect */ | |
331 | ctrl &= ~PHY_M_PC_EN_DET_MSK; | |
332 | ||
333 | /* enable automatic crossover */ | |
334 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO); | |
335 | ||
336 | if (sky2->autoneg == AUTONEG_ENABLE && | |
ed6d32c7 | 337 | (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) { |
cd28ab6a SH |
338 | ctrl &= ~PHY_M_PC_DSC_MSK; |
339 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | |
340 | } | |
341 | } | |
342 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
343 | } else { | |
344 | /* workaround for deviation #4.88 (CRC errors) */ | |
345 | /* disable Automatic Crossover */ | |
346 | ||
347 | ctrl &= ~PHY_M_PC_MDIX_MSK; | |
348 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
349 | ||
350 | if (hw->chip_id == CHIP_ID_YUKON_XL) { | |
351 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ | |
352 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | |
353 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
354 | ctrl &= ~PHY_M_MAC_MD_MSK; | |
355 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | |
356 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | |
357 | ||
358 | /* select page 1 to access Fiber registers */ | |
359 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | |
360 | } | |
cd28ab6a SH |
361 | } |
362 | ||
363 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | |
364 | if (sky2->autoneg == AUTONEG_DISABLE) | |
365 | ctrl &= ~PHY_CT_ANE; | |
366 | else | |
367 | ctrl |= PHY_CT_ANE; | |
368 | ||
369 | ctrl |= PHY_CT_RESET; | |
370 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
371 | ||
372 | ctrl = 0; | |
373 | ct1000 = 0; | |
374 | adv = PHY_AN_CSMA; | |
375 | ||
376 | if (sky2->autoneg == AUTONEG_ENABLE) { | |
377 | if (hw->copper) { | |
378 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | |
379 | ct1000 |= PHY_M_1000C_AFD; | |
380 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | |
381 | ct1000 |= PHY_M_1000C_AHD; | |
382 | if (sky2->advertising & ADVERTISED_100baseT_Full) | |
383 | adv |= PHY_M_AN_100_FD; | |
384 | if (sky2->advertising & ADVERTISED_100baseT_Half) | |
385 | adv |= PHY_M_AN_100_HD; | |
386 | if (sky2->advertising & ADVERTISED_10baseT_Full) | |
387 | adv |= PHY_M_AN_10_FD; | |
388 | if (sky2->advertising & ADVERTISED_10baseT_Half) | |
389 | adv |= PHY_M_AN_10_HD; | |
793b883e | 390 | } else /* special defines for FIBER (88E1011S only) */ |
cd28ab6a SH |
391 | adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; |
392 | ||
393 | /* Set Flow-control capabilities */ | |
394 | if (sky2->tx_pause && sky2->rx_pause) | |
793b883e | 395 | adv |= PHY_AN_PAUSE_CAP; /* symmetric */ |
cd28ab6a | 396 | else if (sky2->rx_pause && !sky2->tx_pause) |
793b883e | 397 | adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP; |
cd28ab6a SH |
398 | else if (!sky2->rx_pause && sky2->tx_pause) |
399 | adv |= PHY_AN_PAUSE_ASYM; /* local */ | |
400 | ||
401 | /* Restart Auto-negotiation */ | |
402 | ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG; | |
403 | } else { | |
404 | /* forced speed/duplex settings */ | |
405 | ct1000 = PHY_M_1000C_MSE; | |
406 | ||
407 | if (sky2->duplex == DUPLEX_FULL) | |
408 | ctrl |= PHY_CT_DUP_MD; | |
409 | ||
410 | switch (sky2->speed) { | |
411 | case SPEED_1000: | |
412 | ctrl |= PHY_CT_SP1000; | |
413 | break; | |
414 | case SPEED_100: | |
415 | ctrl |= PHY_CT_SP100; | |
416 | break; | |
417 | } | |
418 | ||
419 | ctrl |= PHY_CT_RESET; | |
420 | } | |
421 | ||
422 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
423 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); | |
424 | ||
425 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv); | |
426 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | |
427 | ||
428 | /* Setup Phy LED's */ | |
429 | ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS); | |
430 | ledover = 0; | |
431 | ||
432 | switch (hw->chip_id) { | |
433 | case CHIP_ID_YUKON_FE: | |
434 | /* on 88E3082 these bits are at 11..9 (shifted left) */ | |
435 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1; | |
436 | ||
437 | ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR); | |
438 | ||
439 | /* delete ACT LED control bits */ | |
440 | ctrl &= ~PHY_M_FELP_LED1_MSK; | |
441 | /* change ACT LED control to blink mode */ | |
442 | ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL); | |
443 | gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl); | |
444 | break; | |
445 | ||
446 | case CHIP_ID_YUKON_XL: | |
793b883e | 447 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
cd28ab6a SH |
448 | |
449 | /* select page 3 to access LED control register */ | |
450 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
451 | ||
452 | /* set LED Function Control register */ | |
ed6d32c7 SH |
453 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, |
454 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
455 | PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */ | |
456 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
457 | PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */ | |
cd28ab6a SH |
458 | |
459 | /* set Polarity Control register */ | |
460 | gm_phy_write(hw, port, PHY_MARV_PHY_STAT, | |
793b883e SH |
461 | (PHY_M_POLC_LS1_P_MIX(4) | |
462 | PHY_M_POLC_IS0_P_MIX(4) | | |
463 | PHY_M_POLC_LOS_CTRL(2) | | |
464 | PHY_M_POLC_INIT_CTRL(2) | | |
465 | PHY_M_POLC_STA1_CTRL(2) | | |
466 | PHY_M_POLC_STA0_CTRL(2))); | |
cd28ab6a SH |
467 | |
468 | /* restore page register */ | |
793b883e | 469 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
cd28ab6a | 470 | break; |
ed6d32c7 SH |
471 | case CHIP_ID_YUKON_EC_U: |
472 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
473 | ||
474 | /* select page 3 to access LED control register */ | |
475 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
476 | ||
477 | /* set LED Function Control register */ | |
478 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
479 | (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */ | |
480 | PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */ | |
481 | PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */ | |
482 | PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */ | |
483 | ||
484 | /* set Blink Rate in LED Timer Control Register */ | |
485 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, | |
486 | ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS)); | |
487 | /* restore page register */ | |
488 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
489 | break; | |
cd28ab6a SH |
490 | |
491 | default: | |
492 | /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */ | |
493 | ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL; | |
494 | /* turn off the Rx LED (LED_RX) */ | |
495 | ledover |= PHY_M_LED_MO_RX(MO_LED_OFF); | |
496 | } | |
497 | ||
ed6d32c7 | 498 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) { |
977bdf06 | 499 | /* apply fixes in PHY AFE */ |
ed6d32c7 SH |
500 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
501 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255); | |
502 | ||
977bdf06 | 503 | /* increase differential signal amplitude in 10BASE-T */ |
ed6d32c7 SH |
504 | gm_phy_write(hw, port, 0x18, 0xaa99); |
505 | gm_phy_write(hw, port, 0x17, 0x2011); | |
cd28ab6a | 506 | |
977bdf06 | 507 | /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ |
ed6d32c7 SH |
508 | gm_phy_write(hw, port, 0x18, 0xa204); |
509 | gm_phy_write(hw, port, 0x17, 0x2002); | |
977bdf06 SH |
510 | |
511 | /* set page register to 0 */ | |
ed6d32c7 | 512 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
977bdf06 SH |
513 | } else { |
514 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
cd28ab6a | 515 | |
977bdf06 SH |
516 | if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) { |
517 | /* turn on 100 Mbps LED (LED_LINK100) */ | |
518 | ledover |= PHY_M_LED_MO_100(MO_LED_ON); | |
519 | } | |
cd28ab6a | 520 | |
977bdf06 SH |
521 | if (ledover) |
522 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
523 | ||
524 | } | |
d571b694 | 525 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
cd28ab6a SH |
526 | if (sky2->autoneg == AUTONEG_ENABLE) |
527 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | |
528 | else | |
529 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
530 | } | |
531 | ||
1b537565 SH |
532 | /* Force a renegotiation */ |
533 | static void sky2_phy_reinit(struct sky2_port *sky2) | |
534 | { | |
e07b1aa8 | 535 | spin_lock_bh(&sky2->phy_lock); |
1b537565 | 536 | sky2_phy_init(sky2->hw, sky2->port); |
e07b1aa8 | 537 | spin_unlock_bh(&sky2->phy_lock); |
1b537565 SH |
538 | } |
539 | ||
cd28ab6a SH |
540 | static void sky2_mac_init(struct sky2_hw *hw, unsigned port) |
541 | { | |
542 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | |
543 | u16 reg; | |
544 | int i; | |
545 | const u8 *addr = hw->dev[port]->dev_addr; | |
546 | ||
42eeea01 SH |
547 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); |
548 | sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE); | |
cd28ab6a SH |
549 | |
550 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); | |
551 | ||
793b883e | 552 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) { |
cd28ab6a SH |
553 | /* WA DEV_472 -- looks like crossed wires on port 2 */ |
554 | /* clear GMAC 1 Control reset */ | |
555 | sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR); | |
556 | do { | |
557 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET); | |
558 | sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR); | |
559 | } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL || | |
560 | gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 || | |
561 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | |
562 | } | |
563 | ||
cd28ab6a SH |
564 | if (sky2->autoneg == AUTONEG_DISABLE) { |
565 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
566 | reg |= GM_GPCR_AU_ALL_DIS; | |
567 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
568 | gma_read16(hw, port, GM_GP_CTRL); | |
569 | ||
cd28ab6a SH |
570 | switch (sky2->speed) { |
571 | case SPEED_1000: | |
6f4c56b2 | 572 | reg &= ~GM_GPCR_SPEED_100; |
cd28ab6a | 573 | reg |= GM_GPCR_SPEED_1000; |
6f4c56b2 | 574 | break; |
cd28ab6a | 575 | case SPEED_100: |
6f4c56b2 | 576 | reg &= ~GM_GPCR_SPEED_1000; |
cd28ab6a | 577 | reg |= GM_GPCR_SPEED_100; |
6f4c56b2 SH |
578 | break; |
579 | case SPEED_10: | |
580 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
581 | break; | |
cd28ab6a SH |
582 | } |
583 | ||
584 | if (sky2->duplex == DUPLEX_FULL) | |
585 | reg |= GM_GPCR_DUP_FULL; | |
ed6d32c7 SH |
586 | |
587 | /* turn off pause in 10/100mbps half duplex */ | |
588 | else if (sky2->speed != SPEED_1000 && | |
589 | hw->chip_id != CHIP_ID_YUKON_EC_U) | |
590 | sky2->tx_pause = sky2->rx_pause = 0; | |
cd28ab6a SH |
591 | } else |
592 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | |
593 | ||
594 | if (!sky2->tx_pause && !sky2->rx_pause) { | |
595 | sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
793b883e SH |
596 | reg |= |
597 | GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
598 | } else if (sky2->tx_pause && !sky2->rx_pause) { | |
cd28ab6a SH |
599 | /* disable Rx flow-control */ |
600 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | |
601 | } | |
602 | ||
603 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
604 | ||
793b883e | 605 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
cd28ab6a | 606 | |
e07b1aa8 | 607 | spin_lock_bh(&sky2->phy_lock); |
cd28ab6a | 608 | sky2_phy_init(hw, port); |
e07b1aa8 | 609 | spin_unlock_bh(&sky2->phy_lock); |
cd28ab6a SH |
610 | |
611 | /* MIB clear */ | |
612 | reg = gma_read16(hw, port, GM_PHY_ADDR); | |
613 | gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR); | |
614 | ||
43f2f104 SH |
615 | for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4) |
616 | gma_read16(hw, port, i); | |
cd28ab6a SH |
617 | gma_write16(hw, port, GM_PHY_ADDR, reg); |
618 | ||
619 | /* transmit control */ | |
620 | gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); | |
621 | ||
622 | /* receive control reg: unicast + multicast + no FCS */ | |
623 | gma_write16(hw, port, GM_RX_CTRL, | |
793b883e | 624 | GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA); |
cd28ab6a SH |
625 | |
626 | /* transmit flow control */ | |
627 | gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff); | |
628 | ||
629 | /* transmit parameter */ | |
630 | gma_write16(hw, port, GM_TX_PARAM, | |
631 | TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | | |
632 | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | | |
633 | TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | | |
634 | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); | |
635 | ||
636 | /* serial mode register */ | |
637 | reg = DATA_BLIND_VAL(DATA_BLIND_DEF) | | |
6b1a3aef | 638 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); |
cd28ab6a | 639 | |
6b1a3aef | 640 | if (hw->dev[port]->mtu > ETH_DATA_LEN) |
cd28ab6a SH |
641 | reg |= GM_SMOD_JUMBO_ENA; |
642 | ||
643 | gma_write16(hw, port, GM_SERIAL_MODE, reg); | |
644 | ||
cd28ab6a SH |
645 | /* virtual address for data */ |
646 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr); | |
647 | ||
793b883e SH |
648 | /* physical address: used for pause frames */ |
649 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr); | |
650 | ||
651 | /* ignore counter overflows */ | |
cd28ab6a SH |
652 | gma_write16(hw, port, GM_TX_IRQ_MSK, 0); |
653 | gma_write16(hw, port, GM_RX_IRQ_MSK, 0); | |
654 | gma_write16(hw, port, GM_TR_IRQ_MSK, 0); | |
655 | ||
656 | /* Configure Rx MAC FIFO */ | |
657 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR); | |
70f1be48 SH |
658 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), |
659 | GMF_OPER_ON | GMF_RX_F_FL_ON); | |
cd28ab6a | 660 | |
d571b694 | 661 | /* Flush Rx MAC FIFO on any flow control or error */ |
42eeea01 | 662 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR); |
cd28ab6a | 663 | |
793b883e SH |
664 | /* Set threshold to 0xa (64 bytes) |
665 | * ASF disabled so no need to do WA dev #4.30 | |
cd28ab6a SH |
666 | */ |
667 | sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF); | |
668 | ||
669 | /* Configure Tx MAC FIFO */ | |
670 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR); | |
671 | sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON); | |
5a5b1ea0 SH |
672 | |
673 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | |
674 | sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8); | |
675 | sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8); | |
676 | if (hw->dev[port]->mtu > ETH_DATA_LEN) { | |
677 | /* set Tx GMAC FIFO Almost Empty Threshold */ | |
678 | sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180); | |
679 | /* Disable Store & Forward mode for TX */ | |
680 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS); | |
681 | } | |
682 | } | |
683 | ||
cd28ab6a SH |
684 | } |
685 | ||
1c28f6ba SH |
686 | /* Assign Ram Buffer allocation. |
687 | * start and end are in units of 4k bytes | |
688 | * ram registers are in units of 64bit words | |
689 | */ | |
690 | static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk) | |
cd28ab6a | 691 | { |
1c28f6ba | 692 | u32 start, end; |
cd28ab6a | 693 | |
1c28f6ba SH |
694 | start = startk * 4096/8; |
695 | end = (endk * 4096/8) - 1; | |
793b883e | 696 | |
cd28ab6a SH |
697 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR); |
698 | sky2_write32(hw, RB_ADDR(q, RB_START), start); | |
699 | sky2_write32(hw, RB_ADDR(q, RB_END), end); | |
700 | sky2_write32(hw, RB_ADDR(q, RB_WP), start); | |
701 | sky2_write32(hw, RB_ADDR(q, RB_RP), start); | |
702 | ||
703 | if (q == Q_R1 || q == Q_R2) { | |
1c28f6ba SH |
704 | u32 space = (endk - startk) * 4096/8; |
705 | u32 tp = space - space/4; | |
793b883e | 706 | |
1c28f6ba SH |
707 | /* On receive queue's set the thresholds |
708 | * give receiver priority when > 3/4 full | |
709 | * send pause when down to 2K | |
710 | */ | |
711 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp); | |
712 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2); | |
793b883e | 713 | |
1c28f6ba SH |
714 | tp = space - 2048/8; |
715 | sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp); | |
716 | sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4); | |
cd28ab6a SH |
717 | } else { |
718 | /* Enable store & forward on Tx queue's because | |
719 | * Tx FIFO is only 1K on Yukon | |
720 | */ | |
721 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD); | |
722 | } | |
723 | ||
724 | sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD); | |
793b883e | 725 | sky2_read8(hw, RB_ADDR(q, RB_CTRL)); |
cd28ab6a SH |
726 | } |
727 | ||
cd28ab6a | 728 | /* Setup Bus Memory Interface */ |
af4ed7e6 | 729 | static void sky2_qset(struct sky2_hw *hw, u16 q) |
cd28ab6a SH |
730 | { |
731 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET); | |
732 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT); | |
733 | sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON); | |
af4ed7e6 | 734 | sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT); |
cd28ab6a SH |
735 | } |
736 | ||
cd28ab6a SH |
737 | /* Setup prefetch unit registers. This is the interface between |
738 | * hardware and driver list elements | |
739 | */ | |
8cc048e3 | 740 | static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr, |
cd28ab6a SH |
741 | u64 addr, u32 last) |
742 | { | |
cd28ab6a SH |
743 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); |
744 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR); | |
745 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32); | |
746 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr); | |
747 | sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last); | |
748 | sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON); | |
793b883e SH |
749 | |
750 | sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL)); | |
cd28ab6a SH |
751 | } |
752 | ||
793b883e SH |
753 | static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) |
754 | { | |
755 | struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod; | |
756 | ||
cb5d9547 | 757 | sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE); |
793b883e SH |
758 | return le; |
759 | } | |
cd28ab6a | 760 | |
290d4de5 SH |
761 | /* Update chip's next pointer */ |
762 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) | |
cd28ab6a | 763 | { |
762c2de2 | 764 | wmb(); |
290d4de5 | 765 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); |
762c2de2 | 766 | mmiowb(); |
cd28ab6a SH |
767 | } |
768 | ||
793b883e | 769 | |
cd28ab6a SH |
770 | static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2) |
771 | { | |
772 | struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put; | |
cb5d9547 | 773 | sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE); |
cd28ab6a SH |
774 | return le; |
775 | } | |
776 | ||
a018e330 SH |
777 | /* Return high part of DMA address (could be 32 or 64 bit) */ |
778 | static inline u32 high32(dma_addr_t a) | |
779 | { | |
a036119f | 780 | return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0; |
a018e330 SH |
781 | } |
782 | ||
793b883e | 783 | /* Build description to hardware about buffer */ |
28bd181a | 784 | static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map) |
cd28ab6a SH |
785 | { |
786 | struct sky2_rx_le *le; | |
734d1868 SH |
787 | u32 hi = high32(map); |
788 | u16 len = sky2->rx_bufsize; | |
cd28ab6a | 789 | |
793b883e | 790 | if (sky2->rx_addr64 != hi) { |
cd28ab6a | 791 | le = sky2_next_rx(sky2); |
793b883e | 792 | le->addr = cpu_to_le32(hi); |
cd28ab6a SH |
793 | le->ctrl = 0; |
794 | le->opcode = OP_ADDR64 | HW_OWNER; | |
734d1868 | 795 | sky2->rx_addr64 = high32(map + len); |
cd28ab6a | 796 | } |
793b883e | 797 | |
cd28ab6a | 798 | le = sky2_next_rx(sky2); |
734d1868 SH |
799 | le->addr = cpu_to_le32((u32) map); |
800 | le->length = cpu_to_le16(len); | |
cd28ab6a SH |
801 | le->ctrl = 0; |
802 | le->opcode = OP_PACKET | HW_OWNER; | |
803 | } | |
804 | ||
793b883e | 805 | |
cd28ab6a SH |
806 | /* Tell chip where to start receive checksum. |
807 | * Actually has two checksums, but set both same to avoid possible byte | |
808 | * order problems. | |
809 | */ | |
793b883e | 810 | static void rx_set_checksum(struct sky2_port *sky2) |
cd28ab6a SH |
811 | { |
812 | struct sky2_rx_le *le; | |
813 | ||
cd28ab6a | 814 | le = sky2_next_rx(sky2); |
793b883e | 815 | le->addr = (ETH_HLEN << 16) | ETH_HLEN; |
cd28ab6a SH |
816 | le->ctrl = 0; |
817 | le->opcode = OP_TCPSTART | HW_OWNER; | |
793b883e | 818 | |
793b883e SH |
819 | sky2_write32(sky2->hw, |
820 | Q_ADDR(rxqaddr[sky2->port], Q_CSR), | |
821 | sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
cd28ab6a SH |
822 | |
823 | } | |
824 | ||
6b1a3aef SH |
825 | /* |
826 | * The RX Stop command will not work for Yukon-2 if the BMU does not | |
827 | * reach the end of packet and since we can't make sure that we have | |
828 | * incoming data, we must reset the BMU while it is not doing a DMA | |
829 | * transfer. Since it is possible that the RX path is still active, | |
830 | * the RX RAM buffer will be stopped first, so any possible incoming | |
831 | * data will not trigger a DMA. After the RAM buffer is stopped, the | |
832 | * BMU is polled until any DMA in progress is ended and only then it | |
833 | * will be reset. | |
834 | */ | |
835 | static void sky2_rx_stop(struct sky2_port *sky2) | |
836 | { | |
837 | struct sky2_hw *hw = sky2->hw; | |
838 | unsigned rxq = rxqaddr[sky2->port]; | |
839 | int i; | |
840 | ||
841 | /* disable the RAM Buffer receive queue */ | |
842 | sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD); | |
843 | ||
844 | for (i = 0; i < 0xffff; i++) | |
845 | if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL)) | |
846 | == sky2_read8(hw, RB_ADDR(rxq, Q_RL))) | |
847 | goto stopped; | |
848 | ||
849 | printk(KERN_WARNING PFX "%s: receiver stop failed\n", | |
850 | sky2->netdev->name); | |
851 | stopped: | |
852 | sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST); | |
853 | ||
854 | /* reset the Rx prefetch unit */ | |
855 | sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
856 | } | |
793b883e | 857 | |
d571b694 | 858 | /* Clean out receive buffer area, assumes receiver hardware stopped */ |
cd28ab6a SH |
859 | static void sky2_rx_clean(struct sky2_port *sky2) |
860 | { | |
861 | unsigned i; | |
862 | ||
863 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
793b883e | 864 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a SH |
865 | struct ring_info *re = sky2->rx_ring + i; |
866 | ||
867 | if (re->skb) { | |
793b883e | 868 | pci_unmap_single(sky2->hw->pdev, |
734d1868 | 869 | re->mapaddr, sky2->rx_bufsize, |
cd28ab6a SH |
870 | PCI_DMA_FROMDEVICE); |
871 | kfree_skb(re->skb); | |
872 | re->skb = NULL; | |
873 | } | |
874 | } | |
875 | } | |
876 | ||
ef743d33 SH |
877 | /* Basic MII support */ |
878 | static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) | |
879 | { | |
880 | struct mii_ioctl_data *data = if_mii(ifr); | |
881 | struct sky2_port *sky2 = netdev_priv(dev); | |
882 | struct sky2_hw *hw = sky2->hw; | |
883 | int err = -EOPNOTSUPP; | |
884 | ||
885 | if (!netif_running(dev)) | |
886 | return -ENODEV; /* Phy still in reset */ | |
887 | ||
d89e1343 | 888 | switch (cmd) { |
ef743d33 SH |
889 | case SIOCGMIIPHY: |
890 | data->phy_id = PHY_ADDR_MARV; | |
891 | ||
892 | /* fallthru */ | |
893 | case SIOCGMIIREG: { | |
894 | u16 val = 0; | |
91c86df5 | 895 | |
e07b1aa8 | 896 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 | 897 | err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val); |
e07b1aa8 | 898 | spin_unlock_bh(&sky2->phy_lock); |
91c86df5 | 899 | |
ef743d33 SH |
900 | data->val_out = val; |
901 | break; | |
902 | } | |
903 | ||
904 | case SIOCSMIIREG: | |
905 | if (!capable(CAP_NET_ADMIN)) | |
906 | return -EPERM; | |
907 | ||
e07b1aa8 | 908 | spin_lock_bh(&sky2->phy_lock); |
ef743d33 SH |
909 | err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f, |
910 | data->val_in); | |
e07b1aa8 | 911 | spin_unlock_bh(&sky2->phy_lock); |
ef743d33 SH |
912 | break; |
913 | } | |
914 | return err; | |
915 | } | |
916 | ||
d1f13708 SH |
917 | #ifdef SKY2_VLAN_TAG_USED |
918 | static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp) | |
919 | { | |
920 | struct sky2_port *sky2 = netdev_priv(dev); | |
921 | struct sky2_hw *hw = sky2->hw; | |
922 | u16 port = sky2->port; | |
d1f13708 | 923 | |
302d1252 | 924 | spin_lock_bh(&sky2->tx_lock); |
d1f13708 SH |
925 | |
926 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON); | |
927 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON); | |
928 | sky2->vlgrp = grp; | |
929 | ||
302d1252 | 930 | spin_unlock_bh(&sky2->tx_lock); |
d1f13708 SH |
931 | } |
932 | ||
933 | static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |
934 | { | |
935 | struct sky2_port *sky2 = netdev_priv(dev); | |
936 | struct sky2_hw *hw = sky2->hw; | |
937 | u16 port = sky2->port; | |
d1f13708 | 938 | |
302d1252 | 939 | spin_lock_bh(&sky2->tx_lock); |
d1f13708 SH |
940 | |
941 | sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF); | |
942 | sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF); | |
943 | if (sky2->vlgrp) | |
944 | sky2->vlgrp->vlan_devices[vid] = NULL; | |
945 | ||
302d1252 | 946 | spin_unlock_bh(&sky2->tx_lock); |
d1f13708 SH |
947 | } |
948 | #endif | |
949 | ||
82788c7a SH |
950 | /* |
951 | * It appears the hardware has a bug in the FIFO logic that | |
952 | * cause it to hang if the FIFO gets overrun and the receive buffer | |
953 | * is not aligned. ALso alloc_skb() won't align properly if slab | |
954 | * debugging is enabled. | |
955 | */ | |
956 | static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask) | |
957 | { | |
958 | struct sk_buff *skb; | |
959 | ||
960 | skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask); | |
961 | if (likely(skb)) { | |
962 | unsigned long p = (unsigned long) skb->data; | |
4a15d56f | 963 | skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p); |
82788c7a SH |
964 | } |
965 | ||
966 | return skb; | |
967 | } | |
968 | ||
cd28ab6a SH |
969 | /* |
970 | * Allocate and setup receiver buffer pool. | |
971 | * In case of 64 bit dma, there are 2X as many list elements | |
972 | * available as ring entries | |
973 | * and need to reserve one list element so we don't wrap around. | |
974 | */ | |
6b1a3aef | 975 | static int sky2_rx_start(struct sky2_port *sky2) |
cd28ab6a | 976 | { |
6b1a3aef | 977 | struct sky2_hw *hw = sky2->hw; |
6b1a3aef SH |
978 | unsigned rxq = rxqaddr[sky2->port]; |
979 | int i; | |
cd28ab6a | 980 | |
6b1a3aef | 981 | sky2->rx_put = sky2->rx_next = 0; |
af4ed7e6 | 982 | sky2_qset(hw, rxq); |
977bdf06 SH |
983 | |
984 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) { | |
985 | /* MAC Rx RAM Read is controlled by hardware */ | |
986 | sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS); | |
987 | } | |
988 | ||
6b1a3aef SH |
989 | sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1); |
990 | ||
991 | rx_set_checksum(sky2); | |
793b883e | 992 | for (i = 0; i < sky2->rx_pending; i++) { |
cd28ab6a | 993 | struct ring_info *re = sky2->rx_ring + i; |
cd28ab6a | 994 | |
82788c7a | 995 | re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL); |
cd28ab6a SH |
996 | if (!re->skb) |
997 | goto nomem; | |
998 | ||
6b1a3aef | 999 | re->mapaddr = pci_map_single(hw->pdev, re->skb->data, |
734d1868 SH |
1000 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
1001 | sky2_rx_add(sky2, re->mapaddr); | |
cd28ab6a SH |
1002 | } |
1003 | ||
70f1be48 SH |
1004 | /* Truncate oversize frames */ |
1005 | sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), sky2->rx_bufsize - 8); | |
1006 | sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON); | |
1007 | ||
6b1a3aef SH |
1008 | /* Tell chip about available buffers */ |
1009 | sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put); | |
cd28ab6a SH |
1010 | return 0; |
1011 | nomem: | |
1012 | sky2_rx_clean(sky2); | |
1013 | return -ENOMEM; | |
1014 | } | |
1015 | ||
1016 | /* Bring up network interface. */ | |
1017 | static int sky2_up(struct net_device *dev) | |
1018 | { | |
1019 | struct sky2_port *sky2 = netdev_priv(dev); | |
1020 | struct sky2_hw *hw = sky2->hw; | |
1021 | unsigned port = sky2->port; | |
e07b1aa8 | 1022 | u32 ramsize, rxspace, imask; |
843a46f4 SH |
1023 | int err; |
1024 | struct net_device *otherdev = hw->dev[sky2->port^1]; | |
cd28ab6a | 1025 | |
843a46f4 SH |
1026 | /* Block bringing up both ports at the same time on a dual port card. |
1027 | * There is an unfixed bug where receiver gets confused and picks up | |
1028 | * packets out of order. Until this is fixed, prevent data corruption. | |
1029 | */ | |
1030 | if (otherdev && netif_running(otherdev)) { | |
1031 | printk(KERN_INFO PFX "dual port support is disabled.\n"); | |
1032 | return -EBUSY; | |
1033 | } | |
1034 | ||
1035 | err = -ENOMEM; | |
cd28ab6a SH |
1036 | if (netif_msg_ifup(sky2)) |
1037 | printk(KERN_INFO PFX "%s: enabling interface\n", dev->name); | |
1038 | ||
1039 | /* must be power of 2 */ | |
1040 | sky2->tx_le = pci_alloc_consistent(hw->pdev, | |
793b883e SH |
1041 | TX_RING_SIZE * |
1042 | sizeof(struct sky2_tx_le), | |
cd28ab6a SH |
1043 | &sky2->tx_le_map); |
1044 | if (!sky2->tx_le) | |
1045 | goto err_out; | |
1046 | ||
6cdbbdf3 | 1047 | sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info), |
cd28ab6a SH |
1048 | GFP_KERNEL); |
1049 | if (!sky2->tx_ring) | |
1050 | goto err_out; | |
1051 | sky2->tx_prod = sky2->tx_cons = 0; | |
cd28ab6a SH |
1052 | |
1053 | sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES, | |
1054 | &sky2->rx_le_map); | |
1055 | if (!sky2->rx_le) | |
1056 | goto err_out; | |
1057 | memset(sky2->rx_le, 0, RX_LE_BYTES); | |
1058 | ||
6cdbbdf3 | 1059 | sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info), |
cd28ab6a SH |
1060 | GFP_KERNEL); |
1061 | if (!sky2->rx_ring) | |
1062 | goto err_out; | |
1063 | ||
1064 | sky2_mac_init(hw, port); | |
1065 | ||
1c28f6ba SH |
1066 | /* Determine available ram buffer space (in 4K blocks). |
1067 | * Note: not sure about the FE setting below yet | |
1068 | */ | |
1069 | if (hw->chip_id == CHIP_ID_YUKON_FE) | |
1070 | ramsize = 4; | |
1071 | else | |
1072 | ramsize = sky2_read8(hw, B2_E_0); | |
1073 | ||
1074 | /* Give transmitter one third (rounded up) */ | |
1075 | rxspace = ramsize - (ramsize + 2) / 3; | |
cd28ab6a | 1076 | |
cd28ab6a | 1077 | sky2_ramset(hw, rxqaddr[port], 0, rxspace); |
1c28f6ba | 1078 | sky2_ramset(hw, txqaddr[port], rxspace, ramsize); |
cd28ab6a | 1079 | |
793b883e SH |
1080 | /* Make sure SyncQ is disabled */ |
1081 | sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL), | |
1082 | RB_RST_SET); | |
1083 | ||
af4ed7e6 | 1084 | sky2_qset(hw, txqaddr[port]); |
5a5b1ea0 | 1085 | |
977bdf06 SH |
1086 | /* Set almost empty threshold */ |
1087 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1) | |
1088 | sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0); | |
5a5b1ea0 | 1089 | |
6b1a3aef SH |
1090 | sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map, |
1091 | TX_RING_SIZE - 1); | |
cd28ab6a | 1092 | |
6b1a3aef | 1093 | err = sky2_rx_start(sky2); |
cd28ab6a SH |
1094 | if (err) |
1095 | goto err_out; | |
1096 | ||
cd28ab6a | 1097 | /* Enable interrupts from phy/mac for port */ |
e07b1aa8 | 1098 | imask = sky2_read32(hw, B0_IMSK); |
f4ea431b | 1099 | imask |= portirq_msk[port]; |
e07b1aa8 SH |
1100 | sky2_write32(hw, B0_IMSK, imask); |
1101 | ||
cd28ab6a SH |
1102 | return 0; |
1103 | ||
1104 | err_out: | |
1b537565 | 1105 | if (sky2->rx_le) { |
cd28ab6a SH |
1106 | pci_free_consistent(hw->pdev, RX_LE_BYTES, |
1107 | sky2->rx_le, sky2->rx_le_map); | |
1b537565 SH |
1108 | sky2->rx_le = NULL; |
1109 | } | |
1110 | if (sky2->tx_le) { | |
cd28ab6a SH |
1111 | pci_free_consistent(hw->pdev, |
1112 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1113 | sky2->tx_le, sky2->tx_le_map); | |
1b537565 SH |
1114 | sky2->tx_le = NULL; |
1115 | } | |
1116 | kfree(sky2->tx_ring); | |
1117 | kfree(sky2->rx_ring); | |
cd28ab6a | 1118 | |
1b537565 SH |
1119 | sky2->tx_ring = NULL; |
1120 | sky2->rx_ring = NULL; | |
cd28ab6a SH |
1121 | return err; |
1122 | } | |
1123 | ||
793b883e SH |
1124 | /* Modular subtraction in ring */ |
1125 | static inline int tx_dist(unsigned tail, unsigned head) | |
1126 | { | |
cb5d9547 | 1127 | return (head - tail) & (TX_RING_SIZE - 1); |
793b883e | 1128 | } |
cd28ab6a | 1129 | |
793b883e SH |
1130 | /* Number of list elements available for next tx */ |
1131 | static inline int tx_avail(const struct sky2_port *sky2) | |
cd28ab6a | 1132 | { |
793b883e | 1133 | return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod); |
cd28ab6a SH |
1134 | } |
1135 | ||
793b883e | 1136 | /* Estimate of number of transmit list elements required */ |
28bd181a | 1137 | static unsigned tx_le_req(const struct sk_buff *skb) |
cd28ab6a | 1138 | { |
793b883e SH |
1139 | unsigned count; |
1140 | ||
1141 | count = sizeof(dma_addr_t) / sizeof(u32); | |
1142 | count += skb_shinfo(skb)->nr_frags * count; | |
1143 | ||
1144 | if (skb_shinfo(skb)->tso_size) | |
1145 | ++count; | |
1146 | ||
0e3ff6aa | 1147 | if (skb->ip_summed == CHECKSUM_HW) |
793b883e SH |
1148 | ++count; |
1149 | ||
1150 | return count; | |
cd28ab6a SH |
1151 | } |
1152 | ||
793b883e SH |
1153 | /* |
1154 | * Put one packet in ring for transmit. | |
1155 | * A single packet can generate multiple list elements, and | |
1156 | * the number of ring elements will probably be less than the number | |
1157 | * of list elements used. | |
f2e46561 SH |
1158 | * |
1159 | * No BH disabling for tx_lock here (like tg3) | |
793b883e | 1160 | */ |
cd28ab6a SH |
1161 | static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) |
1162 | { | |
1163 | struct sky2_port *sky2 = netdev_priv(dev); | |
1164 | struct sky2_hw *hw = sky2->hw; | |
d1f13708 | 1165 | struct sky2_tx_le *le = NULL; |
6cdbbdf3 | 1166 | struct tx_ring_info *re; |
cd28ab6a | 1167 | unsigned i, len; |
b19666d9 | 1168 | int avail; |
cd28ab6a SH |
1169 | dma_addr_t mapping; |
1170 | u32 addr64; | |
1171 | u16 mss; | |
1172 | u8 ctrl; | |
1173 | ||
302d1252 SH |
1174 | /* No BH disabling for tx_lock here. We are running in BH disabled |
1175 | * context and TX reclaim runs via poll inside of a software | |
1176 | * interrupt, and no related locks in IRQ processing. | |
1177 | */ | |
f2e46561 | 1178 | if (!spin_trylock(&sky2->tx_lock)) |
cd28ab6a SH |
1179 | return NETDEV_TX_LOCKED; |
1180 | ||
793b883e | 1181 | if (unlikely(tx_avail(sky2) < tx_le_req(skb))) { |
8c463ef7 SH |
1182 | /* There is a known but harmless race with lockless tx |
1183 | * and netif_stop_queue. | |
1184 | */ | |
1185 | if (!netif_queue_stopped(dev)) { | |
1186 | netif_stop_queue(dev); | |
3be92a70 SH |
1187 | if (net_ratelimit()) |
1188 | printk(KERN_WARNING PFX "%s: ring full when queue awake!\n", | |
1189 | dev->name); | |
8c463ef7 | 1190 | } |
f2e46561 | 1191 | spin_unlock(&sky2->tx_lock); |
cd28ab6a | 1192 | |
cd28ab6a SH |
1193 | return NETDEV_TX_BUSY; |
1194 | } | |
1195 | ||
793b883e | 1196 | if (unlikely(netif_msg_tx_queued(sky2))) |
cd28ab6a SH |
1197 | printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n", |
1198 | dev->name, sky2->tx_prod, skb->len); | |
1199 | ||
cd28ab6a SH |
1200 | len = skb_headlen(skb); |
1201 | mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE); | |
a018e330 | 1202 | addr64 = high32(mapping); |
793b883e SH |
1203 | |
1204 | re = sky2->tx_ring + sky2->tx_prod; | |
1205 | ||
a018e330 SH |
1206 | /* Send high bits if changed or crosses boundary */ |
1207 | if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { | |
793b883e SH |
1208 | le = get_tx_le(sky2); |
1209 | le->tx.addr = cpu_to_le32(addr64); | |
1210 | le->ctrl = 0; | |
1211 | le->opcode = OP_ADDR64 | HW_OWNER; | |
a018e330 | 1212 | sky2->tx_addr64 = high32(mapping + len); |
793b883e | 1213 | } |
cd28ab6a SH |
1214 | |
1215 | /* Check for TCP Segmentation Offload */ | |
1216 | mss = skb_shinfo(skb)->tso_size; | |
793b883e | 1217 | if (mss != 0) { |
cd28ab6a SH |
1218 | /* just drop the packet if non-linear expansion fails */ |
1219 | if (skb_header_cloned(skb) && | |
1220 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | |
15240072 | 1221 | dev_kfree_skb(skb); |
793b883e | 1222 | goto out_unlock; |
cd28ab6a SH |
1223 | } |
1224 | ||
1225 | mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ | |
1226 | mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); | |
1227 | mss += ETH_HLEN; | |
793b883e | 1228 | } |
cd28ab6a | 1229 | |
793b883e | 1230 | if (mss != sky2->tx_last_mss) { |
cd28ab6a SH |
1231 | le = get_tx_le(sky2); |
1232 | le->tx.tso.size = cpu_to_le16(mss); | |
793b883e | 1233 | le->tx.tso.rsvd = 0; |
cd28ab6a | 1234 | le->opcode = OP_LRGLEN | HW_OWNER; |
cd28ab6a | 1235 | le->ctrl = 0; |
793b883e | 1236 | sky2->tx_last_mss = mss; |
cd28ab6a SH |
1237 | } |
1238 | ||
cd28ab6a | 1239 | ctrl = 0; |
d1f13708 SH |
1240 | #ifdef SKY2_VLAN_TAG_USED |
1241 | /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */ | |
1242 | if (sky2->vlgrp && vlan_tx_tag_present(skb)) { | |
1243 | if (!le) { | |
1244 | le = get_tx_le(sky2); | |
1245 | le->tx.addr = 0; | |
1246 | le->opcode = OP_VLAN|HW_OWNER; | |
1247 | le->ctrl = 0; | |
1248 | } else | |
1249 | le->opcode |= OP_VLAN; | |
1250 | le->length = cpu_to_be16(vlan_tx_tag_get(skb)); | |
1251 | ctrl |= INS_VLAN; | |
1252 | } | |
1253 | #endif | |
1254 | ||
1255 | /* Handle TCP checksum offload */ | |
cd28ab6a | 1256 | if (skb->ip_summed == CHECKSUM_HW) { |
793b883e SH |
1257 | u16 hdr = skb->h.raw - skb->data; |
1258 | u16 offset = hdr + skb->csum; | |
cd28ab6a SH |
1259 | |
1260 | ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | |
1261 | if (skb->nh.iph->protocol == IPPROTO_UDP) | |
1262 | ctrl |= UDPTCP; | |
1263 | ||
1264 | le = get_tx_le(sky2); | |
1265 | le->tx.csum.start = cpu_to_le16(hdr); | |
793b883e SH |
1266 | le->tx.csum.offset = cpu_to_le16(offset); |
1267 | le->length = 0; /* initial checksum value */ | |
cd28ab6a | 1268 | le->ctrl = 1; /* one packet */ |
793b883e | 1269 | le->opcode = OP_TCPLISW | HW_OWNER; |
cd28ab6a SH |
1270 | } |
1271 | ||
1272 | le = get_tx_le(sky2); | |
1273 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1274 | le->length = cpu_to_le16(len); | |
1275 | le->ctrl = ctrl; | |
793b883e | 1276 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
cd28ab6a | 1277 | |
793b883e | 1278 | /* Record the transmit mapping info */ |
cd28ab6a | 1279 | re->skb = skb; |
6cdbbdf3 | 1280 | pci_unmap_addr_set(re, mapaddr, mapping); |
cd28ab6a SH |
1281 | |
1282 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
1283 | skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; | |
6cdbbdf3 | 1284 | struct tx_ring_info *fre; |
cd28ab6a SH |
1285 | |
1286 | mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset, | |
1287 | frag->size, PCI_DMA_TODEVICE); | |
a036119f | 1288 | addr64 = high32(mapping); |
793b883e SH |
1289 | if (addr64 != sky2->tx_addr64) { |
1290 | le = get_tx_le(sky2); | |
1291 | le->tx.addr = cpu_to_le32(addr64); | |
1292 | le->ctrl = 0; | |
1293 | le->opcode = OP_ADDR64 | HW_OWNER; | |
1294 | sky2->tx_addr64 = addr64; | |
cd28ab6a SH |
1295 | } |
1296 | ||
1297 | le = get_tx_le(sky2); | |
1298 | le->tx.addr = cpu_to_le32((u32) mapping); | |
1299 | le->length = cpu_to_le16(frag->size); | |
1300 | le->ctrl = ctrl; | |
793b883e | 1301 | le->opcode = OP_BUFFER | HW_OWNER; |
cd28ab6a | 1302 | |
793b883e | 1303 | fre = sky2->tx_ring |
cb5d9547 | 1304 | + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE); |
6cdbbdf3 | 1305 | pci_unmap_addr_set(fre, mapaddr, mapping); |
cd28ab6a | 1306 | } |
6cdbbdf3 | 1307 | |
793b883e | 1308 | re->idx = sky2->tx_prod; |
cd28ab6a SH |
1309 | le->ctrl |= EOP; |
1310 | ||
b19666d9 SH |
1311 | avail = tx_avail(sky2); |
1312 | if (mss != 0 || avail < TX_MIN_PENDING) { | |
1313 | le->ctrl |= FRC_STAT; | |
1314 | if (avail <= MAX_SKB_TX_LE) | |
1315 | netif_stop_queue(dev); | |
1316 | } | |
1317 | ||
290d4de5 | 1318 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); |
cd28ab6a | 1319 | |
793b883e | 1320 | out_unlock: |
f2e46561 | 1321 | spin_unlock(&sky2->tx_lock); |
cd28ab6a SH |
1322 | |
1323 | dev->trans_start = jiffies; | |
1324 | return NETDEV_TX_OK; | |
1325 | } | |
1326 | ||
cd28ab6a | 1327 | /* |
793b883e SH |
1328 | * Free ring elements from starting at tx_cons until "done" |
1329 | * | |
1330 | * NB: the hardware will tell us about partial completion of multi-part | |
d571b694 | 1331 | * buffers; these are deferred until completion. |
cd28ab6a | 1332 | */ |
d11c13e7 | 1333 | static void sky2_tx_complete(struct sky2_port *sky2, u16 done) |
cd28ab6a | 1334 | { |
d11c13e7 | 1335 | struct net_device *dev = sky2->netdev; |
af2a58ac SH |
1336 | struct pci_dev *pdev = sky2->hw->pdev; |
1337 | u16 nxt, put; | |
793b883e | 1338 | unsigned i; |
cd28ab6a | 1339 | |
0e3ff6aa | 1340 | BUG_ON(done >= TX_RING_SIZE); |
2224795d | 1341 | |
d11c13e7 | 1342 | if (unlikely(netif_msg_tx_done(sky2))) |
d571b694 | 1343 | printk(KERN_DEBUG "%s: tx done, up to %u\n", |
d11c13e7 | 1344 | dev->name, done); |
cd28ab6a | 1345 | |
af2a58ac SH |
1346 | for (put = sky2->tx_cons; put != done; put = nxt) { |
1347 | struct tx_ring_info *re = sky2->tx_ring + put; | |
1348 | struct sk_buff *skb = re->skb; | |
cd28ab6a | 1349 | |
d89e1343 | 1350 | nxt = re->idx; |
af2a58ac | 1351 | BUG_ON(nxt >= TX_RING_SIZE); |
d70cd51a | 1352 | prefetch(sky2->tx_ring + nxt); |
cd28ab6a | 1353 | |
793b883e | 1354 | /* Check for partial status */ |
af2a58ac SH |
1355 | if (tx_dist(put, done) < tx_dist(put, nxt)) |
1356 | break; | |
793b883e SH |
1357 | |
1358 | skb = re->skb; | |
af2a58ac | 1359 | pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr), |
734d1868 | 1360 | skb_headlen(skb), PCI_DMA_TODEVICE); |
793b883e SH |
1361 | |
1362 | for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { | |
6cdbbdf3 | 1363 | struct tx_ring_info *fre; |
cb5d9547 | 1364 | fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE); |
af2a58ac | 1365 | pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr), |
d89e1343 | 1366 | skb_shinfo(skb)->frags[i].size, |
734d1868 | 1367 | PCI_DMA_TODEVICE); |
cd28ab6a SH |
1368 | } |
1369 | ||
15240072 | 1370 | dev_kfree_skb(skb); |
793b883e | 1371 | } |
793b883e | 1372 | |
af2a58ac | 1373 | sky2->tx_cons = put; |
8f24664d | 1374 | if (tx_avail(sky2) > MAX_SKB_TX_LE) |
cd28ab6a | 1375 | netif_wake_queue(dev); |
cd28ab6a SH |
1376 | } |
1377 | ||
1378 | /* Cleanup all untransmitted buffers, assume transmitter not running */ | |
13b97b74 | 1379 | static void sky2_tx_clean(struct sky2_port *sky2) |
cd28ab6a | 1380 | { |
302d1252 | 1381 | spin_lock_bh(&sky2->tx_lock); |
d11c13e7 | 1382 | sky2_tx_complete(sky2, sky2->tx_prod); |
302d1252 | 1383 | spin_unlock_bh(&sky2->tx_lock); |
cd28ab6a SH |
1384 | } |
1385 | ||
1386 | /* Network shutdown */ | |
1387 | static int sky2_down(struct net_device *dev) | |
1388 | { | |
1389 | struct sky2_port *sky2 = netdev_priv(dev); | |
1390 | struct sky2_hw *hw = sky2->hw; | |
1391 | unsigned port = sky2->port; | |
1392 | u16 ctrl; | |
e07b1aa8 | 1393 | u32 imask; |
cd28ab6a | 1394 | |
1b537565 SH |
1395 | /* Never really got started! */ |
1396 | if (!sky2->tx_le) | |
1397 | return 0; | |
1398 | ||
cd28ab6a SH |
1399 | if (netif_msg_ifdown(sky2)) |
1400 | printk(KERN_INFO PFX "%s: disabling interface\n", dev->name); | |
1401 | ||
018d1c66 | 1402 | /* Stop more packets from being queued */ |
cd28ab6a SH |
1403 | netif_stop_queue(dev); |
1404 | ||
793b883e SH |
1405 | sky2_phy_reset(hw, port); |
1406 | ||
cd28ab6a SH |
1407 | /* Stop transmitter */ |
1408 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | |
1409 | sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR)); | |
1410 | ||
1411 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), | |
793b883e | 1412 | RB_RST_SET | RB_DIS_OP_MD); |
cd28ab6a SH |
1413 | |
1414 | ctrl = gma_read16(hw, port, GM_GP_CTRL); | |
793b883e | 1415 | ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA); |
cd28ab6a SH |
1416 | gma_write16(hw, port, GM_GP_CTRL, ctrl); |
1417 | ||
1418 | sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); | |
1419 | ||
1420 | /* Workaround shared GMAC reset */ | |
793b883e SH |
1421 | if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 |
1422 | && port == 0 && hw->dev[1] && netif_running(hw->dev[1]))) | |
cd28ab6a SH |
1423 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET); |
1424 | ||
1425 | /* Disable Force Sync bit and Enable Alloc bit */ | |
1426 | sky2_write8(hw, SK_REG(port, TXA_CTRL), | |
1427 | TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); | |
1428 | ||
1429 | /* Stop Interval Timer and Limit Counter of Tx Arbiter */ | |
1430 | sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L); | |
1431 | sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L); | |
1432 | ||
1433 | /* Reset the PCI FIFO of the async Tx queue */ | |
793b883e SH |
1434 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), |
1435 | BMU_RST_SET | BMU_FIFO_RST); | |
cd28ab6a SH |
1436 | |
1437 | /* Reset the Tx prefetch units */ | |
1438 | sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL), | |
1439 | PREF_UNIT_RST_SET); | |
1440 | ||
1441 | sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET); | |
1442 | ||
6b1a3aef | 1443 | sky2_rx_stop(sky2); |
cd28ab6a SH |
1444 | |
1445 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | |
1446 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET); | |
1447 | ||
e07b1aa8 SH |
1448 | /* Disable port IRQ */ |
1449 | imask = sky2_read32(hw, B0_IMSK); | |
f4ea431b | 1450 | imask &= ~portirq_msk[port]; |
e07b1aa8 SH |
1451 | sky2_write32(hw, B0_IMSK, imask); |
1452 | ||
d571b694 | 1453 | /* turn off LED's */ |
cd28ab6a SH |
1454 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
1455 | ||
018d1c66 SH |
1456 | synchronize_irq(hw->pdev->irq); |
1457 | ||
cd28ab6a SH |
1458 | sky2_tx_clean(sky2); |
1459 | sky2_rx_clean(sky2); | |
1460 | ||
1461 | pci_free_consistent(hw->pdev, RX_LE_BYTES, | |
1462 | sky2->rx_le, sky2->rx_le_map); | |
1463 | kfree(sky2->rx_ring); | |
1464 | ||
1465 | pci_free_consistent(hw->pdev, | |
1466 | TX_RING_SIZE * sizeof(struct sky2_tx_le), | |
1467 | sky2->tx_le, sky2->tx_le_map); | |
1468 | kfree(sky2->tx_ring); | |
1469 | ||
1b537565 SH |
1470 | sky2->tx_le = NULL; |
1471 | sky2->rx_le = NULL; | |
1472 | ||
1473 | sky2->rx_ring = NULL; | |
1474 | sky2->tx_ring = NULL; | |
1475 | ||
cd28ab6a SH |
1476 | return 0; |
1477 | } | |
1478 | ||
1479 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | |
1480 | { | |
793b883e SH |
1481 | if (!hw->copper) |
1482 | return SPEED_1000; | |
1483 | ||
cd28ab6a SH |
1484 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
1485 | return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10; | |
1486 | ||
1487 | switch (aux & PHY_M_PS_SPEED_MSK) { | |
1488 | case PHY_M_PS_SPEED_1000: | |
1489 | return SPEED_1000; | |
1490 | case PHY_M_PS_SPEED_100: | |
1491 | return SPEED_100; | |
1492 | default: | |
1493 | return SPEED_10; | |
1494 | } | |
1495 | } | |
1496 | ||
1497 | static void sky2_link_up(struct sky2_port *sky2) | |
1498 | { | |
1499 | struct sky2_hw *hw = sky2->hw; | |
1500 | unsigned port = sky2->port; | |
1501 | u16 reg; | |
1502 | ||
1503 | /* Enable Transmit FIFO Underrun */ | |
793b883e | 1504 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); |
cd28ab6a SH |
1505 | |
1506 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
6f4c56b2 SH |
1507 | if (sky2->autoneg == AUTONEG_DISABLE) { |
1508 | reg |= GM_GPCR_AU_ALL_DIS; | |
1509 | ||
1510 | /* Is write/read necessary? Copied from sky2_mac_init */ | |
1511 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1512 | gma_read16(hw, port, GM_GP_CTRL); | |
1513 | ||
1514 | switch (sky2->speed) { | |
1515 | case SPEED_1000: | |
1516 | reg &= ~GM_GPCR_SPEED_100; | |
1517 | reg |= GM_GPCR_SPEED_1000; | |
1518 | break; | |
1519 | case SPEED_100: | |
1520 | reg &= ~GM_GPCR_SPEED_1000; | |
1521 | reg |= GM_GPCR_SPEED_100; | |
1522 | break; | |
1523 | case SPEED_10: | |
1524 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | |
1525 | break; | |
1526 | } | |
1527 | } else | |
1528 | reg &= ~GM_GPCR_AU_ALL_DIS; | |
1529 | ||
cd28ab6a SH |
1530 | if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE) |
1531 | reg |= GM_GPCR_DUP_FULL; | |
1532 | ||
cd28ab6a SH |
1533 | /* enable Rx/Tx */ |
1534 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | |
1535 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1536 | gma_read16(hw, port, GM_GP_CTRL); | |
1537 | ||
1538 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | |
1539 | ||
1540 | netif_carrier_on(sky2->netdev); | |
1541 | netif_wake_queue(sky2->netdev); | |
1542 | ||
1543 | /* Turn on link LED */ | |
793b883e | 1544 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), |
cd28ab6a SH |
1545 | LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF); |
1546 | ||
ed6d32c7 | 1547 | if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) { |
793b883e | 1548 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
ed6d32c7 SH |
1549 | u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */ |
1550 | ||
1551 | switch(sky2->speed) { | |
1552 | case SPEED_10: | |
1553 | led |= PHY_M_LEDC_INIT_CTRL(7); | |
1554 | break; | |
1555 | ||
1556 | case SPEED_100: | |
1557 | led |= PHY_M_LEDC_STA1_CTRL(7); | |
1558 | break; | |
1559 | ||
1560 | case SPEED_1000: | |
1561 | led |= PHY_M_LEDC_STA0_CTRL(7); | |
1562 | break; | |
1563 | } | |
793b883e SH |
1564 | |
1565 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
ed6d32c7 | 1566 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led); |
793b883e SH |
1567 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); |
1568 | } | |
1569 | ||
cd28ab6a SH |
1570 | if (netif_msg_link(sky2)) |
1571 | printk(KERN_INFO PFX | |
d571b694 | 1572 | "%s: Link is up at %d Mbps, %s duplex, flow control %s\n", |
cd28ab6a SH |
1573 | sky2->netdev->name, sky2->speed, |
1574 | sky2->duplex == DUPLEX_FULL ? "full" : "half", | |
1575 | (sky2->tx_pause && sky2->rx_pause) ? "both" : | |
793b883e | 1576 | sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none"); |
cd28ab6a SH |
1577 | } |
1578 | ||
1579 | static void sky2_link_down(struct sky2_port *sky2) | |
1580 | { | |
1581 | struct sky2_hw *hw = sky2->hw; | |
1582 | unsigned port = sky2->port; | |
1583 | u16 reg; | |
1584 | ||
1585 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0); | |
1586 | ||
1587 | reg = gma_read16(hw, port, GM_GP_CTRL); | |
1588 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | |
1589 | gma_write16(hw, port, GM_GP_CTRL, reg); | |
1590 | gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ | |
1591 | ||
1592 | if (sky2->rx_pause && !sky2->tx_pause) { | |
1593 | /* restore Asymmetric Pause bit */ | |
1594 | gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, | |
793b883e SH |
1595 | gm_phy_read(hw, port, PHY_MARV_AUNE_ADV) |
1596 | | PHY_M_AN_ASP); | |
cd28ab6a SH |
1597 | } |
1598 | ||
cd28ab6a SH |
1599 | netif_carrier_off(sky2->netdev); |
1600 | netif_stop_queue(sky2->netdev); | |
1601 | ||
1602 | /* Turn on link LED */ | |
1603 | sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF); | |
1604 | ||
1605 | if (netif_msg_link(sky2)) | |
1606 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); | |
1607 | sky2_phy_init(hw, port); | |
1608 | } | |
1609 | ||
793b883e SH |
1610 | static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) |
1611 | { | |
1612 | struct sky2_hw *hw = sky2->hw; | |
1613 | unsigned port = sky2->port; | |
1614 | u16 lpa; | |
1615 | ||
1616 | lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP); | |
1617 | ||
1618 | if (lpa & PHY_M_AN_RF) { | |
1619 | printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name); | |
1620 | return -1; | |
1621 | } | |
1622 | ||
1623 | if (hw->chip_id != CHIP_ID_YUKON_FE && | |
1624 | gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) { | |
1625 | printk(KERN_ERR PFX "%s: master/slave fault", | |
1626 | sky2->netdev->name); | |
1627 | return -1; | |
1628 | } | |
1629 | ||
1630 | if (!(aux & PHY_M_PS_SPDUP_RES)) { | |
1631 | printk(KERN_ERR PFX "%s: speed/duplex mismatch", | |
1632 | sky2->netdev->name); | |
1633 | return -1; | |
1634 | } | |
1635 | ||
1636 | sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
1637 | ||
1638 | sky2->speed = sky2_phy_speed(hw, aux); | |
1639 | ||
1640 | /* Pause bits are offset (9..8) */ | |
ed6d32c7 | 1641 | if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) |
793b883e SH |
1642 | aux >>= 6; |
1643 | ||
1644 | sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; | |
1645 | sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; | |
1646 | ||
1647 | if ((sky2->tx_pause || sky2->rx_pause) | |
1648 | && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF)) | |
1649 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); | |
1650 | else | |
1651 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | |
1652 | ||
1653 | return 0; | |
1654 | } | |
cd28ab6a | 1655 | |
e07b1aa8 SH |
1656 | /* Interrupt from PHY */ |
1657 | static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |
cd28ab6a | 1658 | { |
e07b1aa8 SH |
1659 | struct net_device *dev = hw->dev[port]; |
1660 | struct sky2_port *sky2 = netdev_priv(dev); | |
cd28ab6a SH |
1661 | u16 istatus, phystat; |
1662 | ||
e07b1aa8 SH |
1663 | spin_lock(&sky2->phy_lock); |
1664 | istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT); | |
1665 | phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT); | |
1666 | ||
1667 | if (!netif_running(dev)) | |
1668 | goto out; | |
cd28ab6a SH |
1669 | |
1670 | if (netif_msg_intr(sky2)) | |
1671 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", | |
1672 | sky2->netdev->name, istatus, phystat); | |
1673 | ||
1674 | if (istatus & PHY_M_IS_AN_COMPL) { | |
793b883e SH |
1675 | if (sky2_autoneg_done(sky2, phystat) == 0) |
1676 | sky2_link_up(sky2); | |
1677 | goto out; | |
1678 | } | |
cd28ab6a | 1679 | |
793b883e SH |
1680 | if (istatus & PHY_M_IS_LSP_CHANGE) |
1681 | sky2->speed = sky2_phy_speed(hw, phystat); | |
cd28ab6a | 1682 | |
793b883e SH |
1683 | if (istatus & PHY_M_IS_DUP_CHANGE) |
1684 | sky2->duplex = | |
1685 | (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF; | |
cd28ab6a | 1686 | |
793b883e SH |
1687 | if (istatus & PHY_M_IS_LST_CHANGE) { |
1688 | if (phystat & PHY_M_PS_LINK_UP) | |
cd28ab6a | 1689 | sky2_link_up(sky2); |
793b883e SH |
1690 | else |
1691 | sky2_link_down(sky2); | |
cd28ab6a | 1692 | } |
793b883e | 1693 | out: |
e07b1aa8 | 1694 | spin_unlock(&sky2->phy_lock); |
cd28ab6a SH |
1695 | } |
1696 | ||
302d1252 SH |
1697 | |
1698 | /* Transmit timeout is only called if we are running, carries is up | |
1699 | * and tx queue is full (stopped). | |
1700 | */ | |
cd28ab6a SH |
1701 | static void sky2_tx_timeout(struct net_device *dev) |
1702 | { | |
1703 | struct sky2_port *sky2 = netdev_priv(dev); | |
8cc048e3 SH |
1704 | struct sky2_hw *hw = sky2->hw; |
1705 | unsigned txq = txqaddr[sky2->port]; | |
8f24664d | 1706 | u16 report, done; |
cd28ab6a SH |
1707 | |
1708 | if (netif_msg_timer(sky2)) | |
1709 | printk(KERN_ERR PFX "%s: tx timeout\n", dev->name); | |
1710 | ||
8f24664d SH |
1711 | report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX); |
1712 | done = sky2_read16(hw, Q_ADDR(txq, Q_DONE)); | |
cd28ab6a | 1713 | |
8f24664d SH |
1714 | printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n", |
1715 | dev->name, | |
1716 | sky2->tx_cons, sky2->tx_prod, report, done); | |
1717 | ||
1718 | if (report != done) { | |
1719 | printk(KERN_INFO PFX "status burst pending (irq moderation?)\n"); | |
1720 | ||
1721 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
1722 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
1723 | } else if (report != sky2->tx_cons) { | |
1724 | printk(KERN_INFO PFX "status report lost?\n"); | |
1725 | ||
1726 | spin_lock_bh(&sky2->tx_lock); | |
1727 | sky2_tx_complete(sky2, report); | |
1728 | spin_unlock_bh(&sky2->tx_lock); | |
1729 | } else { | |
1730 | printk(KERN_INFO PFX "hardware hung? flushing\n"); | |
8cc048e3 | 1731 | |
8f24664d SH |
1732 | sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP); |
1733 | sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET); | |
1734 | ||
1735 | sky2_tx_clean(sky2); | |
1736 | ||
1737 | sky2_qset(hw, txq); | |
1738 | sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1); | |
1739 | } | |
cd28ab6a SH |
1740 | } |
1741 | ||
734d1868 | 1742 | |
70f1be48 SH |
1743 | /* Want receive buffer size to be multiple of 64 bits |
1744 | * and incl room for vlan and truncation | |
1745 | */ | |
734d1868 SH |
1746 | static inline unsigned sky2_buf_size(int mtu) |
1747 | { | |
4a15d56f | 1748 | return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8; |
734d1868 SH |
1749 | } |
1750 | ||
cd28ab6a SH |
1751 | static int sky2_change_mtu(struct net_device *dev, int new_mtu) |
1752 | { | |
6b1a3aef SH |
1753 | struct sky2_port *sky2 = netdev_priv(dev); |
1754 | struct sky2_hw *hw = sky2->hw; | |
1755 | int err; | |
1756 | u16 ctl, mode; | |
e07b1aa8 | 1757 | u32 imask; |
cd28ab6a SH |
1758 | |
1759 | if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU) | |
1760 | return -EINVAL; | |
1761 | ||
5a5b1ea0 SH |
1762 | if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN) |
1763 | return -EINVAL; | |
1764 | ||
6b1a3aef SH |
1765 | if (!netif_running(dev)) { |
1766 | dev->mtu = new_mtu; | |
1767 | return 0; | |
1768 | } | |
1769 | ||
e07b1aa8 | 1770 | imask = sky2_read32(hw, B0_IMSK); |
6b1a3aef SH |
1771 | sky2_write32(hw, B0_IMSK, 0); |
1772 | ||
018d1c66 SH |
1773 | dev->trans_start = jiffies; /* prevent tx timeout */ |
1774 | netif_stop_queue(dev); | |
1775 | netif_poll_disable(hw->dev[0]); | |
1776 | ||
e07b1aa8 SH |
1777 | synchronize_irq(hw->pdev->irq); |
1778 | ||
6b1a3aef SH |
1779 | ctl = gma_read16(hw, sky2->port, GM_GP_CTRL); |
1780 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA); | |
1781 | sky2_rx_stop(sky2); | |
1782 | sky2_rx_clean(sky2); | |
cd28ab6a SH |
1783 | |
1784 | dev->mtu = new_mtu; | |
734d1868 | 1785 | sky2->rx_bufsize = sky2_buf_size(new_mtu); |
6b1a3aef SH |
1786 | mode = DATA_BLIND_VAL(DATA_BLIND_DEF) | |
1787 | GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); | |
1788 | ||
1789 | if (dev->mtu > ETH_DATA_LEN) | |
1790 | mode |= GM_SMOD_JUMBO_ENA; | |
1791 | ||
1792 | gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode); | |
cd28ab6a | 1793 | |
6b1a3aef | 1794 | sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD); |
cd28ab6a | 1795 | |
6b1a3aef | 1796 | err = sky2_rx_start(sky2); |
e07b1aa8 | 1797 | sky2_write32(hw, B0_IMSK, imask); |
018d1c66 | 1798 | |
1b537565 SH |
1799 | if (err) |
1800 | dev_close(dev); | |
1801 | else { | |
1802 | gma_write16(hw, sky2->port, GM_GP_CTRL, ctl); | |
1803 | ||
1804 | netif_poll_enable(hw->dev[0]); | |
1805 | netif_wake_queue(dev); | |
1806 | } | |
1807 | ||
cd28ab6a SH |
1808 | return err; |
1809 | } | |
1810 | ||
1811 | /* | |
1812 | * Receive one packet. | |
1813 | * For small packets or errors, just reuse existing skb. | |
d571b694 | 1814 | * For larger packets, get new buffer. |
cd28ab6a | 1815 | */ |
d11c13e7 | 1816 | static struct sk_buff *sky2_receive(struct sky2_port *sky2, |
cd28ab6a SH |
1817 | u16 length, u32 status) |
1818 | { | |
cd28ab6a | 1819 | struct ring_info *re = sky2->rx_ring + sky2->rx_next; |
79e57d32 | 1820 | struct sk_buff *skb = NULL; |
cd28ab6a SH |
1821 | |
1822 | if (unlikely(netif_msg_rx_status(sky2))) | |
1823 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", | |
d11c13e7 | 1824 | sky2->netdev->name, sky2->rx_next, status, length); |
cd28ab6a | 1825 | |
793b883e | 1826 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
d70cd51a | 1827 | prefetch(sky2->rx_ring + sky2->rx_next); |
cd28ab6a | 1828 | |
42eeea01 | 1829 | if (status & GMR_FS_ANY_ERR) |
cd28ab6a SH |
1830 | goto error; |
1831 | ||
42eeea01 SH |
1832 | if (!(status & GMR_FS_RX_OK)) |
1833 | goto resubmit; | |
1834 | ||
70f1be48 | 1835 | if (length > sky2->netdev->mtu + ETH_HLEN) |
6e15b712 SH |
1836 | goto oversize; |
1837 | ||
bdb5c58e | 1838 | if (length < copybreak) { |
79e57d32 SH |
1839 | skb = alloc_skb(length + 2, GFP_ATOMIC); |
1840 | if (!skb) | |
793b883e SH |
1841 | goto resubmit; |
1842 | ||
79e57d32 | 1843 | skb_reserve(skb, 2); |
793b883e SH |
1844 | pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr, |
1845 | length, PCI_DMA_FROMDEVICE); | |
79e57d32 | 1846 | memcpy(skb->data, re->skb->data, length); |
d11c13e7 SH |
1847 | skb->ip_summed = re->skb->ip_summed; |
1848 | skb->csum = re->skb->csum; | |
793b883e SH |
1849 | pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr, |
1850 | length, PCI_DMA_FROMDEVICE); | |
793b883e | 1851 | } else { |
79e57d32 SH |
1852 | struct sk_buff *nskb; |
1853 | ||
82788c7a | 1854 | nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC); |
793b883e SH |
1855 | if (!nskb) |
1856 | goto resubmit; | |
cd28ab6a | 1857 | |
793b883e | 1858 | skb = re->skb; |
79e57d32 | 1859 | re->skb = nskb; |
793b883e | 1860 | pci_unmap_single(sky2->hw->pdev, re->mapaddr, |
734d1868 | 1861 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1862 | prefetch(skb->data); |
cd28ab6a | 1863 | |
793b883e | 1864 | re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data, |
734d1868 | 1865 | sky2->rx_bufsize, PCI_DMA_FROMDEVICE); |
793b883e | 1866 | } |
cd28ab6a | 1867 | |
79e57d32 | 1868 | skb_put(skb, length); |
793b883e | 1869 | resubmit: |
d11c13e7 | 1870 | re->skb->ip_summed = CHECKSUM_NONE; |
734d1868 | 1871 | sky2_rx_add(sky2, re->mapaddr); |
79e57d32 | 1872 | |
bea86103 | 1873 | /* Tell receiver about new buffers. */ |
290d4de5 | 1874 | sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put); |
bea86103 | 1875 | |
cd28ab6a SH |
1876 | return skb; |
1877 | ||
6e15b712 SH |
1878 | oversize: |
1879 | ++sky2->net_stats.rx_over_errors; | |
1880 | goto resubmit; | |
1881 | ||
cd28ab6a | 1882 | error: |
6e15b712 SH |
1883 | ++sky2->net_stats.rx_errors; |
1884 | ||
3be92a70 | 1885 | if (netif_msg_rx_err(sky2) && net_ratelimit()) |
cd28ab6a SH |
1886 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", |
1887 | sky2->netdev->name, status, length); | |
793b883e SH |
1888 | |
1889 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) | |
cd28ab6a SH |
1890 | sky2->net_stats.rx_length_errors++; |
1891 | if (status & GMR_FS_FRAGMENT) | |
1892 | sky2->net_stats.rx_frame_errors++; | |
1893 | if (status & GMR_FS_CRC_ERR) | |
1894 | sky2->net_stats.rx_crc_errors++; | |
793b883e SH |
1895 | if (status & GMR_FS_RX_FF_OV) |
1896 | sky2->net_stats.rx_fifo_errors++; | |
79e57d32 | 1897 | |
793b883e | 1898 | goto resubmit; |
cd28ab6a SH |
1899 | } |
1900 | ||
e07b1aa8 SH |
1901 | /* Transmit complete */ |
1902 | static inline void sky2_tx_done(struct net_device *dev, u16 last) | |
13b97b74 | 1903 | { |
e07b1aa8 | 1904 | struct sky2_port *sky2 = netdev_priv(dev); |
302d1252 | 1905 | |
e07b1aa8 SH |
1906 | if (netif_running(dev)) { |
1907 | spin_lock(&sky2->tx_lock); | |
1908 | sky2_tx_complete(sky2, last); | |
1909 | spin_unlock(&sky2->tx_lock); | |
2224795d | 1910 | } |
cd28ab6a SH |
1911 | } |
1912 | ||
e07b1aa8 SH |
1913 | /* Process status response ring */ |
1914 | static int sky2_status_intr(struct sky2_hw *hw, int to_do) | |
cd28ab6a | 1915 | { |
e07b1aa8 | 1916 | int work_done = 0; |
e71ebd73 | 1917 | u16 hwidx = sky2_read16(hw, STAT_PUT_IDX); |
a8fd6266 | 1918 | |
af2a58ac | 1919 | rmb(); |
bea86103 | 1920 | |
e71ebd73 | 1921 | while (hw->st_idx != hwidx) { |
13210ce5 SH |
1922 | struct sky2_status_le *le = hw->st_le + hw->st_idx; |
1923 | struct net_device *dev; | |
d11c13e7 | 1924 | struct sky2_port *sky2; |
cd28ab6a | 1925 | struct sk_buff *skb; |
cd28ab6a SH |
1926 | u32 status; |
1927 | u16 length; | |
1928 | ||
cb5d9547 | 1929 | hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE); |
bea86103 | 1930 | |
e71ebd73 SH |
1931 | BUG_ON(le->link >= 2); |
1932 | dev = hw->dev[le->link]; | |
13210ce5 SH |
1933 | |
1934 | sky2 = netdev_priv(dev); | |
e07b1aa8 SH |
1935 | length = le->length; |
1936 | status = le->status; | |
cd28ab6a | 1937 | |
e71ebd73 | 1938 | switch (le->opcode & ~HW_OWNER) { |
cd28ab6a | 1939 | case OP_RXSTAT: |
d11c13e7 | 1940 | skb = sky2_receive(sky2, length, status); |
d1f13708 SH |
1941 | if (!skb) |
1942 | break; | |
13210ce5 SH |
1943 | |
1944 | skb->dev = dev; | |
1945 | skb->protocol = eth_type_trans(skb, dev); | |
1946 | dev->last_rx = jiffies; | |
1947 | ||
d1f13708 SH |
1948 | #ifdef SKY2_VLAN_TAG_USED |
1949 | if (sky2->vlgrp && (status & GMR_FS_VLAN)) { | |
1950 | vlan_hwaccel_receive_skb(skb, | |
1951 | sky2->vlgrp, | |
1952 | be16_to_cpu(sky2->rx_tag)); | |
1953 | } else | |
1954 | #endif | |
cd28ab6a | 1955 | netif_receive_skb(skb); |
13210ce5 SH |
1956 | |
1957 | if (++work_done >= to_do) | |
1958 | goto exit_loop; | |
cd28ab6a SH |
1959 | break; |
1960 | ||
d1f13708 SH |
1961 | #ifdef SKY2_VLAN_TAG_USED |
1962 | case OP_RXVLAN: | |
1963 | sky2->rx_tag = length; | |
1964 | break; | |
1965 | ||
1966 | case OP_RXCHKSVLAN: | |
1967 | sky2->rx_tag = length; | |
1968 | /* fall through */ | |
1969 | #endif | |
cd28ab6a | 1970 | case OP_RXCHKS: |
d11c13e7 SH |
1971 | skb = sky2->rx_ring[sky2->rx_next].skb; |
1972 | skb->ip_summed = CHECKSUM_HW; | |
1973 | skb->csum = le16_to_cpu(status); | |
cd28ab6a SH |
1974 | break; |
1975 | ||
1976 | case OP_TXINDEXLE: | |
13b97b74 | 1977 | /* TX index reports status for both ports */ |
f55925d7 SH |
1978 | BUILD_BUG_ON(TX_RING_SIZE > 0x1000); |
1979 | sky2_tx_done(hw->dev[0], status & 0xfff); | |
e07b1aa8 SH |
1980 | if (hw->dev[1]) |
1981 | sky2_tx_done(hw->dev[1], | |
1982 | ((status >> 24) & 0xff) | |
1983 | | (u16)(length & 0xf) << 8); | |
cd28ab6a SH |
1984 | break; |
1985 | ||
cd28ab6a SH |
1986 | default: |
1987 | if (net_ratelimit()) | |
793b883e | 1988 | printk(KERN_WARNING PFX |
e71ebd73 SH |
1989 | "unknown status opcode 0x%x\n", le->opcode); |
1990 | goto exit_loop; | |
cd28ab6a | 1991 | } |
13210ce5 | 1992 | } |
cd28ab6a | 1993 | |
13210ce5 | 1994 | exit_loop: |
e07b1aa8 | 1995 | return work_done; |
cd28ab6a SH |
1996 | } |
1997 | ||
1998 | static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status) | |
1999 | { | |
2000 | struct net_device *dev = hw->dev[port]; | |
2001 | ||
3be92a70 SH |
2002 | if (net_ratelimit()) |
2003 | printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n", | |
2004 | dev->name, status); | |
cd28ab6a SH |
2005 | |
2006 | if (status & Y2_IS_PAR_RD1) { | |
3be92a70 SH |
2007 | if (net_ratelimit()) |
2008 | printk(KERN_ERR PFX "%s: ram data read parity error\n", | |
2009 | dev->name); | |
cd28ab6a SH |
2010 | /* Clear IRQ */ |
2011 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR); | |
2012 | } | |
2013 | ||
2014 | if (status & Y2_IS_PAR_WR1) { | |
3be92a70 SH |
2015 | if (net_ratelimit()) |
2016 | printk(KERN_ERR PFX "%s: ram data write parity error\n", | |
2017 | dev->name); | |
cd28ab6a SH |
2018 | |
2019 | sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR); | |
2020 | } | |
2021 | ||
2022 | if (status & Y2_IS_PAR_MAC1) { | |
3be92a70 SH |
2023 | if (net_ratelimit()) |
2024 | printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name); | |
cd28ab6a SH |
2025 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE); |
2026 | } | |
2027 | ||
2028 | if (status & Y2_IS_PAR_RX1) { | |
3be92a70 SH |
2029 | if (net_ratelimit()) |
2030 | printk(KERN_ERR PFX "%s: RX parity error\n", dev->name); | |
cd28ab6a SH |
2031 | sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR); |
2032 | } | |
2033 | ||
2034 | if (status & Y2_IS_TCP_TXA1) { | |
3be92a70 SH |
2035 | if (net_ratelimit()) |
2036 | printk(KERN_ERR PFX "%s: TCP segmentation error\n", | |
2037 | dev->name); | |
cd28ab6a SH |
2038 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP); |
2039 | } | |
2040 | } | |
2041 | ||
2042 | static void sky2_hw_intr(struct sky2_hw *hw) | |
2043 | { | |
2044 | u32 status = sky2_read32(hw, B0_HWE_ISRC); | |
2045 | ||
793b883e | 2046 | if (status & Y2_IS_TIST_OV) |
cd28ab6a | 2047 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2048 | |
2049 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | |
793b883e SH |
2050 | u16 pci_err; |
2051 | ||
56a645cc | 2052 | pci_err = sky2_pci_read16(hw, PCI_STATUS); |
3be92a70 SH |
2053 | if (net_ratelimit()) |
2054 | printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n", | |
2055 | pci_name(hw->pdev), pci_err); | |
cd28ab6a SH |
2056 | |
2057 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
56a645cc | 2058 | sky2_pci_write16(hw, PCI_STATUS, |
793b883e | 2059 | pci_err | PCI_STATUS_ERROR_BITS); |
cd28ab6a SH |
2060 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2061 | } | |
2062 | ||
2063 | if (status & Y2_IS_PCI_EXP) { | |
d571b694 | 2064 | /* PCI-Express uncorrectable Error occurred */ |
793b883e SH |
2065 | u32 pex_err; |
2066 | ||
56a645cc | 2067 | pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT); |
cd28ab6a | 2068 | |
3be92a70 SH |
2069 | if (net_ratelimit()) |
2070 | printk(KERN_ERR PFX "%s: pci express error (0x%x)\n", | |
2071 | pci_name(hw->pdev), pex_err); | |
cd28ab6a SH |
2072 | |
2073 | /* clear the interrupt */ | |
2074 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | |
56a645cc | 2075 | sky2_pci_write32(hw, PEX_UNC_ERR_STAT, |
793b883e | 2076 | 0xffffffffUL); |
cd28ab6a SH |
2077 | sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
2078 | ||
2079 | if (pex_err & PEX_FATAL_ERRORS) { | |
2080 | u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK); | |
2081 | hwmsk &= ~Y2_IS_PCI_EXP; | |
2082 | sky2_write32(hw, B0_HWE_IMSK, hwmsk); | |
2083 | } | |
2084 | } | |
2085 | ||
2086 | if (status & Y2_HWE_L1_MASK) | |
2087 | sky2_hw_error(hw, 0, status); | |
2088 | status >>= 8; | |
2089 | if (status & Y2_HWE_L1_MASK) | |
2090 | sky2_hw_error(hw, 1, status); | |
2091 | } | |
2092 | ||
2093 | static void sky2_mac_intr(struct sky2_hw *hw, unsigned port) | |
2094 | { | |
2095 | struct net_device *dev = hw->dev[port]; | |
2096 | struct sky2_port *sky2 = netdev_priv(dev); | |
2097 | u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC)); | |
2098 | ||
2099 | if (netif_msg_intr(sky2)) | |
2100 | printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n", | |
2101 | dev->name, status); | |
2102 | ||
2103 | if (status & GM_IS_RX_FF_OR) { | |
2104 | ++sky2->net_stats.rx_fifo_errors; | |
2105 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO); | |
2106 | } | |
2107 | ||
2108 | if (status & GM_IS_TX_FF_UR) { | |
2109 | ++sky2->net_stats.tx_fifo_errors; | |
2110 | sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU); | |
2111 | } | |
cd28ab6a SH |
2112 | } |
2113 | ||
d257924e SH |
2114 | /* This should never happen it is a fatal situation */ |
2115 | static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port, | |
2116 | const char *rxtx, u32 mask) | |
2117 | { | |
2118 | struct net_device *dev = hw->dev[port]; | |
2119 | struct sky2_port *sky2 = netdev_priv(dev); | |
2120 | u32 imask; | |
2121 | ||
2122 | printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n", | |
2123 | dev ? dev->name : "<not registered>", rxtx); | |
2124 | ||
2125 | imask = sky2_read32(hw, B0_IMSK); | |
2126 | imask &= ~mask; | |
2127 | sky2_write32(hw, B0_IMSK, imask); | |
2128 | ||
2129 | if (dev) { | |
2130 | spin_lock(&sky2->phy_lock); | |
2131 | sky2_link_down(sky2); | |
2132 | spin_unlock(&sky2->phy_lock); | |
2133 | } | |
2134 | } | |
cd28ab6a | 2135 | |
d27ed387 SH |
2136 | /* If idle then force a fake soft NAPI poll once a second |
2137 | * to work around cases where sharing an edge triggered interrupt. | |
2138 | */ | |
2139 | static void sky2_idle(unsigned long arg) | |
2140 | { | |
01bd7564 SH |
2141 | struct sky2_hw *hw = (struct sky2_hw *) arg; |
2142 | struct net_device *dev = hw->dev[0]; | |
d27ed387 | 2143 | |
d27ed387 SH |
2144 | if (__netif_rx_schedule_prep(dev)) |
2145 | __netif_rx_schedule(dev); | |
01bd7564 SH |
2146 | |
2147 | mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout)); | |
d27ed387 SH |
2148 | } |
2149 | ||
2150 | ||
e07b1aa8 | 2151 | static int sky2_poll(struct net_device *dev0, int *budget) |
cd28ab6a | 2152 | { |
e07b1aa8 SH |
2153 | struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw; |
2154 | int work_limit = min(dev0->quota, *budget); | |
2155 | int work_done = 0; | |
fb2690a9 | 2156 | u32 status = sky2_read32(hw, B0_Y2_SP_EISR); |
cd28ab6a | 2157 | |
1e5f1283 SH |
2158 | if (status & Y2_IS_HW_ERR) |
2159 | sky2_hw_intr(hw); | |
d257924e | 2160 | |
1e5f1283 SH |
2161 | if (status & Y2_IS_IRQ_PHY1) |
2162 | sky2_phy_intr(hw, 0); | |
cd28ab6a | 2163 | |
1e5f1283 SH |
2164 | if (status & Y2_IS_IRQ_PHY2) |
2165 | sky2_phy_intr(hw, 1); | |
cd28ab6a | 2166 | |
1e5f1283 SH |
2167 | if (status & Y2_IS_IRQ_MAC1) |
2168 | sky2_mac_intr(hw, 0); | |
cd28ab6a | 2169 | |
1e5f1283 SH |
2170 | if (status & Y2_IS_IRQ_MAC2) |
2171 | sky2_mac_intr(hw, 1); | |
cd28ab6a | 2172 | |
1e5f1283 SH |
2173 | if (status & Y2_IS_CHK_RX1) |
2174 | sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1); | |
d257924e | 2175 | |
1e5f1283 SH |
2176 | if (status & Y2_IS_CHK_RX2) |
2177 | sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2); | |
d257924e | 2178 | |
1e5f1283 SH |
2179 | if (status & Y2_IS_CHK_TXA1) |
2180 | sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1); | |
d257924e | 2181 | |
1e5f1283 SH |
2182 | if (status & Y2_IS_CHK_TXA2) |
2183 | sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2); | |
cd28ab6a | 2184 | |
1e5f1283 SH |
2185 | if (status & Y2_IS_STAT_BMU) |
2186 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); | |
e07b1aa8 | 2187 | |
1e5f1283 SH |
2188 | work_done = sky2_status_intr(hw, work_limit); |
2189 | *budget -= work_done; | |
2190 | dev0->quota -= work_done; | |
e07b1aa8 | 2191 | |
1e5f1283 SH |
2192 | if (work_done >= work_limit) |
2193 | return 1; | |
e07b1aa8 | 2194 | |
d3240312 | 2195 | netif_rx_complete(dev0); |
e07b1aa8 | 2196 | |
fb2690a9 | 2197 | status = sky2_read32(hw, B0_Y2_SP_LISR); |
e07b1aa8 SH |
2198 | return 0; |
2199 | } | |
2200 | ||
2201 | static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) | |
2202 | { | |
2203 | struct sky2_hw *hw = dev_id; | |
2204 | struct net_device *dev0 = hw->dev[0]; | |
2205 | u32 status; | |
2206 | ||
2207 | /* Reading this mask interrupts as side effect */ | |
2208 | status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
2209 | if (status == 0 || status == ~0) | |
2210 | return IRQ_NONE; | |
793b883e | 2211 | |
e07b1aa8 SH |
2212 | prefetch(&hw->st_le[hw->st_idx]); |
2213 | if (likely(__netif_rx_schedule_prep(dev0))) | |
2214 | __netif_rx_schedule(dev0); | |
793b883e | 2215 | |
cd28ab6a SH |
2216 | return IRQ_HANDLED; |
2217 | } | |
2218 | ||
2219 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
2220 | static void sky2_netpoll(struct net_device *dev) | |
2221 | { | |
2222 | struct sky2_port *sky2 = netdev_priv(dev); | |
2223 | ||
793b883e | 2224 | sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL); |
cd28ab6a SH |
2225 | } |
2226 | #endif | |
2227 | ||
2228 | /* Chip internal frequency for clock calculations */ | |
fb17358f | 2229 | static inline u32 sky2_mhz(const struct sky2_hw *hw) |
cd28ab6a | 2230 | { |
793b883e | 2231 | switch (hw->chip_id) { |
cd28ab6a | 2232 | case CHIP_ID_YUKON_EC: |
5a5b1ea0 | 2233 | case CHIP_ID_YUKON_EC_U: |
fb17358f | 2234 | return 125; /* 125 Mhz */ |
cd28ab6a | 2235 | case CHIP_ID_YUKON_FE: |
fb17358f | 2236 | return 100; /* 100 Mhz */ |
793b883e | 2237 | default: /* YUKON_XL */ |
fb17358f | 2238 | return 156; /* 156 Mhz */ |
cd28ab6a SH |
2239 | } |
2240 | } | |
2241 | ||
fb17358f | 2242 | static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us) |
cd28ab6a | 2243 | { |
fb17358f | 2244 | return sky2_mhz(hw) * us; |
cd28ab6a SH |
2245 | } |
2246 | ||
fb17358f | 2247 | static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) |
cd28ab6a | 2248 | { |
fb17358f | 2249 | return clk / sky2_mhz(hw); |
cd28ab6a SH |
2250 | } |
2251 | ||
fb17358f | 2252 | |
98712e5e | 2253 | static int __devinit sky2_reset(struct sky2_hw *hw) |
cd28ab6a | 2254 | { |
cd28ab6a SH |
2255 | u16 status; |
2256 | u8 t8, pmd_type; | |
56a645cc | 2257 | int i; |
cd28ab6a | 2258 | |
cd28ab6a | 2259 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
08c06d8a | 2260 | |
cd28ab6a SH |
2261 | hw->chip_id = sky2_read8(hw, B2_CHIP_ID); |
2262 | if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) { | |
2263 | printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n", | |
2264 | pci_name(hw->pdev), hw->chip_id); | |
2265 | return -EOPNOTSUPP; | |
2266 | } | |
2267 | ||
290d4de5 SH |
2268 | hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4; |
2269 | ||
2270 | /* This rev is really old, and requires untested workarounds */ | |
2271 | if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) { | |
2272 | printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n", | |
2273 | pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], | |
2274 | hw->chip_id, hw->chip_rev); | |
2275 | return -EOPNOTSUPP; | |
2276 | } | |
2277 | ||
cd28ab6a SH |
2278 | /* disable ASF */ |
2279 | if (hw->chip_id <= CHIP_ID_YUKON_EC) { | |
2280 | sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); | |
2281 | sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE); | |
2282 | } | |
2283 | ||
2284 | /* do a SW reset */ | |
2285 | sky2_write8(hw, B0_CTST, CS_RST_SET); | |
2286 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | |
2287 | ||
2288 | /* clear PCI errors, if any */ | |
56a645cc | 2289 | status = sky2_pci_read16(hw, PCI_STATUS); |
2d42d21f | 2290 | |
cd28ab6a | 2291 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
56a645cc SH |
2292 | sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS); |
2293 | ||
cd28ab6a SH |
2294 | |
2295 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | |
2296 | ||
2297 | /* clear any PEX errors */ | |
d89e1343 | 2298 | if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP)) |
56a645cc SH |
2299 | sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL); |
2300 | ||
cd28ab6a SH |
2301 | |
2302 | pmd_type = sky2_read8(hw, B2_PMD_TYP); | |
2303 | hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); | |
2304 | ||
2305 | hw->ports = 1; | |
2306 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | |
2307 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | |
2308 | if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) | |
2309 | ++hw->ports; | |
2310 | } | |
cd28ab6a | 2311 | |
5afa0a9c | 2312 | sky2_set_power_state(hw, PCI_D0); |
cd28ab6a SH |
2313 | |
2314 | for (i = 0; i < hw->ports; i++) { | |
2315 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET); | |
2316 | sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR); | |
2317 | } | |
2318 | ||
2319 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | |
2320 | ||
793b883e SH |
2321 | /* Clear I2C IRQ noise */ |
2322 | sky2_write32(hw, B2_I2C_IRQ, 1); | |
cd28ab6a SH |
2323 | |
2324 | /* turn off hardware timer (unused) */ | |
2325 | sky2_write8(hw, B2_TI_CTRL, TIM_STOP); | |
2326 | sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ); | |
793b883e | 2327 | |
cd28ab6a SH |
2328 | sky2_write8(hw, B0_Y2LED, LED_STAT_ON); |
2329 | ||
69634ee7 SH |
2330 | /* Turn off descriptor polling */ |
2331 | sky2_write32(hw, B28_DPT_CTRL, DPT_STOP); | |
cd28ab6a SH |
2332 | |
2333 | /* Turn off receive timestamp */ | |
2334 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP); | |
793b883e | 2335 | sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); |
cd28ab6a SH |
2336 | |
2337 | /* enable the Tx Arbiters */ | |
2338 | for (i = 0; i < hw->ports; i++) | |
2339 | sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB); | |
2340 | ||
2341 | /* Initialize ram interface */ | |
2342 | for (i = 0; i < hw->ports; i++) { | |
793b883e | 2343 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); |
cd28ab6a SH |
2344 | |
2345 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53); | |
2346 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53); | |
2347 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53); | |
2348 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53); | |
2349 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53); | |
2350 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53); | |
2351 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53); | |
2352 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53); | |
2353 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53); | |
2354 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53); | |
2355 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53); | |
2356 | sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53); | |
2357 | } | |
2358 | ||
cd28ab6a SH |
2359 | sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); |
2360 | ||
cd28ab6a SH |
2361 | for (i = 0; i < hw->ports; i++) |
2362 | sky2_phy_reset(hw, i); | |
cd28ab6a | 2363 | |
cd28ab6a SH |
2364 | memset(hw->st_le, 0, STATUS_LE_BYTES); |
2365 | hw->st_idx = 0; | |
2366 | ||
2367 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET); | |
2368 | sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR); | |
2369 | ||
2370 | sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma); | |
793b883e | 2371 | sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32); |
cd28ab6a SH |
2372 | |
2373 | /* Set the list last index */ | |
793b883e | 2374 | sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1); |
cd28ab6a | 2375 | |
290d4de5 SH |
2376 | sky2_write16(hw, STAT_TX_IDX_TH, 10); |
2377 | sky2_write8(hw, STAT_FIFO_WM, 16); | |
cd28ab6a | 2378 | |
290d4de5 SH |
2379 | /* set Status-FIFO ISR watermark */ |
2380 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0) | |
2381 | sky2_write8(hw, STAT_FIFO_ISR_WM, 4); | |
2382 | else | |
2383 | sky2_write8(hw, STAT_FIFO_ISR_WM, 16); | |
cd28ab6a | 2384 | |
290d4de5 | 2385 | sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000)); |
77b3d6a2 SH |
2386 | sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20)); |
2387 | sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100)); | |
cd28ab6a | 2388 | |
793b883e | 2389 | /* enable status unit */ |
cd28ab6a SH |
2390 | sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON); |
2391 | ||
2392 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2393 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2394 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2395 | ||
2396 | return 0; | |
2397 | } | |
2398 | ||
28bd181a | 2399 | static u32 sky2_supported_modes(const struct sky2_hw *hw) |
cd28ab6a SH |
2400 | { |
2401 | u32 modes; | |
2402 | if (hw->copper) { | |
793b883e SH |
2403 | modes = SUPPORTED_10baseT_Half |
2404 | | SUPPORTED_10baseT_Full | |
2405 | | SUPPORTED_100baseT_Half | |
2406 | | SUPPORTED_100baseT_Full | |
2407 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2408 | |
2409 | if (hw->chip_id != CHIP_ID_YUKON_FE) | |
2410 | modes |= SUPPORTED_1000baseT_Half | |
793b883e | 2411 | | SUPPORTED_1000baseT_Full; |
cd28ab6a SH |
2412 | } else |
2413 | modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | |
793b883e | 2414 | | SUPPORTED_Autoneg; |
cd28ab6a SH |
2415 | return modes; |
2416 | } | |
2417 | ||
793b883e | 2418 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
cd28ab6a SH |
2419 | { |
2420 | struct sky2_port *sky2 = netdev_priv(dev); | |
2421 | struct sky2_hw *hw = sky2->hw; | |
2422 | ||
2423 | ecmd->transceiver = XCVR_INTERNAL; | |
2424 | ecmd->supported = sky2_supported_modes(hw); | |
2425 | ecmd->phy_address = PHY_ADDR_MARV; | |
2426 | if (hw->copper) { | |
2427 | ecmd->supported = SUPPORTED_10baseT_Half | |
793b883e SH |
2428 | | SUPPORTED_10baseT_Full |
2429 | | SUPPORTED_100baseT_Half | |
2430 | | SUPPORTED_100baseT_Full | |
2431 | | SUPPORTED_1000baseT_Half | |
2432 | | SUPPORTED_1000baseT_Full | |
2433 | | SUPPORTED_Autoneg | SUPPORTED_TP; | |
cd28ab6a SH |
2434 | ecmd->port = PORT_TP; |
2435 | } else | |
2436 | ecmd->port = PORT_FIBRE; | |
2437 | ||
2438 | ecmd->advertising = sky2->advertising; | |
2439 | ecmd->autoneg = sky2->autoneg; | |
2440 | ecmd->speed = sky2->speed; | |
2441 | ecmd->duplex = sky2->duplex; | |
2442 | return 0; | |
2443 | } | |
2444 | ||
2445 | static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |
2446 | { | |
2447 | struct sky2_port *sky2 = netdev_priv(dev); | |
2448 | const struct sky2_hw *hw = sky2->hw; | |
2449 | u32 supported = sky2_supported_modes(hw); | |
2450 | ||
2451 | if (ecmd->autoneg == AUTONEG_ENABLE) { | |
2452 | ecmd->advertising = supported; | |
2453 | sky2->duplex = -1; | |
2454 | sky2->speed = -1; | |
2455 | } else { | |
2456 | u32 setting; | |
2457 | ||
793b883e | 2458 | switch (ecmd->speed) { |
cd28ab6a SH |
2459 | case SPEED_1000: |
2460 | if (ecmd->duplex == DUPLEX_FULL) | |
2461 | setting = SUPPORTED_1000baseT_Full; | |
2462 | else if (ecmd->duplex == DUPLEX_HALF) | |
2463 | setting = SUPPORTED_1000baseT_Half; | |
2464 | else | |
2465 | return -EINVAL; | |
2466 | break; | |
2467 | case SPEED_100: | |
2468 | if (ecmd->duplex == DUPLEX_FULL) | |
2469 | setting = SUPPORTED_100baseT_Full; | |
2470 | else if (ecmd->duplex == DUPLEX_HALF) | |
2471 | setting = SUPPORTED_100baseT_Half; | |
2472 | else | |
2473 | return -EINVAL; | |
2474 | break; | |
2475 | ||
2476 | case SPEED_10: | |
2477 | if (ecmd->duplex == DUPLEX_FULL) | |
2478 | setting = SUPPORTED_10baseT_Full; | |
2479 | else if (ecmd->duplex == DUPLEX_HALF) | |
2480 | setting = SUPPORTED_10baseT_Half; | |
2481 | else | |
2482 | return -EINVAL; | |
2483 | break; | |
2484 | default: | |
2485 | return -EINVAL; | |
2486 | } | |
2487 | ||
2488 | if ((setting & supported) == 0) | |
2489 | return -EINVAL; | |
2490 | ||
2491 | sky2->speed = ecmd->speed; | |
2492 | sky2->duplex = ecmd->duplex; | |
2493 | } | |
2494 | ||
2495 | sky2->autoneg = ecmd->autoneg; | |
2496 | sky2->advertising = ecmd->advertising; | |
2497 | ||
1b537565 SH |
2498 | if (netif_running(dev)) |
2499 | sky2_phy_reinit(sky2); | |
cd28ab6a SH |
2500 | |
2501 | return 0; | |
2502 | } | |
2503 | ||
2504 | static void sky2_get_drvinfo(struct net_device *dev, | |
2505 | struct ethtool_drvinfo *info) | |
2506 | { | |
2507 | struct sky2_port *sky2 = netdev_priv(dev); | |
2508 | ||
2509 | strcpy(info->driver, DRV_NAME); | |
2510 | strcpy(info->version, DRV_VERSION); | |
2511 | strcpy(info->fw_version, "N/A"); | |
2512 | strcpy(info->bus_info, pci_name(sky2->hw->pdev)); | |
2513 | } | |
2514 | ||
2515 | static const struct sky2_stat { | |
793b883e SH |
2516 | char name[ETH_GSTRING_LEN]; |
2517 | u16 offset; | |
cd28ab6a SH |
2518 | } sky2_stats[] = { |
2519 | { "tx_bytes", GM_TXO_OK_HI }, | |
2520 | { "rx_bytes", GM_RXO_OK_HI }, | |
2521 | { "tx_broadcast", GM_TXF_BC_OK }, | |
2522 | { "rx_broadcast", GM_RXF_BC_OK }, | |
2523 | { "tx_multicast", GM_TXF_MC_OK }, | |
2524 | { "rx_multicast", GM_RXF_MC_OK }, | |
2525 | { "tx_unicast", GM_TXF_UC_OK }, | |
2526 | { "rx_unicast", GM_RXF_UC_OK }, | |
2527 | { "tx_mac_pause", GM_TXF_MPAUSE }, | |
2528 | { "rx_mac_pause", GM_RXF_MPAUSE }, | |
eadfa7dd | 2529 | { "collisions", GM_TXF_COL }, |
cd28ab6a SH |
2530 | { "late_collision",GM_TXF_LAT_COL }, |
2531 | { "aborted", GM_TXF_ABO_COL }, | |
eadfa7dd | 2532 | { "single_collisions", GM_TXF_SNG_COL }, |
cd28ab6a | 2533 | { "multi_collisions", GM_TXF_MUL_COL }, |
eadfa7dd | 2534 | |
d2604540 | 2535 | { "rx_short", GM_RXF_SHT }, |
cd28ab6a | 2536 | { "rx_runt", GM_RXE_FRAG }, |
eadfa7dd SH |
2537 | { "rx_64_byte_packets", GM_RXF_64B }, |
2538 | { "rx_65_to_127_byte_packets", GM_RXF_127B }, | |
2539 | { "rx_128_to_255_byte_packets", GM_RXF_255B }, | |
2540 | { "rx_256_to_511_byte_packets", GM_RXF_511B }, | |
2541 | { "rx_512_to_1023_byte_packets", GM_RXF_1023B }, | |
2542 | { "rx_1024_to_1518_byte_packets", GM_RXF_1518B }, | |
2543 | { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ }, | |
cd28ab6a | 2544 | { "rx_too_long", GM_RXF_LNG_ERR }, |
eadfa7dd SH |
2545 | { "rx_fifo_overflow", GM_RXE_FIFO_OV }, |
2546 | { "rx_jabber", GM_RXF_JAB_PKT }, | |
cd28ab6a | 2547 | { "rx_fcs_error", GM_RXF_FCS_ERR }, |
eadfa7dd SH |
2548 | |
2549 | { "tx_64_byte_packets", GM_TXF_64B }, | |
2550 | { "tx_65_to_127_byte_packets", GM_TXF_127B }, | |
2551 | { "tx_128_to_255_byte_packets", GM_TXF_255B }, | |
2552 | { "tx_256_to_511_byte_packets", GM_TXF_511B }, | |
2553 | { "tx_512_to_1023_byte_packets", GM_TXF_1023B }, | |
2554 | { "tx_1024_to_1518_byte_packets", GM_TXF_1518B }, | |
2555 | { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ }, | |
2556 | { "tx_fifo_underrun", GM_TXE_FIFO_UR }, | |
cd28ab6a SH |
2557 | }; |
2558 | ||
cd28ab6a SH |
2559 | static u32 sky2_get_rx_csum(struct net_device *dev) |
2560 | { | |
2561 | struct sky2_port *sky2 = netdev_priv(dev); | |
2562 | ||
2563 | return sky2->rx_csum; | |
2564 | } | |
2565 | ||
2566 | static int sky2_set_rx_csum(struct net_device *dev, u32 data) | |
2567 | { | |
2568 | struct sky2_port *sky2 = netdev_priv(dev); | |
2569 | ||
2570 | sky2->rx_csum = data; | |
793b883e | 2571 | |
cd28ab6a SH |
2572 | sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), |
2573 | data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM); | |
2574 | ||
2575 | return 0; | |
2576 | } | |
2577 | ||
2578 | static u32 sky2_get_msglevel(struct net_device *netdev) | |
2579 | { | |
2580 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2581 | return sky2->msg_enable; | |
2582 | } | |
2583 | ||
9a7ae0a9 SH |
2584 | static int sky2_nway_reset(struct net_device *dev) |
2585 | { | |
2586 | struct sky2_port *sky2 = netdev_priv(dev); | |
9a7ae0a9 SH |
2587 | |
2588 | if (sky2->autoneg != AUTONEG_ENABLE) | |
2589 | return -EINVAL; | |
2590 | ||
1b537565 | 2591 | sky2_phy_reinit(sky2); |
9a7ae0a9 SH |
2592 | |
2593 | return 0; | |
2594 | } | |
2595 | ||
793b883e | 2596 | static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count) |
cd28ab6a SH |
2597 | { |
2598 | struct sky2_hw *hw = sky2->hw; | |
2599 | unsigned port = sky2->port; | |
2600 | int i; | |
2601 | ||
2602 | data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32 | |
793b883e | 2603 | | (u64) gma_read32(hw, port, GM_TXO_OK_LO); |
cd28ab6a | 2604 | data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32 |
793b883e | 2605 | | (u64) gma_read32(hw, port, GM_RXO_OK_LO); |
cd28ab6a | 2606 | |
793b883e | 2607 | for (i = 2; i < count; i++) |
cd28ab6a SH |
2608 | data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset); |
2609 | } | |
2610 | ||
cd28ab6a SH |
2611 | static void sky2_set_msglevel(struct net_device *netdev, u32 value) |
2612 | { | |
2613 | struct sky2_port *sky2 = netdev_priv(netdev); | |
2614 | sky2->msg_enable = value; | |
2615 | } | |
2616 | ||
2617 | static int sky2_get_stats_count(struct net_device *dev) | |
2618 | { | |
2619 | return ARRAY_SIZE(sky2_stats); | |
2620 | } | |
2621 | ||
2622 | static void sky2_get_ethtool_stats(struct net_device *dev, | |
793b883e | 2623 | struct ethtool_stats *stats, u64 * data) |
cd28ab6a SH |
2624 | { |
2625 | struct sky2_port *sky2 = netdev_priv(dev); | |
2626 | ||
793b883e | 2627 | sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats)); |
cd28ab6a SH |
2628 | } |
2629 | ||
793b883e | 2630 | static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data) |
cd28ab6a SH |
2631 | { |
2632 | int i; | |
2633 | ||
2634 | switch (stringset) { | |
2635 | case ETH_SS_STATS: | |
2636 | for (i = 0; i < ARRAY_SIZE(sky2_stats); i++) | |
2637 | memcpy(data + i * ETH_GSTRING_LEN, | |
2638 | sky2_stats[i].name, ETH_GSTRING_LEN); | |
2639 | break; | |
2640 | } | |
2641 | } | |
2642 | ||
2643 | /* Use hardware MIB variables for critical path statistics and | |
2644 | * transmit feedback not reported at interrupt. | |
2645 | * Other errors are accounted for in interrupt handler. | |
2646 | */ | |
2647 | static struct net_device_stats *sky2_get_stats(struct net_device *dev) | |
2648 | { | |
2649 | struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2650 | u64 data[13]; |
cd28ab6a | 2651 | |
793b883e | 2652 | sky2_phy_stats(sky2, data, ARRAY_SIZE(data)); |
cd28ab6a SH |
2653 | |
2654 | sky2->net_stats.tx_bytes = data[0]; | |
2655 | sky2->net_stats.rx_bytes = data[1]; | |
2656 | sky2->net_stats.tx_packets = data[2] + data[4] + data[6]; | |
2657 | sky2->net_stats.rx_packets = data[3] + data[5] + data[7]; | |
050ff180 | 2658 | sky2->net_stats.multicast = data[3] + data[5]; |
cd28ab6a SH |
2659 | sky2->net_stats.collisions = data[10]; |
2660 | sky2->net_stats.tx_aborted_errors = data[12]; | |
2661 | ||
2662 | return &sky2->net_stats; | |
2663 | } | |
2664 | ||
2665 | static int sky2_set_mac_address(struct net_device *dev, void *p) | |
2666 | { | |
2667 | struct sky2_port *sky2 = netdev_priv(dev); | |
a8ab1ec0 SH |
2668 | struct sky2_hw *hw = sky2->hw; |
2669 | unsigned port = sky2->port; | |
2670 | const struct sockaddr *addr = p; | |
cd28ab6a SH |
2671 | |
2672 | if (!is_valid_ether_addr(addr->sa_data)) | |
2673 | return -EADDRNOTAVAIL; | |
2674 | ||
cd28ab6a | 2675 | memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); |
a8ab1ec0 | 2676 | memcpy_toio(hw->regs + B2_MAC_1 + port * 8, |
cd28ab6a | 2677 | dev->dev_addr, ETH_ALEN); |
a8ab1ec0 | 2678 | memcpy_toio(hw->regs + B2_MAC_2 + port * 8, |
cd28ab6a | 2679 | dev->dev_addr, ETH_ALEN); |
1b537565 | 2680 | |
a8ab1ec0 SH |
2681 | /* virtual address for data */ |
2682 | gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr); | |
2683 | ||
2684 | /* physical address: used for pause frames */ | |
2685 | gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr); | |
1b537565 SH |
2686 | |
2687 | return 0; | |
cd28ab6a SH |
2688 | } |
2689 | ||
2690 | static void sky2_set_multicast(struct net_device *dev) | |
2691 | { | |
2692 | struct sky2_port *sky2 = netdev_priv(dev); | |
2693 | struct sky2_hw *hw = sky2->hw; | |
2694 | unsigned port = sky2->port; | |
2695 | struct dev_mc_list *list = dev->mc_list; | |
2696 | u16 reg; | |
2697 | u8 filter[8]; | |
2698 | ||
2699 | memset(filter, 0, sizeof(filter)); | |
2700 | ||
2701 | reg = gma_read16(hw, port, GM_RX_CTRL); | |
2702 | reg |= GM_RXCR_UCF_ENA; | |
2703 | ||
d571b694 | 2704 | if (dev->flags & IFF_PROMISC) /* promiscuous */ |
cd28ab6a | 2705 | reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); |
793b883e | 2706 | else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */ |
cd28ab6a | 2707 | memset(filter, 0xff, sizeof(filter)); |
793b883e | 2708 | else if (dev->mc_count == 0) /* no multicast */ |
cd28ab6a SH |
2709 | reg &= ~GM_RXCR_MCF_ENA; |
2710 | else { | |
2711 | int i; | |
2712 | reg |= GM_RXCR_MCF_ENA; | |
2713 | ||
2714 | for (i = 0; list && i < dev->mc_count; i++, list = list->next) { | |
2715 | u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f; | |
793b883e | 2716 | filter[bit / 8] |= 1 << (bit % 8); |
cd28ab6a SH |
2717 | } |
2718 | } | |
2719 | ||
cd28ab6a | 2720 | gma_write16(hw, port, GM_MC_ADDR_H1, |
793b883e | 2721 | (u16) filter[0] | ((u16) filter[1] << 8)); |
cd28ab6a | 2722 | gma_write16(hw, port, GM_MC_ADDR_H2, |
793b883e | 2723 | (u16) filter[2] | ((u16) filter[3] << 8)); |
cd28ab6a | 2724 | gma_write16(hw, port, GM_MC_ADDR_H3, |
793b883e | 2725 | (u16) filter[4] | ((u16) filter[5] << 8)); |
cd28ab6a | 2726 | gma_write16(hw, port, GM_MC_ADDR_H4, |
793b883e | 2727 | (u16) filter[6] | ((u16) filter[7] << 8)); |
cd28ab6a SH |
2728 | |
2729 | gma_write16(hw, port, GM_RX_CTRL, reg); | |
2730 | } | |
2731 | ||
2732 | /* Can have one global because blinking is controlled by | |
2733 | * ethtool and that is always under RTNL mutex | |
2734 | */ | |
91c86df5 | 2735 | static void sky2_led(struct sky2_hw *hw, unsigned port, int on) |
cd28ab6a | 2736 | { |
793b883e SH |
2737 | u16 pg; |
2738 | ||
793b883e SH |
2739 | switch (hw->chip_id) { |
2740 | case CHIP_ID_YUKON_XL: | |
2741 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2742 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2743 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, | |
2744 | on ? (PHY_M_LEDC_LOS_CTRL(1) | | |
2745 | PHY_M_LEDC_INIT_CTRL(7) | | |
2746 | PHY_M_LEDC_STA1_CTRL(7) | | |
2747 | PHY_M_LEDC_STA0_CTRL(7)) | |
2748 | : 0); | |
2749 | ||
2750 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2751 | break; | |
2752 | ||
2753 | default: | |
2754 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0); | |
cd28ab6a | 2755 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, |
793b883e SH |
2756 | on ? PHY_M_LED_MO_DUP(MO_LED_ON) | |
2757 | PHY_M_LED_MO_10(MO_LED_ON) | | |
2758 | PHY_M_LED_MO_100(MO_LED_ON) | | |
cd28ab6a | 2759 | PHY_M_LED_MO_1000(MO_LED_ON) | |
793b883e SH |
2760 | PHY_M_LED_MO_RX(MO_LED_ON) |
2761 | : PHY_M_LED_MO_DUP(MO_LED_OFF) | | |
2762 | PHY_M_LED_MO_10(MO_LED_OFF) | | |
2763 | PHY_M_LED_MO_100(MO_LED_OFF) | | |
cd28ab6a SH |
2764 | PHY_M_LED_MO_1000(MO_LED_OFF) | |
2765 | PHY_M_LED_MO_RX(MO_LED_OFF)); | |
2766 | ||
793b883e | 2767 | } |
cd28ab6a SH |
2768 | } |
2769 | ||
2770 | /* blink LED's for finding board */ | |
2771 | static int sky2_phys_id(struct net_device *dev, u32 data) | |
2772 | { | |
2773 | struct sky2_port *sky2 = netdev_priv(dev); | |
2774 | struct sky2_hw *hw = sky2->hw; | |
2775 | unsigned port = sky2->port; | |
793b883e | 2776 | u16 ledctrl, ledover = 0; |
cd28ab6a | 2777 | long ms; |
91c86df5 | 2778 | int interrupted; |
cd28ab6a SH |
2779 | int onoff = 1; |
2780 | ||
793b883e | 2781 | if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)) |
cd28ab6a SH |
2782 | ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT); |
2783 | else | |
2784 | ms = data * 1000; | |
2785 | ||
2786 | /* save initial values */ | |
e07b1aa8 | 2787 | spin_lock_bh(&sky2->phy_lock); |
793b883e SH |
2788 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2789 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2790 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2791 | ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | |
2792 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2793 | } else { | |
2794 | ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL); | |
2795 | ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER); | |
2796 | } | |
cd28ab6a | 2797 | |
91c86df5 SH |
2798 | interrupted = 0; |
2799 | while (!interrupted && ms > 0) { | |
cd28ab6a SH |
2800 | sky2_led(hw, port, onoff); |
2801 | onoff = !onoff; | |
2802 | ||
e07b1aa8 | 2803 | spin_unlock_bh(&sky2->phy_lock); |
91c86df5 | 2804 | interrupted = msleep_interruptible(250); |
e07b1aa8 | 2805 | spin_lock_bh(&sky2->phy_lock); |
91c86df5 | 2806 | |
cd28ab6a SH |
2807 | ms -= 250; |
2808 | } | |
2809 | ||
2810 | /* resume regularly scheduled programming */ | |
793b883e SH |
2811 | if (hw->chip_id == CHIP_ID_YUKON_XL) { |
2812 | u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); | |
2813 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3); | |
2814 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl); | |
2815 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | |
2816 | } else { | |
2817 | gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl); | |
2818 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | |
2819 | } | |
e07b1aa8 | 2820 | spin_unlock_bh(&sky2->phy_lock); |
cd28ab6a SH |
2821 | |
2822 | return 0; | |
2823 | } | |
2824 | ||
2825 | static void sky2_get_pauseparam(struct net_device *dev, | |
2826 | struct ethtool_pauseparam *ecmd) | |
2827 | { | |
2828 | struct sky2_port *sky2 = netdev_priv(dev); | |
2829 | ||
2830 | ecmd->tx_pause = sky2->tx_pause; | |
2831 | ecmd->rx_pause = sky2->rx_pause; | |
2832 | ecmd->autoneg = sky2->autoneg; | |
2833 | } | |
2834 | ||
2835 | static int sky2_set_pauseparam(struct net_device *dev, | |
2836 | struct ethtool_pauseparam *ecmd) | |
2837 | { | |
2838 | struct sky2_port *sky2 = netdev_priv(dev); | |
2839 | int err = 0; | |
2840 | ||
2841 | sky2->autoneg = ecmd->autoneg; | |
2842 | sky2->tx_pause = ecmd->tx_pause != 0; | |
2843 | sky2->rx_pause = ecmd->rx_pause != 0; | |
2844 | ||
1b537565 | 2845 | sky2_phy_reinit(sky2); |
cd28ab6a SH |
2846 | |
2847 | return err; | |
2848 | } | |
2849 | ||
fb17358f SH |
2850 | static int sky2_get_coalesce(struct net_device *dev, |
2851 | struct ethtool_coalesce *ecmd) | |
2852 | { | |
2853 | struct sky2_port *sky2 = netdev_priv(dev); | |
2854 | struct sky2_hw *hw = sky2->hw; | |
2855 | ||
2856 | if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP) | |
2857 | ecmd->tx_coalesce_usecs = 0; | |
2858 | else { | |
2859 | u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI); | |
2860 | ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2861 | } | |
2862 | ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH); | |
2863 | ||
2864 | if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP) | |
2865 | ecmd->rx_coalesce_usecs = 0; | |
2866 | else { | |
2867 | u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI); | |
2868 | ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks); | |
2869 | } | |
2870 | ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM); | |
2871 | ||
2872 | if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP) | |
2873 | ecmd->rx_coalesce_usecs_irq = 0; | |
2874 | else { | |
2875 | u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI); | |
2876 | ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks); | |
2877 | } | |
2878 | ||
2879 | ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM); | |
2880 | ||
2881 | return 0; | |
2882 | } | |
2883 | ||
2884 | /* Note: this affect both ports */ | |
2885 | static int sky2_set_coalesce(struct net_device *dev, | |
2886 | struct ethtool_coalesce *ecmd) | |
2887 | { | |
2888 | struct sky2_port *sky2 = netdev_priv(dev); | |
2889 | struct sky2_hw *hw = sky2->hw; | |
77b3d6a2 | 2890 | const u32 tmax = sky2_clk2us(hw, 0x0ffffff); |
fb17358f | 2891 | |
77b3d6a2 SH |
2892 | if (ecmd->tx_coalesce_usecs > tmax || |
2893 | ecmd->rx_coalesce_usecs > tmax || | |
2894 | ecmd->rx_coalesce_usecs_irq > tmax) | |
fb17358f SH |
2895 | return -EINVAL; |
2896 | ||
ff81fbbe | 2897 | if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1) |
fb17358f | 2898 | return -EINVAL; |
ff81fbbe | 2899 | if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING) |
fb17358f | 2900 | return -EINVAL; |
ff81fbbe | 2901 | if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING) |
fb17358f SH |
2902 | return -EINVAL; |
2903 | ||
2904 | if (ecmd->tx_coalesce_usecs == 0) | |
2905 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP); | |
2906 | else { | |
2907 | sky2_write32(hw, STAT_TX_TIMER_INI, | |
2908 | sky2_us2clk(hw, ecmd->tx_coalesce_usecs)); | |
2909 | sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START); | |
2910 | } | |
2911 | sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames); | |
2912 | ||
2913 | if (ecmd->rx_coalesce_usecs == 0) | |
2914 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP); | |
2915 | else { | |
2916 | sky2_write32(hw, STAT_LEV_TIMER_INI, | |
2917 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs)); | |
2918 | sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START); | |
2919 | } | |
2920 | sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames); | |
2921 | ||
2922 | if (ecmd->rx_coalesce_usecs_irq == 0) | |
2923 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP); | |
2924 | else { | |
d28d4870 | 2925 | sky2_write32(hw, STAT_ISR_TIMER_INI, |
fb17358f SH |
2926 | sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq)); |
2927 | sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START); | |
2928 | } | |
2929 | sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq); | |
2930 | return 0; | |
2931 | } | |
2932 | ||
793b883e SH |
2933 | static void sky2_get_ringparam(struct net_device *dev, |
2934 | struct ethtool_ringparam *ering) | |
2935 | { | |
2936 | struct sky2_port *sky2 = netdev_priv(dev); | |
2937 | ||
2938 | ering->rx_max_pending = RX_MAX_PENDING; | |
2939 | ering->rx_mini_max_pending = 0; | |
2940 | ering->rx_jumbo_max_pending = 0; | |
2941 | ering->tx_max_pending = TX_RING_SIZE - 1; | |
2942 | ||
2943 | ering->rx_pending = sky2->rx_pending; | |
2944 | ering->rx_mini_pending = 0; | |
2945 | ering->rx_jumbo_pending = 0; | |
2946 | ering->tx_pending = sky2->tx_pending; | |
2947 | } | |
2948 | ||
2949 | static int sky2_set_ringparam(struct net_device *dev, | |
2950 | struct ethtool_ringparam *ering) | |
2951 | { | |
2952 | struct sky2_port *sky2 = netdev_priv(dev); | |
2953 | int err = 0; | |
2954 | ||
2955 | if (ering->rx_pending > RX_MAX_PENDING || | |
2956 | ering->rx_pending < 8 || | |
2957 | ering->tx_pending < MAX_SKB_TX_LE || | |
2958 | ering->tx_pending > TX_RING_SIZE - 1) | |
2959 | return -EINVAL; | |
2960 | ||
2961 | if (netif_running(dev)) | |
2962 | sky2_down(dev); | |
2963 | ||
2964 | sky2->rx_pending = ering->rx_pending; | |
2965 | sky2->tx_pending = ering->tx_pending; | |
2966 | ||
1b537565 | 2967 | if (netif_running(dev)) { |
793b883e | 2968 | err = sky2_up(dev); |
1b537565 SH |
2969 | if (err) |
2970 | dev_close(dev); | |
6ed995bb SH |
2971 | else |
2972 | sky2_set_multicast(dev); | |
1b537565 | 2973 | } |
793b883e SH |
2974 | |
2975 | return err; | |
2976 | } | |
2977 | ||
793b883e SH |
2978 | static int sky2_get_regs_len(struct net_device *dev) |
2979 | { | |
6e4cbb34 | 2980 | return 0x4000; |
793b883e SH |
2981 | } |
2982 | ||
2983 | /* | |
2984 | * Returns copy of control register region | |
6e4cbb34 | 2985 | * Note: access to the RAM address register set will cause timeouts. |
793b883e SH |
2986 | */ |
2987 | static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |
2988 | void *p) | |
2989 | { | |
2990 | const struct sky2_port *sky2 = netdev_priv(dev); | |
793b883e | 2991 | const void __iomem *io = sky2->hw->regs; |
793b883e | 2992 | |
6e4cbb34 | 2993 | BUG_ON(regs->len < B3_RI_WTO_R1); |
793b883e | 2994 | regs->version = 1; |
6e4cbb34 | 2995 | memset(p, 0, regs->len); |
793b883e | 2996 | |
6e4cbb34 SH |
2997 | memcpy_fromio(p, io, B3_RAM_ADDR); |
2998 | ||
2999 | memcpy_fromio(p + B3_RI_WTO_R1, | |
3000 | io + B3_RI_WTO_R1, | |
3001 | regs->len - B3_RI_WTO_R1); | |
793b883e | 3002 | } |
cd28ab6a SH |
3003 | |
3004 | static struct ethtool_ops sky2_ethtool_ops = { | |
793b883e SH |
3005 | .get_settings = sky2_get_settings, |
3006 | .set_settings = sky2_set_settings, | |
3007 | .get_drvinfo = sky2_get_drvinfo, | |
3008 | .get_msglevel = sky2_get_msglevel, | |
3009 | .set_msglevel = sky2_set_msglevel, | |
9a7ae0a9 | 3010 | .nway_reset = sky2_nway_reset, |
793b883e SH |
3011 | .get_regs_len = sky2_get_regs_len, |
3012 | .get_regs = sky2_get_regs, | |
3013 | .get_link = ethtool_op_get_link, | |
3014 | .get_sg = ethtool_op_get_sg, | |
3015 | .set_sg = ethtool_op_set_sg, | |
3016 | .get_tx_csum = ethtool_op_get_tx_csum, | |
3017 | .set_tx_csum = ethtool_op_set_tx_csum, | |
3018 | .get_tso = ethtool_op_get_tso, | |
3019 | .set_tso = ethtool_op_set_tso, | |
3020 | .get_rx_csum = sky2_get_rx_csum, | |
3021 | .set_rx_csum = sky2_set_rx_csum, | |
3022 | .get_strings = sky2_get_strings, | |
fb17358f SH |
3023 | .get_coalesce = sky2_get_coalesce, |
3024 | .set_coalesce = sky2_set_coalesce, | |
793b883e SH |
3025 | .get_ringparam = sky2_get_ringparam, |
3026 | .set_ringparam = sky2_set_ringparam, | |
cd28ab6a SH |
3027 | .get_pauseparam = sky2_get_pauseparam, |
3028 | .set_pauseparam = sky2_set_pauseparam, | |
793b883e | 3029 | .phys_id = sky2_phys_id, |
cd28ab6a SH |
3030 | .get_stats_count = sky2_get_stats_count, |
3031 | .get_ethtool_stats = sky2_get_ethtool_stats, | |
2995bfb7 | 3032 | .get_perm_addr = ethtool_op_get_perm_addr, |
cd28ab6a SH |
3033 | }; |
3034 | ||
3035 | /* Initialize network device */ | |
3036 | static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw, | |
3037 | unsigned port, int highmem) | |
3038 | { | |
3039 | struct sky2_port *sky2; | |
3040 | struct net_device *dev = alloc_etherdev(sizeof(*sky2)); | |
3041 | ||
3042 | if (!dev) { | |
3043 | printk(KERN_ERR "sky2 etherdev alloc failed"); | |
3044 | return NULL; | |
3045 | } | |
3046 | ||
3047 | SET_MODULE_OWNER(dev); | |
3048 | SET_NETDEV_DEV(dev, &hw->pdev->dev); | |
ef743d33 | 3049 | dev->irq = hw->pdev->irq; |
cd28ab6a SH |
3050 | dev->open = sky2_up; |
3051 | dev->stop = sky2_down; | |
ef743d33 | 3052 | dev->do_ioctl = sky2_ioctl; |
cd28ab6a SH |
3053 | dev->hard_start_xmit = sky2_xmit_frame; |
3054 | dev->get_stats = sky2_get_stats; | |
3055 | dev->set_multicast_list = sky2_set_multicast; | |
3056 | dev->set_mac_address = sky2_set_mac_address; | |
3057 | dev->change_mtu = sky2_change_mtu; | |
3058 | SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops); | |
3059 | dev->tx_timeout = sky2_tx_timeout; | |
3060 | dev->watchdog_timeo = TX_WATCHDOG; | |
3061 | if (port == 0) | |
3062 | dev->poll = sky2_poll; | |
3063 | dev->weight = NAPI_WEIGHT; | |
3064 | #ifdef CONFIG_NET_POLL_CONTROLLER | |
3065 | dev->poll_controller = sky2_netpoll; | |
3066 | #endif | |
cd28ab6a SH |
3067 | |
3068 | sky2 = netdev_priv(dev); | |
3069 | sky2->netdev = dev; | |
3070 | sky2->hw = hw; | |
3071 | sky2->msg_enable = netif_msg_init(debug, default_msg); | |
3072 | ||
3073 | spin_lock_init(&sky2->tx_lock); | |
3074 | /* Auto speed and flow control */ | |
3075 | sky2->autoneg = AUTONEG_ENABLE; | |
585b5601 | 3076 | sky2->tx_pause = 1; |
cd28ab6a SH |
3077 | sky2->rx_pause = 1; |
3078 | sky2->duplex = -1; | |
3079 | sky2->speed = -1; | |
3080 | sky2->advertising = sky2_supported_modes(hw); | |
75d070c5 | 3081 | |
d89e1343 | 3082 | /* Receive checksum disabled for Yukon XL |
75d070c5 SH |
3083 | * because of observed problems with incorrect |
3084 | * values when multiple packets are received in one interrupt | |
3085 | */ | |
3086 | sky2->rx_csum = (hw->chip_id != CHIP_ID_YUKON_XL); | |
3087 | ||
e07b1aa8 | 3088 | spin_lock_init(&sky2->phy_lock); |
793b883e | 3089 | sky2->tx_pending = TX_DEF_PENDING; |
290d4de5 | 3090 | sky2->rx_pending = RX_DEF_PENDING; |
734d1868 | 3091 | sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN); |
cd28ab6a SH |
3092 | |
3093 | hw->dev[port] = dev; | |
3094 | ||
3095 | sky2->port = port; | |
3096 | ||
5a5b1ea0 SH |
3097 | dev->features |= NETIF_F_LLTX; |
3098 | if (hw->chip_id != CHIP_ID_YUKON_EC_U) | |
3099 | dev->features |= NETIF_F_TSO; | |
cd28ab6a SH |
3100 | if (highmem) |
3101 | dev->features |= NETIF_F_HIGHDMA; | |
793b883e | 3102 | dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG; |
cd28ab6a | 3103 | |
d1f13708 SH |
3104 | #ifdef SKY2_VLAN_TAG_USED |
3105 | dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; | |
3106 | dev->vlan_rx_register = sky2_vlan_rx_register; | |
3107 | dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid; | |
3108 | #endif | |
3109 | ||
cd28ab6a | 3110 | /* read the mac address */ |
793b883e | 3111 | memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); |
2995bfb7 | 3112 | memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len); |
cd28ab6a SH |
3113 | |
3114 | /* device is off until link detection */ | |
3115 | netif_carrier_off(dev); | |
3116 | netif_stop_queue(dev); | |
3117 | ||
3118 | return dev; | |
3119 | } | |
3120 | ||
28bd181a | 3121 | static void __devinit sky2_show_addr(struct net_device *dev) |
cd28ab6a SH |
3122 | { |
3123 | const struct sky2_port *sky2 = netdev_priv(dev); | |
3124 | ||
3125 | if (netif_msg_probe(sky2)) | |
3126 | printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n", | |
3127 | dev->name, | |
3128 | dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2], | |
3129 | dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]); | |
3130 | } | |
3131 | ||
fb2690a9 SH |
3132 | /* Handle software interrupt used during MSI test */ |
3133 | static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id, | |
3134 | struct pt_regs *regs) | |
3135 | { | |
3136 | struct sky2_hw *hw = dev_id; | |
3137 | u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2); | |
3138 | ||
3139 | if (status == 0) | |
3140 | return IRQ_NONE; | |
3141 | ||
3142 | if (status & Y2_IS_IRQ_SW) { | |
3143 | hw->msi_detected = 1; | |
3144 | wake_up(&hw->msi_wait); | |
3145 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
3146 | } | |
3147 | sky2_write32(hw, B0_Y2_SP_ICR, 2); | |
3148 | ||
3149 | return IRQ_HANDLED; | |
3150 | } | |
3151 | ||
3152 | /* Test interrupt path by forcing a a software IRQ */ | |
3153 | static int __devinit sky2_test_msi(struct sky2_hw *hw) | |
3154 | { | |
3155 | struct pci_dev *pdev = hw->pdev; | |
3156 | int err; | |
3157 | ||
3158 | sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); | |
3159 | ||
3160 | err = request_irq(pdev->irq, sky2_test_intr, SA_SHIRQ, DRV_NAME, hw); | |
3161 | if (err) { | |
3162 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3163 | pci_name(pdev), pdev->irq); | |
3164 | return err; | |
3165 | } | |
3166 | ||
3167 | init_waitqueue_head (&hw->msi_wait); | |
3168 | ||
3169 | sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); | |
3170 | wmb(); | |
3171 | ||
3172 | wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10); | |
3173 | ||
3174 | if (!hw->msi_detected) { | |
3175 | /* MSI test failed, go back to INTx mode */ | |
3176 | printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, " | |
3177 | "switching to INTx mode. Please report this failure to " | |
3178 | "the PCI maintainer and include system chipset information.\n", | |
3179 | pci_name(pdev)); | |
3180 | ||
3181 | err = -EOPNOTSUPP; | |
3182 | sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ); | |
3183 | } | |
3184 | ||
3185 | sky2_write32(hw, B0_IMSK, 0); | |
3186 | ||
3187 | free_irq(pdev->irq, hw); | |
3188 | ||
3189 | return err; | |
3190 | } | |
3191 | ||
cd28ab6a SH |
3192 | static int __devinit sky2_probe(struct pci_dev *pdev, |
3193 | const struct pci_device_id *ent) | |
3194 | { | |
793b883e | 3195 | struct net_device *dev, *dev1 = NULL; |
cd28ab6a | 3196 | struct sky2_hw *hw; |
5afa0a9c | 3197 | int err, pm_cap, using_dac = 0; |
cd28ab6a | 3198 | |
793b883e SH |
3199 | err = pci_enable_device(pdev); |
3200 | if (err) { | |
cd28ab6a SH |
3201 | printk(KERN_ERR PFX "%s cannot enable PCI device\n", |
3202 | pci_name(pdev)); | |
3203 | goto err_out; | |
3204 | } | |
3205 | ||
793b883e SH |
3206 | err = pci_request_regions(pdev, DRV_NAME); |
3207 | if (err) { | |
cd28ab6a SH |
3208 | printk(KERN_ERR PFX "%s cannot obtain PCI resources\n", |
3209 | pci_name(pdev)); | |
793b883e | 3210 | goto err_out; |
cd28ab6a SH |
3211 | } |
3212 | ||
3213 | pci_set_master(pdev); | |
3214 | ||
5afa0a9c SH |
3215 | /* Find power-management capability. */ |
3216 | pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
3217 | if (pm_cap == 0) { | |
3218 | printk(KERN_ERR PFX "Cannot find PowerManagement capability, " | |
3219 | "aborting.\n"); | |
3220 | err = -EIO; | |
3221 | goto err_out_free_regions; | |
3222 | } | |
3223 | ||
d1f3d4dd SH |
3224 | if (sizeof(dma_addr_t) > sizeof(u32) && |
3225 | !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) { | |
3226 | using_dac = 1; | |
3227 | err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
3228 | if (err < 0) { | |
3229 | printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA " | |
3230 | "for consistent allocations\n", pci_name(pdev)); | |
3231 | goto err_out_free_regions; | |
3232 | } | |
cd28ab6a | 3233 | |
d1f3d4dd | 3234 | } else { |
cd28ab6a SH |
3235 | err = pci_set_dma_mask(pdev, DMA_32BIT_MASK); |
3236 | if (err) { | |
3237 | printk(KERN_ERR PFX "%s no usable DMA configuration\n", | |
3238 | pci_name(pdev)); | |
3239 | goto err_out_free_regions; | |
3240 | } | |
3241 | } | |
d1f3d4dd | 3242 | |
cd28ab6a | 3243 | err = -ENOMEM; |
6aad85d6 | 3244 | hw = kzalloc(sizeof(*hw), GFP_KERNEL); |
cd28ab6a SH |
3245 | if (!hw) { |
3246 | printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n", | |
3247 | pci_name(pdev)); | |
3248 | goto err_out_free_regions; | |
3249 | } | |
3250 | ||
cd28ab6a | 3251 | hw->pdev = pdev; |
cd28ab6a SH |
3252 | |
3253 | hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000); | |
3254 | if (!hw->regs) { | |
3255 | printk(KERN_ERR PFX "%s: cannot map device registers\n", | |
3256 | pci_name(pdev)); | |
3257 | goto err_out_free_hw; | |
3258 | } | |
5afa0a9c | 3259 | hw->pm_cap = pm_cap; |
cd28ab6a | 3260 | |
56a645cc SH |
3261 | #ifdef __BIG_ENDIAN |
3262 | /* byte swap descriptors in hardware */ | |
3263 | { | |
3264 | u32 reg; | |
3265 | ||
3266 | reg = sky2_pci_read32(hw, PCI_DEV_REG2); | |
3267 | reg |= PCI_REV_DESC; | |
3268 | sky2_pci_write32(hw, PCI_DEV_REG2, reg); | |
3269 | } | |
3270 | #endif | |
3271 | ||
08c06d8a SH |
3272 | /* ring for status responses */ |
3273 | hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES, | |
3274 | &hw->st_dma); | |
3275 | if (!hw->st_le) | |
3276 | goto err_out_iounmap; | |
3277 | ||
cd28ab6a SH |
3278 | err = sky2_reset(hw); |
3279 | if (err) | |
793b883e | 3280 | goto err_out_iounmap; |
cd28ab6a | 3281 | |
5f4f9dc1 SH |
3282 | printk(KERN_INFO PFX "v%s addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n", |
3283 | DRV_VERSION, pci_resource_start(pdev, 0), pdev->irq, | |
92f965e8 | 3284 | yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL], |
793b883e | 3285 | hw->chip_id, hw->chip_rev); |
cd28ab6a | 3286 | |
793b883e SH |
3287 | dev = sky2_init_netdev(hw, 0, using_dac); |
3288 | if (!dev) | |
cd28ab6a SH |
3289 | goto err_out_free_pci; |
3290 | ||
793b883e SH |
3291 | err = register_netdev(dev); |
3292 | if (err) { | |
cd28ab6a SH |
3293 | printk(KERN_ERR PFX "%s: cannot register net device\n", |
3294 | pci_name(pdev)); | |
3295 | goto err_out_free_netdev; | |
3296 | } | |
3297 | ||
3298 | sky2_show_addr(dev); | |
3299 | ||
3300 | if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) { | |
3301 | if (register_netdev(dev1) == 0) | |
3302 | sky2_show_addr(dev1); | |
3303 | else { | |
3304 | /* Failure to register second port need not be fatal */ | |
793b883e SH |
3305 | printk(KERN_WARNING PFX |
3306 | "register of second port failed\n"); | |
cd28ab6a SH |
3307 | hw->dev[1] = NULL; |
3308 | free_netdev(dev1); | |
3309 | } | |
3310 | } | |
3311 | ||
fb2690a9 SH |
3312 | if (!disable_msi && pci_enable_msi(pdev) == 0) { |
3313 | err = sky2_test_msi(hw); | |
3314 | if (err == -EOPNOTSUPP) | |
3315 | pci_disable_msi(pdev); | |
3316 | else if (err) | |
3317 | goto err_out_unregister; | |
3318 | } | |
3319 | ||
3320 | err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw); | |
793b883e SH |
3321 | if (err) { |
3322 | printk(KERN_ERR PFX "%s: cannot assign irq %d\n", | |
3323 | pci_name(pdev), pdev->irq); | |
3324 | goto err_out_unregister; | |
3325 | } | |
3326 | ||
e07b1aa8 | 3327 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); |
793b883e | 3328 | |
01bd7564 SH |
3329 | setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw); |
3330 | if (idle_timeout > 0) | |
3331 | mod_timer(&hw->idle_timer, | |
3332 | jiffies + msecs_to_jiffies(idle_timeout)); | |
d27ed387 | 3333 | |
793b883e SH |
3334 | pci_set_drvdata(pdev, hw); |
3335 | ||
cd28ab6a SH |
3336 | return 0; |
3337 | ||
793b883e | 3338 | err_out_unregister: |
fb2690a9 | 3339 | pci_disable_msi(pdev); |
793b883e SH |
3340 | if (dev1) { |
3341 | unregister_netdev(dev1); | |
3342 | free_netdev(dev1); | |
3343 | } | |
3344 | unregister_netdev(dev); | |
cd28ab6a SH |
3345 | err_out_free_netdev: |
3346 | free_netdev(dev); | |
cd28ab6a | 3347 | err_out_free_pci: |
793b883e | 3348 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
cd28ab6a SH |
3349 | pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
3350 | err_out_iounmap: | |
3351 | iounmap(hw->regs); | |
3352 | err_out_free_hw: | |
3353 | kfree(hw); | |
3354 | err_out_free_regions: | |
3355 | pci_release_regions(pdev); | |
cd28ab6a | 3356 | pci_disable_device(pdev); |
cd28ab6a SH |
3357 | err_out: |
3358 | return err; | |
3359 | } | |
3360 | ||
3361 | static void __devexit sky2_remove(struct pci_dev *pdev) | |
3362 | { | |
793b883e | 3363 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
cd28ab6a SH |
3364 | struct net_device *dev0, *dev1; |
3365 | ||
793b883e | 3366 | if (!hw) |
cd28ab6a SH |
3367 | return; |
3368 | ||
d27ed387 SH |
3369 | del_timer_sync(&hw->idle_timer); |
3370 | ||
3371 | sky2_write32(hw, B0_IMSK, 0); | |
72cb8529 SH |
3372 | synchronize_irq(hw->pdev->irq); |
3373 | ||
cd28ab6a | 3374 | dev0 = hw->dev[0]; |
793b883e SH |
3375 | dev1 = hw->dev[1]; |
3376 | if (dev1) | |
3377 | unregister_netdev(dev1); | |
cd28ab6a SH |
3378 | unregister_netdev(dev0); |
3379 | ||
5afa0a9c | 3380 | sky2_set_power_state(hw, PCI_D3hot); |
cd28ab6a | 3381 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
793b883e | 3382 | sky2_write8(hw, B0_CTST, CS_RST_SET); |
5afa0a9c | 3383 | sky2_read8(hw, B0_CTST); |
cd28ab6a SH |
3384 | |
3385 | free_irq(pdev->irq, hw); | |
fb2690a9 | 3386 | pci_disable_msi(pdev); |
793b883e | 3387 | pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma); |
cd28ab6a SH |
3388 | pci_release_regions(pdev); |
3389 | pci_disable_device(pdev); | |
793b883e | 3390 | |
cd28ab6a SH |
3391 | if (dev1) |
3392 | free_netdev(dev1); | |
3393 | free_netdev(dev0); | |
3394 | iounmap(hw->regs); | |
3395 | kfree(hw); | |
5afa0a9c | 3396 | |
cd28ab6a SH |
3397 | pci_set_drvdata(pdev, NULL); |
3398 | } | |
3399 | ||
3400 | #ifdef CONFIG_PM | |
3401 | static int sky2_suspend(struct pci_dev *pdev, pm_message_t state) | |
3402 | { | |
793b883e | 3403 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
5afa0a9c | 3404 | int i; |
cd28ab6a SH |
3405 | |
3406 | for (i = 0; i < 2; i++) { | |
3407 | struct net_device *dev = hw->dev[i]; | |
3408 | ||
3409 | if (dev) { | |
5afa0a9c SH |
3410 | if (!netif_running(dev)) |
3411 | continue; | |
3412 | ||
3413 | sky2_down(dev); | |
cd28ab6a | 3414 | netif_device_detach(dev); |
cd28ab6a SH |
3415 | } |
3416 | } | |
3417 | ||
5afa0a9c | 3418 | return sky2_set_power_state(hw, pci_choose_state(pdev, state)); |
cd28ab6a SH |
3419 | } |
3420 | ||
3421 | static int sky2_resume(struct pci_dev *pdev) | |
3422 | { | |
793b883e | 3423 | struct sky2_hw *hw = pci_get_drvdata(pdev); |
08c06d8a | 3424 | int i, err; |
cd28ab6a | 3425 | |
cd28ab6a SH |
3426 | pci_restore_state(pdev); |
3427 | pci_enable_wake(pdev, PCI_D0, 0); | |
08c06d8a SH |
3428 | err = sky2_set_power_state(hw, PCI_D0); |
3429 | if (err) | |
3430 | goto out; | |
cd28ab6a | 3431 | |
08c06d8a SH |
3432 | err = sky2_reset(hw); |
3433 | if (err) | |
3434 | goto out; | |
cd28ab6a SH |
3435 | |
3436 | for (i = 0; i < 2; i++) { | |
3437 | struct net_device *dev = hw->dev[i]; | |
08c06d8a SH |
3438 | if (dev && netif_running(dev)) { |
3439 | netif_device_attach(dev); | |
3440 | err = sky2_up(dev); | |
3441 | if (err) { | |
3442 | printk(KERN_ERR PFX "%s: could not up: %d\n", | |
3443 | dev->name, err); | |
3444 | dev_close(dev); | |
3445 | break; | |
5afa0a9c | 3446 | } |
cd28ab6a SH |
3447 | } |
3448 | } | |
08c06d8a SH |
3449 | out: |
3450 | return err; | |
cd28ab6a SH |
3451 | } |
3452 | #endif | |
3453 | ||
3454 | static struct pci_driver sky2_driver = { | |
793b883e SH |
3455 | .name = DRV_NAME, |
3456 | .id_table = sky2_id_table, | |
3457 | .probe = sky2_probe, | |
3458 | .remove = __devexit_p(sky2_remove), | |
cd28ab6a | 3459 | #ifdef CONFIG_PM |
793b883e SH |
3460 | .suspend = sky2_suspend, |
3461 | .resume = sky2_resume, | |
cd28ab6a SH |
3462 | #endif |
3463 | }; | |
3464 | ||
3465 | static int __init sky2_init_module(void) | |
3466 | { | |
50241c4c | 3467 | return pci_register_driver(&sky2_driver); |
cd28ab6a SH |
3468 | } |
3469 | ||
3470 | static void __exit sky2_cleanup_module(void) | |
3471 | { | |
3472 | pci_unregister_driver(&sky2_driver); | |
3473 | } | |
3474 | ||
3475 | module_init(sky2_init_module); | |
3476 | module_exit(sky2_cleanup_module); | |
3477 | ||
3478 | MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver"); | |
3479 | MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>"); | |
3480 | MODULE_LICENSE("GPL"); | |
5f4f9dc1 | 3481 | MODULE_VERSION(DRV_VERSION); |